| blob | 2a2c23c0ff52a56ee41de0d512ad5c7512cdb8ec |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
58 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
60 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
61 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
62 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
65 /* Vector mapping INSN_UIDs to luids.
66 The luids are like uids but increase monotonically always.
67 We use them to see whether a jump comes from outside a given loop. */
71 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
72 number the insn is contained in. */
76 /* 1 + largest uid of any insn. */
80 /* 1 + luid of last insn. */
84 /* Number of loops detected in current function. Used as index to the
85 next few tables. */
89 /* Bound on pseudo register number before loop optimization.
90 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
93 /* The value to pass to the next call of reg_scan_update. */
96 #define obstack_chunk_alloc xmalloc
97 #define obstack_chunk_free free
98 \f
99 /* During the analysis of a loop, a chain of `struct movable's
100 is made to record all the movable insns found.
101 Then the entire chain can be scanned to decide which to move. */
103 struct movable
104 {
109 of any registers used within the LIBCALL. */
111 that must be moved with this one. */
114 may be adjusted when matching movables
115 that load the same value are found. */
117 including other movables that force this
118 or match this one. */
122 /* If PARTIAL is 1, GLOBAL means something different:
123 that the reg is live outside the range from where it is set
124 to the following label. */
128 In particular, moving it does not make it
129 invariant. */
131 load SRC, rather than copying INSN. */
133 first insn of a consecutive sets group. */
136 that we should avoid changing when clearing
137 the rest of the reg. */
141 };
146 /* Forward declarations. */
160 #if 0
162 #endif
191 rtx *));
265 {
266 rtx r1;
267 rtx r2;
271 {
272 rtx match;
273 rtx replacement;
274 rtx insn;
277 /* Nonzero iff INSN is between START and END, inclusive. */
278 #define INSN_IN_RANGE_P(INSN, START, END) \
279 (INSN_UID (INSN) < max_uid_for_loop \
280 && INSN_LUID (INSN) >= INSN_LUID (START) \
281 && INSN_LUID (INSN) <= INSN_LUID (END))
283 /* Indirect_jump_in_function is computed once per function. */
291 rtx));
292 \f
293 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
294 copy the value of the strength reduced giv to its original register. */
297 /* Cost of using a register, to normalize the benefits of a giv. */
300 void
302 {
308 }
309 \f
310 /* Compute the mapping from uids to luids.
311 LUIDs are numbers assigned to insns, like uids,
312 except that luids increase monotonically through the code.
313 Start at insn START and stop just before END. Assign LUIDs
314 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
315 static int
319 {
321 rtx insn;
324 {
327 /* Don't assign luids to line-number NOTEs, so that the distance in
328 luids between two insns is not affected by -g. */
332 else
333 /* Give a line number note the same luid as preceding insn. */
335 }
337 }
338 \f
339 /* Entry point of this file. Perform loop optimization
340 on the current function. F is the first insn of the function
341 and DUMPFILE is a stream for output of a trace of actions taken
342 (or 0 if none should be output). */
344 void
346 /* f is the first instruction of a chain of insns for one function */
347 rtx f;
350 {
366 /* Count the number of loops. */
370 {
373 max_loop_num++;
374 }
376 /* Don't waste time if no loops. */
382 /* Get size to use for tables indexed by uids.
383 Leave some space for labels allocated by find_and_verify_loops. */
390 /* Allocate storage for array of loops. */
394 /* Find and process each loop.
395 First, find them, and record them in order of their beginnings. */
398 /* Allocate and initialize auxiliary loop information. */
403 /* Now find all register lifetimes. This must be done after
404 find_and_verify_loops, because it might reorder the insns in the
405 function. */
408 /* This must occur after reg_scan so that registers created by gcse
409 will have entries in the register tables.
411 We could have added a call to reg_scan after gcse_main in toplev.c,
412 but moving this call to init_alias_analysis is more efficient. */
415 /* See if we went too far. Note that get_max_uid already returns
416 one more that the maximum uid of all insn. */
419 /* Now reset it to the actual size we need. See above. */
422 /* find_and_verify_loops has already called compute_luids, but it
423 might have rearranged code afterwards, so we need to recompute
424 the luids now. */
427 /* Don't leave gaps in uid_luid for insns that have been
428 deleted. It is possible that the first or last insn
429 using some register has been deleted by cross-jumping.
430 Make sure that uid_luid for that former insn's uid
431 points to the general area where that insn used to be. */
433 {
437 }
442 /* Determine if the function has indirect jump. On some systems
443 this prevents low overhead loop instructions from being used. */
446 /* Now scan the loops, last ones first, since this means inner ones are done
447 before outer ones. */
449 {
454 }
456 /* If there were lexical blocks inside the loop, they have been
457 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
458 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
459 the BLOCKs as well. */
465 /* Clean up. */
470 }
471 \f
472 /* Returns the next insn, in execution order, after INSN. START and
473 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
474 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
475 insn-stream; it is used with loops that are entered near the
476 bottom. */
478 static rtx
481 rtx insn;
482 {
486 {
488 /* Go to the top of the loop, and continue there. */
490 else
491 /* We're done. */
493 }
496 /* We're done. */
500 }
502 /* Optimize one loop described by LOOP. */
504 /* ??? Could also move memory writes out of loops if the destination address
505 is invariant, the source is invariant, the memory write is not volatile,
506 and if we can prove that no read inside the loop can read this address
507 before the write occurs. If there is a read of this address after the
508 write, then we can also mark the memory read as invariant. */
510 static void
514 {
520 rtx p;
521 /* 1 if we are scanning insns that could be executed zero times. */
523 /* 1 if we are scanning insns that might never be executed
524 due to a subroutine call which might exit before they are reached. */
526 /* Jump insn that enters the loop, or 0 if control drops in. */
528 /* Number of insns in the loop. */
532 /* The SET from an insn, if it is the only SET in the insn. */
534 /* Chain describing insns movable in current loop. */
536 /* Ratio of extra register life span we can justify
537 for saving an instruction. More if loop doesn't call subroutines
538 since in that case saving an insn makes more difference
539 and more registers are available. */
541 /* Nonzero if we are scanning instructions in a sub-loop. */
550 /* Determine whether this loop starts with a jump down to a test at
551 the end. This will occur for a small number of loops with a test
552 that is too complex to duplicate in front of the loop.
554 We search for the first insn or label in the loop, skipping NOTEs.
555 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
556 (because we might have a loop executed only once that contains a
557 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
558 (in case we have a degenerate loop).
560 Note that if we mistakenly think that a loop is entered at the top
561 when, in fact, it is entered at the exit test, the only effect will be
562 slightly poorer optimization. Making the opposite error can generate
563 incorrect code. Since very few loops now start with a jump to the
564 exit test, the code here to detect that case is very conservative. */
567 p != loop_end
573 ;
577 /* If loop end is the end of the current function, then emit a
578 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
579 note insn. This is the position we use when sinking insns out of
580 the loop. */
583 else
586 /* Set up variables describing this loop. */
590 /* If loop has a jump before the first label,
591 the true entry is the target of that jump.
592 Start scan from there.
593 But record in LOOP->TOP the place where the end-test jumps
594 back to so we can scan that after the end of the loop. */
596 {
599 /* Loop entry must be unconditional jump (and not a RETURN) */
602 /* Check to see whether the jump actually
603 jumps out of the loop (meaning it's no loop).
604 This case can happen for things like
605 do {..} while (0). If this label was generated previously
606 by loop, we can't tell anything about it and have to reject
607 the loop. */
609 {
612 }
613 }
615 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
616 as required by loop_reg_used_before_p. So skip such loops. (This
617 test may never be true, but it's best to play it safe.)
619 Also, skip loops where we do not start scanning at a label. This
620 test also rejects loops starting with a JUMP_INSN that failed the
621 test above. */
625 {
630 }
632 /* Allocate extra space for REGs that might be created by load_mems.
633 We allocate a little extra slop as well, in the hopes that we
634 won't have to reallocate the regs array. */
638 {
644 }
646 /* Scan through the loop finding insns that are safe to move.
647 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
648 this reg will be considered invariant for subsequent insns.
649 We consider whether subsequent insns use the reg
650 in deciding whether it is worth actually moving.
652 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
653 and therefore it is possible that the insns we are scanning
654 would never be executed. At such times, we must make sure
655 that it is safe to execute the insn once instead of zero times.
656 When MAYBE_NEVER is 0, all insns will be executed at least once
657 so that is not a problem. */
662 {
667 {
674 /* Figure out what to use as a source of this insn. If a REG_EQUIV
675 note is given or if a REG_EQUAL note with a constant operand is
676 specified, use it as the source and mark that we should move
677 this insn by calling emit_move_insn rather that duplicating the
678 insn.
680 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
681 is present. */
685 else
686 {
691 {
693 /* A libcall block can use regs that don't appear in
694 the equivalent expression. To move the libcall,
695 we must move those regs too. */
697 }
698 }
700 /* Don't try to optimize a register that was made
701 by loop-optimization for an inner loop.
702 We don't know its life-span, so we can't compute the benefit. */
704 ;
706 than the one where it is set (meaning that
707 something after this point in the loop might
708 depend on its value before the set). */
710 /* And the set is not guaranteed to be executed one
711 the loop starts, or the value before the set is
712 needed before the set occurs...
714 ??? Note we have quadratic behaviour here, mitigated
715 by the fact that the previous test will often fail for
716 large loops. Rather than re-scanning the entire loop
717 each time for register usage, we should build tables
718 of the register usage and use them here instead. */
719 && (maybe_never
721 /* It is unsafe to move the set.
723 This code used to consider it OK to move a set of a variable
724 which was not created by the user and not used in an exit test.
725 That behavior is incorrect and was removed. */
726 ;
731 || (tem1
732 = consec_sets_invariant_p
735 p)))
736 /* If the insn can cause a trap (such as divide by zero),
737 can't move it unless it's guaranteed to be executed
738 once loop is entered. Even a function call might
739 prevent the trap insn from being reached
740 (since it might exit!) */
743 {
747 /* A potential lossage is where we have a case where two insns
748 can be combined as long as they are both in the loop, but
749 we move one of them outside the loop. For large loops,
750 this can lose. The most common case of this is the address
751 of a function being called.
753 Therefore, if this register is marked as being used exactly
754 once if we are in a loop with calls (a "large loop"), see if
755 we can replace the usage of this register with the source
756 of this SET. If we can, delete this insn.
758 Don't do this if P has a REG_RETVAL note or if we have
759 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
770 && (! SMALL_REGISTER_CLASSES
773 /* This test is not redundant; SET_SRC (set) might be
774 a call-clobbered register and the life of REGNO
775 might span a call. */
781 {
782 /* Replace any usage in a REG_EQUAL note. Must copy the
783 new source, so that we don't get rtx sharing between the
784 SET_SOURCE and REG_NOTES of insn p. */
794 }
812 /* Set M->cond if either loop_invariant_p
813 or consec_sets_invariant_p returned 2
814 (only conditionally invariant). */
823 /* Add M to the end of the chain MOVABLES. */
827 {
828 /* It is possible for the first instruction to have a
829 REG_EQUAL note but a non-invariant SET_SRC, so we must
830 remember the status of the first instruction in case
831 the last instruction doesn't have a REG_EQUAL note. */
834 /* Skip this insn, not checking REG_LIBCALL notes. */
836 /* Skip the consecutive insns, if there are any. */
838 /* Back up to the last insn of the consecutive group. */
841 /* We must now reset m->move_insn, m->is_equiv, and possibly
842 m->set_src to correspond to the effects of all the
843 insns. */
847 else
848 {
852 else
855 }
857 }
858 }
859 /* If this register is always set within a STRICT_LOW_PART
860 or set to zero, then its high bytes are constant.
861 So clear them outside the loop and within the loop
862 just load the low bytes.
863 We must check that the machine has an instruction to do so.
864 Also, if the value loaded into the register
865 depends on the same register, this cannot be done. */
875 {
878 {
892 /* If the insn may not be executed on some cycles,
893 we can't clear the whole reg; clear just high part.
894 Not even if the reg is used only within this loop.
895 Consider this:
896 while (1)
897 while (s != t) {
898 if (foo ()) x = *s;
899 use (x);
900 }
901 Clearing x before the inner loop could clobber a value
902 being saved from the last time around the outer loop.
903 However, if the reg is not used outside this loop
904 and all uses of the register are in the same
905 basic block as the store, there is no problem.
907 If this insn was made by loop, we don't know its
908 INSN_LUID and hence must make a conservative
909 assumption. */
912 || (labels_in_range_p
916 else
924 /* Add M to the end of the chain MOVABLES. */
926 }
927 }
928 }
929 /* Past a call insn, we get to insns which might not be executed
930 because the call might exit. This matters for insns that trap.
931 Constant and pure call insns always return, so they don't count. */
934 /* Past a label or a jump, we get to insns for which we
935 can't count on whether or how many times they will be
936 executed during each iteration. Therefore, we can
937 only move out sets of trivial variables
938 (those not used after the loop). */
939 /* Similar code appears twice in strength_reduce. */
941 /* If we enter the loop in the middle, and scan around to the
942 beginning, don't set maybe_never for that. This must be an
943 unconditional jump, otherwise the code at the top of the
944 loop might never be executed. Unconditional jumps are
945 followed a by barrier then loop end. */
951 {
952 /* At the virtual top of a converted loop, insns are again known to
953 be executed: logically, the loop begins here even though the exit
954 code has been duplicated. */
958 loop_depth++;
960 loop_depth--;
961 }
962 }
964 /* If one movable subsumes another, ignore that other. */
968 /* For each movable insn, see if the reg that it loads
969 leads when it dies right into another conditionally movable insn.
970 If so, record that the second insn "forces" the first one,
971 since the second can be moved only if the first is. */
975 /* See if there are multiple movable insns that load the same value.
976 If there are, make all but the first point at the first one
977 through the `match' field, and add the priorities of them
978 all together as the priority of the first. */
982 /* Now consider each movable insn to decide whether it is worth moving.
983 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
985 Generally this increases code size, so do not move moveables when
986 optimizing for code size. */
991 /* Now candidates that still are negative are those not moved.
992 Change regs->array[I].set_in_loop to indicate that those are not actually
993 invariant. */
998 /* Now that we've moved some things out of the loop, we might be able to
999 hoist even more memory references. */
1002 /* Recalculate regs->array if load_mems has created new registers. */
1010 ;
1017 {
1019 /* Ensure our label doesn't go away. */
1030 }
1033 /* The movable information is required for strength reduction. */
1039 }
1040 \f
1041 /* Add elements to *OUTPUT to record all the pseudo-regs
1042 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1044 void
1048 {
1056 {
1074 }
1078 {
1082 {
1091 }
1092 }
1093 }
1094 \f
1095 /* Check what regs are referred to in the libcall block ending with INSN,
1096 aside from those mentioned in the equivalent value.
1097 If there are none, return 0.
1098 If there are one or more, return an EXPR_LIST containing all of them. */
1100 rtx
1103 {
1108 /* First, find all the regs used in the libcall block
1109 that are not mentioned as inputs to the result. */
1112 {
1117 }
1120 }
1121 \f
1122 /* Return 1 if all uses of REG
1123 are between INSN and the end of the basic block. */
1125 static int
1128 {
1130 rtx p;
1135 /* Search this basic block for the already recorded last use of the reg. */
1137 {
1139 {
1145 /* Ordinary insn: if this is the last use, we win. */
1151 /* Jump insn: if this is the last use, we win. */
1154 /* Otherwise, it's the end of the basic block, so we lose. */
1159 /* It's the end of the basic block, so we lose. */
1164 }
1165 }
1167 /* The "last use" that was recorded can't be found after the first
1168 use. This can happen when the last use was deleted while
1169 processing an inner loop, this inner loop was then completely
1170 unrolled, and the outer loop is always exited after the inner loop,
1171 so that everything after the first use becomes a single basic block. */
1173 }
1174 \f
1175 /* Compute the benefit of eliminating the insns in the block whose
1176 last insn is LAST. This may be a group of insns used to compute a
1177 value directly or can contain a library call. */
1179 static int
1181 rtx last;
1182 {
1183 rtx insn;
1188 {
1191 routine. */
1195 benefit++;
1196 }
1199 }
1200 \f
1201 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1203 static rtx
1205 rtx insn;
1207 {
1209 {
1210 rtx temp;
1212 /* If first insn of libcall sequence, skip to end. */
1213 /* Do this at start of loop, since INSN is guaranteed to
1214 be an insn here. */
1219 do
1222 }
1225 }
1227 /* Ignore any movable whose insn falls within a libcall
1228 which is part of another movable.
1229 We make use of the fact that the movable for the libcall value
1230 was made later and so appears later on the chain. */
1232 static void
1235 {
1239 {
1240 /* Is this a movable for the value of a libcall? */
1243 {
1244 rtx insn;
1245 /* Check for earlier movables inside that range,
1246 and mark them invalid. We cannot use LUIDs here because
1247 insns created by loop.c for prior loops don't have LUIDs.
1248 Rather than reject all such insns from movables, we just
1249 explicitly check each insn in the libcall (since invariant
1250 libcalls aren't that common). */
1255 }
1256 }
1257 }
1259 /* For each movable insn, see if the reg that it loads
1260 leads when it dies right into another conditionally movable insn.
1261 If so, record that the second insn "forces" the first one,
1262 since the second can be moved only if the first is. */
1264 static void
1267 {
1270 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1272 {
1275 /* ??? Could this be a bug? What if CSE caused the
1276 register of M1 to be used after this insn?
1277 Since CSE does not update regno_last_uid,
1278 this insn M->insn might not be where it dies.
1279 But very likely this doesn't matter; what matters is
1280 that M's reg is computed from M1's reg. */
1285 /* If m->consec, m->set_src isn't valid. */
1289 /* Increase the priority of the moving the first insn
1290 since it permits the second to be moved as well. */
1292 {
1296 }
1297 }
1298 }
1299 \f
1300 /* Find invariant expressions that are equal and can be combined into
1301 one register. */
1303 static void
1307 {
1312 /* Regs that are set more than once are not allowed to match
1313 or be matched. I'm no longer sure why not. */
1314 /* Perhaps testing m->consec_sets would be more appropriate here? */
1319 {
1326 /* We want later insns to match the first one. Don't make the first
1327 one match any later ones. So start this loop at m->next. */
1331 /* A reg used outside the loop mustn't be eliminated. */
1333 /* A reg used for zero-extending mustn't be eliminated. */
1336 ||
1337 (
1338 /* Can combine regs with different modes loaded from the
1339 same constant only if the modes are the same or
1340 if both are integer modes with M wider or the same
1341 width as M1. The check for integer is redundant, but
1342 safe, since the only case of differing destination
1343 modes with equal sources is when both sources are
1344 VOIDmode, i.e., CONST_INT. */
1350 /* See if the source of M1 says it matches M. */
1357 {
1363 }
1364 }
1366 /* Now combine the regs used for zero-extension.
1367 This can be done for those not marked `global'
1368 provided their lives don't overlap. */
1372 {
1375 /* Combine all the registers for extension from mode MODE.
1376 Don't combine any that are used outside this loop. */
1380 {
1386 {
1387 /* First one: don't check for overlap, just record it. */
1390 }
1392 /* Make sure they extend to the same mode.
1393 (Almost always true.) */
1397 /* We already have one: check for overlap with those
1398 already combined together. */
1405 /* No overlap: we can combine this with the others. */
1411 overlap:
1412 ;
1413 }
1414 }
1416 /* Clean up. */
1418 }
1419 \f
1420 /* Return 1 if regs X and Y will become the same if moved. */
1422 static int
1426 {
1443 }
1445 /* Return 1 if X and Y are identical-looking rtx's.
1446 This is the Lisp function EQUAL for rtx arguments.
1448 If two registers are matching movables or a movable register and an
1449 equivalent constant, consider them equal. */
1451 static int
1456 {
1470 /* If we have a register and a constant, they may sometimes be
1471 equal. */
1474 {
1479 }
1482 {
1487 }
1489 /* Otherwise, rtx's of different codes cannot be equal. */
1493 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1494 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1499 /* These three types of rtx's can be compared nonrecursively. */
1508 /* Compare the elements. If any pair of corresponding elements
1509 fail to match, return 0 for the whole things. */
1513 {
1515 {
1527 /* Two vectors must have the same length. */
1531 /* And the corresponding elements must match. */
1550 /* These are just backpointers, so they don't matter. */
1556 /* It is believed that rtx's at this level will never
1557 contain anything but integers and other rtx's,
1558 except for within LABEL_REFs and SYMBOL_REFs. */
1561 }
1562 }
1564 }
1565 \f
1566 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1567 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1568 references is incremented once for each added note. */
1570 static void
1572 rtx x;
1573 rtx insns;
1574 {
1578 rtx insn;
1581 {
1582 /* This code used to ignore labels that referred to dispatch tables to
1583 avoid flow generating (slighly) worse code.
1585 We no longer ignore such label references (see LABEL_REF handling in
1586 mark_jump_label for additional information). */
1589 {
1594 }
1595 }
1599 {
1605 }
1606 }
1607 \f
1608 /* Scan MOVABLES, and move the insns that deserve to be moved.
1609 If two matching movables are combined, replace one reg with the
1610 other throughout. */
1612 static void
1618 {
1626 /* Map of pseudo-register replacements to handle combining
1627 when we move several insns that load the same value
1628 into different pseudo-registers. */
1635 {
1636 /* Describe this movable insn. */
1639 {
1660 }
1662 /* Count movables. Value used in heuristics in strength_reduce. */
1665 /* Ignore the insn if it's already done (it matched something else).
1666 Otherwise, see if it is now safe to move. */
1678 {
1683 /* We have an insn that is safe to move.
1684 Compute its desirability. */
1695 /* An insn MUST be moved if we already moved something else
1696 which is safe only if this one is moved too: that is,
1697 if already_moved[REGNO] is nonzero. */
1699 /* An insn is desirable to move if the new lifetime of the
1700 register is no more than THRESHOLD times the old lifetime.
1701 If it's not desirable, it means the loop is so big
1702 that moving won't speed things up much,
1703 and it is liable to make register usage worse. */
1705 /* It is also desirable to move if it can be moved at no
1706 extra cost because something else was already moved. */
1709 || flag_move_all_movables
1714 {
1719 /* Now move the insns that set the reg. */
1722 {
1725 /* Find the end of this chain of matching regs.
1726 Thus, we load each reg in the chain from that one reg.
1727 And that reg is loaded with 0 directly,
1728 since it has ->match == 0. */
1734 /* Mark the moved, invariant reg as being allowed to
1735 share a hard reg with the other matching invariant. */
1739 regs_may_share
1742 regs_may_share));
1750 }
1751 /* If we are to re-generate the item being moved with a
1752 new move insn, first delete what we have and then emit
1753 the move insn before the loop. */
1755 {
1759 {
1760 /* If this is the first insn of a library call sequence,
1761 skip to the end. */
1766 /* If this is the last insn of a libcall sequence, then
1767 delete every insn in the sequence except the last.
1768 The last insn is handled in the normal manner. */
1771 {
1775 }
1780 /* simplify_giv_expr expects that it can walk the insns
1781 at m->insn forwards and see this old sequence we are
1782 tossing here. delete_insn does preserve the next
1783 pointers, but when we skip over a NOTE we must fix
1784 it up. Otherwise that code walks into the non-deleted
1785 insn stream. */
1788 }
1807 /* The more regs we move, the less we like moving them. */
1809 }
1810 else
1811 {
1813 {
1816 /* If first insn of libcall sequence, skip to end. */
1817 /* Do this at start of loop, since p is guaranteed to
1818 be an insn here. */
1823 /* If last insn of libcall sequence, move all
1824 insns except the last before the loop. The last
1825 insn is handled in the normal manner. */
1828 {
1836 {
1837 rtx body;
1838 rtx n;
1839 rtx next;
1846 /* Find the next insn after TEMP,
1847 not counting USE or NOTE insns. */
1855 /* If that is the call, this may be the insn
1856 that loads the function address.
1858 Extract the function address from the insn
1859 that loads it into a register.
1860 If this insn was cse'd, we get incorrect code.
1862 So emit a new move insn that copies the
1863 function address into the register that the
1864 call insn will use. flow.c will delete any
1865 redundant stores that we have created. */
1870 NULL_RTX)))
1871 {
1877 }
1878 /* We have the call insn.
1879 If it uses the register we suspect it might,
1880 load it with the correct address directly. */
1885 fn_address),
1886 fn_address_insn);
1889 {
1891 /* Because the USAGE information potentially
1892 contains objects other than hard registers
1893 we need to copy it. */
1897 }
1898 else
1906 }
1909 }
1911 {
1912 /* P sets REG to zero; but we should clear only
1913 the bits that are not covered by the mode
1914 m->savemode. */
1916 rtx sequence;
1917 rtx tem;
1920 tem = expand_binop
1933 }
1935 {
1937 /* Because the USAGE information potentially
1938 contains objects other than hard registers
1939 we need to copy it. */
1943 }
1945 {
1946 rtx seq;
1947 /* The SET_SRC might not be invariant, so we must
1948 use the REG_EQUAL note. */
1963 }
1964 else
1968 {
1971 /* If there is a REG_EQUAL note present whose value
1972 is not loop invariant, then delete it, since it
1973 may cause problems with later optimization passes.
1974 It is possible for cse to create such notes
1975 like this as a result of record_jump_cond. */
1980 }
1989 /* If library call, now fix the REG_NOTES that contain
1990 insn pointers, namely REG_LIBCALL on FIRST
1991 and REG_RETVAL on I1. */
1993 {
1997 }
2003 /* simplify_giv_expr expects that it can walk the insns
2004 at m->insn forwards and see this old sequence we are
2005 tossing here. delete_insn does preserve the next
2006 pointers, but when we skip over a NOTE we must fix
2007 it up. Otherwise that code walks into the non-deleted
2008 insn stream. */
2011 }
2013 /* The more regs we move, the less we like moving them. */
2015 }
2017 /* Any other movable that loads the same register
2018 MUST be moved. */
2021 /* This reg has been moved out of one loop. */
2024 /* The reg set here is now invariant. */
2030 /* Change the length-of-life info for the register
2031 to say it lives at least the full length of this loop.
2032 This will help guide optimizations in outer loops. */
2035 /* This is the old insn before all the moved insns.
2036 We can't use the moved insn because it is out of range
2037 in uid_luid. Only the old insns have luids. */
2042 /* Combine with this moved insn any other matching movables. */
2047 {
2048 rtx temp;
2050 /* Schedule the reg loaded by M1
2051 for replacement so that shares the reg of M.
2052 If the modes differ (only possible in restricted
2053 circumstances, make a SUBREG.
2055 Note this assumes that the target dependent files
2056 treat REG and SUBREG equally, including within
2057 GO_IF_LEGITIMATE_ADDRESS and in all the
2058 predicates since we never verify that replacing the
2059 original register with a SUBREG results in a
2060 recognizable insn. */
2063 else
2068 /* Get rid of the matching insn
2069 and prevent further processing of it. */
2072 /* if library call, delete all insn except last, which
2073 is deleted below */
2075 NULL_RTX)))
2076 {
2080 }
2083 /* Any other movable that loads the same register
2084 MUST be moved. */
2087 /* The reg merged here is now invariant,
2088 if the reg it matches is invariant. */
2091 }
2092 }
2095 }
2101 }
2106 /* Go through all the instructions in the loop, making
2107 all the register substitutions scheduled in REG_MAP. */
2111 {
2115 }
2117 /* Clean up. */
2120 }
2123 static void
2127 {
2130 else
2133 }
2136 static void
2139 {
2144 {
2147 }
2148 }
2149 \f
2150 #if 0
2151 /* Scan X and replace the address of any MEM in it with ADDR.
2152 REG is the address that MEM should have before the replacement. */
2154 static void
2157 {
2166 {
2178 /* Short cut for very common case. */
2183 /* Short cut for very common case. */
2188 /* If this MEM uses a reg other than the one we expected,
2189 something is wrong. */
2197 }
2201 {
2205 {
2209 }
2210 }
2211 }
2212 #endif
2213 \f
2214 /* Return the number of memory refs to addresses that vary
2215 in the rtx X. */
2217 static int
2220 rtx x;
2221 {
2232 {
2249 }
2254 {
2258 {
2262 }
2263 }
2265 }
2266 \f
2267 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2268 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2269 `unknown_address_altered', `unknown_constant_address_altered', and
2270 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2271 list `store_mems' in LOOP. */
2273 static void
2276 {
2278 rtx insn;
2282 /* The label after END. Jumping here is just like falling off the
2283 end of the loop. We use next_nonnote_insn instead of next_label
2284 as a hedge against the (pathological) case where some actual insn
2285 might end up between the two. */
2307 {
2309 {
2312 }
2313 }
2317 {
2319 {
2321 {
2323 /* Count number of loops contained in this one. */
2325 }
2327 {
2329 }
2330 }
2332 {
2334 {
2337 }
2339 }
2341 {
2361 {
2363 {
2366 }
2367 else
2368 {
2370 }
2372 do
2373 {
2375 {
2377 {
2378 /* Something tricky. */
2381 }
2384 {
2385 /* A jump outside the current loop. */
2388 }
2389 }
2393 }
2395 }
2396 }
2399 }
2401 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2403 anywhere. */
2405 /* We don't want loads for MEMs moved to a location before the
2406 one at which their stack memory becomes allocated. (Note
2407 that this is not a problem for malloc, etc., since those
2408 require actual function calls. */
2409 && ! current_function_calls_alloca
2410 /* There are ways to leave the loop other than falling off the
2411 end. */
2417 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2418 that loop_invariant_p and load_mems can use true_dependence
2419 to determine what is really clobbered. */
2421 {
2424 loop_info->store_mems
2426 }
2428 {
2432 loop_info->store_mems
2434 }
2435 }
2436 \f
2437 /* Scan the function looking for loops. Record the start and end of each loop.
2438 Also mark as invalid loops any loops that contain a setjmp or are branched
2439 to from outside the loop. */
2441 static void
2443 rtx f;
2445 {
2446 rtx insn;
2447 rtx label;
2457 /* If there are jumps to undefined labels,
2458 treat them as jumps out of any/all loops.
2459 This also avoids writing past end of tables when there are no loops. */
2462 /* Find boundaries of loops, mark which loops are contained within
2463 loops, and invalidate loops that have setjmp. */
2468 {
2471 {
2475 num_loops++;
2482 /* In this case, we must invalidate our current loop and any
2483 enclosing loop. */
2485 {
2491 }
2512 }
2514 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2515 enclosing loop, but this doesn't matter. */
2517 }
2519 /* Any loop containing a label used in an initializer must be invalidated,
2520 because it can be jumped into from anywhere. */
2523 {
2527 }
2529 /* Any loop containing a label used for an exception handler must be
2530 invalidated, because it can be jumped into from anywhere. */
2533 {
2537 }
2539 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2540 loop that it is not contained within, that loop is marked invalid.
2541 If any INSN or CALL_INSN uses a label's address, then the loop containing
2542 that label is marked invalid, because it could be jumped into from
2543 anywhere.
2545 Also look for blocks of code ending in an unconditional branch that
2546 exits the loop. If such a block is surrounded by a conditional
2547 branch around the block, move the block elsewhere (see below) and
2548 invert the jump to point to the code block. This may eliminate a
2549 label in our loop and will simplify processing by both us and a
2550 possible second cse pass. */
2554 {
2558 {
2561 {
2565 }
2566 }
2573 /* See if this is an unconditional branch outside the loop. */
2581 {
2582 rtx p;
2588 /* Go backwards until we reach the start of the loop, a label,
2589 or a JUMP_INSN. */
2596 ;
2598 /* Check for the case where we have a jump to an inner nested
2599 loop, and do not perform the optimization in that case. */
2602 {
2605 {
2610 }
2611 }
2613 /* Make sure that the target of P is within the current loop. */
2619 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2620 we have a block of code to try to move.
2622 We look backward and then forward from the target of INSN
2623 to find a BARRIER at the same loop depth as the target.
2624 If we find such a BARRIER, we make a new label for the start
2625 of the block, invert the jump in P and point it to that label,
2626 and move the block of code to the spot we found. */
2631 /* Just ignore jumps to labels that were never emitted.
2632 These always indicate compilation errors. */
2636 /* If it's not safe to move the sequence, then we
2637 mustn't try. */
2640 {
2641 rtx target
2648 /* Don't move things inside a tablejump. */
2661 /* Don't move things inside a tablejump. */
2672 {
2676 /* Ensure our label doesn't go away. */
2679 /* Verify that uid_loop is large enough and that
2680 we can invert P. */
2682 {
2685 /* If no suitable BARRIER was found, create a suitable
2686 one before TARGET. Since TARGET is a fall through
2687 path, we'll need to insert an jump around our block
2688 and a add a BARRIER before TARGET.
2690 This creates an extra unconditional jump outside
2691 the loop. However, the benefits of removing rarely
2692 executed instructions from inside the loop usually
2693 outweighs the cost of the extra unconditional jump
2694 outside the loop. */
2696 {
2697 rtx temp;
2704 }
2706 /* Include the BARRIER after INSN and copy the
2707 block after LOC. */
2709 last_insn_to_move);
2712 /* All those insns are now in TARGET_LOOP. */
2718 /* The label jumped to by INSN is no longer a loop
2719 exit. Unless INSN does not have a label (e.g.,
2720 it is a RETURN insn), search loop->exit_labels
2721 to find its label_ref, and remove it. Also turn
2722 off LABEL_OUTSIDE_LOOP_P bit. */
2724 {
2726 r;
2729 {
2733 else
2736 }
2742 /* If we didn't find it, then something is
2743 wrong. */
2746 }
2748 /* P is now a jump outside the loop, so it must be put
2749 in loop->exit_labels, and marked as such.
2750 The easiest way to do this is to just call
2751 mark_loop_jump again for P. */
2754 /* If INSN now jumps to the insn after it,
2755 delete INSN. */
2760 }
2762 /* Continue the loop after where the conditional
2763 branch used to jump, since the only branch insn
2764 in the block (if it still remains) is an inter-loop
2765 branch and hence needs no processing. */
2771 /* This loop will be continued with NEXT_INSN (insn). */
2773 }
2774 }
2775 }
2776 }
2777 }
2779 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2780 loops it is contained in, mark the target loop invalid.
2782 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2784 static void
2786 rtx x;
2788 {
2794 {
2806 /* There could be a label reference in here. */
2818 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2830 /* Link together all labels that branch outside the loop. This
2831 is used by final_[bg]iv_value and the loop unrolling code. Also
2832 mark this LABEL_REF so we know that this branch should predict
2833 false. */
2835 /* A check to make sure the label is not in an inner nested loop,
2836 since this does not count as a loop exit. */
2838 {
2843 }
2844 else
2848 {
2857 }
2859 /* If this is inside a loop, but not in the current loop or one enclosed
2860 by it, it invalidates at least one loop. */
2865 /* We must invalidate every nested loop containing the target of this
2866 label, except those that also contain the jump insn. */
2869 {
2870 /* Stop when we reach a loop that also contains the jump insn. */
2875 /* If we get here, we know we need to invalidate a loop. */
2882 }
2886 /* If this is not setting pc, ignore. */
2908 /* Strictly speaking this is not a jump into the loop, only a possible
2909 jump out of the loop. However, we have no way to link the destination
2910 of this jump onto the list of exit labels. To be safe we mark this
2911 loop and any containing loops as invalid. */
2913 {
2915 {
2921 }
2922 }
2924 }
2925 }
2926 \f
2927 /* Return nonzero if there is a label in the range from
2928 insn INSN to and including the insn whose luid is END
2929 INSN must have an assigned luid (i.e., it must not have
2930 been previously created by loop.c). */
2932 static int
2934 rtx insn;
2936 {
2938 {
2942 }
2945 }
2947 /* Record that a memory reference X is being set. */
2949 static void
2951 rtx x;
2952 rtx y ATTRIBUTE_UNUSED;
2954 {
2960 /* Count number of memory writes.
2961 This affects heuristics in strength_reduce. */
2964 /* BLKmode MEM means all memory is clobbered. */
2966 {
2969 else
2973 }
2977 }
2979 /* X is a value modified by an INSN that references a biv inside a loop
2980 exit test (ie, X is somehow related to the value of the biv). If X
2981 is a pseudo that is used more than once, then the biv is (effectively)
2982 used more than once. DATA is a pointer to a loop_regs structure. */
2984 static void
2986 rtx x;
2987 rtx y ATTRIBUTE_UNUSED;
2989 {
3004 /* If we do not have usage information, or if we know the register
3005 is used more than once, note that fact for check_dbra_loop. */
3010 }
3011 \f
3012 /* Return nonzero if the rtx X is invariant over the current loop.
3014 The value is 2 if we refer to something only conditionally invariant.
3016 A memory ref is invariant if it is not volatile and does not conflict
3017 with anything stored in `loop_info->store_mems'. */
3019 int
3023 {
3030 rtx mem_list_entry;
3036 {
3044 /* A LABEL_REF is normally invariant, however, if we are unrolling
3045 loops, and this label is inside the loop, then it isn't invariant.
3046 This is because each unrolled copy of the loop body will have
3047 a copy of this label. If this was invariant, then an insn loading
3048 the address of this label into a register might get moved outside
3049 the loop, and then each loop body would end up using the same label.
3051 We don't know the loop bounds here though, so just fail for all
3052 labels. */
3055 else
3064 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3065 since the reg might be set by initialization within the loop. */
3082 /* Volatile memory references must be rejected. Do this before
3083 checking for read-only items, so that volatile read-only items
3084 will be rejected also. */
3088 /* See if there is any dependence between a store and this load. */
3091 {
3097 }
3099 /* It's not invalidated by a store in memory
3100 but we must still verify the address is invariant. */
3104 /* Don't mess with insns declared volatile. */
3111 }
3115 {
3117 {
3123 }
3125 {
3128 {
3134 }
3136 }
3137 }
3140 }
3141 \f
3142 /* Return nonzero if all the insns in the loop that set REG
3143 are INSN and the immediately following insns,
3144 and if each of those insns sets REG in an invariant way
3145 (not counting uses of REG in them).
3147 The value is 2 if some of these insns are only conditionally invariant.
3149 We assume that INSN itself is the first set of REG
3150 and that its source is invariant. */
3152 static int
3157 {
3161 rtx temp;
3162 /* Number of sets we have to insist on finding after INSN. */
3168 /* If N_SETS hit the limit, we can't rely on its value. */
3175 {
3177 rtx set;
3182 /* If library call, skip to end of it. */
3191 {
3196 {
3197 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3198 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3199 notes are OK. */
3205 }
3206 }
3208 count--;
3210 {
3213 }
3214 }
3217 /* If loop_invariant_p ever returned 2, we return 2. */
3219 }
3221 #if 0
3222 /* I don't think this condition is sufficient to allow INSN
3223 to be moved, so we no longer test it. */
3225 /* Return 1 if all insns in the basic block of INSN and following INSN
3226 that set REG are invariant according to TABLE. */
3228 static int
3232 {
3237 {
3246 {
3249 }
3250 }
3251 }
3253 \f
3254 /* Look at all uses (not sets) of registers in X. For each, if it is
3255 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3256 a different insn, set USAGE[REGNO] to const0_rtx. */
3258 static void
3261 rtx insn;
3262 rtx x;
3263 {
3275 {
3276 /* Don't count SET_DEST if it is a REG; otherwise count things
3277 in SET_DEST because if a register is partially modified, it won't
3278 show up as a potential movable so we don't care how USAGE is set
3279 for it. */
3283 }
3284 else
3286 {
3292 }
3293 }
3294 \f
3295 /* Count and record any set in X which is contained in INSN. Update
3296 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3297 in X. */
3299 static void
3304 {
3306 /* Don't move a reg that has an explicit clobber.
3307 It's not worth the pain to try to do it correctly. */
3311 {
3319 {
3321 /* If this is the first setting of this reg
3322 in current basic block, and it was set before,
3323 it must be set in two basic blocks, so it cannot
3324 be moved out of the loop. */
3328 /* If this is not first setting in current basic block,
3329 see if reg was used in between previous one and this.
3330 If so, neither one can be moved. */
3337 }
3338 }
3339 }
3340 \f
3341 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3342 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3343 contained in insn INSN is used by any insn that precedes INSN in
3344 cyclic order starting from the loop entry point.
3346 We don't want to use INSN_LUID here because if we restrict INSN to those
3347 that have a valid INSN_LUID, it means we cannot move an invariant out
3348 from an inner loop past two loops. */
3350 static int
3354 {
3356 rtx p;
3358 /* Scan forward checking for register usage. If we hit INSN, we
3359 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3361 {
3367 }
3370 }
3371 \f
3372 /* A "basic induction variable" or biv is a pseudo reg that is set
3373 (within this loop) only by incrementing or decrementing it. */
3374 /* A "general induction variable" or giv is a pseudo reg whose
3375 value is a linear function of a biv. */
3377 /* Bivs are recognized by `basic_induction_var';
3378 Givs by `general_induction_var'. */
3380 /* Communication with routines called via `note_stores'. */
3384 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3388 /* ??? Unfinished optimizations, and possible future optimizations,
3389 for the strength reduction code. */
3391 /* ??? The interaction of biv elimination, and recognition of 'constant'
3392 bivs, may cause problems. */
3394 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3395 performance problems.
3397 Perhaps don't eliminate things that can be combined with an addressing
3398 mode. Find all givs that have the same biv, mult_val, and add_val;
3399 then for each giv, check to see if its only use dies in a following
3400 memory address. If so, generate a new memory address and check to see
3401 if it is valid. If it is valid, then store the modified memory address,
3402 otherwise, mark the giv as not done so that it will get its own iv. */
3404 /* ??? Could try to optimize branches when it is known that a biv is always
3405 positive. */
3407 /* ??? When replace a biv in a compare insn, we should replace with closest
3408 giv so that an optimized branch can still be recognized by the combiner,
3409 e.g. the VAX acb insn. */
3411 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3412 was rerun in loop_optimize whenever a register was added or moved.
3413 Also, some of the optimizations could be a little less conservative. */
3414 \f
3415 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3416 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3417 callback.
3419 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3420 loop iteration except for the last one.
3422 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3423 loop iteration.
3424 */
3425 void
3428 loop_insn_callback fncall;
3429 {
3430 /* This is 1 if current insn is not executed at least once for every loop
3431 iteration. */
3436 rtx p;
3438 /* If loop_scan_start points to the loop exit test, we have to be wary of
3439 subversive use of gotos inside expression statements. */
3443 /* Scan through loop to find all possible bivs. */
3448 {
3451 /* Past CODE_LABEL, we get to insns that may be executed multiple
3452 times. The only way we can be sure that they can't is if every
3453 jump insn between here and the end of the loop either
3454 returns, exits the loop, is a jump to a location that is still
3455 behind the label, or is a jump to the loop start. */
3458 {
3464 {
3469 {
3472 else
3476 }
3484 {
3487 }
3488 }
3489 }
3491 /* Past a jump, we get to insns for which we can't count
3492 on whether they will be executed during each iteration. */
3493 /* This code appears twice in strength_reduce. There is also similar
3494 code in scan_loop. */
3496 /* If we enter the loop in the middle, and scan around to the
3497 beginning, don't set not_every_iteration for that.
3498 This can be any kind of jump, since we want to know if insns
3499 will be executed if the loop is executed. */
3504 {
3507 /* If this is a jump outside the loop, then it also doesn't
3508 matter. Check to see if the target of this branch is on the
3509 loop->exits_labels list. */
3517 }
3520 {
3521 /* At the virtual top of a converted loop, insns are again known to
3522 be executed each iteration: logically, the loop begins here
3523 even though the exit code has been duplicated.
3525 Insns are also again known to be executed each iteration at
3526 the LOOP_CONT note. */
3532 loop_depth++;
3534 loop_depth--;
3535 }
3537 /* Note if we pass a loop latch. If we do, then we can not clear
3538 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3539 a loop since a jump before the last CODE_LABEL may have started
3540 a new loop iteration.
3542 Note that LOOP_TOP is only set for rotated loops and we need
3543 this check for all loops, so compare against the CODE_LABEL
3544 which immediately follows LOOP_START. */
3549 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3550 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3551 or not an insn is known to be executed each iteration of the
3552 loop, whether or not any iterations are known to occur.
3554 Therefore, if we have just passed a label and have no more labels
3555 between here and the test insn of the loop, and we have not passed
3556 a jump to the top of the loop, then we know these insns will be
3557 executed each iteration. */
3560 && !past_loop_latch
3565 }
3566 }
3567 \f
3568 static void
3571 {
3574 /* Temporary list pointers for traversing ivs->list. */
3581 /* Scan ivs->list to remove all regs that proved not to be bivs.
3582 Make a sanity check against regs->n_times_set. */
3584 {
3586 /* Above happens if register modified by subreg, etc. */
3587 /* Make sure it is not recognized as a basic induction var: */
3589 /* If never incremented, it is invariant that we decided not to
3590 move. So leave it alone. */
3592 {
3603 }
3604 else
3605 {
3610 }
3611 }
3612 }
3615 /* Determine how BIVS are initialised by looking through pre-header
3616 extended basic block. */
3617 static void
3620 {
3622 /* Temporary list pointers for traversing ivs->list. */
3625 rtx p;
3627 /* Find initial value for each biv by searching backwards from loop_start,
3628 halting at first label. Also record any test condition. */
3632 {
3633 rtx test;
3643 /* Record any test of a biv that branches around the loop if no store
3644 between it and the start of loop. We only care about tests with
3645 constants and registers and only certain of those. */
3655 {
3656 /* If an NE test, we have an initial value! */
3658 {
3662 }
3663 else
3665 }
3666 }
3667 }
3670 /* Look at the each biv and see if we can say anything better about its
3671 initial value from any initializing insns set up above. (This is done
3672 in two passes to avoid missing SETs in a PARALLEL.) */
3673 static void
3676 {
3678 /* Temporary list pointers for traversing ivs->list. */
3683 {
3684 rtx src;
3685 rtx note;
3690 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3691 is a constant, use the value of that. */
3697 else
3710 {
3714 {
3717 }
3718 }
3719 /* If we can't make it a giv,
3720 let biv keep initial value of "itself". */
3723 }
3724 }
3727 /* Search the loop for general induction variables. */
3729 static void
3732 {
3734 }
3737 /* For each giv for which we still don't know whether or not it is
3738 replaceable, check to see if it is replaceable because its final value
3739 can be calculated. */
3741 static void
3744 {
3749 {
3755 }
3756 }
3759 /* Return non-zero if it is possible to eliminate the biv BL provided
3760 all givs are reduced. This is possible if either the reg is not
3761 used outside the loop, or we can compute what its final value will
3762 be. */
3764 static int
3770 {
3771 /* For architectures with a decrement_and_branch_until_zero insn,
3772 don't do this if we put a REG_NONNEG note on the endtest for this
3773 biv. */
3775 #ifdef HAVE_decrement_and_branch_until_zero
3777 {
3782 }
3783 #endif
3785 /* Check that biv is used outside loop or if it has a final value.
3786 Compare against bl->init_insn rather than loop->start. We aren't
3787 concerned with any uses of the biv between init_insn and
3788 loop->start since these won't be affected by the value of the biv
3789 elsewhere in the function, so long as init_insn doesn't use the
3790 biv itself. */
3801 {
3809 }
3811 }
3814 /* Reduce each giv of BL that we have decided to reduce. */
3816 static void
3820 {
3824 {
3827 {
3830 /* If the code for derived givs immediately below has already
3831 allocated a new_reg, we must keep it. */
3835 #ifdef AUTO_INC_DEC
3836 /* If the target has auto-increment addressing modes, and
3837 this is an address giv, then try to put the increment
3838 immediately after its use, so that flow can create an
3839 auto-increment addressing mode. */
3842 /* We don't handle reversed biv's because bl->biv->insn
3843 does not have a valid INSN_LUID. */
3847 {
3848 /* If other giv's have been combined with this one, then
3849 this will work only if all uses of the other giv's occur
3850 before this giv's insn. This is difficult to check.
3852 We simplify this by looking for the common case where
3853 there is one DEST_REG giv, and this giv's insn is the
3854 last use of the dest_reg of that DEST_REG giv. If the
3855 increment occurs after the address giv, then we can
3856 perform the optimization. (Otherwise, the increment
3857 would have to go before other_giv, and we would not be
3858 able to combine it with the address giv to get an
3859 auto-inc address.) */
3861 {
3866 {
3869 else
3871 }
3878 }
3879 /* Check for case where increment is before the address
3880 giv. Do this test in "loop order". */
3889 else
3892 #ifdef HAVE_cc0
3893 {
3894 rtx prev;
3896 /* We can't put an insn immediately after one setting
3897 cc0, or immediately before one using cc0. */
3904 }
3905 #endif
3909 }
3910 #endif
3912 /* For each place where the biv is incremented, add an insn
3913 to increment the new, reduced reg for the giv. */
3915 {
3916 rtx insert_before;
3922 else
3930 /* A multiply is acceptable here
3931 since this is presumed to be seldom executed. */
3935 }
3937 /* Add code at loop start to initialize giv's reduced reg. */
3942 }
3943 }
3944 }
3947 /* Check for givs whose first use is their definition and whose
3948 last use is the definition of another giv. If so, it is likely
3949 dead and should not be used to derive another giv nor to
3950 eliminate a biv. */
3952 static void
3956 {
3960 {
3967 {
3973 }
3974 }
3975 }
3978 static void
3983 {
3987 {
3994 /* Update expression if this was combined, in case other giv was
3995 replaced. */
4000 /* See if this register is known to be a pointer to something. If
4001 so, see if we can find the alignment. First see if there is a
4002 destination register that is a pointer. If so, this shares the
4003 alignment too. Next see if we can deduce anything from the
4004 computational information. If not, and this is a DEST_ADDR
4005 giv, at least we know that it's a pointer, though we don't know
4006 the alignment. */
4014 {
4023 }
4027 {
4035 }
4040 /* Store reduced reg as the address in the memref where we found
4041 this giv. */
4044 {
4046 }
4047 else
4048 {
4049 /* Not replaceable; emit an insn to set the original giv reg from
4050 the reduced giv, same as above. */
4053 }
4055 /* When a loop is reversed, givs which depend on the reversed
4056 biv, and which are live outside the loop, must be set to their
4057 correct final value. This insn is only needed if the giv is
4058 not replaceable. The correct final value is the same as the
4059 value that the giv starts the reversed loop with. */
4069 {
4074 }
4075 }
4076 }
4079 static int
4084 rtx test_reg;
4085 {
4094 /* Reduce benefit if not replaceable, since we will insert a
4095 move-insn to replace the insn that calculates this giv. Don't do
4096 this unless the giv is a user variable, since it will often be
4097 marked non-replaceable because of the duplication of the exit
4098 code outside the loop. In such a case, the copies we insert are
4099 dead and will be deleted. So they don't have a cost. Similar
4100 situations exist. */
4101 /* ??? The new final_[bg]iv_value code does a much better job of
4102 finding replaceable giv's, and hence this code may no longer be
4103 necessary. */
4108 /* Decrease the benefit to count the add-insns that we will insert
4109 to increment the reduced reg for the giv. ??? This can
4110 overestimate the run-time cost of the additional insns, e.g. if
4111 there are multiple basic blocks that increment the biv, but only
4112 one of these blocks is executed during each iteration. There is
4113 no good way to detect cases like this with the current structure
4114 of the loop optimizer. This code is more accurate for
4115 determining code size than run-time benefits. */
4118 /* Decide whether to strength-reduce this giv or to leave the code
4119 unchanged (recompute it from the biv each time it is used). This
4120 decision can be made independently for each giv. */
4122 #ifdef AUTO_INC_DEC
4123 /* Attempt to guess whether autoincrement will handle some of the
4124 new add insns; if so, increase BENEFIT (undo the subtraction of
4125 add_cost that was done above). */
4127 /* Increasing the benefit is risky, since this is only a guess.
4128 Avoid increasing register pressure in cases where there would
4129 be no other benefit from reducing this giv. */
4132 {
4145 }
4146 #endif
4149 }
4152 /* Free IV structures for LOOP. */
4154 static void
4157 {
4164 {
4170 {
4173 }
4175 {
4178 }
4182 }
4183 }
4186 /* Perform strength reduction and induction variable elimination.
4188 Pseudo registers created during this function will be beyond the
4189 last valid index in several tables including
4190 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4191 problem here, because the added registers cannot be givs outside of
4192 their loop, and hence will never be reconsidered. But scan_loop
4193 must check regnos to make sure they are in bounds. */
4195 static void
4200 {
4204 rtx p;
4205 /* Temporary list pointer for traversing ivs->list. */
4207 /* Ratio of extra register life span we can justify
4208 for saving an instruction. More if loop doesn't call subroutines
4209 since in that case saving an insn makes more difference
4210 and more registers are available. */
4211 /* ??? could set this to last value of threshold in move_movables */
4213 /* Map of pseudo-register replacements. */
4224 /* Find all BIVs in loop. */
4227 /* Exit if there are no bivs. */
4229 {
4230 /* Can still unroll the loop anyways, but indicate that there is no
4231 strength reduction info available. */
4237 }
4239 /* Determine how BIVS are initialised by looking through pre-header
4240 extended basic block. */
4243 /* Look at the each biv and see if we can say anything better about its
4244 initial value from any initializing insns set up above. */
4247 /* Search the loop for general induction variables. */
4250 /* Try to calculate and save the number of loop iterations. This is
4251 set to zero if the actual number can not be calculated. This must
4252 be called after all giv's have been identified, since otherwise it may
4253 fail if the iteration variable is a giv. */
4256 /* Now for each giv for which we still don't know whether or not it is
4257 replaceable, check to see if it is replaceable because its final value
4258 can be calculated. This must be done after loop_iterations is called,
4259 so that final_giv_value will work correctly. */
4262 /* Try to prove that the loop counter variable (if any) is always
4263 nonnegative; if so, record that fact with a REG_NONNEG note
4264 so that "decrement and branch until zero" insn can be used. */
4267 /* Create reg_map to hold substitutions for replaceable giv regs.
4268 Some givs might have been made from biv increments, so look at
4269 ivs->reg_iv_type for a suitable size. */
4273 /* Examine each iv class for feasibility of strength reduction/induction
4274 variable elimination. */
4277 {
4281 /* Test whether it will be possible to eliminate this biv
4282 provided all givs are reduced. */
4285 /* Check each extension dependent giv in this class to see if its
4286 root biv is safe from wrapping in the interior mode. */
4289 /* Combine all giv's for this iv_class. */
4292 /* This will be true at the end, if all givs which depend on this
4293 biv have been strength reduced.
4294 We can't (currently) eliminate the biv unless this is so. */
4298 {
4306 /* If an insn is not to be strength reduced, then set its ignore
4307 flag, and clear bl->all_reduced. */
4309 /* A giv that depends on a reversed biv must be reduced if it is
4310 used after the loop exit, otherwise, it would have the wrong
4311 value after the loop exit. To make it simple, just reduce all
4312 of such giv's whether or not we know they are used after the loop
4313 exit. */
4318 {
4326 }
4327 else
4328 {
4329 /* Check that we can increment the reduced giv without a
4330 multiply insn. If not, reject it. */
4335 {
4343 }
4344 }
4345 }
4347 /* Check for givs whose first use is their definition and whose
4348 last use is the definition of another giv. If so, it is likely
4349 dead and should not be used to derive another giv nor to
4350 eliminate a biv. */
4353 /* Reduce each giv that we decided to reduce. */
4356 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4357 as not reduced.
4359 For each giv register that can be reduced now: if replaceable,
4360 substitute reduced reg wherever the old giv occurs;
4361 else add new move insn "giv_reg = reduced_reg". */
4364 /* All the givs based on the biv bl have been reduced if they
4365 merit it. */
4367 /* For each giv not marked as maybe dead that has been combined with a
4368 second giv, clear any "maybe dead" mark on that second giv.
4369 v->new_reg will either be or refer to the register of the giv it
4370 combined with.
4372 Doing this clearing avoids problems in biv elimination where
4373 a giv's new_reg is a complex value that can't be put in the
4374 insn but the giv combined with (with a reg as new_reg) is
4375 marked maybe_dead. Since the register will be used in either
4376 case, we'd prefer it be used from the simpler giv. */
4382 /* Try to eliminate the biv, if it is a candidate.
4383 This won't work if ! bl->all_reduced,
4384 since the givs we planned to use might not have been reduced.
4386 We have to be careful that we didn't initially think we could
4387 eliminate this biv because of a giv that we now think may be
4388 dead and shouldn't be used as a biv replacement.
4390 Also, there is the possibility that we may have a giv that looks
4391 like it can be used to eliminate a biv, but the resulting insn
4392 isn't valid. This can happen, for example, on the 88k, where a
4393 JUMP_INSN can compare a register only with zero. Attempts to
4394 replace it with a compare with a constant will fail.
4396 Note that in cases where this call fails, we may have replaced some
4397 of the occurrences of the biv with a giv, but no harm was done in
4398 doing so in the rare cases where it can occur. */
4402 {
4403 /* ?? If we created a new test to bypass the loop entirely,
4404 or otherwise drop straight in, based on this test, then
4405 we might want to rewrite it also. This way some later
4406 pass has more hope of removing the initialization of this
4407 biv entirely. */
4409 /* If final_value != 0, then the biv may be used after loop end
4410 and we must emit an insn to set it just in case.
4412 Reversed bivs already have an insn after the loop setting their
4413 value, so we don't need another one. We can't calculate the
4414 proper final value for such a biv here anyways. */
4422 }
4423 }
4425 /* Go through all the instructions in the loop, making all the
4426 register substitutions scheduled in REG_MAP. */
4431 {
4435 }
4438 {
4439 /* When we completely unroll a loop we will likely not need the increment
4440 of the loop BIV and we will not need the conditional branch at the
4441 end of the loop. */
4444 #ifdef HAVE_cc0
4445 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4446 need the comparison before the conditional branch at the end of the
4447 loop. */
4449 #endif
4451 /* We'll need one copy for each loop iteration. */
4454 /* A little slop to account for the ability to remove initialization
4455 code, better CSE, and other secondary benefits of completely
4456 unrolling some loops. */
4459 /* Clamp the value. */
4462 }
4464 /* Unroll loops from within strength reduction so that we can use the
4465 induction variable information that strength_reduce has already
4466 collected. Always unroll loops that would be as small or smaller
4467 unrolled than when rolled. */
4473 #ifdef HAVE_doloop_end
4484 }
4485 \f
4486 /*Record all basic induction variables calculated in the insn. */
4487 static rtx
4490 rtx p;
4493 {
4495 rtx set;
4496 rtx dest_reg;
4497 rtx inc_val;
4498 rtx mult_val;
4504 {
4509 {
4514 {
4515 /* It is a possible basic induction variable.
4516 Create and initialize an induction structure for it. */
4524 }
4527 }
4528 }
4530 }
4531 \f
4532 /* Record all givs calculated in the insn.
4533 A register is a giv if: it is only set once, it is a function of a
4534 biv and a constant (or invariant), and it is not a biv. */
4535 static rtx
4538 rtx p;
4541 {
4544 rtx set;
4545 /* Look for a general induction variable in a register. */
4550 {
4551 rtx src_reg;
4552 rtx dest_reg;
4553 rtx add_val;
4554 rtx mult_val;
4555 rtx ext_val;
4558 rtx last_consec_insn;
4567 /* Equivalent expression is a giv. */
4572 /* Don't try to handle any regs made by loop optimization.
4573 We have nothing on them in regno_first_uid, etc. */
4575 /* Don't recognize a BASIC_INDUCT_VAR here. */
4577 /* This must be the only place where the register is set. */
4579 /* or all sets must be consecutive and make a giv. */
4584 {
4588 /* If this is a library call, increase benefit. */
4592 /* Skip the consecutive insns, if there are any. */
4600 }
4601 }
4603 #ifndef DONT_REDUCE_ADDR
4604 /* Look for givs which are memory addresses. */
4605 /* This resulted in worse code on a VAX 8600. I wonder if it
4606 still does. */
4609 maybe_multiple);
4610 #endif
4612 /* Update the status of whether giv can derive other givs. This can
4613 change when we pass a label or an insn that updates a biv. */
4618 }
4619 \f
4620 /* Return 1 if X is a valid source for an initial value (or as value being
4621 compared against in an initial test).
4623 X must be either a register or constant and must not be clobbered between
4624 the current insn and the start of the loop.
4626 INSN is the insn containing X. */
4628 static int
4630 rtx x;
4631 rtx insn;
4633 rtx loop_start;
4634 {
4638 /* Only consider pseudos we know about initialized in insns whose luids
4639 we know. */
4644 /* Don't use call-clobbered registers across a call which clobbers it. On
4645 some machines, don't use any hard registers at all. */
4647 && (SMALL_REGISTER_CLASSES
4651 /* Don't use registers that have been clobbered before the start of the
4652 loop. */
4657 }
4658 \f
4659 /* Scan X for memory refs and check each memory address
4660 as a possible giv. INSN is the insn whose pattern X comes from.
4661 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4662 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4663 more thanonce in each loop iteration. */
4665 static void
4668 rtx x;
4669 rtx insn;
4671 {
4681 {
4697 {
4698 rtx src_reg;
4699 rtx add_val;
4700 rtx mult_val;
4701 rtx ext_val;
4704 /* This code used to disable creating GIVs with mult_val == 1 and
4705 add_val == 0. However, this leads to lost optimizations when
4706 it comes time to combine a set of related DEST_ADDR GIVs, since
4707 this one would not be seen. */
4712 {
4713 /* Found one; record it. */
4722 }
4723 }
4728 }
4730 /* Recursively scan the subexpressions for other mem refs. */
4736 maybe_multiple);
4740 maybe_multiple);
4741 }
4742 \f
4743 /* Fill in the data about one biv update.
4744 V is the `struct induction' in which we record the biv. (It is
4745 allocated by the caller, with alloca.)
4746 INSN is the insn that sets it.
4747 DEST_REG is the biv's reg.
4749 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4750 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4751 being set to INC_VAL.
4753 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4754 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4755 can be executed more than once per iteration. If MAYBE_MULTIPLE
4756 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4757 executed exactly once per iteration. */
4759 static void
4764 rtx insn;
4765 rtx dest_reg;
4766 rtx inc_val;
4767 rtx mult_val;
4771 {
4787 /* Add this to the reg's iv_class, creating a class
4788 if this is the first incrementation of the reg. */
4792 {
4793 /* Create and initialize new iv_class. */
4803 /* Set initial value to the reg itself. */
4806 /* We haven't seen the initializing insn yet */
4816 /* Add this class to ivs->list. */
4820 /* Put it in the array of biv register classes. */
4822 }
4824 /* Update IV_CLASS entry for this biv. */
4833 }
4834 \f
4835 /* Fill in the data about one giv.
4836 V is the `struct induction' in which we record the giv. (It is
4837 allocated by the caller, with alloca.)
4838 INSN is the insn that sets it.
4839 BENEFIT estimates the savings from deleting this insn.
4840 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4841 into a register or is used as a memory address.
4843 SRC_REG is the biv reg which the giv is computed from.
4844 DEST_REG is the giv's reg (if the giv is stored in a reg).
4845 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4846 LOCATION points to the place where this giv's value appears in INSN. */
4848 static void
4853 rtx insn;
4854 rtx src_reg;
4855 rtx dest_reg;
4861 {
4866 rtx temp;
4868 /* Attempt to prove constantness of the values. */
4896 /* The v->always_computable field is used in update_giv_derive, to
4897 determine whether a giv can be used to derive another giv. For a
4898 DEST_REG giv, INSN computes a new value for the giv, so its value
4899 isn't computable if INSN insn't executed every iteration.
4900 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4901 it does not compute a new value. Hence the value is always computable
4902 regardless of whether INSN is executed each iteration. */
4906 else
4912 {
4915 }
4917 {
4922 /* If the lifetime is zero, it means that this register is
4923 really a dead store. So mark this as a giv that can be
4924 ignored. This will not prevent the biv from being eliminated. */
4930 }
4932 /* Add the giv to the class of givs computed from one biv. */
4936 {
4939 /* Don't count DEST_ADDR. This is supposed to count the number of
4940 insns that calculate givs. */
4944 }
4945 else
4946 /* Fatal error, biv missing for this giv? */
4951 else
4952 {
4953 /* The giv can be replaced outright by the reduced register only if all
4954 of the following conditions are true:
4955 - the insn that sets the giv is always executed on any iteration
4956 on which the giv is used at all
4957 (there are two ways to deduce this:
4958 either the insn is executed on every iteration,
4959 or all uses follow that insn in the same basic block),
4960 - the giv is not used outside the loop
4961 - no assignments to the biv occur during the giv's lifetime. */
4964 /* Previous line always fails if INSN was moved by loop opt. */
4967 && (! not_every_iteration
4969 {
4970 /* Now check that there are no assignments to the biv within the
4971 giv's lifetime. This requires two separate checks. */
4973 /* Check each biv update, and fail if any are between the first
4974 and last use of the giv.
4976 If this loop contains an inner loop that was unrolled, then
4977 the insn modifying the biv may have been emitted by the loop
4978 unrolling code, and hence does not have a valid luid. Just
4979 mark the biv as not replaceable in this case. It is not very
4980 useful as a biv, because it is used in two different loops.
4981 It is very unlikely that we would be able to optimize the giv
4982 using this biv anyways. */
4986 {
4992 {
4996 }
4997 }
4999 /* If there are any backwards branches that go from after the
5000 biv update to before it, then this giv is not replaceable. */
5004 {
5008 }
5009 }
5010 else
5011 {
5012 /* May still be replaceable, we don't have enough info here to
5013 decide. */
5016 }
5017 }
5019 /* Record whether the add_val contains a const_int, for later use by
5020 combine_givs. */
5021 {
5026 ;
5030 {
5032 {
5037 else
5039 }
5042 }
5043 }
5047 }
5049 /* All this does is determine whether a giv can be made replaceable because
5050 its final value can be calculated. This code can not be part of record_giv
5051 above, because final_giv_value requires that the number of loop iterations
5052 be known, and that can not be accurately calculated until after all givs
5053 have been identified. */
5055 static void
5059 {
5066 /* DEST_ADDR givs will never reach here, because they are always marked
5067 replaceable above in record_giv. */
5069 /* The giv can be replaced outright by the reduced register only if all
5070 of the following conditions are true:
5071 - the insn that sets the giv is always executed on any iteration
5072 on which the giv is used at all
5073 (there are two ways to deduce this:
5074 either the insn is executed on every iteration,
5075 or all uses follow that insn in the same basic block),
5076 - its final value can be calculated (this condition is different
5077 than the one above in record_giv)
5078 - it's not used before the it's set
5079 - no assignments to the biv occur during the giv's lifetime. */
5081 #if 0
5082 /* This is only called now when replaceable is known to be false. */
5083 /* Clear replaceable, so that it won't confuse final_giv_value. */
5085 #endif
5089 {
5092 rtx last_giv_use;
5096 /* When trying to determine whether or not a biv increment occurs
5097 during the lifetime of the giv, we can ignore uses of the variable
5098 outside the loop because final_value is true. Hence we can not
5099 use regno_last_uid and regno_first_uid as above in record_giv. */
5101 /* Search the loop to determine whether any assignments to the
5102 biv occur during the giv's lifetime. Start with the insn
5103 that sets the giv, and search around the loop until we come
5104 back to that insn again.
5106 Also fail if there is a jump within the giv's lifetime that jumps
5107 to somewhere outside the lifetime but still within the loop. This
5108 catches spaghetti code where the execution order is not linear, and
5109 hence the above test fails. Here we assume that the giv lifetime
5110 does not extend from one iteration of the loop to the next, so as
5111 to make the test easier. Since the lifetime isn't known yet,
5112 this requires two loops. See also record_giv above. */
5117 {
5120 {
5123 }
5129 {
5130 /* It is possible for the BIV increment to use the GIV if we
5131 have a cycle. Thus we must be sure to check each insn for
5132 both BIV and GIV uses, and we must check for BIV uses
5133 first. */
5140 {
5142 {
5146 }
5148 }
5149 }
5150 }
5152 /* Now that the lifetime of the giv is known, check for branches
5153 from within the lifetime to outside the lifetime if it is still
5154 replaceable. */
5157 {
5160 {
5173 {
5182 }
5183 }
5184 }
5186 /* If it is replaceable, then save the final value. */
5189 }
5194 }
5195 \f
5196 /* Update the status of whether a giv can derive other givs.
5198 We need to do something special if there is or may be an update to the biv
5199 between the time the giv is defined and the time it is used to derive
5200 another giv.
5202 In addition, a giv that is only conditionally set is not allowed to
5203 derive another giv once a label has been passed.
5205 The cases we look at are when a label or an update to a biv is passed. */
5207 static void
5210 rtx p;
5211 {
5215 rtx tem;
5218 /* Search all IV classes, then all bivs, and finally all givs.
5220 There are three cases we are concerned with. First we have the situation
5221 of a giv that is only updated conditionally. In that case, it may not
5222 derive any givs after a label is passed.
5224 The second case is when a biv update occurs, or may occur, after the
5225 definition of a giv. For certain biv updates (see below) that are
5226 known to occur between the giv definition and use, we can adjust the
5227 giv definition. For others, or when the biv update is conditional,
5228 we must prevent the giv from deriving any other givs. There are two
5229 sub-cases within this case.
5231 If this is a label, we are concerned with any biv update that is done
5232 conditionally, since it may be done after the giv is defined followed by
5233 a branch here (actually, we need to pass both a jump and a label, but
5234 this extra tracking doesn't seem worth it).
5236 If this is a jump, we are concerned about any biv update that may be
5237 executed multiple times. We are actually only concerned about
5238 backward jumps, but it is probably not worth performing the test
5239 on the jump again here.
5241 If this is a biv update, we must adjust the giv status to show that a
5242 subsequent biv update was performed. If this adjustment cannot be done,
5243 the giv cannot derive further givs. */
5249 {
5251 {
5252 /* If cant_derive is already true, there is no point in
5253 checking all of these conditions again. */
5257 /* If this giv is conditionally set and we have passed a label,
5258 it cannot derive anything. */
5262 /* Skip givs that have mult_val == 0, since
5263 they are really invariants. Also skip those that are
5264 replaceable, since we know their lifetime doesn't contain
5265 any biv update. */
5269 /* The only way we can allow this giv to derive another
5270 is if this is a biv increment and we can form the product
5271 of biv->add_val and giv->mult_val. In this case, we will
5272 be able to compute a compensation. */
5274 {
5275 rtx ext_val_dummy;
5286 tem = simplify_giv_expr
5293 else
5295 }
5299 }
5300 }
5301 }
5302 \f
5303 /* Check whether an insn is an increment legitimate for a basic induction var.
5304 X is the source of insn P, or a part of it.
5305 MODE is the mode in which X should be interpreted.
5307 DEST_REG is the putative biv, also the destination of the insn.
5308 We accept patterns of these forms:
5309 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5310 REG = INVARIANT + REG
5312 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5313 store the additive term into *INC_VAL, and store the place where
5314 we found the additive term into *LOCATION.
5316 If X is an assignment of an invariant into DEST_REG, we set
5317 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5319 We also want to detect a BIV when it corresponds to a variable
5320 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5321 of the variable may be a PLUS that adds a SUBREG of that variable to
5322 an invariant and then sign- or zero-extends the result of the PLUS
5323 into the variable.
5325 Most GIVs in such cases will be in the promoted mode, since that is the
5326 probably the natural computation mode (and almost certainly the mode
5327 used for addresses) on the machine. So we view the pseudo-reg containing
5328 the variable as the BIV, as if it were simply incremented.
5330 Note that treating the entire pseudo as a BIV will result in making
5331 simple increments to any GIVs based on it. However, if the variable
5332 overflows in its declared mode but not its promoted mode, the result will
5333 be incorrect. This is acceptable if the variable is signed, since
5334 overflows in such cases are undefined, but not if it is unsigned, since
5335 those overflows are defined. So we only check for SIGN_EXTEND and
5336 not ZERO_EXTEND.
5338 If we cannot find a biv, we return 0. */
5340 static int
5345 rtx dest_reg;
5346 rtx p;
5350 {
5358 {
5364 {
5366 }
5371 {
5373 }
5374 else
5387 /* If this is a SUBREG for a promoted variable, check the inner
5388 value. */
5396 /* If this register is assigned in a previous insn, look at its
5397 source, but don't go outside the loop or past a label. */
5399 /* If this sets a register to itself, we would repeat any previous
5400 biv increment if we applied this strategy blindly. */
5406 {
5407 rtx dest;
5408 do
5409 {
5411 }
5440 }
5441 /* Fall through. */
5443 /* Can accept constant setting of biv only when inside inner most loop.
5444 Otherwise, a biv of an inner loop may be incorrectly recognized
5445 as a biv of the outer loop,
5446 causing code to be moved INTO the inner loop. */
5453 /* convert_modes aborts if we try to convert to or from CCmode, so just
5454 exclude that case. It is very unlikely that a condition code value
5455 would be a useful iterator anyways. */
5459 {
5460 /* Possible bug here? Perhaps we don't know the mode of X. */
5464 }
5465 else
5473 /* Similar, since this can be a sign extension. */
5478 ;
5492 location);
5497 }
5498 }
5499 \f
5500 /* A general induction variable (giv) is any quantity that is a linear
5501 function of a basic induction variable,
5502 i.e. giv = biv * mult_val + add_val.
5503 The coefficients can be any loop invariant quantity.
5504 A giv need not be computed directly from the biv;
5505 it can be computed by way of other givs. */
5507 /* Determine whether X computes a giv.
5508 If it does, return a nonzero value
5509 which is the benefit from eliminating the computation of X;
5510 set *SRC_REG to the register of the biv that it is computed from;
5511 set *ADD_VAL and *MULT_VAL to the coefficients,
5512 such that the value of X is biv * mult + add; */
5514 static int
5518 rtx x;
5526 {
5530 /* If this is an invariant, forget it, it isn't a giv. */
5541 {
5544 /* Since this is now an invariant and wasn't before, it must be a giv
5545 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5546 with. */
5553 /* This is equivalent to a BIV. */
5560 /* Either (plus (biv) (invar)) or
5561 (plus (mult (biv) (invar_1)) (invar_2)). */
5563 {
5566 }
5567 else
5568 {
5571 }
5576 /* ADD_VAL is zero. */
5584 }
5586 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5587 unless they are CONST_INT). */
5595 else
5598 /* Always return true if this is a giv so it will be detected as such,
5599 even if the benefit is zero or negative. This allows elimination
5600 of bivs that might otherwise not be eliminated. */
5602 }
5603 \f
5604 /* Given an expression, X, try to form it as a linear function of a biv.
5605 We will canonicalize it to be of the form
5606 (plus (mult (BIV) (invar_1))
5607 (invar_2))
5608 with possible degeneracies.
5610 The invariant expressions must each be of a form that can be used as a
5611 machine operand. We surround then with a USE rtx (a hack, but localized
5612 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5613 routine; it is the caller's responsibility to strip them.
5615 If no such canonicalization is possible (i.e., two biv's are used or an
5616 expression that is neither invariant nor a biv or giv), this routine
5617 returns 0.
5619 For a non-zero return, the result will have a code of CONST_INT, USE,
5620 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5622 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5627 static rtx
5630 rtx x;
5633 {
5638 rtx tem;
5640 /* If this is not an integer mode, or if we cannot do arithmetic in this
5641 mode, this can't be a giv. */
5648 {
5655 /* Put constant last, CONST_INT last if both constant. */
5663 /* Handle addition of zero, then addition of an invariant. */
5668 {
5671 /* Adding two invariants must result in an invariant, so enclose
5672 addition operation inside a USE and return it. */
5682 else
5691 /* biv + invar or mult + invar. Return sum. */
5695 /* (a + invar_1) + invar_2. Associate. */
5696 return
5702 arg1)),
5707 }
5709 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5710 MULT to reduce cases. */
5716 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5717 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5718 Recurse to associate the second PLUS. */
5723 return
5731 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5747 /* Handle "a - b" as "a + b * (-1)". */
5753 constm1_rtx)),
5762 /* Put constant last, CONST_INT last if both constant. */
5767 /* If second argument is not now constant, not giv. */
5771 /* Handle multiply by 0 or 1. */
5779 {
5781 /* biv * invar. Done. */
5785 /* Product of two constants. */
5789 /* invar * invar is a giv, but attempt to simplify it somehow. */
5795 {
5796 /* (invar_0 * invar_1) * invar_2. Associate. */
5803 arg1)),
5805 }
5806 /* Porpagate the MULT expressions to the intermost nodes. */
5808 {
5809 /* (invar_0 + invar_1) * invar_2. Distribute. */
5815 arg1),
5819 arg1)),
5821 }
5825 /* (a * invar_1) * invar_2. Associate. */
5831 arg1)),
5835 /* (a + invar_1) * invar_2. Distribute. */
5840 arg1),
5843 arg1)),
5848 }
5851 /* Shift by constant is multiply by power of two. */
5855 return
5864 /* "-a" is "a * (-1)" */
5870 /* "~a" is "-a - 1". Silly, but easy. */
5874 const1_rtx),
5878 /* Already in proper form for invariant. */
5884 /* Conditionally recognize extensions of simple IVs. After we've
5885 computed loop traversal counts and verified the range of the
5886 source IV, we'll reevaluate this as a GIV. */
5888 {
5891 {
5894 }
5895 }
5899 /* If this is a new register, we can't deal with it. */
5903 /* Check for biv or giv. */
5905 {
5909 {
5912 /* Form expression from giv and add benefit. Ensure this giv
5913 can derive another and subtract any needed adjustment if so. */
5915 /* Increasing the benefit here is risky. The only case in which it
5916 is arguably correct is if this is the only use of V. In other
5917 cases, this will artificially inflate the benefit of the current
5918 giv, and lead to suboptimal code. Thus, it is disabled, since
5919 potentially not reducing an only marginally beneficial giv is
5920 less harmful than reducing many givs that are not really
5921 beneficial. */
5922 {
5926 }
5939 {
5942 }
5943 else
5944 {
5947 }
5949 }
5952 do_default:
5953 /* If it isn't an induction variable, and it is invariant, we
5954 may be able to simplify things further by looking through
5955 the bits we just moved outside the loop. */
5957 {
5963 {
5964 /* Ok, we found a match. Substitute and simplify. */
5966 /* If we match another movable, we must use that, as
5967 this one is going away. */
5972 /* If consec is non-zero, this is a member of a group of
5973 instructions that were moved together. We handle this
5974 case only to the point of seeking to the last insn and
5975 looking for a REG_EQUAL. Fail if we don't find one. */
5977 {
5980 do
5981 {
5983 }
5989 }
5990 else
5991 {
5995 }
5998 {
5999 /* What we are most interested in is pointer
6000 arithmetic on invariants -- only take
6001 patterns we may be able to do something with. */
6007 {
6009 benefit);
6012 }
6017 {
6022 }
6023 }
6025 }
6026 }
6028 }
6030 /* Fall through to general case. */
6032 /* If invariant, return as USE (unless CONST_INT).
6033 Otherwise, not giv. */
6038 {
6047 }
6048 else
6050 }
6051 }
6053 /* This routine folds invariants such that there is only ever one
6054 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6056 static rtx
6059 {
6065 {
6068 }
6071 {
6074 }
6075 else
6076 {
6079 }
6080 }
6082 static rtx
6086 {
6088 {
6092 else
6095 }
6098 else
6101 }
6102 \f
6103 /* Help detect a giv that is calculated by several consecutive insns;
6104 for example,
6105 giv = biv * M
6106 giv = giv + A
6107 The caller has already identified the first insn P as having a giv as dest;
6108 we check that all other insns that set the same register follow
6109 immediately after P, that they alter nothing else,
6110 and that the result of the last is still a giv.
6112 The value is 0 if the reg set in P is not really a giv.
6113 Otherwise, the value is the amount gained by eliminating
6114 all the consecutive insns that compute the value.
6116 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6117 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6119 The coefficients of the ultimate giv value are stored in
6120 *MULT_VAL and *ADD_VAL. */
6122 static int
6127 rtx p;
6128 rtx src_reg;
6129 rtx dest_reg;
6134 {
6140 rtx temp;
6141 rtx set;
6143 /* Indicate that this is a giv so that we can update the value produced in
6144 each insn of the multi-insn sequence.
6146 This induction structure will be used only by the call to
6147 general_induction_var below, so we can allocate it on our stack.
6148 If this is a giv, our caller will replace the induct var entry with
6149 a new induction structure. */
6170 {
6174 /* If libcall, skip to end of call sequence. */
6185 /* Giv created by equivalent expression. */
6191 {
6195 count--;
6199 }
6201 {
6202 /* Allow insns that set something other than this giv to a
6203 constant. Such insns are needed on machines which cannot
6204 include long constants and should not disqualify a giv. */
6213 }
6214 }
6219 }
6220 \f
6221 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6222 represented by G1. If no such expression can be found, or it is clear that
6223 it cannot possibly be a valid address, 0 is returned.
6225 To perform the computation, we note that
6226 G1 = x * v + a and
6227 G2 = y * v + b
6228 where `v' is the biv.
6230 So G2 = (y/b) * G1 + (b - a*y/x).
6232 Note that MULT = y/x.
6234 Update: A and B are now allowed to be additive expressions such that
6235 B contains all variables in A. That is, computing B-A will not require
6236 subtracting variables. */
6238 static rtx
6241 {
6242 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6247 /* If MULT is not 1, we cannot handle A with non-constants, since we
6248 would then be required to subtract multiples of the registers in A.
6249 This is theoretically possible, and may even apply to some Fortran
6250 constructs, but it is a lot of work and we do not attempt it here. */
6255 /* In general these structures are sorted top to bottom (down the PLUS
6256 chain), but not left to right across the PLUS. If B is a higher
6257 order giv than A, we can strip one level and recurse. If A is higher
6258 order, we'll eventually bail out, but won't know that until the end.
6259 If they are the same, we'll strip one level around this loop. */
6262 {
6274 /* We matched: remove one reg completely. */
6277 /* An alternate match. */
6280 /* An alternate match. */
6282 else
6283 {
6284 /* Indicates an extra register in B. Strip one level from B and
6285 recurse, hoping B was the higher order expression. */
6290 }
6291 }
6293 /* Here we are at the last level of A, go through the cases hoping to
6294 get rid of everything but a constant. */
6297 {
6310 }
6312 {
6314 }
6316 {
6317 return simplify_gen_binary (MINUS, GET_MODE (b) != VOIDmode ? GET_MODE (b) : GET_MODE (a), const0_rtx, a);
6318 }
6320 {
6325 else
6327 }
6332 }
6334 rtx
6337 {
6340 /* The value that G1 will be multiplied by must be a constant integer. Also,
6341 the only chance we have of getting a valid address is if b*c/a (see above
6342 for notation) is also an integer. */
6345 {
6350 }
6353 else
6354 {
6355 /* ??? Find out if the one is a multiple of the other? */
6357 }
6361 {
6362 /* Failed. If we've got a multiplication factor between G1 and G2,
6363 scale G1's addend and try again. */
6365 {
6369 {
6370 HOST_WIDE_INT m;
6374 }
6375 else
6376 {
6378 mult);
6379 }
6382 }
6383 }
6387 /* Form simplified final result. */
6392 else
6397 else
6398 {
6401 {
6405 }
6408 }
6409 }
6410 \f
6411 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6412 represented by G1. This indicates that G2 should be combined with G1 and
6413 that G2 can use (either directly or via an address expression) a register
6414 used to represent G1. */
6416 static rtx
6419 {
6422 /* With the introduction of ext dependant givs, we must care for modes.
6423 G2 must not use a wider mode than G1. */
6433 /* If these givs are identical, they can be combined. We use the results
6434 of express_from because the addends are not in a canonical form, so
6435 rtx_equal_p is a weaker test. */
6436 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6437 combination to be the other way round. */
6440 {
6442 }
6444 /* If G2 can be expressed as a function of G1 and that function is valid
6445 as an address and no more expensive than using a register for G2,
6446 the expression of G2 in terms of G1 can be used. */
6450 /* ??? Looses, especially with -fforce-addr, where *g2->location
6451 will always be a register, and so anything more complicated
6452 gets discarded. */
6453 #if 0
6454 #ifdef ADDRESS_COST
6456 #else
6458 #endif
6459 #endif
6460 )
6461 {
6463 }
6466 }
6467 \f
6468 /* Check each extension dependant giv in this class to see if its
6469 root biv is safe from wrapping in the interior mode, which would
6470 make the giv illegal. */
6472 static void
6476 {
6479 HOST_WIDE_INT start_val;
6484 /* Make sure the iteration data is available. We must have
6485 constants in order to be certain of no overflow. */
6486 /* ??? An unknown iteration count with an increment of +-1
6487 combined with friendly exit tests of against an invariant
6488 value is also ameanable to optimization. Not implemented. */
6494 /* Make sure the host can represent the arithmetic. */
6496 {
6498 HOST_WIDE_INT s_end_val;
6510 /* Check for host arithmatic overflow. */
6512 {
6514 HOST_WIDE_INT s_max;
6521 /* Check zero extension of biv ok. */
6523 /* Check for host arithmatic overflow. */
6524 && (neg_incr
6527 /* Check for target arithmetic overflow. */
6528 && (neg_incr
6531 {
6533 }
6535 /* Check sign extension of biv ok. */
6536 /* ??? While it is true that overflow with signed and pointer
6537 arithmetic is undefined, I fear too many programmers don't
6538 keep this fact in mind -- myself included on occasion.
6539 So leave alone with the signed overflow optimizations. */
6541 /* Check for host arithmatic overflow. */
6542 && (neg_incr
6545 /* Check for target arithmetic overflow. */
6546 && (neg_incr
6549 {
6551 }
6552 }
6553 }
6555 /* Invalidate givs that fail the tests. */
6558 {
6563 {
6572 /* We don't know whether this value is being used as either
6573 signed or unsigned, so to safely truncate we must satisfy
6574 both. The initial check here verifies the BIV itself;
6575 once that is successful we may check its range wrt the
6576 derived GIV. */
6578 {
6582 /* We know from the above that both endpoints are nonnegative,
6583 and that there is no wrapping. Verify that both endpoints
6584 are within the (signed) range of the outer mode. */
6587 }
6592 }
6595 {
6597 {
6601 }
6602 }
6603 else
6604 {
6606 {
6611 else
6612 {
6617 else
6619 }
6624 }
6626 }
6627 }
6628 }
6630 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6632 rtx
6635 rtx value;
6636 {
6642 /* Recall that check_ext_dependant_givs verified that the known bounds
6643 of a biv did not overflow or wrap with respect to the extension for
6644 the giv. Therefore, constants need no additional adjustment. */
6648 /* Otherwise, we must adjust the value to compensate for the
6649 differing modes of the biv and the giv. */
6651 }
6652 \f
6653 struct combine_givs_stats
6654 {
6657 };
6659 static int
6663 {
6670 /* Stabilize the sort. */
6674 }
6676 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6677 any other. If so, point SAME to the giv combined with and set NEW_REG to
6678 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6679 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6681 static void
6685 {
6686 /* Additional benefit to add for being combined multiple times. */
6694 /* Count givs, because bl->giv_count is incorrect here. */
6698 giv_count++;
6700 giv_array
6711 {
6713 rtx single_use;
6718 /* If a DEST_REG GIV is used only once, do not allow it to combine
6719 with anything, for in doing so we will gain nothing that cannot
6720 be had by simply letting the GIV with which we would have combined
6721 to be reduced on its own. The losage shows up in particular with
6722 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6723 be seen elsewhere as well. */
6730 /* Add an additional weight for zero addends. */
6735 {
6736 rtx this_combine;
6741 {
6744 }
6745 }
6747 }
6749 /* Iterate, combining until we can't. */
6750 restart:
6754 {
6757 {
6763 }
6765 }
6768 {
6774 /* If it has already been combined, skip. */
6779 {
6782 /* If it has already been combined, skip. */
6784 {
6794 /* ??? The new final_[bg]iv_value code does a much better job
6795 of finding replaceable giv's, and hence this code may no
6796 longer be necessary. */
6800 /* To help optimize the next set of combinations, remove
6801 this giv from the benefits of other potential mates. */
6803 {
6807 }
6814 }
6815 }
6817 /* To help optimize the next set of combinations, remove
6818 this giv from the benefits of other potential mates. */
6820 {
6822 {
6826 }
6830 /* We've finished with this giv, and everything it touched.
6831 Restart the combination so that proper weights for the
6832 rest of the givs are properly taken into account. */
6833 /* ??? Ideally we would compact the arrays at this point, so
6834 as to not cover old ground. But sanely compacting
6835 can_combine is tricky. */
6837 }
6838 }
6840 /* Clean up. */
6843 }
6844 \f
6845 /* Generate sequence for REG = B * M + A. */
6847 static rtx
6853 {
6854 rtx seq;
6855 rtx result;
6858 /* Use unsigned arithmetic. */
6866 }
6869 /* Update registers created in insn sequence SEQ. */
6871 static void
6874 rtx seq;
6875 {
6876 /* Update register info for alias analysis. */
6879 {
6882 {
6886 }
6887 }
6888 else
6889 {
6893 }
6894 }
6897 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
6899 void
6906 basic_block before_bb;
6907 rtx before_insn;
6908 {
6909 rtx seq;
6912 {
6915 }
6917 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6920 /* Increase the lifetime of any invariants moved further in code. */
6927 /* It is possible that the expansion created lots of new registers.
6928 Iterate over the sequence we just created and record them all. */
6930 }
6933 /* Emit insns in loop pre-header to set REG = B * M + A. */
6935 void
6942 {
6943 rtx seq;
6945 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6948 /* Increase the lifetime of any invariants moved further in code.
6949 ???? Is this really necessary? */
6956 /* It is possible that the expansion created lots of new registers.
6957 Iterate over the sequence we just created and record them all. */
6959 }
6962 /* Emit insns after loop to set REG = B * M + A. */
6964 void
6971 {
6972 rtx seq;
6974 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6979 /* It is possible that the expansion created lots of new registers.
6980 Iterate over the sequence we just created and record them all. */
6982 }
6986 /* Similar to gen_add_mult, but compute cost rather than generating
6987 sequence. */
6989 static int
6995 {
7005 {
7010 }
7013 }
7014 \f
7015 /* Test whether A * B can be computed without
7016 an actual multiply insn. Value is 1 if so. */
7018 static int
7020 rtx a;
7021 rtx b;
7022 {
7024 rtx tmp;
7027 /* If only one is constant, make it B. */
7031 /* If first constant, both constant, so don't need multiply. */
7035 /* If second not constant, neither is constant, so would need multiply. */
7039 /* One operand is constant, so might not need multiply insn. Generate the
7040 code for the multiply and see if a call or multiply, or long sequence
7041 of insns is generated. */
7049 {
7054 else
7056 {
7065 {
7068 }
7069 }
7070 }
7080 }
7081 \f
7082 /* Check to see if loop can be terminated by a "decrement and branch until
7083 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7084 Also try reversing an increment loop to a decrement loop
7085 to see if the optimization can be performed.
7086 Value is nonzero if optimization was performed. */
7088 /* This is useful even if the architecture doesn't have such an insn,
7089 because it might change a loops which increments from 0 to n to a loop
7090 which decrements from n to 0. A loop that decrements to zero is usually
7091 faster than one that increments from zero. */
7093 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7094 such as approx_final_value, biv_total_increment, loop_iterations, and
7095 final_[bg]iv_value. */
7097 static int
7101 {
7106 rtx reg;
7107 rtx jump_label;
7108 rtx final_value;
7109 rtx start_value;
7110 rtx new_add_val;
7111 rtx comparison;
7112 rtx before_comparison;
7113 rtx p;
7114 rtx jump;
7115 rtx first_compare;
7120 /* If last insn is a conditional branch, and the insn before tests a
7121 register value, try to optimize it. Otherwise, we can't do anything. */
7130 /* Try to compute whether the compare/branch at the loop end is one or
7131 two instructions. */
7137 else
7140 {
7141 /* If more than one condition is present to control the loop, then
7142 do not proceed, as this function does not know how to rewrite
7143 loop tests with more than one condition.
7145 Look backwards from the first insn in the last comparison
7146 sequence and see if we've got another comparison sequence. */
7148 rtx jump1;
7152 }
7154 /* Check all of the bivs to see if the compare uses one of them.
7155 Skip biv's set more than once because we can't guarantee that
7156 it will be zero on the last iteration. Also skip if the biv is
7157 used between its update and the test insn. */
7160 {
7165 first_compare))
7167 }
7172 /* Look for the case where the basic induction variable is always
7173 nonnegative, and equals zero on the last iteration.
7174 In this case, add a reg_note REG_NONNEG, which allows the
7175 m68k DBRA instruction to be used. */
7183 {
7184 /* Initial value must be greater than 0,
7185 init_val % -dec_value == 0 to ensure that it equals zero on
7186 the last iteration */
7192 {
7193 /* register always nonnegative, add REG_NOTE to branch */
7201 }
7203 /* If the decrement is 1 and the value was tested as >= 0 before
7204 the loop, then we can safely optimize. */
7206 {
7219 {
7227 }
7228 }
7229 }
7232 {
7233 /* Try to change inc to dec, so can apply above optimization. */
7234 /* Can do this if:
7235 all registers modified are induction variables or invariant,
7236 all memory references have non-overlapping addresses
7237 (obviously true if only one write)
7238 allow 2 insns for the compare/jump at the end of the loop. */
7239 /* Also, we must avoid any instructions which use both the reversed
7240 biv and another biv. Such instructions will fail if the loop is
7241 reversed. We meet this condition by requiring that either
7242 no_use_except_counting is true, or else that there is only
7243 one biv. */
7245 /* 1 if the iteration var is used only to count iterations. */
7247 /* 1 if the loop has no memory store, or it has a single memory store
7248 which is reversible. */
7252 {
7255 /* If there are no givs for this biv, and the only exit is the
7256 fall through at the end of the loop, then
7257 see if perhaps there are no uses except to count. */
7261 {
7266 /* An insn that sets the biv is okay. */
7267 ;
7271 {
7272 /* If either of these insns uses the biv and sets a pseudo
7273 that has more than one usage, then the biv has uses
7274 other than counting since it's used to derive a value
7275 that is used more than one time. */
7277 regs);
7279 {
7282 }
7283 }
7285 {
7288 }
7289 }
7290 }
7293 /* No need to worry about MEMs. */
7294 ;
7296 {
7301 /* If the loop has a single store, and the destination address is
7302 invariant, then we can't reverse the loop, because this address
7303 might then have the wrong value at loop exit.
7304 This would work if the source was invariant also, however, in that
7305 case, the insn should have been moved out of the loop. */
7308 {
7311 reversible_mem_store
7318 /* If the store depends on a register that is set after the
7319 store, it depends on the initial value, and is thus not
7320 reversible. */
7322 {
7329 }
7330 }
7331 }
7332 else
7335 /* This code only acts for innermost loops. Also it simplifies
7336 the memory address check by only reversing loops with
7337 zero or one memory access.
7338 Two memory accesses could involve parts of the same array,
7339 and that can't be reversed.
7340 If the biv is used only for counting, than we don't need to worry
7341 about all these things. */
7346 && reversible_mem_store
7351 {
7352 rtx tem;
7354 /* Loop can be reversed. */
7358 /* Now check other conditions:
7360 The increment must be a constant, as must the initial value,
7361 and the comparison code must be LT.
7363 This test can probably be improved since +/- 1 in the constant
7364 can be obtained by changing LT to LE and vice versa; this is
7365 confusing. */
7368 /* for constants, LE gets turned into LT */
7372 {
7383 comparison_const_width
7385 else
7386 comparison_const_width
7390 comparison_sign_mask
7393 /* If the comparison value is not a loop invariant, then we
7394 can not reverse this loop.
7396 ??? If the insns which initialize the comparison value as
7397 a whole compute an invariant result, then we could move
7398 them out of the loop and proceed with loop reversal. */
7406 /* Normalize the initial value if it is an integer and
7407 has no other use except as a counter. This will allow
7408 a few more loops to be reversed. */
7412 {
7414 /* The code below requires comparison_val to be a multiple
7415 of add_val in order to do the loop reversal, so
7416 round up comparison_val to a multiple of add_val.
7417 Since comparison_value is constant, we know that the
7418 current comparison code is LT. */
7420 comparison_val
7422 /* We postpone overflow checks for COMPARISON_VAL here;
7423 even if there is an overflow, we might still be able to
7424 reverse the loop, if converting the loop exit test to
7425 NE is possible. */
7427 }
7429 /* First check if we can do a vanilla loop reversal. */
7431 /* If we have a decrement_and_branch_on_count,
7432 prefer the NE test, since this will allow that
7433 instruction to be generated. Note that we must
7434 use a vanilla loop reversal if the biv is used to
7435 calculate a giv or has a non-counting use. */
7436 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7437 && defined (HAVE_decrement_and_branch_on_count)
7441 #endif
7443 /* Now do postponed overflow checks on COMPARISON_VAL. */
7446 {
7447 /* Register will always be nonnegative, with value
7448 0 on last iteration */
7452 }
7456 {
7459 }
7460 else
7466 /* If the initial value is not zero, or if the comparison
7467 value is not an exact multiple of the increment, then we
7468 can not reverse this loop. */
7471 {
7474 }
7475 else
7476 {
7479 }
7483 /* Reset these in case we normalized the initial value
7484 and comparison value above. */
7487 {
7489 final_value
7491 }
7494 /* Save some info needed to produce the new insns. */
7501 /* Set start_value; if this is not a CONST_INT, we need
7502 to generate a SUB.
7503 Initialize biv to start_value before loop start.
7504 The old initializing insn will be deleted as a
7505 dead store by flow.c. */
7508 {
7511 }
7513 {
7516 enum insn_code icode
7525 start_value
7532 }
7534 {
7536 enum insn_code icode
7544 start_value
7548 initial_value)));
7549 }
7550 else
7551 /* We could handle the other cases too, but it'll be
7552 better to have a testcase first. */
7555 /* We may not have a single insn which can increment a reg, so
7556 create a sequence to hold all the insns from expand_inc. */
7565 /* Update biv info to reflect its new status. */
7570 /* Update loop info. */
7579 /* Inc LABEL_NUSES so that delete_insn will
7580 not delete the label. */
7583 /* Emit an insn after the end of the loop to set the biv's
7584 proper exit value if it is used anywhere outside the loop. */
7590 /* Delete compare/branch at end of loop. */
7595 /* Add new compare/branch insn at end of loop. */
7607 ;
7613 {
7615 {
7616 /* Increment of LABEL_NUSES done above. */
7617 /* Register is now always nonnegative,
7618 so add REG_NONNEG note to the branch. */
7621 }
7623 }
7625 /* No insn may reference both the reversed and another biv or it
7626 will fail (see comment near the top of the loop reversal
7627 code).
7628 Earlier on, we have verified that the biv has no use except
7629 counting, or it is the only biv in this function.
7630 However, the code that computes no_use_except_counting does
7631 not verify reg notes. It's possible to have an insn that
7632 references another biv, and has a REG_EQUAL note with an
7633 expression based on the reversed biv. To avoid this case,
7634 remove all REG_EQUAL notes based on the reversed biv
7635 here. */
7638 {
7641 /* If this is a set of a GIV based on the reversed biv, any
7642 REG_EQUAL notes should still be correct. */
7649 {
7654 else
7656 }
7657 }
7659 /* Mark that this biv has been reversed. Each giv which depends
7660 on this biv, and which is also live past the end of the loop
7661 will have to be fixed up. */
7666 {
7670 else
7672 }
7675 }
7676 }
7677 }
7680 }
7681 \f
7682 /* Verify whether the biv BL appears to be eliminable,
7683 based on the insns in the loop that refer to it.
7685 If ELIMINATE_P is non-zero, actually do the elimination.
7687 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7688 determine whether invariant insns should be placed inside or at the
7689 start of the loop. */
7691 static int
7697 {
7700 rtx p;
7702 /* Scan all insns in the loop, stopping if we find one that uses the
7703 biv in a way that we cannot eliminate. */
7706 {
7711 /* If this is a libcall that sets a giv, skip ahead to its end. */
7713 {
7717 {
7722 {
7729 }
7730 }
7731 }
7736 {
7742 }
7743 }
7746 {
7751 }
7754 }
7755 \f
7756 /* INSN and REFERENCE are instructions in the same insn chain.
7757 Return non-zero if INSN is first. */
7759 int
7762 {
7766 {
7767 /* Start with test for not first so that INSN == REFERENCE yields not
7768 first. */
7774 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7775 previous insn, hence the <= comparison below does not work if
7776 P is a note. */
7787 }
7788 }
7790 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7791 the offset that we have to take into account due to auto-increment /
7792 div derivation is zero. */
7793 static int
7796 rtx insn;
7797 {
7798 /* If the giv V had the auto-inc address optimization applied
7799 to it, and INSN occurs between the giv insn and the biv
7800 insn, then we'd have to adjust the value used here.
7801 This is rare, so we don't bother to make this possible. */
7810 }
7812 /* If BL appears in X (part of the pattern of INSN), see if we can
7813 eliminate its use. If so, return 1. If not, return 0.
7815 If BIV does not appear in X, return 1.
7817 If ELIMINATE_P is non-zero, actually do the elimination.
7818 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
7819 Depending on how many items have been moved out of the loop, it
7820 will either be before INSN (when WHERE_INSN is non-zero) or at the
7821 start of the loop (when WHERE_INSN is zero). */
7823 static int
7829 basic_block where_bb;
7830 rtx where_insn;
7831 {
7837 #ifdef HAVE_cc0
7839 #endif
7845 {
7847 /* If we haven't already been able to do something with this BIV,
7848 we can't eliminate it. */
7854 /* If this sets the BIV, it is not a problem. */
7858 /* If this is an insn that defines a giv, it is also ok because
7859 it will go away when the giv is reduced. */
7864 #ifdef HAVE_cc0
7866 {
7867 /* Can replace with any giv that was reduced and
7868 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7869 Require a constant for MULT_VAL, so we know it's nonzero.
7870 ??? We disable this optimization to avoid potential
7871 overflows. */
7879 {
7886 /* If the giv has the opposite direction of change,
7887 then reverse the comparison. */
7891 else
7894 /* We can probably test that giv's reduced reg. */
7897 }
7899 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7900 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7901 Require a constant for MULT_VAL, so we know it's nonzero.
7902 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7903 overflow problem. */
7915 {
7922 /* If the giv has the opposite direction of change,
7923 then reverse the comparison. */
7927 else
7931 /* Replace biv with the giv's reduced register. */
7936 /* Insn doesn't support that constant or invariant. Copy it
7937 into a register (it will be a loop invariant.) */
7941 where_insn);
7943 /* Substitute the new register for its invariant value in
7944 the compare expression. */
7948 }
7949 }
7950 #endif
7957 /* See if either argument is the biv. */
7962 else
7966 {
7967 /* First try to replace with any giv that has constant positive
7968 mult_val and constant add_val. We might be able to support
7969 negative mult_val, but it seems complex to do it in general. */
7981 {
7988 /* Replace biv with the giv's reduced reg. */
7991 /* If all constants are actually constant integers and
7992 the derived constant can be directly placed in the COMPARE,
7993 do so. */
7997 {
8002 }
8003 else
8004 {
8005 /* Otherwise, load it into a register. */
8011 }
8014 }
8016 /* Look for giv with positive constant mult_val and nonconst add_val.
8017 Insert insns to calculate new compare value.
8018 ??? Turn this off due to possible overflow. */
8026 {
8027 rtx tem;
8037 /* Replace biv with giv's reduced register. */
8041 /* Compute value to compare against. */
8045 /* Use it in this insn. */
8049 }
8050 }
8052 {
8054 {
8055 /* Look for giv with constant positive mult_val and nonconst
8056 add_val. Insert insns to compute new compare value.
8057 ??? Turn this off due to possible overflow. */
8064 {
8065 rtx tem;
8075 /* Replace biv with giv's reduced register. */
8079 /* Compute value to compare against. */
8086 }
8087 }
8089 /* This code has problems. Basically, you can't know when
8090 seeing if we will eliminate BL, whether a particular giv
8091 of ARG will be reduced. If it isn't going to be reduced,
8092 we can't eliminate BL. We can try forcing it to be reduced,
8093 but that can generate poor code.
8095 The problem is that the benefit of reducing TV, below should
8096 be increased if BL can actually be eliminated, but this means
8097 we might have to do a topological sort of the order in which
8098 we try to process biv. It doesn't seem worthwhile to do
8099 this sort of thing now. */
8101 #if 0
8102 /* Otherwise the reg compared with had better be a biv. */
8107 /* Look for a pair of givs, one for each biv,
8108 with identical coefficients. */
8110 {
8122 {
8129 /* Replace biv with its giv's reduced reg. */
8131 /* Replace other operand with the other giv's
8132 reduced reg. */
8135 }
8136 }
8137 #endif
8138 }
8140 /* If we get here, the biv can't be eliminated. */
8144 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8145 biv is used in it, since it will be replaced. */
8153 }
8155 /* See if any subexpression fails elimination. */
8158 {
8160 {
8173 }
8174 }
8177 }
8178 \f
8179 /* Return nonzero if the last use of REG
8180 is in an insn following INSN in the same basic block. */
8182 static int
8184 rtx reg;
8185 rtx insn;
8186 {
8187 rtx n;
8191 {
8194 }
8196 }
8197 \f
8198 /* Called via `note_stores' to record the initial value of a biv. Here we
8199 just record the location of the set and process it later. */
8201 static void
8203 rtx dest;
8204 rtx set;
8206 {
8217 /* If this is the first set found, record it. */
8219 {
8222 }
8223 }
8224 \f
8225 /* If any of the registers in X are "old" and currently have a last use earlier
8226 than INSN, update them to have a last use of INSN. Their actual last use
8227 will be the previous insn but it will not have a valid uid_luid so we can't
8228 use it. X must be a source expression only. */
8230 static void
8232 rtx x;
8233 rtx insn;
8234 {
8235 /* Check for the case where INSN does not have a valid luid. In this case,
8236 there is no need to modify the regno_last_uid, as this can only happen
8237 when code is inserted after the loop_end to set a pseudo's final value,
8238 and hence this insn will never be the last use of x.
8239 ???? This comment is not correct. See for example loop_givs_reduce.
8240 This may insert an insn before another new insn. */
8244 {
8246 }
8247 else
8248 {
8252 {
8258 }
8259 }
8260 }
8261 \f
8262 /* Given an insn INSN and condition COND, return the condition in a
8263 canonical form to simplify testing by callers. Specifically:
8265 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8266 (2) Both operands will be machine operands; (cc0) will have been replaced.
8267 (3) If an operand is a constant, it will be the second operand.
8268 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8269 for GE, GEU, and LEU.
8271 If the condition cannot be understood, or is an inequality floating-point
8272 comparison which needs to be reversed, 0 will be returned.
8274 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8276 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8277 insn used in locating the condition was found. If a replacement test
8278 of the condition is desired, it should be placed in front of that
8279 insn and we will be sure that the inputs are still valid.
8281 If WANT_REG is non-zero, we wish the condition to be relative to that
8282 register, if possible. Therefore, do not canonicalize the condition
8283 further. */
8285 rtx
8287 rtx insn;
8288 rtx cond;
8291 rtx want_reg;
8292 {
8295 rtx set;
8296 rtx tem;
8308 {
8311 }
8316 /* If we are comparing a register with zero, see if the register is set
8317 in the previous insn to a COMPARE or a comparison operation. Perform
8318 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8319 in cse.c */
8324 {
8325 /* Set non-zero when we find something of interest. */
8328 #ifdef HAVE_cc0
8329 /* If comparison with cc0, import actual comparison from compare
8330 insn. */
8332 {
8343 }
8344 #endif
8346 /* If this is a COMPARE, pick up the two things being compared. */
8348 {
8352 }
8356 /* Go back to the previous insn. Stop if it is not an INSN. We also
8357 stop if it isn't a single set or if it has a REG_INC note because
8358 we don't want to bother dealing with it. */
8366 /* If this is setting OP0, get what it sets it to if it looks
8367 relevant. */
8369 {
8372 /* ??? We may not combine comparisons done in a CCmode with
8373 comparisons not done in a CCmode. This is to aid targets
8374 like Alpha that have an IEEE compliant EQ instruction, and
8375 a non-IEEE compliant BEQ instruction. The use of CCmode is
8376 actually artificial, simply to prevent the combination, but
8377 should not affect other platforms.
8379 However, we must allow VOIDmode comparisons to match either
8380 CCmode or non-CCmode comparison, because some ports have
8381 modeless comparisons inside branch patterns.
8383 ??? This mode check should perhaps look more like the mode check
8384 in simplify_comparison in combine. */
8392 && (STORE_FLAG_VALUE
8395 #ifdef FLOAT_STORE_FLAG_VALUE
8398 && (REAL_VALUE_NEGATIVE
8400 #endif
8401 ))
8412 && (STORE_FLAG_VALUE
8415 #ifdef FLOAT_STORE_FLAG_VALUE
8418 && (REAL_VALUE_NEGATIVE
8420 #endif
8421 ))
8427 {
8428 /* We might have reversed a LT to get a GE here. But this wasn't
8429 actually the comparison of data, so we don't flag that we
8430 have had to reverse the condition. */
8434 }
8435 else
8437 }
8440 /* If this sets OP0, but not directly, we have to give up. */
8444 {
8448 {
8454 }
8459 }
8460 }
8462 /* If constant is first, put it last. */
8466 /* If OP0 is the result of a comparison, we weren't able to find what
8467 was really being compared, so fail. */
8471 /* Canonicalize any ordered comparison with integers involving equality
8472 if we can do computations in the relevant mode and we do not
8473 overflow. */
8478 {
8481 unsigned HOST_WIDE_INT max_val
8485 {
8491 /* When cross-compiling, const_val might be sign-extended from
8492 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8512 }
8513 }
8515 /* If this was floating-point and we reversed anything other than an
8516 EQ or NE or (UN)ORDERED, return zero. */
8518 && did_reverse_condition
8520 && ! flag_fast_math
8524 #ifdef HAVE_cc0
8525 /* Never return CC0; return zero instead. */
8528 #endif
8531 }
8533 /* Given a jump insn JUMP, return the condition that will cause it to branch
8534 to its JUMP_LABEL. If the condition cannot be understood, or is an
8535 inequality floating-point comparison which needs to be reversed, 0 will
8536 be returned.
8538 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8539 insn used in locating the condition was found. If a replacement test
8540 of the condition is desired, it should be placed in front of that
8541 insn and we will be sure that the inputs are still valid. */
8543 rtx
8545 rtx jump;
8547 {
8548 rtx cond;
8550 rtx set;
8552 /* If this is not a standard conditional jump, we can't parse it. */
8560 /* If this branches to JUMP_LABEL when the condition is false, reverse
8561 the condition. */
8562 reverse
8567 }
8569 /* Similar to above routine, except that we also put an invariant last
8570 unless both operands are invariants. */
8572 rtx
8575 rtx x;
8576 {
8586 }
8588 /* Scan the function and determine whether it has indirect (computed) jumps.
8590 This is taken mostly from flow.c; similar code exists elsewhere
8591 in the compiler. It may be useful to put this into rtlanal.c. */
8592 static int
8594 rtx start;
8595 {
8596 rtx insn;
8603 }
8605 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8606 documentation for LOOP_MEMS for the definition of `appropriate'.
8607 This function is called from prescan_loop via for_each_rtx. */
8609 static int
8613 {
8622 {
8627 /* We're not interested in MEMs that are only clobbered. */
8631 /* We're not interested in the MEM associated with a
8632 CONST_DOUBLE, so there's no need to traverse into this. */
8636 /* We're not interested in any MEMs that only appear in notes. */
8640 /* This is not a MEM. */
8642 }
8644 /* See if we've already seen this MEM. */
8647 {
8649 /* The modes of the two memory accesses are different. If
8650 this happens, something tricky is going on, and we just
8651 don't optimize accesses to this MEM. */
8655 }
8657 /* Resize the array, if necessary. */
8659 {
8662 else
8668 }
8670 /* Actually insert the MEM. */
8672 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8673 because we can't put it in a register. We still store it in the
8674 table, though, so that if we see the same address later, but in a
8675 non-BLK mode, we'll not think we can optimize it at that point. */
8681 }
8684 /* Allocate REGS->ARRAY or reallocate it if it is too small.
8686 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
8687 register that is modified by an insn between FROM and TO. If the
8688 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
8689 more, stop incrementing it, to avoid overflow.
8691 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
8692 register I is used, if it is only used once. Otherwise, it is set
8693 to 0 (for no uses) or const0_rtx for more than one use. This
8694 parameter may be zero, in which case this processing is not done.
8696 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
8697 optimize register I.
8699 Store in *COUNT_PTR the number of actual instructions
8700 in the loop. We use this to decide what is worth moving out. */
8702 static void
8707 {
8710 /* last_set[n] is nonzero iff reg n has been set in the current
8711 basic block. In that case, it is the insn that last set reg n. */
8713 rtx insn;
8720 /* Grow the regs array if not allocated or too small. */
8722 {
8728 /* Zero the new elements. */
8731 }
8733 /* Clear previously scanned fields but do not clear n_times_set. */
8735 {
8739 }
8743 /* Scan the loop, recording register usage. */
8746 {
8748 {
8751 /* Record registers that have exactly one use. */
8754 /* Include uses in REG_EQUAL notes. */
8762 {
8766 last_set);
8767 }
8768 }
8772 }
8775 {
8778 }
8780 #ifdef AVOID_CCMODE_COPIES
8781 /* Don't try to move insns which set CC registers if we should not
8782 create CCmode register copies. */
8786 #endif
8788 /* Set regs->array[I].n_times_set for the new registers. */
8794 }
8797 /* Move MEMs into registers for the duration of the loop. */
8799 static void
8802 {
8807 rtx p;
8809 rtx end_label;
8810 /* Nonzero if the next instruction may never be executed. */
8817 /* We cannot use next_label here because it skips over normal insns. */
8822 /* Check to see if it's possible that some instructions in the loop are
8823 never executed. Also check if there is a goto out of the loop other
8824 than right after the end of the loop. */
8828 {
8832 /* If we enter the loop in the middle, and scan
8833 around to the beginning, don't set maybe_never
8834 for that. This must be an unconditional jump,
8835 otherwise the code at the top of the loop might
8836 never be executed. Unconditional jumps are
8837 followed a by barrier then loop end. */
8842 {
8843 /* If this is a jump outside of the loop but not right
8844 after the end of the loop, we would have to emit new fixup
8845 sequences for each such label. */
8853 /* Something complicated. */
8855 else
8856 /* If there are any more instructions in the loop, they
8857 might not be reached. */
8859 }
8862 }
8864 /* Find start of the extended basic block that enters the loop. */
8868 ;
8872 /* Build table of mems that get set to constant values before the
8873 loop. */
8877 /* Actually move the MEMs. */
8879 {
8880 regset_head load_copies;
8881 regset_head store_copies;
8883 rtx reg;
8885 rtx mem_list_entry;
8889 /* There's no telling whether or not MEM is modified. */
8892 /* Go through the MEMs written to in the loop to see if this
8893 one is aliased by one of them. */
8896 {
8901 {
8902 /* MEM is indeed aliased by this store. */
8905 }
8907 }
8913 /* If this MEM is written to, we must be sure that there
8914 are no reads from another MEM that aliases this one. */
8916 {
8920 {
8924 VOIDmode,
8926 rtx_varies_p))
8927 {
8928 /* It's not safe to hoist loop_info->mems[i] out of
8929 the loop because writes to it might not be
8930 seen by reads from loop_info->mems[j]. */
8933 }
8934 }
8935 }
8938 /* We can't access the MEM outside the loop; it might
8939 cause a trap that wouldn't have happened otherwise. */
8943 /* We thought we were going to lift this MEM out of the
8944 loop, but later discovered that we could not. */
8950 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
8951 order to keep scan_loop from moving stores to this MEM
8952 out of the loop just because this REG is neither a
8953 user-variable nor used in the loop test. */
8958 /* Now, replace all references to the MEM with the
8959 corresponding pesudos. */
8964 {
8966 {
8967 rtx set;
8971 /* See if this copies the mem into a register that isn't
8972 modified afterwards. We'll try to do copy propagation
8973 a little further on. */
8975 /* @@@ This test is _way_ too conservative. */
8976 && ! maybe_never
8984 /* See if this copies the mem from a register that isn't
8985 modified afterwards. We'll try to remove the
8986 redundant copy later on by doing a little register
8987 renaming and copy propagation. This will help
8988 to untangle things for the BIV detection code. */
8990 && ! maybe_never
8998 /* Replace the memory reference with the shadow register. */
9001 }
9006 }
9009 /* We couldn't replace all occurrences of the MEM. */
9011 else
9012 {
9013 /* Load the memory immediately before LOOP->START, which is
9014 the NOTE_LOOP_BEG. */
9016 rtx set;
9022 {
9026 {
9030 /* Extending hard register lifetimes cuases crash
9031 on SRC targets. Doing so on non-SRC is
9032 probably also not good idea, since we most
9033 probably have pseudoregister equivalence as
9034 well. */
9037 }
9038 /* Use the constant equivalence if that is cheap enough. */
9044 {
9047 }
9049 /* If best_equiv is nonzero, we know that MEM is set to a
9050 constant or register before the loop. We will use this
9051 knowledge to initialize the shadow register with that
9052 constant or reg rather than by loading from MEM. */
9055 }
9064 {
9066 {
9069 }
9071 /* Store the memory immediately after END, which is
9072 the NOTE_LOOP_END. */
9075 }
9078 {
9083 }
9085 /* Attempt a bit of copy propagation. This helps untangle the
9086 data flow, and enables {basic,general}_induction_var to find
9087 more bivs/givs. */
9088 EXECUTE_IF_SET_IN_REG_SET
9090 {
9092 });
9095 EXECUTE_IF_SET_IN_REG_SET
9097 {
9099 });
9101 }
9102 }
9105 {
9106 /* Now, we need to replace all references to the previous exit
9107 label with the new one. */
9108 rtx_pair rr;
9113 {
9116 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9117 field. This is not handled by for_each_rtx because it doesn't
9118 handle unprinted ('0') fields. We need to update JUMP_LABEL
9119 because the immediately following unroll pass will use it.
9120 replace_label would not work anyways, because that only handles
9121 LABEL_REFs. */
9124 }
9125 }
9128 }
9130 /* For communication between note_reg_stored and its caller. */
9131 struct note_reg_stored_arg
9132 {
9134 rtx reg;
9135 };
9137 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9138 is equal to ARG. */
9139 static void
9143 {
9147 }
9149 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9150 There must be exactly one insn that sets this pseudo; it will be
9151 deleted if all replacements succeed and we can prove that the register
9152 is not used after the loop. */
9154 static void
9157 rtx replacement;
9159 {
9160 /* This is the reg that we are copying from. */
9163 rtx insn;
9164 /* These help keep track of whether we replaced all uses of the reg. */
9171 {
9172 rtx set;
9174 /* Only substitute within one extended basic block from the initializing
9175 insn. */
9182 /* Is this the initializing insn? */
9187 {
9194 }
9196 /* Only substitute after seeing the initializing insn. */
9198 {
9205 /* Stop replacing when REPLACEMENT is modified. */
9211 }
9212 }
9216 {
9220 {
9226 }
9229 }
9230 }
9232 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9233 loop LOOP if the order of the sets of these registers can be
9234 swapped. There must be exactly one insn within the loop that sets
9235 this pseudo followed immediately by a move insn that sets
9236 REPLACEMENT with REGNO. */
9237 static void
9240 rtx replacement;
9242 {
9243 rtx insn;
9244 rtx set;
9252 {
9253 /* Search for the insn that copies REGNO to NEW_REGNO? */
9261 }
9264 {
9265 rtx prev_insn;
9266 rtx prev_set;
9268 /* Some DEF-USE info would come in handy here to make this
9269 function more general. For now, just check the previous insn
9270 which is the most likely candidate for setting REGNO. */
9278 {
9279 /* We have:
9280 (set (reg regno) (expr))
9281 (set (reg new_regno) (reg regno))
9283 so try converting this to:
9284 (set (reg new_regno) (expr))
9285 (set (reg regno) (reg new_regno))
9287 The former construct is often generated when a global
9288 variable used for an induction variable is shadowed by a
9289 register (NEW_REGNO). The latter construct improves the
9290 chances of GIV replacement and BIV elimination. */
9300 {
9307 /* Update first use of REGNO. */
9311 /* Now perform copy propagation to hopefully
9312 remove all uses of REGNO within the loop. */
9314 }
9315 }
9316 }
9317 }
9319 /* Replace MEM with its associated pseudo register. This function is
9320 called from load_mems via for_each_rtx. DATA is actually a pointer
9321 to a structure describing the instruction currently being scanned
9322 and the MEM we are currently replacing. */
9324 static int
9328 {
9336 {
9341 /* We're not interested in the MEM associated with a
9342 CONST_DOUBLE, so there's no need to traverse into one. */
9346 /* This is not a MEM. */
9348 }
9351 /* This is not the MEM we are currently replacing. */
9354 /* Actually replace the MEM. */
9358 }
9360 static void
9362 rtx insn;
9363 rtx mem;
9364 rtx reg;
9365 {
9366 loop_replace_args args;
9373 }
9375 /* Replace one register with another. Called through for_each_rtx; PX points
9376 to the rtx being scanned. DATA is actually a pointer to
9377 a structure of arguments. */
9379 static int
9383 {
9394 }
9396 static void
9398 rtx insn;
9399 rtx reg;
9400 rtx replacement;
9401 {
9402 loop_replace_args args;
9409 }
9411 /* Replace occurrences of the old exit label for the loop with the new
9412 one. DATA is an rtx_pair containing the old and new labels,
9413 respectively. */
9415 static int
9419 {
9438 }
9439 \f
9440 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
9441 (ignored in the interim). */
9443 static rtx
9446 basic_block where_bb ATTRIBUTE_UNUSED;
9447 rtx where_insn;
9448 rtx pattern;
9449 {
9451 }
9454 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
9455 in basic block WHERE_BB (ignored in the interim) within the loop
9456 otherwise hoist PATTERN into the loop pre-header. */
9458 static rtx
9461 basic_block where_bb ATTRIBUTE_UNUSED;
9462 rtx where_insn;
9463 rtx pattern;
9464 {
9468 }
9471 /* Hoist insn for PATTERN into the loop pre-header. */
9473 rtx
9476 rtx pattern;
9477 {
9479 }
9482 /* Sink insn for PATTERN after the loop end. */
9484 rtx
9487 rtx pattern;
9488 {
9490 }
9493 /* If the loop has multiple exits, emit insn for PATTERN before the
9494 loop to ensure that it will always be executed no matter how the
9495 loop exits. Otherwise, emit the insn for PATTERN after the loop,
9496 since this is slightly more efficient. */
9498 static rtx
9501 rtx pattern;
9502 {
9505 else
9507 }
9508 \f
9509 static void
9514 {
9525 {
9529 }
9532 }
9535 static void
9540 {
9547 else
9563 {
9565 {
9577 }
9578 }
9589 {
9593 }
9596 }
9599 void
9602 {
9604 }
9607 void
9610 {
9612 }
9615 #define LOOP_BLOCK_NUM_1(INSN) \
9616 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9618 /* The notes do not have an assigned block, so look at the next insn. */
9619 #define LOOP_BLOCK_NUM(INSN) \
9620 ((INSN) ? (GET_CODE (INSN) == NOTE \
9621 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9622 : LOOP_BLOCK_NUM_1 (INSN)) \
9623 : -1)
9625 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9627 static void
9632 {
9633 rtx label;
9638 /* Print diagnostics to compare our concept of a loop with
9639 what the loop notes say. */
9654 {
9674 {
9677 {
9680 }
9681 }
9684 /* This can happen when a marked loop appears as two nested loops,
9685 say from while (a || b) {}. The inner loop won't match
9686 the loop markers but the outer one will. */
9689 }
9690 }
9692 /* Call this function from the debugger to dump LOOP. */
9694 void
9697 {
9699 }
9701 /* Call this function from the debugger to dump LOOPS. */
9703 void
9706 {
9708 }