1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
26 #include "rtl-error.h"
28 #include "insn-config.h"
29 #include "insn-attr.h"
30 #include "hard-reg-set.h"
33 #include "addresses.h"
37 #include "basic-block.h"
40 #include "tree-pass.h"
42 #include "insn-codes.h"
44 #ifndef STACK_PUSH_CODE
45 #ifdef STACK_GROWS_DOWNWARD
46 #define STACK_PUSH_CODE PRE_DEC
48 #define STACK_PUSH_CODE PRE_INC
52 #ifndef STACK_POP_CODE
53 #ifdef STACK_GROWS_DOWNWARD
54 #define STACK_POP_CODE POST_INC
56 #define STACK_POP_CODE POST_DEC
60 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx
, bool);
61 static void validate_replace_src_1 (rtx
*, void *);
62 static rtx
split_insn (rtx
);
64 /* Nonzero means allow operands to be volatile.
65 This should be 0 if you are generating rtl, such as if you are calling
66 the functions in optabs.c and expmed.c (most of the time).
67 This should be 1 if all valid insns need to be recognized,
68 such as in reginfo.c and final.c and reload.c.
70 init_recog and init_recog_no_volatile are responsible for setting this. */
74 struct recog_data_d recog_data
;
76 /* Contains a vector of operand_alternative structures for every operand.
77 Set up by preprocess_constraints. */
78 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
80 /* On return from `constrain_operands', indicate which alternative
83 int which_alternative
;
85 /* Nonzero after end of reload pass.
86 Set to 1 or 0 by toplev.c.
87 Controls the significance of (SUBREG (MEM)). */
91 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
92 int epilogue_completed
;
94 /* Initialize data used by the function `recog'.
95 This must be called once in the compilation of a function
96 before any insn recognition may be done in the function. */
99 init_recog_no_volatile (void)
111 /* Return true if labels in asm operands BODY are LABEL_REFs. */
114 asm_labels_ok (rtx body
)
119 asmop
= extract_asm_operands (body
);
120 if (asmop
== NULL_RTX
)
123 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
124 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
130 /* Check that X is an insn-body for an `asm' with operands
131 and that the operands mentioned in it are legitimate. */
134 check_asm_operands (rtx x
)
138 const char **constraints
;
141 if (!asm_labels_ok (x
))
144 /* Post-reload, be more strict with things. */
145 if (reload_completed
)
147 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
148 extract_insn (make_insn_raw (x
));
149 constrain_operands (1);
150 return which_alternative
>= 0;
153 noperands
= asm_noperands (x
);
159 operands
= XALLOCAVEC (rtx
, noperands
);
160 constraints
= XALLOCAVEC (const char *, noperands
);
162 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
164 for (i
= 0; i
< noperands
; i
++)
166 const char *c
= constraints
[i
];
169 if (! asm_operand_ok (operands
[i
], c
, constraints
))
176 /* Static data for the next two routines. */
178 typedef struct change_t
187 static change_t
*changes
;
188 static int changes_allocated
;
190 static int num_changes
= 0;
192 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
193 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
194 the change is simply made.
196 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
197 will be called with the address and mode as parameters. If OBJECT is
198 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
201 IN_GROUP is nonzero if this is part of a group of changes that must be
202 performed as a group. In that case, the changes will be stored. The
203 function `apply_change_group' will validate and apply the changes.
205 If IN_GROUP is zero, this is a single change. Try to recognize the insn
206 or validate the memory reference with the change applied. If the result
207 is not valid for the machine, suppress the change and return zero.
208 Otherwise, perform the change and return 1. */
211 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
215 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
218 gcc_assert (in_group
!= 0 || num_changes
== 0);
222 /* Save the information describing this change. */
223 if (num_changes
>= changes_allocated
)
225 if (changes_allocated
== 0)
226 /* This value allows for repeated substitutions inside complex
227 indexed addresses, or changes in up to 5 insns. */
228 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
230 changes_allocated
*= 2;
232 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
235 changes
[num_changes
].object
= object
;
236 changes
[num_changes
].loc
= loc
;
237 changes
[num_changes
].old
= old
;
238 changes
[num_changes
].unshare
= unshare
;
240 if (object
&& !MEM_P (object
))
242 /* Set INSN_CODE to force rerecognition of insn. Save old code in
244 changes
[num_changes
].old_code
= INSN_CODE (object
);
245 INSN_CODE (object
) = -1;
250 /* If we are making a group of changes, return 1. Otherwise, validate the
251 change group we made. */
256 return apply_change_group ();
259 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
263 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
265 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
268 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
272 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
274 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
278 /* Keep X canonicalized if some changes have made it non-canonical; only
279 modifies the operands of X, not (for example) its code. Simplifications
280 are not the job of this routine.
282 Return true if anything was changed. */
284 canonicalize_change_group (rtx insn
, rtx x
)
286 if (COMMUTATIVE_P (x
)
287 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
289 /* Oops, the caller has made X no longer canonical.
290 Let's redo the changes in the correct order. */
291 rtx tem
= XEXP (x
, 0);
292 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
293 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
301 /* This subroutine of apply_change_group verifies whether the changes to INSN
302 were valid; i.e. whether INSN can still be recognized.
304 If IN_GROUP is true clobbers which have to be added in order to
305 match the instructions will be added to the current change group.
306 Otherwise the changes will take effect immediately. */
309 insn_invalid_p (rtx insn
, bool in_group
)
311 rtx pat
= PATTERN (insn
);
312 int num_clobbers
= 0;
313 /* If we are before reload and the pattern is a SET, see if we can add
315 int icode
= recog (pat
, insn
,
316 (GET_CODE (pat
) == SET
317 && ! reload_completed
318 && ! reload_in_progress
)
319 ? &num_clobbers
: 0);
320 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
323 /* If this is an asm and the operand aren't legal, then fail. Likewise if
324 this is not an asm and the insn wasn't recognized. */
325 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
326 || (!is_asm
&& icode
< 0))
329 /* If we have to add CLOBBERs, fail if we have to add ones that reference
330 hard registers since our callers can't know if they are live or not.
331 Otherwise, add them. */
332 if (num_clobbers
> 0)
336 if (added_clobbers_hard_reg_p (icode
))
339 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
340 XVECEXP (newpat
, 0, 0) = pat
;
341 add_clobbers (newpat
, icode
);
343 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
345 PATTERN (insn
) = pat
= newpat
;
348 /* After reload, verify that all constraints are satisfied. */
349 if (reload_completed
)
353 if (! constrain_operands (1))
357 INSN_CODE (insn
) = icode
;
361 /* Return number of changes made and not validated yet. */
363 num_changes_pending (void)
368 /* Tentatively apply the changes numbered NUM and up.
369 Return 1 if all changes are valid, zero otherwise. */
372 verify_changes (int num
)
375 rtx last_validated
= NULL_RTX
;
377 /* The changes have been applied and all INSN_CODEs have been reset to force
380 The changes are valid if we aren't given an object, or if we are
381 given a MEM and it still is a valid address, or if this is in insn
382 and it is recognized. In the latter case, if reload has completed,
383 we also require that the operands meet the constraints for
386 for (i
= num
; i
< num_changes
; i
++)
388 rtx object
= changes
[i
].object
;
390 /* If there is no object to test or if it is the same as the one we
391 already tested, ignore it. */
392 if (object
== 0 || object
== last_validated
)
397 if (! memory_address_addr_space_p (GET_MODE (object
),
399 MEM_ADDR_SPACE (object
)))
402 else if (/* changes[i].old might be zero, e.g. when putting a
403 REG_FRAME_RELATED_EXPR into a previously empty list. */
405 && REG_P (changes
[i
].old
)
406 && asm_noperands (PATTERN (object
)) > 0
407 && REG_EXPR (changes
[i
].old
) != NULL_TREE
408 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
409 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
411 /* Don't allow changes of hard register operands to inline
412 assemblies if they have been defined as register asm ("x"). */
415 else if (DEBUG_INSN_P (object
))
417 else if (insn_invalid_p (object
, true))
419 rtx pat
= PATTERN (object
);
421 /* Perhaps we couldn't recognize the insn because there were
422 extra CLOBBERs at the end. If so, try to re-recognize
423 without the last CLOBBER (later iterations will cause each of
424 them to be eliminated, in turn). But don't do this if we
425 have an ASM_OPERAND. */
426 if (GET_CODE (pat
) == PARALLEL
427 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
428 && asm_noperands (PATTERN (object
)) < 0)
432 if (XVECLEN (pat
, 0) == 2)
433 newpat
= XVECEXP (pat
, 0, 0);
439 = gen_rtx_PARALLEL (VOIDmode
,
440 rtvec_alloc (XVECLEN (pat
, 0) - 1));
441 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
442 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
445 /* Add a new change to this group to replace the pattern
446 with this new pattern. Then consider this change
447 as having succeeded. The change we added will
448 cause the entire call to fail if things remain invalid.
450 Note that this can lose if a later change than the one
451 we are processing specified &XVECEXP (PATTERN (object), 0, X)
452 but this shouldn't occur. */
454 validate_change (object
, &PATTERN (object
), newpat
, 1);
457 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
458 || GET_CODE (pat
) == VAR_LOCATION
)
459 /* If this insn is a CLOBBER or USE, it is always valid, but is
465 last_validated
= object
;
468 return (i
== num_changes
);
471 /* A group of changes has previously been issued with validate_change
472 and verified with verify_changes. Call df_insn_rescan for each of
473 the insn changed and clear num_changes. */
476 confirm_change_group (void)
479 rtx last_object
= NULL
;
481 for (i
= 0; i
< num_changes
; i
++)
483 rtx object
= changes
[i
].object
;
485 if (changes
[i
].unshare
)
486 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
488 /* Avoid unnecessary rescanning when multiple changes to same instruction
492 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
493 df_insn_rescan (last_object
);
494 last_object
= object
;
498 if (last_object
&& INSN_P (last_object
))
499 df_insn_rescan (last_object
);
503 /* Apply a group of changes previously issued with `validate_change'.
504 If all changes are valid, call confirm_change_group and return 1,
505 otherwise, call cancel_changes and return 0. */
508 apply_change_group (void)
510 if (verify_changes (0))
512 confirm_change_group ();
523 /* Return the number of changes so far in the current group. */
526 num_validated_changes (void)
531 /* Retract the changes numbered NUM and up. */
534 cancel_changes (int num
)
538 /* Back out all the changes. Do this in the opposite order in which
540 for (i
= num_changes
- 1; i
>= num
; i
--)
542 *changes
[i
].loc
= changes
[i
].old
;
543 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
544 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
549 /* Reduce conditional compilation elsewhere. */
552 #define CODE_FOR_extv CODE_FOR_nothing
556 #define CODE_FOR_extzv CODE_FOR_nothing
559 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
563 simplify_while_replacing (rtx
*loc
, rtx to
, rtx object
,
564 enum machine_mode op0_mode
)
567 enum rtx_code code
= GET_CODE (x
);
568 rtx new_rtx
= NULL_RTX
;
570 if (SWAPPABLE_OPERANDS_P (x
)
571 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
573 validate_unshare_change (object
, loc
,
574 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
575 : swap_condition (code
),
576 GET_MODE (x
), XEXP (x
, 1),
582 /* Canonicalize arithmetics with all constant operands. */
583 switch (GET_RTX_CLASS (code
))
586 if (CONSTANT_P (XEXP (x
, 0)))
587 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
592 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
593 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
597 case RTX_COMM_COMPARE
:
598 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
599 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
600 XEXP (x
, 0), XEXP (x
, 1));
607 validate_change (object
, loc
, new_rtx
, 1);
614 /* If we have a PLUS whose second operand is now a CONST_INT, use
615 simplify_gen_binary to try to simplify it.
616 ??? We may want later to remove this, once simplification is
617 separated from this function. */
618 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
619 validate_change (object
, loc
,
621 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
624 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
625 validate_change (object
, loc
,
627 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
628 simplify_gen_unary (NEG
,
629 GET_MODE (x
), XEXP (x
, 1),
634 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
636 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
638 /* If any of the above failed, substitute in something that
639 we know won't be recognized. */
641 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
642 validate_change (object
, loc
, new_rtx
, 1);
646 /* All subregs possible to simplify should be simplified. */
647 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
650 /* Subregs of VOIDmode operands are incorrect. */
651 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
652 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
654 validate_change (object
, loc
, new_rtx
, 1);
658 /* If we are replacing a register with memory, try to change the memory
659 to be the mode required for memory in extract operations (this isn't
660 likely to be an insertion operation; if it was, nothing bad will
661 happen, we might just fail in some cases). */
663 if (MEM_P (XEXP (x
, 0))
664 && CONST_INT_P (XEXP (x
, 1))
665 && CONST_INT_P (XEXP (x
, 2))
666 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
667 MEM_ADDR_SPACE (XEXP (x
, 0)))
668 && !MEM_VOLATILE_P (XEXP (x
, 0)))
670 enum machine_mode wanted_mode
= VOIDmode
;
671 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
672 int pos
= INTVAL (XEXP (x
, 2));
674 if (GET_CODE (x
) == ZERO_EXTRACT
&& HAVE_extzv
)
676 wanted_mode
= insn_data
[CODE_FOR_extzv
].operand
[1].mode
;
677 if (wanted_mode
== VOIDmode
)
678 wanted_mode
= word_mode
;
680 else if (GET_CODE (x
) == SIGN_EXTRACT
&& HAVE_extv
)
682 wanted_mode
= insn_data
[CODE_FOR_extv
].operand
[1].mode
;
683 if (wanted_mode
== VOIDmode
)
684 wanted_mode
= word_mode
;
687 /* If we have a narrower mode, we can do something. */
688 if (wanted_mode
!= VOIDmode
689 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
691 int offset
= pos
/ BITS_PER_UNIT
;
694 /* If the bytes and bits are counted differently, we
695 must adjust the offset. */
696 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
698 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
701 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
702 == GET_MODE_BITSIZE (wanted_mode
));
703 pos
%= GET_MODE_BITSIZE (wanted_mode
);
705 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
707 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
708 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
719 /* Replace every occurrence of FROM in X with TO. Mark each change with
720 validate_change passing OBJECT. */
723 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx object
,
730 enum machine_mode op0_mode
= VOIDmode
;
731 int prev_changes
= num_changes
;
737 fmt
= GET_RTX_FORMAT (code
);
739 op0_mode
= GET_MODE (XEXP (x
, 0));
741 /* X matches FROM if it is the same rtx or they are both referring to the
742 same register in the same mode. Avoid calling rtx_equal_p unless the
743 operands look similar. */
746 || (REG_P (x
) && REG_P (from
)
747 && GET_MODE (x
) == GET_MODE (from
)
748 && REGNO (x
) == REGNO (from
))
749 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
750 && rtx_equal_p (x
, from
)))
752 validate_unshare_change (object
, loc
, to
, 1);
756 /* Call ourself recursively to perform the replacements.
757 We must not replace inside already replaced expression, otherwise we
758 get infinite recursion for replacements like (reg X)->(subreg (reg X))
759 so we must special case shared ASM_OPERANDS. */
761 if (GET_CODE (x
) == PARALLEL
)
763 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
765 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
766 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
768 /* Verify that operands are really shared. */
769 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
770 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
772 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
773 from
, to
, object
, simplify
);
776 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
781 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
784 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
785 else if (fmt
[i
] == 'E')
786 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
787 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
791 /* If we didn't substitute, there is nothing more to do. */
792 if (num_changes
== prev_changes
)
795 /* ??? The regmove is no more, so is this aberration still necessary? */
796 /* Allow substituted expression to have different mode. This is used by
797 regmove to change mode of pseudo register. */
798 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
799 op0_mode
= GET_MODE (XEXP (x
, 0));
801 /* Do changes needed to keep rtx consistent. Don't do any other
802 simplifications, as it is not our job. */
804 simplify_while_replacing (loc
, to
, object
, op0_mode
);
807 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
808 with TO. After all changes have been made, validate by seeing
809 if INSN is still valid. */
812 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx insn
, rtx
*loc
)
814 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
815 return apply_change_group ();
818 /* Try replacing every occurrence of FROM in INSN with TO. After all
819 changes have been made, validate by seeing if INSN is still valid. */
822 validate_replace_rtx (rtx from
, rtx to
, rtx insn
)
824 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
825 return apply_change_group ();
828 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
829 is a part of INSN. After all changes have been made, validate by seeing if
831 validate_replace_rtx (from, to, insn) is equivalent to
832 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
835 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx insn
)
837 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
838 return apply_change_group ();
841 /* Same as above, but do not simplify rtx afterwards. */
843 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
846 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
847 return apply_change_group ();
851 /* Try replacing every occurrence of FROM in INSN with TO. This also
852 will replace in REG_EQUAL and REG_EQUIV notes. */
855 validate_replace_rtx_group (rtx from
, rtx to
, rtx insn
)
858 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
859 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
860 if (REG_NOTE_KIND (note
) == REG_EQUAL
861 || REG_NOTE_KIND (note
) == REG_EQUIV
)
862 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
865 /* Function called by note_uses to replace used subexpressions. */
866 struct validate_replace_src_data
868 rtx from
; /* Old RTX */
869 rtx to
; /* New RTX */
870 rtx insn
; /* Insn in which substitution is occurring. */
874 validate_replace_src_1 (rtx
*x
, void *data
)
876 struct validate_replace_src_data
*d
877 = (struct validate_replace_src_data
*) data
;
879 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
882 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
886 validate_replace_src_group (rtx from
, rtx to
, rtx insn
)
888 struct validate_replace_src_data d
;
893 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
896 /* Try simplify INSN.
897 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
898 pattern and return true if something was simplified. */
901 validate_simplify_insn (rtx insn
)
907 pat
= PATTERN (insn
);
909 if (GET_CODE (pat
) == SET
)
911 newpat
= simplify_rtx (SET_SRC (pat
));
912 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
913 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
914 newpat
= simplify_rtx (SET_DEST (pat
));
915 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
916 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
918 else if (GET_CODE (pat
) == PARALLEL
)
919 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
921 rtx s
= XVECEXP (pat
, 0, i
);
923 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
925 newpat
= simplify_rtx (SET_SRC (s
));
926 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
927 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
928 newpat
= simplify_rtx (SET_DEST (s
));
929 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
930 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
933 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
937 /* Return 1 if the insn using CC0 set by INSN does not contain
938 any ordered tests applied to the condition codes.
939 EQ and NE tests do not count. */
942 next_insn_tests_no_inequality (rtx insn
)
944 rtx next
= next_cc0_user (insn
);
946 /* If there is no next insn, we have to take the conservative choice. */
950 return (INSN_P (next
)
951 && ! inequality_comparisons_p (PATTERN (next
)));
955 /* Return 1 if OP is a valid general operand for machine mode MODE.
956 This is either a register reference, a memory reference,
957 or a constant. In the case of a memory reference, the address
958 is checked for general validity for the target machine.
960 Register and memory references must have mode MODE in order to be valid,
961 but some constants have no machine mode and are valid for any mode.
963 If MODE is VOIDmode, OP is checked for validity for whatever mode
966 The main use of this function is as a predicate in match_operand
967 expressions in the machine description. */
970 general_operand (rtx op
, enum machine_mode mode
)
972 enum rtx_code code
= GET_CODE (op
);
974 if (mode
== VOIDmode
)
975 mode
= GET_MODE (op
);
977 /* Don't accept CONST_INT or anything similar
978 if the caller wants something floating. */
979 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
980 && GET_MODE_CLASS (mode
) != MODE_INT
981 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
986 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
990 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
992 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
993 && targetm
.legitimate_constant_p (mode
== VOIDmode
997 /* Except for certain constants with VOIDmode, already checked for,
998 OP's mode must match MODE if MODE specifies a mode. */
1000 if (GET_MODE (op
) != mode
)
1005 rtx sub
= SUBREG_REG (op
);
1007 #ifdef INSN_SCHEDULING
1008 /* On machines that have insn scheduling, we want all memory
1009 reference to be explicit, so outlaw paradoxical SUBREGs.
1010 However, we must allow them after reload so that they can
1011 get cleaned up by cleanup_subreg_operands. */
1012 if (!reload_completed
&& MEM_P (sub
)
1013 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1016 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1017 may result in incorrect reference. We should simplify all valid
1018 subregs of MEM anyway. But allow this after reload because we
1019 might be called from cleanup_subreg_operands.
1021 ??? This is a kludge. */
1022 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1026 #ifdef CANNOT_CHANGE_MODE_CLASS
1028 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1029 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1030 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1031 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1032 /* LRA can generate some invalid SUBREGS just for matched
1033 operand reload presentation. LRA needs to treat them as
1035 && ! LRA_SUBREG_P (op
))
1039 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1040 create such rtl, and we must reject it. */
1041 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1042 /* LRA can use subreg to store a floating point value in an
1043 integer mode. Although the floating point and the
1044 integer modes need the same number of hard registers, the
1045 size of floating point mode can be less than the integer
1047 && ! lra_in_progress
1048 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1052 code
= GET_CODE (op
);
1056 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1057 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1061 rtx y
= XEXP (op
, 0);
1063 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1066 /* Use the mem's mode, since it will be reloaded thus. LRA can
1067 generate move insn with invalid addresses which is made valid
1068 and efficiently calculated by LRA through further numerous
1071 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1078 /* Return 1 if OP is a valid memory address for a memory reference
1081 The main use of this function is as a predicate in match_operand
1082 expressions in the machine description. */
1085 address_operand (rtx op
, enum machine_mode mode
)
1087 return memory_address_p (mode
, op
);
1090 /* Return 1 if OP is a register reference of mode MODE.
1091 If MODE is VOIDmode, accept a register in any mode.
1093 The main use of this function is as a predicate in match_operand
1094 expressions in the machine description. */
1097 register_operand (rtx op
, enum machine_mode mode
)
1099 if (GET_CODE (op
) == SUBREG
)
1101 rtx sub
= SUBREG_REG (op
);
1103 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1104 because it is guaranteed to be reloaded into one.
1105 Just make sure the MEM is valid in itself.
1106 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1107 but currently it does result from (SUBREG (REG)...) where the
1108 reg went on the stack.) */
1109 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1112 else if (!REG_P (op
))
1114 return general_operand (op
, mode
);
1117 /* Return 1 for a register in Pmode; ignore the tested mode. */
1120 pmode_register_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1122 return register_operand (op
, Pmode
);
1125 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1126 or a hard register. */
1129 scratch_operand (rtx op
, enum machine_mode mode
)
1131 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1134 return (GET_CODE (op
) == SCRATCH
1136 && (lra_in_progress
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
1139 /* Return 1 if OP is a valid immediate operand for mode MODE.
1141 The main use of this function is as a predicate in match_operand
1142 expressions in the machine description. */
1145 immediate_operand (rtx op
, enum machine_mode mode
)
1147 /* Don't accept CONST_INT or anything similar
1148 if the caller wants something floating. */
1149 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1150 && GET_MODE_CLASS (mode
) != MODE_INT
1151 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1154 if (CONST_INT_P (op
)
1156 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1159 return (CONSTANT_P (op
)
1160 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1161 || GET_MODE (op
) == VOIDmode
)
1162 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1163 && targetm
.legitimate_constant_p (mode
== VOIDmode
1168 /* Returns 1 if OP is an operand that is a CONST_INT. */
1171 const_int_operand (rtx op
, enum machine_mode mode
)
1173 if (!CONST_INT_P (op
))
1176 if (mode
!= VOIDmode
1177 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1183 /* Returns 1 if OP is an operand that is a constant integer or constant
1184 floating-point number. */
1187 const_double_operand (rtx op
, enum machine_mode mode
)
1189 /* Don't accept CONST_INT or anything similar
1190 if the caller wants something floating. */
1191 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1192 && GET_MODE_CLASS (mode
) != MODE_INT
1193 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1196 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1197 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1198 || GET_MODE (op
) == VOIDmode
));
1201 /* Return 1 if OP is a general operand that is not an immediate operand. */
1204 nonimmediate_operand (rtx op
, enum machine_mode mode
)
1206 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1209 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1212 nonmemory_operand (rtx op
, enum machine_mode mode
)
1214 if (CONSTANT_P (op
))
1215 return immediate_operand (op
, mode
);
1216 return register_operand (op
, mode
);
1219 /* Return 1 if OP is a valid operand that stands for pushing a
1220 value of mode MODE onto the stack.
1222 The main use of this function is as a predicate in match_operand
1223 expressions in the machine description. */
1226 push_operand (rtx op
, enum machine_mode mode
)
1228 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1230 #ifdef PUSH_ROUNDING
1231 rounded_size
= PUSH_ROUNDING (rounded_size
);
1237 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1242 if (rounded_size
== GET_MODE_SIZE (mode
))
1244 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1249 if (GET_CODE (op
) != PRE_MODIFY
1250 || GET_CODE (XEXP (op
, 1)) != PLUS
1251 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1252 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1253 #ifdef STACK_GROWS_DOWNWARD
1254 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1256 || INTVAL (XEXP (XEXP (op
, 1), 1)) != (int) rounded_size
1262 return XEXP (op
, 0) == stack_pointer_rtx
;
1265 /* Return 1 if OP is a valid operand that stands for popping a
1266 value of mode MODE off the stack.
1268 The main use of this function is as a predicate in match_operand
1269 expressions in the machine description. */
1272 pop_operand (rtx op
, enum machine_mode mode
)
1277 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1282 if (GET_CODE (op
) != STACK_POP_CODE
)
1285 return XEXP (op
, 0) == stack_pointer_rtx
;
1288 /* Return 1 if ADDR is a valid memory address
1289 for mode MODE in address space AS. */
1292 memory_address_addr_space_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1293 rtx addr
, addr_space_t as
)
1295 #ifdef GO_IF_LEGITIMATE_ADDRESS
1296 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1297 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1303 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1307 /* Return 1 if OP is a valid memory reference with mode MODE,
1308 including a valid address.
1310 The main use of this function is as a predicate in match_operand
1311 expressions in the machine description. */
1314 memory_operand (rtx op
, enum machine_mode mode
)
1318 if (! reload_completed
)
1319 /* Note that no SUBREG is a memory operand before end of reload pass,
1320 because (SUBREG (MEM...)) forces reloading into a register. */
1321 return MEM_P (op
) && general_operand (op
, mode
);
1323 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1327 if (GET_CODE (inner
) == SUBREG
)
1328 inner
= SUBREG_REG (inner
);
1330 return (MEM_P (inner
) && general_operand (op
, mode
));
1333 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1334 that is, a memory reference whose address is a general_operand. */
1337 indirect_operand (rtx op
, enum machine_mode mode
)
1339 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1340 if (! reload_completed
1341 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1343 int offset
= SUBREG_BYTE (op
);
1344 rtx inner
= SUBREG_REG (op
);
1346 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1349 /* The only way that we can have a general_operand as the resulting
1350 address is if OFFSET is zero and the address already is an operand
1351 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1354 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1355 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1356 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1357 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1358 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1362 && memory_operand (op
, mode
)
1363 && general_operand (XEXP (op
, 0), Pmode
));
1366 /* Return 1 if this is an ordered comparison operator (not including
1367 ORDERED and UNORDERED). */
1370 ordered_comparison_operator (rtx op
, enum machine_mode mode
)
1372 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1374 switch (GET_CODE (op
))
1392 /* Return 1 if this is a comparison operator. This allows the use of
1393 MATCH_OPERATOR to recognize all the branch insns. */
1396 comparison_operator (rtx op
, enum machine_mode mode
)
1398 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1399 && COMPARISON_P (op
));
1402 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1405 extract_asm_operands (rtx body
)
1408 switch (GET_CODE (body
))
1414 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1415 tmp
= SET_SRC (body
);
1416 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1421 tmp
= XVECEXP (body
, 0, 0);
1422 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1424 if (GET_CODE (tmp
) == SET
)
1426 tmp
= SET_SRC (tmp
);
1427 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1438 /* If BODY is an insn body that uses ASM_OPERANDS,
1439 return the number of operands (both input and output) in the insn.
1440 Otherwise return -1. */
1443 asm_noperands (const_rtx body
)
1445 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1451 if (GET_CODE (body
) == SET
)
1453 else if (GET_CODE (body
) == PARALLEL
)
1456 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1458 /* Multiple output operands, or 1 output plus some clobbers:
1460 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1461 /* Count backwards through CLOBBERs to determine number of SETs. */
1462 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1464 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1466 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1470 /* N_SETS is now number of output operands. */
1473 /* Verify that all the SETs we have
1474 came from a single original asm_operands insn
1475 (so that invalid combinations are blocked). */
1476 for (i
= 0; i
< n_sets
; i
++)
1478 rtx elt
= XVECEXP (body
, 0, i
);
1479 if (GET_CODE (elt
) != SET
)
1481 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1483 /* If these ASM_OPERANDS rtx's came from different original insns
1484 then they aren't allowed together. */
1485 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1486 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1492 /* 0 outputs, but some clobbers:
1493 body is [(asm_operands ...) (clobber (reg ...))...]. */
1494 /* Make sure all the other parallel things really are clobbers. */
1495 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1496 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1501 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1502 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1505 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1506 copy its operands (both input and output) into the vector OPERANDS,
1507 the locations of the operands within the insn into the vector OPERAND_LOCS,
1508 and the constraints for the operands into CONSTRAINTS.
1509 Write the modes of the operands into MODES.
1510 Return the assembler-template.
1512 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1513 we don't store that info. */
1516 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1517 const char **constraints
, enum machine_mode
*modes
,
1520 int nbase
= 0, n
, i
;
1523 switch (GET_CODE (body
))
1526 /* Zero output asm: BODY is (asm_operands ...). */
1531 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1532 asmop
= SET_SRC (body
);
1534 /* The output is in the SET.
1535 Its constraint is in the ASM_OPERANDS itself. */
1537 operands
[0] = SET_DEST (body
);
1539 operand_locs
[0] = &SET_DEST (body
);
1541 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1543 modes
[0] = GET_MODE (SET_DEST (body
));
1549 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1551 asmop
= XVECEXP (body
, 0, 0);
1552 if (GET_CODE (asmop
) == SET
)
1554 asmop
= SET_SRC (asmop
);
1556 /* At least one output, plus some CLOBBERs. The outputs are in
1557 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1558 for (i
= 0; i
< nparallel
; i
++)
1560 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1561 break; /* Past last SET */
1563 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1565 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1567 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1569 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1580 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1581 for (i
= 0; i
< n
; i
++)
1584 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1586 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1588 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1590 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1594 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1595 for (i
= 0; i
< n
; i
++)
1598 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1600 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1602 constraints
[nbase
+ i
] = "";
1604 modes
[nbase
+ i
] = Pmode
;
1608 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1610 return ASM_OPERANDS_TEMPLATE (asmop
);
1613 /* Parse inline assembly string STRING and determine which operands are
1614 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1615 to true if operand I is referenced.
1617 This is intended to distinguish barrier-like asms such as:
1619 asm ("" : "=m" (...));
1621 from real references such as:
1623 asm ("sw\t$0, %0" : "=m" (...)); */
1626 get_referenced_operands (const char *string
, bool *used
,
1627 unsigned int noperands
)
1629 memset (used
, 0, sizeof (bool) * noperands
);
1630 const char *p
= string
;
1636 /* A letter followed by a digit indicates an operand number. */
1637 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1642 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1643 if (endptr
!= p
&& opnum
< noperands
)
1657 /* Check if an asm_operand matches its constraints.
1658 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1661 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1665 bool incdec_ok
= false;
1668 /* Use constrain_operands after reload. */
1669 gcc_assert (!reload_completed
);
1671 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1672 many alternatives as required to match the other operands. */
1673 if (*constraint
== '\0')
1678 char c
= *constraint
;
1695 case '0': case '1': case '2': case '3': case '4':
1696 case '5': case '6': case '7': case '8': case '9':
1697 /* If caller provided constraints pointer, look up
1698 the matching constraint. Otherwise, our caller should have
1699 given us the proper matching constraint, but we can't
1700 actually fail the check if they didn't. Indicate that
1701 results are inconclusive. */
1705 unsigned long match
;
1707 match
= strtoul (constraint
, &end
, 10);
1709 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1710 constraint
= (const char *) end
;
1716 while (ISDIGIT (*constraint
));
1723 if (address_operand (op
, VOIDmode
))
1727 case TARGET_MEM_CONSTRAINT
:
1728 case 'V': /* non-offsettable */
1729 if (memory_operand (op
, VOIDmode
))
1733 case 'o': /* offsettable */
1734 if (offsettable_nonstrict_memref_p (op
))
1739 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed to exist,
1740 excepting those that expand_call created. Further, on some
1741 machines which do not have generalized auto inc/dec, an inc/dec
1742 is not a memory_operand.
1744 Match any memory and hope things are resolved after reload. */
1748 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1749 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1759 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1760 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1769 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1770 || (GET_CODE (op
) == CONST_VECTOR
1771 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
1776 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1777 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', constraint
))
1781 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1782 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'H', constraint
))
1787 if (CONST_SCALAR_INT_P (op
))
1792 if (CONSTANT_P (op
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
1797 if (CONST_SCALAR_INT_P (op
))
1802 if (CONST_INT_P (op
)
1803 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'I', constraint
))
1807 if (CONST_INT_P (op
)
1808 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'J', constraint
))
1812 if (CONST_INT_P (op
)
1813 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'K', constraint
))
1817 if (CONST_INT_P (op
)
1818 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'L', constraint
))
1822 if (CONST_INT_P (op
)
1823 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'M', constraint
))
1827 if (CONST_INT_P (op
)
1828 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'N', constraint
))
1832 if (CONST_INT_P (op
)
1833 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'O', constraint
))
1837 if (CONST_INT_P (op
)
1838 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), 'P', constraint
))
1847 if (general_operand (op
, VOIDmode
))
1852 /* For all other letters, we first check for a register class,
1853 otherwise it is an EXTRA_CONSTRAINT. */
1854 if (REG_CLASS_FROM_CONSTRAINT (c
, constraint
) != NO_REGS
)
1857 if (GET_MODE (op
) == BLKmode
)
1859 if (register_operand (op
, VOIDmode
))
1862 #ifdef EXTRA_CONSTRAINT_STR
1863 else if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
))
1864 /* Every memory operand can be reloaded to fit. */
1865 result
= result
|| memory_operand (op
, VOIDmode
);
1866 else if (EXTRA_ADDRESS_CONSTRAINT (c
, constraint
))
1867 /* Every address operand can be reloaded to fit. */
1868 result
= result
|| address_operand (op
, VOIDmode
);
1869 else if (EXTRA_CONSTRAINT_STR (op
, c
, constraint
))
1874 len
= CONSTRAINT_LEN (c
, constraint
);
1877 while (--len
&& *constraint
);
1883 /* For operands without < or > constraints reject side-effects. */
1884 if (!incdec_ok
&& result
&& MEM_P (op
))
1885 switch (GET_CODE (XEXP (op
, 0)))
1902 /* Given an rtx *P, if it is a sum containing an integer constant term,
1903 return the location (type rtx *) of the pointer to that constant term.
1904 Otherwise, return a null pointer. */
1907 find_constant_term_loc (rtx
*p
)
1910 enum rtx_code code
= GET_CODE (*p
);
1912 /* If *P IS such a constant term, P is its location. */
1914 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1918 /* Otherwise, if not a sum, it has no constant term. */
1920 if (GET_CODE (*p
) != PLUS
)
1923 /* If one of the summands is constant, return its location. */
1925 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1926 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1929 /* Otherwise, check each summand for containing a constant term. */
1931 if (XEXP (*p
, 0) != 0)
1933 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1938 if (XEXP (*p
, 1) != 0)
1940 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1948 /* Return 1 if OP is a memory reference
1949 whose address contains no side effects
1950 and remains valid after the addition
1951 of a positive integer less than the
1952 size of the object being referenced.
1954 We assume that the original address is valid and do not check it.
1956 This uses strict_memory_address_p as a subroutine, so
1957 don't use it before reload. */
1960 offsettable_memref_p (rtx op
)
1962 return ((MEM_P (op
))
1963 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1964 MEM_ADDR_SPACE (op
)));
1967 /* Similar, but don't require a strictly valid mem ref:
1968 consider pseudo-regs valid as index or base regs. */
1971 offsettable_nonstrict_memref_p (rtx op
)
1973 return ((MEM_P (op
))
1974 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1975 MEM_ADDR_SPACE (op
)));
1978 /* Return 1 if Y is a memory address which contains no side effects
1979 and would remain valid for address space AS after the addition of
1980 a positive integer less than the size of that mode.
1982 We assume that the original address is valid and do not check it.
1983 We do check that it is valid for narrower modes.
1985 If STRICTP is nonzero, we require a strictly valid address,
1986 for the sake of use in reload.c. */
1989 offsettable_address_addr_space_p (int strictp
, enum machine_mode mode
, rtx y
,
1992 enum rtx_code ycode
= GET_CODE (y
);
1996 int (*addressp
) (enum machine_mode
, rtx
, addr_space_t
) =
1997 (strictp
? strict_memory_address_addr_space_p
1998 : memory_address_addr_space_p
);
1999 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
2001 if (CONSTANT_ADDRESS_P (y
))
2004 /* Adjusting an offsettable address involves changing to a narrower mode.
2005 Make sure that's OK. */
2007 if (mode_dependent_address_p (y
, as
))
2010 enum machine_mode address_mode
= GET_MODE (y
);
2011 if (address_mode
== VOIDmode
)
2012 address_mode
= targetm
.addr_space
.address_mode (as
);
2013 #ifdef POINTERS_EXTEND_UNSIGNED
2014 enum machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
2017 /* ??? How much offset does an offsettable BLKmode reference need?
2018 Clearly that depends on the situation in which it's being used.
2019 However, the current situation in which we test 0xffffffff is
2020 less than ideal. Caveat user. */
2022 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
2024 /* If the expression contains a constant term,
2025 see if it remains valid when max possible offset is added. */
2027 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
2032 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
2033 /* Use QImode because an odd displacement may be automatically invalid
2034 for any wider mode. But it should be valid for a single byte. */
2035 good
= (*addressp
) (QImode
, y
, as
);
2037 /* In any case, restore old contents of memory. */
2042 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
2045 /* The offset added here is chosen as the maximum offset that
2046 any instruction could need to add when operating on something
2047 of the specified mode. We assume that if Y and Y+c are
2048 valid addresses then so is Y+d for all 0<d<c. adjust_address will
2049 go inside a LO_SUM here, so we do so as well. */
2050 if (GET_CODE (y
) == LO_SUM
2052 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
2053 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
2054 plus_constant (address_mode
, XEXP (y
, 1),
2056 #ifdef POINTERS_EXTEND_UNSIGNED
2057 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2058 else if (POINTERS_EXTEND_UNSIGNED
> 0
2059 && GET_CODE (y
) == ZERO_EXTEND
2060 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2061 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2062 plus_constant (pointer_mode
, XEXP (y
, 0),
2066 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2068 /* Use QImode because an odd displacement may be automatically invalid
2069 for any wider mode. But it should be valid for a single byte. */
2070 return (*addressp
) (QImode
, z
, as
);
2073 /* Return 1 if ADDR is an address-expression whose effect depends
2074 on the mode of the memory reference it is used in.
2076 ADDRSPACE is the address space associated with the address.
2078 Autoincrement addressing is a typical example of mode-dependence
2079 because the amount of the increment depends on the mode. */
2082 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2084 /* Auto-increment addressing with anything other than post_modify
2085 or pre_modify always introduces a mode dependency. Catch such
2086 cases now instead of deferring to the target. */
2087 if (GET_CODE (addr
) == PRE_INC
2088 || GET_CODE (addr
) == POST_INC
2089 || GET_CODE (addr
) == PRE_DEC
2090 || GET_CODE (addr
) == POST_DEC
)
2093 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2096 /* Like extract_insn, but save insn extracted and don't extract again, when
2097 called again for the same insn expecting that recog_data still contain the
2098 valid information. This is used primary by gen_attr infrastructure that
2099 often does extract insn again and again. */
2101 extract_insn_cached (rtx insn
)
2103 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2105 extract_insn (insn
);
2106 recog_data
.insn
= insn
;
2109 /* Do cached extract_insn, constrain_operands and complain about failures.
2110 Used by insn_attrtab. */
2112 extract_constrain_insn_cached (rtx insn
)
2114 extract_insn_cached (insn
);
2115 if (which_alternative
== -1
2116 && !constrain_operands (reload_completed
))
2117 fatal_insn_not_found (insn
);
2120 /* Do cached constrain_operands and complain about failures. */
2122 constrain_operands_cached (int strict
)
2124 if (which_alternative
== -1)
2125 return constrain_operands (strict
);
2130 /* Analyze INSN and fill in recog_data. */
2133 extract_insn (rtx insn
)
2138 rtx body
= PATTERN (insn
);
2140 recog_data
.n_operands
= 0;
2141 recog_data
.n_alternatives
= 0;
2142 recog_data
.n_dups
= 0;
2143 recog_data
.is_asm
= false;
2145 switch (GET_CODE (body
))
2156 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2161 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2162 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2163 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2169 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2172 /* This insn is an `asm' with operands. */
2174 /* expand_asm_operands makes sure there aren't too many operands. */
2175 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2177 /* Now get the operand values and constraints out of the insn. */
2178 decode_asm_operands (body
, recog_data
.operand
,
2179 recog_data
.operand_loc
,
2180 recog_data
.constraints
,
2181 recog_data
.operand_mode
, NULL
);
2182 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2185 const char *p
= recog_data
.constraints
[0];
2186 recog_data
.n_alternatives
= 1;
2188 recog_data
.n_alternatives
+= (*p
++ == ',');
2190 recog_data
.is_asm
= true;
2193 fatal_insn_not_found (insn
);
2197 /* Ordinary insn: recognize it, get the operands via insn_extract
2198 and get the constraints. */
2200 icode
= recog_memoized (insn
);
2202 fatal_insn_not_found (insn
);
2204 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2205 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2206 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2208 insn_extract (insn
);
2210 for (i
= 0; i
< noperands
; i
++)
2212 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2213 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2214 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2215 /* VOIDmode match_operands gets mode from their real operand. */
2216 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2217 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2220 for (i
= 0; i
< noperands
; i
++)
2221 recog_data
.operand_type
[i
]
2222 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2223 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2226 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2228 if (INSN_CODE (insn
) < 0)
2229 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2230 recog_data
.alternative_enabled_p
[i
] = true;
2233 recog_data
.insn
= insn
;
2234 for (i
= 0; i
< recog_data
.n_alternatives
; i
++)
2236 which_alternative
= i
;
2237 recog_data
.alternative_enabled_p
[i
]
2238 = HAVE_ATTR_enabled
? get_attr_enabled (insn
) : 1;
2242 recog_data
.insn
= NULL
;
2243 which_alternative
= -1;
2246 /* After calling extract_insn, you can use this function to extract some
2247 information from the constraint strings into a more usable form.
2248 The collected data is stored in recog_op_alt. */
2250 preprocess_constraints (void)
2254 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2255 memset (recog_op_alt
[i
], 0, (recog_data
.n_alternatives
2256 * sizeof (struct operand_alternative
)));
2258 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2261 struct operand_alternative
*op_alt
;
2262 const char *p
= recog_data
.constraints
[i
];
2264 op_alt
= recog_op_alt
[i
];
2266 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2268 op_alt
[j
].cl
= NO_REGS
;
2269 op_alt
[j
].constraint
= p
;
2270 op_alt
[j
].matches
= -1;
2271 op_alt
[j
].matched
= -1;
2273 if (!recog_data
.alternative_enabled_p
[j
])
2275 p
= skip_alternative (p
);
2279 if (*p
== '\0' || *p
== ',')
2281 op_alt
[j
].anything_ok
= 1;
2291 while (c
!= ',' && c
!= '\0');
2292 if (c
== ',' || c
== '\0')
2300 case '=': case '+': case '*': case '%':
2301 case 'E': case 'F': case 'G': case 'H':
2302 case 's': case 'i': case 'n':
2303 case 'I': case 'J': case 'K': case 'L':
2304 case 'M': case 'N': case 'O': case 'P':
2305 /* These don't say anything we care about. */
2309 op_alt
[j
].reject
+= 6;
2312 op_alt
[j
].reject
+= 600;
2315 op_alt
[j
].earlyclobber
= 1;
2318 case '0': case '1': case '2': case '3': case '4':
2319 case '5': case '6': case '7': case '8': case '9':
2322 op_alt
[j
].matches
= strtoul (p
, &end
, 10);
2323 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2328 case TARGET_MEM_CONSTRAINT
:
2329 op_alt
[j
].memory_ok
= 1;
2332 op_alt
[j
].decmem_ok
= 1;
2335 op_alt
[j
].incmem_ok
= 1;
2338 op_alt
[j
].nonoffmem_ok
= 1;
2341 op_alt
[j
].offmem_ok
= 1;
2344 op_alt
[j
].anything_ok
= 1;
2348 op_alt
[j
].is_address
= 1;
2349 op_alt
[j
].cl
= reg_class_subunion
[(int) op_alt
[j
].cl
]
2350 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2357 reg_class_subunion
[(int) op_alt
[j
].cl
][(int) GENERAL_REGS
];
2361 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
2363 op_alt
[j
].memory_ok
= 1;
2366 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2368 op_alt
[j
].is_address
= 1;
2370 = (reg_class_subunion
2371 [(int) op_alt
[j
].cl
]
2372 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2373 ADDRESS
, SCRATCH
)]);
2378 = (reg_class_subunion
2379 [(int) op_alt
[j
].cl
]
2380 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
2383 p
+= CONSTRAINT_LEN (c
, p
);
2389 /* Check the operands of an insn against the insn's operand constraints
2390 and return 1 if they are valid.
2391 The information about the insn's operands, constraints, operand modes
2392 etc. is obtained from the global variables set up by extract_insn.
2394 WHICH_ALTERNATIVE is set to a number which indicates which
2395 alternative of constraints was matched: 0 for the first alternative,
2396 1 for the next, etc.
2398 In addition, when two operands are required to match
2399 and it happens that the output operand is (reg) while the
2400 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2401 make the output operand look like the input.
2402 This is because the output operand is the one the template will print.
2404 This is used in final, just before printing the assembler code and by
2405 the routines that determine an insn's attribute.
2407 If STRICT is a positive nonzero value, it means that we have been
2408 called after reload has been completed. In that case, we must
2409 do all checks strictly. If it is zero, it means that we have been called
2410 before reload has completed. In that case, we first try to see if we can
2411 find an alternative that matches strictly. If not, we try again, this
2412 time assuming that reload will fix up the insn. This provides a "best
2413 guess" for the alternative and is used to compute attributes of insns prior
2414 to reload. A negative value of STRICT is used for this internal call. */
2422 constrain_operands (int strict
)
2424 const char *constraints
[MAX_RECOG_OPERANDS
];
2425 int matching_operands
[MAX_RECOG_OPERANDS
];
2426 int earlyclobber
[MAX_RECOG_OPERANDS
];
2429 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2430 int funny_match_index
;
2432 which_alternative
= 0;
2433 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2436 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2438 constraints
[c
] = recog_data
.constraints
[c
];
2439 matching_operands
[c
] = -1;
2444 int seen_earlyclobber_at
= -1;
2447 funny_match_index
= 0;
2449 if (!recog_data
.alternative_enabled_p
[which_alternative
])
2453 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2454 constraints
[i
] = skip_alternative (constraints
[i
]);
2456 which_alternative
++;
2460 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2462 rtx op
= recog_data
.operand
[opno
];
2463 enum machine_mode mode
= GET_MODE (op
);
2464 const char *p
= constraints
[opno
];
2470 earlyclobber
[opno
] = 0;
2472 /* A unary operator may be accepted by the predicate, but it
2473 is irrelevant for matching constraints. */
2477 if (GET_CODE (op
) == SUBREG
)
2479 if (REG_P (SUBREG_REG (op
))
2480 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2481 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2482 GET_MODE (SUBREG_REG (op
)),
2485 op
= SUBREG_REG (op
);
2488 /* An empty constraint or empty alternative
2489 allows anything which matched the pattern. */
2490 if (*p
== 0 || *p
== ',')
2494 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2503 case '?': case '!': case '*': case '%':
2508 /* Ignore rest of this alternative as far as
2509 constraint checking is concerned. */
2512 while (*p
&& *p
!= ',');
2517 earlyclobber
[opno
] = 1;
2518 if (seen_earlyclobber_at
< 0)
2519 seen_earlyclobber_at
= opno
;
2522 case '0': case '1': case '2': case '3': case '4':
2523 case '5': case '6': case '7': case '8': case '9':
2525 /* This operand must be the same as a previous one.
2526 This kind of constraint is used for instructions such
2527 as add when they take only two operands.
2529 Note that the lower-numbered operand is passed first.
2531 If we are not testing strictly, assume that this
2532 constraint will be satisfied. */
2537 match
= strtoul (p
, &end
, 10);
2544 rtx op1
= recog_data
.operand
[match
];
2545 rtx op2
= recog_data
.operand
[opno
];
2547 /* A unary operator may be accepted by the predicate,
2548 but it is irrelevant for matching constraints. */
2550 op1
= XEXP (op1
, 0);
2552 op2
= XEXP (op2
, 0);
2554 val
= operands_match_p (op1
, op2
);
2557 matching_operands
[opno
] = match
;
2558 matching_operands
[match
] = opno
;
2563 /* If output is *x and input is *--x, arrange later
2564 to change the output to *--x as well, since the
2565 output op is the one that will be printed. */
2566 if (val
== 2 && strict
> 0)
2568 funny_match
[funny_match_index
].this_op
= opno
;
2569 funny_match
[funny_match_index
++].other
= match
;
2576 /* p is used for address_operands. When we are called by
2577 gen_reload, no one will have checked that the address is
2578 strictly valid, i.e., that all pseudos requiring hard regs
2579 have gotten them. */
2581 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2586 /* No need to check general_operand again;
2587 it was done in insn-recog.c. Well, except that reload
2588 doesn't check the validity of its replacements, but
2589 that should only matter when there's a bug. */
2591 /* Anything goes unless it is a REG and really has a hard reg
2592 but the hard reg is not in the class GENERAL_REGS. */
2596 || GENERAL_REGS
== ALL_REGS
2597 || (reload_in_progress
2598 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2599 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2602 else if (strict
< 0 || general_operand (op
, mode
))
2607 /* This is used for a MATCH_SCRATCH in the cases when
2608 we don't actually need anything. So anything goes
2613 case TARGET_MEM_CONSTRAINT
:
2614 /* Memory operands must be valid, to the extent
2615 required by STRICT. */
2619 && !strict_memory_address_addr_space_p
2620 (GET_MODE (op
), XEXP (op
, 0),
2621 MEM_ADDR_SPACE (op
)))
2624 && !memory_address_addr_space_p
2625 (GET_MODE (op
), XEXP (op
, 0),
2626 MEM_ADDR_SPACE (op
)))
2630 /* Before reload, accept what reload can turn into a mem. */
2631 else if (strict
< 0 && CONSTANT_P (op
))
2633 /* Before reload, accept a pseudo,
2634 since LRA can turn it into a mem. */
2635 else if (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2636 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2638 /* During reload, accept a pseudo */
2639 else if (reload_in_progress
&& REG_P (op
)
2640 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2646 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2647 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2653 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2654 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2660 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2661 || (GET_CODE (op
) == CONST_VECTOR
2662 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
))
2668 if (CONST_DOUBLE_AS_FLOAT_P (op
)
2669 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
2674 if (CONST_SCALAR_INT_P (op
))
2677 if (CONSTANT_P (op
))
2682 if (CONST_SCALAR_INT_P (op
))
2694 if (CONST_INT_P (op
)
2695 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
2701 && ((strict
> 0 && ! offsettable_memref_p (op
))
2703 && !(CONSTANT_P (op
) || MEM_P (op
)))
2704 || (reload_in_progress
2706 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2711 if ((strict
> 0 && offsettable_memref_p (op
))
2712 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2713 /* Before reload, accept what reload can handle. */
2715 && (CONSTANT_P (op
) || MEM_P (op
)))
2716 /* Before reload, accept a pseudo,
2717 since LRA can turn it into a mem. */
2718 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2719 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2720 /* During reload, accept a pseudo */
2721 || (reload_in_progress
&& REG_P (op
)
2722 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2731 ? GENERAL_REGS
: REG_CLASS_FROM_CONSTRAINT (c
, p
));
2737 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2738 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2740 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2743 #ifdef EXTRA_CONSTRAINT_STR
2744 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2747 else if (EXTRA_MEMORY_CONSTRAINT (c
, p
)
2748 /* Every memory operand can be reloaded to fit. */
2749 && ((strict
< 0 && MEM_P (op
))
2750 /* Before reload, accept what reload can turn
2752 || (strict
< 0 && CONSTANT_P (op
))
2753 /* Before reload, accept a pseudo,
2754 since LRA can turn it into a mem. */
2755 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2756 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2757 /* During reload, accept a pseudo */
2758 || (reload_in_progress
&& REG_P (op
)
2759 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2761 else if (EXTRA_ADDRESS_CONSTRAINT (c
, p
)
2762 /* Every address operand can be reloaded to fit. */
2765 /* Cater to architectures like IA-64 that define extra memory
2766 constraints without using define_memory_constraint. */
2767 else if (reload_in_progress
2769 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2770 && reg_renumber
[REGNO (op
)] < 0
2771 && reg_equiv_mem (REGNO (op
)) != 0
2772 && EXTRA_CONSTRAINT_STR
2773 (reg_equiv_mem (REGNO (op
)), c
, p
))
2779 while (p
+= len
, c
);
2781 constraints
[opno
] = p
;
2782 /* If this operand did not win somehow,
2783 this alternative loses. */
2787 /* This alternative won; the operands are ok.
2788 Change whichever operands this alternative says to change. */
2793 /* See if any earlyclobber operand conflicts with some other
2796 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2797 for (eopno
= seen_earlyclobber_at
;
2798 eopno
< recog_data
.n_operands
;
2800 /* Ignore earlyclobber operands now in memory,
2801 because we would often report failure when we have
2802 two memory operands, one of which was formerly a REG. */
2803 if (earlyclobber
[eopno
]
2804 && REG_P (recog_data
.operand
[eopno
]))
2805 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2806 if ((MEM_P (recog_data
.operand
[opno
])
2807 || recog_data
.operand_type
[opno
] != OP_OUT
)
2809 /* Ignore things like match_operator operands. */
2810 && *recog_data
.constraints
[opno
] != 0
2811 && ! (matching_operands
[opno
] == eopno
2812 && operands_match_p (recog_data
.operand
[opno
],
2813 recog_data
.operand
[eopno
]))
2814 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2815 recog_data
.operand
[eopno
]))
2820 while (--funny_match_index
>= 0)
2822 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2823 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2827 /* For operands without < or > constraints reject side-effects. */
2828 if (recog_data
.is_asm
)
2830 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2831 if (MEM_P (recog_data
.operand
[opno
]))
2832 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2840 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2841 && strchr (recog_data
.constraints
[opno
], '>')
2854 which_alternative
++;
2856 while (which_alternative
< recog_data
.n_alternatives
);
2858 which_alternative
= -1;
2859 /* If we are about to reject this, but we are not to test strictly,
2860 try a very loose test. Only return failure if it fails also. */
2862 return constrain_operands (-1);
2867 /* Return true iff OPERAND (assumed to be a REG rtx)
2868 is a hard reg in class CLASS when its regno is offset by OFFSET
2869 and changed to mode MODE.
2870 If REG occupies multiple hard regs, all of them must be in CLASS. */
2873 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2874 enum machine_mode mode
)
2876 unsigned int regno
= REGNO (operand
);
2881 /* Regno must not be a pseudo register. Offset may be negative. */
2882 return (HARD_REGISTER_NUM_P (regno
)
2883 && HARD_REGISTER_NUM_P (regno
+ offset
)
2884 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2888 /* Split single instruction. Helper function for split_all_insns and
2889 split_all_insns_noflow. Return last insn in the sequence if successful,
2890 or NULL if unsuccessful. */
2893 split_insn (rtx insn
)
2895 /* Split insns here to get max fine-grain parallelism. */
2896 rtx first
= PREV_INSN (insn
);
2897 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2898 rtx insn_set
, last_set
, note
;
2903 /* If the original instruction was a single set that was known to be
2904 equivalent to a constant, see if we can say the same about the last
2905 instruction in the split sequence. The two instructions must set
2906 the same destination. */
2907 insn_set
= single_set (insn
);
2910 last_set
= single_set (last
);
2911 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2913 note
= find_reg_equal_equiv_note (insn
);
2914 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2915 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2916 else if (CONSTANT_P (SET_SRC (insn_set
)))
2917 set_unique_reg_note (last
, REG_EQUAL
,
2918 copy_rtx (SET_SRC (insn_set
)));
2922 /* try_split returns the NOTE that INSN became. */
2923 SET_INSN_DELETED (insn
);
2925 /* ??? Coddle to md files that generate subregs in post-reload
2926 splitters instead of computing the proper hard register. */
2927 if (reload_completed
&& first
!= last
)
2929 first
= NEXT_INSN (first
);
2933 cleanup_subreg_operands (first
);
2936 first
= NEXT_INSN (first
);
2943 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2946 split_all_insns (void)
2952 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2953 bitmap_clear (blocks
);
2956 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2959 bool finish
= false;
2961 rtl_profile_for_bb (bb
);
2962 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2964 /* Can't use `next_real_insn' because that might go across
2965 CODE_LABELS and short-out basic blocks. */
2966 next
= NEXT_INSN (insn
);
2967 finish
= (insn
== BB_END (bb
));
2970 rtx set
= single_set (insn
);
2972 /* Don't split no-op move insns. These should silently
2973 disappear later in final. Splitting such insns would
2974 break the code that handles LIBCALL blocks. */
2975 if (set
&& set_noop_p (set
))
2977 /* Nops get in the way while scheduling, so delete them
2978 now if register allocation has already been done. It
2979 is too risky to try to do this before register
2980 allocation, and there are unlikely to be very many
2981 nops then anyways. */
2982 if (reload_completed
)
2983 delete_insn_and_edges (insn
);
2987 if (split_insn (insn
))
2989 bitmap_set_bit (blocks
, bb
->index
);
2997 default_rtl_profile ();
2999 find_many_sub_basic_blocks (blocks
);
3001 #ifdef ENABLE_CHECKING
3002 verify_flow_info ();
3005 sbitmap_free (blocks
);
3008 /* Same as split_all_insns, but do not expect CFG to be available.
3009 Used by machine dependent reorg passes. */
3012 split_all_insns_noflow (void)
3016 for (insn
= get_insns (); insn
; insn
= next
)
3018 next
= NEXT_INSN (insn
);
3021 /* Don't split no-op move insns. These should silently
3022 disappear later in final. Splitting such insns would
3023 break the code that handles LIBCALL blocks. */
3024 rtx set
= single_set (insn
);
3025 if (set
&& set_noop_p (set
))
3027 /* Nops get in the way while scheduling, so delete them
3028 now if register allocation has already been done. It
3029 is too risky to try to do this before register
3030 allocation, and there are unlikely to be very many
3033 ??? Should we use delete_insn when the CFG isn't valid? */
3034 if (reload_completed
)
3035 delete_insn_and_edges (insn
);
3044 #ifdef HAVE_peephole2
3045 struct peep2_insn_data
3051 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3052 static int peep2_current
;
3054 static bool peep2_do_rebuild_jump_labels
;
3055 static bool peep2_do_cleanup_cfg
;
3057 /* The number of instructions available to match a peep2. */
3058 int peep2_current_count
;
3060 /* A non-insn marker indicating the last insn of the block.
3061 The live_before regset for this element is correct, indicating
3062 DF_LIVE_OUT for the block. */
3063 #define PEEP2_EOB pc_rtx
3065 /* Wrap N to fit into the peep2_insn_data buffer. */
3068 peep2_buf_position (int n
)
3070 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3071 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3075 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3076 does not exist. Used by the recognizer to find the next insn to match
3077 in a multi-insn pattern. */
3080 peep2_next_insn (int n
)
3082 gcc_assert (n
<= peep2_current_count
);
3084 n
= peep2_buf_position (peep2_current
+ n
);
3086 return peep2_insn_data
[n
].insn
;
3089 /* Return true if REGNO is dead before the Nth non-note insn
3093 peep2_regno_dead_p (int ofs
, int regno
)
3095 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3097 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3099 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3101 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3104 /* Similarly for a REG. */
3107 peep2_reg_dead_p (int ofs
, rtx reg
)
3111 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3113 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3115 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3117 regno
= REGNO (reg
);
3118 n
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
3120 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
3125 /* Regno offset to be used in the register search. */
3126 static int search_ofs
;
3128 /* Try to find a hard register of mode MODE, matching the register class in
3129 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3130 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3131 in which case the only condition is that the register must be available
3132 before CURRENT_INSN.
3133 Registers that already have bits set in REG_SET will not be considered.
3135 If an appropriate register is available, it will be returned and the
3136 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3140 peep2_find_free_register (int from
, int to
, const char *class_str
,
3141 enum machine_mode mode
, HARD_REG_SET
*reg_set
)
3148 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3149 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3151 from
= peep2_buf_position (peep2_current
+ from
);
3152 to
= peep2_buf_position (peep2_current
+ to
);
3154 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3155 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3159 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3161 /* Don't use registers set or clobbered by the insn. */
3162 for (def_rec
= DF_INSN_DEFS (peep2_insn_data
[from
].insn
);
3163 *def_rec
; def_rec
++)
3164 SET_HARD_REG_BIT (live
, DF_REF_REGNO (*def_rec
));
3166 from
= peep2_buf_position (from
+ 1);
3169 cl
= (class_str
[0] == 'r' ? GENERAL_REGS
3170 : REG_CLASS_FROM_CONSTRAINT (class_str
[0], class_str
));
3172 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3174 int raw_regno
, regno
, success
, j
;
3176 /* Distribute the free registers as much as possible. */
3177 raw_regno
= search_ofs
+ i
;
3178 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3179 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3180 #ifdef REG_ALLOC_ORDER
3181 regno
= reg_alloc_order
[raw_regno
];
3186 /* Can it support the mode we need? */
3187 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3191 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3193 /* Don't allocate fixed registers. */
3194 if (fixed_regs
[regno
+ j
])
3199 /* Don't allocate global registers. */
3200 if (global_regs
[regno
+ j
])
3205 /* Make sure the register is of the right class. */
3206 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3211 /* And that we don't create an extra save/restore. */
3212 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3218 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3224 /* And we don't clobber traceback for noreturn functions. */
3225 if ((regno
+ j
== FRAME_POINTER_REGNUM
3226 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3227 && (! reload_completed
|| frame_pointer_needed
))
3233 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3234 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3243 add_to_hard_reg_set (reg_set
, mode
, regno
);
3245 /* Start the next search with the next register. */
3246 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3248 search_ofs
= raw_regno
;
3250 return gen_rtx_REG (mode
, regno
);
3258 /* Forget all currently tracked instructions, only remember current
3262 peep2_reinit_state (regset live
)
3266 /* Indicate that all slots except the last holds invalid data. */
3267 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3268 peep2_insn_data
[i
].insn
= NULL_RTX
;
3269 peep2_current_count
= 0;
3271 /* Indicate that the last slot contains live_after data. */
3272 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3273 peep2_current
= MAX_INSNS_PER_PEEP2
;
3275 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3278 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3279 starting at INSN. Perform the replacement, removing the old insns and
3280 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3281 if the replacement is rejected. */
3284 peep2_attempt (basic_block bb
, rtx insn
, int match_len
, rtx attempt
)
3287 rtx last
, eh_note
, as_note
, before_try
, x
;
3288 rtx old_insn
, new_insn
;
3289 bool was_call
= false;
3291 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3292 match more than one insn, or to be split into more than one insn. */
3293 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3294 if (RTX_FRAME_RELATED_P (old_insn
))
3296 bool any_note
= false;
3302 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3303 may be in the stream for the purpose of register allocation. */
3304 if (active_insn_p (attempt
))
3307 new_insn
= next_active_insn (attempt
);
3308 if (next_active_insn (new_insn
))
3311 /* We have a 1-1 replacement. Copy over any frame-related info. */
3312 RTX_FRAME_RELATED_P (new_insn
) = 1;
3314 /* Allow the backend to fill in a note during the split. */
3315 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3316 switch (REG_NOTE_KIND (note
))
3318 case REG_FRAME_RELATED_EXPR
:
3319 case REG_CFA_DEF_CFA
:
3320 case REG_CFA_ADJUST_CFA
:
3321 case REG_CFA_OFFSET
:
3322 case REG_CFA_REGISTER
:
3323 case REG_CFA_EXPRESSION
:
3324 case REG_CFA_RESTORE
:
3325 case REG_CFA_SET_VDRAP
:
3332 /* If the backend didn't supply a note, copy one over. */
3334 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3335 switch (REG_NOTE_KIND (note
))
3337 case REG_FRAME_RELATED_EXPR
:
3338 case REG_CFA_DEF_CFA
:
3339 case REG_CFA_ADJUST_CFA
:
3340 case REG_CFA_OFFSET
:
3341 case REG_CFA_REGISTER
:
3342 case REG_CFA_EXPRESSION
:
3343 case REG_CFA_RESTORE
:
3344 case REG_CFA_SET_VDRAP
:
3345 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3352 /* If there still isn't a note, make sure the unwind info sees the
3353 same expression as before the split. */
3356 rtx old_set
, new_set
;
3358 /* The old insn had better have been simple, or annotated. */
3359 old_set
= single_set (old_insn
);
3360 gcc_assert (old_set
!= NULL
);
3362 new_set
= single_set (new_insn
);
3363 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3364 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3367 /* Copy prologue/epilogue status. This is required in order to keep
3368 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3369 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3372 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3373 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3374 cfg-related call notes. */
3375 for (i
= 0; i
<= match_len
; ++i
)
3380 j
= peep2_buf_position (peep2_current
+ i
);
3381 old_insn
= peep2_insn_data
[j
].insn
;
3382 if (!CALL_P (old_insn
))
3387 while (new_insn
!= NULL_RTX
)
3389 if (CALL_P (new_insn
))
3391 new_insn
= NEXT_INSN (new_insn
);
3394 gcc_assert (new_insn
!= NULL_RTX
);
3396 CALL_INSN_FUNCTION_USAGE (new_insn
)
3397 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3399 for (note
= REG_NOTES (old_insn
);
3401 note
= XEXP (note
, 1))
3402 switch (REG_NOTE_KIND (note
))
3407 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3411 /* Discard all other reg notes. */
3415 /* Croak if there is another call in the sequence. */
3416 while (++i
<= match_len
)
3418 j
= peep2_buf_position (peep2_current
+ i
);
3419 old_insn
= peep2_insn_data
[j
].insn
;
3420 gcc_assert (!CALL_P (old_insn
));
3425 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3426 move those notes over to the new sequence. */
3428 for (i
= match_len
; i
>= 0; --i
)
3430 int j
= peep2_buf_position (peep2_current
+ i
);
3431 old_insn
= peep2_insn_data
[j
].insn
;
3433 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3438 i
= peep2_buf_position (peep2_current
+ match_len
);
3439 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3441 /* Replace the old sequence with the new. */
3442 last
= emit_insn_after_setloc (attempt
,
3443 peep2_insn_data
[i
].insn
,
3444 INSN_LOCATION (peep2_insn_data
[i
].insn
));
3445 before_try
= PREV_INSN (insn
);
3446 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3448 /* Re-insert the EH_REGION notes. */
3449 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3454 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3455 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3459 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3462 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3463 if (x
!= BB_END (bb
)
3464 && (can_throw_internal (x
)
3465 || can_nonlocal_goto (x
)))
3470 nfte
= split_block (bb
, x
);
3471 flags
= (eh_edge
->flags
3472 & (EDGE_EH
| EDGE_ABNORMAL
));
3474 flags
|= EDGE_ABNORMAL_CALL
;
3475 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3478 nehe
->probability
= eh_edge
->probability
;
3480 = REG_BR_PROB_BASE
- nehe
->probability
;
3482 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3487 /* Converting possibly trapping insn to non-trapping is
3488 possible. Zap dummy outgoing edges. */
3489 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3492 /* Re-insert the ARGS_SIZE notes. */
3494 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3496 /* If we generated a jump instruction, it won't have
3497 JUMP_LABEL set. Recompute after we're done. */
3498 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3501 peep2_do_rebuild_jump_labels
= true;
3508 /* After performing a replacement in basic block BB, fix up the life
3509 information in our buffer. LAST is the last of the insns that we
3510 emitted as a replacement. PREV is the insn before the start of
3511 the replacement. MATCH_LEN is the number of instructions that were
3512 matched, and which now need to be replaced in the buffer. */
3515 peep2_update_life (basic_block bb
, int match_len
, rtx last
, rtx prev
)
3517 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3521 INIT_REG_SET (&live
);
3522 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3524 gcc_assert (peep2_current_count
>= match_len
+ 1);
3525 peep2_current_count
-= match_len
+ 1;
3533 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3535 peep2_current_count
++;
3537 i
= MAX_INSNS_PER_PEEP2
;
3538 peep2_insn_data
[i
].insn
= x
;
3539 df_simulate_one_insn_backwards (bb
, x
, &live
);
3540 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3546 CLEAR_REG_SET (&live
);
3551 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3552 Return true if we added it, false otherwise. The caller will try to match
3553 peepholes against the buffer if we return false; otherwise it will try to
3554 add more instructions to the buffer. */
3557 peep2_fill_buffer (basic_block bb
, rtx insn
, regset live
)
3561 /* Once we have filled the maximum number of insns the buffer can hold,
3562 allow the caller to match the insns against peepholes. We wait until
3563 the buffer is full in case the target has similar peepholes of different
3564 length; we always want to match the longest if possible. */
3565 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3568 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3569 any other pattern, lest it change the semantics of the frame info. */
3570 if (RTX_FRAME_RELATED_P (insn
))
3572 /* Let the buffer drain first. */
3573 if (peep2_current_count
> 0)
3575 /* Now the insn will be the only thing in the buffer. */
3578 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3579 peep2_insn_data
[pos
].insn
= insn
;
3580 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3581 peep2_current_count
++;
3583 df_simulate_one_insn_forwards (bb
, insn
, live
);
3587 /* Perform the peephole2 optimization pass. */
3590 peephole2_optimize (void)
3597 peep2_do_cleanup_cfg
= false;
3598 peep2_do_rebuild_jump_labels
= false;
3600 df_set_flags (DF_LR_RUN_DCE
);
3601 df_note_add_problem ();
3604 /* Initialize the regsets we're going to use. */
3605 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3606 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3608 live
= BITMAP_ALLOC (®_obstack
);
3610 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3612 bool past_end
= false;
3615 rtl_profile_for_bb (bb
);
3617 /* Start up propagation. */
3618 bitmap_copy (live
, DF_LR_IN (bb
));
3619 df_simulate_initialize_forwards (bb
, live
);
3620 peep2_reinit_state (live
);
3622 insn
= BB_HEAD (bb
);
3628 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3631 insn
= NEXT_INSN (insn
);
3632 if (insn
== NEXT_INSN (BB_END (bb
)))
3636 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3639 /* If we did not fill an empty buffer, it signals the end of the
3641 if (peep2_current_count
== 0)
3644 /* The buffer filled to the current maximum, so try to match. */
3646 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3647 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3648 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3650 /* Match the peephole. */
3651 head
= peep2_insn_data
[peep2_current
].insn
;
3652 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3653 if (attempt
!= NULL
)
3655 rtx last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3658 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3663 /* No match: advance the buffer by one insn. */
3664 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3665 peep2_current_count
--;
3669 default_rtl_profile ();
3670 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3671 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3673 if (peep2_do_rebuild_jump_labels
)
3674 rebuild_jump_labels (get_insns ());
3675 if (peep2_do_cleanup_cfg
)
3676 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3678 #endif /* HAVE_peephole2 */
3680 /* Common predicates for use with define_bypass. */
3682 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3683 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3684 must be either a single_set or a PARALLEL with SETs inside. */
3687 store_data_bypass_p (rtx out_insn
, rtx in_insn
)
3689 rtx out_set
, in_set
;
3690 rtx out_pat
, in_pat
;
3691 rtx out_exp
, in_exp
;
3694 in_set
= single_set (in_insn
);
3697 if (!MEM_P (SET_DEST (in_set
)))
3700 out_set
= single_set (out_insn
);
3703 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3708 out_pat
= PATTERN (out_insn
);
3710 if (GET_CODE (out_pat
) != PARALLEL
)
3713 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3715 out_exp
= XVECEXP (out_pat
, 0, i
);
3717 if (GET_CODE (out_exp
) == CLOBBER
)
3720 gcc_assert (GET_CODE (out_exp
) == SET
);
3722 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3729 in_pat
= PATTERN (in_insn
);
3730 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3732 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3734 in_exp
= XVECEXP (in_pat
, 0, i
);
3736 if (GET_CODE (in_exp
) == CLOBBER
)
3739 gcc_assert (GET_CODE (in_exp
) == SET
);
3741 if (!MEM_P (SET_DEST (in_exp
)))
3744 out_set
= single_set (out_insn
);
3747 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3752 out_pat
= PATTERN (out_insn
);
3753 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3755 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3757 out_exp
= XVECEXP (out_pat
, 0, j
);
3759 if (GET_CODE (out_exp
) == CLOBBER
)
3762 gcc_assert (GET_CODE (out_exp
) == SET
);
3764 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3774 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3775 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3776 or multiple set; IN_INSN should be single_set for truth, but for convenience
3777 of insn categorization may be any JUMP or CALL insn. */
3780 if_test_bypass_p (rtx out_insn
, rtx in_insn
)
3782 rtx out_set
, in_set
;
3784 in_set
= single_set (in_insn
);
3787 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3791 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3793 in_set
= SET_SRC (in_set
);
3795 out_set
= single_set (out_insn
);
3798 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3799 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3807 out_pat
= PATTERN (out_insn
);
3808 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3810 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3812 rtx exp
= XVECEXP (out_pat
, 0, i
);
3814 if (GET_CODE (exp
) == CLOBBER
)
3817 gcc_assert (GET_CODE (exp
) == SET
);
3819 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3820 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3829 gate_handle_peephole2 (void)
3831 return (optimize
> 0 && flag_peephole2
);
3835 rest_of_handle_peephole2 (void)
3837 #ifdef HAVE_peephole2
3838 peephole2_optimize ();
3845 const pass_data pass_data_peephole2
=
3847 RTL_PASS
, /* type */
3848 "peephole2", /* name */
3849 OPTGROUP_NONE
, /* optinfo_flags */
3850 true, /* has_gate */
3851 true, /* has_execute */
3852 TV_PEEPHOLE2
, /* tv_id */
3853 0, /* properties_required */
3854 0, /* properties_provided */
3855 0, /* properties_destroyed */
3856 0, /* todo_flags_start */
3857 ( TODO_df_finish
| TODO_verify_rtl_sharing
| 0 ), /* todo_flags_finish */
3860 class pass_peephole2
: public rtl_opt_pass
3863 pass_peephole2 (gcc::context
*ctxt
)
3864 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3867 /* opt_pass methods: */
3868 /* The epiphany backend creates a second instance of this pass, so we need
3870 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3871 bool gate () { return gate_handle_peephole2 (); }
3872 unsigned int execute () { return rest_of_handle_peephole2 (); }
3874 }; // class pass_peephole2
3879 make_pass_peephole2 (gcc::context
*ctxt
)
3881 return new pass_peephole2 (ctxt
);
3885 rest_of_handle_split_all_insns (void)
3893 const pass_data pass_data_split_all_insns
=
3895 RTL_PASS
, /* type */
3896 "split1", /* name */
3897 OPTGROUP_NONE
, /* optinfo_flags */
3898 false, /* has_gate */
3899 true, /* has_execute */
3900 TV_NONE
, /* tv_id */
3901 0, /* properties_required */
3902 0, /* properties_provided */
3903 0, /* properties_destroyed */
3904 0, /* todo_flags_start */
3905 0, /* todo_flags_finish */
3908 class pass_split_all_insns
: public rtl_opt_pass
3911 pass_split_all_insns (gcc::context
*ctxt
)
3912 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3915 /* opt_pass methods: */
3916 /* The epiphany backend creates a second instance of this pass, so
3917 we need a clone method. */
3918 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3919 unsigned int execute () { return rest_of_handle_split_all_insns (); }
3921 }; // class pass_split_all_insns
3926 make_pass_split_all_insns (gcc::context
*ctxt
)
3928 return new pass_split_all_insns (ctxt
);
3932 rest_of_handle_split_after_reload (void)
3934 /* If optimizing, then go ahead and split insns now. */
3944 const pass_data pass_data_split_after_reload
=
3946 RTL_PASS
, /* type */
3947 "split2", /* name */
3948 OPTGROUP_NONE
, /* optinfo_flags */
3949 false, /* has_gate */
3950 true, /* has_execute */
3951 TV_NONE
, /* tv_id */
3952 0, /* properties_required */
3953 0, /* properties_provided */
3954 0, /* properties_destroyed */
3955 0, /* todo_flags_start */
3956 0, /* todo_flags_finish */
3959 class pass_split_after_reload
: public rtl_opt_pass
3962 pass_split_after_reload (gcc::context
*ctxt
)
3963 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3966 /* opt_pass methods: */
3967 unsigned int execute () { return rest_of_handle_split_after_reload (); }
3969 }; // class pass_split_after_reload
3974 make_pass_split_after_reload (gcc::context
*ctxt
)
3976 return new pass_split_after_reload (ctxt
);
3980 gate_handle_split_before_regstack (void)
3982 #if HAVE_ATTR_length && defined (STACK_REGS)
3983 /* If flow2 creates new instructions which need splitting
3984 and scheduling after reload is not done, they might not be
3985 split until final which doesn't allow splitting
3986 if HAVE_ATTR_length. */
3987 # ifdef INSN_SCHEDULING
3988 return (optimize
&& !flag_schedule_insns_after_reload
);
3998 rest_of_handle_split_before_regstack (void)
4006 const pass_data pass_data_split_before_regstack
=
4008 RTL_PASS
, /* type */
4009 "split3", /* name */
4010 OPTGROUP_NONE
, /* optinfo_flags */
4011 true, /* has_gate */
4012 true, /* has_execute */
4013 TV_NONE
, /* tv_id */
4014 0, /* properties_required */
4015 0, /* properties_provided */
4016 0, /* properties_destroyed */
4017 0, /* todo_flags_start */
4018 0, /* todo_flags_finish */
4021 class pass_split_before_regstack
: public rtl_opt_pass
4024 pass_split_before_regstack (gcc::context
*ctxt
)
4025 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
4028 /* opt_pass methods: */
4029 bool gate () { return gate_handle_split_before_regstack (); }
4030 unsigned int execute () {
4031 return rest_of_handle_split_before_regstack ();
4034 }; // class pass_split_before_regstack
4039 make_pass_split_before_regstack (gcc::context
*ctxt
)
4041 return new pass_split_before_regstack (ctxt
);
4045 gate_handle_split_before_sched2 (void)
4047 #ifdef INSN_SCHEDULING
4048 return optimize
> 0 && flag_schedule_insns_after_reload
;
4055 rest_of_handle_split_before_sched2 (void)
4057 #ifdef INSN_SCHEDULING
4065 const pass_data pass_data_split_before_sched2
=
4067 RTL_PASS
, /* type */
4068 "split4", /* name */
4069 OPTGROUP_NONE
, /* optinfo_flags */
4070 true, /* has_gate */
4071 true, /* has_execute */
4072 TV_NONE
, /* tv_id */
4073 0, /* properties_required */
4074 0, /* properties_provided */
4075 0, /* properties_destroyed */
4076 0, /* todo_flags_start */
4077 TODO_verify_flow
, /* todo_flags_finish */
4080 class pass_split_before_sched2
: public rtl_opt_pass
4083 pass_split_before_sched2 (gcc::context
*ctxt
)
4084 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4087 /* opt_pass methods: */
4088 bool gate () { return gate_handle_split_before_sched2 (); }
4089 unsigned int execute () { return rest_of_handle_split_before_sched2 (); }
4091 }; // class pass_split_before_sched2
4096 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4098 return new pass_split_before_sched2 (ctxt
);
4101 /* The placement of the splitting that we do for shorten_branches
4102 depends on whether regstack is used by the target or not. */
4104 gate_do_final_split (void)
4106 #if HAVE_ATTR_length && !defined (STACK_REGS)
4115 const pass_data pass_data_split_for_shorten_branches
=
4117 RTL_PASS
, /* type */
4118 "split5", /* name */
4119 OPTGROUP_NONE
, /* optinfo_flags */
4120 true, /* has_gate */
4121 true, /* has_execute */
4122 TV_NONE
, /* tv_id */
4123 0, /* properties_required */
4124 0, /* properties_provided */
4125 0, /* properties_destroyed */
4126 0, /* todo_flags_start */
4127 TODO_verify_rtl_sharing
, /* todo_flags_finish */
4130 class pass_split_for_shorten_branches
: public rtl_opt_pass
4133 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4134 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4137 /* opt_pass methods: */
4138 bool gate () { return gate_do_final_split (); }
4139 unsigned int execute () { return split_all_insns_noflow (); }
4141 }; // class pass_split_for_shorten_branches
4146 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4148 return new pass_split_for_shorten_branches (ctxt
);