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1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS has a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The SPARC always has a branch delay slot, but its effects can be
43 annulled when the branch is not taken. This means that failing to
44 find other sources of insns, we can hoist an insn from the branch
45 target that would only be safe to execute knowing that the branch
46 is taken.
48 The HP-PA always has a branch delay slot. For unconditional branches
49 its effects can be annulled when the branch is taken. The effects
50 of the delay slot in a conditional branch can be nullified for forward
51 taken branches, or for untaken backward branches. This means
52 we can hoist insns from the fall-through path for forward branches or
53 steal insns from the target of backward branches.
55 The TMS320C3x and C4x have three branch delay slots. When the three
56 slots are filled, the branch penalty is zero. Most insns can fill the
57 delay slots except jump insns.
59 Three techniques for filling delay slots have been implemented so far:
61 (1) `fill_simple_delay_slots' is the simplest, most efficient way
62 to fill delay slots. This pass first looks for insns which come
63 from before the branch and which are safe to execute after the
64 branch. Then it searches after the insn requiring delay slots or,
65 in the case of a branch, for insns that are after the point at
66 which the branch merges into the fallthrough code, if such a point
67 exists. When such insns are found, the branch penalty decreases
68 and no code expansion takes place.
70 (2) `fill_eager_delay_slots' is more complicated: it is used for
71 scheduling conditional jumps, or for scheduling jumps which cannot
72 be filled using (1). A machine need not have annulled jumps to use
73 this strategy, but it helps (by keeping more options open).
74 `fill_eager_delay_slots' tries to guess the direction the branch
75 will go; if it guesses right 100% of the time, it can reduce the
76 branch penalty as much as `fill_simple_delay_slots' does. If it
77 guesses wrong 100% of the time, it might as well schedule nops. When
78 `fill_eager_delay_slots' takes insns from the fall-through path of
79 the jump, usually there is no code expansion; when it takes insns
80 from the branch target, there is code expansion if it is not the
81 only way to reach that target.
83 (3) `relax_delay_slots' uses a set of rules to simplify code that
84 has been reorganized by (1) and (2). It finds cases where
85 conditional test can be eliminated, jumps can be threaded, extra
86 insns can be eliminated, etc. It is the job of (1) and (2) to do a
87 good job of scheduling locally; `relax_delay_slots' takes care of
88 making the various individual schedules work well together. It is
89 especially tuned to handle the control flow interactions of branch
90 insns. It does nothing for insns with delay slots that do not
91 branch.
93 On machines that use CC0, we are very conservative. We will not make
94 a copy of an insn involving CC0 since we want to maintain a 1-1
95 correspondence between the insn that sets and uses CC0. The insns are
96 allowed to be separated by placing an insn that sets CC0 (but not an insn
97 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
98 delay slot. In that case, we point each insn at the other with REG_CC_USER
99 and REG_CC_SETTER notes. Note that these restrictions affect very few
100 machines because most RISC machines with delay slots will not use CC0
101 (the RT is the only known exception at this point). */
122 \f
123 /* First, some functions that were used before GCC got a control flow graph.
124 These functions are now only used here in reorg.c, and have therefore
125 been moved here to avoid inadvertent misuse elsewhere in the compiler. */
127 /* Return the last label to mark the same position as LABEL. Return LABEL
128 itself if it is null or any return rtx. */
130 static rtx
132 {
145 }
147 /* INSN uses CC0 and is being moved into a delay slot. Set up REG_CC_SETTER
148 and REG_CC_USER notes so we can find it. */
150 static void
152 {
160 }
161 \f
162 /* Insns which have delay slots that have not yet been filled. */
167 /* Define macros to refer to the first and last slot containing unfilled
168 insns. These are used because the list may move and its address
169 should be recomputed at each use. */
171 #define unfilled_slots_base \
172 ((rtx_insn **) obstack_base (&unfilled_slots_obstack))
174 #define unfilled_slots_next \
175 ((rtx_insn **) obstack_next_free (&unfilled_slots_obstack))
177 /* Points to the label before the end of the function, or before a
178 return insn. */
180 /* Likewise for a simple_return. */
183 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
184 not always monotonically increase. */
187 /* Highest valid index in `uid_to_ruid'. */
215 rtx *);
237 \f
238 /* A wrapper around next_active_insn which takes care to return ret_rtx
239 unchanged. */
241 static rtx
243 {
247 }
248 \f
249 /* Return true iff INSN is a simplejump, or any kind of return insn. */
251 static bool
253 {
257 }
258 \f
259 /* Return TRUE if this insn should stop the search for insn to fill delay
260 slots. LABELS_P indicates that labels should terminate the search.
261 In all cases, jumps terminate the search. */
263 static int
265 {
269 /* If the insn can throw an exception that is caught within the function,
270 it may effectively perform a jump from the viewpoint of the function.
271 Therefore act like for a jump. */
276 {
290 /* OK unless it contains a delay slot or is an `asm' insn of some type.
291 We don't know anything about these. */
298 }
299 }
300 \f
301 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
302 resource set contains a volatile memory reference. Otherwise, return FALSE. */
304 static int
306 {
312 }
314 /* Return TRUE if any resource marked in RES, a `struct resources', is
315 referenced by INSN. If INCLUDE_DELAYED_EFFECTS is set, return if the called
316 routine is using those resources.
318 We compute this by computing all the resources referenced by INSN and
319 seeing if this conflicts with RES. It might be faster to directly check
320 ourselves, and this is the way it used to work, but it means duplicating
321 a large block of complex code. */
323 static int
326 {
332 }
334 /* Return TRUE if INSN modifies resources that are marked in RES.
335 INCLUDE_DELAYED_EFFECTS is set if the actions of that routine should be
336 included. CC0 is only modified if it is explicitly set; see comments
337 in front of mark_set_resources for details. */
339 static int
342 {
347 (include_delayed_effects
348 ? MARK_SRC_DEST_CALL
351 }
352 \f
353 /* Find a label at the end of the function or before a RETURN. If there
354 is none, try to make one. If that fails, returns 0.
356 The property of such a label is that it is placed just before the
357 epilogue or a bare RETURN insn, so that another bare RETURN can be
358 turned into a jump to the label unconditionally. In particular, the
359 label cannot be placed before a RETURN insn with a filled delay slot.
361 ??? There may be a problem with the current implementation. Suppose
362 we start with a bare RETURN insn and call find_end_label. It may set
363 function_return_label just before the RETURN. Suppose the machinery
364 is able to fill the delay slot of the RETURN insn afterwards. Then
365 function_return_label is no longer valid according to the property
366 described above and find_end_label will still return it unmodified.
367 Note that this is probably mitigated by the following observation:
368 once function_return_label is made, it is very likely the target of
369 a jump, so filling the delay slot of the RETURN will be much more
370 difficult.
371 KIND is either simple_return_rtx or ret_rtx, indicating which type of
372 return we're looking for. */
376 {
382 else
383 {
386 }
388 /* If we found one previously, return it. */
392 /* Otherwise, see if there is a label at the end of the function. If there
393 is, it must be that RETURN insns aren't needed, so that is our return
394 label and we don't have to do anything else. */
403 /* When a target threads its epilogue we might already have a
404 suitable return insn. If so put a label before it for the
405 function_return_label. */
409 {
414 /* Put the label before any USE insns that may precede the RETURN
415 insn. */
421 }
425 else
426 {
429 /* If the basic block reorder pass moves the return insn to
430 some other place try to locate it again and put our
431 function_return_label there. */
435 {
438 /* Put the label before any USE insns that may precede the
439 RETURN insn. */
444 }
445 else
446 {
448 /* The RETURN insn has its delay slot filled so we cannot
449 emit the label just before it. Since we already have
450 an epilogue and cannot emit a new RETURN, we cannot
451 emit the label at all. */
454 /* Otherwise, make a new label and emit a RETURN and BARRIER,
455 if needed. */
458 {
459 /* The return we make may have delay slots too. */
466 }
467 }
469 }
471 /* Show one additional use for this label so it won't go away until
472 we are done. */
476 }
477 \f
478 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
479 the pattern of INSN with the SEQUENCE.
481 Returns the insn containing the SEQUENCE that replaces INSN. */
485 {
486 /* Allocate the rtvec to hold the insns and the SEQUENCE. */
491 /* If DELAY_INSN has a location, use it for SEQ_INSN. If DELAY_INSN does
492 not have a location, but one of the delayed insns does, we pick up a
493 location from there later. */
496 /* Unlink INSN from the insn chain, so that we can put it into
497 the SEQUENCE. Remember where we want to emit SEQUENCE in AFTER. */
502 /* Build our SEQUENCE and rebuild the insn chain. */
509 {
513 /* Show that this copy of the insn isn't deleted. */
516 /* Unlink insn from its original place, and re-emit it into
517 the sequence. */
521 /* SPARC assembler, for instance, emit warning when debug info is output
522 into the delay slot. */
528 {
531 {
533 /* Remove any REG_DEAD notes because we can't rely on them now
534 that the insn has been moved. */
540 /* Keep the label reference count up to date. */
547 }
548 }
549 }
552 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
556 }
558 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
559 be in the order in which the insns are to be executed. */
561 static void
563 {
564 /* If INSN has its block number recorded, clear it since we may
565 be moving the insn to a new block. */
568 }
569 \f
570 /* Delete INSN from the delay slot of the insn that it is in, which may
571 produce an insn with no delay slots. Return the new insn. */
575 {
581 /* We first must find the insn containing the SEQUENCE with INSN in its
582 delay slot. Do this by finding an insn, TRIAL, where
583 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
588 ;
596 /* Create a delay list consisting of all the insns other than the one
597 we are deleting (unless we were the only one). */
604 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
605 list, and rebuild the delay list if non-empty. */
611 /* If there was a barrier after the old SEQUENCE, remit it. */
615 /* If there are any delay insns, remit them. Otherwise clear the
616 annul flag. */
624 /* Show we need to fill this insn again. */
628 }
629 \f
630 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
631 the insn that sets CC0 for it and delete it too. */
633 static void
635 {
636 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
637 delete the insn that sets the condition code, but it is hard to find it.
638 Since this case is rare anyway, don't bother trying; there would likely
639 be other insns that became dead anyway, which we wouldn't know to
640 delete. */
643 {
646 /* If a reg-note was found, it points to an insn to set CC0. This
647 insn is in the delay list of some other insn. So delete it from
648 the delay list it was in. */
650 {
654 }
655 else
656 {
657 /* The insn setting CC0 is our previous insn, but it may be in
658 a delay slot. It will be the last insn in the delay slot, if
659 it is. */
668 else
670 }
671 }
674 }
675 \f
676 /* Counters for delay-slot filling. */
678 #define NUM_REORG_FUNCTIONS 2
679 #define MAX_DELAY_HISTOGRAM 3
680 #define MAX_REORG_PASSES 2
688 static void
690 {
695 }
696 \f
697 /* Optimize the following cases:
699 1. When a conditional branch skips over only one instruction,
700 use an annulling branch and put that insn in the delay slot.
701 Use either a branch that annuls when the condition if true or
702 invert the test with a branch that annuls when the condition is
703 false. This saves insns, since otherwise we must copy an insn
704 from the L1 target.
706 (orig) (skip) (otherwise)
707 Bcc.n L1 Bcc',a L1 Bcc,a L1'
708 insn insn insn2
709 L1: L1: L1:
710 insn2 insn2 insn2
711 insn3 insn3 L1':
712 insn3
714 2. When a conditional branch skips over only one instruction,
715 and after that, it unconditionally branches somewhere else,
716 perform the similar optimization. This saves executing the
717 second branch in the case where the inverted condition is true.
719 Bcc.n L1 Bcc',a L2
720 insn insn
721 L1: L1:
722 Bra L2 Bra L2
724 INSN is a JUMP_INSN.
726 This should be expanded to skip over N insns, where N is the number
727 of delay slots required. */
729 static void
731 {
748 /* There are two cases where we are just executing one insn (we assume
749 here that a branch requires only one insn; this should be generalized
750 at some point): Where the branch goes around a single insn or where
751 we have one insn followed by a branch to the same label we branch to.
752 In both of these cases, inverting the jump and annulling the delay
753 slot give the same effect in fewer insns. */
758 {
760 {
765 }
772 /* Also, if we are targeting an unconditional
773 branch, thread our jump to the target of that branch. Don't
774 change this into a RETURN here, because it may not accept what
775 we have in the delay slot. We'll fix this up later. */
777 {
783 {
784 /* Recompute the flags based on TARGET_LABEL since threading
785 the jump to TARGET_LABEL may change the direction of the
786 jump (which may change the circumstances in which the
787 delay slot is nullified). */
791 }
792 }
795 }
796 }
797 \f
798 /* Encode and return branch direction and prediction information for
799 INSN assuming it will jump to LABEL.
801 Non conditional branches return no direction information and
802 are predicted as very likely taken. */
804 static int
806 {
809 /* get_jump_flags can be passed any insn with delay slots, these may
810 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
811 direction information, and only if they are conditional jumps.
813 If LABEL is a return, then there is no way to determine the branch
814 direction. */
820 flags
823 /* No valid direction information. */
824 else
828 }
830 /* Return truth value of the statement that this branch
831 is mostly taken. If we think that the branch is extremely likely
832 to be taken, we return 2. If the branch is slightly more likely to be
833 taken, return 1. If the branch is slightly less likely to be taken,
834 return 0 and if the branch is highly unlikely to be taken, return -1. */
836 static int
838 {
839 /* If branch probabilities are available, then use that number since it
840 always gives a correct answer. */
843 {
853 else
855 }
857 /* If there is no note, assume branches are not taken.
858 This should be rare. */
860 }
862 /* Return the condition under which INSN will branch to TARGET. If TARGET
863 is zero, return the condition under which INSN will return. If INSN is
864 an unconditional branch, return const_true_rtx. If INSN isn't a simple
865 type of jump, or it doesn't go to TARGET, return 0. */
867 static rtx
869 {
871 rtx src;
898 {
905 }
908 }
910 /* Return nonzero if CONDITION is more strict than the condition of
911 INSN, i.e., if INSN will always branch if CONDITION is true. */
913 static int
915 {
934 }
936 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
937 any insns already in the delay slot of JUMP. */
939 static int
941 {
945 /* Make sure all the delay slots of this jump would still
946 be valid after threading the jump. If they are still
947 valid, then return nonzero. */
952 #if ANNUL_IFFALSE_SLOTS
956 #endif
957 #if ANNUL_IFTRUE_SLOTS
961 #endif
966 }
968 /* Return nonzero if redirecting JUMP to NEWLABEL does not invalidate
969 any insns we wish to place in the delay slot of JUMP. */
971 static int
974 {
975 /* Make sure all the insns in DELAY_LIST would still be
976 valid after threading the jump. If they are still
977 valid, then return nonzero. */
984 #if ANNUL_IFFALSE_SLOTS
988 #endif
989 #if ANNUL_IFTRUE_SLOTS
993 #endif
998 }
1000 /* DELAY_LIST is a list of insns that have already been placed into delay
1001 slots. See if all of them have the same annulling status as ANNUL_TRUE_P.
1002 If not, return 0; otherwise return 1. */
1004 static int
1007 {
1016 }
1017 \f
1018 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1019 the condition tested by INSN is CONDITION and the resources shown in
1020 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1021 from SEQ's delay list, in addition to whatever insns it may execute
1022 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1023 needed while searching for delay slot insns. Return the concatenated
1024 delay list if possible, otherwise, return 0.
1026 SLOTS_TO_FILL is the total number of slots required by INSN, and
1027 PSLOTS_FILLED points to the number filled so far (also the number of
1028 insns in DELAY_LIST). It is updated with the number that have been
1029 filled from the SEQUENCE, if any.
1031 PANNUL_P points to a nonzero value if we already know that we need
1032 to annul INSN. If this routine determines that annulling is needed,
1033 it may set that value nonzero.
1035 PNEW_THREAD points to a location that is to receive the place at which
1036 execution should continue. */
1038 static void
1046 {
1056 /* We can't do anything if there are more delay slots in SEQ than we
1057 can handle, or if we don't know that it will be a taken branch.
1058 We know that it will be a taken branch if it is either an unconditional
1059 branch or a conditional branch with a stricter branch condition.
1061 Also, exit if the branch has more than one set, since then it is computing
1062 other results that can't be ignored, e.g. the HPPA mov&branch instruction.
1063 ??? It may be possible to move other sets into INSN in addition to
1064 moving the instructions in the delay slots.
1066 We can not steal the delay list if one of the instructions in the
1067 current delay_list modifies the condition codes and the jump in the
1068 sequence is a conditional jump. We can not do this because we can
1069 not change the direction of the jump because the condition codes
1070 will effect the direction of the jump in the sequence. */
1076 {
1080 }
1087 /* On some targets, branches with delay slots can have a limited
1088 displacement. Give the back end a chance to tell us we can't do
1089 this. */
1095 {
1102 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1103 delay list. */
1105 /* If TRIAL is from the fallthrough code of an annulled branch insn
1106 in SEQ, we cannot use it. */
1111 /* If this insn was already done (usually in a previous delay slot),
1112 pretend we put it in our delay slot. */
1117 /* We will end up re-vectoring this branch, so compute flags
1118 based on jumping to the new label. */
1132 {
1134 {
1135 /* Frame related instructions cannot go into annulled delay
1136 slots, it messes up the dwarf info. */
1140 }
1144 total_slots_filled++;
1148 }
1149 else
1151 }
1153 /* Record the effect of the instructions that were redundant and which
1154 we therefore decided not to copy. */
1157 {
1160 }
1162 /* Show the place to which we will be branching. */
1165 /* Add any new insns to the delay list and update the count of the
1166 number of slots filled. */
1174 }
1175 \f
1176 /* Similar to steal_delay_list_from_target except that SEQ is on the
1177 fallthrough path of INSN. Here we only do something if the delay insn
1178 of SEQ is an unconditional branch. In that case we steal its delay slot
1179 for INSN since unconditional branches are much easier to fill. */
1181 static void
1190 {
1198 /* We can't do anything if SEQ's delay insn isn't an
1199 unconditional branch. */
1205 {
1209 /* If TRIAL sets CC0, stealing it will move it too far from the use
1210 of CC0. */
1218 /* If this insn was already done, we don't need it. */
1220 {
1225 }
1235 {
1243 }
1244 else
1246 }
1250 }
1251 \f
1252 /* Try merging insns starting at THREAD which match exactly the insns in
1253 INSN's delay list.
1255 If all insns were matched and the insn was previously annulling, the
1256 annul bit will be cleared.
1258 For each insn that is merged, if the branch is or will be non-annulling,
1259 we delete the merged insn. */
1261 static void
1263 {
1279 /* If this is not an annulling branch, take into account anything needed in
1280 INSN's delay slot. This prevents two increments from being incorrectly
1281 folded into one. If we are annulling, this would be the correct
1282 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1283 will essentially disable this optimization. This method is somewhat of
1284 a kludge, but I don't see a better way.) */
1292 {
1298 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1304 /* We can't share an insn that sets cc0. */
1310 /* Update next_trial, in case try_split succeeded. */
1312 /* Likewise THREAD. */
1315 /* Have to test this condition if annul condition is different
1316 from (and less restrictive than) non-annulling one. */
1318 {
1321 {
1328 }
1329 else
1336 }
1340 }
1342 /* See if we stopped on a filled insn. If we did, try to see if its
1343 delay slots match. */
1349 {
1353 /* Account for resources set/needed by the filled insn. */
1358 {
1362 /* Account for resources set by the insn following NEXT_TO_MATCH
1363 inside INSN's delay list. */
1367 /* Account for resources set by the insn before DTRIAL and inside
1368 TRIAL's delay list. */
1377 /* Check that DTRIAL and NEXT_TO_MATCH does not reference a
1378 resource modified between them (only dtrial is checked because
1379 next_to_match and dtrial shall to be equal in order to hit
1380 this line) */
1383 {
1385 {
1393 }
1394 else
1402 }
1403 else
1404 {
1405 /* Keep track of the set/referenced resources for the delay
1406 slots of any trial insns we encounter. */
1409 }
1410 }
1411 }
1413 /* If all insns in the delay slot have been matched and we were previously
1414 annulling the branch, we need not any more. In that case delete all the
1415 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn in
1416 the delay list so that we know that it isn't only being used at the
1417 target. */
1419 {
1423 {
1428 }
1429 else
1430 {
1433 }
1439 }
1440 }
1441 \f
1442 /* See if INSN is redundant with an insn in front of TARGET. Often this
1443 is called when INSN is a candidate for a delay slot of TARGET.
1444 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1445 of INSN. Often INSN will be redundant with an insn in a delay slot of
1446 some previous insn. This happens when we have a series of branches to the
1447 same label; in that case the first insn at the target might want to go
1448 into each of the delay slots.
1450 If we are not careful, this routine can take up a significant fraction
1451 of the total compilation time (4%), but only wins rarely. Hence we
1452 speed this routine up by making two passes. The first pass goes back
1453 until it hits a label and sees if it finds an insn with an identical
1454 pattern. Only in this (relatively rare) event does it check for
1455 data conflicts.
1457 We do not split insns we encounter. This could cause us not to find a
1458 redundant insn, but the cost of splitting seems greater than the possible
1459 gain in rare cases. */
1463 {
1467 rtx pat;
1472 /* If INSN has any REG_UNUSED notes, it can't match anything since we
1473 are allowed to not actually assign to such a register. */
1477 /* Scan backwards looking for a match. */
1482 {
1483 /* (use (insn))s can come immediately after a barrier if the
1484 label that used to precede them has been deleted as dead.
1485 See delete_related_insns. */
1501 {
1502 /* Stop for a CALL and its delay slots because it is difficult to
1503 track its resource needs correctly. */
1507 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1508 slots because it is difficult to track its resource needs
1509 correctly. */
1517 /* See if any of the insns in the delay slot match, updating
1518 resource requirements as we go. */
1525 /* If found a match, exit this loop early. */
1528 }
1533 }
1535 /* If we didn't find an insn that matches, return 0. */
1539 /* See what resources this insn sets and needs. If they overlap, or
1540 if this insn references CC0, it can't be redundant. */
1547 /* If TARGET is a SEQUENCE, get the main insn. */
1553 /* The insn requiring the delay may not set anything needed or set by
1554 INSN. */
1559 /* Insns we pass may not set either NEEDED or SET, so merge them for
1560 simpler tests. */
1564 /* This insn isn't redundant if it conflicts with an insn that either is
1565 or will be in a delay slot of TARGET. */
1579 /* Scan backwards until we reach a label or an insn that uses something
1580 INSN sets or sets something insn uses or sets. */
1586 {
1599 {
1603 /* If this is a CALL_INSN and its delay slots, it is hard to track
1604 the resource needs properly, so give up. */
1608 /* If this is an INSN or JUMP_INSN with delayed effects, it
1609 is hard to track the resource needs properly, so give up. */
1620 /* See if any of the insns in the delay slot match, updating
1621 resource requirements as we go. */
1623 {
1626 /* If an insn will be annulled if the branch is false, it isn't
1627 considered as a possible duplicate insn. */
1630 {
1631 /* Show that this insn will be used in the sequel. */
1634 }
1636 /* Unless this is an annulled insn from the target of a branch,
1637 we must stop if it sets anything needed or set by INSN. */
1641 }
1643 /* If the insn requiring the delay slot conflicts with INSN, we
1644 must stop. */
1647 }
1648 else
1649 {
1650 /* See if TRIAL is the same as INSN. */
1655 /* Can't go any further if TRIAL conflicts with INSN. */
1658 }
1659 }
1662 }
1663 \f
1664 /* Return 1 if THREAD can only be executed in one way. If LABEL is nonzero,
1665 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
1666 is nonzero, we are allowed to fall into this thread; otherwise, we are
1667 not.
1669 If LABEL is used more than one or we pass a label other than LABEL before
1670 finding an active insn, we do not own this thread. */
1672 static int
1674 {
1678 /* We don't own the function end. */
1682 /* We have a non-NULL insn. */
1685 /* Get the first active insn, or THREAD_INSN, if it is an active insn. */
1696 /* Ensure that we reach a BARRIER before any insn or label. */
1708 }
1709 \f
1710 /* Called when INSN is being moved from a location near the target of a jump.
1711 We leave a marker of the form (use (INSN)) immediately in front of WHERE
1712 for mark_target_live_regs. These markers will be deleted at the end.
1714 We used to try to update the live status of registers if WHERE is at
1715 the start of a basic block, but that can't work since we may remove a
1716 BARRIER in relax_delay_slots. */
1718 static void
1720 {
1723 /* INSN might be making a value live in a block where it didn't use to
1724 be. So recompute liveness information for this block. */
1726 }
1728 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
1729 the basic block containing the jump. */
1731 static int
1733 {
1736 }
1738 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
1739 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
1740 that reference values used in INSN. If we find one, then we move the
1741 REG_DEAD note to INSN.
1743 This is needed to handle the case where a later insn (after INSN) has a
1744 REG_DEAD note for a register used by INSN, and this later insn subsequently
1745 gets moved before a CODE_LABEL because it is a redundant insn. In this
1746 case, mark_target_live_regs may be confused into thinking the register
1747 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
1749 static void
1751 {
1758 {
1766 {
1767 /* Move the REG_DEAD note from P to INSN. */
1771 }
1772 }
1773 }
1775 /* Called when an insn redundant with start_insn is deleted. If there
1776 is a REG_DEAD note for the target of start_insn between start_insn
1777 and stop_insn, then the REG_DEAD note needs to be deleted since the
1778 value no longer dies there.
1780 If the REG_DEAD note isn't deleted, then mark_target_live_regs may be
1781 confused into thinking the register is dead. */
1783 static void
1785 {
1792 {
1800 {
1803 }
1804 }
1805 }
1807 /* Delete any REG_UNUSED notes that exist on INSN but not on OTHER_INSN.
1809 This handles the case of udivmodXi4 instructions which optimize their
1810 output depending on whether any REG_UNUSED notes are present. We must
1811 make sure that INSN calculates as many results as OTHER_INSN does. */
1813 static void
1815 {
1819 {
1828 }
1829 }
1830 \f
1833 /* Return the label before INSN, or put a new label there. If SIBLING is
1834 non-zero, it is another label associated with the new label (if any),
1835 typically the former target of the jump that will be redirected to
1836 the new label. */
1840 {
1843 /* Find an existing label at this point
1844 or make a new one if there is none. */
1848 {
1855 {
1858 }
1859 }
1861 }
1863 /* Scan a function looking for insns that need a delay slot and find insns to
1864 put into the delay slot.
1866 NON_JUMPS_P is nonzero if we are to only try to fill non-jump insns (such
1867 as calls). We do these first since we don't want jump insns (that are
1868 easier to fill) to get the only insns that could be used for non-jump insns.
1869 When it is zero, only try to fill JUMP_INSNs.
1871 When slots are filled in this manner, the insns (including the
1872 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
1873 it is possible to tell whether a delay slot has really been filled
1874 or not. `final' knows how to deal with this, by communicating
1875 through FINAL_SEQUENCE. */
1877 static void
1879 {
1881 rtx pat;
1889 {
1891 /* Get the next insn to fill. If it has already had any slots assigned,
1892 we can't do anything with it. Maybe we'll improve this later. */
1903 /* It may have been that this insn used to need delay slots, but
1904 now doesn't; ignore in that case. This can happen, for example,
1905 on the HP PA RISC, where the number of delay slots depends on
1906 what insns are nearby. */
1909 /* Some machine description have defined instructions to have
1910 delay slots only in certain circumstances which may depend on
1911 nearby insns (which change due to reorg's actions).
1913 For example, the PA port normally has delay slots for unconditional
1914 jumps.
1916 However, the PA port claims such jumps do not have a delay slot
1917 if they are immediate successors of certain CALL_INSNs. This
1918 allows the port to favor filling the delay slot of the call with
1919 the unconditional jump. */
1923 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
1924 says how many. After initialization, first try optimizing
1926 call _foo call _foo
1927 nop add %o7,.-L1,%o7
1928 b,a L1
1929 nop
1931 If this case applies, the delay slot of the call is filled with
1932 the unconditional jump. This is done first to avoid having the
1933 delay slot of the call filled in the backward scan. Also, since
1934 the unconditional jump is likely to also have a delay slot, that
1935 insn must exist when it is subsequently scanned.
1937 This is tried on each insn with delay slots as some machines
1938 have insns which perform calls, but are not represented as
1939 CALL_INSNs. */
1946 else
1955 {
1957 slots_filled++;
1960 /* TRIAL may have had its delay slot filled, then unfilled. When
1961 the delay slot is unfilled, TRIAL is placed back on the unfilled
1962 slots obstack. Unfortunately, it is placed on the end of the
1963 obstack, not in its original location. Therefore, we must search
1964 from entry i + 1 to the end of the unfilled slots obstack to
1965 try and find TRIAL. */
1968 tmp++;
1970 /* Remove the unconditional jump from consideration for delay slot
1971 filling and unthread it. */
1974 {
1981 }
1982 }
1984 /* Now, scan backwards from the insn to search for a potential
1985 delay-slot candidate. Stop searching when a label or jump is hit.
1987 For each candidate, if it is to go into the delay slot (moved
1988 forward in execution sequence), it must not need or set any resources
1989 that were set by later insns and must not set any resources that
1990 are needed for those insns.
1992 The delay slot insn itself sets resources unless it is a call
1993 (in which case the called routine, not the insn itself, is doing
1994 the setting). */
1997 {
1998 /* If the flags register is dead after the insn, then we want to be
1999 able to accept a candidate that clobbers it. For this purpose,
2000 we need to filter the flags register during life analysis, so
2001 that it doesn't create RAW and WAW dependencies, while still
2002 creating the necessary WAR dependencies. */
2003 bool filter_flags
2012 {
2015 }
2020 {
2023 /* This must be an INSN or CALL_INSN. */
2026 /* Stand-alone USE and CLOBBER are just for flow. */
2030 /* And DEBUG_INSNs never go into delay slots. */
2034 /* Check for resource conflict first, to avoid unnecessary
2035 splitting. */
2041 /* Can't separate set of cc0 from its use. */
2044 {
2048 {
2049 /* In this case, we are searching backward, so if we
2050 find insns to put on the delay list, we want
2051 to put them at the head, rather than the
2052 tail, of the list. */
2061 }
2062 }
2066 {
2068 /* If the flags register is set, then it doesn't create RAW
2069 dependencies any longer and it also doesn't create WAW
2070 dependencies since it's dead after the original insn. */
2072 {
2075 }
2076 }
2078 }
2079 }
2081 /* If all needed slots haven't been filled, we come here. */
2083 /* Try to optimize case of jumping around a single insn. */
2090 {
2094 }
2096 /* Try to get insns from beyond the insn needing the delay slot.
2097 These insns can neither set or reference resources set in insns being
2098 skipped, cannot set resources in the insn being skipped, and, if this
2099 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2100 call might not return).
2102 There used to be code which continued past the target label if
2103 we saw all uses of the target label. This code did not work,
2104 because it failed to account for some instructions which were
2105 both annulled and marked as from the target. This can happen as a
2106 result of optimize_skip. Since this code was redundant with
2107 fill_eager_delay_slots anyways, it was just deleted. */
2110 /* If this instruction could throw an exception which is
2111 caught in the same function, then it's not safe to fill
2112 the delay slot with an instruction from beyond this
2113 point. For example, consider:
2115 int i = 2;
2117 try {
2118 f();
2119 i = 3;
2120 } catch (...) {}
2122 return i;
2124 Even though `i' is a local variable, we must be sure not
2125 to put `i = 3' in the delay slot if `f' might throw an
2126 exception.
2128 Presumably, we should also check to see if we could get
2129 back to this function via `setjmp'. */
2132 {
2146 {
2149 /* This must be an INSN or CALL_INSN. */
2152 /* Stand-alone USE and CLOBBER are just for flow. */
2156 /* And DEBUG_INSNs do not go in delay slots. */
2160 /* If this already has filled delay slots, get the insn needing
2161 the delay slots. */
2164 else
2167 /* Stop our search when seeing a jump. */
2171 /* See if we have a resource problem before we try to split. */
2181 {
2191 }
2196 /* Ensure we don't put insns between the setting of cc and the
2197 comparison by moving a setting of cc into an earlier delay
2198 slot since these insns could clobber the condition code. */
2201 /* If this is a call, we might not get here. */
2204 }
2206 /* If there are slots left to fill and our search was stopped by an
2207 unconditional branch, try the insn at the branch target. We can
2208 redirect the branch if it works.
2210 Don't do this if the insn at the branch target is a branch. */
2212 && trial
2227 {
2228 /* See comment in relax_delay_slots about necessity of using
2229 next_real_nondebug_insn here. */
2234 else
2238 {
2241 slots_filled++;
2243 new_label);
2244 }
2245 }
2246 }
2248 /* If this is an unconditional jump, then try to get insns from the
2249 target of the jump. */
2268 }
2269 }
2270 \f
2271 /* Follow any unconditional jump at LABEL, for the purpose of redirecting JUMP;
2272 return the ultimate label reached by any such chain of jumps.
2273 Return a suitable return rtx if the chain ultimately leads to a
2274 return instruction.
2275 If LABEL is not followed by a jump, return LABEL.
2276 If the chain loops or we can't find end, return LABEL,
2277 since that tells caller to avoid changing the insn.
2278 If the returned label is obtained by following a crossing jump,
2279 set *CROSSING to true, otherwise set it to false. */
2281 static rtx
2283 {
2303 depth++)
2304 {
2307 /* If we have found a cycle, make the insn jump to itself. */
2311 /* Cannot follow returns and cannot look through tablejumps. */
2325 }
2329 }
2331 /* Try to find insns to place in delay slots.
2333 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
2334 or is an unconditional branch if CONDITION is const_true_rtx.
2335 *PSLOTS_FILLED is updated with the number of slots that we have filled.
2337 THREAD is a flow-of-control, either the insns to be executed if the
2338 branch is true or if the branch is false, THREAD_IF_TRUE says which.
2340 OPPOSITE_THREAD is the thread in the opposite direction. It is used
2341 to see if any potential delay slot insns set things needed there.
2343 LIKELY is nonzero if it is extremely likely that the branch will be
2344 taken and THREAD_IF_TRUE is set. This is used for the branch at the
2345 end of a loop back up to the top.
2347 OWN_THREAD is true if we are the only user of the thread, i.e. it is
2348 the target of the jump when we are the only jump going there.
2350 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
2351 case, we can only take insns from the head of the thread for our delay
2352 slot. We then adjust the jump to point after the insns we have taken. */
2354 static void
2359 {
2360 rtx new_thread;
2367 /* Validate our arguments. */
2373 /* If our thread is the end of subroutine, we can't get any delay
2374 insns from that. */
2380 /* If this is an unconditional branch, nothing is needed at the
2381 opposite thread. Otherwise, compute what is needed there. */
2384 else
2387 /* If the insn at THREAD can be split, do it here to avoid having to
2388 update THREAD and NEW_THREAD if it is done in the loop below. Also
2389 initialize NEW_THREAD. */
2393 /* Scan insns at THREAD. We are looking for an insn that can be removed
2394 from THREAD (it neither sets nor references resources that were set
2395 ahead of it and it doesn't set anything needs by the insns ahead of
2396 it) and that either can be placed in an annulling insn or aren't
2397 needed at OPPOSITE_THREAD. */
2402 /* If we do not own this thread, we must stop as soon as we find
2403 something that we can't put in a delay slot, since all we can do
2404 is branch into THREAD at a later point. Therefore, labels stop
2405 the search if this is not the `true' thread. */
2410 {
2413 /* If we have passed a label, we no longer own this thread. */
2415 {
2418 }
2427 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
2428 don't separate or copy insns that set and use CC0. */
2435 {
2438 /* If TRIAL is redundant with some insn before INSN, we don't
2439 actually need to add it to the delay list; we can merely pretend
2440 we did. */
2442 {
2445 {
2448 {
2452 }
2455 }
2456 else
2457 {
2460 }
2463 }
2465 /* There are two ways we can win: If TRIAL doesn't set anything
2466 needed at the opposite thread and can't trap, or if it can
2467 go into an annulled delay slot. But we want neither to copy
2468 nor to speculate frame-related insns. */
2475 {
2485 }
2489 {
2502 {
2506 winner:
2511 /* If we own this thread, delete the insn. If this is the
2512 destination of a branch, show that a basic block status
2513 may have been updated. In any case, mark the new
2514 starting point of this thread. */
2516 {
2517 rtx note;
2521 {
2525 }
2527 /* We are moving this insn, not deleting it. We must
2528 temporarily increment the use count on any referenced
2529 label lest it be deleted by delete_related_insns. */
2535 {
2536 /* REG_LABEL_OPERAND could be
2537 NOTE_INSN_DELETED_LABEL too. */
2540 else
2543 }
2554 {
2555 /* REG_LABEL_OPERAND could be
2556 NOTE_INSN_DELETED_LABEL too. */
2559 else
2562 }
2565 }
2566 else
2576 {
2577 /* Even though we have filled all the slots, we
2578 may be branching to a location that has a
2579 redundant insn. Skip any if so. */
2586 && (prior_insn
2589 {
2590 /* We know we do not own the thread, so no need
2591 to call update_block and delete_insn. */
2594 new_thread
2596 }
2598 }
2601 }
2602 }
2603 }
2605 /* This insn can't go into a delay slot. */
2610 /* Ensure we don't put insns between the setting of cc and the comparison
2611 by moving a setting of cc into an earlier delay slot since these insns
2612 could clobber the condition code. */
2615 /* If this insn is a register-register copy and the next insn has
2616 a use of our destination, change it to use our source. That way,
2617 it will become a candidate for our delay slot the next time
2618 through this loop. This case occurs commonly in loops that
2619 scan a list.
2621 We could check for more complex cases than those tested below,
2622 but it doesn't seem worth it. It might also be a good idea to try
2623 to swap the two insns. That might do better.
2625 We can't do this if the next insn modifies our destination, because
2626 that would make the replacement into the insn invalid. We also can't
2627 do this if it modifies our source, because it might be an earlyclobber
2628 operand. This latter test also prevents updating the contents of
2629 a PRE_INC. We also can't do this if there's overlap of source and
2630 destination. Overlap may happen for larger-than-register-size modes. */
2636 {
2646 }
2647 }
2649 /* If we stopped on a branch insn that has delay slots, see if we can
2650 steal some of the insns in those slots. */
2654 {
2656 /* If this is the `true' thread, we will want to follow the jump,
2657 so we can only do this if we have taken everything up to here. */
2659 {
2665 /* If we owned the thread and are told that it branched
2666 elsewhere, make sure we own the thread at the new location. */
2669 }
2675 }
2677 /* If we haven't found anything for this delay slot and it is very
2678 likely that the branch will be taken, see if the insn at our target
2679 increments or decrements a register with an increment that does not
2680 depend on the destination register. If so, try to place the opposite
2681 arithmetic insn after the jump insn and put the arithmetic insn in the
2682 delay slot. If we can't do this, return. */
2689 {
2691 rtx dest;
2692 rtx src;
2694 /* We know "new_thread" is an insn due to NONJUMP_INSN_P (new_thread)
2695 above. */
2712 {
2714 rtx new_arith;
2717 /* If this is a constant adjustment, use the same code with
2718 the negated constant. Otherwise, reverse the sense of the
2719 arithmetic. */
2723 else
2732 {
2735 }
2738 {
2741 {
2745 }
2747 }
2748 else
2757 }
2758 }
2763 /* If we are to branch into the middle of this thread, find an appropriate
2764 label or make a new one if none, and redirect INSN to it. If we hit the
2765 end of the function, use the end-of-function label. */
2767 {
2768 rtx label;
2784 else
2789 {
2793 }
2794 }
2795 }
2796 \f
2797 /* Make another attempt to find insns to place in delay slots.
2799 We previously looked for insns located in front of the delay insn
2800 and, for non-jump delay insns, located behind the delay insn.
2802 Here only try to schedule jump insns and try to move insns from either
2803 the target or the following insns into the delay slot. If annulling is
2804 supported, we will be likely to do this. Otherwise, we can do this only
2805 if safe. */
2807 static void
2809 {
2815 {
2816 rtx condition;
2833 /* Some machine description have defined instructions to have
2834 delay slots only in certain circumstances which may depend on
2835 nearby insns (which change due to reorg's actions).
2837 For example, the PA port normally has delay slots for unconditional
2838 jumps.
2840 However, the PA port claims such jumps do not have a delay slot
2841 if they are immediate successors of certain CALL_INSNs. This
2842 allows the port to favor filling the delay slot of the call with
2843 the unconditional jump. */
2854 /* Get the next active fallthrough and target insns and see if we own
2855 them. Then see whether the branch is likely true. We don't need
2856 to do a lot of this for unconditional branches. */
2862 {
2866 }
2867 else
2868 {
2872 }
2874 /* If this insn is expected to branch, first try to get insns from our
2875 target, then our fallthrough insns. If it is not expected to branch,
2876 try the other order. */
2879 {
2882 own_target,
2886 {
2887 /* Even though we didn't find anything for delay slots,
2888 we might have found a redundant insn which we deleted
2889 from the thread that was filled. So we have to recompute
2890 the next insn at the target. */
2898 }
2899 }
2900 else
2901 {
2911 }
2921 }
2922 }
2923 \f
2926 /* Recursively delete prior insns that compute the value (used only by INSN
2927 which the caller is deleting) stored in the register mentioned by NOTE
2928 which is a REG_DEAD note associated with INSN. */
2930 static void
2932 {
2940 {
2943 /* If we reach a CALL which is not calling a const function
2944 or the callee pops the arguments, then give up. */
2950 /* If we reach a SEQUENCE, it is too complex to try to
2951 do anything with it, so give up. We can be run during
2952 and after reorg, so SEQUENCE rtl can legitimately show
2953 up here. */
2959 /* reorg creates USEs that look like this. We leave them
2960 alone because reorg needs them for its own purposes. */
2964 {
2969 {
2970 /* If we find a SET of something else, we can't
2971 delete the insn. */
2976 {
2982 }
2986 }
2989 {
2999 /* We may have a multi-word hard register and some, but not
3000 all, of the words of the register are needed in subsequent
3001 insns. Write REG_UNUSED notes for those parts that were not
3002 needed. */
3005 {
3016 }
3017 }
3020 }
3022 /* If PAT references the register that dies here, it is an
3023 additional use. Hence any prior SET isn't dead. However, this
3024 insn becomes the new place for the REG_DEAD note. */
3026 {
3030 }
3031 }
3032 }
3034 /* Delete INSN and recursively delete insns that compute values used only
3035 by INSN. This uses the REG_DEAD notes computed during flow analysis.
3037 Look at all our REG_DEAD notes. If a previous insn does nothing other
3038 than set a register that dies in this insn, we can delete that insn
3039 as well.
3041 On machines with CC0, if CC0 is used in this insn, we may be able to
3042 delete the insn that set it. */
3044 static void
3046 {
3050 {
3052 /* We assume that at this stage
3053 CC's are always set explicitly
3054 and always immediately before the jump that
3055 will use them. So if the previous insn
3056 exists to set the CC's, delete it
3057 (unless it performs auto-increments, etc.). */
3060 {
3064 else
3065 /* Otherwise, show that cc0 won't be used. */
3067 }
3068 }
3071 {
3075 /* Verify that the REG_NOTE is legitimate. */
3080 }
3083 }
3085 /* If all INSN does is set the pc, delete it,
3086 and delete the insn that set the condition codes for it
3087 if that's what the previous thing was. */
3089 static void
3091 {
3096 }
3100 {
3103 {
3109 }
3111 }
3113 /* Return TRUE if there is a NOTE_INSN_SWITCH_TEXT_SECTIONS note in between
3114 BEG and END. */
3116 static bool
3118 {
3124 }
3126 \f
3127 /* Once we have tried two ways to fill a delay slot, make a pass over the
3128 code to try to improve the results and to do such things as more jump
3129 threading. */
3131 static void
3133 {
3137 rtx target_label;
3139 /* Look at every JUMP_INSN and see if we can improve it. */
3141 {
3147 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3148 the next insn, or jumps to a label that is not the last of a
3149 group of consecutive labels. */
3153 {
3155 target_label
3165 {
3168 }
3171 {
3175 }
3177 /* See if this jump conditionally branches around an unconditional
3178 jump. If so, invert this jump and point it to the target of the
3179 second jump. Check if it's possible on the target. */
3182 && target_label
3187 {
3190 /* Be careful how we do this to avoid deleting code or
3191 labels that are momentarily dead. See similar optimization
3192 in jump.c.
3194 We also need to ensure we properly handle the case when
3195 invert_jump fails. */
3202 {
3205 }
3214 }
3215 }
3217 /* If this is an unconditional jump and the previous insn is a
3218 conditional jump, try reversing the condition of the previous
3219 insn and swapping our targets. The next pass might be able to
3220 fill the slots.
3222 Don't do this if we expect the conditional branch to be true, because
3223 we would then be making the more common case longer. */
3230 {
3236 }
3238 /* Now look only at cases where we have a filled delay slot. */
3245 /* See if the first insn in the delay slot is redundant with some
3246 previous insn. Remove it from the delay slot if so; then set up
3247 to reprocess this insn. */
3249 {
3255 }
3257 /* See if we have a RETURN insn with a filled delay slot followed
3258 by a RETURN insn with an unfilled a delay slot. If so, we can delete
3259 the first RETURN (but not its delay insn). This gives the same
3260 effect in fewer instructions.
3262 Only do so if optimizing for size since this results in slower, but
3263 smaller code. */
3266 && next
3269 {
3273 /* Delete the RETURN and just execute the delay list insns.
3275 We do this by deleting the INSN containing the SEQUENCE, then
3276 re-emitting the insns separately, and then deleting the RETURN.
3277 This allows the count of the jump target to be properly
3278 decremented.
3280 Note that we need to change the INSN_UID of the re-emitted insns
3281 since it is used to hash the insns for mark_target_live_regs and
3282 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3284 Clear the from target bit, since these insns are no longer
3285 in delay slots. */
3298 }
3300 /* Now look only at the cases where we have a filled JUMP_INSN. */
3311 /* If this jump goes to another unconditional jump, thread it, but
3312 don't convert a jump into a RETURN here. */
3314 delay_jump_insn,
3321 {
3326 }
3328 /* If the first insn at TARGET_LABEL is redundant with a previous
3329 insn, redirect the jump to the following insn and process again.
3330 We use next_real_nondebug_insn instead of next_active_insn so we
3331 don't skip USE-markers, or we'll end up with incorrect
3332 liveness info. */
3337 {
3338 /* Figure out where to emit the special USE insn so we don't
3339 later incorrectly compute register live/death info. */
3345 {
3346 /* Insert the special USE insn and update dataflow info.
3347 We know "trial" is an insn here as it is the output of
3348 next_real_nondebug_insn () above. */
3351 /* Now emit a label before the special USE insn, and
3352 redirect our jump to the new label. */
3357 }
3358 }
3360 /* Similarly, if it is an unconditional jump with one insn in its
3361 delay list and that insn is redundant, thread the jump. */
3369 {
3377 {
3382 }
3383 }
3385 /* See if we have a simple (conditional) jump that is useless. */
3391 /* If the last insn in the delay slot sets CC0 for some insn,
3392 various code assumes that it is in a delay slot. We could
3393 put it back where it belonged and delete the register notes,
3394 but it doesn't seem worthwhile in this uncommon case. */
3395 && (!HAVE_cc0
3398 {
3402 /* All this insn does is execute its delay list and jump to the
3403 following insn. So delete the jump and just execute the delay
3404 list insns.
3406 We do this by deleting the INSN containing the SEQUENCE, then
3407 re-emitting the insns separately, and then deleting the jump.
3408 This allows the count of the jump target to be properly
3409 decremented.
3411 Note that we need to change the INSN_UID of the re-emitted insns
3412 since it is used to hash the insns for mark_target_live_regs and
3413 the re-emitted insns will no longer be wrapped up in a SEQUENCE.
3415 Clear the from target bit, since these insns are no longer
3416 in delay slots. */
3429 }
3431 /* See if this is an unconditional jump around a single insn which is
3432 identical to the one in its delay slot. In this case, we can just
3433 delete the branch and the insn in its delay slot. */
3439 {
3442 }
3444 /* See if this jump (with its delay slots) conditionally branches
3445 around an unconditional jump (without delay slots). If so, invert
3446 this jump and point it to the target of the second jump. We cannot
3447 do this for annulled jumps, though. Again, don't convert a jump to
3448 a RETURN here. */
3455 {
3462 /* find_end_label can generate a new label. Check this first. */
3467 {
3468 /* Be careful how we do this to avoid deleting code or labels
3469 that are momentarily dead. See similar optimization in
3470 jump.c */
3475 {
3478 /* Must update the INSN_FROM_TARGET_P bits now that
3479 the branch is reversed, so that mark_target_live_regs
3480 will handle the delay slot insn correctly. */
3482 {
3485 }
3489 }
3494 }
3495 }
3497 /* If we own the thread opposite the way this insn branches, see if we
3498 can merge its delay slots with following insns. */
3507 /* If we get here, we haven't deleted INSN. But we may have deleted
3508 NEXT, so recompute it. */
3510 }
3511 }
3512 \f
3514 /* Look for filled jumps to the end of function label. We can try to convert
3515 them into RETURN insns if the insns in the delay slot are valid for the
3516 RETURN as well. */
3518 static void
3520 {
3527 /* See if there is a RETURN insn in the function other than the one we
3528 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3529 into a RETURN to jump to it. */
3532 {
3536 else
3539 }
3541 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3542 was equal to END_OF_FUNCTION_LABEL. */
3548 /* Clear the list of insns to fill so we can use it. */
3552 {
3556 /* Only look at filled JUMP_INSNs that go to the end of function
3557 label. */
3570 {
3573 }
3575 {
3578 }
3579 else
3584 /* If we can't make the jump into a RETURN, try to redirect it to the best
3585 RETURN and go on to the next insn. */
3587 {
3588 /* Make sure redirecting the jump will not invalidate the delay
3589 slot insns. */
3593 }
3595 /* See if this RETURN can accept the insns current in its delay slot.
3596 It can if it has more or an equal number of slots and the contents
3597 of each is valid. */
3602 {
3605 #if ANNUL_IFFALSE_SLOTS
3610 #endif
3611 #if ANNUL_IFTRUE_SLOTS
3616 #endif
3620 }
3621 else
3627 /* We have to do something with this insn. If it is an unconditional
3628 RETURN, delete the SEQUENCE and output the individual insns,
3629 followed by the RETURN. Then set things up so we try to find
3630 insns for its delay slots, if it needs some. */
3632 {
3637 {
3641 }
3649 }
3650 else
3651 /* It is probably more efficient to keep this with its current
3652 delay slot as a branch to a RETURN. */
3654 }
3656 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3657 new delay slots we have created. */
3666 }
3667 \f
3668 /* Try to find insns to place in delay slots. */
3670 static void
3672 {
3677 /* If the current function has no insns other than the prologue and
3678 epilogue, then do not try to fill any delay slots. */
3682 /* Find the highest INSN_UID and allocate and initialize our map from
3683 INSN_UID's to position in code. */
3685 {
3691 }
3697 /* Initialize the list of insns that need filling. */
3699 {
3702 }
3705 {
3706 rtx target;
3708 /* Skip vector tables. We can't get attributes for them. */
3719 /* Ensure all jumps go to the last of a set of consecutive labels. */
3726 }
3730 /* Show we haven't computed an end-of-function label yet. */
3733 /* Initialize the statistics for this function. */
3737 /* Now do the delay slot filling. Try everything twice in case earlier
3738 changes make more slots fillable. */
3742 reorg_pass_number++)
3743 {
3749 }
3751 /* If we made an end of function label, indicate that it is now
3752 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
3753 If it is now unused, delete it. */
3767 /* Delete any USE insns made by update_block; subsequent passes don't need
3768 them or know how to deal with them. */
3770 {
3776 }
3780 /* It is not clear why the line below is needed, but it does seem to be. */
3784 {
3791 reorg_pass_number++)
3792 {
3795 {
3804 {
3810 }
3812 }
3813 }
3817 {
3822 {
3824 {
3825 rtx control;
3832 else
3834 }
3837 }
3838 }
3842 {
3844 {
3849 }
3850 }
3854 {
3858 {
3860 {
3865 }
3866 }
3868 }
3871 }
3874 {
3877 }
3882 }
3883 \f
3884 /* Run delay slot optimization. */
3885 static unsigned int
3887 {
3892 }
3897 {
3907 };
3910 {
3914 {}
3916 /* opt_pass methods: */
3919 {
3921 }
3925 bool
3927 {
3928 /* At -O0 dataflow info isn't updated after RA. */
3933 }
3937 rtl_opt_pass *
3939 {
3941 }
3943 /* Machine dependent reorg pass. */
3948 {
3958 };
3961 {
3965 {}
3967 /* opt_pass methods: */
3969 {
3971 }
3974 {
3977 }
3983 rtl_opt_pass *
3985 {
3987 }