1 @c Copyright (C) 1988-2016 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 A @code{define_insn} expression is used to define instruction patterns
109 to which insns may be matched. A @code{define_insn} expression contains
110 an incomplete RTL expression, with pieces to be filled in later, operand
111 constraints that restrict how the pieces can be filled in, and an output
112 template or C code to generate the assembler output.
114 A @code{define_insn} is an RTL expression containing four or five operands:
118 An optional name. The presence of a name indicate that this instruction
119 pattern can perform a certain standard job for the RTL-generation
120 pass of the compiler. This pass knows certain names and will use
121 the instruction patterns with those names, if the names are defined
122 in the machine description.
124 The absence of a name is indicated by writing an empty string
125 where the name should go. Nameless instruction patterns are never
126 used for generating RTL code, but they may permit several simpler insns
127 to be combined later on.
129 Names that are not thus known and used in RTL-generation have no
130 effect; they are equivalent to no name at all.
132 For the purpose of debugging the compiler, you may also specify a
133 name beginning with the @samp{*} character. Such a name is used only
134 for identifying the instruction in RTL dumps; it is equivalent to having
135 a nameless pattern for all other purposes. Names beginning with the
136 @samp{*} character are not required to be unique.
139 The @dfn{RTL template}: This is a vector of incomplete RTL expressions
140 which describe the semantics of the instruction (@pxref{RTL Template}).
141 It is incomplete because it may contain @code{match_operand},
142 @code{match_operator}, and @code{match_dup} expressions that stand for
143 operands of the instruction.
145 If the vector has multiple elements, the RTL template is treated as a
146 @code{parallel} expression.
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 The condition: This is a string which contains a C expression. When the
152 compiler attempts to match RTL against a pattern, the condition is
153 evaluated. If the condition evaluates to @code{true}, the match is
154 permitted. The condition may be an empty string, which is treated
155 as always @code{true}.
157 @cindex named patterns and conditions
158 For a named pattern, the condition may not depend on the data in the
159 insn being matched, but only the target-machine-type flags. The compiler
160 needs to test these conditions during initialization in order to learn
161 exactly which named instructions are available in a particular run.
164 For nameless patterns, the condition is applied only when matching an
165 individual insn, and only after the insn has matched the pattern's
166 recognition template. The insn's operands may be found in the vector
169 For an insn where the condition has once matched, it
170 cannot later be used to control register allocation by excluding
171 certain register or value combinations.
174 The @dfn{output template} or @dfn{output statement}: This is either
175 a string, or a fragment of C code which returns a string.
177 When simple substitution isn't general enough, you can specify a piece
178 of C code to compute the output. @xref{Output Statement}.
181 The @dfn{insn attributes}: This is an optional vector containing the values of
182 attributes for insns matching this pattern (@pxref{Insn Attributes}).
186 @section Example of @code{define_insn}
187 @cindex @code{define_insn} example
189 Here is an example of an instruction pattern, taken from the machine
190 description for the 68000/68020.
195 (match_operand:SI 0 "general_operand" "rm"))]
199 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
201 return \"cmpl #0,%0\";
206 This can also be written using braced strings:
211 (match_operand:SI 0 "general_operand" "rm"))]
214 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
220 This describes an instruction which sets the condition codes based on the
221 value of a general operand. It has no condition, so any insn with an RTL
222 description of the form shown may be matched to this pattern. The name
223 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL
224 generation pass that, when it is necessary to test such a value, an insn
225 to do so can be constructed using this pattern.
227 The output control string is a piece of C code which chooses which
228 output template to return based on the kind of operand and the specific
229 type of CPU for which code is being generated.
231 @samp{"rm"} is an operand constraint. Its meaning is explained below.
234 @section RTL Template
235 @cindex RTL insn template
236 @cindex generating insns
237 @cindex insns, generating
238 @cindex recognizing insns
239 @cindex insns, recognizing
241 The RTL template is used to define which insns match the particular pattern
242 and how to find their operands. For named patterns, the RTL template also
243 says how to construct an insn from specified operands.
245 Construction involves substituting specified operands into a copy of the
246 template. Matching involves determining the values that serve as the
247 operands in the insn being matched. Both of these activities are
248 controlled by special expression types that direct matching and
249 substitution of the operands.
252 @findex match_operand
253 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
254 This expression is a placeholder for operand number @var{n} of
255 the insn. When constructing an insn, operand number @var{n}
256 will be substituted at this point. When matching an insn, whatever
257 appears at this position in the insn will be taken as operand
258 number @var{n}; but it must satisfy @var{predicate} or this instruction
259 pattern will not match at all.
261 Operand numbers must be chosen consecutively counting from zero in
262 each instruction pattern. There may be only one @code{match_operand}
263 expression in the pattern for each operand number. Usually operands
264 are numbered in the order of appearance in @code{match_operand}
265 expressions. In the case of a @code{define_expand}, any operand numbers
266 used only in @code{match_dup} expressions have higher values than all
267 other operand numbers.
269 @var{predicate} is a string that is the name of a function that
270 accepts two arguments, an expression and a machine mode.
271 @xref{Predicates}. During matching, the function will be called with
272 the putative operand as the expression and @var{m} as the mode
273 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
274 which normally causes @var{predicate} to accept any mode). If it
275 returns zero, this instruction pattern fails to match.
276 @var{predicate} may be an empty string; then it means no test is to be
277 done on the operand, so anything which occurs in this position is
280 Most of the time, @var{predicate} will reject modes other than @var{m}---but
281 not always. For example, the predicate @code{address_operand} uses
282 @var{m} as the mode of memory ref that the address should be valid for.
283 Many predicates accept @code{const_int} nodes even though their mode is
286 @var{constraint} controls reloading and the choice of the best register
287 class to use for a value, as explained later (@pxref{Constraints}).
288 If the constraint would be an empty string, it can be omitted.
290 People are often unclear on the difference between the constraint and the
291 predicate. The predicate helps decide whether a given insn matches the
292 pattern. The constraint plays no role in this decision; instead, it
293 controls various decisions in the case of an insn which does match.
295 @findex match_scratch
296 @item (match_scratch:@var{m} @var{n} @var{constraint})
297 This expression is also a placeholder for operand number @var{n}
298 and indicates that operand must be a @code{scratch} or @code{reg}
301 When matching patterns, this is equivalent to
304 (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint})
307 but, when generating RTL, it produces a (@code{scratch}:@var{m})
310 If the last few expressions in a @code{parallel} are @code{clobber}
311 expressions whose operands are either a hard register or
312 @code{match_scratch}, the combiner can add or delete them when
313 necessary. @xref{Side Effects}.
316 @item (match_dup @var{n})
317 This expression is also a placeholder for operand number @var{n}.
318 It is used when the operand needs to appear more than once in the
321 In construction, @code{match_dup} acts just like @code{match_operand}:
322 the operand is substituted into the insn being constructed. But in
323 matching, @code{match_dup} behaves differently. It assumes that operand
324 number @var{n} has already been determined by a @code{match_operand}
325 appearing earlier in the recognition template, and it matches only an
326 identical-looking expression.
328 Note that @code{match_dup} should not be used to tell the compiler that
329 a particular register is being used for two operands (example:
330 @code{add} that adds one register to another; the second register is
331 both an input operand and the output operand). Use a matching
332 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
333 operand is used in two places in the template, such as an instruction
334 that computes both a quotient and a remainder, where the opcode takes
335 two input operands but the RTL template has to refer to each of those
336 twice; once for the quotient pattern and once for the remainder pattern.
338 @findex match_operator
339 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
340 This pattern is a kind of placeholder for a variable RTL expression
343 When constructing an insn, it stands for an RTL expression whose
344 expression code is taken from that of operand @var{n}, and whose
345 operands are constructed from the patterns @var{operands}.
347 When matching an expression, it matches an expression if the function
348 @var{predicate} returns nonzero on that expression @emph{and} the
349 patterns @var{operands} match the operands of the expression.
351 Suppose that the function @code{commutative_operator} is defined as
352 follows, to match any expression whose operator is one of the
353 commutative arithmetic operators of RTL and whose mode is @var{mode}:
357 commutative_integer_operator (x, mode)
361 enum rtx_code code = GET_CODE (x);
362 if (GET_MODE (x) != mode)
364 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
365 || code == EQ || code == NE);
369 Then the following pattern will match any RTL expression consisting
370 of a commutative operator applied to two general operands:
373 (match_operator:SI 3 "commutative_operator"
374 [(match_operand:SI 1 "general_operand" "g")
375 (match_operand:SI 2 "general_operand" "g")])
378 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
379 because the expressions to be matched all contain two operands.
381 When this pattern does match, the two operands of the commutative
382 operator are recorded as operands 1 and 2 of the insn. (This is done
383 by the two instances of @code{match_operand}.) Operand 3 of the insn
384 will be the entire commutative expression: use @code{GET_CODE
385 (operands[3])} to see which commutative operator was used.
387 The machine mode @var{m} of @code{match_operator} works like that of
388 @code{match_operand}: it is passed as the second argument to the
389 predicate function, and that function is solely responsible for
390 deciding whether the expression to be matched ``has'' that mode.
392 When constructing an insn, argument 3 of the gen-function will specify
393 the operation (i.e.@: the expression code) for the expression to be
394 made. It should be an RTL expression, whose expression code is copied
395 into a new expression whose operands are arguments 1 and 2 of the
396 gen-function. The subexpressions of argument 3 are not used;
397 only its expression code matters.
399 When @code{match_operator} is used in a pattern for matching an insn,
400 it usually best if the operand number of the @code{match_operator}
401 is higher than that of the actual operands of the insn. This improves
402 register allocation because the register allocator often looks at
403 operands 1 and 2 of insns to see if it can do register tying.
405 There is no way to specify constraints in @code{match_operator}. The
406 operand of the insn which corresponds to the @code{match_operator}
407 never has any constraints because it is never reloaded as a whole.
408 However, if parts of its @var{operands} are matched by
409 @code{match_operand} patterns, those parts may have constraints of
413 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
414 Like @code{match_dup}, except that it applies to operators instead of
415 operands. When constructing an insn, operand number @var{n} will be
416 substituted at this point. But in matching, @code{match_op_dup} behaves
417 differently. It assumes that operand number @var{n} has already been
418 determined by a @code{match_operator} appearing earlier in the
419 recognition template, and it matches only an identical-looking
422 @findex match_parallel
423 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
424 This pattern is a placeholder for an insn that consists of a
425 @code{parallel} expression with a variable number of elements. This
426 expression should only appear at the top level of an insn pattern.
428 When constructing an insn, operand number @var{n} will be substituted at
429 this point. When matching an insn, it matches if the body of the insn
430 is a @code{parallel} expression with at least as many elements as the
431 vector of @var{subpat} expressions in the @code{match_parallel}, if each
432 @var{subpat} matches the corresponding element of the @code{parallel},
433 @emph{and} the function @var{predicate} returns nonzero on the
434 @code{parallel} that is the body of the insn. It is the responsibility
435 of the predicate to validate elements of the @code{parallel} beyond
436 those listed in the @code{match_parallel}.
438 A typical use of @code{match_parallel} is to match load and store
439 multiple expressions, which can contain a variable number of elements
440 in a @code{parallel}. For example,
444 [(match_parallel 0 "load_multiple_operation"
445 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
446 (match_operand:SI 2 "memory_operand" "m"))
448 (clobber (reg:SI 179))])]
453 This example comes from @file{a29k.md}. The function
454 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
455 that subsequent elements in the @code{parallel} are the same as the
456 @code{set} in the pattern, except that they are referencing subsequent
457 registers and memory locations.
459 An insn that matches this pattern might look like:
463 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
465 (clobber (reg:SI 179))
467 (mem:SI (plus:SI (reg:SI 100)
470 (mem:SI (plus:SI (reg:SI 100)
474 @findex match_par_dup
475 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
476 Like @code{match_op_dup}, but for @code{match_parallel} instead of
477 @code{match_operator}.
481 @node Output Template
482 @section Output Templates and Operand Substitution
483 @cindex output templates
484 @cindex operand substitution
486 @cindex @samp{%} in template
488 The @dfn{output template} is a string which specifies how to output the
489 assembler code for an instruction pattern. Most of the template is a
490 fixed string which is output literally. The character @samp{%} is used
491 to specify where to substitute an operand; it can also be used to
492 identify places where different variants of the assembler require
495 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
496 operand @var{n} at that point in the string.
498 @samp{%} followed by a letter and a digit says to output an operand in an
499 alternate fashion. Four letters have standard, built-in meanings described
500 below. The machine description macro @code{PRINT_OPERAND} can define
501 additional letters with nonstandard meanings.
503 @samp{%c@var{digit}} can be used to substitute an operand that is a
504 constant value without the syntax that normally indicates an immediate
507 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
508 the constant is negated before printing.
510 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
511 memory reference, with the actual operand treated as the address. This may
512 be useful when outputting a ``load address'' instruction, because often the
513 assembler syntax for such an instruction requires you to write the operand
514 as if it were a memory reference.
516 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
519 @samp{%=} outputs a number which is unique to each instruction in the
520 entire compilation. This is useful for making local labels to be
521 referred to more than once in a single template that generates multiple
522 assembler instructions.
524 @samp{%} followed by a punctuation character specifies a substitution that
525 does not use an operand. Only one case is standard: @samp{%%} outputs a
526 @samp{%} into the assembler code. Other nonstandard cases can be
527 defined in the @code{PRINT_OPERAND} macro. You must also define
528 which punctuation characters are valid with the
529 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
533 The template may generate multiple assembler instructions. Write the text
534 for the instructions, with @samp{\;} between them.
536 @cindex matching operands
537 When the RTL contains two operands which are required by constraint to match
538 each other, the output template must refer only to the lower-numbered operand.
539 Matching operands are not always identical, and the rest of the compiler
540 arranges to put the proper RTL expression for printing into the lower-numbered
543 One use of nonstandard letters or punctuation following @samp{%} is to
544 distinguish between different assembler languages for the same machine; for
545 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
546 requires periods in most opcode names, while MIT syntax does not. For
547 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
548 syntax. The same file of patterns is used for both kinds of output syntax,
549 but the character sequence @samp{%.} is used in each place where Motorola
550 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
551 defines the sequence to output a period; the macro for MIT syntax defines
554 @cindex @code{#} in template
555 As a special case, a template consisting of the single character @code{#}
556 instructs the compiler to first split the insn, and then output the
557 resulting instructions separately. This helps eliminate redundancy in the
558 output templates. If you have a @code{define_insn} that needs to emit
559 multiple assembler instructions, and there is a matching @code{define_split}
560 already defined, then you can simply use @code{#} as the output template
561 instead of writing an output template that emits the multiple assembler
564 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
565 of the form @samp{@{option0|option1|option2@}} in the templates. These
566 describe multiple variants of assembler language syntax.
567 @xref{Instruction Output}.
569 @node Output Statement
570 @section C Statements for Assembler Output
571 @cindex output statements
572 @cindex C statements for assembler output
573 @cindex generating assembler output
575 Often a single fixed template string cannot produce correct and efficient
576 assembler code for all the cases that are recognized by a single
577 instruction pattern. For example, the opcodes may depend on the kinds of
578 operands; or some unfortunate combinations of operands may require extra
579 machine instructions.
581 If the output control string starts with a @samp{@@}, then it is actually
582 a series of templates, each on a separate line. (Blank lines and
583 leading spaces and tabs are ignored.) The templates correspond to the
584 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
585 if a target machine has a two-address add instruction @samp{addr} to add
586 into a register and another @samp{addm} to add a register to memory, you
587 might write this pattern:
590 (define_insn "addsi3"
591 [(set (match_operand:SI 0 "general_operand" "=r,m")
592 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
593 (match_operand:SI 2 "general_operand" "g,r")))]
600 @cindex @code{*} in template
601 @cindex asterisk in template
602 If the output control string starts with a @samp{*}, then it is not an
603 output template but rather a piece of C program that should compute a
604 template. It should execute a @code{return} statement to return the
605 template-string you want. Most such templates use C string literals, which
606 require doublequote characters to delimit them. To include these
607 doublequote characters in the string, prefix each one with @samp{\}.
609 If the output control string is written as a brace block instead of a
610 double-quoted string, it is automatically assumed to be C code. In that
611 case, it is not necessary to put in a leading asterisk, or to escape the
612 doublequotes surrounding C string literals.
614 The operands may be found in the array @code{operands}, whose C data type
617 It is very common to select different ways of generating assembler code
618 based on whether an immediate operand is within a certain range. Be
619 careful when doing this, because the result of @code{INTVAL} is an
620 integer on the host machine. If the host machine has more bits in an
621 @code{int} than the target machine has in the mode in which the constant
622 will be used, then some of the bits you get from @code{INTVAL} will be
623 superfluous. For proper results, you must carefully disregard the
624 values of those bits.
626 @findex output_asm_insn
627 It is possible to output an assembler instruction and then go on to output
628 or compute more of them, using the subroutine @code{output_asm_insn}. This
629 receives two arguments: a template-string and a vector of operands. The
630 vector may be @code{operands}, or it may be another array of @code{rtx}
631 that you declare locally and initialize yourself.
633 @findex which_alternative
634 When an insn pattern has multiple alternatives in its constraints, often
635 the appearance of the assembler code is determined mostly by which alternative
636 was matched. When this is so, the C code can test the variable
637 @code{which_alternative}, which is the ordinal number of the alternative
638 that was actually satisfied (0 for the first, 1 for the second alternative,
641 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
642 for registers and @samp{clrmem} for memory locations. Here is how
643 a pattern could use @code{which_alternative} to choose between them:
647 [(set (match_operand:SI 0 "general_operand" "=r,m")
651 return (which_alternative == 0
652 ? "clrreg %0" : "clrmem %0");
656 The example above, where the assembler code to generate was
657 @emph{solely} determined by the alternative, could also have been specified
658 as follows, having the output control string start with a @samp{@@}:
663 [(set (match_operand:SI 0 "general_operand" "=r,m")
672 If you just need a little bit of C code in one (or a few) alternatives,
673 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
678 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
683 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
691 @cindex operand predicates
692 @cindex operator predicates
694 A predicate determines whether a @code{match_operand} or
695 @code{match_operator} expression matches, and therefore whether the
696 surrounding instruction pattern will be used for that combination of
697 operands. GCC has a number of machine-independent predicates, and you
698 can define machine-specific predicates as needed. By convention,
699 predicates used with @code{match_operand} have names that end in
700 @samp{_operand}, and those used with @code{match_operator} have names
701 that end in @samp{_operator}.
703 All predicates are Boolean functions (in the mathematical sense) of
704 two arguments: the RTL expression that is being considered at that
705 position in the instruction pattern, and the machine mode that the
706 @code{match_operand} or @code{match_operator} specifies. In this
707 section, the first argument is called @var{op} and the second argument
708 @var{mode}. Predicates can be called from C as ordinary two-argument
709 functions; this can be useful in output templates or other
710 machine-specific code.
712 Operand predicates can allow operands that are not actually acceptable
713 to the hardware, as long as the constraints give reload the ability to
714 fix them up (@pxref{Constraints}). However, GCC will usually generate
715 better code if the predicates specify the requirements of the machine
716 instructions as closely as possible. Reload cannot fix up operands
717 that must be constants (``immediate operands''); you must use a
718 predicate that allows only constants, or else enforce the requirement
719 in the extra condition.
721 @cindex predicates and machine modes
722 @cindex normal predicates
723 @cindex special predicates
724 Most predicates handle their @var{mode} argument in a uniform manner.
725 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
726 any mode. If @var{mode} is anything else, then @var{op} must have the
727 same mode, unless @var{op} is a @code{CONST_INT} or integer
728 @code{CONST_DOUBLE}. These RTL expressions always have
729 @code{VOIDmode}, so it would be counterproductive to check that their
730 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
731 integer @code{CONST_DOUBLE} check that the value stored in the
732 constant will fit in the requested mode.
734 Predicates with this behavior are called @dfn{normal}.
735 @command{genrecog} can optimize the instruction recognizer based on
736 knowledge of how normal predicates treat modes. It can also diagnose
737 certain kinds of common errors in the use of normal predicates; for
738 instance, it is almost always an error to use a normal predicate
739 without specifying a mode.
741 Predicates that do something different with their @var{mode} argument
742 are called @dfn{special}. The generic predicates
743 @code{address_operand} and @code{pmode_register_operand} are special
744 predicates. @command{genrecog} does not do any optimizations or
745 diagnosis when special predicates are used.
748 * Machine-Independent Predicates:: Predicates available to all back ends.
749 * Defining Predicates:: How to write machine-specific predicate
753 @node Machine-Independent Predicates
754 @subsection Machine-Independent Predicates
755 @cindex machine-independent predicates
756 @cindex generic predicates
758 These are the generic predicates available to all back ends. They are
759 defined in @file{recog.c}. The first category of predicates allow
760 only constant, or @dfn{immediate}, operands.
762 @defun immediate_operand
763 This predicate allows any sort of constant that fits in @var{mode}.
764 It is an appropriate choice for instructions that take operands that
768 @defun const_int_operand
769 This predicate allows any @code{CONST_INT} expression that fits in
770 @var{mode}. It is an appropriate choice for an immediate operand that
771 does not allow a symbol or label.
774 @defun const_double_operand
775 This predicate accepts any @code{CONST_DOUBLE} expression that has
776 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
777 accept @code{CONST_INT}. It is intended for immediate floating point
782 The second category of predicates allow only some kind of machine
785 @defun register_operand
786 This predicate allows any @code{REG} or @code{SUBREG} expression that
787 is valid for @var{mode}. It is often suitable for arithmetic
788 instruction operands on a RISC machine.
791 @defun pmode_register_operand
792 This is a slight variant on @code{register_operand} which works around
793 a limitation in the machine-description reader.
796 (match_operand @var{n} "pmode_register_operand" @var{constraint})
803 (match_operand:P @var{n} "register_operand" @var{constraint})
807 would mean, if the machine-description reader accepted @samp{:P}
808 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
809 alias for some other mode, and might vary with machine-specific
810 options. @xref{Misc}.
813 @defun scratch_operand
814 This predicate allows hard registers and @code{SCRATCH} expressions,
815 but not pseudo-registers. It is used internally by @code{match_scratch};
816 it should not be used directly.
820 The third category of predicates allow only some kind of memory reference.
822 @defun memory_operand
823 This predicate allows any valid reference to a quantity of mode
824 @var{mode} in memory, as determined by the weak form of
825 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
828 @defun address_operand
829 This predicate is a little unusual; it allows any operand that is a
830 valid expression for the @emph{address} of a quantity of mode
831 @var{mode}, again determined by the weak form of
832 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
833 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
834 @code{memory_operand}, then @var{exp} is acceptable to
835 @code{address_operand}. Note that @var{exp} does not necessarily have
839 @defun indirect_operand
840 This is a stricter form of @code{memory_operand} which allows only
841 memory references with a @code{general_operand} as the address
842 expression. New uses of this predicate are discouraged, because
843 @code{general_operand} is very permissive, so it's hard to tell what
844 an @code{indirect_operand} does or does not allow. If a target has
845 different requirements for memory operands for different instructions,
846 it is better to define target-specific predicates which enforce the
847 hardware's requirements explicitly.
851 This predicate allows a memory reference suitable for pushing a value
852 onto the stack. This will be a @code{MEM} which refers to
853 @code{stack_pointer_rtx}, with a side-effect in its address expression
854 (@pxref{Incdec}); which one is determined by the
855 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
859 This predicate allows a memory reference suitable for popping a value
860 off the stack. Again, this will be a @code{MEM} referring to
861 @code{stack_pointer_rtx}, with a side-effect in its address
862 expression. However, this time @code{STACK_POP_CODE} is expected.
866 The fourth category of predicates allow some combination of the above
869 @defun nonmemory_operand
870 This predicate allows any immediate or register operand valid for @var{mode}.
873 @defun nonimmediate_operand
874 This predicate allows any register or memory operand valid for @var{mode}.
877 @defun general_operand
878 This predicate allows any immediate, register, or memory operand
879 valid for @var{mode}.
883 Finally, there are two generic operator predicates.
885 @defun comparison_operator
886 This predicate matches any expression which performs an arithmetic
887 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
891 @defun ordered_comparison_operator
892 This predicate matches any expression which performs an arithmetic
893 comparison in @var{mode} and whose expression code is valid for integer
894 modes; that is, the expression code will be one of @code{eq}, @code{ne},
895 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
896 @code{ge}, @code{geu}.
899 @node Defining Predicates
900 @subsection Defining Machine-Specific Predicates
901 @cindex defining predicates
902 @findex define_predicate
903 @findex define_special_predicate
905 Many machines have requirements for their operands that cannot be
906 expressed precisely using the generic predicates. You can define
907 additional predicates using @code{define_predicate} and
908 @code{define_special_predicate} expressions. These expressions have
913 The name of the predicate, as it will be referred to in
914 @code{match_operand} or @code{match_operator} expressions.
917 An RTL expression which evaluates to true if the predicate allows the
918 operand @var{op}, false if it does not. This expression can only use
919 the following RTL codes:
923 When written inside a predicate expression, a @code{MATCH_OPERAND}
924 expression evaluates to true if the predicate it names would allow
925 @var{op}. The operand number and constraint are ignored. Due to
926 limitations in @command{genrecog}, you can only refer to generic
927 predicates and predicates that have already been defined.
930 This expression evaluates to true if @var{op} or a specified
931 subexpression of @var{op} has one of a given list of RTX codes.
933 The first operand of this expression is a string constant containing a
934 comma-separated list of RTX code names (in lower case). These are the
935 codes for which the @code{MATCH_CODE} will be true.
937 The second operand is a string constant which indicates what
938 subexpression of @var{op} to examine. If it is absent or the empty
939 string, @var{op} itself is examined. Otherwise, the string constant
940 must be a sequence of digits and/or lowercase letters. Each character
941 indicates a subexpression to extract from the current expression; for
942 the first character this is @var{op}, for the second and subsequent
943 characters it is the result of the previous character. A digit
944 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
945 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
946 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
947 @code{MATCH_CODE} then examines the RTX code of the subexpression
948 extracted by the complete string. It is not possible to extract
949 components of an @code{rtvec} that is not at position 0 within its RTX
953 This expression has one operand, a string constant containing a C
954 expression. The predicate's arguments, @var{op} and @var{mode}, are
955 available with those names in the C expression. The @code{MATCH_TEST}
956 evaluates to true if the C expression evaluates to a nonzero value.
957 @code{MATCH_TEST} expressions must not have side effects.
963 The basic @samp{MATCH_} expressions can be combined using these
964 logical operators, which have the semantics of the C operators
965 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
966 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
967 arbitrary number of arguments; this has exactly the same effect as
968 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
972 An optional block of C code, which should execute
973 @samp{@w{return true}} if the predicate is found to match and
974 @samp{@w{return false}} if it does not. It must not have any side
975 effects. The predicate arguments, @var{op} and @var{mode}, are
976 available with those names.
978 If a code block is present in a predicate definition, then the RTL
979 expression must evaluate to true @emph{and} the code block must
980 execute @samp{@w{return true}} for the predicate to allow the operand.
981 The RTL expression is evaluated first; do not re-check anything in the
982 code block that was checked in the RTL expression.
985 The program @command{genrecog} scans @code{define_predicate} and
986 @code{define_special_predicate} expressions to determine which RTX
987 codes are possibly allowed. You should always make this explicit in
988 the RTL predicate expression, using @code{MATCH_OPERAND} and
991 Here is an example of a simple predicate definition, from the IA64
996 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
997 (define_predicate "small_addr_symbolic_operand"
998 (and (match_code "symbol_ref")
999 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1004 And here is another, showing the use of the C block.
1008 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1009 (define_predicate "gr_register_operand"
1010 (match_operand 0 "register_operand")
1013 if (GET_CODE (op) == SUBREG)
1014 op = SUBREG_REG (op);
1017 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1022 Predicates written with @code{define_predicate} automatically include
1023 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1024 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1025 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1026 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1027 kind of constant fits in the requested mode. This is because
1028 target-specific predicates that take constants usually have to do more
1029 stringent value checks anyway. If you need the exact same treatment
1030 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1031 provide, use a @code{MATCH_OPERAND} subexpression to call
1032 @code{const_int_operand}, @code{const_double_operand}, or
1033 @code{immediate_operand}.
1035 Predicates written with @code{define_special_predicate} do not get any
1036 automatic mode checks, and are treated as having special mode handling
1037 by @command{genrecog}.
1039 The program @command{genpreds} is responsible for generating code to
1040 test predicates. It also writes a header file containing function
1041 declarations for all machine-specific predicates. It is not necessary
1042 to declare these predicates in @file{@var{cpu}-protos.h}.
1045 @c Most of this node appears by itself (in a different place) even
1046 @c when the INTERNALS flag is clear. Passages that require the internals
1047 @c manual's context are conditionalized to appear only in the internals manual.
1050 @section Operand Constraints
1051 @cindex operand constraints
1054 Each @code{match_operand} in an instruction pattern can specify
1055 constraints for the operands allowed. The constraints allow you to
1056 fine-tune matching within the set of operands allowed by the
1062 @section Constraints for @code{asm} Operands
1063 @cindex operand constraints, @code{asm}
1064 @cindex constraints, @code{asm}
1065 @cindex @code{asm} constraints
1067 Here are specific details on what constraint letters you can use with
1068 @code{asm} operands.
1070 Constraints can say whether
1071 an operand may be in a register, and which kinds of register; whether the
1072 operand can be a memory reference, and which kinds of address; whether the
1073 operand may be an immediate constant, and which possible values it may
1074 have. Constraints can also require two operands to match.
1075 Side-effects aren't allowed in operands of inline @code{asm}, unless
1076 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1077 that the side-effects will happen exactly once in an instruction that can update
1078 the addressing register.
1082 * Simple Constraints:: Basic use of constraints.
1083 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1084 * Class Preferences:: Constraints guide which hard register to put things in.
1085 * Modifiers:: More precise control over effects of constraints.
1086 * Machine Constraints:: Existing constraints for some particular machines.
1087 * Disable Insn Alternatives:: Disable insn alternatives using attributes.
1088 * Define Constraints:: How to define machine-specific constraints.
1089 * C Constraint Interface:: How to test constraints from C code.
1095 * Simple Constraints:: Basic use of constraints.
1096 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1097 * Modifiers:: More precise control over effects of constraints.
1098 * Machine Constraints:: Special constraints for some particular machines.
1102 @node Simple Constraints
1103 @subsection Simple Constraints
1104 @cindex simple constraints
1106 The simplest kind of constraint is a string full of letters, each of
1107 which describes one kind of operand that is permitted. Here are
1108 the letters that are allowed:
1112 Whitespace characters are ignored and can be inserted at any position
1113 except the first. This enables each alternative for different operands to
1114 be visually aligned in the machine description even if they have different
1115 number of constraints and modifiers.
1117 @cindex @samp{m} in constraint
1118 @cindex memory references in constraints
1120 A memory operand is allowed, with any kind of address that the machine
1121 supports in general.
1122 Note that the letter used for the general memory constraint can be
1123 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1125 @cindex offsettable address
1126 @cindex @samp{o} in constraint
1128 A memory operand is allowed, but only if the address is
1129 @dfn{offsettable}. This means that adding a small integer (actually,
1130 the width in bytes of the operand, as determined by its machine mode)
1131 may be added to the address and the result is also a valid memory
1134 @cindex autoincrement/decrement addressing
1135 For example, an address which is constant is offsettable; so is an
1136 address that is the sum of a register and a constant (as long as a
1137 slightly larger constant is also within the range of address-offsets
1138 supported by the machine); but an autoincrement or autodecrement
1139 address is not offsettable. More complicated indirect/indexed
1140 addresses may or may not be offsettable depending on the other
1141 addressing modes that the machine supports.
1143 Note that in an output operand which can be matched by another
1144 operand, the constraint letter @samp{o} is valid only when accompanied
1145 by both @samp{<} (if the target machine has predecrement addressing)
1146 and @samp{>} (if the target machine has preincrement addressing).
1148 @cindex @samp{V} in constraint
1150 A memory operand that is not offsettable. In other words, anything that
1151 would fit the @samp{m} constraint but not the @samp{o} constraint.
1153 @cindex @samp{<} in constraint
1155 A memory operand with autodecrement addressing (either predecrement or
1156 postdecrement) is allowed. In inline @code{asm} this constraint is only
1157 allowed if the operand is used exactly once in an instruction that can
1158 handle the side-effects. Not using an operand with @samp{<} in constraint
1159 string in the inline @code{asm} pattern at all or using it in multiple
1160 instructions isn't valid, because the side-effects wouldn't be performed
1161 or would be performed more than once. Furthermore, on some targets
1162 the operand with @samp{<} in constraint string must be accompanied by
1163 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1164 or @code{%P0} on IA-64.
1166 @cindex @samp{>} in constraint
1168 A memory operand with autoincrement addressing (either preincrement or
1169 postincrement) is allowed. In inline @code{asm} the same restrictions
1170 as for @samp{<} apply.
1172 @cindex @samp{r} in constraint
1173 @cindex registers in constraints
1175 A register operand is allowed provided that it is in a general
1178 @cindex constants in constraints
1179 @cindex @samp{i} in constraint
1181 An immediate integer operand (one with constant value) is allowed.
1182 This includes symbolic constants whose values will be known only at
1183 assembly time or later.
1185 @cindex @samp{n} in constraint
1187 An immediate integer operand with a known numeric value is allowed.
1188 Many systems cannot support assembly-time constants for operands less
1189 than a word wide. Constraints for these operands should use @samp{n}
1190 rather than @samp{i}.
1192 @cindex @samp{I} in constraint
1193 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1194 Other letters in the range @samp{I} through @samp{P} may be defined in
1195 a machine-dependent fashion to permit immediate integer operands with
1196 explicit integer values in specified ranges. For example, on the
1197 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1198 This is the range permitted as a shift count in the shift
1201 @cindex @samp{E} in constraint
1203 An immediate floating operand (expression code @code{const_double}) is
1204 allowed, but only if the target floating point format is the same as
1205 that of the host machine (on which the compiler is running).
1207 @cindex @samp{F} in constraint
1209 An immediate floating operand (expression code @code{const_double} or
1210 @code{const_vector}) is allowed.
1212 @cindex @samp{G} in constraint
1213 @cindex @samp{H} in constraint
1214 @item @samp{G}, @samp{H}
1215 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1216 permit immediate floating operands in particular ranges of values.
1218 @cindex @samp{s} in constraint
1220 An immediate integer operand whose value is not an explicit integer is
1223 This might appear strange; if an insn allows a constant operand with a
1224 value not known at compile time, it certainly must allow any known
1225 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1226 better code to be generated.
1228 For example, on the 68000 in a fullword instruction it is possible to
1229 use an immediate operand; but if the immediate value is between @minus{}128
1230 and 127, better code results from loading the value into a register and
1231 using the register. This is because the load into the register can be
1232 done with a @samp{moveq} instruction. We arrange for this to happen
1233 by defining the letter @samp{K} to mean ``any integer outside the
1234 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1237 @cindex @samp{g} in constraint
1239 Any register, memory or immediate integer operand is allowed, except for
1240 registers that are not general registers.
1242 @cindex @samp{X} in constraint
1245 Any operand whatsoever is allowed, even if it does not satisfy
1246 @code{general_operand}. This is normally used in the constraint of
1247 a @code{match_scratch} when certain alternatives will not actually
1248 require a scratch register.
1251 Any operand whatsoever is allowed.
1254 @cindex @samp{0} in constraint
1255 @cindex digits in constraint
1256 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1257 An operand that matches the specified operand number is allowed. If a
1258 digit is used together with letters within the same alternative, the
1259 digit should come last.
1261 This number is allowed to be more than a single digit. If multiple
1262 digits are encountered consecutively, they are interpreted as a single
1263 decimal integer. There is scant chance for ambiguity, since to-date
1264 it has never been desirable that @samp{10} be interpreted as matching
1265 either operand 1 @emph{or} operand 0. Should this be desired, one
1266 can use multiple alternatives instead.
1268 @cindex matching constraint
1269 @cindex constraint, matching
1270 This is called a @dfn{matching constraint} and what it really means is
1271 that the assembler has only a single operand that fills two roles
1273 considered separate in the RTL insn. For example, an add insn has two
1274 input operands and one output operand in the RTL, but on most CISC
1277 which @code{asm} distinguishes. For example, an add instruction uses
1278 two input operands and an output operand, but on most CISC
1280 machines an add instruction really has only two operands, one of them an
1281 input-output operand:
1287 Matching constraints are used in these circumstances.
1288 More precisely, the two operands that match must include one input-only
1289 operand and one output-only operand. Moreover, the digit must be a
1290 smaller number than the number of the operand that uses it in the
1294 For operands to match in a particular case usually means that they
1295 are identical-looking RTL expressions. But in a few special cases
1296 specific kinds of dissimilarity are allowed. For example, @code{*x}
1297 as an input operand will match @code{*x++} as an output operand.
1298 For proper results in such cases, the output template should always
1299 use the output-operand's number when printing the operand.
1302 @cindex load address instruction
1303 @cindex push address instruction
1304 @cindex address constraints
1305 @cindex @samp{p} in constraint
1307 An operand that is a valid memory address is allowed. This is
1308 for ``load address'' and ``push address'' instructions.
1310 @findex address_operand
1311 @samp{p} in the constraint must be accompanied by @code{address_operand}
1312 as the predicate in the @code{match_operand}. This predicate interprets
1313 the mode specified in the @code{match_operand} as the mode of the memory
1314 reference for which the address would be valid.
1316 @cindex other register constraints
1317 @cindex extensible constraints
1318 @item @var{other-letters}
1319 Other letters can be defined in machine-dependent fashion to stand for
1320 particular classes of registers or other arbitrary operand types.
1321 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1322 for data, address and floating point registers.
1326 In order to have valid assembler code, each operand must satisfy
1327 its constraint. But a failure to do so does not prevent the pattern
1328 from applying to an insn. Instead, it directs the compiler to modify
1329 the code so that the constraint will be satisfied. Usually this is
1330 done by copying an operand into a register.
1332 Contrast, therefore, the two instruction patterns that follow:
1336 [(set (match_operand:SI 0 "general_operand" "=r")
1337 (plus:SI (match_dup 0)
1338 (match_operand:SI 1 "general_operand" "r")))]
1344 which has two operands, one of which must appear in two places, and
1348 [(set (match_operand:SI 0 "general_operand" "=r")
1349 (plus:SI (match_operand:SI 1 "general_operand" "0")
1350 (match_operand:SI 2 "general_operand" "r")))]
1356 which has three operands, two of which are required by a constraint to be
1357 identical. If we are considering an insn of the form
1360 (insn @var{n} @var{prev} @var{next}
1362 (plus:SI (reg:SI 6) (reg:SI 109)))
1367 the first pattern would not apply at all, because this insn does not
1368 contain two identical subexpressions in the right place. The pattern would
1369 say, ``That does not look like an add instruction; try other patterns''.
1370 The second pattern would say, ``Yes, that's an add instruction, but there
1371 is something wrong with it''. It would direct the reload pass of the
1372 compiler to generate additional insns to make the constraint true. The
1373 results might look like this:
1376 (insn @var{n2} @var{prev} @var{n}
1377 (set (reg:SI 3) (reg:SI 6))
1380 (insn @var{n} @var{n2} @var{next}
1382 (plus:SI (reg:SI 3) (reg:SI 109)))
1386 It is up to you to make sure that each operand, in each pattern, has
1387 constraints that can handle any RTL expression that could be present for
1388 that operand. (When multiple alternatives are in use, each pattern must,
1389 for each possible combination of operand expressions, have at least one
1390 alternative which can handle that combination of operands.) The
1391 constraints don't need to @emph{allow} any possible operand---when this is
1392 the case, they do not constrain---but they must at least point the way to
1393 reloading any possible operand so that it will fit.
1397 If the constraint accepts whatever operands the predicate permits,
1398 there is no problem: reloading is never necessary for this operand.
1400 For example, an operand whose constraints permit everything except
1401 registers is safe provided its predicate rejects registers.
1403 An operand whose predicate accepts only constant values is safe
1404 provided its constraints include the letter @samp{i}. If any possible
1405 constant value is accepted, then nothing less than @samp{i} will do;
1406 if the predicate is more selective, then the constraints may also be
1410 Any operand expression can be reloaded by copying it into a register.
1411 So if an operand's constraints allow some kind of register, it is
1412 certain to be safe. It need not permit all classes of registers; the
1413 compiler knows how to copy a register into another register of the
1414 proper class in order to make an instruction valid.
1416 @cindex nonoffsettable memory reference
1417 @cindex memory reference, nonoffsettable
1419 A nonoffsettable memory reference can be reloaded by copying the
1420 address into a register. So if the constraint uses the letter
1421 @samp{o}, all memory references are taken care of.
1424 A constant operand can be reloaded by allocating space in memory to
1425 hold it as preinitialized data. Then the memory reference can be used
1426 in place of the constant. So if the constraint uses the letters
1427 @samp{o} or @samp{m}, constant operands are not a problem.
1430 If the constraint permits a constant and a pseudo register used in an insn
1431 was not allocated to a hard register and is equivalent to a constant,
1432 the register will be replaced with the constant. If the predicate does
1433 not permit a constant and the insn is re-recognized for some reason, the
1434 compiler will crash. Thus the predicate must always recognize any
1435 objects allowed by the constraint.
1438 If the operand's predicate can recognize registers, but the constraint does
1439 not permit them, it can make the compiler crash. When this operand happens
1440 to be a register, the reload pass will be stymied, because it does not know
1441 how to copy a register temporarily into memory.
1443 If the predicate accepts a unary operator, the constraint applies to the
1444 operand. For example, the MIPS processor at ISA level 3 supports an
1445 instruction which adds two registers in @code{SImode} to produce a
1446 @code{DImode} result, but only if the registers are correctly sign
1447 extended. This predicate for the input operands accepts a
1448 @code{sign_extend} of an @code{SImode} register. Write the constraint
1449 to indicate the type of register that is required for the operand of the
1453 @node Multi-Alternative
1454 @subsection Multiple Alternative Constraints
1455 @cindex multiple alternative constraints
1457 Sometimes a single instruction has multiple alternative sets of possible
1458 operands. For example, on the 68000, a logical-or instruction can combine
1459 register or an immediate value into memory, or it can combine any kind of
1460 operand into a register; but it cannot combine one memory location into
1463 These constraints are represented as multiple alternatives. An alternative
1464 can be described by a series of letters for each operand. The overall
1465 constraint for an operand is made from the letters for this operand
1466 from the first alternative, a comma, the letters for this operand from
1467 the second alternative, a comma, and so on until the last alternative.
1468 All operands for a single instruction must have the same number of
1471 Here is how it is done for fullword logical-or on the 68000:
1474 (define_insn "iorsi3"
1475 [(set (match_operand:SI 0 "general_operand" "=m,d")
1476 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1477 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1481 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1482 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1483 2. The second alternative has @samp{d} (data register) for operand 0,
1484 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1485 @samp{%} in the constraints apply to all the alternatives; their
1486 meaning is explained in the next section (@pxref{Class Preferences}).
1488 If all the operands fit any one alternative, the instruction is valid.
1489 Otherwise, for each alternative, the compiler counts how many instructions
1490 must be added to copy the operands so that that alternative applies.
1491 The alternative requiring the least copying is chosen. If two alternatives
1492 need the same amount of copying, the one that comes first is chosen.
1493 These choices can be altered with the @samp{?} and @samp{!} characters:
1496 @cindex @samp{?} in constraint
1497 @cindex question mark
1499 Disparage slightly the alternative that the @samp{?} appears in,
1500 as a choice when no alternative applies exactly. The compiler regards
1501 this alternative as one unit more costly for each @samp{?} that appears
1504 @cindex @samp{!} in constraint
1505 @cindex exclamation point
1507 Disparage severely the alternative that the @samp{!} appears in.
1508 This alternative can still be used if it fits without reloading,
1509 but if reloading is needed, some other alternative will be used.
1511 @cindex @samp{^} in constraint
1514 This constraint is analogous to @samp{?} but it disparages slightly
1515 the alternative only if the operand with the @samp{^} needs a reload.
1517 @cindex @samp{$} in constraint
1520 This constraint is analogous to @samp{!} but it disparages severely
1521 the alternative only if the operand with the @samp{$} needs a reload.
1524 When an insn pattern has multiple alternatives in its constraints, often
1525 the appearance of the assembler code is determined mostly by which
1526 alternative was matched. When this is so, the C code for writing the
1527 assembler code can use the variable @code{which_alternative}, which is
1528 the ordinal number of the alternative that was actually satisfied (0 for
1529 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1533 So the first alternative for the 68000's logical-or could be written as
1534 @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r"
1535 (output): "irm" (input)}. However, the fact that two memory locations
1536 cannot be used in a single instruction prevents simply using @code{"+rm"
1537 (output) : "irm" (input)}. Using multi-alternatives, this might be
1538 written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes
1539 all the available alternatives to the compiler, allowing it to choose
1540 the most efficient one for the current conditions.
1542 There is no way within the template to determine which alternative was
1543 chosen. However you may be able to wrap your @code{asm} statements with
1544 builtins such as @code{__builtin_constant_p} to achieve the desired results.
1548 @node Class Preferences
1549 @subsection Register Class Preferences
1550 @cindex class preference constraints
1551 @cindex register class preference constraints
1553 @cindex voting between constraint alternatives
1554 The operand constraints have another function: they enable the compiler
1555 to decide which kind of hardware register a pseudo register is best
1556 allocated to. The compiler examines the constraints that apply to the
1557 insns that use the pseudo register, looking for the machine-dependent
1558 letters such as @samp{d} and @samp{a} that specify classes of registers.
1559 The pseudo register is put in whichever class gets the most ``votes''.
1560 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1561 favor of a general register. The machine description says which registers
1562 are considered general.
1564 Of course, on some machines all registers are equivalent, and no register
1565 classes are defined. Then none of this complexity is relevant.
1569 @subsection Constraint Modifier Characters
1570 @cindex modifiers in constraints
1571 @cindex constraint modifier characters
1573 @c prevent bad page break with this line
1574 Here are constraint modifier characters.
1577 @cindex @samp{=} in constraint
1579 Means that this operand is written to by this instruction:
1580 the previous value is discarded and replaced by new data.
1582 @cindex @samp{+} in constraint
1584 Means that this operand is both read and written by the instruction.
1586 When the compiler fixes up the operands to satisfy the constraints,
1587 it needs to know which operands are read by the instruction and
1588 which are written by it. @samp{=} identifies an operand which is only
1589 written; @samp{+} identifies an operand that is both read and written; all
1590 other operands are assumed to only be read.
1592 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1593 first character of the constraint string.
1595 @cindex @samp{&} in constraint
1596 @cindex earlyclobber operand
1598 Means (in a particular alternative) that this operand is an
1599 @dfn{earlyclobber} operand, which is written before the instruction is
1600 finished using the input operands. Therefore, this operand may not lie
1601 in a register that is read by the instruction or as part of any memory
1604 @samp{&} applies only to the alternative in which it is written. In
1605 constraints with multiple alternatives, sometimes one alternative
1606 requires @samp{&} while others do not. See, for example, the
1607 @samp{movdf} insn of the 68000.
1609 A operand which is read by the instruction can be tied to an earlyclobber
1610 operand if its only use as an input occurs before the early result is
1611 written. Adding alternatives of this form often allows GCC to produce
1612 better code when only some of the read operands can be affected by the
1613 earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@.
1615 Furthermore, if the @dfn{earlyclobber} operand is also a read/write
1616 operand, then that operand is written only after it's used.
1618 @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As
1619 @dfn{earlyclobber} operands are always written, a read-only
1620 @dfn{earlyclobber} operand is ill-formed and will be rejected by the
1623 @cindex @samp{%} in constraint
1625 Declares the instruction to be commutative for this operand and the
1626 following operand. This means that the compiler may interchange the
1627 two operands if that is the cheapest way to make all operands fit the
1628 constraints. @samp{%} applies to all alternatives and must appear as
1629 the first character in the constraint. Only read-only operands can use
1633 This is often used in patterns for addition instructions
1634 that really have only two operands: the result must go in one of the
1635 arguments. Here for example, is how the 68000 halfword-add
1636 instruction is defined:
1639 (define_insn "addhi3"
1640 [(set (match_operand:HI 0 "general_operand" "=m,r")
1641 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1642 (match_operand:HI 2 "general_operand" "di,g")))]
1646 GCC can only handle one commutative pair in an asm; if you use more,
1647 the compiler may fail. Note that you need not use the modifier if
1648 the two alternatives are strictly identical; this would only waste
1649 time in the reload pass.
1651 The modifier is not operational after
1652 register allocation, so the result of @code{define_peephole2}
1653 and @code{define_split}s performed after reload cannot rely on
1654 @samp{%} to make the intended insn match.
1656 @cindex @samp{#} in constraint
1658 Says that all following characters, up to the next comma, are to be
1659 ignored as a constraint. They are significant only for choosing
1660 register preferences.
1662 @cindex @samp{*} in constraint
1664 Says that the following character should be ignored when choosing
1665 register preferences. @samp{*} has no effect on the meaning of the
1666 constraint as a constraint, and no effect on reloading. For LRA
1667 @samp{*} additionally disparages slightly the alternative if the
1668 following character matches the operand.
1670 Here is an example: the 68000 has an instruction to sign-extend a
1671 halfword in a data register, and can also sign-extend a value by
1672 copying it into an address register. While either kind of register is
1673 acceptable, the constraints on an address-register destination are
1674 less strict, so it is best if register allocation makes an address
1675 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1676 constraint letter (for data register) is ignored when computing
1677 register preferences.
1680 (define_insn "extendhisi2"
1681 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1683 (match_operand:HI 1 "general_operand" "0,g")))]
1689 @node Machine Constraints
1690 @subsection Constraints for Particular Machines
1691 @cindex machine specific constraints
1692 @cindex constraints, machine specific
1694 Whenever possible, you should use the general-purpose constraint letters
1695 in @code{asm} arguments, since they will convey meaning more readily to
1696 people reading your code. Failing that, use the constraint letters
1697 that usually have very similar meanings across architectures. The most
1698 commonly used constraints are @samp{m} and @samp{r} (for memory and
1699 general-purpose registers respectively; @pxref{Simple Constraints}), and
1700 @samp{I}, usually the letter indicating the most common
1701 immediate-constant format.
1703 Each architecture defines additional constraints. These constraints
1704 are used by the compiler itself for instruction generation, as well as
1705 for @code{asm} statements; therefore, some of the constraints are not
1706 particularly useful for @code{asm}. Here is a summary of some of the
1707 machine-dependent constraints available on some particular machines;
1708 it includes both constraints that are useful for @code{asm} and
1709 constraints that aren't. The compiler source file mentioned in the
1710 table heading for each architecture is the definitive reference for
1711 the meanings of that architecture's constraints.
1713 @c Please keep this table alphabetized by target!
1715 @item AArch64 family---@file{config/aarch64/constraints.md}
1718 The stack pointer register (@code{SP})
1721 Floating point or SIMD vector register
1724 Integer constant that is valid as an immediate operand in an @code{ADD}
1728 Integer constant that is valid as an immediate operand in a @code{SUB}
1729 instruction (once negated)
1732 Integer constant that can be used with a 32-bit logical instruction
1735 Integer constant that can be used with a 64-bit logical instruction
1738 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1739 pseudo instruction. The @code{MOV} may be assembled to one of several different
1740 machine instructions depending on the value
1743 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1747 An absolute symbolic address or a label reference
1750 Floating point constant zero
1753 Integer constant zero
1756 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1757 within 4GB of the instruction
1760 A memory address which uses a single base register with no offset
1763 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1769 @item ARC ---@file{config/arc/constraints.md}
1772 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1773 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1774 option is in effect.
1777 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1778 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1779 This constraint can only match when the @option{-mq}
1780 option is in effect.
1782 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1785 A signed 12-bit integer constant.
1788 constant for arithmetic/logical operations. This might be any constant
1789 that can be put into a long immediate by the assmbler or linker without
1790 involving a PIC relocation.
1793 A 3-bit unsigned integer constant.
1796 A 6-bit unsigned integer constant.
1799 One's complement of a 6-bit unsigned integer constant.
1802 Two's complement of a 6-bit unsigned integer constant.
1805 A 5-bit unsigned integer constant.
1808 A 7-bit unsigned integer constant.
1811 A 8-bit unsigned integer constant.
1814 Any const_double value.
1817 @item ARM family---@file{config/arm/constraints.md}
1821 In Thumb state, the core registers @code{r8}-@code{r15}.
1824 The stack pointer register.
1827 In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this
1828 is an alias for the @code{r} constraint.
1831 VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values.
1834 VFP floating-point registers @code{d0}-@code{d31} and the appropriate
1835 subset @code{d0}-@code{d15} based on command line options.
1836 Used for 64 bit values only. Not valid for Thumb1.
1839 The iWMMX co-processor registers.
1842 The iWMMX GR registers.
1845 The floating-point constant 0.0
1848 Integer that is valid as an immediate operand in a data processing
1849 instruction. That is, an integer in the range 0 to 255 rotated by a
1853 Integer in the range @minus{}4095 to 4095
1856 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1859 Integer that satisfies constraint @samp{I} when negated (twos complement)
1862 Integer in the range 0 to 32
1865 A memory reference where the exact address is in a single register
1866 (`@samp{m}' is preferable for @code{asm} statements)
1869 An item in the constant pool
1872 A symbol in the text segment of the current file
1875 A memory reference suitable for VFP load/store insns (reg+constant offset)
1878 A memory reference suitable for iWMMXt load/store instructions.
1881 A memory reference suitable for the ARMv4 ldrsb instruction.
1884 @item AVR family---@file{config/avr/constraints.md}
1887 Registers from r0 to r15
1890 Registers from r16 to r23
1893 Registers from r16 to r31
1896 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1899 Pointer register (r26--r31)
1902 Base pointer register (r28--r31)
1905 Stack pointer register (SPH:SPL)
1908 Temporary register r0
1911 Register pair X (r27:r26)
1914 Register pair Y (r29:r28)
1917 Register pair Z (r31:r30)
1920 Constant greater than @minus{}1, less than 64
1923 Constant greater than @minus{}64, less than 1
1932 Constant that fits in 8 bits
1935 Constant integer @minus{}1
1938 Constant integer 8, 16, or 24
1944 A floating point constant 0.0
1947 A memory address based on Y or Z pointer with displacement.
1950 @item Blackfin family---@file{config/bfin/constraints.md}
1959 A call clobbered P register.
1962 A single register. If @var{n} is in the range 0 to 7, the corresponding D
1963 register. If it is @code{A}, then the register P0.
1966 Even-numbered D register
1969 Odd-numbered D register
1972 Accumulator register.
1975 Even-numbered accumulator register.
1978 Odd-numbered accumulator register.
1990 Registers used for circular buffering, i.e. I, B, or L registers.
2005 Any D, P, B, M, I or L register.
2008 Additional registers typically used only in prologues and epilogues: RETS,
2009 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2012 Any register except accumulators or CC.
2015 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2018 Unsigned 16 bit integer (in the range 0 to 65535)
2021 Signed 7 bit integer (in the range @minus{}64 to 63)
2024 Unsigned 7 bit integer (in the range 0 to 127)
2027 Unsigned 5 bit integer (in the range 0 to 31)
2030 Signed 4 bit integer (in the range @minus{}8 to 7)
2033 Signed 3 bit integer (in the range @minus{}3 to 4)
2036 Unsigned 3 bit integer (in the range 0 to 7)
2039 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2042 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2043 use with either accumulator.
2046 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2047 use only with accumulator A1.
2056 An integer constant with exactly a single bit set.
2059 An integer constant with all bits set except exactly one.
2067 @item CR16 Architecture---@file{config/cr16/cr16.h}
2071 Registers from r0 to r14 (registers without stack pointer)
2074 Register from r0 to r11 (all 16-bit registers)
2077 Register from r12 to r15 (all 32-bit registers)
2080 Signed constant that fits in 4 bits
2083 Signed constant that fits in 5 bits
2086 Signed constant that fits in 6 bits
2089 Unsigned constant that fits in 4 bits
2092 Signed constant that fits in 32 bits
2095 Check for 64 bits wide constants for add/sub instructions
2098 Floating point constant that is legal for store immediate
2101 @item Epiphany---@file{config/epiphany/constraints.md}
2104 An unsigned 16-bit constant.
2107 An unsigned 5-bit constant.
2110 A signed 11-bit constant.
2113 A signed 11-bit constant added to @minus{}1.
2114 Can only match when the @option{-m1reg-@var{reg}} option is active.
2117 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
2118 being a block of trailing zeroes.
2119 Can only match when the @option{-m1reg-@var{reg}} option is active.
2122 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
2123 rest being zeroes. Or to put it another way, one less than a power of two.
2124 Can only match when the @option{-m1reg-@var{reg}} option is active.
2127 Constant for arithmetic/logical operations.
2128 This is like @code{i}, except that for position independent code,
2129 no symbols / expressions needing relocations are allowed.
2132 Symbolic constant for call/jump instruction.
2135 The register class usable in short insns. This is a register class
2136 constraint, and can thus drive register allocation.
2137 This constraint won't match unless @option{-mprefer-short-insn-regs} is
2141 The the register class of registers that can be used to hold a
2142 sibcall call address. I.e., a caller-saved register.
2145 Core control register class.
2148 The register group usable in short insns.
2149 This constraint does not use a register class, so that it only
2150 passively matches suitable registers, and doesn't drive register allocation.
2154 Constant suitable for the addsi3_r pattern. This is a valid offset
2155 For byte, halfword, or word addressing.
2159 Matches the return address if it can be replaced with the link register.
2162 Matches the integer condition code register.
2165 Matches the return address if it is in a stack slot.
2168 Matches control register values to switch fp mode, which are encapsulated in
2169 @code{UNSPEC_FP_MODE}.
2172 @item FRV---@file{config/frv/frv.h}
2175 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2178 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2181 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2182 @code{icc0} to @code{icc3}).
2185 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2188 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2189 Odd registers are excluded not in the class but through the use of a machine
2190 mode larger than 4 bytes.
2193 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2196 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2197 Odd registers are excluded not in the class but through the use of a machine
2198 mode larger than 4 bytes.
2201 Register in the class @code{LR_REG} (the @code{lr} register).
2204 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2205 Register numbers not divisible by 4 are excluded not in the class but through
2206 the use of a machine mode larger than 8 bytes.
2209 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2212 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2215 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2218 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2221 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2222 Register numbers not divisible by 4 are excluded not in the class but through
2223 the use of a machine mode larger than 8 bytes.
2226 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2229 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2232 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2235 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2238 Floating point constant zero
2241 6-bit signed integer constant
2244 10-bit signed integer constant
2247 16-bit signed integer constant
2250 16-bit unsigned integer constant
2253 12-bit signed integer constant that is negative---i.e.@: in the
2254 range of @minus{}2048 to @minus{}1
2260 12-bit signed integer constant that is greater than zero---i.e.@: in the
2265 @item FT32---@file{config/ft32/constraints.md}
2274 A register indirect memory operand
2283 The constant zero or one
2286 A 16-bit signed constant (@minus{}32768 @dots{} 32767)
2289 A bitfield mask suitable for bext or bins
2292 An inverted bitfield mask suitable for bext or bins
2295 A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532)
2298 A 20-bit signed constant (@minus{}524288 @dots{} 524287)
2301 A constant for a bitfield width (1 @dots{} 16)
2304 A 10-bit signed constant (@minus{}512 @dots{} 511)
2308 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
2314 Floating point register
2317 Shift amount register
2320 Floating point register (deprecated)
2323 Upper floating point register (32-bit), floating point register (64-bit)
2329 Signed 11-bit integer constant
2332 Signed 14-bit integer constant
2335 Integer constant that can be deposited with a @code{zdepi} instruction
2338 Signed 5-bit integer constant
2344 Integer constant that can be loaded with a @code{ldil} instruction
2347 Integer constant whose value plus one is a power of 2
2350 Integer constant that can be used for @code{and} operations in @code{depi}
2351 and @code{extru} instructions
2360 Floating-point constant 0.0
2363 A @code{lo_sum} data-linkage-table memory operand
2366 A memory operand that can be used as the destination operand of an
2367 integer store instruction
2370 A scaled or unscaled indexed memory operand
2373 A memory operand for floating-point loads and stores
2376 A register indirect memory operand
2379 @item Intel IA-64---@file{config/ia64/ia64.h}
2382 General register @code{r0} to @code{r3} for @code{addl} instruction
2388 Predicate register (@samp{c} as in ``conditional'')
2391 Application register residing in M-unit
2394 Application register residing in I-unit
2397 Floating-point register
2400 Memory operand. If used together with @samp{<} or @samp{>},
2401 the operand can have postincrement and postdecrement which
2402 require printing with @samp{%Pn} on IA-64.
2405 Floating-point constant 0.0 or 1.0
2408 14-bit signed integer constant
2411 22-bit signed integer constant
2414 8-bit signed integer constant for logical instructions
2417 8-bit adjusted signed integer constant for compare pseudo-ops
2420 6-bit unsigned integer constant for shift counts
2423 9-bit signed integer constant for load and store postincrements
2429 0 or @minus{}1 for @code{dep} instruction
2432 Non-volatile memory for floating-point loads and stores
2435 Integer constant in the range 1 to 4 for @code{shladd} instruction
2438 Memory operand except postincrement and postdecrement. This is
2439 now roughly the same as @samp{m} when not used together with @samp{<}
2443 @item M32C---@file{config/m32c/m32c.c}
2448 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2451 Any control register, when they're 16 bits wide (nothing if control
2452 registers are 24 bits wide)
2455 Any control register, when they're 24 bits wide.
2464 $r0 or $r2, or $r2r0 for 32 bit values.
2467 $r1 or $r3, or $r3r1 for 32 bit values.
2470 A register that can hold a 64 bit value.
2473 $r0 or $r1 (registers with addressable high/low bytes)
2482 Address registers when they're 16 bits wide.
2485 Address registers when they're 24 bits wide.
2488 Registers that can hold QI values.
2491 Registers that can be used with displacements ($a0, $a1, $sb).
2494 Registers that can hold 32 bit values.
2497 Registers that can hold 16 bit values.
2500 Registers chat can hold 16 bit values, including all control
2504 $r0 through R1, plus $a0 and $a1.
2510 The memory-based pseudo-registers $mem0 through $mem15.
2513 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2514 bit registers for m32cm, m32c).
2517 Matches multiple registers in a PARALLEL to form a larger register.
2518 Used to match function return values.
2524 @minus{}128 @dots{} 127
2527 @minus{}32768 @dots{} 32767
2533 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2536 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2539 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2542 @minus{}65536 @dots{} @minus{}1
2545 An 8 bit value with exactly one bit set.
2548 A 16 bit value with exactly one bit set.
2551 The common src/dest memory addressing modes.
2554 Memory addressed using $a0 or $a1.
2557 Memory addressed with immediate addresses.
2560 Memory addressed using the stack pointer ($sp).
2563 Memory addressed using the frame base register ($fb).
2566 Memory addressed using the small base register ($sb).
2572 @item MeP---@file{config/mep/constraints.md}
2582 Any control register.
2585 Either the $hi or the $lo register.
2588 Coprocessor registers that can be directly loaded ($c0-$c15).
2591 Coprocessor registers that can be moved to each other.
2594 Coprocessor registers that can be moved to core registers.
2606 Registers which can be used in $tp-relative addressing.
2612 The coprocessor registers.
2615 The coprocessor control registers.
2621 User-defined register set A.
2624 User-defined register set B.
2627 User-defined register set C.
2630 User-defined register set D.
2633 Offsets for $gp-rel addressing.
2636 Constants that can be used directly with boolean insns.
2639 Constants that can be moved directly to registers.
2642 Small constants that can be added to registers.
2648 Small constants that can be compared to registers.
2651 Constants that can be loaded into the top half of registers.
2654 Signed 8-bit immediates.
2657 Symbols encoded for $tp-rel or $gp-rel addressing.
2660 Non-constant addresses for loading/saving coprocessor registers.
2663 The top half of a symbol's value.
2666 A register indirect address without offset.
2669 Symbolic references to the control bus.
2673 @item MicroBlaze---@file{config/microblaze/constraints.md}
2676 A general register (@code{r0} to @code{r31}).
2679 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2683 @item MIPS---@file{config/mips/constraints.md}
2686 An address register. This is equivalent to @code{r} unless
2687 generating MIPS16 code.
2690 A floating-point register (if available).
2693 Formerly the @code{hi} register. This constraint is no longer supported.
2696 The @code{lo} register. Use this register to store values that are
2697 no bigger than a word.
2700 The concatenated @code{hi} and @code{lo} registers. Use this register
2701 to store doubleword values.
2704 A register suitable for use in an indirect jump. This will always be
2705 @code{$25} for @option{-mabicalls}.
2708 Register @code{$3}. Do not use this constraint in new code;
2709 it is retained only for compatibility with glibc.
2712 Equivalent to @code{r}; retained for backwards compatibility.
2715 A floating-point condition code register.
2718 A signed 16-bit constant (for arithmetic instructions).
2724 An unsigned 16-bit constant (for logic instructions).
2727 A signed 32-bit constant in which the lower 16 bits are zero.
2728 Such constants can be loaded using @code{lui}.
2731 A constant that cannot be loaded using @code{lui}, @code{addiu}
2735 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2738 A signed 15-bit constant.
2741 A constant in the range 1 to 65535 (inclusive).
2744 Floating-point zero.
2747 An address that can be used in a non-macro load or store.
2750 A memory operand whose address is formed by a base register and offset
2751 that is suitable for use in instructions with the same addressing mode
2752 as @code{ll} and @code{sc}.
2755 An address suitable for a @code{prefetch} instruction, or for any other
2756 instruction with the same addressing mode as @code{prefetch}.
2759 @item Motorola 680x0---@file{config/m68k/constraints.md}
2768 68881 floating-point register, if available
2771 Integer in the range 1 to 8
2774 16-bit signed number
2777 Signed number whose magnitude is greater than 0x80
2780 Integer in the range @minus{}8 to @minus{}1
2783 Signed number whose magnitude is greater than 0x100
2786 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2789 16 (for rotate using swap)
2792 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2795 Numbers that mov3q can handle
2798 Floating point constant that is not a 68881 constant
2801 Operands that satisfy 'm' when -mpcrel is in effect
2804 Operands that satisfy 's' when -mpcrel is not in effect
2807 Address register indirect addressing mode
2810 Register offset addressing
2825 Range of signed numbers that don't fit in 16 bits
2828 Integers valid for mvq
2831 Integers valid for a moveq followed by a swap
2834 Integers valid for mvz
2837 Integers valid for mvs
2843 Non-register operands allowed in clr
2847 @item Moxie---@file{config/moxie/constraints.md}
2856 A register indirect memory operand
2859 A constant in the range of 0 to 255.
2862 A constant in the range of 0 to @minus{}255.
2866 @item MSP430--@file{config/msp430/constraints.md}
2879 Integer constant -1^20..1^19.
2882 Integer constant 1-4.
2885 Memory references which do not require an extended MOVX instruction.
2888 Memory reference, labels only.
2891 Memory reference, stack only.
2895 @item NDS32---@file{config/nds32/constraints.md}
2898 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
2900 LOW register class $r0 to $r7.
2902 MIDDLE register class $r0 to $r11, $r16 to $r19.
2904 HIGH register class $r12 to $r14, $r20 to $r31.
2906 Temporary assist register $ta (i.e.@: $r15).
2910 Unsigned immediate 3-bit value.
2912 Negative immediate 3-bit value in the range of @minus{}7--0.
2914 Unsigned immediate 4-bit value.
2916 Signed immediate 5-bit value.
2918 Unsigned immediate 5-bit value.
2920 Negative immediate 5-bit value in the range of @minus{}31--0.
2922 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
2924 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
2926 Unsigned immediate 8-bit value.
2928 Unsigned immediate 9-bit value.
2930 Signed immediate 10-bit value.
2932 Signed immediate 11-bit value.
2934 Signed immediate 15-bit value.
2936 Unsigned immediate 15-bit value.
2938 A constant which is not in the range of imm15u but ok for bclr instruction.
2940 A constant which is not in the range of imm15u but ok for bset instruction.
2942 A constant which is not in the range of imm15u but ok for btgl instruction.
2944 A constant whose compliment value is in the range of imm15u
2945 and ok for bitci instruction.
2947 Signed immediate 16-bit value.
2949 Signed immediate 17-bit value.
2951 Signed immediate 19-bit value.
2953 Signed immediate 20-bit value.
2955 The immediate value that can be simply set high 20-bit.
2957 The immediate value 0xff.
2959 The immediate value 0xffff.
2961 The immediate value 0x01.
2963 The immediate value 0x7ff.
2965 The immediate value with power of 2.
2967 The immediate value with power of 2 minus 1.
2969 Memory constraint for 333 format.
2971 Memory constraint for 45 format.
2973 Memory constraint for 37 format.
2976 @item Nios II family---@file{config/nios2/constraints.md}
2980 Integer that is valid as an immediate operand in an
2981 instruction taking a signed 16-bit number. Range
2982 @minus{}32768 to 32767.
2985 Integer that is valid as an immediate operand in an
2986 instruction taking an unsigned 16-bit number. Range
2990 Integer that is valid as an immediate operand in an
2991 instruction taking only the upper 16-bits of a
2992 32-bit number. Range 32-bit numbers with the lower
2996 Integer that is valid as an immediate operand for a
2997 shift instruction. Range 0 to 31.
3000 Integer that is valid as an immediate operand for
3001 only the value 0. Can be used in conjunction with
3002 the format modifier @code{z} to use @code{r0}
3003 instead of @code{0} in the assembly output.
3006 Integer that is valid as an immediate operand for
3007 a custom instruction opcode. Range 0 to 255.
3010 An immediate operand for R2 andchi/andci instructions.
3013 Matches immediates which are addresses in the small
3014 data section and therefore can be added to @code{gp}
3015 as a 16-bit immediate to re-create their 32-bit value.
3018 Matches constants suitable as an operand for the rdprs and
3022 A memory operand suitable for Nios II R2 load/store
3023 exclusive instructions.
3026 A memory operand suitable for load/store IO and cache
3031 A @code{const} wrapped @code{UNSPEC} expression,
3032 representing a supported PIC or TLS relocation.
3037 @item PDP-11---@file{config/pdp11/constraints.md}
3040 Floating point registers AC0 through AC3. These can be loaded from/to
3041 memory with a single instruction.
3044 Odd numbered general registers (R1, R3, R5). These are used for
3045 16-bit multiply operations.
3048 Any of the floating point registers (AC0 through AC5).
3051 Floating point constant 0.
3054 An integer constant that fits in 16 bits.
3057 An integer constant whose low order 16 bits are zero.
3060 An integer constant that does not meet the constraints for codes
3061 @samp{I} or @samp{J}.
3064 The integer constant 1.
3067 The integer constant @minus{}1.
3070 The integer constant 0.
3073 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3074 amounts are handled as multiple single-bit shifts rather than a single
3075 variable-length shift.
3078 A memory reference which requires an additional word (address or
3079 offset) after the opcode.
3082 A memory reference that is encoded within the opcode.
3086 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
3089 Address base register
3092 Floating point register (containing 64-bit value)
3095 Floating point register (containing 32-bit value)
3098 Altivec vector register
3101 Any VSX register if the -mvsx option was used or NO_REGS.
3103 When using any of the register constraints (@code{wa}, @code{wd},
3104 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
3105 @code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
3106 @code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
3107 that take VSX registers, you must use @code{%x<n>} in the template so
3108 that the correct register is used. Otherwise the register number
3109 output in the assembly file will be incorrect if an Altivec register
3110 is an operand of a VSX instruction that expects VSX register
3114 asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
3120 asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
3125 If an instruction only takes Altivec registers, you do not want to use
3129 asm ("xsaddqp %0,%1,%2" : "=v" (v1) : "v" (v2), "v" (v3));
3132 is correct because the @code{xsaddqp} instruction only takes Altivec
3136 asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2), "v" (v3));
3142 Altivec register if @option{-mpower9-dform} is used or NO_REGS.
3145 VSX vector register to hold vector double data or NO_REGS.
3148 VSX register if the @option{-mpower9-vector} and @option{-m64} options
3149 were used or NO_REGS.
3152 VSX vector register to hold vector float data or NO_REGS.
3155 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
3158 Floating point register if direct moves are available, or NO_REGS.
3161 FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
3164 FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
3167 FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
3170 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
3173 VSX register if direct move instructions are enabled, or NO_REGS.
3176 No register (NO_REGS).
3179 VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
3182 VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
3185 VSX register to use for IEEE 128-bit floating point, or NO_REGS.
3188 General purpose register if 64-bit instructions are enabled or NO_REGS.
3191 VSX vector register to hold scalar double values or NO_REGS.
3194 VSX vector register to hold 128 bit integer or NO_REGS.
3197 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
3200 Altivec register to use for double loads/stores or NO_REGS.
3203 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
3206 Floating point register if the STFIWX instruction is enabled or NO_REGS.
3209 FP or VSX register to perform ISA 2.07 float ops or NO_REGS.
3212 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
3215 Int constant that is the element number of the 64-bit scalar in a vector.
3218 Memory operand suitable for power9 fusion load/stores.
3221 Memory operand suitable for TOC fusion memory references.
3224 Int constant that is the element number that the MFVSRLD instruction
3228 A memory address that will work with the @code{lq} and @code{stq}
3232 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
3238 @samp{LINK} register
3241 @samp{CR} register (condition register) number 0
3244 @samp{CR} register (condition register)
3247 @samp{XER[CA]} carry bit (part of the XER register)
3250 Signed 16-bit constant
3253 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
3254 @code{SImode} constants)
3257 Unsigned 16-bit constant
3260 Signed 16-bit constant shifted left 16 bits
3263 Constant larger than 31
3272 Constant whose negation is a signed 16-bit constant
3275 Floating point constant that can be loaded into a register with one
3276 instruction per word
3279 Integer/Floating point constant that can be loaded into a register using
3284 Normally, @code{m} does not allow addresses that update the base register.
3285 If @samp{<} or @samp{>} constraint is also used, they are allowed and
3286 therefore on PowerPC targets in that case it is only safe
3287 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
3288 accesses the operand exactly once. The @code{asm} statement must also
3289 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
3290 corresponding load or store instruction. For example:
3293 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
3299 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
3305 A ``stable'' memory operand; that is, one which does not include any
3306 automodification of the base register. This used to be useful when
3307 @samp{m} allowed automodification of the base register, but as those are now only
3308 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
3309 as @samp{m} without @samp{<} and @samp{>}.
3312 Memory operand that is an offset from a register (it is usually better
3313 to use @samp{m} or @samp{es} in @code{asm} statements)
3316 Memory operand that is an indexed or indirect from a register (it is
3317 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
3323 Address operand that is an indexed or indirect from a register (@samp{p} is
3324 preferable for @code{asm} statements)
3327 System V Release 4 small data area reference
3330 Vector constant that does not require memory
3333 Vector constant that is all zeros.
3337 @item RL78---@file{config/rl78/constraints.md}
3341 An integer constant in the range 1 @dots{} 7.
3343 An integer constant in the range 0 @dots{} 255.
3345 An integer constant in the range @minus{}255 @dots{} 0
3347 The integer constant 1.
3349 The integer constant -1.
3351 The integer constant 0.
3353 The integer constant 2.
3355 The integer constant -2.
3357 An integer constant in the range 1 @dots{} 15.
3359 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3361 The synthetic compare types--gt, lt, ge, and le.
3363 A memory reference with an absolute address.
3365 A memory reference using @code{BC} as a base register, with an optional offset.
3367 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3369 A memory reference using any 16-bit register pair for the address, for calls.
3371 A memory reference using @code{DE} as a base register, with an optional offset.
3373 A memory reference using @code{DE} as a base register, without any offset.
3375 Any memory reference to an address in the far address space.
3377 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3379 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3381 A memory reference using @code{HL} as a base register, without any offset.
3383 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3385 Any memory reference to an address in the near address space.
3387 The @code{AX} register.
3389 The @code{BC} register.
3391 The @code{DE} register.
3393 @code{A} through @code{L} registers.
3395 The @code{SP} register.
3397 The @code{HL} register.
3399 The 16-bit @code{R8} register.
3401 The 16-bit @code{R10} register.
3403 The registers reserved for interrupts (@code{R24} to @code{R31}).
3405 The @code{A} register.
3407 The @code{B} register.
3409 The @code{C} register.
3411 The @code{D} register.
3413 The @code{E} register.
3415 The @code{H} register.
3417 The @code{L} register.
3419 The virtual registers.
3421 The @code{PSW} register.
3423 The @code{X} register.
3427 @item RX---@file{config/rx/constraints.md}
3430 An address which does not involve register indirect addressing or
3431 pre/post increment/decrement addressing.
3437 A constant in the range @minus{}256 to 255, inclusive.
3440 A constant in the range @minus{}128 to 127, inclusive.
3443 A constant in the range @minus{}32768 to 32767, inclusive.
3446 A constant in the range @minus{}8388608 to 8388607, inclusive.
3449 A constant in the range 0 to 15, inclusive.
3453 @item S/390 and zSeries---@file{config/s390/s390.h}
3456 Address register (general purpose register except r0)
3459 Condition code register
3462 Data register (arbitrary general purpose register)
3465 Floating-point register
3468 Unsigned 8-bit constant (0--255)
3471 Unsigned 12-bit constant (0--4095)
3474 Signed 16-bit constant (@minus{}32768--32767)
3477 Value appropriate as displacement.
3480 for short displacement
3481 @item (@minus{}524288..524287)
3482 for long displacement
3486 Constant integer with a value of 0x7fffffff.
3489 Multiple letter constraint followed by 4 parameter letters.
3492 number of the part counting from most to least significant
3496 mode of the containing operand
3498 value of the other parts (F---all bits set)
3500 The constraint matches if the specified part of a constant
3501 has a value different from its other parts.
3504 Memory reference without index register and with short displacement.
3507 Memory reference with index register and short displacement.
3510 Memory reference without index register but with long displacement.
3513 Memory reference with index register and long displacement.
3516 Pointer with short displacement.
3519 Pointer with long displacement.
3522 Shift count operand.
3527 @item SPARC---@file{config/sparc/sparc.h}
3530 Floating-point register on the SPARC-V8 architecture and
3531 lower floating-point register on the SPARC-V9 architecture.
3534 Floating-point register. It is equivalent to @samp{f} on the
3535 SPARC-V8 architecture and contains both lower and upper
3536 floating-point registers on the SPARC-V9 architecture.
3539 Floating-point condition code register.
3542 Lower floating-point register. It is only valid on the SPARC-V9
3543 architecture when the Visual Instruction Set is available.
3546 Floating-point register. It is only valid on the SPARC-V9 architecture
3547 when the Visual Instruction Set is available.
3550 64-bit global or out register for the SPARC-V8+ architecture.
3553 The constant all-ones, for floating-point.
3556 Signed 5-bit constant
3562 Signed 13-bit constant
3568 32-bit constant with the low 12 bits clear (a constant that can be
3569 loaded with the @code{sethi} instruction)
3572 A constant in the range supported by @code{movcc} instructions (11-bit
3576 A constant in the range supported by @code{movrcc} instructions (10-bit
3580 Same as @samp{K}, except that it verifies that bits that are not in the
3581 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3582 modes wider than @code{SImode}
3591 Signed 13-bit constant, sign-extended to 32 or 64 bits
3597 Floating-point constant whose integral representation can
3598 be moved into an integer register using a single sethi
3602 Floating-point constant whose integral representation can
3603 be moved into an integer register using a single mov
3607 Floating-point constant whose integral representation can
3608 be moved into an integer register using a high/lo_sum
3609 instruction sequence
3612 Memory address aligned to an 8-byte boundary
3618 Memory address for @samp{e} constraint registers
3621 Memory address with only a base register
3628 @item SPU---@file{config/spu/spu.h}
3631 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3634 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3637 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3640 An immediate which can be loaded with @code{fsmbi}.
3643 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3646 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3649 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3652 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3655 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3658 An unsigned 7-bit constant for conversion/nop/channel instructions.
3661 A signed 10-bit constant for most arithmetic instructions.
3664 A signed 16 bit immediate for @code{stop}.
3667 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3670 An unsigned 7-bit constant whose 3 least significant bits are 0.
3673 An unsigned 3-bit constant for 16-byte rotates and shifts
3676 Call operand, reg, for indirect calls
3679 Call operand, symbol, for relative calls.
3682 Call operand, const_int, for absolute calls.
3685 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3688 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3691 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3694 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3698 @item TI C6X family---@file{config/c6x/constraints.md}
3701 Register file A (A0--A31).
3704 Register file B (B0--B31).
3707 Predicate registers in register file A (A0--A2 on C64X and
3708 higher, A1 and A2 otherwise).
3711 Predicate registers in register file B (B0--B2).
3714 A call-used register in register file B (B0--B9, B16--B31).
3717 Register file A, excluding predicate registers (A3--A31,
3718 plus A0 if not C64X or higher).
3721 Register file B, excluding predicate registers (B3--B31).
3724 Integer constant in the range 0 @dots{} 15.
3727 Integer constant in the range 0 @dots{} 31.
3730 Integer constant in the range @minus{}31 @dots{} 0.
3733 Integer constant in the range @minus{}16 @dots{} 15.
3736 Integer constant that can be the operand of an ADDA or a SUBA insn.
3739 Integer constant in the range 0 @dots{} 65535.
3742 Integer constant in the range @minus{}32768 @dots{} 32767.
3745 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3748 Integer constant that is a valid mask for the clr instruction.
3751 Integer constant that is a valid mask for the set instruction.
3754 Memory location with A base register.
3757 Memory location with B base register.
3761 On C64x+ targets, a GP-relative small data reference.
3764 Any kind of @code{SYMBOL_REF}, for use in a call address.
3767 Any kind of immediate operand, unless it matches the S0 constraint.
3770 Memory location with B base register, but not using a long offset.
3773 A memory operand with an address that can't be used in an unaligned access.
3777 Register B14 (aka DP).
3781 @item TILE-Gx---@file{config/tilegx/constraints.md}
3794 Each of these represents a register constraint for an individual
3795 register, from r0 to r10.
3798 Signed 8-bit integer constant.
3801 Signed 16-bit integer constant.
3804 Unsigned 16-bit integer constant.
3807 Integer constant that fits in one signed byte when incremented by one
3808 (@minus{}129 @dots{} 126).
3811 Memory operand. If used together with @samp{<} or @samp{>}, the
3812 operand can have postincrement which requires printing with @samp{%In}
3813 and @samp{%in} on TILE-Gx. For example:
3816 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3820 A bit mask suitable for the BFINS instruction.
3823 Integer constant that is a byte tiled out eight times.
3826 The integer zero constant.
3829 Integer constant that is a sign-extended byte tiled out as four shorts.
3832 Integer constant that fits in one signed byte when incremented
3833 (@minus{}129 @dots{} 126), but excluding -1.
3836 Integer constant that has all 1 bits consecutive and starting at bit 0.
3839 A 16-bit fragment of a got, tls, or pc-relative reference.
3842 Memory operand except postincrement. This is roughly the same as
3843 @samp{m} when not used together with @samp{<} or @samp{>}.
3846 An 8-element vector constant with identical elements.
3849 A 4-element vector constant with identical elements.
3852 The integer constant 0xffffffff.
3855 The integer constant 0xffffffff00000000.
3859 @item TILEPro---@file{config/tilepro/constraints.md}
3872 Each of these represents a register constraint for an individual
3873 register, from r0 to r10.
3876 Signed 8-bit integer constant.
3879 Signed 16-bit integer constant.
3882 Nonzero integer constant with low 16 bits zero.
3885 Integer constant that fits in one signed byte when incremented by one
3886 (@minus{}129 @dots{} 126).
3889 Memory operand. If used together with @samp{<} or @samp{>}, the
3890 operand can have postincrement which requires printing with @samp{%In}
3891 and @samp{%in} on TILEPro. For example:
3894 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3898 A bit mask suitable for the MM instruction.
3901 Integer constant that is a byte tiled out four times.
3904 The integer zero constant.
3907 Integer constant that is a sign-extended byte tiled out as two shorts.
3910 Integer constant that fits in one signed byte when incremented
3911 (@minus{}129 @dots{} 126), but excluding -1.
3914 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3918 Memory operand except postincrement. This is roughly the same as
3919 @samp{m} when not used together with @samp{<} or @samp{>}.
3922 A 4-element vector constant with identical elements.
3925 A 2-element vector constant with identical elements.
3929 @item Visium---@file{config/visium/constraints.md}
3932 EAM register @code{mdb}
3935 EAM register @code{mdc}
3938 Floating point register
3942 Register for sibcall optimization
3946 General register, but not @code{r29}, @code{r30} and @code{r31}
3958 Floating-point constant 0.0
3961 Integer constant in the range 0 .. 65535 (16-bit immediate)
3964 Integer constant in the range 1 .. 31 (5-bit immediate)
3967 Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate)
3970 Integer constant @minus{}1
3979 @item x86 family---@file{config/i386/constraints.md}
3982 Legacy register---the eight integer registers available on all
3983 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
3984 @code{si}, @code{di}, @code{bp}, @code{sp}).
3987 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
3988 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
3991 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
3992 @code{c}, and @code{d}.
3996 Any register that can be used as the index in a base+index memory
3997 access: that is, any general register except the stack pointer.
4001 The @code{a} register.
4004 The @code{b} register.
4007 The @code{c} register.
4010 The @code{d} register.
4013 The @code{si} register.
4016 The @code{di} register.
4019 The @code{a} and @code{d} registers. This class is used for instructions
4020 that return double word results in the @code{ax:dx} register pair. Single
4021 word values will be allocated either in @code{ax} or @code{dx}.
4022 For example on i386 the following implements @code{rdtsc}:
4025 unsigned long long rdtsc (void)
4027 unsigned long long tick;
4028 __asm__ __volatile__("rdtsc":"=A"(tick));
4033 This is not correct on x86-64 as it would allocate tick in either @code{ax}
4034 or @code{dx}. You have to use the following variant instead:
4037 unsigned long long rdtsc (void)
4039 unsigned int tickl, tickh;
4040 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
4041 return ((unsigned long long)tickh << 32)|tickl;
4047 Any 80387 floating-point (stack) register.
4050 Top of 80387 floating-point stack (@code{%st(0)}).
4053 Second from top of 80387 floating-point stack (@code{%st(1)}).
4062 First SSE register (@code{%xmm0}).
4066 Any SSE register, when SSE2 is enabled.
4069 Any SSE register, when SSE2 and inter-unit moves are enabled.
4072 Any MMX register, when inter-unit moves are enabled.
4076 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
4079 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
4082 Signed 8-bit integer constant.
4085 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
4088 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
4091 Unsigned 8-bit integer constant (for @code{in} and @code{out}
4096 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
4100 Standard 80387 floating point constant.
4103 SSE constant zero operand.
4106 32-bit signed integer constant, or a symbolic reference known
4107 to fit that range (for immediate operands in sign-extending x86-64
4111 32-bit unsigned integer constant, or a symbolic reference known
4112 to fit that range (for immediate operands in zero-extending x86-64
4117 @item Xstormy16---@file{config/stormy16/stormy16.h}
4132 Registers r0 through r7.
4135 Registers r0 and r1.
4141 Registers r8 and r9.
4144 A constant between 0 and 3 inclusive.
4147 A constant that has exactly one bit set.
4150 A constant that has exactly one bit clear.
4153 A constant between 0 and 255 inclusive.
4156 A constant between @minus{}255 and 0 inclusive.
4159 A constant between @minus{}3 and 0 inclusive.
4162 A constant between 1 and 4 inclusive.
4165 A constant between @minus{}4 and @minus{}1 inclusive.
4168 A memory reference that is a stack push.
4171 A memory reference that is a stack pop.
4174 A memory reference that refers to a constant address of known value.
4177 The register indicated by Rx (not implemented yet).
4180 A constant that is not between 2 and 15 inclusive.
4187 @item Xtensa---@file{config/xtensa/constraints.md}
4190 General-purpose 32-bit register
4193 One-bit boolean register
4196 MAC16 40-bit accumulator register
4199 Signed 12-bit integer constant, for use in MOVI instructions
4202 Signed 8-bit integer constant, for use in ADDI instructions
4205 Integer constant valid for BccI instructions
4208 Unsigned constant valid for BccUI instructions
4215 @node Disable Insn Alternatives
4216 @subsection Disable insn alternatives using the @code{enabled} attribute
4219 There are three insn attributes that may be used to selectively disable
4220 instruction alternatives:
4224 Says whether an alternative is available on the current subtarget.
4226 @item preferred_for_size
4227 Says whether an enabled alternative should be used in code that is
4230 @item preferred_for_speed
4231 Says whether an enabled alternative should be used in code that is
4232 optimized for speed.
4235 All these attributes should use @code{(const_int 1)} to allow an alternative
4236 or @code{(const_int 0)} to disallow it. The attributes must be a static
4237 property of the subtarget; they cannot for example depend on the
4238 current operands, on the current optimization level, on the location
4239 of the insn within the body of a loop, on whether register allocation
4240 has finished, or on the current compiler pass.
4242 The @code{enabled} attribute is a correctness property. It tells GCC to act
4243 as though the disabled alternatives were never defined in the first place.
4244 This is useful when adding new instructions to an existing pattern in
4245 cases where the new instructions are only available for certain cpu
4246 architecture levels (typically mapped to the @code{-march=} command-line
4249 In contrast, the @code{preferred_for_size} and @code{preferred_for_speed}
4250 attributes are strong optimization hints rather than correctness properties.
4251 @code{preferred_for_size} tells GCC which alternatives to consider when
4252 adding or modifying an instruction that GCC wants to optimize for size.
4253 @code{preferred_for_speed} does the same thing for speed. Note that things
4254 like code motion can lead to cases where code optimized for size uses
4255 alternatives that are not preferred for size, and similarly for speed.
4257 Although @code{define_insn}s can in principle specify the @code{enabled}
4258 attribute directly, it is often clearer to have subsiduary attributes
4259 for each architectural feature of interest. The @code{define_insn}s
4260 can then use these subsiduary attributes to say which alternatives
4261 require which features. The example below does this for @code{cpu_facility}.
4263 E.g. the following two patterns could easily be merged using the @code{enabled}
4268 (define_insn "*movdi_old"
4269 [(set (match_operand:DI 0 "register_operand" "=d")
4270 (match_operand:DI 1 "register_operand" " d"))]
4274 (define_insn "*movdi_new"
4275 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4276 (match_operand:DI 1 "register_operand" " d,d,f"))]
4289 (define_insn "*movdi_combined"
4290 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4291 (match_operand:DI 1 "register_operand" " d,d,f"))]
4297 [(set_attr "cpu_facility" "*,new,new")])
4301 with the @code{enabled} attribute defined like this:
4305 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4307 (define_attr "enabled" ""
4308 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4309 (and (eq_attr "cpu_facility" "new")
4310 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4319 @node Define Constraints
4320 @subsection Defining Machine-Specific Constraints
4321 @cindex defining constraints
4322 @cindex constraints, defining
4324 Machine-specific constraints fall into two categories: register and
4325 non-register constraints. Within the latter category, constraints
4326 which allow subsets of all possible memory or address operands should
4327 be specially marked, to give @code{reload} more information.
4329 Machine-specific constraints can be given names of arbitrary length,
4330 but they must be entirely composed of letters, digits, underscores
4331 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4332 must begin with a letter or underscore.
4334 In order to avoid ambiguity in operand constraint strings, no
4335 constraint can have a name that begins with any other constraint's
4336 name. For example, if @code{x} is defined as a constraint name,
4337 @code{xy} may not be, and vice versa. As a consequence of this rule,
4338 no constraint may begin with one of the generic constraint letters:
4339 @samp{E F V X g i m n o p r s}.
4341 Register constraints correspond directly to register classes.
4342 @xref{Register Classes}. There is thus not much flexibility in their
4345 @deffn {MD Expression} define_register_constraint name regclass docstring
4346 All three arguments are string constants.
4347 @var{name} is the name of the constraint, as it will appear in
4348 @code{match_operand} expressions. If @var{name} is a multi-letter
4349 constraint its length shall be the same for all constraints starting
4350 with the same letter. @var{regclass} can be either the
4351 name of the corresponding register class (@pxref{Register Classes}),
4352 or a C expression which evaluates to the appropriate register class.
4353 If it is an expression, it must have no side effects, and it cannot
4354 look at the operand. The usual use of expressions is to map some
4355 register constraints to @code{NO_REGS} when the register class
4356 is not available on a given subarchitecture.
4358 @var{docstring} is a sentence documenting the meaning of the
4359 constraint. Docstrings are explained further below.
4362 Non-register constraints are more like predicates: the constraint
4363 definition gives a Boolean expression which indicates whether the
4366 @deffn {MD Expression} define_constraint name docstring exp
4367 The @var{name} and @var{docstring} arguments are the same as for
4368 @code{define_register_constraint}, but note that the docstring comes
4369 immediately after the name for these expressions. @var{exp} is an RTL
4370 expression, obeying the same rules as the RTL expressions in predicate
4371 definitions. @xref{Defining Predicates}, for details. If it
4372 evaluates true, the constraint matches; if it evaluates false, it
4373 doesn't. Constraint expressions should indicate which RTL codes they
4374 might match, just like predicate expressions.
4376 @code{match_test} C expressions have access to the
4377 following variables:
4381 The RTL object defining the operand.
4383 The machine mode of @var{op}.
4385 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4387 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4388 @code{const_double}.
4390 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4391 @code{const_double}.
4393 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4394 @code{const_double}.
4397 The @var{*val} variables should only be used once another piece of the
4398 expression has verified that @var{op} is the appropriate kind of RTL
4402 Most non-register constraints should be defined with
4403 @code{define_constraint}. The remaining two definition expressions
4404 are only appropriate for constraints that should be handled specially
4405 by @code{reload} if they fail to match.
4407 @deffn {MD Expression} define_memory_constraint name docstring exp
4408 Use this expression for constraints that match a subset of all memory
4409 operands: that is, @code{reload} can make them match by converting the
4410 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4411 base register (from the register class specified by
4412 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4414 For example, on the S/390, some instructions do not accept arbitrary
4415 memory references, but only those that do not make use of an index
4416 register. The constraint letter @samp{Q} is defined to represent a
4417 memory address of this type. If @samp{Q} is defined with
4418 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4419 memory operand, because @code{reload} knows it can simply copy the
4420 memory address into a base register if required. This is analogous to
4421 the way an @samp{o} constraint can handle any memory operand.
4423 The syntax and semantics are otherwise identical to
4424 @code{define_constraint}.
4427 @deffn {MD Expression} define_special_memory_constraint name docstring exp
4428 Use this expression for constraints that match a subset of all memory
4429 operands: that is, @code{reload} can not make them match by reloading
4430 the address as it is described for @code{define_memory_constraint} or
4431 such address reload is undesirable with the performance point of view.
4433 For example, @code{define_special_memory_constraint} can be useful if
4434 specifically aligned memory is necessary or desirable for some insn
4437 The syntax and semantics are otherwise identical to
4438 @code{define_constraint}.
4441 @deffn {MD Expression} define_address_constraint name docstring exp
4442 Use this expression for constraints that match a subset of all address
4443 operands: that is, @code{reload} can make the constraint match by
4444 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4445 with @var{X} a base register.
4447 Constraints defined with @code{define_address_constraint} can only be
4448 used with the @code{address_operand} predicate, or machine-specific
4449 predicates that work the same way. They are treated analogously to
4450 the generic @samp{p} constraint.
4452 The syntax and semantics are otherwise identical to
4453 @code{define_constraint}.
4456 For historical reasons, names beginning with the letters @samp{G H}
4457 are reserved for constraints that match only @code{const_double}s, and
4458 names beginning with the letters @samp{I J K L M N O P} are reserved
4459 for constraints that match only @code{const_int}s. This may change in
4460 the future. For the time being, constraints with these names must be
4461 written in a stylized form, so that @code{genpreds} can tell you did
4466 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4468 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4469 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4472 @c the semicolons line up in the formatted manual
4474 It is fine to use names beginning with other letters for constraints
4475 that match @code{const_double}s or @code{const_int}s.
4477 Each docstring in a constraint definition should be one or more complete
4478 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4479 In the future they will be copied into the GCC manual, in @ref{Machine
4480 Constraints}, replacing the hand-maintained tables currently found in
4481 that section. Also, in the future the compiler may use this to give
4482 more helpful diagnostics when poor choice of @code{asm} constraints
4483 causes a reload failure.
4485 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4486 beginning of a docstring, then (in the future) it will appear only in
4487 the internals manual's version of the machine-specific constraint tables.
4488 Use this for constraints that should not appear in @code{asm} statements.
4490 @node C Constraint Interface
4491 @subsection Testing constraints from C
4492 @cindex testing constraints
4493 @cindex constraints, testing
4495 It is occasionally useful to test a constraint from C code rather than
4496 implicitly via the constraint string in a @code{match_operand}. The
4497 generated file @file{tm_p.h} declares a few interfaces for working
4498 with constraints. At present these are defined for all constraints
4499 except @code{g} (which is equivalent to @code{general_operand}).
4501 Some valid constraint names are not valid C identifiers, so there is a
4502 mangling scheme for referring to them from C@. Constraint names that
4503 do not contain angle brackets or underscores are left unchanged.
4504 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4505 each @samp{>} with @samp{_g}. Here are some examples:
4507 @c the @c's prevent double blank lines in the printed manual.
4509 @multitable {Original} {Mangled}
4510 @item @strong{Original} @tab @strong{Mangled} @c
4511 @item @code{x} @tab @code{x} @c
4512 @item @code{P42x} @tab @code{P42x} @c
4513 @item @code{P4_x} @tab @code{P4__x} @c
4514 @item @code{P4>x} @tab @code{P4_gx} @c
4515 @item @code{P4>>} @tab @code{P4_g_g} @c
4516 @item @code{P4_g>} @tab @code{P4__g_g} @c
4520 Throughout this section, the variable @var{c} is either a constraint
4521 in the abstract sense, or a constant from @code{enum constraint_num};
4522 the variable @var{m} is a mangled constraint name (usually as part of
4523 a larger identifier).
4525 @deftp Enum constraint_num
4526 For each constraint except @code{g}, there is a corresponding
4527 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4528 constraint. Functions that take an @code{enum constraint_num} as an
4529 argument expect one of these constants.
4532 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4533 For each non-register constraint @var{m} except @code{g}, there is
4534 one of these functions; it returns @code{true} if @var{exp} satisfies the
4535 constraint. These functions are only visible if @file{rtl.h} was included
4536 before @file{tm_p.h}.
4539 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4540 Like the @code{satisfies_constraint_@var{m}} functions, but the
4541 constraint to test is given as an argument, @var{c}. If @var{c}
4542 specifies a register constraint, this function will always return
4546 @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c})
4547 Returns the register class associated with @var{c}. If @var{c} is not
4548 a register constraint, or those registers are not available for the
4549 currently selected subtarget, returns @code{NO_REGS}.
4552 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4553 peephole optimizations (@pxref{Peephole Definitions}), operand
4554 constraint strings are ignored, so if there are relevant constraints,
4555 they must be tested in the C condition. In the example, the
4556 optimization is applied if operand 2 does @emph{not} satisfy the
4557 @samp{K} constraint. (This is a simplified version of a peephole
4558 definition from the i386 machine description.)
4562 [(match_scratch:SI 3 "r")
4563 (set (match_operand:SI 0 "register_operand" "")
4564 (mult:SI (match_operand:SI 1 "memory_operand" "")
4565 (match_operand:SI 2 "immediate_operand" "")))]
4567 "!satisfies_constraint_K (operands[2])"
4569 [(set (match_dup 3) (match_dup 1))
4570 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4575 @node Standard Names
4576 @section Standard Pattern Names For Generation
4577 @cindex standard pattern names
4578 @cindex pattern names
4579 @cindex names, pattern
4581 Here is a table of the instruction names that are meaningful in the RTL
4582 generation pass of the compiler. Giving one of these names to an
4583 instruction pattern tells the RTL generation pass that it can use the
4584 pattern to accomplish a certain task.
4587 @cindex @code{mov@var{m}} instruction pattern
4588 @item @samp{mov@var{m}}
4589 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4590 This instruction pattern moves data with that machine mode from operand
4591 1 to operand 0. For example, @samp{movsi} moves full-word data.
4593 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4594 own mode is wider than @var{m}, the effect of this instruction is
4595 to store the specified value in the part of the register that corresponds
4596 to mode @var{m}. Bits outside of @var{m}, but which are within the
4597 same target word as the @code{subreg} are undefined. Bits which are
4598 outside the target word are left unchanged.
4600 This class of patterns is special in several ways. First of all, each
4601 of these names up to and including full word size @emph{must} be defined,
4602 because there is no other way to copy a datum from one place to another.
4603 If there are patterns accepting operands in larger modes,
4604 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4606 Second, these patterns are not used solely in the RTL generation pass.
4607 Even the reload pass can generate move insns to copy values from stack
4608 slots into temporary registers. When it does so, one of the operands is
4609 a hard register and the other is an operand that can need to be reloaded
4613 Therefore, when given such a pair of operands, the pattern must generate
4614 RTL which needs no reloading and needs no temporary registers---no
4615 registers other than the operands. For example, if you support the
4616 pattern with a @code{define_expand}, then in such a case the
4617 @code{define_expand} mustn't call @code{force_reg} or any other such
4618 function which might generate new pseudo registers.
4620 This requirement exists even for subword modes on a RISC machine where
4621 fetching those modes from memory normally requires several insns and
4622 some temporary registers.
4624 @findex change_address
4625 During reload a memory reference with an invalid address may be passed
4626 as an operand. Such an address will be replaced with a valid address
4627 later in the reload pass. In this case, nothing may be done with the
4628 address except to use it as it stands. If it is copied, it will not be
4629 replaced with a valid address. No attempt should be made to make such
4630 an address into a valid address and no routine (such as
4631 @code{change_address}) that will do so may be called. Note that
4632 @code{general_operand} will fail when applied to such an address.
4634 @findex reload_in_progress
4635 The global variable @code{reload_in_progress} (which must be explicitly
4636 declared if required) can be used to determine whether such special
4637 handling is required.
4639 The variety of operands that have reloads depends on the rest of the
4640 machine description, but typically on a RISC machine these can only be
4641 pseudo registers that did not get hard registers, while on other
4642 machines explicit memory references will get optional reloads.
4644 If a scratch register is required to move an object to or from memory,
4645 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4647 If there are cases which need scratch registers during or after reload,
4648 you must provide an appropriate secondary_reload target hook.
4650 @findex can_create_pseudo_p
4651 The macro @code{can_create_pseudo_p} can be used to determine if it
4652 is unsafe to create new pseudo registers. If this variable is nonzero, then
4653 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4655 The constraints on a @samp{mov@var{m}} must permit moving any hard
4656 register to any other hard register provided that
4657 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4658 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4661 It is obligatory to support floating point @samp{mov@var{m}}
4662 instructions into and out of any registers that can hold fixed point
4663 values, because unions and structures (which have modes @code{SImode} or
4664 @code{DImode}) can be in those registers and they may have floating
4667 There may also be a need to support fixed point @samp{mov@var{m}}
4668 instructions in and out of floating point registers. Unfortunately, I
4669 have forgotten why this was so, and I don't know whether it is still
4670 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4671 floating point registers, then the constraints of the fixed point
4672 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4673 reload into a floating point register.
4675 @cindex @code{reload_in} instruction pattern
4676 @cindex @code{reload_out} instruction pattern
4677 @item @samp{reload_in@var{m}}
4678 @itemx @samp{reload_out@var{m}}
4679 These named patterns have been obsoleted by the target hook
4680 @code{secondary_reload}.
4682 Like @samp{mov@var{m}}, but used when a scratch register is required to
4683 move between operand 0 and operand 1. Operand 2 describes the scratch
4684 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4685 macro in @pxref{Register Classes}.
4687 There are special restrictions on the form of the @code{match_operand}s
4688 used in these patterns. First, only the predicate for the reload
4689 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4690 the predicates for operand 0 or 2. Second, there may be only one
4691 alternative in the constraints. Third, only a single register class
4692 letter may be used for the constraint; subsequent constraint letters
4693 are ignored. As a special exception, an empty constraint string
4694 matches the @code{ALL_REGS} register class. This may relieve ports
4695 of the burden of defining an @code{ALL_REGS} constraint letter just
4698 @cindex @code{movstrict@var{m}} instruction pattern
4699 @item @samp{movstrict@var{m}}
4700 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4701 with mode @var{m} of a register whose natural mode is wider,
4702 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4703 any of the register except the part which belongs to mode @var{m}.
4705 @cindex @code{movmisalign@var{m}} instruction pattern
4706 @item @samp{movmisalign@var{m}}
4707 This variant of a move pattern is designed to load or store a value
4708 from a memory address that is not naturally aligned for its mode.
4709 For a store, the memory will be in operand 0; for a load, the memory
4710 will be in operand 1. The other operand is guaranteed not to be a
4711 memory, so that it's easy to tell whether this is a load or store.
4713 This pattern is used by the autovectorizer, and when expanding a
4714 @code{MISALIGNED_INDIRECT_REF} expression.
4716 @cindex @code{load_multiple} instruction pattern
4717 @item @samp{load_multiple}
4718 Load several consecutive memory locations into consecutive registers.
4719 Operand 0 is the first of the consecutive registers, operand 1
4720 is the first memory location, and operand 2 is a constant: the
4721 number of consecutive registers.
4723 Define this only if the target machine really has such an instruction;
4724 do not define this if the most efficient way of loading consecutive
4725 registers from memory is to do them one at a time.
4727 On some machines, there are restrictions as to which consecutive
4728 registers can be stored into memory, such as particular starting or
4729 ending register numbers or only a range of valid counts. For those
4730 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4731 and make the pattern fail if the restrictions are not met.
4733 Write the generated insn as a @code{parallel} with elements being a
4734 @code{set} of one register from the appropriate memory location (you may
4735 also need @code{use} or @code{clobber} elements). Use a
4736 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4737 @file{rs6000.md} for examples of the use of this insn pattern.
4739 @cindex @samp{store_multiple} instruction pattern
4740 @item @samp{store_multiple}
4741 Similar to @samp{load_multiple}, but store several consecutive registers
4742 into consecutive memory locations. Operand 0 is the first of the
4743 consecutive memory locations, operand 1 is the first register, and
4744 operand 2 is a constant: the number of consecutive registers.
4746 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4747 @item @samp{vec_load_lanes@var{m}@var{n}}
4748 Perform an interleaved load of several vectors from memory operand 1
4749 into register operand 0. Both operands have mode @var{m}. The register
4750 operand is viewed as holding consecutive vectors of mode @var{n},
4751 while the memory operand is a flat array that contains the same number
4752 of elements. The operation is equivalent to:
4755 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4756 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4757 for (i = 0; i < c; i++)
4758 operand0[i][j] = operand1[j * c + i];
4761 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4762 from memory into a register of mode @samp{TI}@. The register
4763 contains two consecutive vectors of mode @samp{V4HI}@.
4765 This pattern can only be used if:
4767 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4769 is true. GCC assumes that, if a target supports this kind of
4770 instruction for some mode @var{n}, it also supports unaligned
4771 loads for vectors of mode @var{n}.
4773 This pattern is not allowed to @code{FAIL}.
4775 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4776 @item @samp{vec_store_lanes@var{m}@var{n}}
4777 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4778 and register operands reversed. That is, the instruction is
4782 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4783 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4784 for (i = 0; i < c; i++)
4785 operand0[j * c + i] = operand1[i][j];
4788 for a memory operand 0 and register operand 1.
4790 This pattern is not allowed to @code{FAIL}.
4792 @cindex @code{vec_set@var{m}} instruction pattern
4793 @item @samp{vec_set@var{m}}
4794 Set given field in the vector value. Operand 0 is the vector to modify,
4795 operand 1 is new value of field and operand 2 specify the field index.
4797 @cindex @code{vec_extract@var{m}} instruction pattern
4798 @item @samp{vec_extract@var{m}}
4799 Extract given field from the vector value. Operand 1 is the vector, operand 2
4800 specify field index and operand 0 place to store value into.
4802 @cindex @code{vec_init@var{m}} instruction pattern
4803 @item @samp{vec_init@var{m}}
4804 Initialize the vector to given values. Operand 0 is the vector to initialize
4805 and operand 1 is parallel containing values for individual fields.
4807 @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern
4808 @item @samp{vec_cmp@var{m}@var{n}}
4809 Output a vector comparison. Operand 0 of mode @var{n} is the destination for
4810 predicate in operand 1 which is a signed vector comparison with operands of
4811 mode @var{m} in operands 2 and 3. Predicate is computed by element-wise
4812 evaluation of the vector comparison with a truth value of all-ones and a false
4815 @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern
4816 @item @samp{vec_cmpu@var{m}@var{n}}
4817 Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison.
4819 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4820 @item @samp{vcond@var{m}@var{n}}
4821 Output a conditional vector move. Operand 0 is the destination to
4822 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4823 dependent on the outcome of the predicate in operand 3 which is a signed
4824 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4825 modes @var{m} and @var{n} should have the same size. Operand 0
4826 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4827 where @var{msk} is computed by element-wise evaluation of the vector
4828 comparison with a truth value of all-ones and a false value of all-zeros.
4830 @cindex @code{vcondu@var{m}@var{n}} instruction pattern
4831 @item @samp{vcondu@var{m}@var{n}}
4832 Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector
4835 @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern
4836 @item @samp{vcond_mask_@var{m}@var{n}}
4837 Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed
4838 result of vector comparison.
4840 @cindex @code{maskload@var{m}@var{n}} instruction pattern
4841 @item @samp{maskload@var{m}@var{n}}
4842 Perform a masked load of vector from memory operand 1 of mode @var{m}
4843 into register operand 0. Mask is provided in register operand 2 of
4846 This pattern is not allowed to @code{FAIL}.
4848 @cindex @code{maskstore@var{m}@var{n}} instruction pattern
4849 @item @samp{maskstore@var{m}@var{n}}
4850 Perform a masked store of vector from register operand 1 of mode @var{m}
4851 into memory operand 0. Mask is provided in register operand 2 of
4854 This pattern is not allowed to @code{FAIL}.
4856 @cindex @code{vec_perm@var{m}} instruction pattern
4857 @item @samp{vec_perm@var{m}}
4858 Output a (variable) vector permutation. Operand 0 is the destination
4859 to receive elements from operand 1 and operand 2, which are of mode
4860 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4861 vector of the same width and number of elements as mode @var{m}.
4863 The input elements are numbered from 0 in operand 1 through
4864 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4865 be computed modulo @math{2*@var{N}}. Note that if
4866 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4867 with just operand 1 and selector elements modulo @var{N}.
4869 In order to make things easy for a number of targets, if there is no
4870 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4871 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4872 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4875 @cindex @code{vec_perm_const@var{m}} instruction pattern
4876 @item @samp{vec_perm_const@var{m}}
4877 Like @samp{vec_perm} except that the permutation is a compile-time
4878 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4880 Some targets cannot perform a permutation with a variable selector,
4881 but can efficiently perform a constant permutation. Further, the
4882 target hook @code{vec_perm_ok} is queried to determine if the
4883 specific constant permutation is available efficiently; the named
4884 pattern is never expanded without @code{vec_perm_ok} returning true.
4886 There is no need for a target to supply both @samp{vec_perm@var{m}}
4887 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4888 the operation with, say, the vector constant loaded into a register.
4890 @cindex @code{push@var{m}1} instruction pattern
4891 @item @samp{push@var{m}1}
4892 Output a push instruction. Operand 0 is value to push. Used only when
4893 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4894 missing and in such case an @code{mov} expander is used instead, with a
4895 @code{MEM} expression forming the push operation. The @code{mov} expander
4896 method is deprecated.
4898 @cindex @code{add@var{m}3} instruction pattern
4899 @item @samp{add@var{m}3}
4900 Add operand 2 and operand 1, storing the result in operand 0. All operands
4901 must have mode @var{m}. This can be used even on two-address machines, by
4902 means of constraints requiring operands 1 and 0 to be the same location.
4904 @cindex @code{ssadd@var{m}3} instruction pattern
4905 @cindex @code{usadd@var{m}3} instruction pattern
4906 @cindex @code{sub@var{m}3} instruction pattern
4907 @cindex @code{sssub@var{m}3} instruction pattern
4908 @cindex @code{ussub@var{m}3} instruction pattern
4909 @cindex @code{mul@var{m}3} instruction pattern
4910 @cindex @code{ssmul@var{m}3} instruction pattern
4911 @cindex @code{usmul@var{m}3} instruction pattern
4912 @cindex @code{div@var{m}3} instruction pattern
4913 @cindex @code{ssdiv@var{m}3} instruction pattern
4914 @cindex @code{udiv@var{m}3} instruction pattern
4915 @cindex @code{usdiv@var{m}3} instruction pattern
4916 @cindex @code{mod@var{m}3} instruction pattern
4917 @cindex @code{umod@var{m}3} instruction pattern
4918 @cindex @code{umin@var{m}3} instruction pattern
4919 @cindex @code{umax@var{m}3} instruction pattern
4920 @cindex @code{and@var{m}3} instruction pattern
4921 @cindex @code{ior@var{m}3} instruction pattern
4922 @cindex @code{xor@var{m}3} instruction pattern
4923 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4924 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4925 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4926 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4927 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4928 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4929 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4930 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4931 Similar, for other arithmetic operations.
4933 @cindex @code{addv@var{m}4} instruction pattern
4934 @item @samp{addv@var{m}4}
4935 Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and
4936 emits code to jump to it if signed overflow occurs during the addition.
4937 This pattern is used to implement the built-in functions performing
4938 signed integer addition with overflow checking.
4940 @cindex @code{subv@var{m}4} instruction pattern
4941 @cindex @code{mulv@var{m}4} instruction pattern
4942 @item @samp{subv@var{m}4}, @samp{mulv@var{m}4}
4943 Similar, for other signed arithmetic operations.
4945 @cindex @code{uaddv@var{m}4} instruction pattern
4946 @item @samp{uaddv@var{m}4}
4947 Like @code{addv@var{m}4} but for unsigned addition. That is to
4948 say, the operation is the same as signed addition but the jump
4949 is taken only on unsigned overflow.
4951 @cindex @code{usubv@var{m}4} instruction pattern
4952 @cindex @code{umulv@var{m}4} instruction pattern
4953 @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4}
4954 Similar, for other unsigned arithmetic operations.
4956 @cindex @code{addptr@var{m}3} instruction pattern
4957 @item @samp{addptr@var{m}3}
4958 Like @code{add@var{m}3} but is guaranteed to only be used for address
4959 calculations. The expanded code is not allowed to clobber the
4960 condition code. It only needs to be defined if @code{add@var{m}3}
4961 sets the condition code. If adds used for address calculations and
4962 normal adds are not compatible it is required to expand a distinct
4963 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4964 address calculations. @code{add@var{m}3} is used if
4965 @code{addptr@var{m}3} is not defined.
4967 @cindex @code{fma@var{m}4} instruction pattern
4968 @item @samp{fma@var{m}4}
4969 Multiply operand 2 and operand 1, then add operand 3, storing the
4970 result in operand 0 without doing an intermediate rounding step. All
4971 operands must have mode @var{m}. This pattern is used to implement
4972 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4973 the ISO C99 standard.
4975 @cindex @code{fms@var{m}4} instruction pattern
4976 @item @samp{fms@var{m}4}
4977 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4978 product instead of added to the product. This is represented
4982 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4985 @cindex @code{fnma@var{m}4} instruction pattern
4986 @item @samp{fnma@var{m}4}
4987 Like @code{fma@var{m}4} except that the intermediate product
4988 is negated before being added to operand 3. This is represented
4992 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4995 @cindex @code{fnms@var{m}4} instruction pattern
4996 @item @samp{fnms@var{m}4}
4997 Like @code{fms@var{m}4} except that the intermediate product
4998 is negated before subtracting operand 3. This is represented
5002 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
5005 @cindex @code{min@var{m}3} instruction pattern
5006 @cindex @code{max@var{m}3} instruction pattern
5007 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
5008 Signed minimum and maximum operations. When used with floating point,
5009 if both operands are zeros, or if either operand is @code{NaN}, then
5010 it is unspecified which of the two operands is returned as the result.
5012 @cindex @code{fmin@var{m}3} instruction pattern
5013 @cindex @code{fmax@var{m}3} instruction pattern
5014 @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3}
5015 IEEE-conformant minimum and maximum operations. If one operand is a quiet
5016 @code{NaN}, then the other operand is returned. If both operands are quiet
5017 @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports
5018 signalling @code{NaN} (-fsignaling-nans) an invalid floating point exception is
5019 raised and a quiet @code{NaN} is returned.
5021 All operands have mode @var{m}, which is a scalar or vector
5022 floating-point mode. These patterns are not allowed to @code{FAIL}.
5024 @cindex @code{reduc_smin_scal_@var{m}} instruction pattern
5025 @cindex @code{reduc_smax_scal_@var{m}} instruction pattern
5026 @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}}
5027 Find the signed minimum/maximum of the elements of a vector. The vector is
5028 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5029 the elements of the input vector.
5031 @cindex @code{reduc_umin_scal_@var{m}} instruction pattern
5032 @cindex @code{reduc_umax_scal_@var{m}} instruction pattern
5033 @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}}
5034 Find the unsigned minimum/maximum of the elements of a vector. The vector is
5035 operand 1, and operand 0 is the scalar result, with mode equal to the mode of
5036 the elements of the input vector.
5038 @cindex @code{reduc_plus_scal_@var{m}} instruction pattern
5039 @item @samp{reduc_plus_scal_@var{m}}
5040 Compute the sum of the elements of a vector. The vector is operand 1, and
5041 operand 0 is the scalar result, with mode equal to the mode of the elements of
5044 @cindex @code{sdot_prod@var{m}} instruction pattern
5045 @item @samp{sdot_prod@var{m}}
5046 @cindex @code{udot_prod@var{m}} instruction pattern
5047 @itemx @samp{udot_prod@var{m}}
5048 Compute the sum of the products of two signed/unsigned elements.
5049 Operand 1 and operand 2 are of the same mode. Their product, which is of a
5050 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
5051 wider than the mode of the product. The result is placed in operand 0, which
5052 is of the same mode as operand 3.
5054 @cindex @code{ssad@var{m}} instruction pattern
5055 @item @samp{ssad@var{m}}
5056 @cindex @code{usad@var{m}} instruction pattern
5057 @item @samp{usad@var{m}}
5058 Compute the sum of absolute differences of two signed/unsigned elements.
5059 Operand 1 and operand 2 are of the same mode. Their absolute difference, which
5060 is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode
5061 equal or wider than the mode of the absolute difference. The result is placed
5062 in operand 0, which is of the same mode as operand 3.
5064 @cindex @code{widen_ssum@var{m3}} instruction pattern
5065 @item @samp{widen_ssum@var{m3}}
5066 @cindex @code{widen_usum@var{m3}} instruction pattern
5067 @itemx @samp{widen_usum@var{m3}}
5068 Operands 0 and 2 are of the same mode, which is wider than the mode of
5069 operand 1. Add operand 1 to operand 2 and place the widened result in
5070 operand 0. (This is used express accumulation of elements into an accumulator
5073 @cindex @code{vec_shr_@var{m}} instruction pattern
5074 @item @samp{vec_shr_@var{m}}
5075 Whole vector right shift in bits, i.e. towards element 0.
5076 Operand 1 is a vector to be shifted.
5077 Operand 2 is an integer shift amount in bits.
5078 Operand 0 is where the resulting shifted vector is stored.
5079 The output and input vectors should have the same modes.
5081 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
5082 @item @samp{vec_pack_trunc_@var{m}}
5083 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5084 are vectors of the same mode having N integral or floating point elements
5085 of size S@. Operand 0 is the resulting vector in which 2*N elements of
5086 size N/2 are concatenated after narrowing them down using truncation.
5088 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
5089 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
5090 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
5091 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
5092 are vectors of the same mode having N integral elements of size S.
5093 Operand 0 is the resulting vector in which the elements of the two input
5094 vectors are concatenated after narrowing them down using signed/unsigned
5095 saturating arithmetic.
5097 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
5098 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
5099 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
5100 Narrow, convert to signed/unsigned integral type and merge the elements
5101 of two vectors. Operands 1 and 2 are vectors of the same mode having N
5102 floating point elements of size S@. Operand 0 is the resulting vector
5103 in which 2*N elements of size N/2 are concatenated.
5105 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
5106 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
5107 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
5108 Extract and widen (promote) the high/low part of a vector of signed
5109 integral or floating point elements. The input vector (operand 1) has N
5110 elements of size S@. Widen (promote) the high/low elements of the vector
5111 using signed or floating point extension and place the resulting N/2
5112 values of size 2*S in the output vector (operand 0).
5114 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
5115 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
5116 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
5117 Extract and widen (promote) the high/low part of a vector of unsigned
5118 integral elements. The input vector (operand 1) has N elements of size S.
5119 Widen (promote) the high/low elements of the vector using zero extension and
5120 place the resulting N/2 values of size 2*S in the output vector (operand 0).
5122 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
5123 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
5124 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
5125 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
5126 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
5127 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
5128 Extract, convert to floating point type and widen the high/low part of a
5129 vector of signed/unsigned integral elements. The input vector (operand 1)
5130 has N elements of size S@. Convert the high/low elements of the vector using
5131 floating point conversion and place the resulting N/2 values of size 2*S in
5132 the output vector (operand 0).
5134 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
5135 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
5136 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
5137 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
5138 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
5139 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
5140 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
5141 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
5142 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
5143 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
5144 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
5145 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
5146 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
5147 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
5148 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
5149 in the output vector (operand 0). A target shouldn't implement even/odd pattern
5150 pair if it is less efficient than lo/hi one.
5152 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
5153 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
5154 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
5155 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
5156 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
5157 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
5158 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
5159 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
5160 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
5161 output vector (operand 0).
5163 @cindex @code{mulhisi3} instruction pattern
5164 @item @samp{mulhisi3}
5165 Multiply operands 1 and 2, which have mode @code{HImode}, and store
5166 a @code{SImode} product in operand 0.
5168 @cindex @code{mulqihi3} instruction pattern
5169 @cindex @code{mulsidi3} instruction pattern
5170 @item @samp{mulqihi3}, @samp{mulsidi3}
5171 Similar widening-multiplication instructions of other widths.
5173 @cindex @code{umulqihi3} instruction pattern
5174 @cindex @code{umulhisi3} instruction pattern
5175 @cindex @code{umulsidi3} instruction pattern
5176 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
5177 Similar widening-multiplication instructions that do unsigned
5180 @cindex @code{usmulqihi3} instruction pattern
5181 @cindex @code{usmulhisi3} instruction pattern
5182 @cindex @code{usmulsidi3} instruction pattern
5183 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
5184 Similar widening-multiplication instructions that interpret the first
5185 operand as unsigned and the second operand as signed, then do a signed
5188 @cindex @code{smul@var{m}3_highpart} instruction pattern
5189 @item @samp{smul@var{m}3_highpart}
5190 Perform a signed multiplication of operands 1 and 2, which have mode
5191 @var{m}, and store the most significant half of the product in operand 0.
5192 The least significant half of the product is discarded.
5194 @cindex @code{umul@var{m}3_highpart} instruction pattern
5195 @item @samp{umul@var{m}3_highpart}
5196 Similar, but the multiplication is unsigned.
5198 @cindex @code{madd@var{m}@var{n}4} instruction pattern
5199 @item @samp{madd@var{m}@var{n}4}
5200 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
5201 operand 3, and store the result in operand 0. Operands 1 and 2
5202 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5203 Both modes must be integer or fixed-point modes and @var{n} must be twice
5204 the size of @var{m}.
5206 In other words, @code{madd@var{m}@var{n}4} is like
5207 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
5209 These instructions are not allowed to @code{FAIL}.
5211 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
5212 @item @samp{umadd@var{m}@var{n}4}
5213 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5214 operands instead of sign-extending them.
5216 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5217 @item @samp{ssmadd@var{m}@var{n}4}
5218 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5221 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5222 @item @samp{usmadd@var{m}@var{n}4}
5223 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5224 unsigned-saturating.
5226 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5227 @item @samp{msub@var{m}@var{n}4}
5228 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5229 result from operand 3, and store the result in operand 0. Operands 1 and 2
5230 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5231 Both modes must be integer or fixed-point modes and @var{n} must be twice
5232 the size of @var{m}.
5234 In other words, @code{msub@var{m}@var{n}4} is like
5235 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5238 These instructions are not allowed to @code{FAIL}.
5240 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5241 @item @samp{umsub@var{m}@var{n}4}
5242 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5243 operands instead of sign-extending them.
5245 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5246 @item @samp{ssmsub@var{m}@var{n}4}
5247 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5250 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5251 @item @samp{usmsub@var{m}@var{n}4}
5252 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5253 unsigned-saturating.
5255 @cindex @code{divmod@var{m}4} instruction pattern
5256 @item @samp{divmod@var{m}4}
5257 Signed division that produces both a quotient and a remainder.
5258 Operand 1 is divided by operand 2 to produce a quotient stored
5259 in operand 0 and a remainder stored in operand 3.
5261 For machines with an instruction that produces both a quotient and a
5262 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5263 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5264 allows optimization in the relatively common case when both the quotient
5265 and remainder are computed.
5267 If an instruction that just produces a quotient or just a remainder
5268 exists and is more efficient than the instruction that produces both,
5269 write the output routine of @samp{divmod@var{m}4} to call
5270 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5271 quotient or remainder and generate the appropriate instruction.
5273 @cindex @code{udivmod@var{m}4} instruction pattern
5274 @item @samp{udivmod@var{m}4}
5275 Similar, but does unsigned division.
5277 @anchor{shift patterns}
5278 @cindex @code{ashl@var{m}3} instruction pattern
5279 @cindex @code{ssashl@var{m}3} instruction pattern
5280 @cindex @code{usashl@var{m}3} instruction pattern
5281 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5282 Arithmetic-shift operand 1 left by a number of bits specified by operand
5283 2, and store the result in operand 0. Here @var{m} is the mode of
5284 operand 0 and operand 1; operand 2's mode is specified by the
5285 instruction pattern, and the compiler will convert the operand to that
5286 mode before generating the instruction. The shift or rotate expander
5287 or instruction pattern should explicitly specify the mode of the operand 2,
5288 it should never be @code{VOIDmode}. The meaning of out-of-range shift
5289 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5290 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5292 @cindex @code{ashr@var{m}3} instruction pattern
5293 @cindex @code{lshr@var{m}3} instruction pattern
5294 @cindex @code{rotl@var{m}3} instruction pattern
5295 @cindex @code{rotr@var{m}3} instruction pattern
5296 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5297 Other shift and rotate instructions, analogous to the
5298 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5300 @cindex @code{vashl@var{m}3} instruction pattern
5301 @cindex @code{vashr@var{m}3} instruction pattern
5302 @cindex @code{vlshr@var{m}3} instruction pattern
5303 @cindex @code{vrotl@var{m}3} instruction pattern
5304 @cindex @code{vrotr@var{m}3} instruction pattern
5305 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5306 Vector shift and rotate instructions that take vectors as operand 2
5307 instead of a scalar type.
5309 @cindex @code{bswap@var{m}2} instruction pattern
5310 @item @samp{bswap@var{m}2}
5311 Reverse the order of bytes of operand 1 and store the result in operand 0.
5313 @cindex @code{neg@var{m}2} instruction pattern
5314 @cindex @code{ssneg@var{m}2} instruction pattern
5315 @cindex @code{usneg@var{m}2} instruction pattern
5316 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5317 Negate operand 1 and store the result in operand 0.
5319 @cindex @code{negv@var{m}3} instruction pattern
5320 @item @samp{negv@var{m}3}
5321 Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and
5322 emits code to jump to it if signed overflow occurs during the negation.
5324 @cindex @code{abs@var{m}2} instruction pattern
5325 @item @samp{abs@var{m}2}
5326 Store the absolute value of operand 1 into operand 0.
5328 @cindex @code{sqrt@var{m}2} instruction pattern
5329 @item @samp{sqrt@var{m}2}
5330 Store the square root of operand 1 into operand 0. Both operands have
5331 mode @var{m}, which is a scalar or vector floating-point mode.
5333 This pattern is not allowed to @code{FAIL}.
5335 @cindex @code{rsqrt@var{m}2} instruction pattern
5336 @item @samp{rsqrt@var{m}2}
5337 Store the reciprocal of the square root of operand 1 into operand 0.
5338 Both operands have mode @var{m}, which is a scalar or vector
5339 floating-point mode.
5341 On most architectures this pattern is only approximate, so either
5342 its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should
5343 check for the appropriate math flags. (Using the C condition is
5344 more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful
5345 if a target-specific built-in also uses the @samp{rsqrt@var{m}2}
5348 This pattern is not allowed to @code{FAIL}.
5350 @cindex @code{fmod@var{m}3} instruction pattern
5351 @item @samp{fmod@var{m}3}
5352 Store the remainder of dividing operand 1 by operand 2 into
5353 operand 0, rounded towards zero to an integer. All operands have
5354 mode @var{m}, which is a scalar or vector floating-point mode.
5356 This pattern is not allowed to @code{FAIL}.
5358 @cindex @code{remainder@var{m}3} instruction pattern
5359 @item @samp{remainder@var{m}3}
5360 Store the remainder of dividing operand 1 by operand 2 into
5361 operand 0, rounded to the nearest integer. All operands have
5362 mode @var{m}, which is a scalar or vector floating-point mode.
5364 This pattern is not allowed to @code{FAIL}.
5366 @cindex @code{scalb@var{m}3} instruction pattern
5367 @item @samp{scalb@var{m}3}
5368 Raise @code{FLT_RADIX} to the power of operand 2, multiply it by
5369 operand 1, and store the result in operand 0. All operands have
5370 mode @var{m}, which is a scalar or vector floating-point mode.
5372 This pattern is not allowed to @code{FAIL}.
5374 @cindex @code{ldexp@var{m}3} instruction pattern
5375 @item @samp{ldexp@var{m}3}
5376 Raise 2 to the power of operand 2, multiply it by operand 1, and store
5377 the result in operand 0. Operands 0 and 1 have mode @var{m}, which is
5378 a scalar or vector floating-point mode. Operand 2's mode has
5379 the same number of elements as @var{m} and each element is wide
5380 enough to store an @code{int}. The integers are signed.
5382 This pattern is not allowed to @code{FAIL}.
5384 @cindex @code{cos@var{m}2} instruction pattern
5385 @item @samp{cos@var{m}2}
5386 Store the cosine of operand 1 into operand 0. Both operands have
5387 mode @var{m}, which is a scalar or vector floating-point mode.
5389 This pattern is not allowed to @code{FAIL}.
5391 @cindex @code{sin@var{m}2} instruction pattern
5392 @item @samp{sin@var{m}2}
5393 Store the sine of operand 1 into operand 0. Both operands have
5394 mode @var{m}, which is a scalar or vector floating-point mode.
5396 This pattern is not allowed to @code{FAIL}.
5398 @cindex @code{sincos@var{m}3} instruction pattern
5399 @item @samp{sincos@var{m}3}
5400 Store the cosine of operand 2 into operand 0 and the sine of
5401 operand 2 into operand 1. All operands have mode @var{m},
5402 which is a scalar or vector floating-point mode.
5404 Targets that can calculate the sine and cosine simultaneously can
5405 implement this pattern as opposed to implementing individual
5406 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5407 and @code{cos} built-in functions will then be expanded to the
5408 @code{sincos@var{m}3} pattern, with one of the output values
5411 @cindex @code{tan@var{m}2} instruction pattern
5412 @item @samp{tan@var{m}2}
5413 Store the tangent of operand 1 into operand 0. Both operands have
5414 mode @var{m}, which is a scalar or vector floating-point mode.
5416 This pattern is not allowed to @code{FAIL}.
5418 @cindex @code{asin@var{m}2} instruction pattern
5419 @item @samp{asin@var{m}2}
5420 Store the arc sine of operand 1 into operand 0. Both operands have
5421 mode @var{m}, which is a scalar or vector floating-point mode.
5423 This pattern is not allowed to @code{FAIL}.
5425 @cindex @code{acos@var{m}2} instruction pattern
5426 @item @samp{acos@var{m}2}
5427 Store the arc cosine of operand 1 into operand 0. Both operands have
5428 mode @var{m}, which is a scalar or vector floating-point mode.
5430 This pattern is not allowed to @code{FAIL}.
5432 @cindex @code{atan@var{m}2} instruction pattern
5433 @item @samp{atan@var{m}2}
5434 Store the arc tangent of operand 1 into operand 0. Both operands have
5435 mode @var{m}, which is a scalar or vector floating-point mode.
5437 This pattern is not allowed to @code{FAIL}.
5439 @cindex @code{exp@var{m}2} instruction pattern
5440 @item @samp{exp@var{m}2}
5441 Raise e (the base of natural logarithms) to the power of operand 1
5442 and store the result in operand 0. Both operands have mode @var{m},
5443 which is a scalar or vector floating-point mode.
5445 This pattern is not allowed to @code{FAIL}.
5447 @cindex @code{expm1@var{m}2} instruction pattern
5448 @item @samp{expm1@var{m}2}
5449 Raise e (the base of natural logarithms) to the power of operand 1,
5450 subtract 1, and store the result in operand 0. Both operands have
5451 mode @var{m}, which is a scalar or vector floating-point mode.
5453 For inputs close to zero, the pattern is expected to be more
5454 accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3}
5457 This pattern is not allowed to @code{FAIL}.
5459 @cindex @code{exp10@var{m}2} instruction pattern
5460 @item @samp{exp10@var{m}2}
5461 Raise 10 to the power of operand 1 and store the result in operand 0.
5462 Both operands have mode @var{m}, which is a scalar or vector
5463 floating-point mode.
5465 This pattern is not allowed to @code{FAIL}.
5467 @cindex @code{exp2@var{m}2} instruction pattern
5468 @item @samp{exp2@var{m}2}
5469 Raise 2 to the power of operand 1 and store the result in operand 0.
5470 Both operands have mode @var{m}, which is a scalar or vector
5471 floating-point mode.
5473 This pattern is not allowed to @code{FAIL}.
5475 @cindex @code{log@var{m}2} instruction pattern
5476 @item @samp{log@var{m}2}
5477 Store the natural logarithm of operand 1 into operand 0. Both operands
5478 have mode @var{m}, which is a scalar or vector floating-point mode.
5480 This pattern is not allowed to @code{FAIL}.
5482 @cindex @code{log1p@var{m}2} instruction pattern
5483 @item @samp{log1p@var{m}2}
5484 Add 1 to operand 1, compute the natural logarithm, and store
5485 the result in operand 0. Both operands have mode @var{m}, which is
5486 a scalar or vector floating-point mode.
5488 For inputs close to zero, the pattern is expected to be more
5489 accurate than a separate @code{add@var{m}3} and @code{log@var{m}2}
5492 This pattern is not allowed to @code{FAIL}.
5494 @cindex @code{log10@var{m}2} instruction pattern
5495 @item @samp{log10@var{m}2}
5496 Store the base-10 logarithm of operand 1 into operand 0. Both operands
5497 have mode @var{m}, which is a scalar or vector floating-point mode.
5499 This pattern is not allowed to @code{FAIL}.
5501 @cindex @code{log2@var{m}2} instruction pattern
5502 @item @samp{log2@var{m}2}
5503 Store the base-2 logarithm of operand 1 into operand 0. Both operands
5504 have mode @var{m}, which is a scalar or vector floating-point mode.
5506 This pattern is not allowed to @code{FAIL}.
5508 @cindex @code{logb@var{m}2} instruction pattern
5509 @item @samp{logb@var{m}2}
5510 Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0.
5511 Both operands have mode @var{m}, which is a scalar or vector
5512 floating-point mode.
5514 This pattern is not allowed to @code{FAIL}.
5516 @cindex @code{significand@var{m}2} instruction pattern
5517 @item @samp{significand@var{m}2}
5518 Store the significand of floating-point operand 1 in operand 0.
5519 Both operands have mode @var{m}, which is a scalar or vector
5520 floating-point mode.
5522 This pattern is not allowed to @code{FAIL}.
5524 @cindex @code{pow@var{m}3} instruction pattern
5525 @item @samp{pow@var{m}3}
5526 Store the value of operand 1 raised to the exponent operand 2
5527 into operand 0. All operands have mode @var{m}, which is a scalar
5528 or vector floating-point mode.
5530 This pattern is not allowed to @code{FAIL}.
5532 @cindex @code{atan2@var{m}3} instruction pattern
5533 @item @samp{atan2@var{m}3}
5534 Store the arc tangent (inverse tangent) of operand 1 divided by
5535 operand 2 into operand 0, using the signs of both arguments to
5536 determine the quadrant of the result. All operands have mode
5537 @var{m}, which is a scalar or vector floating-point mode.
5539 This pattern is not allowed to @code{FAIL}.
5541 @cindex @code{floor@var{m}2} instruction pattern
5542 @item @samp{floor@var{m}2}
5543 Store the largest integral value not greater than operand 1 in operand 0.
5544 Both operands have mode @var{m}, which is a scalar or vector
5545 floating-point mode.
5547 This pattern is not allowed to @code{FAIL}.
5549 @cindex @code{btrunc@var{m}2} instruction pattern
5550 @item @samp{btrunc@var{m}2}
5551 Round operand 1 to an integer, towards zero, and store the result in
5552 operand 0. Both operands have mode @var{m}, which is a scalar or
5553 vector floating-point mode.
5555 This pattern is not allowed to @code{FAIL}.
5557 @cindex @code{round@var{m}2} instruction pattern
5558 @item @samp{round@var{m}2}
5559 Round operand 1 to the nearest integer, rounding away from zero in the
5560 event of a tie, and store the result in operand 0. Both operands have
5561 mode @var{m}, which is a scalar or vector floating-point mode.
5563 This pattern is not allowed to @code{FAIL}.
5565 @cindex @code{ceil@var{m}2} instruction pattern
5566 @item @samp{ceil@var{m}2}
5567 Store the smallest integral value not less than operand 1 in operand 0.
5568 Both operands have mode @var{m}, which is a scalar or vector
5569 floating-point mode.
5571 This pattern is not allowed to @code{FAIL}.
5573 @cindex @code{nearbyint@var{m}2} instruction pattern
5574 @item @samp{nearbyint@var{m}2}
5575 Round operand 1 to an integer, using the current rounding mode, and
5576 store the result in operand 0. Do not raise an inexact condition when
5577 the result is different from the argument. Both operands have mode
5578 @var{m}, which is a scalar or vector floating-point mode.
5580 This pattern is not allowed to @code{FAIL}.
5582 @cindex @code{rint@var{m}2} instruction pattern
5583 @item @samp{rint@var{m}2}
5584 Round operand 1 to an integer, using the current rounding mode, and
5585 store the result in operand 0. Raise an inexact condition when
5586 the result is different from the argument. Both operands have mode
5587 @var{m}, which is a scalar or vector floating-point mode.
5589 This pattern is not allowed to @code{FAIL}.
5591 @cindex @code{lrint@var{m}@var{n}2}
5592 @item @samp{lrint@var{m}@var{n}2}
5593 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5594 point mode @var{n} as a signed number according to the current
5595 rounding mode and store in operand 0 (which has mode @var{n}).
5597 @cindex @code{lround@var{m}@var{n}2}
5598 @item @samp{lround@var{m}@var{n}2}
5599 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5600 point mode @var{n} as a signed number rounding to nearest and away
5601 from zero and store in operand 0 (which has mode @var{n}).
5603 @cindex @code{lfloor@var{m}@var{n}2}
5604 @item @samp{lfloor@var{m}@var{n}2}
5605 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5606 point mode @var{n} as a signed number rounding down and store in
5607 operand 0 (which has mode @var{n}).
5609 @cindex @code{lceil@var{m}@var{n}2}
5610 @item @samp{lceil@var{m}@var{n}2}
5611 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5612 point mode @var{n} as a signed number rounding up and store in
5613 operand 0 (which has mode @var{n}).
5615 @cindex @code{copysign@var{m}3} instruction pattern
5616 @item @samp{copysign@var{m}3}
5617 Store a value with the magnitude of operand 1 and the sign of operand
5618 2 into operand 0. All operands have mode @var{m}, which is a scalar or
5619 vector floating-point mode.
5621 This pattern is not allowed to @code{FAIL}.
5623 @cindex @code{ffs@var{m}2} instruction pattern
5624 @item @samp{ffs@var{m}2}
5625 Store into operand 0 one plus the index of the least significant 1-bit
5626 of operand 1. If operand 1 is zero, store zero.
5628 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5629 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5630 integer mode is suitable for the target. The compiler will insert
5631 conversion instructions as necessary (typically to convert the result
5632 to the same width as @code{int}). When @var{m} is a vector, both
5633 operands must have mode @var{m}.
5635 This pattern is not allowed to @code{FAIL}.
5637 @cindex @code{clrsb@var{m}2} instruction pattern
5638 @item @samp{clrsb@var{m}2}
5639 Count leading redundant sign bits.
5640 Store into operand 0 the number of redundant sign bits in operand 1, starting
5641 at the most significant bit position.
5642 A redundant sign bit is defined as any sign bit after the first. As such,
5643 this count will be one less than the count of leading sign bits.
5645 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5646 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5647 integer mode is suitable for the target. The compiler will insert
5648 conversion instructions as necessary (typically to convert the result
5649 to the same width as @code{int}). When @var{m} is a vector, both
5650 operands must have mode @var{m}.
5652 This pattern is not allowed to @code{FAIL}.
5654 @cindex @code{clz@var{m}2} instruction pattern
5655 @item @samp{clz@var{m}2}
5656 Store into operand 0 the number of leading 0-bits in operand 1, starting
5657 at the most significant bit position. If operand 1 is 0, the
5658 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5659 the result is undefined or has a useful value.
5661 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5662 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5663 integer mode is suitable for the target. The compiler will insert
5664 conversion instructions as necessary (typically to convert the result
5665 to the same width as @code{int}). When @var{m} is a vector, both
5666 operands must have mode @var{m}.
5668 This pattern is not allowed to @code{FAIL}.
5670 @cindex @code{ctz@var{m}2} instruction pattern
5671 @item @samp{ctz@var{m}2}
5672 Store into operand 0 the number of trailing 0-bits in operand 1, starting
5673 at the least significant bit position. If operand 1 is 0, the
5674 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5675 the result is undefined or has a useful value.
5677 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5678 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5679 integer mode is suitable for the target. The compiler will insert
5680 conversion instructions as necessary (typically to convert the result
5681 to the same width as @code{int}). When @var{m} is a vector, both
5682 operands must have mode @var{m}.
5684 This pattern is not allowed to @code{FAIL}.
5686 @cindex @code{popcount@var{m}2} instruction pattern
5687 @item @samp{popcount@var{m}2}
5688 Store into operand 0 the number of 1-bits in operand 1.
5690 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5691 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5692 integer mode is suitable for the target. The compiler will insert
5693 conversion instructions as necessary (typically to convert the result
5694 to the same width as @code{int}). When @var{m} is a vector, both
5695 operands must have mode @var{m}.
5697 This pattern is not allowed to @code{FAIL}.
5699 @cindex @code{parity@var{m}2} instruction pattern
5700 @item @samp{parity@var{m}2}
5701 Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits
5702 in operand 1 modulo 2.
5704 @var{m} is either a scalar or vector integer mode. When it is a scalar,
5705 operand 1 has mode @var{m} but operand 0 can have whatever scalar
5706 integer mode is suitable for the target. The compiler will insert
5707 conversion instructions as necessary (typically to convert the result
5708 to the same width as @code{int}). When @var{m} is a vector, both
5709 operands must have mode @var{m}.
5711 This pattern is not allowed to @code{FAIL}.
5713 @cindex @code{one_cmpl@var{m}2} instruction pattern
5714 @item @samp{one_cmpl@var{m}2}
5715 Store the bitwise-complement of operand 1 into operand 0.
5717 @cindex @code{movmem@var{m}} instruction pattern
5718 @item @samp{movmem@var{m}}
5719 Block move instruction. The destination and source blocks of memory
5720 are the first two operands, and both are @code{mem:BLK}s with an
5721 address in mode @code{Pmode}.
5723 The number of bytes to move is the third operand, in mode @var{m}.
5724 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5725 generate better code knowing the range of valid lengths is smaller than
5726 those representable in a full Pmode pointer, you should provide
5728 mode corresponding to the range of values you can handle efficiently
5729 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5730 that appear negative) and also a pattern with @code{Pmode}.
5732 The fourth operand is the known shared alignment of the source and
5733 destination, in the form of a @code{const_int} rtx. Thus, if the
5734 compiler knows that both source and destination are word-aligned,
5735 it may provide the value 4 for this operand.
5737 Optional operands 5 and 6 specify expected alignment and size of block
5738 respectively. The expected alignment differs from alignment in operand 4
5739 in a way that the blocks are not required to be aligned according to it in
5740 all cases. This expected alignment is also in bytes, just like operand 4.
5741 Expected size, when unknown, is set to @code{(const_int -1)}.
5743 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5744 beneficial if the patterns for smaller modes have fewer restrictions
5745 on their first, second and fourth operands. Note that the mode @var{m}
5746 in @code{movmem@var{m}} does not impose any restriction on the mode of
5747 individually moved data units in the block.
5749 These patterns need not give special consideration to the possibility
5750 that the source and destination strings might overlap.
5752 @cindex @code{movstr} instruction pattern
5754 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5755 an output operand in mode @code{Pmode}. The addresses of the
5756 destination and source strings are operands 1 and 2, and both are
5757 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5758 the expansion of this pattern should store in operand 0 the address in
5759 which the @code{NUL} terminator was stored in the destination string.
5761 This patern has also several optional operands that are same as in
5764 @cindex @code{setmem@var{m}} instruction pattern
5765 @item @samp{setmem@var{m}}
5766 Block set instruction. The destination string is the first operand,
5767 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5768 number of bytes to set is the second operand, in mode @var{m}. The value to
5769 initialize the memory with is the third operand. Targets that only support the
5770 clearing of memory should reject any value that is not the constant 0. See
5771 @samp{movmem@var{m}} for a discussion of the choice of mode.
5773 The fourth operand is the known alignment of the destination, in the form
5774 of a @code{const_int} rtx. Thus, if the compiler knows that the
5775 destination is word-aligned, it may provide the value 4 for this
5778 Optional operands 5 and 6 specify expected alignment and size of block
5779 respectively. The expected alignment differs from alignment in operand 4
5780 in a way that the blocks are not required to be aligned according to it in
5781 all cases. This expected alignment is also in bytes, just like operand 4.
5782 Expected size, when unknown, is set to @code{(const_int -1)}.
5783 Operand 7 is the minimal size of the block and operand 8 is the
5784 maximal size of the block (NULL if it can not be represented as CONST_INT).
5785 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5786 but it can be used for choosing proper code sequence for a given size).
5788 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5790 @cindex @code{cmpstrn@var{m}} instruction pattern
5791 @item @samp{cmpstrn@var{m}}
5792 String compare instruction, with five operands. Operand 0 is the output;
5793 it has mode @var{m}. The remaining four operands are like the operands
5794 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5795 byte by byte in lexicographic order starting at the beginning of each
5796 string. The instruction is not allowed to prefetch more than one byte
5797 at a time since either string may end in the first byte and reading past
5798 that may access an invalid page or segment and cause a fault. The
5799 comparison terminates early if the fetched bytes are different or if
5800 they are equal to zero. The effect of the instruction is to store a
5801 value in operand 0 whose sign indicates the result of the comparison.
5803 @cindex @code{cmpstr@var{m}} instruction pattern
5804 @item @samp{cmpstr@var{m}}
5805 String compare instruction, without known maximum length. Operand 0 is the
5806 output; it has mode @var{m}. The second and third operand are the blocks of
5807 memory to be compared; both are @code{mem:BLK} with an address in mode
5810 The fourth operand is the known shared alignment of the source and
5811 destination, in the form of a @code{const_int} rtx. Thus, if the
5812 compiler knows that both source and destination are word-aligned,
5813 it may provide the value 4 for this operand.
5815 The two memory blocks specified are compared byte by byte in lexicographic
5816 order starting at the beginning of each string. The instruction is not allowed
5817 to prefetch more than one byte at a time since either string may end in the
5818 first byte and reading past that may access an invalid page or segment and
5819 cause a fault. The comparison will terminate when the fetched bytes
5820 are different or if they are equal to zero. The effect of the
5821 instruction is to store a value in operand 0 whose sign indicates the
5822 result of the comparison.
5824 @cindex @code{cmpmem@var{m}} instruction pattern
5825 @item @samp{cmpmem@var{m}}
5826 Block compare instruction, with five operands like the operands
5827 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5828 byte by byte in lexicographic order starting at the beginning of each
5829 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5830 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5831 the comparison will not stop if both bytes are zero. The effect of
5832 the instruction is to store a value in operand 0 whose sign indicates
5833 the result of the comparison.
5835 @cindex @code{strlen@var{m}} instruction pattern
5836 @item @samp{strlen@var{m}}
5837 Compute the length of a string, with three operands.
5838 Operand 0 is the result (of mode @var{m}), operand 1 is
5839 a @code{mem} referring to the first character of the string,
5840 operand 2 is the character to search for (normally zero),
5841 and operand 3 is a constant describing the known alignment
5842 of the beginning of the string.
5844 @cindex @code{float@var{m}@var{n}2} instruction pattern
5845 @item @samp{float@var{m}@var{n}2}
5846 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5847 floating point mode @var{n} and store in operand 0 (which has mode
5850 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5851 @item @samp{floatuns@var{m}@var{n}2}
5852 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5853 to floating point mode @var{n} and store in operand 0 (which has mode
5856 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5857 @item @samp{fix@var{m}@var{n}2}
5858 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5859 point mode @var{n} as a signed number and store in operand 0 (which
5860 has mode @var{n}). This instruction's result is defined only when
5861 the value of operand 1 is an integer.
5863 If the machine description defines this pattern, it also needs to
5864 define the @code{ftrunc} pattern.
5866 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5867 @item @samp{fixuns@var{m}@var{n}2}
5868 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5869 point mode @var{n} as an unsigned number and store in operand 0 (which
5870 has mode @var{n}). This instruction's result is defined only when the
5871 value of operand 1 is an integer.
5873 @cindex @code{ftrunc@var{m}2} instruction pattern
5874 @item @samp{ftrunc@var{m}2}
5875 Convert operand 1 (valid for floating point mode @var{m}) to an
5876 integer value, still represented in floating point mode @var{m}, and
5877 store it in operand 0 (valid for floating point mode @var{m}).
5879 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5880 @item @samp{fix_trunc@var{m}@var{n}2}
5881 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5882 of mode @var{m} by converting the value to an integer.
5884 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5885 @item @samp{fixuns_trunc@var{m}@var{n}2}
5886 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5887 value of mode @var{m} by converting the value to an integer.
5889 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5890 @item @samp{trunc@var{m}@var{n}2}
5891 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5892 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5893 point or both floating point.
5895 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5896 @item @samp{extend@var{m}@var{n}2}
5897 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5898 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5899 point or both floating point.
5901 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5902 @item @samp{zero_extend@var{m}@var{n}2}
5903 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5904 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5907 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5908 @item @samp{fract@var{m}@var{n}2}
5909 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5910 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5911 could be fixed-point to fixed-point, signed integer to fixed-point,
5912 fixed-point to signed integer, floating-point to fixed-point,
5913 or fixed-point to floating-point.
5914 When overflows or underflows happen, the results are undefined.
5916 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5917 @item @samp{satfract@var{m}@var{n}2}
5918 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5919 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5920 could be fixed-point to fixed-point, signed integer to fixed-point,
5921 or floating-point to fixed-point.
5922 When overflows or underflows happen, the instruction saturates the
5923 results to the maximum or the minimum.
5925 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5926 @item @samp{fractuns@var{m}@var{n}2}
5927 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5928 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5929 could be unsigned integer to fixed-point, or
5930 fixed-point to unsigned integer.
5931 When overflows or underflows happen, the results are undefined.
5933 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5934 @item @samp{satfractuns@var{m}@var{n}2}
5935 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5936 @var{n} and store in operand 0 (which has mode @var{n}).
5937 When overflows or underflows happen, the instruction saturates the
5938 results to the maximum or the minimum.
5940 @cindex @code{extv@var{m}} instruction pattern
5941 @item @samp{extv@var{m}}
5942 Extract a bit-field from register operand 1, sign-extend it, and store
5943 it in operand 0. Operand 2 specifies the width of the field in bits
5944 and operand 3 the starting bit, which counts from the most significant
5945 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5948 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5949 target-specific mode.
5951 @cindex @code{extvmisalign@var{m}} instruction pattern
5952 @item @samp{extvmisalign@var{m}}
5953 Extract a bit-field from memory operand 1, sign extend it, and store
5954 it in operand 0. Operand 2 specifies the width in bits and operand 3
5955 the starting bit. The starting bit is always somewhere in the first byte of
5956 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5957 is true and from the least significant bit otherwise.
5959 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5960 Operands 2 and 3 have a target-specific mode.
5962 The instruction must not read beyond the last byte of the bit-field.
5964 @cindex @code{extzv@var{m}} instruction pattern
5965 @item @samp{extzv@var{m}}
5966 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5968 @cindex @code{extzvmisalign@var{m}} instruction pattern
5969 @item @samp{extzvmisalign@var{m}}
5970 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5973 @cindex @code{insv@var{m}} instruction pattern
5974 @item @samp{insv@var{m}}
5975 Insert operand 3 into a bit-field of register operand 0. Operand 1
5976 specifies the width of the field in bits and operand 2 the starting bit,
5977 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5978 is true and from the least significant bit otherwise.
5980 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5981 target-specific mode.
5983 @cindex @code{insvmisalign@var{m}} instruction pattern
5984 @item @samp{insvmisalign@var{m}}
5985 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5986 specifies the width of the field in bits and operand 2 the starting bit.
5987 The starting bit is always somewhere in the first byte of operand 0;
5988 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5989 is true and from the least significant bit otherwise.
5991 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5992 Operands 1 and 2 have a target-specific mode.
5994 The instruction must not read or write beyond the last byte of the bit-field.
5996 @cindex @code{extv} instruction pattern
5998 Extract a bit-field from operand 1 (a register or memory operand), where
5999 operand 2 specifies the width in bits and operand 3 the starting bit,
6000 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
6001 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
6002 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
6003 be valid for @code{word_mode}.
6005 The RTL generation pass generates this instruction only with constants
6006 for operands 2 and 3 and the constant is never zero for operand 2.
6008 The bit-field value is sign-extended to a full word integer
6009 before it is stored in operand 0.
6011 This pattern is deprecated; please use @samp{extv@var{m}} and
6012 @code{extvmisalign@var{m}} instead.
6014 @cindex @code{extzv} instruction pattern
6016 Like @samp{extv} except that the bit-field value is zero-extended.
6018 This pattern is deprecated; please use @samp{extzv@var{m}} and
6019 @code{extzvmisalign@var{m}} instead.
6021 @cindex @code{insv} instruction pattern
6023 Store operand 3 (which must be valid for @code{word_mode}) into a
6024 bit-field in operand 0, where operand 1 specifies the width in bits and
6025 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
6026 @code{word_mode}; often @code{word_mode} is allowed only for registers.
6027 Operands 1 and 2 must be valid for @code{word_mode}.
6029 The RTL generation pass generates this instruction only with constants
6030 for operands 1 and 2 and the constant is never zero for operand 1.
6032 This pattern is deprecated; please use @samp{insv@var{m}} and
6033 @code{insvmisalign@var{m}} instead.
6035 @cindex @code{mov@var{mode}cc} instruction pattern
6036 @item @samp{mov@var{mode}cc}
6037 Conditionally move operand 2 or operand 3 into operand 0 according to the
6038 comparison in operand 1. If the comparison is true, operand 2 is moved
6039 into operand 0, otherwise operand 3 is moved.
6041 The mode of the operands being compared need not be the same as the operands
6042 being moved. Some machines, sparc64 for example, have instructions that
6043 conditionally move an integer value based on the floating point condition
6044 codes and vice versa.
6046 If the machine does not have conditional move instructions, do not
6047 define these patterns.
6049 @cindex @code{add@var{mode}cc} instruction pattern
6050 @item @samp{add@var{mode}cc}
6051 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
6052 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
6053 comparison in operand 1. If the comparison is false, operand 2 is moved into
6054 operand 0, otherwise (operand 2 + operand 3) is moved.
6056 @cindex @code{neg@var{mode}cc} instruction pattern
6057 @item @samp{neg@var{mode}cc}
6058 Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally
6059 move the negation of operand 2 or the unchanged operand 3 into operand 0
6060 according to the comparison in operand 1. If the comparison is true, the negation
6061 of operand 2 is moved into operand 0, otherwise operand 3 is moved.
6063 @cindex @code{not@var{mode}cc} instruction pattern
6064 @item @samp{not@var{mode}cc}
6065 Similar to @samp{neg@var{mode}cc} but for conditional complement.
6066 Conditionally move the bitwise complement of operand 2 or the unchanged
6067 operand 3 into operand 0 according to the comparison in operand 1.
6068 If the comparison is true, the complement of operand 2 is moved into
6069 operand 0, otherwise operand 3 is moved.
6071 @cindex @code{cstore@var{mode}4} instruction pattern
6072 @item @samp{cstore@var{mode}4}
6073 Store zero or nonzero in operand 0 according to whether a comparison
6074 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
6075 are the first and second operand of the comparison, respectively.
6076 You specify the mode that operand 0 must have when you write the
6077 @code{match_operand} expression. The compiler automatically sees which
6078 mode you have used and supplies an operand of that mode.
6080 The value stored for a true condition must have 1 as its low bit, or
6081 else must be negative. Otherwise the instruction is not suitable and
6082 you should omit it from the machine description. You describe to the
6083 compiler exactly which value is stored by defining the macro
6084 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
6085 found that can be used for all the possible comparison operators, you
6086 should pick one and use a @code{define_expand} to map all results
6087 onto the one you chose.
6089 These operations may @code{FAIL}, but should do so only in relatively
6090 uncommon cases; if they would @code{FAIL} for common cases involving
6091 integer comparisons, it is best to restrict the predicates to not
6092 allow these operands. Likewise if a given comparison operator will
6093 always fail, independent of the operands (for floating-point modes, the
6094 @code{ordered_comparison_operator} predicate is often useful in this case).
6096 If this pattern is omitted, the compiler will generate a conditional
6097 branch---for example, it may copy a constant one to the target and branching
6098 around an assignment of zero to the target---or a libcall. If the predicate
6099 for operand 1 only rejects some operators, it will also try reordering the
6100 operands and/or inverting the result value (e.g.@: by an exclusive OR).
6101 These possibilities could be cheaper or equivalent to the instructions
6102 used for the @samp{cstore@var{mode}4} pattern followed by those required
6103 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
6104 case, you can and should make operand 1's predicate reject some operators
6105 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
6106 from the machine description.
6108 @cindex @code{cbranch@var{mode}4} instruction pattern
6109 @item @samp{cbranch@var{mode}4}
6110 Conditional branch instruction combined with a compare instruction.
6111 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
6112 first and second operands of the comparison, respectively. Operand 3
6113 is the @code{code_label} to jump to.
6115 @cindex @code{jump} instruction pattern
6117 A jump inside a function; an unconditional branch. Operand 0 is the
6118 @code{code_label} to jump to. This pattern name is mandatory on all
6121 @cindex @code{call} instruction pattern
6123 Subroutine call instruction returning no value. Operand 0 is the
6124 function to call; operand 1 is the number of bytes of arguments pushed
6125 as a @code{const_int}; operand 2 is the number of registers used as
6128 On most machines, operand 2 is not actually stored into the RTL
6129 pattern. It is supplied for the sake of some RISC machines which need
6130 to put this information into the assembler code; they can put it in
6131 the RTL instead of operand 1.
6133 Operand 0 should be a @code{mem} RTX whose address is the address of the
6134 function. Note, however, that this address can be a @code{symbol_ref}
6135 expression even if it would not be a legitimate memory address on the
6136 target machine. If it is also not a valid argument for a call
6137 instruction, the pattern for this operation should be a
6138 @code{define_expand} (@pxref{Expander Definitions}) that places the
6139 address into a register and uses that register in the call instruction.
6141 @cindex @code{call_value} instruction pattern
6142 @item @samp{call_value}
6143 Subroutine call instruction returning a value. Operand 0 is the hard
6144 register in which the value is returned. There are three more
6145 operands, the same as the three operands of the @samp{call}
6146 instruction (but with numbers increased by one).
6148 Subroutines that return @code{BLKmode} objects use the @samp{call}
6151 @cindex @code{call_pop} instruction pattern
6152 @cindex @code{call_value_pop} instruction pattern
6153 @item @samp{call_pop}, @samp{call_value_pop}
6154 Similar to @samp{call} and @samp{call_value}, except used if defined and
6155 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
6156 that contains both the function call and a @code{set} to indicate the
6157 adjustment made to the frame pointer.
6159 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
6160 patterns increases the number of functions for which the frame pointer
6161 can be eliminated, if desired.
6163 @cindex @code{untyped_call} instruction pattern
6164 @item @samp{untyped_call}
6165 Subroutine call instruction returning a value of any type. Operand 0 is
6166 the function to call; operand 1 is a memory location where the result of
6167 calling the function is to be stored; operand 2 is a @code{parallel}
6168 expression where each element is a @code{set} expression that indicates
6169 the saving of a function return value into the result block.
6171 This instruction pattern should be defined to support
6172 @code{__builtin_apply} on machines where special instructions are needed
6173 to call a subroutine with arbitrary arguments or to save the value
6174 returned. This instruction pattern is required on machines that have
6175 multiple registers that can hold a return value
6176 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
6178 @cindex @code{return} instruction pattern
6180 Subroutine return instruction. This instruction pattern name should be
6181 defined only if a single instruction can do all the work of returning
6184 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
6185 RTL generation phase. In this case it is to support machines where
6186 multiple instructions are usually needed to return from a function, but
6187 some class of functions only requires one instruction to implement a
6188 return. Normally, the applicable functions are those which do not need
6189 to save any registers or allocate stack space.
6191 It is valid for this pattern to expand to an instruction using
6192 @code{simple_return} if no epilogue is required.
6194 @cindex @code{simple_return} instruction pattern
6195 @item @samp{simple_return}
6196 Subroutine return instruction. This instruction pattern name should be
6197 defined only if a single instruction can do all the work of returning
6198 from a function on a path where no epilogue is required. This pattern
6199 is very similar to the @code{return} instruction pattern, but it is emitted
6200 only by the shrink-wrapping optimization on paths where the function
6201 prologue has not been executed, and a function return should occur without
6202 any of the effects of the epilogue. Additional uses may be introduced on
6203 paths where both the prologue and the epilogue have executed.
6205 @findex reload_completed
6206 @findex leaf_function_p
6207 For such machines, the condition specified in this pattern should only
6208 be true when @code{reload_completed} is nonzero and the function's
6209 epilogue would only be a single instruction. For machines with register
6210 windows, the routine @code{leaf_function_p} may be used to determine if
6211 a register window push is required.
6213 Machines that have conditional return instructions should define patterns
6219 (if_then_else (match_operator
6220 0 "comparison_operator"
6221 [(cc0) (const_int 0)])
6228 where @var{condition} would normally be the same condition specified on the
6229 named @samp{return} pattern.
6231 @cindex @code{untyped_return} instruction pattern
6232 @item @samp{untyped_return}
6233 Untyped subroutine return instruction. This instruction pattern should
6234 be defined to support @code{__builtin_return} on machines where special
6235 instructions are needed to return a value of any type.
6237 Operand 0 is a memory location where the result of calling a function
6238 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
6239 expression where each element is a @code{set} expression that indicates
6240 the restoring of a function return value from the result block.
6242 @cindex @code{nop} instruction pattern
6244 No-op instruction. This instruction pattern name should always be defined
6245 to output a no-op in assembler code. @code{(const_int 0)} will do as an
6248 @cindex @code{indirect_jump} instruction pattern
6249 @item @samp{indirect_jump}
6250 An instruction to jump to an address which is operand zero.
6251 This pattern name is mandatory on all machines.
6253 @cindex @code{casesi} instruction pattern
6255 Instruction to jump through a dispatch table, including bounds checking.
6256 This instruction takes five operands:
6260 The index to dispatch on, which has mode @code{SImode}.
6263 The lower bound for indices in the table, an integer constant.
6266 The total range of indices in the table---the largest index
6267 minus the smallest one (both inclusive).
6270 A label that precedes the table itself.
6273 A label to jump to if the index has a value outside the bounds.
6276 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
6277 @code{jump_table_data}. The number of elements in the table is one plus the
6278 difference between the upper bound and the lower bound.
6280 @cindex @code{tablejump} instruction pattern
6281 @item @samp{tablejump}
6282 Instruction to jump to a variable address. This is a low-level
6283 capability which can be used to implement a dispatch table when there
6284 is no @samp{casesi} pattern.
6286 This pattern requires two operands: the address or offset, and a label
6287 which should immediately precede the jump table. If the macro
6288 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
6289 operand is an offset which counts from the address of the table; otherwise,
6290 it is an absolute address to jump to. In either case, the first operand has
6293 The @samp{tablejump} insn is always the last insn before the jump
6294 table it uses. Its assembler code normally has no need to use the
6295 second operand, but you should incorporate it in the RTL pattern so
6296 that the jump optimizer will not delete the table as unreachable code.
6299 @cindex @code{decrement_and_branch_until_zero} instruction pattern
6300 @item @samp{decrement_and_branch_until_zero}
6301 Conditional branch instruction that decrements a register and
6302 jumps if the register is nonzero. Operand 0 is the register to
6303 decrement and test; operand 1 is the label to jump to if the
6304 register is nonzero. @xref{Looping Patterns}.
6306 This optional instruction pattern is only used by the combiner,
6307 typically for loops reversed by the loop optimizer when strength
6308 reduction is enabled.
6310 @cindex @code{doloop_end} instruction pattern
6311 @item @samp{doloop_end}
6312 Conditional branch instruction that decrements a register and
6313 jumps if the register is nonzero. Operand 0 is the register to
6314 decrement and test; operand 1 is the label to jump to if the
6315 register is nonzero.
6316 @xref{Looping Patterns}.
6318 This optional instruction pattern should be defined for machines with
6319 low-overhead looping instructions as the loop optimizer will try to
6320 modify suitable loops to utilize it. The target hook
6321 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
6322 low-overhead loops can be used.
6324 @cindex @code{doloop_begin} instruction pattern
6325 @item @samp{doloop_begin}
6326 Companion instruction to @code{doloop_end} required for machines that
6327 need to perform some initialization, such as loading a special counter
6328 register. Operand 1 is the associated @code{doloop_end} pattern and
6329 operand 0 is the register that it decrements.
6331 If initialization insns do not always need to be emitted, use a
6332 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
6334 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
6335 @item @samp{canonicalize_funcptr_for_compare}
6336 Canonicalize the function pointer in operand 1 and store the result
6339 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
6340 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
6341 and also has mode @code{Pmode}.
6343 Canonicalization of a function pointer usually involves computing
6344 the address of the function which would be called if the function
6345 pointer were used in an indirect call.
6347 Only define this pattern if function pointers on the target machine
6348 can have different values but still call the same function when
6349 used in an indirect call.
6351 @cindex @code{save_stack_block} instruction pattern
6352 @cindex @code{save_stack_function} instruction pattern
6353 @cindex @code{save_stack_nonlocal} instruction pattern
6354 @cindex @code{restore_stack_block} instruction pattern
6355 @cindex @code{restore_stack_function} instruction pattern
6356 @cindex @code{restore_stack_nonlocal} instruction pattern
6357 @item @samp{save_stack_block}
6358 @itemx @samp{save_stack_function}
6359 @itemx @samp{save_stack_nonlocal}
6360 @itemx @samp{restore_stack_block}
6361 @itemx @samp{restore_stack_function}
6362 @itemx @samp{restore_stack_nonlocal}
6363 Most machines save and restore the stack pointer by copying it to or
6364 from an object of mode @code{Pmode}. Do not define these patterns on
6367 Some machines require special handling for stack pointer saves and
6368 restores. On those machines, define the patterns corresponding to the
6369 non-standard cases by using a @code{define_expand} (@pxref{Expander
6370 Definitions}) that produces the required insns. The three types of
6371 saves and restores are:
6375 @samp{save_stack_block} saves the stack pointer at the start of a block
6376 that allocates a variable-sized object, and @samp{restore_stack_block}
6377 restores the stack pointer when the block is exited.
6380 @samp{save_stack_function} and @samp{restore_stack_function} do a
6381 similar job for the outermost block of a function and are used when the
6382 function allocates variable-sized objects or calls @code{alloca}. Only
6383 the epilogue uses the restored stack pointer, allowing a simpler save or
6384 restore sequence on some machines.
6387 @samp{save_stack_nonlocal} is used in functions that contain labels
6388 branched to by nested functions. It saves the stack pointer in such a
6389 way that the inner function can use @samp{restore_stack_nonlocal} to
6390 restore the stack pointer. The compiler generates code to restore the
6391 frame and argument pointer registers, but some machines require saving
6392 and restoring additional data such as register window information or
6393 stack backchains. Place insns in these patterns to save and restore any
6397 When saving the stack pointer, operand 0 is the save area and operand 1
6398 is the stack pointer. The mode used to allocate the save area defaults
6399 to @code{Pmode} but you can override that choice by defining the
6400 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6401 specify an integral mode, or @code{VOIDmode} if no save area is needed
6402 for a particular type of save (either because no save is needed or
6403 because a machine-specific save area can be used). Operand 0 is the
6404 stack pointer and operand 1 is the save area for restore operations. If
6405 @samp{save_stack_block} is defined, operand 0 must not be
6406 @code{VOIDmode} since these saves can be arbitrarily nested.
6408 A save area is a @code{mem} that is at a constant offset from
6409 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6410 nonlocal gotos and a @code{reg} in the other two cases.
6412 @cindex @code{allocate_stack} instruction pattern
6413 @item @samp{allocate_stack}
6414 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6415 the stack pointer to create space for dynamically allocated data.
6417 Store the resultant pointer to this space into operand 0. If you
6418 are allocating space from the main stack, do this by emitting a
6419 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6420 If you are allocating the space elsewhere, generate code to copy the
6421 location of the space to operand 0. In the latter case, you must
6422 ensure this space gets freed when the corresponding space on the main
6425 Do not define this pattern if all that must be done is the subtraction.
6426 Some machines require other operations such as stack probes or
6427 maintaining the back chain. Define this pattern to emit those
6428 operations in addition to updating the stack pointer.
6430 @cindex @code{check_stack} instruction pattern
6431 @item @samp{check_stack}
6432 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6433 probing the stack, define this pattern to perform the needed check and signal
6434 an error if the stack has overflowed. The single operand is the address in
6435 the stack farthest from the current stack pointer that you need to validate.
6436 Normally, on platforms where this pattern is needed, you would obtain the
6437 stack limit from a global or thread-specific variable or register.
6439 @cindex @code{probe_stack_address} instruction pattern
6440 @item @samp{probe_stack_address}
6441 If stack checking (@pxref{Stack Checking}) can be done on your system by
6442 probing the stack but without the need to actually access it, define this
6443 pattern and signal an error if the stack has overflowed. The single operand
6444 is the memory address in the stack that needs to be probed.
6446 @cindex @code{probe_stack} instruction pattern
6447 @item @samp{probe_stack}
6448 If stack checking (@pxref{Stack Checking}) can be done on your system by
6449 probing the stack but doing it with a ``store zero'' instruction is not valid
6450 or optimal, define this pattern to do the probing differently and signal an
6451 error if the stack has overflowed. The single operand is the memory reference
6452 in the stack that needs to be probed.
6454 @cindex @code{nonlocal_goto} instruction pattern
6455 @item @samp{nonlocal_goto}
6456 Emit code to generate a non-local goto, e.g., a jump from one function
6457 to a label in an outer function. This pattern has four arguments,
6458 each representing a value to be used in the jump. The first
6459 argument is to be loaded into the frame pointer, the second is
6460 the address to branch to (code to dispatch to the actual label),
6461 the third is the address of a location where the stack is saved,
6462 and the last is the address of the label, to be placed in the
6463 location for the incoming static chain.
6465 On most machines you need not define this pattern, since GCC will
6466 already generate the correct code, which is to load the frame pointer
6467 and static chain, restore the stack (using the
6468 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6469 to the dispatcher. You need only define this pattern if this code will
6470 not work on your machine.
6472 @cindex @code{nonlocal_goto_receiver} instruction pattern
6473 @item @samp{nonlocal_goto_receiver}
6474 This pattern, if defined, contains code needed at the target of a
6475 nonlocal goto after the code already generated by GCC@. You will not
6476 normally need to define this pattern. A typical reason why you might
6477 need this pattern is if some value, such as a pointer to a global table,
6478 must be restored when the frame pointer is restored. Note that a nonlocal
6479 goto only occurs within a unit-of-translation, so a global table pointer
6480 that is shared by all functions of a given module need not be restored.
6481 There are no arguments.
6483 @cindex @code{exception_receiver} instruction pattern
6484 @item @samp{exception_receiver}
6485 This pattern, if defined, contains code needed at the site of an
6486 exception handler that isn't needed at the site of a nonlocal goto. You
6487 will not normally need to define this pattern. A typical reason why you
6488 might need this pattern is if some value, such as a pointer to a global
6489 table, must be restored after control flow is branched to the handler of
6490 an exception. There are no arguments.
6492 @cindex @code{builtin_setjmp_setup} instruction pattern
6493 @item @samp{builtin_setjmp_setup}
6494 This pattern, if defined, contains additional code needed to initialize
6495 the @code{jmp_buf}. You will not normally need to define this pattern.
6496 A typical reason why you might need this pattern is if some value, such
6497 as a pointer to a global table, must be restored. Though it is
6498 preferred that the pointer value be recalculated if possible (given the
6499 address of a label for instance). The single argument is a pointer to
6500 the @code{jmp_buf}. Note that the buffer is five words long and that
6501 the first three are normally used by the generic mechanism.
6503 @cindex @code{builtin_setjmp_receiver} instruction pattern
6504 @item @samp{builtin_setjmp_receiver}
6505 This pattern, if defined, contains code needed at the site of a
6506 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6507 will not normally need to define this pattern. A typical reason why you
6508 might need this pattern is if some value, such as a pointer to a global
6509 table, must be restored. It takes one argument, which is the label
6510 to which builtin_longjmp transferred control; this pattern may be emitted
6511 at a small offset from that label.
6513 @cindex @code{builtin_longjmp} instruction pattern
6514 @item @samp{builtin_longjmp}
6515 This pattern, if defined, performs the entire action of the longjmp.
6516 You will not normally need to define this pattern unless you also define
6517 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6520 @cindex @code{eh_return} instruction pattern
6521 @item @samp{eh_return}
6522 This pattern, if defined, affects the way @code{__builtin_eh_return},
6523 and thence the call frame exception handling library routines, are
6524 built. It is intended to handle non-trivial actions needed along
6525 the abnormal return path.
6527 The address of the exception handler to which the function should return
6528 is passed as operand to this pattern. It will normally need to copied by
6529 the pattern to some special register or memory location.
6530 If the pattern needs to determine the location of the target call
6531 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6532 if defined; it will have already been assigned.
6534 If this pattern is not defined, the default action will be to simply
6535 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6536 that macro or this pattern needs to be defined if call frame exception
6537 handling is to be used.
6539 @cindex @code{prologue} instruction pattern
6540 @anchor{prologue instruction pattern}
6541 @item @samp{prologue}
6542 This pattern, if defined, emits RTL for entry to a function. The function
6543 entry is responsible for setting up the stack frame, initializing the frame
6544 pointer register, saving callee saved registers, etc.
6546 Using a prologue pattern is generally preferred over defining
6547 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6549 The @code{prologue} pattern is particularly useful for targets which perform
6550 instruction scheduling.
6552 @cindex @code{window_save} instruction pattern
6553 @anchor{window_save instruction pattern}
6554 @item @samp{window_save}
6555 This pattern, if defined, emits RTL for a register window save. It should
6556 be defined if the target machine has register windows but the window events
6557 are decoupled from calls to subroutines. The canonical example is the SPARC
6560 @cindex @code{epilogue} instruction pattern
6561 @anchor{epilogue instruction pattern}
6562 @item @samp{epilogue}
6563 This pattern emits RTL for exit from a function. The function
6564 exit is responsible for deallocating the stack frame, restoring callee saved
6565 registers and emitting the return instruction.
6567 Using an epilogue pattern is generally preferred over defining
6568 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6570 The @code{epilogue} pattern is particularly useful for targets which perform
6571 instruction scheduling or which have delay slots for their return instruction.
6573 @cindex @code{sibcall_epilogue} instruction pattern
6574 @item @samp{sibcall_epilogue}
6575 This pattern, if defined, emits RTL for exit from a function without the final
6576 branch back to the calling function. This pattern will be emitted before any
6577 sibling call (aka tail call) sites.
6579 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6580 parameter passing or any stack slots for arguments passed to the current
6583 @cindex @code{trap} instruction pattern
6585 This pattern, if defined, signals an error, typically by causing some
6586 kind of signal to be raised. Among other places, it is used by the Java
6587 front end to signal `invalid array index' exceptions.
6589 @cindex @code{ctrap@var{MM}4} instruction pattern
6590 @item @samp{ctrap@var{MM}4}
6591 Conditional trap instruction. Operand 0 is a piece of RTL which
6592 performs a comparison, and operands 1 and 2 are the arms of the
6593 comparison. Operand 3 is the trap code, an integer.
6595 A typical @code{ctrap} pattern looks like
6598 (define_insn "ctrapsi4"
6599 [(trap_if (match_operator 0 "trap_operator"
6600 [(match_operand 1 "register_operand")
6601 (match_operand 2 "immediate_operand")])
6602 (match_operand 3 "const_int_operand" "i"))]
6607 @cindex @code{prefetch} instruction pattern
6608 @item @samp{prefetch}
6609 This pattern, if defined, emits code for a non-faulting data prefetch
6610 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6611 is a constant 1 if the prefetch is preparing for a write to the memory
6612 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6613 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6614 means that the data has no temporal locality, so it need not be left in the
6615 cache after the access; 3 means that the data has a high degree of temporal
6616 locality and should be left in all levels of cache possible; 1 and 2 mean,
6617 respectively, a low or moderate degree of temporal locality.
6619 Targets that do not support write prefetches or locality hints can ignore
6620 the values of operands 1 and 2.
6622 @cindex @code{blockage} instruction pattern
6623 @item @samp{blockage}
6624 This pattern defines a pseudo insn that prevents the instruction
6625 scheduler and other passes from moving instructions and using register
6626 equivalences across the boundary defined by the blockage insn.
6627 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6629 @cindex @code{memory_barrier} instruction pattern
6630 @item @samp{memory_barrier}
6631 If the target memory model is not fully synchronous, then this pattern
6632 should be defined to an instruction that orders both loads and stores
6633 before the instruction with respect to loads and stores after the instruction.
6634 This pattern has no operands.
6636 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6637 @item @samp{sync_compare_and_swap@var{mode}}
6638 This pattern, if defined, emits code for an atomic compare-and-swap
6639 operation. Operand 1 is the memory on which the atomic operation is
6640 performed. Operand 2 is the ``old'' value to be compared against the
6641 current contents of the memory location. Operand 3 is the ``new'' value
6642 to store in the memory if the compare succeeds. Operand 0 is the result
6643 of the operation; it should contain the contents of the memory
6644 before the operation. If the compare succeeds, this should obviously be
6645 a copy of operand 2.
6647 This pattern must show that both operand 0 and operand 1 are modified.
6649 This pattern must issue any memory barrier instructions such that all
6650 memory operations before the atomic operation occur before the atomic
6651 operation and all memory operations after the atomic operation occur
6652 after the atomic operation.
6654 For targets where the success or failure of the compare-and-swap
6655 operation is available via the status flags, it is possible to
6656 avoid a separate compare operation and issue the subsequent
6657 branch or store-flag operation immediately after the compare-and-swap.
6658 To this end, GCC will look for a @code{MODE_CC} set in the
6659 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6660 description includes such a set, the target should also define special
6661 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6662 be able to take the destination of the @code{MODE_CC} set and pass it
6663 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6664 operand of the comparison (the second will be @code{(const_int 0)}).
6666 For targets where the operating system may provide support for this
6667 operation via library calls, the @code{sync_compare_and_swap_optab}
6668 may be initialized to a function with the same interface as the
6669 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6670 set of @var{__sync} builtins are supported via library calls, the
6671 target can initialize all of the optabs at once with
6672 @code{init_sync_libfuncs}.
6673 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6674 assumed that these library calls do @emph{not} use any kind of
6675 interruptable locking.
6677 @cindex @code{sync_add@var{mode}} instruction pattern
6678 @cindex @code{sync_sub@var{mode}} instruction pattern
6679 @cindex @code{sync_ior@var{mode}} instruction pattern
6680 @cindex @code{sync_and@var{mode}} instruction pattern
6681 @cindex @code{sync_xor@var{mode}} instruction pattern
6682 @cindex @code{sync_nand@var{mode}} instruction pattern
6683 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6684 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6685 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6686 These patterns emit code for an atomic operation on memory.
6687 Operand 0 is the memory on which the atomic operation is performed.
6688 Operand 1 is the second operand to the binary operator.
6690 This pattern must issue any memory barrier instructions such that all
6691 memory operations before the atomic operation occur before the atomic
6692 operation and all memory operations after the atomic operation occur
6693 after the atomic operation.
6695 If these patterns are not defined, the operation will be constructed
6696 from a compare-and-swap operation, if defined.
6698 @cindex @code{sync_old_add@var{mode}} instruction pattern
6699 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6700 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6701 @cindex @code{sync_old_and@var{mode}} instruction pattern
6702 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6703 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6704 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6705 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6706 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6707 These patterns emit code for an atomic operation on memory,
6708 and return the value that the memory contained before the operation.
6709 Operand 0 is the result value, operand 1 is the memory on which the
6710 atomic operation is performed, and operand 2 is the second operand
6711 to the binary operator.
6713 This pattern must issue any memory barrier instructions such that all
6714 memory operations before the atomic operation occur before the atomic
6715 operation and all memory operations after the atomic operation occur
6716 after the atomic operation.
6718 If these patterns are not defined, the operation will be constructed
6719 from a compare-and-swap operation, if defined.
6721 @cindex @code{sync_new_add@var{mode}} instruction pattern
6722 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6723 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6724 @cindex @code{sync_new_and@var{mode}} instruction pattern
6725 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6726 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6727 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6728 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6729 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6730 These patterns are like their @code{sync_old_@var{op}} counterparts,
6731 except that they return the value that exists in the memory location
6732 after the operation, rather than before the operation.
6734 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6735 @item @samp{sync_lock_test_and_set@var{mode}}
6736 This pattern takes two forms, based on the capabilities of the target.
6737 In either case, operand 0 is the result of the operand, operand 1 is
6738 the memory on which the atomic operation is performed, and operand 2
6739 is the value to set in the lock.
6741 In the ideal case, this operation is an atomic exchange operation, in
6742 which the previous value in memory operand is copied into the result
6743 operand, and the value operand is stored in the memory operand.
6745 For less capable targets, any value operand that is not the constant 1
6746 should be rejected with @code{FAIL}. In this case the target may use
6747 an atomic test-and-set bit operation. The result operand should contain
6748 1 if the bit was previously set and 0 if the bit was previously clear.
6749 The true contents of the memory operand are implementation defined.
6751 This pattern must issue any memory barrier instructions such that the
6752 pattern as a whole acts as an acquire barrier, that is all memory
6753 operations after the pattern do not occur until the lock is acquired.
6755 If this pattern is not defined, the operation will be constructed from
6756 a compare-and-swap operation, if defined.
6758 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6759 @item @samp{sync_lock_release@var{mode}}
6760 This pattern, if defined, releases a lock set by
6761 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6762 that contains the lock; operand 1 is the value to store in the lock.
6764 If the target doesn't implement full semantics for
6765 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6766 the constant 0 should be rejected with @code{FAIL}, and the true contents
6767 of the memory operand are implementation defined.
6769 This pattern must issue any memory barrier instructions such that the
6770 pattern as a whole acts as a release barrier, that is the lock is
6771 released only after all previous memory operations have completed.
6773 If this pattern is not defined, then a @code{memory_barrier} pattern
6774 will be emitted, followed by a store of the value to the memory operand.
6776 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6777 @item @samp{atomic_compare_and_swap@var{mode}}
6778 This pattern, if defined, emits code for an atomic compare-and-swap
6779 operation with memory model semantics. Operand 2 is the memory on which
6780 the atomic operation is performed. Operand 0 is an output operand which
6781 is set to true or false based on whether the operation succeeded. Operand
6782 1 is an output operand which is set to the contents of the memory before
6783 the operation was attempted. Operand 3 is the value that is expected to
6784 be in memory. Operand 4 is the value to put in memory if the expected
6785 value is found there. Operand 5 is set to 1 if this compare and swap is to
6786 be treated as a weak operation. Operand 6 is the memory model to be used
6787 if the operation is a success. Operand 7 is the memory model to be used
6788 if the operation fails.
6790 If memory referred to in operand 2 contains the value in operand 3, then
6791 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6792 the memory model in operand 6 is issued.
6794 If memory referred to in operand 2 does not contain the value in operand 3,
6795 then fencing based on the memory model in operand 7 is issued.
6797 If a target does not support weak compare-and-swap operations, or the port
6798 elects not to implement weak operations, the argument in operand 5 can be
6799 ignored. Note a strong implementation must be provided.
6801 If this pattern is not provided, the @code{__atomic_compare_exchange}
6802 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6803 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6805 @cindex @code{atomic_load@var{mode}} instruction pattern
6806 @item @samp{atomic_load@var{mode}}
6807 This pattern implements an atomic load operation with memory model
6808 semantics. Operand 1 is the memory address being loaded from. Operand 0
6809 is the result of the load. Operand 2 is the memory model to be used for
6812 If not present, the @code{__atomic_load} built-in function will either
6813 resort to a normal load with memory barriers, or a compare-and-swap
6814 operation if a normal load would not be atomic.
6816 @cindex @code{atomic_store@var{mode}} instruction pattern
6817 @item @samp{atomic_store@var{mode}}
6818 This pattern implements an atomic store operation with memory model
6819 semantics. Operand 0 is the memory address being stored to. Operand 1
6820 is the value to be written. Operand 2 is the memory model to be used for
6823 If not present, the @code{__atomic_store} built-in function will attempt to
6824 perform a normal store and surround it with any required memory fences. If
6825 the store would not be atomic, then an @code{__atomic_exchange} is
6826 attempted with the result being ignored.
6828 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6829 @item @samp{atomic_exchange@var{mode}}
6830 This pattern implements an atomic exchange operation with memory model
6831 semantics. Operand 1 is the memory location the operation is performed on.
6832 Operand 0 is an output operand which is set to the original value contained
6833 in the memory pointed to by operand 1. Operand 2 is the value to be
6834 stored. Operand 3 is the memory model to be used.
6836 If this pattern is not present, the built-in function
6837 @code{__atomic_exchange} will attempt to preform the operation with a
6838 compare and swap loop.
6840 @cindex @code{atomic_add@var{mode}} instruction pattern
6841 @cindex @code{atomic_sub@var{mode}} instruction pattern
6842 @cindex @code{atomic_or@var{mode}} instruction pattern
6843 @cindex @code{atomic_and@var{mode}} instruction pattern
6844 @cindex @code{atomic_xor@var{mode}} instruction pattern
6845 @cindex @code{atomic_nand@var{mode}} instruction pattern
6846 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6847 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6848 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6849 These patterns emit code for an atomic operation on memory with memory
6850 model semantics. Operand 0 is the memory on which the atomic operation is
6851 performed. Operand 1 is the second operand to the binary operator.
6852 Operand 2 is the memory model to be used by the operation.
6854 If these patterns are not defined, attempts will be made to use legacy
6855 @code{sync} patterns, or equivalent patterns which return a result. If
6856 none of these are available a compare-and-swap loop will be used.
6858 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6859 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6860 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6861 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6862 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6863 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6864 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6865 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6866 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6867 These patterns emit code for an atomic operation on memory with memory
6868 model semantics, and return the original value. Operand 0 is an output
6869 operand which contains the value of the memory location before the
6870 operation was performed. Operand 1 is the memory on which the atomic
6871 operation is performed. Operand 2 is the second operand to the binary
6872 operator. Operand 3 is the memory model to be used by the operation.
6874 If these patterns are not defined, attempts will be made to use legacy
6875 @code{sync} patterns. If none of these are available a compare-and-swap
6878 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6879 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6880 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6881 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6882 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6883 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6884 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6885 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6886 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6887 These patterns emit code for an atomic operation on memory with memory
6888 model semantics and return the result after the operation is performed.
6889 Operand 0 is an output operand which contains the value after the
6890 operation. Operand 1 is the memory on which the atomic operation is
6891 performed. Operand 2 is the second operand to the binary operator.
6892 Operand 3 is the memory model to be used by the operation.
6894 If these patterns are not defined, attempts will be made to use legacy
6895 @code{sync} patterns, or equivalent patterns which return the result before
6896 the operation followed by the arithmetic operation required to produce the
6897 result. If none of these are available a compare-and-swap loop will be
6900 @cindex @code{atomic_test_and_set} instruction pattern
6901 @item @samp{atomic_test_and_set}
6902 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6903 Operand 0 is an output operand which is set to true if the previous
6904 previous contents of the byte was "set", and false otherwise. Operand 1
6905 is the @code{QImode} memory to be modified. Operand 2 is the memory
6908 The specific value that defines "set" is implementation defined, and
6909 is normally based on what is performed by the native atomic test and set
6912 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6913 @item @samp{mem_thread_fence@var{mode}}
6914 This pattern emits code required to implement a thread fence with
6915 memory model semantics. Operand 0 is the memory model to be used.
6917 If this pattern is not specified, all memory models except
6918 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6921 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6922 @item @samp{mem_signal_fence@var{mode}}
6923 This pattern emits code required to implement a signal fence with
6924 memory model semantics. Operand 0 is the memory model to be used.
6926 This pattern should impact the compiler optimizers the same way that
6927 mem_signal_fence does, but it does not need to issue any barrier
6930 If this pattern is not specified, all memory models except
6931 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6934 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6935 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6936 @item @samp{get_thread_pointer@var{mode}}
6937 @itemx @samp{set_thread_pointer@var{mode}}
6938 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6939 these are only needed if the target needs to support the
6940 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6943 The get/set patterns have a single output/input operand respectively,
6944 with @var{mode} intended to be @code{Pmode}.
6946 @cindex @code{stack_protect_set} instruction pattern
6947 @item @samp{stack_protect_set}
6948 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6949 in operand 1 to the memory in operand 0 without leaving the value in
6950 a register afterward. This is to avoid leaking the value some place
6951 that an attacker might use to rewrite the stack guard slot after
6952 having clobbered it.
6954 If this pattern is not defined, then a plain move pattern is generated.
6956 @cindex @code{stack_protect_test} instruction pattern
6957 @item @samp{stack_protect_test}
6958 This pattern, if defined, compares a @code{ptr_mode} value from the
6959 memory in operand 1 with the memory in operand 0 without leaving the
6960 value in a register afterward and branches to operand 2 if the values
6963 If this pattern is not defined, then a plain compare pattern and
6964 conditional branch pattern is used.
6966 @cindex @code{clear_cache} instruction pattern
6967 @item @samp{clear_cache}
6968 This pattern, if defined, flushes the instruction cache for a region of
6969 memory. The region is bounded to by the Pmode pointers in operand 0
6970 inclusive and operand 1 exclusive.
6972 If this pattern is not defined, a call to the library function
6973 @code{__clear_cache} is used.
6978 @c Each of the following nodes are wrapped in separate
6979 @c "@ifset INTERNALS" to work around memory limits for the default
6980 @c configuration in older tetex distributions. Known to not work:
6981 @c tetex-1.0.7, known to work: tetex-2.0.2.
6983 @node Pattern Ordering
6984 @section When the Order of Patterns Matters
6985 @cindex Pattern Ordering
6986 @cindex Ordering of Patterns
6988 Sometimes an insn can match more than one instruction pattern. Then the
6989 pattern that appears first in the machine description is the one used.
6990 Therefore, more specific patterns (patterns that will match fewer things)
6991 and faster instructions (those that will produce better code when they
6992 do match) should usually go first in the description.
6994 In some cases the effect of ordering the patterns can be used to hide
6995 a pattern when it is not valid. For example, the 68000 has an
6996 instruction for converting a fullword to floating point and another
6997 for converting a byte to floating point. An instruction converting
6998 an integer to floating point could match either one. We put the
6999 pattern to convert the fullword first to make sure that one will
7000 be used rather than the other. (Otherwise a large integer might
7001 be generated as a single-byte immediate quantity, which would not work.)
7002 Instead of using this pattern ordering it would be possible to make the
7003 pattern for convert-a-byte smart enough to deal properly with any
7008 @node Dependent Patterns
7009 @section Interdependence of Patterns
7010 @cindex Dependent Patterns
7011 @cindex Interdependence of Patterns
7013 In some cases machines support instructions identical except for the
7014 machine mode of one or more operands. For example, there may be
7015 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
7019 (set (match_operand:SI 0 @dots{})
7020 (extend:SI (match_operand:HI 1 @dots{})))
7022 (set (match_operand:SI 0 @dots{})
7023 (extend:SI (match_operand:QI 1 @dots{})))
7027 Constant integers do not specify a machine mode, so an instruction to
7028 extend a constant value could match either pattern. The pattern it
7029 actually will match is the one that appears first in the file. For correct
7030 results, this must be the one for the widest possible mode (@code{HImode},
7031 here). If the pattern matches the @code{QImode} instruction, the results
7032 will be incorrect if the constant value does not actually fit that mode.
7034 Such instructions to extend constants are rarely generated because they are
7035 optimized away, but they do occasionally happen in nonoptimized
7038 If a constraint in a pattern allows a constant, the reload pass may
7039 replace a register with a constant permitted by the constraint in some
7040 cases. Similarly for memory references. Because of this substitution,
7041 you should not provide separate patterns for increment and decrement
7042 instructions. Instead, they should be generated from the same pattern
7043 that supports register-register add insns by examining the operands and
7044 generating the appropriate machine instruction.
7049 @section Defining Jump Instruction Patterns
7050 @cindex jump instruction patterns
7051 @cindex defining jump instruction patterns
7053 GCC does not assume anything about how the machine realizes jumps.
7054 The machine description should define a single pattern, usually
7055 a @code{define_expand}, which expands to all the required insns.
7057 Usually, this would be a comparison insn to set the condition code
7058 and a separate branch insn testing the condition code and branching
7059 or not according to its value. For many machines, however,
7060 separating compares and branches is limiting, which is why the
7061 more flexible approach with one @code{define_expand} is used in GCC.
7062 The machine description becomes clearer for architectures that
7063 have compare-and-branch instructions but no condition code. It also
7064 works better when different sets of comparison operators are supported
7065 by different kinds of conditional branches (e.g. integer vs. floating-point),
7066 or by conditional branches with respect to conditional stores.
7068 Two separate insns are always used if the machine description represents
7069 a condition code register using the legacy RTL expression @code{(cc0)},
7070 and on most machines that use a separate condition code register
7071 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
7072 fact, the set and use of the condition code must be separate and
7073 adjacent@footnote{@code{note} insns can separate them, though.}, thus
7074 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
7075 so that the comparison and branch insns could be located from each other
7076 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
7078 Even in this case having a single entry point for conditional branches
7079 is advantageous, because it handles equally well the case where a single
7080 comparison instruction records the results of both signed and unsigned
7081 comparison of the given operands (with the branch insns coming in distinct
7082 signed and unsigned flavors) as in the x86 or SPARC, and the case where
7083 there are distinct signed and unsigned compare instructions and only
7084 one set of conditional branch instructions as in the PowerPC.
7088 @node Looping Patterns
7089 @section Defining Looping Instruction Patterns
7090 @cindex looping instruction patterns
7091 @cindex defining looping instruction patterns
7093 Some machines have special jump instructions that can be utilized to
7094 make loops more efficient. A common example is the 68000 @samp{dbra}
7095 instruction which performs a decrement of a register and a branch if the
7096 result was greater than zero. Other machines, in particular digital
7097 signal processors (DSPs), have special block repeat instructions to
7098 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
7099 DSPs have a block repeat instruction that loads special registers to
7100 mark the top and end of a loop and to count the number of loop
7101 iterations. This avoids the need for fetching and executing a
7102 @samp{dbra}-like instruction and avoids pipeline stalls associated with
7105 GCC has three special named patterns to support low overhead looping.
7106 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
7107 and @samp{doloop_end}. The first pattern,
7108 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
7109 generation but may be emitted during the instruction combination phase.
7110 This requires the assistance of the loop optimizer, using information
7111 collected during strength reduction, to reverse a loop to count down to
7112 zero. Some targets also require the loop optimizer to add a
7113 @code{REG_NONNEG} note to indicate that the iteration count is always
7114 positive. This is needed if the target performs a signed loop
7115 termination test. For example, the 68000 uses a pattern similar to the
7116 following for its @code{dbra} instruction:
7120 (define_insn "decrement_and_branch_until_zero"
7123 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
7126 (label_ref (match_operand 1 "" ""))
7129 (plus:SI (match_dup 0)
7131 "find_reg_note (insn, REG_NONNEG, 0)"
7136 Note that since the insn is both a jump insn and has an output, it must
7137 deal with its own reloads, hence the `m' constraints. Also note that
7138 since this insn is generated by the instruction combination phase
7139 combining two sequential insns together into an implicit parallel insn,
7140 the iteration counter needs to be biased by the same amount as the
7141 decrement operation, in this case @minus{}1. Note that the following similar
7142 pattern will not be matched by the combiner.
7146 (define_insn "decrement_and_branch_until_zero"
7149 (ge (match_operand:SI 0 "general_operand" "+d*am")
7151 (label_ref (match_operand 1 "" ""))
7154 (plus:SI (match_dup 0)
7156 "find_reg_note (insn, REG_NONNEG, 0)"
7161 The other two special looping patterns, @samp{doloop_begin} and
7162 @samp{doloop_end}, are emitted by the loop optimizer for certain
7163 well-behaved loops with a finite number of loop iterations using
7164 information collected during strength reduction.
7166 The @samp{doloop_end} pattern describes the actual looping instruction
7167 (or the implicit looping operation) and the @samp{doloop_begin} pattern
7168 is an optional companion pattern that can be used for initialization
7169 needed for some low-overhead looping instructions.
7171 Note that some machines require the actual looping instruction to be
7172 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
7173 the true RTL for a looping instruction at the top of the loop can cause
7174 problems with flow analysis. So instead, a dummy @code{doloop} insn is
7175 emitted at the end of the loop. The machine dependent reorg pass checks
7176 for the presence of this @code{doloop} insn and then searches back to
7177 the top of the loop, where it inserts the true looping insn (provided
7178 there are no instructions in the loop which would cause problems). Any
7179 additional labels can be emitted at this point. In addition, if the
7180 desired special iteration counter register was not allocated, this
7181 machine dependent reorg pass could emit a traditional compare and jump
7184 The essential difference between the
7185 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
7186 patterns is that the loop optimizer allocates an additional pseudo
7187 register for the latter as an iteration counter. This pseudo register
7188 cannot be used within the loop (i.e., general induction variables cannot
7189 be derived from it), however, in many cases the loop induction variable
7190 may become redundant and removed by the flow pass.
7195 @node Insn Canonicalizations
7196 @section Canonicalization of Instructions
7197 @cindex canonicalization of instructions
7198 @cindex insn canonicalization
7200 There are often cases where multiple RTL expressions could represent an
7201 operation performed by a single machine instruction. This situation is
7202 most commonly encountered with logical, branch, and multiply-accumulate
7203 instructions. In such cases, the compiler attempts to convert these
7204 multiple RTL expressions into a single canonical form to reduce the
7205 number of insn patterns required.
7207 In addition to algebraic simplifications, following canonicalizations
7212 For commutative and comparison operators, a constant is always made the
7213 second operand. If a machine only supports a constant as the second
7214 operand, only patterns that match a constant in the second operand need
7218 For associative operators, a sequence of operators will always chain
7219 to the left; for instance, only the left operand of an integer @code{plus}
7220 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
7221 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
7222 @code{umax} are associative when applied to integers, and sometimes to
7226 @cindex @code{neg}, canonicalization of
7227 @cindex @code{not}, canonicalization of
7228 @cindex @code{mult}, canonicalization of
7229 @cindex @code{plus}, canonicalization of
7230 @cindex @code{minus}, canonicalization of
7231 For these operators, if only one operand is a @code{neg}, @code{not},
7232 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
7236 In combinations of @code{neg}, @code{mult}, @code{plus}, and
7237 @code{minus}, the @code{neg} operations (if any) will be moved inside
7238 the operations as far as possible. For instance,
7239 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
7240 @code{(plus (mult (neg B) C) A)} is canonicalized as
7241 @code{(minus A (mult B C))}.
7243 @cindex @code{compare}, canonicalization of
7245 For the @code{compare} operator, a constant is always the second operand
7246 if the first argument is a condition code register or @code{(cc0)}.
7249 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
7250 @code{minus} is made the first operand under the same conditions as
7254 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
7255 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
7259 @code{(minus @var{x} (const_int @var{n}))} is converted to
7260 @code{(plus @var{x} (const_int @var{-n}))}.
7263 Within address computations (i.e., inside @code{mem}), a left shift is
7264 converted into the appropriate multiplication by a power of two.
7266 @cindex @code{ior}, canonicalization of
7267 @cindex @code{and}, canonicalization of
7268 @cindex De Morgan's law
7270 De Morgan's Law is used to move bitwise negation inside a bitwise
7271 logical-and or logical-or operation. If this results in only one
7272 operand being a @code{not} expression, it will be the first one.
7274 A machine that has an instruction that performs a bitwise logical-and of one
7275 operand with the bitwise negation of the other should specify the pattern
7276 for that instruction as
7280 [(set (match_operand:@var{m} 0 @dots{})
7281 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7282 (match_operand:@var{m} 2 @dots{})))]
7288 Similarly, a pattern for a ``NAND'' instruction should be written
7292 [(set (match_operand:@var{m} 0 @dots{})
7293 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
7294 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
7299 In both cases, it is not necessary to include patterns for the many
7300 logically equivalent RTL expressions.
7302 @cindex @code{xor}, canonicalization of
7304 The only possible RTL expressions involving both bitwise exclusive-or
7305 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
7306 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
7309 The sum of three items, one of which is a constant, will only appear in
7313 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
7316 @cindex @code{zero_extract}, canonicalization of
7317 @cindex @code{sign_extract}, canonicalization of
7319 Equality comparisons of a group of bits (usually a single bit) with zero
7320 will be written using @code{zero_extract} rather than the equivalent
7321 @code{and} or @code{sign_extract} operations.
7323 @cindex @code{mult}, canonicalization of
7325 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
7326 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
7327 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
7328 for @code{zero_extend}.
7331 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
7332 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
7333 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
7334 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
7335 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
7336 operand of @code{mult} is also a shift, then that is extended also.
7337 This transformation is only applied when it can be proven that the
7338 original operation had sufficient precision to prevent overflow.
7342 Further canonicalization rules are defined in the function
7343 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
7347 @node Expander Definitions
7348 @section Defining RTL Sequences for Code Generation
7349 @cindex expander definitions
7350 @cindex code generation RTL sequences
7351 @cindex defining RTL sequences for code generation
7353 On some target machines, some standard pattern names for RTL generation
7354 cannot be handled with single insn, but a sequence of RTL insns can
7355 represent them. For these target machines, you can write a
7356 @code{define_expand} to specify how to generate the sequence of RTL@.
7358 @findex define_expand
7359 A @code{define_expand} is an RTL expression that looks almost like a
7360 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
7361 only for RTL generation and it can produce more than one RTL insn.
7363 A @code{define_expand} RTX has four operands:
7367 The name. Each @code{define_expand} must have a name, since the only
7368 use for it is to refer to it by name.
7371 The RTL template. This is a vector of RTL expressions representing
7372 a sequence of separate instructions. Unlike @code{define_insn}, there
7373 is no implicit surrounding @code{PARALLEL}.
7376 The condition, a string containing a C expression. This expression is
7377 used to express how the availability of this pattern depends on
7378 subclasses of target machine, selected by command-line options when GCC
7379 is run. This is just like the condition of a @code{define_insn} that
7380 has a standard name. Therefore, the condition (if present) may not
7381 depend on the data in the insn being matched, but only the
7382 target-machine-type flags. The compiler needs to test these conditions
7383 during initialization in order to learn exactly which named instructions
7384 are available in a particular run.
7387 The preparation statements, a string containing zero or more C
7388 statements which are to be executed before RTL code is generated from
7391 Usually these statements prepare temporary registers for use as
7392 internal operands in the RTL template, but they can also generate RTL
7393 insns directly by calling routines such as @code{emit_insn}, etc.
7394 Any such insns precede the ones that come from the RTL template.
7397 Optionally, a vector containing the values of attributes. @xref{Insn
7401 Every RTL insn emitted by a @code{define_expand} must match some
7402 @code{define_insn} in the machine description. Otherwise, the compiler
7403 will crash when trying to generate code for the insn or trying to optimize
7406 The RTL template, in addition to controlling generation of RTL insns,
7407 also describes the operands that need to be specified when this pattern
7408 is used. In particular, it gives a predicate for each operand.
7410 A true operand, which needs to be specified in order to generate RTL from
7411 the pattern, should be described with a @code{match_operand} in its first
7412 occurrence in the RTL template. This enters information on the operand's
7413 predicate into the tables that record such things. GCC uses the
7414 information to preload the operand into a register if that is required for
7415 valid RTL code. If the operand is referred to more than once, subsequent
7416 references should use @code{match_dup}.
7418 The RTL template may also refer to internal ``operands'' which are
7419 temporary registers or labels used only within the sequence made by the
7420 @code{define_expand}. Internal operands are substituted into the RTL
7421 template with @code{match_dup}, never with @code{match_operand}. The
7422 values of the internal operands are not passed in as arguments by the
7423 compiler when it requests use of this pattern. Instead, they are computed
7424 within the pattern, in the preparation statements. These statements
7425 compute the values and store them into the appropriate elements of
7426 @code{operands} so that @code{match_dup} can find them.
7428 There are two special macros defined for use in the preparation statements:
7429 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7436 Use the @code{DONE} macro to end RTL generation for the pattern. The
7437 only RTL insns resulting from the pattern on this occasion will be
7438 those already emitted by explicit calls to @code{emit_insn} within the
7439 preparation statements; the RTL template will not be generated.
7443 Make the pattern fail on this occasion. When a pattern fails, it means
7444 that the pattern was not truly available. The calling routines in the
7445 compiler will try other strategies for code generation using other patterns.
7447 Failure is currently supported only for binary (addition, multiplication,
7448 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7452 If the preparation falls through (invokes neither @code{DONE} nor
7453 @code{FAIL}), then the @code{define_expand} acts like a
7454 @code{define_insn} in that the RTL template is used to generate the
7457 The RTL template is not used for matching, only for generating the
7458 initial insn list. If the preparation statement always invokes
7459 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7460 list of operands, such as this example:
7464 (define_expand "addsi3"
7465 [(match_operand:SI 0 "register_operand" "")
7466 (match_operand:SI 1 "register_operand" "")
7467 (match_operand:SI 2 "register_operand" "")]
7473 handle_add (operands[0], operands[1], operands[2]);
7479 Here is an example, the definition of left-shift for the SPUR chip:
7483 (define_expand "ashlsi3"
7484 [(set (match_operand:SI 0 "register_operand" "")
7488 (match_operand:SI 1 "register_operand" "")
7489 (match_operand:SI 2 "nonmemory_operand" "")))]
7498 if (GET_CODE (operands[2]) != CONST_INT
7499 || (unsigned) INTVAL (operands[2]) > 3)
7506 This example uses @code{define_expand} so that it can generate an RTL insn
7507 for shifting when the shift-count is in the supported range of 0 to 3 but
7508 fail in other cases where machine insns aren't available. When it fails,
7509 the compiler tries another strategy using different patterns (such as, a
7512 If the compiler were able to handle nontrivial condition-strings in
7513 patterns with names, then it would be possible to use a
7514 @code{define_insn} in that case. Here is another case (zero-extension
7515 on the 68000) which makes more use of the power of @code{define_expand}:
7518 (define_expand "zero_extendhisi2"
7519 [(set (match_operand:SI 0 "general_operand" "")
7521 (set (strict_low_part
7525 (match_operand:HI 1 "general_operand" ""))]
7527 "operands[1] = make_safe_from (operands[1], operands[0]);")
7531 @findex make_safe_from
7532 Here two RTL insns are generated, one to clear the entire output operand
7533 and the other to copy the input operand into its low half. This sequence
7534 is incorrect if the input operand refers to [the old value of] the output
7535 operand, so the preparation statement makes sure this isn't so. The
7536 function @code{make_safe_from} copies the @code{operands[1]} into a
7537 temporary register if it refers to @code{operands[0]}. It does this
7538 by emitting another RTL insn.
7540 Finally, a third example shows the use of an internal operand.
7541 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7542 against a halfword mask. But this mask cannot be represented by a
7543 @code{const_int} because the constant value is too large to be legitimate
7544 on this machine. So it must be copied into a register with
7545 @code{force_reg} and then the register used in the @code{and}.
7548 (define_expand "zero_extendhisi2"
7549 [(set (match_operand:SI 0 "register_operand" "")
7551 (match_operand:HI 1 "register_operand" "")
7556 = force_reg (SImode, GEN_INT (65535)); ")
7559 @emph{Note:} If the @code{define_expand} is used to serve a
7560 standard binary or unary arithmetic operation or a bit-field operation,
7561 then the last insn it generates must not be a @code{code_label},
7562 @code{barrier} or @code{note}. It must be an @code{insn},
7563 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7564 at the end, emit an insn to copy the result of the operation into
7565 itself. Such an insn will generate no code, but it can avoid problems
7570 @node Insn Splitting
7571 @section Defining How to Split Instructions
7572 @cindex insn splitting
7573 @cindex instruction splitting
7574 @cindex splitting instructions
7576 There are two cases where you should specify how to split a pattern
7577 into multiple insns. On machines that have instructions requiring
7578 delay slots (@pxref{Delay Slots}) or that have instructions whose
7579 output is not available for multiple cycles (@pxref{Processor pipeline
7580 description}), the compiler phases that optimize these cases need to
7581 be able to move insns into one-instruction delay slots. However, some
7582 insns may generate more than one machine instruction. These insns
7583 cannot be placed into a delay slot.
7585 Often you can rewrite the single insn as a list of individual insns,
7586 each corresponding to one machine instruction. The disadvantage of
7587 doing so is that it will cause the compilation to be slower and require
7588 more space. If the resulting insns are too complex, it may also
7589 suppress some optimizations. The compiler splits the insn if there is a
7590 reason to believe that it might improve instruction or delay slot
7593 The insn combiner phase also splits putative insns. If three insns are
7594 merged into one insn with a complex expression that cannot be matched by
7595 some @code{define_insn} pattern, the combiner phase attempts to split
7596 the complex pattern into two insns that are recognized. Usually it can
7597 break the complex pattern into two patterns by splitting out some
7598 subexpression. However, in some other cases, such as performing an
7599 addition of a large constant in two insns on a RISC machine, the way to
7600 split the addition into two insns is machine-dependent.
7602 @findex define_split
7603 The @code{define_split} definition tells the compiler how to split a
7604 complex insn into several simpler insns. It looks like this:
7608 [@var{insn-pattern}]
7610 [@var{new-insn-pattern-1}
7611 @var{new-insn-pattern-2}
7613 "@var{preparation-statements}")
7616 @var{insn-pattern} is a pattern that needs to be split and
7617 @var{condition} is the final condition to be tested, as in a
7618 @code{define_insn}. When an insn matching @var{insn-pattern} and
7619 satisfying @var{condition} is found, it is replaced in the insn list
7620 with the insns given by @var{new-insn-pattern-1},
7621 @var{new-insn-pattern-2}, etc.
7623 The @var{preparation-statements} are similar to those statements that
7624 are specified for @code{define_expand} (@pxref{Expander Definitions})
7625 and are executed before the new RTL is generated to prepare for the
7626 generated code or emit some insns whose pattern is not fixed. Unlike
7627 those in @code{define_expand}, however, these statements must not
7628 generate any new pseudo-registers. Once reload has completed, they also
7629 must not allocate any space in the stack frame.
7631 Patterns are matched against @var{insn-pattern} in two different
7632 circumstances. If an insn needs to be split for delay slot scheduling
7633 or insn scheduling, the insn is already known to be valid, which means
7634 that it must have been matched by some @code{define_insn} and, if
7635 @code{reload_completed} is nonzero, is known to satisfy the constraints
7636 of that @code{define_insn}. In that case, the new insn patterns must
7637 also be insns that are matched by some @code{define_insn} and, if
7638 @code{reload_completed} is nonzero, must also satisfy the constraints
7639 of those definitions.
7641 As an example of this usage of @code{define_split}, consider the following
7642 example from @file{a29k.md}, which splits a @code{sign_extend} from
7643 @code{HImode} to @code{SImode} into a pair of shift insns:
7647 [(set (match_operand:SI 0 "gen_reg_operand" "")
7648 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7651 (ashift:SI (match_dup 1)
7654 (ashiftrt:SI (match_dup 0)
7657 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7660 When the combiner phase tries to split an insn pattern, it is always the
7661 case that the pattern is @emph{not} matched by any @code{define_insn}.
7662 The combiner pass first tries to split a single @code{set} expression
7663 and then the same @code{set} expression inside a @code{parallel}, but
7664 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7665 register. In these cases, the combiner expects exactly two new insn
7666 patterns to be generated. It will verify that these patterns match some
7667 @code{define_insn} definitions, so you need not do this test in the
7668 @code{define_split} (of course, there is no point in writing a
7669 @code{define_split} that will never produce insns that match).
7671 Here is an example of this use of @code{define_split}, taken from
7676 [(set (match_operand:SI 0 "gen_reg_operand" "")
7677 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7678 (match_operand:SI 2 "non_add_cint_operand" "")))]
7680 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7681 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7684 int low = INTVAL (operands[2]) & 0xffff;
7685 int high = (unsigned) INTVAL (operands[2]) >> 16;
7688 high++, low |= 0xffff0000;
7690 operands[3] = GEN_INT (high << 16);
7691 operands[4] = GEN_INT (low);
7695 Here the predicate @code{non_add_cint_operand} matches any
7696 @code{const_int} that is @emph{not} a valid operand of a single add
7697 insn. The add with the smaller displacement is written so that it
7698 can be substituted into the address of a subsequent operation.
7700 An example that uses a scratch register, from the same file, generates
7701 an equality comparison of a register and a large constant:
7705 [(set (match_operand:CC 0 "cc_reg_operand" "")
7706 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7707 (match_operand:SI 2 "non_short_cint_operand" "")))
7708 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7709 "find_single_use (operands[0], insn, 0)
7710 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7711 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7712 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7713 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7716 /* @r{Get the constant we are comparing against, C, and see what it
7717 looks like sign-extended to 16 bits. Then see what constant
7718 could be XOR'ed with C to get the sign-extended value.} */
7720 int c = INTVAL (operands[2]);
7721 int sextc = (c << 16) >> 16;
7722 int xorv = c ^ sextc;
7724 operands[4] = GEN_INT (xorv);
7725 operands[5] = GEN_INT (sextc);
7729 To avoid confusion, don't write a single @code{define_split} that
7730 accepts some insns that match some @code{define_insn} as well as some
7731 insns that don't. Instead, write two separate @code{define_split}
7732 definitions, one for the insns that are valid and one for the insns that
7735 The splitter is allowed to split jump instructions into sequence of
7736 jumps or create new jumps in while splitting non-jump instructions. As
7737 the central flowgraph and branch prediction information needs to be updated,
7738 several restriction apply.
7740 Splitting of jump instruction into sequence that over by another jump
7741 instruction is always valid, as compiler expect identical behavior of new
7742 jump. When new sequence contains multiple jump instructions or new labels,
7743 more assistance is needed. Splitter is required to create only unconditional
7744 jumps, or simple conditional jump instructions. Additionally it must attach a
7745 @code{REG_BR_PROB} note to each conditional jump. A global variable
7746 @code{split_branch_probability} holds the probability of the original branch in case
7747 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7748 recomputing of edge frequencies, the new sequence is required to have only
7749 forward jumps to the newly created labels.
7751 @findex define_insn_and_split
7752 For the common case where the pattern of a define_split exactly matches the
7753 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7757 (define_insn_and_split
7758 [@var{insn-pattern}]
7760 "@var{output-template}"
7761 "@var{split-condition}"
7762 [@var{new-insn-pattern-1}
7763 @var{new-insn-pattern-2}
7765 "@var{preparation-statements}"
7766 [@var{insn-attributes}])
7770 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7771 @var{insn-attributes} are used as in @code{define_insn}. The
7772 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7773 in a @code{define_split}. The @var{split-condition} is also used as in
7774 @code{define_split}, with the additional behavior that if the condition starts
7775 with @samp{&&}, the condition used for the split will be the constructed as a
7776 logical ``and'' of the split condition with the insn condition. For example,
7780 (define_insn_and_split "zero_extendhisi2_and"
7781 [(set (match_operand:SI 0 "register_operand" "=r")
7782 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7783 (clobber (reg:CC 17))]
7784 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7786 "&& reload_completed"
7787 [(parallel [(set (match_dup 0)
7788 (and:SI (match_dup 0) (const_int 65535)))
7789 (clobber (reg:CC 17))])]
7791 [(set_attr "type" "alu1")])
7795 In this case, the actual split condition will be
7796 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7798 The @code{define_insn_and_split} construction provides exactly the same
7799 functionality as two separate @code{define_insn} and @code{define_split}
7800 patterns. It exists for compactness, and as a maintenance tool to prevent
7801 having to ensure the two patterns' templates match.
7805 @node Including Patterns
7806 @section Including Patterns in Machine Descriptions.
7807 @cindex insn includes
7810 The @code{include} pattern tells the compiler tools where to
7811 look for patterns that are in files other than in the file
7812 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7826 (include "filestuff")
7830 Where @var{pathname} is a string that specifies the location of the file,
7831 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7832 directory @file{gcc/config/target} is regarded as the default directory.
7835 Machine descriptions may be split up into smaller more manageable subsections
7836 and placed into subdirectories.
7842 (include "BOGUS/filestuff")
7846 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7848 Specifying an absolute path for the include file such as;
7851 (include "/u2/BOGUS/filestuff")
7854 is permitted but is not encouraged.
7856 @subsection RTL Generation Tool Options for Directory Search
7857 @cindex directory options .md
7858 @cindex options, directory search
7859 @cindex search options
7861 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7866 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7871 Add the directory @var{dir} to the head of the list of directories to be
7872 searched for header files. This can be used to override a system machine definition
7873 file, substituting your own version, since these directories are
7874 searched before the default machine description file directories. If you use more than
7875 one @option{-I} option, the directories are scanned in left-to-right
7876 order; the standard default directory come after.
7881 @node Peephole Definitions
7882 @section Machine-Specific Peephole Optimizers
7883 @cindex peephole optimizer definitions
7884 @cindex defining peephole optimizers
7886 In addition to instruction patterns the @file{md} file may contain
7887 definitions of machine-specific peephole optimizations.
7889 The combiner does not notice certain peephole optimizations when the data
7890 flow in the program does not suggest that it should try them. For example,
7891 sometimes two consecutive insns related in purpose can be combined even
7892 though the second one does not appear to use a register computed in the
7893 first one. A machine-specific peephole optimizer can detect such
7896 There are two forms of peephole definitions that may be used. The
7897 original @code{define_peephole} is run at assembly output time to
7898 match insns and substitute assembly text. Use of @code{define_peephole}
7901 A newer @code{define_peephole2} matches insns and substitutes new
7902 insns. The @code{peephole2} pass is run after register allocation
7903 but before scheduling, which may result in much better code for
7904 targets that do scheduling.
7907 * define_peephole:: RTL to Text Peephole Optimizers
7908 * define_peephole2:: RTL to RTL Peephole Optimizers
7913 @node define_peephole
7914 @subsection RTL to Text Peephole Optimizers
7915 @findex define_peephole
7918 A definition looks like this:
7922 [@var{insn-pattern-1}
7923 @var{insn-pattern-2}
7927 "@var{optional-insn-attributes}")
7931 The last string operand may be omitted if you are not using any
7932 machine-specific information in this machine description. If present,
7933 it must obey the same rules as in a @code{define_insn}.
7935 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7936 consecutive insns. The optimization applies to a sequence of insns when
7937 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7938 the next, and so on.
7940 Each of the insns matched by a peephole must also match a
7941 @code{define_insn}. Peepholes are checked only at the last stage just
7942 before code generation, and only optionally. Therefore, any insn which
7943 would match a peephole but no @code{define_insn} will cause a crash in code
7944 generation in an unoptimized compilation, or at various optimization
7947 The operands of the insns are matched with @code{match_operands},
7948 @code{match_operator}, and @code{match_dup}, as usual. What is not
7949 usual is that the operand numbers apply to all the insn patterns in the
7950 definition. So, you can check for identical operands in two insns by
7951 using @code{match_operand} in one insn and @code{match_dup} in the
7954 The operand constraints used in @code{match_operand} patterns do not have
7955 any direct effect on the applicability of the peephole, but they will
7956 be validated afterward, so make sure your constraints are general enough
7957 to apply whenever the peephole matches. If the peephole matches
7958 but the constraints are not satisfied, the compiler will crash.
7960 It is safe to omit constraints in all the operands of the peephole; or
7961 you can write constraints which serve as a double-check on the criteria
7964 Once a sequence of insns matches the patterns, the @var{condition} is
7965 checked. This is a C expression which makes the final decision whether to
7966 perform the optimization (we do so if the expression is nonzero). If
7967 @var{condition} is omitted (in other words, the string is empty) then the
7968 optimization is applied to every sequence of insns that matches the
7971 The defined peephole optimizations are applied after register allocation
7972 is complete. Therefore, the peephole definition can check which
7973 operands have ended up in which kinds of registers, just by looking at
7976 @findex prev_active_insn
7977 The way to refer to the operands in @var{condition} is to write
7978 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7979 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7980 to refer to the last of the insns being matched; use
7981 @code{prev_active_insn} to find the preceding insns.
7983 @findex dead_or_set_p
7984 When optimizing computations with intermediate results, you can use
7985 @var{condition} to match only when the intermediate results are not used
7986 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7987 @var{op})}, where @var{insn} is the insn in which you expect the value
7988 to be used for the last time (from the value of @code{insn}, together
7989 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7990 value (from @code{operands[@var{i}]}).
7992 Applying the optimization means replacing the sequence of insns with one
7993 new insn. The @var{template} controls ultimate output of assembler code
7994 for this combined insn. It works exactly like the template of a
7995 @code{define_insn}. Operand numbers in this template are the same ones
7996 used in matching the original sequence of insns.
7998 The result of a defined peephole optimizer does not need to match any of
7999 the insn patterns in the machine description; it does not even have an
8000 opportunity to match them. The peephole optimizer definition itself serves
8001 as the insn pattern to control how the insn is output.
8003 Defined peephole optimizers are run as assembler code is being output,
8004 so the insns they produce are never combined or rearranged in any way.
8006 Here is an example, taken from the 68000 machine description:
8010 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
8011 (set (match_operand:DF 0 "register_operand" "=f")
8012 (match_operand:DF 1 "register_operand" "ad"))]
8013 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
8016 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8018 output_asm_insn ("move.l %1,(sp)", xoperands);
8019 output_asm_insn ("move.l %1,-(sp)", operands);
8020 return "fmove.d (sp)+,%0";
8022 output_asm_insn ("movel %1,sp@@", xoperands);
8023 output_asm_insn ("movel %1,sp@@-", operands);
8024 return "fmoved sp@@+,%0";
8030 The effect of this optimization is to change
8056 If a peephole matches a sequence including one or more jump insns, you must
8057 take account of the flags such as @code{CC_REVERSED} which specify that the
8058 condition codes are represented in an unusual manner. The compiler
8059 automatically alters any ordinary conditional jumps which occur in such
8060 situations, but the compiler cannot alter jumps which have been replaced by
8061 peephole optimizations. So it is up to you to alter the assembler code
8062 that the peephole produces. Supply C code to write the assembler output,
8063 and in this C code check the condition code status flags and change the
8064 assembler code as appropriate.
8067 @var{insn-pattern-1} and so on look @emph{almost} like the second
8068 operand of @code{define_insn}. There is one important difference: the
8069 second operand of @code{define_insn} consists of one or more RTX's
8070 enclosed in square brackets. Usually, there is only one: then the same
8071 action can be written as an element of a @code{define_peephole}. But
8072 when there are multiple actions in a @code{define_insn}, they are
8073 implicitly enclosed in a @code{parallel}. Then you must explicitly
8074 write the @code{parallel}, and the square brackets within it, in the
8075 @code{define_peephole}. Thus, if an insn pattern looks like this,
8078 (define_insn "divmodsi4"
8079 [(set (match_operand:SI 0 "general_operand" "=d")
8080 (div:SI (match_operand:SI 1 "general_operand" "0")
8081 (match_operand:SI 2 "general_operand" "dmsK")))
8082 (set (match_operand:SI 3 "general_operand" "=d")
8083 (mod:SI (match_dup 1) (match_dup 2)))]
8085 "divsl%.l %2,%3:%0")
8089 then the way to mention this insn in a peephole is as follows:
8095 [(set (match_operand:SI 0 "general_operand" "=d")
8096 (div:SI (match_operand:SI 1 "general_operand" "0")
8097 (match_operand:SI 2 "general_operand" "dmsK")))
8098 (set (match_operand:SI 3 "general_operand" "=d")
8099 (mod:SI (match_dup 1) (match_dup 2)))])
8106 @node define_peephole2
8107 @subsection RTL to RTL Peephole Optimizers
8108 @findex define_peephole2
8110 The @code{define_peephole2} definition tells the compiler how to
8111 substitute one sequence of instructions for another sequence,
8112 what additional scratch registers may be needed and what their
8117 [@var{insn-pattern-1}
8118 @var{insn-pattern-2}
8121 [@var{new-insn-pattern-1}
8122 @var{new-insn-pattern-2}
8124 "@var{preparation-statements}")
8127 The definition is almost identical to @code{define_split}
8128 (@pxref{Insn Splitting}) except that the pattern to match is not a
8129 single instruction, but a sequence of instructions.
8131 It is possible to request additional scratch registers for use in the
8132 output template. If appropriate registers are not free, the pattern
8133 will simply not match.
8135 @findex match_scratch
8137 Scratch registers are requested with a @code{match_scratch} pattern at
8138 the top level of the input pattern. The allocated register (initially) will
8139 be dead at the point requested within the original sequence. If the scratch
8140 is used at more than a single point, a @code{match_dup} pattern at the
8141 top level of the input pattern marks the last position in the input sequence
8142 at which the register must be available.
8144 Here is an example from the IA-32 machine description:
8148 [(match_scratch:SI 2 "r")
8149 (parallel [(set (match_operand:SI 0 "register_operand" "")
8150 (match_operator:SI 3 "arith_or_logical_operator"
8152 (match_operand:SI 1 "memory_operand" "")]))
8153 (clobber (reg:CC 17))])]
8154 "! optimize_size && ! TARGET_READ_MODIFY"
8155 [(set (match_dup 2) (match_dup 1))
8156 (parallel [(set (match_dup 0)
8157 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
8158 (clobber (reg:CC 17))])]
8163 This pattern tries to split a load from its use in the hopes that we'll be
8164 able to schedule around the memory load latency. It allocates a single
8165 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
8166 to be live only at the point just before the arithmetic.
8168 A real example requiring extended scratch lifetimes is harder to come by,
8169 so here's a silly made-up example:
8173 [(match_scratch:SI 4 "r")
8174 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8175 (set (match_operand:SI 2 "" "") (match_dup 1))
8177 (set (match_operand:SI 3 "" "") (match_dup 1))]
8178 "/* @r{determine 1 does not overlap 0 and 2} */"
8179 [(set (match_dup 4) (match_dup 1))
8180 (set (match_dup 0) (match_dup 4))
8181 (set (match_dup 2) (match_dup 4))
8182 (set (match_dup 3) (match_dup 4))]
8187 If we had not added the @code{(match_dup 4)} in the middle of the input
8188 sequence, it might have been the case that the register we chose at the
8189 beginning of the sequence is killed by the first or second @code{set}.
8193 @node Insn Attributes
8194 @section Instruction Attributes
8195 @cindex insn attributes
8196 @cindex instruction attributes
8198 In addition to describing the instruction supported by the target machine,
8199 the @file{md} file also defines a group of @dfn{attributes} and a set of
8200 values for each. Every generated insn is assigned a value for each attribute.
8201 One possible attribute would be the effect that the insn has on the machine's
8202 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
8203 to track the condition codes.
8206 * Defining Attributes:: Specifying attributes and their values.
8207 * Expressions:: Valid expressions for attribute values.
8208 * Tagging Insns:: Assigning attribute values to insns.
8209 * Attr Example:: An example of assigning attributes.
8210 * Insn Lengths:: Computing the length of insns.
8211 * Constant Attributes:: Defining attributes that are constant.
8212 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
8213 * Delay Slots:: Defining delay slots required for a machine.
8214 * Processor pipeline description:: Specifying information for insn scheduling.
8219 @node Defining Attributes
8220 @subsection Defining Attributes and their Values
8221 @cindex defining attributes and their values
8222 @cindex attributes, defining
8225 The @code{define_attr} expression is used to define each attribute required
8226 by the target machine. It looks like:
8229 (define_attr @var{name} @var{list-of-values} @var{default})
8232 @var{name} is a string specifying the name of the attribute being
8233 defined. Some attributes are used in a special way by the rest of the
8234 compiler. The @code{enabled} attribute can be used to conditionally
8235 enable or disable insn alternatives (@pxref{Disable Insn
8236 Alternatives}). The @code{predicable} attribute, together with a
8237 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
8238 be used to automatically generate conditional variants of instruction
8239 patterns. The @code{mnemonic} attribute can be used to check for the
8240 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
8241 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
8242 so they should not be used elsewhere as alternative names.
8244 @var{list-of-values} is either a string that specifies a comma-separated
8245 list of values that can be assigned to the attribute, or a null string to
8246 indicate that the attribute takes numeric values.
8248 @var{default} is an attribute expression that gives the value of this
8249 attribute for insns that match patterns whose definition does not include
8250 an explicit value for this attribute. @xref{Attr Example}, for more
8251 information on the handling of defaults. @xref{Constant Attributes},
8252 for information on attributes that do not depend on any particular insn.
8255 For each defined attribute, a number of definitions are written to the
8256 @file{insn-attr.h} file. For cases where an explicit set of values is
8257 specified for an attribute, the following are defined:
8261 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
8264 An enumerated class is defined for @samp{attr_@var{name}} with
8265 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
8266 the attribute name and value are first converted to uppercase.
8269 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
8270 returns the attribute value for that insn.
8273 For example, if the following is present in the @file{md} file:
8276 (define_attr "type" "branch,fp,load,store,arith" @dots{})
8280 the following lines will be written to the file @file{insn-attr.h}.
8283 #define HAVE_ATTR_type 1
8284 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
8285 TYPE_STORE, TYPE_ARITH@};
8286 extern enum attr_type get_attr_type ();
8289 If the attribute takes numeric values, no @code{enum} type will be
8290 defined and the function to obtain the attribute's value will return
8293 There are attributes which are tied to a specific meaning. These
8294 attributes are not free to use for other purposes:
8298 The @code{length} attribute is used to calculate the length of emitted
8299 code chunks. This is especially important when verifying branch
8300 distances. @xref{Insn Lengths}.
8303 The @code{enabled} attribute can be defined to prevent certain
8304 alternatives of an insn definition from being used during code
8305 generation. @xref{Disable Insn Alternatives}.
8308 The @code{mnemonic} attribute can be defined to implement instruction
8309 specific checks in e.g. the pipeline description.
8310 @xref{Mnemonic Attribute}.
8313 For each of these special attributes, the corresponding
8314 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
8315 attribute is not defined; in that case, it is defined as @samp{0}.
8317 @findex define_enum_attr
8318 @anchor{define_enum_attr}
8319 Another way of defining an attribute is to use:
8322 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
8325 This works in just the same way as @code{define_attr}, except that
8326 the list of values is taken from a separate enumeration called
8327 @var{enum} (@pxref{define_enum}). This form allows you to use
8328 the same list of values for several attributes without having to
8329 repeat the list each time. For example:
8332 (define_enum "processor" [
8337 (define_enum_attr "arch" "processor"
8338 (const (symbol_ref "target_arch")))
8339 (define_enum_attr "tune" "processor"
8340 (const (symbol_ref "target_tune")))
8343 defines the same attributes as:
8346 (define_attr "arch" "model_a,model_b,@dots{}"
8347 (const (symbol_ref "target_arch")))
8348 (define_attr "tune" "model_a,model_b,@dots{}"
8349 (const (symbol_ref "target_tune")))
8352 but without duplicating the processor list. The second example defines two
8353 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
8354 defines a single C enum (@code{processor}).
8358 @subsection Attribute Expressions
8359 @cindex attribute expressions
8361 RTL expressions used to define attributes use the codes described above
8362 plus a few specific to attribute definitions, to be discussed below.
8363 Attribute value expressions must have one of the following forms:
8366 @cindex @code{const_int} and attributes
8367 @item (const_int @var{i})
8368 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8369 must be non-negative.
8371 The value of a numeric attribute can be specified either with a
8372 @code{const_int}, or as an integer represented as a string in
8373 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8374 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8375 overrides on specific instructions (@pxref{Tagging Insns}).
8377 @cindex @code{const_string} and attributes
8378 @item (const_string @var{value})
8379 The string @var{value} specifies a constant attribute value.
8380 If @var{value} is specified as @samp{"*"}, it means that the default value of
8381 the attribute is to be used for the insn containing this expression.
8382 @samp{"*"} obviously cannot be used in the @var{default} expression
8383 of a @code{define_attr}.
8385 If the attribute whose value is being specified is numeric, @var{value}
8386 must be a string containing a non-negative integer (normally
8387 @code{const_int} would be used in this case). Otherwise, it must
8388 contain one of the valid values for the attribute.
8390 @cindex @code{if_then_else} and attributes
8391 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8392 @var{test} specifies an attribute test, whose format is defined below.
8393 The value of this expression is @var{true-value} if @var{test} is true,
8394 otherwise it is @var{false-value}.
8396 @cindex @code{cond} and attributes
8397 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8398 The first operand of this expression is a vector containing an even
8399 number of expressions and consisting of pairs of @var{test} and @var{value}
8400 expressions. The value of the @code{cond} expression is that of the
8401 @var{value} corresponding to the first true @var{test} expression. If
8402 none of the @var{test} expressions are true, the value of the @code{cond}
8403 expression is that of the @var{default} expression.
8406 @var{test} expressions can have one of the following forms:
8409 @cindex @code{const_int} and attribute tests
8410 @item (const_int @var{i})
8411 This test is true if @var{i} is nonzero and false otherwise.
8413 @cindex @code{not} and attributes
8414 @cindex @code{ior} and attributes
8415 @cindex @code{and} and attributes
8416 @item (not @var{test})
8417 @itemx (ior @var{test1} @var{test2})
8418 @itemx (and @var{test1} @var{test2})
8419 These tests are true if the indicated logical function is true.
8421 @cindex @code{match_operand} and attributes
8422 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8423 This test is true if operand @var{n} of the insn whose attribute value
8424 is being determined has mode @var{m} (this part of the test is ignored
8425 if @var{m} is @code{VOIDmode}) and the function specified by the string
8426 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8427 @var{m} (this part of the test is ignored if @var{pred} is the null
8430 The @var{constraints} operand is ignored and should be the null string.
8432 @cindex @code{match_test} and attributes
8433 @item (match_test @var{c-expr})
8434 The test is true if C expression @var{c-expr} is true. In non-constant
8435 attributes, @var{c-expr} has access to the following variables:
8439 The rtl instruction under test.
8440 @item which_alternative
8441 The @code{define_insn} alternative that @var{insn} matches.
8442 @xref{Output Statement}.
8444 An array of @var{insn}'s rtl operands.
8447 @var{c-expr} behaves like the condition in a C @code{if} statement,
8448 so there is no need to explicitly convert the expression into a boolean
8449 0 or 1 value. For example, the following two tests are equivalent:
8452 (match_test "x & 2")
8453 (match_test "(x & 2) != 0")
8456 @cindex @code{le} and attributes
8457 @cindex @code{leu} and attributes
8458 @cindex @code{lt} and attributes
8459 @cindex @code{gt} and attributes
8460 @cindex @code{gtu} and attributes
8461 @cindex @code{ge} and attributes
8462 @cindex @code{geu} and attributes
8463 @cindex @code{ne} and attributes
8464 @cindex @code{eq} and attributes
8465 @cindex @code{plus} and attributes
8466 @cindex @code{minus} and attributes
8467 @cindex @code{mult} and attributes
8468 @cindex @code{div} and attributes
8469 @cindex @code{mod} and attributes
8470 @cindex @code{abs} and attributes
8471 @cindex @code{neg} and attributes
8472 @cindex @code{ashift} and attributes
8473 @cindex @code{lshiftrt} and attributes
8474 @cindex @code{ashiftrt} and attributes
8475 @item (le @var{arith1} @var{arith2})
8476 @itemx (leu @var{arith1} @var{arith2})
8477 @itemx (lt @var{arith1} @var{arith2})
8478 @itemx (ltu @var{arith1} @var{arith2})
8479 @itemx (gt @var{arith1} @var{arith2})
8480 @itemx (gtu @var{arith1} @var{arith2})
8481 @itemx (ge @var{arith1} @var{arith2})
8482 @itemx (geu @var{arith1} @var{arith2})
8483 @itemx (ne @var{arith1} @var{arith2})
8484 @itemx (eq @var{arith1} @var{arith2})
8485 These tests are true if the indicated comparison of the two arithmetic
8486 expressions is true. Arithmetic expressions are formed with
8487 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8488 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8489 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8492 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8493 Lengths},for additional forms). @code{symbol_ref} is a string
8494 denoting a C expression that yields an @code{int} when evaluated by the
8495 @samp{get_attr_@dots{}} routine. It should normally be a global
8499 @item (eq_attr @var{name} @var{value})
8500 @var{name} is a string specifying the name of an attribute.
8502 @var{value} is a string that is either a valid value for attribute
8503 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8504 value or list. If @var{value} does not begin with a @samp{!}, this
8505 test is true if the value of the @var{name} attribute of the current
8506 insn is in the list specified by @var{value}. If @var{value} begins
8507 with a @samp{!}, this test is true if the attribute's value is
8508 @emph{not} in the specified list.
8513 (eq_attr "type" "load,store")
8520 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8523 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8524 value of the compiler variable @code{which_alternative}
8525 (@pxref{Output Statement}) and the values must be small integers. For
8529 (eq_attr "alternative" "2,3")
8536 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8537 (eq (symbol_ref "which_alternative") (const_int 3)))
8540 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8541 where the value of the attribute being tested is known for all insns matching
8542 a particular pattern. This is by far the most common case.
8545 @item (attr_flag @var{name})
8546 The value of an @code{attr_flag} expression is true if the flag
8547 specified by @var{name} is true for the @code{insn} currently being
8550 @var{name} is a string specifying one of a fixed set of flags to test.
8551 Test the flags @code{forward} and @code{backward} to determine the
8552 direction of a conditional branch.
8554 This example describes a conditional branch delay slot which
8555 can be nullified for forward branches that are taken (annul-true) or
8556 for backward branches which are not taken (annul-false).
8559 (define_delay (eq_attr "type" "cbranch")
8560 [(eq_attr "in_branch_delay" "true")
8561 (and (eq_attr "in_branch_delay" "true")
8562 (attr_flag "forward"))
8563 (and (eq_attr "in_branch_delay" "true")
8564 (attr_flag "backward"))])
8567 The @code{forward} and @code{backward} flags are false if the current
8568 @code{insn} being scheduled is not a conditional branch.
8570 @code{attr_flag} is only used during delay slot scheduling and has no
8571 meaning to other passes of the compiler.
8574 @item (attr @var{name})
8575 The value of another attribute is returned. This is most useful
8576 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8577 produce more efficient code for non-numeric attributes.
8583 @subsection Assigning Attribute Values to Insns
8584 @cindex tagging insns
8585 @cindex assigning attribute values to insns
8587 The value assigned to an attribute of an insn is primarily determined by
8588 which pattern is matched by that insn (or which @code{define_peephole}
8589 generated it). Every @code{define_insn} and @code{define_peephole} can
8590 have an optional last argument to specify the values of attributes for
8591 matching insns. The value of any attribute not specified in a particular
8592 insn is set to the default value for that attribute, as specified in its
8593 @code{define_attr}. Extensive use of default values for attributes
8594 permits the specification of the values for only one or two attributes
8595 in the definition of most insn patterns, as seen in the example in the
8598 The optional last argument of @code{define_insn} and
8599 @code{define_peephole} is a vector of expressions, each of which defines
8600 the value for a single attribute. The most general way of assigning an
8601 attribute's value is to use a @code{set} expression whose first operand is an
8602 @code{attr} expression giving the name of the attribute being set. The
8603 second operand of the @code{set} is an attribute expression
8604 (@pxref{Expressions}) giving the value of the attribute.
8606 When the attribute value depends on the @samp{alternative} attribute
8607 (i.e., which is the applicable alternative in the constraint of the
8608 insn), the @code{set_attr_alternative} expression can be used. It
8609 allows the specification of a vector of attribute expressions, one for
8613 When the generality of arbitrary attribute expressions is not required,
8614 the simpler @code{set_attr} expression can be used, which allows
8615 specifying a string giving either a single attribute value or a list
8616 of attribute values, one for each alternative.
8618 The form of each of the above specifications is shown below. In each case,
8619 @var{name} is a string specifying the attribute to be set.
8622 @item (set_attr @var{name} @var{value-string})
8623 @var{value-string} is either a string giving the desired attribute value,
8624 or a string containing a comma-separated list giving the values for
8625 succeeding alternatives. The number of elements must match the number
8626 of alternatives in the constraint of the insn pattern.
8628 Note that it may be useful to specify @samp{*} for some alternative, in
8629 which case the attribute will assume its default value for insns matching
8632 @findex set_attr_alternative
8633 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8634 Depending on the alternative of the insn, the value will be one of the
8635 specified values. This is a shorthand for using a @code{cond} with
8636 tests on the @samp{alternative} attribute.
8639 @item (set (attr @var{name}) @var{value})
8640 The first operand of this @code{set} must be the special RTL expression
8641 @code{attr}, whose sole operand is a string giving the name of the
8642 attribute being set. @var{value} is the value of the attribute.
8645 The following shows three different ways of representing the same
8646 attribute value specification:
8649 (set_attr "type" "load,store,arith")
8651 (set_attr_alternative "type"
8652 [(const_string "load") (const_string "store")
8653 (const_string "arith")])
8656 (cond [(eq_attr "alternative" "1") (const_string "load")
8657 (eq_attr "alternative" "2") (const_string "store")]
8658 (const_string "arith")))
8662 @findex define_asm_attributes
8663 The @code{define_asm_attributes} expression provides a mechanism to
8664 specify the attributes assigned to insns produced from an @code{asm}
8665 statement. It has the form:
8668 (define_asm_attributes [@var{attr-sets}])
8672 where @var{attr-sets} is specified the same as for both the
8673 @code{define_insn} and the @code{define_peephole} expressions.
8675 These values will typically be the ``worst case'' attribute values. For
8676 example, they might indicate that the condition code will be clobbered.
8678 A specification for a @code{length} attribute is handled specially. The
8679 way to compute the length of an @code{asm} insn is to multiply the
8680 length specified in the expression @code{define_asm_attributes} by the
8681 number of machine instructions specified in the @code{asm} statement,
8682 determined by counting the number of semicolons and newlines in the
8683 string. Therefore, the value of the @code{length} attribute specified
8684 in a @code{define_asm_attributes} should be the maximum possible length
8685 of a single machine instruction.
8690 @subsection Example of Attribute Specifications
8691 @cindex attribute specifications example
8692 @cindex attribute specifications
8694 The judicious use of defaulting is important in the efficient use of
8695 insn attributes. Typically, insns are divided into @dfn{types} and an
8696 attribute, customarily called @code{type}, is used to represent this
8697 value. This attribute is normally used only to define the default value
8698 for other attributes. An example will clarify this usage.
8700 Assume we have a RISC machine with a condition code and in which only
8701 full-word operations are performed in registers. Let us assume that we
8702 can divide all insns into loads, stores, (integer) arithmetic
8703 operations, floating point operations, and branches.
8705 Here we will concern ourselves with determining the effect of an insn on
8706 the condition code and will limit ourselves to the following possible
8707 effects: The condition code can be set unpredictably (clobbered), not
8708 be changed, be set to agree with the results of the operation, or only
8709 changed if the item previously set into the condition code has been
8712 Here is part of a sample @file{md} file for such a machine:
8715 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8717 (define_attr "cc" "clobber,unchanged,set,change0"
8718 (cond [(eq_attr "type" "load")
8719 (const_string "change0")
8720 (eq_attr "type" "store,branch")
8721 (const_string "unchanged")
8722 (eq_attr "type" "arith")
8723 (if_then_else (match_operand:SI 0 "" "")
8724 (const_string "set")
8725 (const_string "clobber"))]
8726 (const_string "clobber")))
8729 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8730 (match_operand:SI 1 "general_operand" "r,m,r"))]
8736 [(set_attr "type" "arith,load,store")])
8739 Note that we assume in the above example that arithmetic operations
8740 performed on quantities smaller than a machine word clobber the condition
8741 code since they will set the condition code to a value corresponding to the
8747 @subsection Computing the Length of an Insn
8748 @cindex insn lengths, computing
8749 @cindex computing the length of an insn
8751 For many machines, multiple types of branch instructions are provided, each
8752 for different length branch displacements. In most cases, the assembler
8753 will choose the correct instruction to use. However, when the assembler
8754 cannot do so, GCC can when a special attribute, the @code{length}
8755 attribute, is defined. This attribute must be defined to have numeric
8756 values by specifying a null string in its @code{define_attr}.
8758 In the case of the @code{length} attribute, two additional forms of
8759 arithmetic terms are allowed in test expressions:
8762 @cindex @code{match_dup} and attributes
8763 @item (match_dup @var{n})
8764 This refers to the address of operand @var{n} of the current insn, which
8765 must be a @code{label_ref}.
8767 @cindex @code{pc} and attributes
8769 For non-branch instructions and backward branch instructions, this refers
8770 to the address of the current insn. But for forward branch instructions,
8771 this refers to the address of the next insn, because the length of the
8772 current insn is to be computed.
8775 @cindex @code{addr_vec}, length of
8776 @cindex @code{addr_diff_vec}, length of
8777 For normal insns, the length will be determined by value of the
8778 @code{length} attribute. In the case of @code{addr_vec} and
8779 @code{addr_diff_vec} insn patterns, the length is computed as
8780 the number of vectors multiplied by the size of each vector.
8782 Lengths are measured in addressable storage units (bytes).
8784 Note that it is possible to call functions via the @code{symbol_ref}
8785 mechanism to compute the length of an insn. However, if you use this
8786 mechanism you must provide dummy clauses to express the maximum length
8787 without using the function call. You can an example of this in the
8788 @code{pa} machine description for the @code{call_symref} pattern.
8790 The following macros can be used to refine the length computation:
8793 @findex ADJUST_INSN_LENGTH
8794 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8795 If defined, modifies the length assigned to instruction @var{insn} as a
8796 function of the context in which it is used. @var{length} is an lvalue
8797 that contains the initially computed length of the insn and should be
8798 updated with the correct length of the insn.
8800 This macro will normally not be required. A case in which it is
8801 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8802 insn must be increased by two to compensate for the fact that alignment
8806 @findex get_attr_length
8807 The routine that returns @code{get_attr_length} (the value of the
8808 @code{length} attribute) can be used by the output routine to
8809 determine the form of the branch instruction to be written, as the
8810 example below illustrates.
8812 As an example of the specification of variable-length branches, consider
8813 the IBM 360. If we adopt the convention that a register will be set to
8814 the starting address of a function, we can jump to labels within 4k of
8815 the start using a four-byte instruction. Otherwise, we need a six-byte
8816 sequence to load the address from memory and then branch to it.
8818 On such a machine, a pattern for a branch instruction might be specified
8824 (label_ref (match_operand 0 "" "")))]
8827 return (get_attr_length (insn) == 4
8828 ? "b %l0" : "l r15,=a(%l0); br r15");
8830 [(set (attr "length")
8831 (if_then_else (lt (match_dup 0) (const_int 4096))
8838 @node Constant Attributes
8839 @subsection Constant Attributes
8840 @cindex constant attributes
8842 A special form of @code{define_attr}, where the expression for the
8843 default value is a @code{const} expression, indicates an attribute that
8844 is constant for a given run of the compiler. Constant attributes may be
8845 used to specify which variety of processor is used. For example,
8848 (define_attr "cpu" "m88100,m88110,m88000"
8850 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8851 (symbol_ref "TARGET_88110") (const_string "m88110")]
8852 (const_string "m88000"))))
8854 (define_attr "memory" "fast,slow"
8856 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8857 (const_string "fast")
8858 (const_string "slow"))))
8861 The routine generated for constant attributes has no parameters as it
8862 does not depend on any particular insn. RTL expressions used to define
8863 the value of a constant attribute may use the @code{symbol_ref} form,
8864 but may not use either the @code{match_operand} form or @code{eq_attr}
8865 forms involving insn attributes.
8869 @node Mnemonic Attribute
8870 @subsection Mnemonic Attribute
8871 @cindex mnemonic attribute
8873 The @code{mnemonic} attribute is a string type attribute holding the
8874 instruction mnemonic for an insn alternative. The attribute values
8875 will automatically be generated by the machine description parser if
8876 there is an attribute definition in the md file:
8879 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8882 The default value can be freely chosen as long as it does not collide
8883 with any of the instruction mnemonics. This value will be used
8884 whenever the machine description parser is not able to determine the
8885 mnemonic string. This might be the case for output templates
8886 containing more than a single instruction as in
8887 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8889 The @code{mnemonic} attribute set is not generated automatically if the
8890 instruction string is generated via C code.
8892 An existing @code{mnemonic} attribute set in an insn definition will not
8893 be overriden by the md file parser. That way it is possible to
8894 manually set the instruction mnemonics for the cases where the md file
8895 parser fails to determine it automatically.
8897 The @code{mnemonic} attribute is useful for dealing with instruction
8898 specific properties in the pipeline description without defining
8899 additional insn attributes.
8902 (define_attr "ooo_expanded" ""
8903 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8911 @subsection Delay Slot Scheduling
8912 @cindex delay slots, defining
8914 The insn attribute mechanism can be used to specify the requirements for
8915 delay slots, if any, on a target machine. An instruction is said to
8916 require a @dfn{delay slot} if some instructions that are physically
8917 after the instruction are executed as if they were located before it.
8918 Classic examples are branch and call instructions, which often execute
8919 the following instruction before the branch or call is performed.
8921 On some machines, conditional branch instructions can optionally
8922 @dfn{annul} instructions in the delay slot. This means that the
8923 instruction will not be executed for certain branch outcomes. Both
8924 instructions that annul if the branch is true and instructions that
8925 annul if the branch is false are supported.
8927 Delay slot scheduling differs from instruction scheduling in that
8928 determining whether an instruction needs a delay slot is dependent only
8929 on the type of instruction being generated, not on data flow between the
8930 instructions. See the next section for a discussion of data-dependent
8931 instruction scheduling.
8933 @findex define_delay
8934 The requirement of an insn needing one or more delay slots is indicated
8935 via the @code{define_delay} expression. It has the following form:
8938 (define_delay @var{test}
8939 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8940 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8944 @var{test} is an attribute test that indicates whether this
8945 @code{define_delay} applies to a particular insn. If so, the number of
8946 required delay slots is determined by the length of the vector specified
8947 as the second argument. An insn placed in delay slot @var{n} must
8948 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8949 attribute test that specifies which insns may be annulled if the branch
8950 is true. Similarly, @var{annul-false-n} specifies which insns in the
8951 delay slot may be annulled if the branch is false. If annulling is not
8952 supported for that delay slot, @code{(nil)} should be coded.
8954 For example, in the common case where branch and call insns require
8955 a single delay slot, which may contain any insn other than a branch or
8956 call, the following would be placed in the @file{md} file:
8959 (define_delay (eq_attr "type" "branch,call")
8960 [(eq_attr "type" "!branch,call") (nil) (nil)])
8963 Multiple @code{define_delay} expressions may be specified. In this
8964 case, each such expression specifies different delay slot requirements
8965 and there must be no insn for which tests in two @code{define_delay}
8966 expressions are both true.
8968 For example, if we have a machine that requires one delay slot for branches
8969 but two for calls, no delay slot can contain a branch or call insn,
8970 and any valid insn in the delay slot for the branch can be annulled if the
8971 branch is true, we might represent this as follows:
8974 (define_delay (eq_attr "type" "branch")
8975 [(eq_attr "type" "!branch,call")
8976 (eq_attr "type" "!branch,call")
8979 (define_delay (eq_attr "type" "call")
8980 [(eq_attr "type" "!branch,call") (nil) (nil)
8981 (eq_attr "type" "!branch,call") (nil) (nil)])
8983 @c the above is *still* too long. --mew 4feb93
8987 @node Processor pipeline description
8988 @subsection Specifying processor pipeline description
8989 @cindex processor pipeline description
8990 @cindex processor functional units
8991 @cindex instruction latency time
8992 @cindex interlock delays
8993 @cindex data dependence delays
8994 @cindex reservation delays
8995 @cindex pipeline hazard recognizer
8996 @cindex automaton based pipeline description
8997 @cindex regular expressions
8998 @cindex deterministic finite state automaton
8999 @cindex automaton based scheduler
9003 To achieve better performance, most modern processors
9004 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
9005 processors) have many @dfn{functional units} on which several
9006 instructions can be executed simultaneously. An instruction starts
9007 execution if its issue conditions are satisfied. If not, the
9008 instruction is stalled until its conditions are satisfied. Such
9009 @dfn{interlock (pipeline) delay} causes interruption of the fetching
9010 of successor instructions (or demands nop instructions, e.g.@: for some
9013 There are two major kinds of interlock delays in modern processors.
9014 The first one is a data dependence delay determining @dfn{instruction
9015 latency time}. The instruction execution is not started until all
9016 source data have been evaluated by prior instructions (there are more
9017 complex cases when the instruction execution starts even when the data
9018 are not available but will be ready in given time after the
9019 instruction execution start). Taking the data dependence delays into
9020 account is simple. The data dependence (true, output, and
9021 anti-dependence) delay between two instructions is given by a
9022 constant. In most cases this approach is adequate. The second kind
9023 of interlock delays is a reservation delay. The reservation delay
9024 means that two instructions under execution will be in need of shared
9025 processors resources, i.e.@: buses, internal registers, and/or
9026 functional units, which are reserved for some time. Taking this kind
9027 of delay into account is complex especially for modern @acronym{RISC}
9030 The task of exploiting more processor parallelism is solved by an
9031 instruction scheduler. For a better solution to this problem, the
9032 instruction scheduler has to have an adequate description of the
9033 processor parallelism (or @dfn{pipeline description}). GCC
9034 machine descriptions describe processor parallelism and functional
9035 unit reservations for groups of instructions with the aid of
9036 @dfn{regular expressions}.
9038 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
9039 figure out the possibility of the instruction issue by the processor
9040 on a given simulated processor cycle. The pipeline hazard recognizer is
9041 automatically generated from the processor pipeline description. The
9042 pipeline hazard recognizer generated from the machine description
9043 is based on a deterministic finite state automaton (@acronym{DFA}):
9044 the instruction issue is possible if there is a transition from one
9045 automaton state to another one. This algorithm is very fast, and
9046 furthermore, its speed is not dependent on processor
9047 complexity@footnote{However, the size of the automaton depends on
9048 processor complexity. To limit this effect, machine descriptions
9049 can split orthogonal parts of the machine description among several
9050 automata: but then, since each of these must be stepped independently,
9051 this does cause a small decrease in the algorithm's performance.}.
9053 @cindex automaton based pipeline description
9054 The rest of this section describes the directives that constitute
9055 an automaton-based processor pipeline description. The order of
9056 these constructions within the machine description file is not
9059 @findex define_automaton
9060 @cindex pipeline hazard recognizer
9061 The following optional construction describes names of automata
9062 generated and used for the pipeline hazards recognition. Sometimes
9063 the generated finite state automaton used by the pipeline hazard
9064 recognizer is large. If we use more than one automaton and bind functional
9065 units to the automata, the total size of the automata is usually
9066 less than the size of the single automaton. If there is no one such
9067 construction, only one finite state automaton is generated.
9070 (define_automaton @var{automata-names})
9073 @var{automata-names} is a string giving names of the automata. The
9074 names are separated by commas. All the automata should have unique names.
9075 The automaton name is used in the constructions @code{define_cpu_unit} and
9076 @code{define_query_cpu_unit}.
9078 @findex define_cpu_unit
9079 @cindex processor functional units
9080 Each processor functional unit used in the description of instruction
9081 reservations should be described by the following construction.
9084 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
9087 @var{unit-names} is a string giving the names of the functional units
9088 separated by commas. Don't use name @samp{nothing}, it is reserved
9091 @var{automaton-name} is a string giving the name of the automaton with
9092 which the unit is bound. The automaton should be described in
9093 construction @code{define_automaton}. You should give
9094 @dfn{automaton-name}, if there is a defined automaton.
9096 The assignment of units to automata are constrained by the uses of the
9097 units in insn reservations. The most important constraint is: if a
9098 unit reservation is present on a particular cycle of an alternative
9099 for an insn reservation, then some unit from the same automaton must
9100 be present on the same cycle for the other alternatives of the insn
9101 reservation. The rest of the constraints are mentioned in the
9102 description of the subsequent constructions.
9104 @findex define_query_cpu_unit
9105 @cindex querying function unit reservations
9106 The following construction describes CPU functional units analogously
9107 to @code{define_cpu_unit}. The reservation of such units can be
9108 queried for an automaton state. The instruction scheduler never
9109 queries reservation of functional units for given automaton state. So
9110 as a rule, you don't need this construction. This construction could
9111 be used for future code generation goals (e.g.@: to generate
9112 @acronym{VLIW} insn templates).
9115 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
9118 @var{unit-names} is a string giving names of the functional units
9119 separated by commas.
9121 @var{automaton-name} is a string giving the name of the automaton with
9122 which the unit is bound.
9124 @findex define_insn_reservation
9125 @cindex instruction latency time
9126 @cindex regular expressions
9128 The following construction is the major one to describe pipeline
9129 characteristics of an instruction.
9132 (define_insn_reservation @var{insn-name} @var{default_latency}
9133 @var{condition} @var{regexp})
9136 @var{default_latency} is a number giving latency time of the
9137 instruction. There is an important difference between the old
9138 description and the automaton based pipeline description. The latency
9139 time is used for all dependencies when we use the old description. In
9140 the automaton based pipeline description, the given latency time is only
9141 used for true dependencies. The cost of anti-dependencies is always
9142 zero and the cost of output dependencies is the difference between
9143 latency times of the producing and consuming insns (if the difference
9144 is negative, the cost is considered to be zero). You can always
9145 change the default costs for any description by using the target hook
9146 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
9148 @var{insn-name} is a string giving the internal name of the insn. The
9149 internal names are used in constructions @code{define_bypass} and in
9150 the automaton description file generated for debugging. The internal
9151 name has nothing in common with the names in @code{define_insn}. It is a
9152 good practice to use insn classes described in the processor manual.
9154 @var{condition} defines what RTL insns are described by this
9155 construction. You should remember that you will be in trouble if
9156 @var{condition} for two or more different
9157 @code{define_insn_reservation} constructions is TRUE for an insn. In
9158 this case what reservation will be used for the insn is not defined.
9159 Such cases are not checked during generation of the pipeline hazards
9160 recognizer because in general recognizing that two conditions may have
9161 the same value is quite difficult (especially if the conditions
9162 contain @code{symbol_ref}). It is also not checked during the
9163 pipeline hazard recognizer work because it would slow down the
9164 recognizer considerably.
9166 @var{regexp} is a string describing the reservation of the cpu's functional
9167 units by the instruction. The reservations are described by a regular
9168 expression according to the following syntax:
9171 regexp = regexp "," oneof
9174 oneof = oneof "|" allof
9177 allof = allof "+" repeat
9180 repeat = element "*" number
9183 element = cpu_function_unit_name
9192 @samp{,} is used for describing the start of the next cycle in
9196 @samp{|} is used for describing a reservation described by the first
9197 regular expression @strong{or} a reservation described by the second
9198 regular expression @strong{or} etc.
9201 @samp{+} is used for describing a reservation described by the first
9202 regular expression @strong{and} a reservation described by the
9203 second regular expression @strong{and} etc.
9206 @samp{*} is used for convenience and simply means a sequence in which
9207 the regular expression are repeated @var{number} times with cycle
9208 advancing (see @samp{,}).
9211 @samp{cpu_function_unit_name} denotes reservation of the named
9215 @samp{reservation_name} --- see description of construction
9216 @samp{define_reservation}.
9219 @samp{nothing} denotes no unit reservations.
9222 @findex define_reservation
9223 Sometimes unit reservations for different insns contain common parts.
9224 In such case, you can simplify the pipeline description by describing
9225 the common part by the following construction
9228 (define_reservation @var{reservation-name} @var{regexp})
9231 @var{reservation-name} is a string giving name of @var{regexp}.
9232 Functional unit names and reservation names are in the same name
9233 space. So the reservation names should be different from the
9234 functional unit names and can not be the reserved name @samp{nothing}.
9236 @findex define_bypass
9237 @cindex instruction latency time
9239 The following construction is used to describe exceptions in the
9240 latency time for given instruction pair. This is so called bypasses.
9243 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
9247 @var{number} defines when the result generated by the instructions
9248 given in string @var{out_insn_names} will be ready for the
9249 instructions given in string @var{in_insn_names}. Each of these
9250 strings is a comma-separated list of filename-style globs and
9251 they refer to the names of @code{define_insn_reservation}s.
9254 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
9256 defines a bypass between instructions that start with
9257 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
9260 @var{guard} is an optional string giving the name of a C function which
9261 defines an additional guard for the bypass. The function will get the
9262 two insns as parameters. If the function returns zero the bypass will
9263 be ignored for this case. The additional guard is necessary to
9264 recognize complicated bypasses, e.g.@: when the consumer is only an address
9265 of insn @samp{store} (not a stored value).
9267 If there are more one bypass with the same output and input insns, the
9268 chosen bypass is the first bypass with a guard in description whose
9269 guard function returns nonzero. If there is no such bypass, then
9270 bypass without the guard function is chosen.
9272 @findex exclusion_set
9273 @findex presence_set
9274 @findex final_presence_set
9276 @findex final_absence_set
9279 The following five constructions are usually used to describe
9280 @acronym{VLIW} processors, or more precisely, to describe a placement
9281 of small instructions into @acronym{VLIW} instruction slots. They
9282 can be used for @acronym{RISC} processors, too.
9285 (exclusion_set @var{unit-names} @var{unit-names})
9286 (presence_set @var{unit-names} @var{patterns})
9287 (final_presence_set @var{unit-names} @var{patterns})
9288 (absence_set @var{unit-names} @var{patterns})
9289 (final_absence_set @var{unit-names} @var{patterns})
9292 @var{unit-names} is a string giving names of functional units
9293 separated by commas.
9295 @var{patterns} is a string giving patterns of functional units
9296 separated by comma. Currently pattern is one unit or units
9297 separated by white-spaces.
9299 The first construction (@samp{exclusion_set}) means that each
9300 functional unit in the first string can not be reserved simultaneously
9301 with a unit whose name is in the second string and vice versa. For
9302 example, the construction is useful for describing processors
9303 (e.g.@: some SPARC processors) with a fully pipelined floating point
9304 functional unit which can execute simultaneously only single floating
9305 point insns or only double floating point insns.
9307 The second construction (@samp{presence_set}) means that each
9308 functional unit in the first string can not be reserved unless at
9309 least one of pattern of units whose names are in the second string is
9310 reserved. This is an asymmetric relation. For example, it is useful
9311 for description that @acronym{VLIW} @samp{slot1} is reserved after
9312 @samp{slot0} reservation. We could describe it by the following
9316 (presence_set "slot1" "slot0")
9319 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
9320 reservation. In this case we could write
9323 (presence_set "slot1" "slot0 b0")
9326 The third construction (@samp{final_presence_set}) is analogous to
9327 @samp{presence_set}. The difference between them is when checking is
9328 done. When an instruction is issued in given automaton state
9329 reflecting all current and planned unit reservations, the automaton
9330 state is changed. The first state is a source state, the second one
9331 is a result state. Checking for @samp{presence_set} is done on the
9332 source state reservation, checking for @samp{final_presence_set} is
9333 done on the result reservation. This construction is useful to
9334 describe a reservation which is actually two subsequent reservations.
9335 For example, if we use
9338 (presence_set "slot1" "slot0")
9341 the following insn will be never issued (because @samp{slot1} requires
9342 @samp{slot0} which is absent in the source state).
9345 (define_reservation "insn_and_nop" "slot0 + slot1")
9348 but it can be issued if we use analogous @samp{final_presence_set}.
9350 The forth construction (@samp{absence_set}) means that each functional
9351 unit in the first string can be reserved only if each pattern of units
9352 whose names are in the second string is not reserved. This is an
9353 asymmetric relation (actually @samp{exclusion_set} is analogous to
9354 this one but it is symmetric). For example it might be useful in a
9355 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
9356 after either @samp{slot1} or @samp{slot2} have been reserved. This
9357 can be described as:
9360 (absence_set "slot0" "slot1, slot2")
9363 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
9364 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
9365 this case we could write
9368 (absence_set "slot2" "slot0 b0, slot1 b1")
9371 All functional units mentioned in a set should belong to the same
9374 The last construction (@samp{final_absence_set}) is analogous to
9375 @samp{absence_set} but checking is done on the result (state)
9376 reservation. See comments for @samp{final_presence_set}.
9378 @findex automata_option
9379 @cindex deterministic finite state automaton
9380 @cindex nondeterministic finite state automaton
9381 @cindex finite state automaton minimization
9382 You can control the generator of the pipeline hazard recognizer with
9383 the following construction.
9386 (automata_option @var{options})
9389 @var{options} is a string giving options which affect the generated
9390 code. Currently there are the following options:
9394 @dfn{no-minimization} makes no minimization of the automaton. This is
9395 only worth to do when we are debugging the description and need to
9396 look more accurately at reservations of states.
9399 @dfn{time} means printing time statistics about the generation of
9403 @dfn{stats} means printing statistics about the generated automata
9404 such as the number of DFA states, NDFA states and arcs.
9407 @dfn{v} means a generation of the file describing the result automata.
9408 The file has suffix @samp{.dfa} and can be used for the description
9409 verification and debugging.
9412 @dfn{w} means a generation of warning instead of error for
9413 non-critical errors.
9416 @dfn{no-comb-vect} prevents the automaton generator from generating
9417 two data structures and comparing them for space efficiency. Using
9418 a comb vector to represent transitions may be better, but it can be
9419 very expensive to construct. This option is useful if the build
9420 process spends an unacceptably long time in genautomata.
9423 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9424 the treatment of operator @samp{|} in the regular expressions. The
9425 usual treatment of the operator is to try the first alternative and,
9426 if the reservation is not possible, the second alternative. The
9427 nondeterministic treatment means trying all alternatives, some of them
9428 may be rejected by reservations in the subsequent insns.
9431 @dfn{collapse-ndfa} modifies the behavior of the generator when
9432 producing an automaton. An additional state transition to collapse a
9433 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9434 state is generated. It can be triggered by passing @code{const0_rtx} to
9435 state_transition. In such an automaton, cycle advance transitions are
9436 available only for these collapsed states. This option is useful for
9437 ports that want to use the @code{ndfa} option, but also want to use
9438 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9441 @dfn{progress} means output of a progress bar showing how many states
9442 were generated so far for automaton being processed. This is useful
9443 during debugging a @acronym{DFA} description. If you see too many
9444 generated states, you could interrupt the generator of the pipeline
9445 hazard recognizer and try to figure out a reason for generation of the
9449 As an example, consider a superscalar @acronym{RISC} machine which can
9450 issue three insns (two integer insns and one floating point insn) on
9451 the cycle but can finish only two insns. To describe this, we define
9452 the following functional units.
9455 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9456 (define_cpu_unit "port0, port1")
9459 All simple integer insns can be executed in any integer pipeline and
9460 their result is ready in two cycles. The simple integer insns are
9461 issued into the first pipeline unless it is reserved, otherwise they
9462 are issued into the second pipeline. Integer division and
9463 multiplication insns can be executed only in the second integer
9464 pipeline and their results are ready correspondingly in 8 and 4
9465 cycles. The integer division is not pipelined, i.e.@: the subsequent
9466 integer division insn can not be issued until the current division
9467 insn finished. Floating point insns are fully pipelined and their
9468 results are ready in 3 cycles. Where the result of a floating point
9469 insn is used by an integer insn, an additional delay of one cycle is
9470 incurred. To describe all of this we could specify
9473 (define_cpu_unit "div")
9475 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9476 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9478 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9479 "i1_pipeline, nothing*2, (port0 | port1)")
9481 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9482 "i1_pipeline, div*7, div + (port0 | port1)")
9484 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9485 "f_pipeline, nothing, (port0 | port1))
9487 (define_bypass 4 "float" "simple,mult,div")
9490 To simplify the description we could describe the following reservation
9493 (define_reservation "finish" "port0|port1")
9496 and use it in all @code{define_insn_reservation} as in the following
9500 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9501 "(i0_pipeline | i1_pipeline), finish")
9507 @node Conditional Execution
9508 @section Conditional Execution
9509 @cindex conditional execution
9512 A number of architectures provide for some form of conditional
9513 execution, or predication. The hallmark of this feature is the
9514 ability to nullify most of the instructions in the instruction set.
9515 When the instruction set is large and not entirely symmetric, it
9516 can be quite tedious to describe these forms directly in the
9517 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9519 @findex define_cond_exec
9522 [@var{predicate-pattern}]
9524 "@var{output-template}"
9525 "@var{optional-insn-attribues}")
9528 @var{predicate-pattern} is the condition that must be true for the
9529 insn to be executed at runtime and should match a relational operator.
9530 One can use @code{match_operator} to match several relational operators
9531 at once. Any @code{match_operand} operands must have no more than one
9534 @var{condition} is a C expression that must be true for the generated
9537 @findex current_insn_predicate
9538 @var{output-template} is a string similar to the @code{define_insn}
9539 output template (@pxref{Output Template}), except that the @samp{*}
9540 and @samp{@@} special cases do not apply. This is only useful if the
9541 assembly text for the predicate is a simple prefix to the main insn.
9542 In order to handle the general case, there is a global variable
9543 @code{current_insn_predicate} that will contain the entire predicate
9544 if the current insn is predicated, and will otherwise be @code{NULL}.
9546 @var{optional-insn-attributes} is an optional vector of attributes that gets
9547 appended to the insn attributes of the produced cond_exec rtx. It can
9548 be used to add some distinguishing attribute to cond_exec rtxs produced
9549 that way. An example usage would be to use this attribute in conjunction
9550 with attributes on the main pattern to disable particular alternatives under
9553 When @code{define_cond_exec} is used, an implicit reference to
9554 the @code{predicable} instruction attribute is made.
9555 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9556 exactly two elements in its @var{list-of-values}), with the possible
9557 values being @code{no} and @code{yes}. The default and all uses in
9558 the insns must be a simple constant, not a complex expressions. It
9559 may, however, depend on the alternative, by using a comma-separated
9560 list of values. If that is the case, the port should also define an
9561 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9562 should also allow only @code{no} and @code{yes} as its values.
9564 For each @code{define_insn} for which the @code{predicable}
9565 attribute is true, a new @code{define_insn} pattern will be
9566 generated that matches a predicated version of the instruction.
9570 (define_insn "addsi"
9571 [(set (match_operand:SI 0 "register_operand" "r")
9572 (plus:SI (match_operand:SI 1 "register_operand" "r")
9573 (match_operand:SI 2 "register_operand" "r")))]
9578 [(ne (match_operand:CC 0 "register_operand" "c")
9585 generates a new pattern
9590 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9591 (set (match_operand:SI 0 "register_operand" "r")
9592 (plus:SI (match_operand:SI 1 "register_operand" "r")
9593 (match_operand:SI 2 "register_operand" "r"))))]
9594 "(@var{test2}) && (@var{test1})"
9595 "(%3) add %2,%1,%0")
9601 @section RTL Templates Transformations
9602 @cindex define_subst
9604 For some hardware architectures there are common cases when the RTL
9605 templates for the instructions can be derived from the other RTL
9606 templates using simple transformations. E.g., @file{i386.md} contains
9607 an RTL template for the ordinary @code{sub} instruction---
9608 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9609 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9610 implemented by a single meta-template capable of generating a modified
9611 case based on the initial one:
9613 @findex define_subst
9615 (define_subst "@var{name}"
9616 [@var{input-template}]
9618 [@var{output-template}])
9620 @var{input-template} is a pattern describing the source RTL template,
9621 which will be transformed.
9623 @var{condition} is a C expression that is conjunct with the condition
9624 from the input-template to generate a condition to be used in the
9627 @var{output-template} is a pattern that will be used in the resulting
9630 @code{define_subst} mechanism is tightly coupled with the notion of the
9631 subst attribute (@pxref{Subst Iterators}). The use of
9632 @code{define_subst} is triggered by a reference to a subst attribute in
9633 the transforming RTL template. This reference initiates duplication of
9634 the source RTL template and substitution of the attributes with their
9635 values. The source RTL template is left unchanged, while the copy is
9636 transformed by @code{define_subst}. This transformation can fail in the
9637 case when the source RTL template is not matched against the
9638 input-template of the @code{define_subst}. In such case the copy is
9641 @code{define_subst} can be used only in @code{define_insn} and
9642 @code{define_expand}, it cannot be used in other expressions (e.g. in
9643 @code{define_insn_and_split}).
9646 * Define Subst Example:: Example of @code{define_subst} work.
9647 * Define Subst Pattern Matching:: Process of template comparison.
9648 * Define Subst Output Template:: Generation of output template.
9651 @node Define Subst Example
9652 @subsection @code{define_subst} Example
9653 @cindex define_subst
9655 To illustrate how @code{define_subst} works, let us examine a simple
9656 template transformation.
9658 Suppose there are two kinds of instructions: one that touches flags and
9659 the other that does not. The instructions of the second type could be
9660 generated with the following @code{define_subst}:
9663 (define_subst "add_clobber_subst"
9664 [(set (match_operand:SI 0 "" "")
9665 (match_operand:SI 1 "" ""))]
9669 (clobber (reg:CC FLAGS_REG))]
9672 This @code{define_subst} can be applied to any RTL pattern containing
9673 @code{set} of mode SI and generates a copy with clobber when it is
9676 Assume there is an RTL template for a @code{max} instruction to be used
9677 in @code{define_subst} mentioned above:
9680 (define_insn "maxsi"
9681 [(set (match_operand:SI 0 "register_operand" "=r")
9683 (match_operand:SI 1 "register_operand" "r")
9684 (match_operand:SI 2 "register_operand" "r")))]
9686 "max\t@{%2, %1, %0|%0, %1, %2@}"
9690 To mark the RTL template for @code{define_subst} application,
9691 subst-attributes are used. They should be declared in advance:
9694 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9697 Here @samp{add_clobber_name} is the attribute name,
9698 @samp{add_clobber_subst} is the name of the corresponding
9699 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9700 attribute value that would be substituted into the unchanged version of
9701 the source RTL template, and the last argument (@samp{_clobber}) is the
9702 value that would be substituted into the second, transformed,
9703 version of the RTL template.
9705 Once the subst-attribute has been defined, it should be used in RTL
9706 templates which need to be processed by the @code{define_subst}. So,
9707 the original RTL template should be changed:
9710 (define_insn "maxsi<add_clobber_name>"
9711 [(set (match_operand:SI 0 "register_operand" "=r")
9713 (match_operand:SI 1 "register_operand" "r")
9714 (match_operand:SI 2 "register_operand" "r")))]
9716 "max\t@{%2, %1, %0|%0, %1, %2@}"
9720 The result of the @code{define_subst} usage would look like the following:
9723 (define_insn "maxsi_noclobber"
9724 [(set (match_operand:SI 0 "register_operand" "=r")
9726 (match_operand:SI 1 "register_operand" "r")
9727 (match_operand:SI 2 "register_operand" "r")))]
9729 "max\t@{%2, %1, %0|%0, %1, %2@}"
9731 (define_insn "maxsi_clobber"
9732 [(set (match_operand:SI 0 "register_operand" "=r")
9734 (match_operand:SI 1 "register_operand" "r")
9735 (match_operand:SI 2 "register_operand" "r")))
9736 (clobber (reg:CC FLAGS_REG))]
9738 "max\t@{%2, %1, %0|%0, %1, %2@}"
9742 @node Define Subst Pattern Matching
9743 @subsection Pattern Matching in @code{define_subst}
9744 @cindex define_subst
9746 All expressions, allowed in @code{define_insn} or @code{define_expand},
9747 are allowed in the input-template of @code{define_subst}, except
9748 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9749 meanings of expressions in the input-template were changed:
9751 @code{match_operand} matches any expression (possibly, a subtree in
9752 RTL-template), if modes of the @code{match_operand} and this expression
9753 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9754 this expression is @code{match_dup}, @code{match_op_dup}. If the
9755 expression is @code{match_operand} too, and predicate of
9756 @code{match_operand} from the input pattern is not empty, then the
9757 predicates are compared. That can be used for more accurate filtering
9758 of accepted RTL-templates.
9760 @code{match_operator} matches common operators (like @code{plus},
9761 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9762 @code{match_operator}s from the original pattern if the modes match and
9763 @code{match_operator} from the input pattern has the same number of
9764 operands as the operator from the original pattern.
9766 @node Define Subst Output Template
9767 @subsection Generation of output template in @code{define_subst}
9768 @cindex define_subst
9770 If all necessary checks for @code{define_subst} application pass, a new
9771 RTL-pattern, based on the output-template, is created to replace the old
9772 template. Like in input-patterns, meanings of some RTL expressions are
9773 changed when they are used in output-patterns of a @code{define_subst}.
9774 Thus, @code{match_dup} is used for copying the whole expression from the
9775 original pattern, which matched corresponding @code{match_operand} from
9778 @code{match_dup N} is used in the output template to be replaced with
9779 the expression from the original pattern, which matched
9780 @code{match_operand N} from the input pattern. As a consequence,
9781 @code{match_dup} cannot be used to point to @code{match_operand}s from
9782 the output pattern, it should always refer to a @code{match_operand}
9783 from the input pattern.
9785 In the output template one can refer to the expressions from the
9786 original pattern and create new ones. For instance, some operands could
9787 be added by means of standard @code{match_operand}.
9789 After replacing @code{match_dup} with some RTL-subtree from the original
9790 pattern, it could happen that several @code{match_operand}s in the
9791 output pattern have the same indexes. It is unknown, how many and what
9792 indexes would be used in the expression which would replace
9793 @code{match_dup}, so such conflicts in indexes are inevitable. To
9794 overcome this issue, @code{match_operands} and @code{match_operators},
9795 which were introduced into the output pattern, are renumerated when all
9796 @code{match_dup}s are replaced.
9798 Number of alternatives in @code{match_operand}s introduced into the
9799 output template @code{M} could differ from the number of alternatives in
9800 the original pattern @code{N}, so in the resultant pattern there would
9801 be @code{N*M} alternatives. Thus, constraints from the original pattern
9802 would be duplicated @code{N} times, constraints from the output pattern
9803 would be duplicated @code{M} times, producing all possible combinations.
9807 @node Constant Definitions
9808 @section Constant Definitions
9809 @cindex constant definitions
9810 @findex define_constants
9812 Using literal constants inside instruction patterns reduces legibility and
9813 can be a maintenance problem.
9815 To overcome this problem, you may use the @code{define_constants}
9816 expression. It contains a vector of name-value pairs. From that
9817 point on, wherever any of the names appears in the MD file, it is as
9818 if the corresponding value had been written instead. You may use
9819 @code{define_constants} multiple times; each appearance adds more
9820 constants to the table. It is an error to redefine a constant with
9823 To come back to the a29k load multiple example, instead of
9827 [(match_parallel 0 "load_multiple_operation"
9828 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9829 (match_operand:SI 2 "memory_operand" "m"))
9831 (clobber (reg:SI 179))])]
9847 [(match_parallel 0 "load_multiple_operation"
9848 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9849 (match_operand:SI 2 "memory_operand" "m"))
9851 (clobber (reg:SI R_CR))])]
9856 The constants that are defined with a define_constant are also output
9857 in the insn-codes.h header file as #defines.
9859 @cindex enumerations
9860 @findex define_c_enum
9861 You can also use the machine description file to define enumerations.
9862 Like the constants defined by @code{define_constant}, these enumerations
9863 are visible to both the machine description file and the main C code.
9865 The syntax is as follows:
9868 (define_c_enum "@var{name}" [
9876 This definition causes the equivalent of the following C code to appear
9877 in @file{insn-constants.h}:
9884 @var{valuen} = @var{n}
9886 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9889 where @var{cname} is the capitalized form of @var{name}.
9890 It also makes each @var{valuei} available in the machine description
9891 file, just as if it had been declared with:
9894 (define_constants [(@var{valuei} @var{i})])
9897 Each @var{valuei} is usually an upper-case identifier and usually
9898 begins with @var{cname}.
9900 You can split the enumeration definition into as many statements as
9901 you like. The above example is directly equivalent to:
9904 (define_c_enum "@var{name}" [@var{value0}])
9905 (define_c_enum "@var{name}" [@var{value1}])
9907 (define_c_enum "@var{name}" [@var{valuen}])
9910 Splitting the enumeration helps to improve the modularity of each
9911 individual @code{.md} file. For example, if a port defines its
9912 synchronization instructions in a separate @file{sync.md} file,
9913 it is convenient to define all synchronization-specific enumeration
9914 values in @file{sync.md} rather than in the main @file{.md} file.
9916 Some enumeration names have special significance to GCC:
9920 @findex unspec_volatile
9921 If an enumeration called @code{unspecv} is defined, GCC will use it
9922 when printing out @code{unspec_volatile} expressions. For example:
9925 (define_c_enum "unspecv" [
9930 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9933 (unspec_volatile ... UNSPECV_BLOCKAGE)
9938 If an enumeration called @code{unspec} is defined, GCC will use
9939 it when printing out @code{unspec} expressions. GCC will also use
9940 it when printing out @code{unspec_volatile} expressions unless an
9941 @code{unspecv} enumeration is also defined. You can therefore
9942 decide whether to keep separate enumerations for volatile and
9943 non-volatile expressions or whether to use the same enumeration
9948 @anchor{define_enum}
9949 Another way of defining an enumeration is to use @code{define_enum}:
9952 (define_enum "@var{name}" [
9960 This directive implies:
9963 (define_c_enum "@var{name}" [
9964 @var{cname}_@var{cvalue0}
9965 @var{cname}_@var{cvalue1}
9967 @var{cname}_@var{cvaluen}
9971 @findex define_enum_attr
9972 where @var{cvaluei} is the capitalized form of @var{valuei}.
9973 However, unlike @code{define_c_enum}, the enumerations defined
9974 by @code{define_enum} can be used in attribute specifications
9975 (@pxref{define_enum_attr}).
9980 @cindex iterators in @file{.md} files
9982 Ports often need to define similar patterns for more than one machine
9983 mode or for more than one rtx code. GCC provides some simple iterator
9984 facilities to make this process easier.
9987 * Mode Iterators:: Generating variations of patterns for different modes.
9988 * Code Iterators:: Doing the same for codes.
9989 * Int Iterators:: Doing the same for integers.
9990 * Subst Iterators:: Generating variations of patterns for define_subst.
9993 @node Mode Iterators
9994 @subsection Mode Iterators
9995 @cindex mode iterators in @file{.md} files
9997 Ports often need to define similar patterns for two or more different modes.
10002 If a processor has hardware support for both single and double
10003 floating-point arithmetic, the @code{SFmode} patterns tend to be
10004 very similar to the @code{DFmode} ones.
10007 If a port uses @code{SImode} pointers in one configuration and
10008 @code{DImode} pointers in another, it will usually have very similar
10009 @code{SImode} and @code{DImode} patterns for manipulating pointers.
10012 Mode iterators allow several patterns to be instantiated from one
10013 @file{.md} file template. They can be used with any type of
10014 rtx-based construct, such as a @code{define_insn},
10015 @code{define_split}, or @code{define_peephole2}.
10018 * Defining Mode Iterators:: Defining a new mode iterator.
10019 * Substitutions:: Combining mode iterators with substitutions
10020 * Examples:: Examples
10023 @node Defining Mode Iterators
10024 @subsubsection Defining Mode Iterators
10025 @findex define_mode_iterator
10027 The syntax for defining a mode iterator is:
10030 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
10033 This allows subsequent @file{.md} file constructs to use the mode suffix
10034 @code{:@var{name}}. Every construct that does so will be expanded
10035 @var{n} times, once with every use of @code{:@var{name}} replaced by
10036 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
10037 and so on. In the expansion for a particular @var{modei}, every
10038 C condition will also require that @var{condi} be true.
10043 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10046 defines a new mode suffix @code{:P}. Every construct that uses
10047 @code{:P} will be expanded twice, once with every @code{:P} replaced
10048 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
10049 The @code{:SI} version will only apply if @code{Pmode == SImode} and
10050 the @code{:DI} version will only apply if @code{Pmode == DImode}.
10052 As with other @file{.md} conditions, an empty string is treated
10053 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
10054 to @code{@var{mode}}. For example:
10057 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10060 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
10061 but that the @code{:SI} expansion has no such constraint.
10063 Iterators are applied in the order they are defined. This can be
10064 significant if two iterators are used in a construct that requires
10065 substitutions. @xref{Substitutions}.
10067 @node Substitutions
10068 @subsubsection Substitution in Mode Iterators
10069 @findex define_mode_attr
10071 If an @file{.md} file construct uses mode iterators, each version of the
10072 construct will often need slightly different strings or modes. For
10077 When a @code{define_expand} defines several @code{add@var{m}3} patterns
10078 (@pxref{Standard Names}), each expander will need to use the
10079 appropriate mode name for @var{m}.
10082 When a @code{define_insn} defines several instruction patterns,
10083 each instruction will often use a different assembler mnemonic.
10086 When a @code{define_insn} requires operands with different modes,
10087 using an iterator for one of the operand modes usually requires a specific
10088 mode for the other operand(s).
10091 GCC supports such variations through a system of ``mode attributes''.
10092 There are two standard attributes: @code{mode}, which is the name of
10093 the mode in lower case, and @code{MODE}, which is the same thing in
10094 upper case. You can define other attributes using:
10097 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
10100 where @var{name} is the name of the attribute and @var{valuei}
10101 is the value associated with @var{modei}.
10103 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
10104 each string and mode in the pattern for sequences of the form
10105 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
10106 mode attribute. If the attribute is defined for @var{mode}, the whole
10107 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
10110 For example, suppose an @file{.md} file has:
10113 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
10114 (define_mode_attr load [(SI "lw") (DI "ld")])
10117 If one of the patterns that uses @code{:P} contains the string
10118 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
10119 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
10120 @code{"ld\t%0,%1"}.
10122 Here is an example of using an attribute for a mode:
10125 (define_mode_iterator LONG [SI DI])
10126 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
10127 (define_insn @dots{}
10128 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
10131 The @code{@var{iterator}:} prefix may be omitted, in which case the
10132 substitution will be attempted for every iterator expansion.
10135 @subsubsection Mode Iterator Examples
10137 Here is an example from the MIPS port. It defines the following
10138 modes and attributes (among others):
10141 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
10142 (define_mode_attr d [(SI "") (DI "d")])
10145 and uses the following template to define both @code{subsi3}
10149 (define_insn "sub<mode>3"
10150 [(set (match_operand:GPR 0 "register_operand" "=d")
10151 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
10152 (match_operand:GPR 2 "register_operand" "d")))]
10154 "<d>subu\t%0,%1,%2"
10155 [(set_attr "type" "arith")
10156 (set_attr "mode" "<MODE>")])
10159 This is exactly equivalent to:
10162 (define_insn "subsi3"
10163 [(set (match_operand:SI 0 "register_operand" "=d")
10164 (minus:SI (match_operand:SI 1 "register_operand" "d")
10165 (match_operand:SI 2 "register_operand" "d")))]
10168 [(set_attr "type" "arith")
10169 (set_attr "mode" "SI")])
10171 (define_insn "subdi3"
10172 [(set (match_operand:DI 0 "register_operand" "=d")
10173 (minus:DI (match_operand:DI 1 "register_operand" "d")
10174 (match_operand:DI 2 "register_operand" "d")))]
10177 [(set_attr "type" "arith")
10178 (set_attr "mode" "DI")])
10181 @node Code Iterators
10182 @subsection Code Iterators
10183 @cindex code iterators in @file{.md} files
10184 @findex define_code_iterator
10185 @findex define_code_attr
10187 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
10192 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
10195 defines a pseudo rtx code @var{name} that can be instantiated as
10196 @var{codei} if condition @var{condi} is true. Each @var{codei}
10197 must have the same rtx format. @xref{RTL Classes}.
10199 As with mode iterators, each pattern that uses @var{name} will be
10200 expanded @var{n} times, once with all uses of @var{name} replaced by
10201 @var{code1}, once with all uses replaced by @var{code2}, and so on.
10202 @xref{Defining Mode Iterators}.
10204 It is possible to define attributes for codes as well as for modes.
10205 There are two standard code attributes: @code{code}, the name of the
10206 code in lower case, and @code{CODE}, the name of the code in upper case.
10207 Other attributes are defined using:
10210 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
10213 Here's an example of code iterators in action, taken from the MIPS port:
10216 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
10217 eq ne gt ge lt le gtu geu ltu leu])
10219 (define_expand "b<code>"
10221 (if_then_else (any_cond:CC (cc0)
10223 (label_ref (match_operand 0 ""))
10227 gen_conditional_branch (operands, <CODE>);
10232 This is equivalent to:
10235 (define_expand "bunordered"
10237 (if_then_else (unordered:CC (cc0)
10239 (label_ref (match_operand 0 ""))
10243 gen_conditional_branch (operands, UNORDERED);
10247 (define_expand "bordered"
10249 (if_then_else (ordered:CC (cc0)
10251 (label_ref (match_operand 0 ""))
10255 gen_conditional_branch (operands, ORDERED);
10262 @node Int Iterators
10263 @subsection Int Iterators
10264 @cindex int iterators in @file{.md} files
10265 @findex define_int_iterator
10266 @findex define_int_attr
10268 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
10273 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
10276 defines a pseudo integer constant @var{name} that can be instantiated as
10277 @var{inti} if condition @var{condi} is true. Each @var{int}
10278 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
10279 in only those rtx fields that have 'i' as the specifier. This means that
10280 each @var{int} has to be a constant defined using define_constant or
10283 As with mode and code iterators, each pattern that uses @var{name} will be
10284 expanded @var{n} times, once with all uses of @var{name} replaced by
10285 @var{int1}, once with all uses replaced by @var{int2}, and so on.
10286 @xref{Defining Mode Iterators}.
10288 It is possible to define attributes for ints as well as for codes and modes.
10289 Attributes are defined using:
10292 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
10295 Here's an example of int iterators in action, taken from the ARM port:
10298 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
10300 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
10302 (define_insn "neon_vq<absneg><mode>"
10303 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10304 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10305 (match_operand:SI 2 "immediate_operand" "i")]
10308 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10309 [(set_attr "type" "neon_vqneg_vqabs")]
10314 This is equivalent to:
10317 (define_insn "neon_vqabs<mode>"
10318 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10319 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10320 (match_operand:SI 2 "immediate_operand" "i")]
10323 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10324 [(set_attr "type" "neon_vqneg_vqabs")]
10327 (define_insn "neon_vqneg<mode>"
10328 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
10329 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
10330 (match_operand:SI 2 "immediate_operand" "i")]
10333 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
10334 [(set_attr "type" "neon_vqneg_vqabs")]
10339 @node Subst Iterators
10340 @subsection Subst Iterators
10341 @cindex subst iterators in @file{.md} files
10342 @findex define_subst
10343 @findex define_subst_attr
10345 Subst iterators are special type of iterators with the following
10346 restrictions: they could not be declared explicitly, they always have
10347 only two values, and they do not have explicit dedicated name.
10348 Subst-iterators are triggered only when corresponding subst-attribute is
10349 used in RTL-pattern.
10351 Subst iterators transform templates in the following way: the templates
10352 are duplicated, the subst-attributes in these templates are replaced
10353 with the corresponding values, and a new attribute is implicitly added
10354 to the given @code{define_insn}/@code{define_expand}. The name of the
10355 added attribute matches the name of @code{define_subst}. Such
10356 attributes are declared implicitly, and it is not allowed to have a
10357 @code{define_attr} named as a @code{define_subst}.
10359 Each subst iterator is linked to a @code{define_subst}. It is declared
10360 implicitly by the first appearance of the corresponding
10361 @code{define_subst_attr}, and it is not allowed to define it explicitly.
10363 Declarations of subst-attributes have the following syntax:
10365 @findex define_subst_attr
10367 (define_subst_attr "@var{name}"
10369 "@var{no-subst-value}"
10370 "@var{subst-applied-value}")
10373 @var{name} is a string with which the given subst-attribute could be
10376 @var{subst-name} shows which @code{define_subst} should be applied to an
10377 RTL-template if the given subst-attribute is present in the
10380 @var{no-subst-value} is a value with which subst-attribute would be
10381 replaced in the first copy of the original RTL-template.
10383 @var{subst-applied-value} is a value with which subst-attribute would be
10384 replaced in the second copy of the original RTL-template.