1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
101 #include "tree-pass.h"
103 #include "valtrack.h"
107 /* Number of attempts to combine instructions in this function. */
109 static int combine_attempts
;
111 /* Number of attempts that got as far as substitution in this function. */
113 static int combine_merges
;
115 /* Number of instructions combined with added SETs in this function. */
117 static int combine_extras
;
119 /* Number of instructions combined in this function. */
121 static int combine_successes
;
123 /* Totals over entire compilation. */
125 static int total_attempts
, total_merges
, total_extras
, total_successes
;
127 /* combine_instructions may try to replace the right hand side of the
128 second instruction with the value of an associated REG_EQUAL note
129 before throwing it at try_combine. That is problematic when there
130 is a REG_DEAD note for a register used in the old right hand side
131 and can cause distribute_notes to do wrong things. This is the
132 second instruction if it has been so modified, null otherwise. */
136 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
138 static rtx i2mod_old_rhs
;
140 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
142 static rtx i2mod_new_rhs
;
144 typedef struct reg_stat_struct
{
145 /* Record last point of death of (hard or pseudo) register n. */
148 /* Record last point of modification of (hard or pseudo) register n. */
151 /* The next group of fields allows the recording of the last value assigned
152 to (hard or pseudo) register n. We use this information to see if an
153 operation being processed is redundant given a prior operation performed
154 on the register. For example, an `and' with a constant is redundant if
155 all the zero bits are already known to be turned off.
157 We use an approach similar to that used by cse, but change it in the
160 (1) We do not want to reinitialize at each label.
161 (2) It is useful, but not critical, to know the actual value assigned
162 to a register. Often just its form is helpful.
164 Therefore, we maintain the following fields:
166 last_set_value the last value assigned
167 last_set_label records the value of label_tick when the
168 register was assigned
169 last_set_table_tick records the value of label_tick when a
170 value using the register is assigned
171 last_set_invalid set to nonzero when it is not valid
172 to use the value of this register in some
175 To understand the usage of these tables, it is important to understand
176 the distinction between the value in last_set_value being valid and
177 the register being validly contained in some other expression in the
180 (The next two parameters are out of date).
182 reg_stat[i].last_set_value is valid if it is nonzero, and either
183 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
185 Register I may validly appear in any expression returned for the value
186 of another register if reg_n_sets[i] is 1. It may also appear in the
187 value for register J if reg_stat[j].last_set_invalid is zero, or
188 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
190 If an expression is found in the table containing a register which may
191 not validly appear in an expression, the register is replaced by
192 something that won't match, (clobber (const_int 0)). */
194 /* Record last value assigned to (hard or pseudo) register n. */
198 /* Record the value of label_tick when an expression involving register n
199 is placed in last_set_value. */
201 int last_set_table_tick
;
203 /* Record the value of label_tick when the value for register n is placed in
208 /* These fields are maintained in parallel with last_set_value and are
209 used to store the mode in which the register was last set, the bits
210 that were known to be zero when it was last set, and the number of
211 sign bits copies it was known to have when it was last set. */
213 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
214 char last_set_sign_bit_copies
;
215 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
217 /* Set nonzero if references to register n in expressions should not be
218 used. last_set_invalid is set nonzero when this register is being
219 assigned to and last_set_table_tick == label_tick. */
221 char last_set_invalid
;
223 /* Some registers that are set more than once and used in more than one
224 basic block are nevertheless always set in similar ways. For example,
225 a QImode register may be loaded from memory in two places on a machine
226 where byte loads zero extend.
228 We record in the following fields if a register has some leading bits
229 that are always equal to the sign bit, and what we know about the
230 nonzero bits of a register, specifically which bits are known to be
233 If an entry is zero, it means that we don't know anything special. */
235 unsigned char sign_bit_copies
;
237 unsigned HOST_WIDE_INT nonzero_bits
;
239 /* Record the value of the label_tick when the last truncation
240 happened. The field truncated_to_mode is only valid if
241 truncation_label == label_tick. */
243 int truncation_label
;
245 /* Record the last truncation seen for this register. If truncation
246 is not a nop to this mode we might be able to save an explicit
247 truncation if we know that value already contains a truncated
250 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
254 static vec
<reg_stat_type
> reg_stat
;
256 /* Record the luid of the last insn that invalidated memory
257 (anything that writes memory, and subroutine calls, but not pushes). */
259 static int mem_last_set
;
261 /* Record the luid of the last CALL_INSN
262 so we can tell whether a potential combination crosses any calls. */
264 static int last_call_luid
;
266 /* When `subst' is called, this is the insn that is being modified
267 (by combining in a previous insn). The PATTERN of this insn
268 is still the old pattern partially modified and it should not be
269 looked at, but this may be used to examine the successors of the insn
270 to judge whether a simplification is valid. */
272 static rtx subst_insn
;
274 /* This is the lowest LUID that `subst' is currently dealing with.
275 get_last_value will not return a value if the register was set at or
276 after this LUID. If not for this mechanism, we could get confused if
277 I2 or I1 in try_combine were an insn that used the old value of a register
278 to obtain a new value. In that case, we might erroneously get the
279 new value of the register when we wanted the old one. */
281 static int subst_low_luid
;
283 /* This contains any hard registers that are used in newpat; reg_dead_at_p
284 must consider all these registers to be always live. */
286 static HARD_REG_SET newpat_used_regs
;
288 /* This is an insn to which a LOG_LINKS entry has been added. If this
289 insn is the earlier than I2 or I3, combine should rescan starting at
292 static rtx added_links_insn
;
294 /* Basic block in which we are performing combines. */
295 static basic_block this_basic_block
;
296 static bool optimize_this_for_speed_p
;
299 /* Length of the currently allocated uid_insn_cost array. */
301 static int max_uid_known
;
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
306 static int *uid_insn_cost
;
308 /* The following array records the LOG_LINKS for every insn in the
309 instruction stream as struct insn_link pointers. */
313 struct insn_link
*next
;
316 static struct insn_link
**uid_log_links
;
318 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
319 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
321 #define FOR_EACH_LOG_LINK(L, INSN) \
322 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
324 /* Links for LOG_LINKS are allocated from this obstack. */
326 static struct obstack insn_link_obstack
;
328 /* Allocate a link. */
330 static inline struct insn_link
*
331 alloc_insn_link (rtx insn
, struct insn_link
*next
)
334 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
335 sizeof (struct insn_link
));
341 /* Incremented for each basic block. */
343 static int label_tick
;
345 /* Reset to label_tick for each extended basic block in scanning order. */
347 static int label_tick_ebb_start
;
349 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
350 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
352 static enum machine_mode nonzero_bits_mode
;
354 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
355 be safely used. It is zero while computing them and after combine has
356 completed. This former test prevents propagating values based on
357 previously set values, which can be incorrect if a variable is modified
360 static int nonzero_sign_valid
;
363 /* Record one modification to rtl structure
364 to be undone by storing old_contents into *where. */
366 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
372 union { rtx r
; int i
; enum machine_mode m
; struct insn_link
*l
; } old_contents
;
373 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
376 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
377 num_undo says how many are currently recorded.
379 other_insn is nonzero if we have modified some other insn in the process
380 of working on subst_insn. It must be verified too. */
389 static struct undobuf undobuf
;
391 /* Number of times the pseudo being substituted for
392 was found and replaced. */
394 static int n_occurrences
;
396 static rtx
reg_nonzero_bits_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
398 unsigned HOST_WIDE_INT
,
399 unsigned HOST_WIDE_INT
*);
400 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, enum machine_mode
, const_rtx
,
402 unsigned int, unsigned int *);
403 static void do_SUBST (rtx
*, rtx
);
404 static void do_SUBST_INT (int *, int);
405 static void init_reg_last (void);
406 static void setup_incoming_promotions (rtx
);
407 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
408 static int cant_combine_insn_p (rtx
);
409 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
410 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
411 static int contains_muldiv (rtx
);
412 static rtx
try_combine (rtx
, rtx
, rtx
, rtx
, int *, rtx
);
413 static void undo_all (void);
414 static void undo_commit (void);
415 static rtx
*find_split_point (rtx
*, rtx
, bool);
416 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
417 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
418 static rtx
simplify_if_then_else (rtx
);
419 static rtx
simplify_set (rtx
);
420 static rtx
simplify_logical (rtx
);
421 static rtx
expand_compound_operation (rtx
);
422 static const_rtx
expand_field_assignment (const_rtx
);
423 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
424 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
425 static rtx
extract_left_shift (rtx
, int);
426 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
427 unsigned HOST_WIDE_INT
*);
428 static rtx
canon_reg_for_combine (rtx
, rtx
);
429 static rtx
force_to_mode (rtx
, enum machine_mode
,
430 unsigned HOST_WIDE_INT
, int);
431 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
432 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
433 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
434 static rtx
make_field_assignment (rtx
);
435 static rtx
apply_distributive_law (rtx
);
436 static rtx
distribute_and_simplify_rtx (rtx
, int);
437 static rtx
simplify_and_const_int_1 (enum machine_mode
, rtx
,
438 unsigned HOST_WIDE_INT
);
439 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
440 unsigned HOST_WIDE_INT
);
441 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
442 HOST_WIDE_INT
, enum machine_mode
, int *);
443 static rtx
simplify_shift_const_1 (enum rtx_code
, enum machine_mode
, rtx
, int);
444 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
446 static int recog_for_combine (rtx
*, rtx
, rtx
*);
447 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
448 static enum rtx_code
simplify_compare_const (enum rtx_code
, rtx
, rtx
*);
449 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
450 static void update_table_tick (rtx
);
451 static void record_value_for_reg (rtx
, rtx
, rtx
);
452 static void check_promoted_subreg (rtx
, rtx
);
453 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
454 static void record_dead_and_set_regs (rtx
);
455 static int get_last_value_validate (rtx
*, rtx
, int, int);
456 static rtx
get_last_value (const_rtx
);
457 static int use_crosses_set_p (const_rtx
, int);
458 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
459 static int reg_dead_at_p (rtx
, rtx
);
460 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
461 static int reg_bitfield_target_p (rtx
, rtx
);
462 static void distribute_notes (rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
);
463 static void distribute_links (struct insn_link
*);
464 static void mark_used_regs_combine (rtx
);
465 static void record_promoted_value (rtx
, rtx
);
466 static int unmentioned_reg_p_1 (rtx
*, void *);
467 static bool unmentioned_reg_p (rtx
, rtx
);
468 static int record_truncated_value (rtx
*, void *);
469 static void record_truncated_values (rtx
*, void *);
470 static bool reg_truncated_to_mode (enum machine_mode
, const_rtx
);
471 static rtx
gen_lowpart_or_truncate (enum machine_mode
, rtx
);
474 /* It is not safe to use ordinary gen_lowpart in combine.
475 See comments in gen_lowpart_for_combine. */
476 #undef RTL_HOOKS_GEN_LOWPART
477 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
479 /* Our implementation of gen_lowpart never emits a new pseudo. */
480 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
481 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
483 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
484 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
486 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
487 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
489 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
490 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
492 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
495 /* Convenience wrapper for the canonicalize_comparison target hook.
496 Target hooks cannot use enum rtx_code. */
498 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
499 bool op0_preserve_value
)
501 int code_int
= (int)*code
;
502 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
503 *code
= (enum rtx_code
)code_int
;
506 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
507 PATTERN can not be split. Otherwise, it returns an insn sequence.
508 This is a wrapper around split_insns which ensures that the
509 reg_stat vector is made larger if the splitter creates a new
513 combine_split_insns (rtx pattern
, rtx insn
)
518 ret
= split_insns (pattern
, insn
);
519 nregs
= max_reg_num ();
520 if (nregs
> reg_stat
.length ())
521 reg_stat
.safe_grow_cleared (nregs
);
525 /* This is used by find_single_use to locate an rtx in LOC that
526 contains exactly one use of DEST, which is typically either a REG
527 or CC0. It returns a pointer to the innermost rtx expression
528 containing DEST. Appearances of DEST that are being used to
529 totally replace it are not counted. */
532 find_single_use_1 (rtx dest
, rtx
*loc
)
535 enum rtx_code code
= GET_CODE (x
);
551 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
552 of a REG that occupies all of the REG, the insn uses DEST if
553 it is mentioned in the destination or the source. Otherwise, we
554 need just check the source. */
555 if (GET_CODE (SET_DEST (x
)) != CC0
556 && GET_CODE (SET_DEST (x
)) != PC
557 && !REG_P (SET_DEST (x
))
558 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
559 && REG_P (SUBREG_REG (SET_DEST (x
)))
560 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
561 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
562 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
563 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
566 return find_single_use_1 (dest
, &SET_SRC (x
));
570 return find_single_use_1 (dest
, &XEXP (x
, 0));
576 /* If it wasn't one of the common cases above, check each expression and
577 vector of this code. Look for a unique usage of DEST. */
579 fmt
= GET_RTX_FORMAT (code
);
580 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
584 if (dest
== XEXP (x
, i
)
585 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
586 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
589 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
592 result
= this_result
;
593 else if (this_result
)
594 /* Duplicate usage. */
597 else if (fmt
[i
] == 'E')
601 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
603 if (XVECEXP (x
, i
, j
) == dest
605 && REG_P (XVECEXP (x
, i
, j
))
606 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
609 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
612 result
= this_result
;
613 else if (this_result
)
623 /* See if DEST, produced in INSN, is used only a single time in the
624 sequel. If so, return a pointer to the innermost rtx expression in which
627 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
629 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
630 care about REG_DEAD notes or LOG_LINKS.
632 Otherwise, we find the single use by finding an insn that has a
633 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
634 only referenced once in that insn, we know that it must be the first
635 and last insn referencing DEST. */
638 find_single_use (rtx dest
, rtx insn
, rtx
*ploc
)
643 struct insn_link
*link
;
648 next
= NEXT_INSN (insn
);
650 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
653 result
= find_single_use_1 (dest
, &PATTERN (next
));
663 bb
= BLOCK_FOR_INSN (insn
);
664 for (next
= NEXT_INSN (insn
);
665 next
&& BLOCK_FOR_INSN (next
) == bb
;
666 next
= NEXT_INSN (next
))
667 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
669 FOR_EACH_LOG_LINK (link
, next
)
670 if (link
->insn
== insn
)
675 result
= find_single_use_1 (dest
, &PATTERN (next
));
685 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
686 insn. The substitution can be undone by undo_all. If INTO is already
687 set to NEWVAL, do not record this change. Because computing NEWVAL might
688 also call SUBST, we have to compute it before we put anything into
692 do_SUBST (rtx
*into
, rtx newval
)
697 if (oldval
== newval
)
700 /* We'd like to catch as many invalid transformations here as
701 possible. Unfortunately, there are way too many mode changes
702 that are perfectly valid, so we'd waste too much effort for
703 little gain doing the checks here. Focus on catching invalid
704 transformations involving integer constants. */
705 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
706 && CONST_INT_P (newval
))
708 /* Sanity check that we're replacing oldval with a CONST_INT
709 that is a valid sign-extension for the original mode. */
710 gcc_assert (INTVAL (newval
)
711 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
713 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
714 CONST_INT is not valid, because after the replacement, the
715 original mode would be gone. Unfortunately, we can't tell
716 when do_SUBST is called to replace the operand thereof, so we
717 perform this test on oldval instead, checking whether an
718 invalid replacement took place before we got here. */
719 gcc_assert (!(GET_CODE (oldval
) == SUBREG
720 && CONST_INT_P (SUBREG_REG (oldval
))));
721 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
722 && CONST_INT_P (XEXP (oldval
, 0))));
726 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
728 buf
= XNEW (struct undo
);
730 buf
->kind
= UNDO_RTX
;
732 buf
->old_contents
.r
= oldval
;
735 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
738 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
740 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
741 for the value of a HOST_WIDE_INT value (including CONST_INT) is
745 do_SUBST_INT (int *into
, int newval
)
750 if (oldval
== newval
)
754 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
756 buf
= XNEW (struct undo
);
758 buf
->kind
= UNDO_INT
;
760 buf
->old_contents
.i
= oldval
;
763 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
766 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
768 /* Similar to SUBST, but just substitute the mode. This is used when
769 changing the mode of a pseudo-register, so that any other
770 references to the entry in the regno_reg_rtx array will change as
774 do_SUBST_MODE (rtx
*into
, enum machine_mode newval
)
777 enum machine_mode oldval
= GET_MODE (*into
);
779 if (oldval
== newval
)
783 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
785 buf
= XNEW (struct undo
);
787 buf
->kind
= UNDO_MODE
;
789 buf
->old_contents
.m
= oldval
;
790 adjust_reg_mode (*into
, newval
);
792 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
795 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
798 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
801 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
804 struct insn_link
* oldval
= *into
;
806 if (oldval
== newval
)
810 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
812 buf
= XNEW (struct undo
);
814 buf
->kind
= UNDO_LINKS
;
816 buf
->old_contents
.l
= oldval
;
819 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
822 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
825 /* Subroutine of try_combine. Determine whether the replacement patterns
826 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
827 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
828 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
829 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
830 of all the instructions can be estimated and the replacements are more
831 expensive than the original sequence. */
834 combine_validate_cost (rtx i0
, rtx i1
, rtx i2
, rtx i3
, rtx newpat
,
835 rtx newi2pat
, rtx newotherpat
)
837 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
838 int new_i2_cost
, new_i3_cost
;
839 int old_cost
, new_cost
;
841 /* Lookup the original insn_rtx_costs. */
842 i2_cost
= INSN_COST (i2
);
843 i3_cost
= INSN_COST (i3
);
847 i1_cost
= INSN_COST (i1
);
850 i0_cost
= INSN_COST (i0
);
851 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
852 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
856 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
857 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
863 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
864 i1_cost
= i0_cost
= 0;
867 /* Calculate the replacement insn_rtx_costs. */
868 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
871 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
872 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
873 ? new_i2_cost
+ new_i3_cost
: 0;
877 new_cost
= new_i3_cost
;
881 if (undobuf
.other_insn
)
883 int old_other_cost
, new_other_cost
;
885 old_other_cost
= INSN_COST (undobuf
.other_insn
);
886 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
887 if (old_other_cost
> 0 && new_other_cost
> 0)
889 old_cost
+= old_other_cost
;
890 new_cost
+= new_other_cost
;
896 /* Disallow this combination if both new_cost and old_cost are greater than
897 zero, and new_cost is greater than old cost. */
898 if (old_cost
> 0 && new_cost
> old_cost
)
905 "rejecting combination of insns %d, %d, %d and %d\n",
906 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
),
908 fprintf (dump_file
, "original costs %d + %d + %d + %d = %d\n",
909 i0_cost
, i1_cost
, i2_cost
, i3_cost
, old_cost
);
914 "rejecting combination of insns %d, %d and %d\n",
915 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
916 fprintf (dump_file
, "original costs %d + %d + %d = %d\n",
917 i1_cost
, i2_cost
, i3_cost
, old_cost
);
922 "rejecting combination of insns %d and %d\n",
923 INSN_UID (i2
), INSN_UID (i3
));
924 fprintf (dump_file
, "original costs %d + %d = %d\n",
925 i2_cost
, i3_cost
, old_cost
);
930 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
931 new_i2_cost
, new_i3_cost
, new_cost
);
934 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
940 /* Update the uid_insn_cost array with the replacement costs. */
941 INSN_COST (i2
) = new_i2_cost
;
942 INSN_COST (i3
) = new_i3_cost
;
954 /* Delete any insns that copy a register to itself. */
957 delete_noop_moves (void)
964 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
966 next
= NEXT_INSN (insn
);
967 if (INSN_P (insn
) && noop_move_p (insn
))
970 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
972 delete_insn_and_edges (insn
);
979 /* Fill in log links field for all insns. */
982 create_log_links (void)
986 df_ref
*def_vec
, *use_vec
;
988 next_use
= XCNEWVEC (rtx
, max_reg_num ());
990 /* Pass through each block from the end, recording the uses of each
991 register and establishing log links when def is encountered.
992 Note that we do not clear next_use array in order to save time,
993 so we have to test whether the use is in the same basic block as def.
995 There are a few cases below when we do not consider the definition or
996 usage -- these are taken from original flow.c did. Don't ask me why it is
997 done this way; I don't know and if it works, I don't want to know. */
1001 FOR_BB_INSNS_REVERSE (bb
, insn
)
1003 if (!NONDEBUG_INSN_P (insn
))
1006 /* Log links are created only once. */
1007 gcc_assert (!LOG_LINKS (insn
));
1009 for (def_vec
= DF_INSN_DEFS (insn
); *def_vec
; def_vec
++)
1011 df_ref def
= *def_vec
;
1012 int regno
= DF_REF_REGNO (def
);
1015 if (!next_use
[regno
])
1018 /* Do not consider if it is pre/post modification in MEM. */
1019 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
1022 /* Do not make the log link for frame pointer. */
1023 if ((regno
== FRAME_POINTER_REGNUM
1024 && (! reload_completed
|| frame_pointer_needed
))
1025 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1026 || (regno
== HARD_FRAME_POINTER_REGNUM
1027 && (! reload_completed
|| frame_pointer_needed
))
1029 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1030 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1035 use_insn
= next_use
[regno
];
1036 if (BLOCK_FOR_INSN (use_insn
) == bb
)
1040 We don't build a LOG_LINK for hard registers contained
1041 in ASM_OPERANDs. If these registers get replaced,
1042 we might wind up changing the semantics of the insn,
1043 even if reload can make what appear to be valid
1044 assignments later. */
1045 if (regno
>= FIRST_PSEUDO_REGISTER
1046 || asm_noperands (PATTERN (use_insn
)) < 0)
1048 /* Don't add duplicate links between instructions. */
1049 struct insn_link
*links
;
1050 FOR_EACH_LOG_LINK (links
, use_insn
)
1051 if (insn
== links
->insn
)
1055 LOG_LINKS (use_insn
)
1056 = alloc_insn_link (insn
, LOG_LINKS (use_insn
));
1059 next_use
[regno
] = NULL_RTX
;
1062 for (use_vec
= DF_INSN_USES (insn
); *use_vec
; use_vec
++)
1064 df_ref use
= *use_vec
;
1065 int regno
= DF_REF_REGNO (use
);
1067 /* Do not consider the usage of the stack pointer
1068 by function call. */
1069 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1072 next_use
[regno
] = insn
;
1080 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1081 true if we found a LOG_LINK that proves that A feeds B. This only works
1082 if there are no instructions between A and B which could have a link
1083 depending on A, since in that case we would not record a link for B.
1084 We also check the implicit dependency created by a cc0 setter/user
1088 insn_a_feeds_b (rtx a
, rtx b
)
1090 struct insn_link
*links
;
1091 FOR_EACH_LOG_LINK (links
, b
)
1092 if (links
->insn
== a
)
1101 /* Main entry point for combiner. F is the first insn of the function.
1102 NREGS is the first unused pseudo-reg number.
1104 Return nonzero if the combiner has turned an indirect jump
1105 instruction into a direct jump. */
1107 combine_instructions (rtx f
, unsigned int nregs
)
1113 struct insn_link
*links
, *nextlinks
;
1115 basic_block last_bb
;
1117 int new_direct_jump_p
= 0;
1119 for (first
= f
; first
&& !INSN_P (first
); )
1120 first
= NEXT_INSN (first
);
1124 combine_attempts
= 0;
1127 combine_successes
= 0;
1129 rtl_hooks
= combine_rtl_hooks
;
1131 reg_stat
.safe_grow_cleared (nregs
);
1133 init_recog_no_volatile ();
1135 /* Allocate array for insn info. */
1136 max_uid_known
= get_max_uid ();
1137 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1138 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1139 gcc_obstack_init (&insn_link_obstack
);
1141 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1143 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1144 problems when, for example, we have j <<= 1 in a loop. */
1146 nonzero_sign_valid
= 0;
1147 label_tick
= label_tick_ebb_start
= 1;
1149 /* Scan all SETs and see if we can deduce anything about what
1150 bits are known to be zero for some registers and how many copies
1151 of the sign bit are known to exist for those registers.
1153 Also set any known values so that we can use it while searching
1154 for what bits are known to be set. */
1156 setup_incoming_promotions (first
);
1157 /* Allow the entry block and the first block to fall into the same EBB.
1158 Conceptually the incoming promotions are assigned to the entry block. */
1159 last_bb
= ENTRY_BLOCK_PTR
;
1161 create_log_links ();
1162 FOR_EACH_BB (this_basic_block
)
1164 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1169 if (!single_pred_p (this_basic_block
)
1170 || single_pred (this_basic_block
) != last_bb
)
1171 label_tick_ebb_start
= label_tick
;
1172 last_bb
= this_basic_block
;
1174 FOR_BB_INSNS (this_basic_block
, insn
)
1175 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1181 subst_low_luid
= DF_INSN_LUID (insn
);
1184 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1186 record_dead_and_set_regs (insn
);
1189 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1190 if (REG_NOTE_KIND (links
) == REG_INC
)
1191 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1195 /* Record the current insn_rtx_cost of this instruction. */
1196 if (NONJUMP_INSN_P (insn
))
1197 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1198 optimize_this_for_speed_p
);
1200 fprintf(dump_file
, "insn_cost %d: %d\n",
1201 INSN_UID (insn
), INSN_COST (insn
));
1205 nonzero_sign_valid
= 1;
1207 /* Now scan all the insns in forward order. */
1208 label_tick
= label_tick_ebb_start
= 1;
1210 setup_incoming_promotions (first
);
1211 last_bb
= ENTRY_BLOCK_PTR
;
1213 FOR_EACH_BB (this_basic_block
)
1215 rtx last_combined_insn
= NULL_RTX
;
1216 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1221 if (!single_pred_p (this_basic_block
)
1222 || single_pred (this_basic_block
) != last_bb
)
1223 label_tick_ebb_start
= label_tick
;
1224 last_bb
= this_basic_block
;
1226 rtl_profile_for_bb (this_basic_block
);
1227 for (insn
= BB_HEAD (this_basic_block
);
1228 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1229 insn
= next
? next
: NEXT_INSN (insn
))
1232 if (NONDEBUG_INSN_P (insn
))
1234 while (last_combined_insn
1235 && INSN_DELETED_P (last_combined_insn
))
1236 last_combined_insn
= PREV_INSN (last_combined_insn
);
1237 if (last_combined_insn
== NULL_RTX
1238 || BARRIER_P (last_combined_insn
)
1239 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1240 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1241 last_combined_insn
= insn
;
1243 /* See if we know about function return values before this
1244 insn based upon SUBREG flags. */
1245 check_promoted_subreg (insn
, PATTERN (insn
));
1247 /* See if we can find hardregs and subreg of pseudos in
1248 narrower modes. This could help turning TRUNCATEs
1250 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1252 /* Try this insn with each insn it links back to. */
1254 FOR_EACH_LOG_LINK (links
, insn
)
1255 if ((next
= try_combine (insn
, links
->insn
, NULL_RTX
,
1256 NULL_RTX
, &new_direct_jump_p
,
1257 last_combined_insn
)) != 0)
1260 /* Try each sequence of three linked insns ending with this one. */
1262 FOR_EACH_LOG_LINK (links
, insn
)
1264 rtx link
= links
->insn
;
1266 /* If the linked insn has been replaced by a note, then there
1267 is no point in pursuing this chain any further. */
1271 FOR_EACH_LOG_LINK (nextlinks
, link
)
1272 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1273 NULL_RTX
, &new_direct_jump_p
,
1274 last_combined_insn
)) != 0)
1279 /* Try to combine a jump insn that uses CC0
1280 with a preceding insn that sets CC0, and maybe with its
1281 logical predecessor as well.
1282 This is how we make decrement-and-branch insns.
1283 We need this special code because data flow connections
1284 via CC0 do not get entered in LOG_LINKS. */
1287 && (prev
= prev_nonnote_insn (insn
)) != 0
1288 && NONJUMP_INSN_P (prev
)
1289 && sets_cc0_p (PATTERN (prev
)))
1291 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1293 last_combined_insn
)) != 0)
1296 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1297 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1298 NULL_RTX
, &new_direct_jump_p
,
1299 last_combined_insn
)) != 0)
1303 /* Do the same for an insn that explicitly references CC0. */
1304 if (NONJUMP_INSN_P (insn
)
1305 && (prev
= prev_nonnote_insn (insn
)) != 0
1306 && NONJUMP_INSN_P (prev
)
1307 && sets_cc0_p (PATTERN (prev
))
1308 && GET_CODE (PATTERN (insn
)) == SET
1309 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1311 if ((next
= try_combine (insn
, prev
, NULL_RTX
, NULL_RTX
,
1313 last_combined_insn
)) != 0)
1316 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1317 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1318 NULL_RTX
, &new_direct_jump_p
,
1319 last_combined_insn
)) != 0)
1323 /* Finally, see if any of the insns that this insn links to
1324 explicitly references CC0. If so, try this insn, that insn,
1325 and its predecessor if it sets CC0. */
1326 FOR_EACH_LOG_LINK (links
, insn
)
1327 if (NONJUMP_INSN_P (links
->insn
)
1328 && GET_CODE (PATTERN (links
->insn
)) == SET
1329 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1330 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1331 && NONJUMP_INSN_P (prev
)
1332 && sets_cc0_p (PATTERN (prev
))
1333 && (next
= try_combine (insn
, links
->insn
,
1334 prev
, NULL_RTX
, &new_direct_jump_p
,
1335 last_combined_insn
)) != 0)
1339 /* Try combining an insn with two different insns whose results it
1341 FOR_EACH_LOG_LINK (links
, insn
)
1342 for (nextlinks
= links
->next
; nextlinks
;
1343 nextlinks
= nextlinks
->next
)
1344 if ((next
= try_combine (insn
, links
->insn
,
1345 nextlinks
->insn
, NULL_RTX
,
1347 last_combined_insn
)) != 0)
1350 /* Try four-instruction combinations. */
1351 FOR_EACH_LOG_LINK (links
, insn
)
1353 struct insn_link
*next1
;
1354 rtx link
= links
->insn
;
1356 /* If the linked insn has been replaced by a note, then there
1357 is no point in pursuing this chain any further. */
1361 FOR_EACH_LOG_LINK (next1
, link
)
1363 rtx link1
= next1
->insn
;
1366 /* I0 -> I1 -> I2 -> I3. */
1367 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1368 if ((next
= try_combine (insn
, link
, link1
,
1371 last_combined_insn
)) != 0)
1373 /* I0, I1 -> I2, I2 -> I3. */
1374 for (nextlinks
= next1
->next
; nextlinks
;
1375 nextlinks
= nextlinks
->next
)
1376 if ((next
= try_combine (insn
, link
, link1
,
1379 last_combined_insn
)) != 0)
1383 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1385 rtx link1
= next1
->insn
;
1388 /* I0 -> I2; I1, I2 -> I3. */
1389 FOR_EACH_LOG_LINK (nextlinks
, link
)
1390 if ((next
= try_combine (insn
, link
, link1
,
1393 last_combined_insn
)) != 0)
1395 /* I0 -> I1; I1, I2 -> I3. */
1396 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1397 if ((next
= try_combine (insn
, link
, link1
,
1400 last_combined_insn
)) != 0)
1405 /* Try this insn with each REG_EQUAL note it links back to. */
1406 FOR_EACH_LOG_LINK (links
, insn
)
1409 rtx temp
= links
->insn
;
1410 if ((set
= single_set (temp
)) != 0
1411 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1412 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1413 /* Avoid using a register that may already been marked
1414 dead by an earlier instruction. */
1415 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1416 && (GET_MODE (note
) == VOIDmode
1417 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1418 : GET_MODE (SET_DEST (set
)) == GET_MODE (note
)))
1420 /* Temporarily replace the set's source with the
1421 contents of the REG_EQUAL note. The insn will
1422 be deleted or recognized by try_combine. */
1423 rtx orig
= SET_SRC (set
);
1424 SET_SRC (set
) = note
;
1426 i2mod_old_rhs
= copy_rtx (orig
);
1427 i2mod_new_rhs
= copy_rtx (note
);
1428 next
= try_combine (insn
, i2mod
, NULL_RTX
, NULL_RTX
,
1430 last_combined_insn
);
1434 SET_SRC (set
) = orig
;
1439 record_dead_and_set_regs (insn
);
1447 default_rtl_profile ();
1449 new_direct_jump_p
|= purge_all_dead_edges ();
1450 delete_noop_moves ();
1453 obstack_free (&insn_link_obstack
, NULL
);
1454 free (uid_log_links
);
1455 free (uid_insn_cost
);
1456 reg_stat
.release ();
1459 struct undo
*undo
, *next
;
1460 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1468 total_attempts
+= combine_attempts
;
1469 total_merges
+= combine_merges
;
1470 total_extras
+= combine_extras
;
1471 total_successes
+= combine_successes
;
1473 nonzero_sign_valid
= 0;
1474 rtl_hooks
= general_rtl_hooks
;
1476 /* Make recognizer allow volatile MEMs again. */
1479 return new_direct_jump_p
;
1482 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1485 init_reg_last (void)
1490 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1491 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1494 /* Set up any promoted values for incoming argument registers. */
1497 setup_incoming_promotions (rtx first
)
1500 bool strictly_local
= false;
1502 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1503 arg
= DECL_CHAIN (arg
))
1505 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1507 enum machine_mode mode1
, mode2
, mode3
, mode4
;
1509 /* Only continue if the incoming argument is in a register. */
1513 /* Determine, if possible, whether all call sites of the current
1514 function lie within the current compilation unit. (This does
1515 take into account the exporting of a function via taking its
1516 address, and so forth.) */
1517 strictly_local
= cgraph_local_info (current_function_decl
)->local
;
1519 /* The mode and signedness of the argument before any promotions happen
1520 (equal to the mode of the pseudo holding it at that stage). */
1521 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1522 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1524 /* The mode and signedness of the argument after any source language and
1525 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1526 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1527 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1529 /* The mode and signedness of the argument as it is actually passed,
1530 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1531 mode3
= promote_function_mode (DECL_ARG_TYPE (arg
), mode2
, &uns3
,
1532 TREE_TYPE (cfun
->decl
), 0);
1534 /* The mode of the register in which the argument is being passed. */
1535 mode4
= GET_MODE (reg
);
1537 /* Eliminate sign extensions in the callee when:
1538 (a) A mode promotion has occurred; */
1541 /* (b) The mode of the register is the same as the mode of
1542 the argument as it is passed; */
1545 /* (c) There's no language level extension; */
1548 /* (c.1) All callers are from the current compilation unit. If that's
1549 the case we don't have to rely on an ABI, we only have to know
1550 what we're generating right now, and we know that we will do the
1551 mode1 to mode2 promotion with the given sign. */
1552 else if (!strictly_local
)
1554 /* (c.2) The combination of the two promotions is useful. This is
1555 true when the signs match, or if the first promotion is unsigned.
1556 In the later case, (sign_extend (zero_extend x)) is the same as
1557 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1563 /* Record that the value was promoted from mode1 to mode3,
1564 so that any sign extension at the head of the current
1565 function may be eliminated. */
1566 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1567 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1568 record_value_for_reg (reg
, first
, x
);
1572 /* Called via note_stores. If X is a pseudo that is narrower than
1573 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1575 If we are setting only a portion of X and we can't figure out what
1576 portion, assume all bits will be used since we don't know what will
1579 Similarly, set how many bits of X are known to be copies of the sign bit
1580 at all locations in the function. This is the smallest number implied
1584 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1586 rtx insn
= (rtx
) data
;
1590 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1591 /* If this register is undefined at the start of the file, we can't
1592 say what its contents were. */
1593 && ! REGNO_REG_SET_P
1594 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
))
1595 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1597 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1599 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1601 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1602 rsp
->sign_bit_copies
= 1;
1606 /* If this register is being initialized using itself, and the
1607 register is uninitialized in this basic block, and there are
1608 no LOG_LINKS which set the register, then part of the
1609 register is uninitialized. In that case we can't assume
1610 anything about the number of nonzero bits.
1612 ??? We could do better if we checked this in
1613 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1614 could avoid making assumptions about the insn which initially
1615 sets the register, while still using the information in other
1616 insns. We would have to be careful to check every insn
1617 involved in the combination. */
1620 && reg_referenced_p (x
, PATTERN (insn
))
1621 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1624 struct insn_link
*link
;
1626 FOR_EACH_LOG_LINK (link
, insn
)
1627 if (dead_or_set_p (link
->insn
, x
))
1631 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1632 rsp
->sign_bit_copies
= 1;
1637 /* If this is a complex assignment, see if we can convert it into a
1638 simple assignment. */
1639 set
= expand_field_assignment (set
);
1641 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1642 set what we know about X. */
1644 if (SET_DEST (set
) == x
1645 || (paradoxical_subreg_p (SET_DEST (set
))
1646 && SUBREG_REG (SET_DEST (set
)) == x
))
1648 rtx src
= SET_SRC (set
);
1650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1651 /* If X is narrower than a word and SRC is a non-negative
1652 constant that would appear negative in the mode of X,
1653 sign-extend it for use in reg_stat[].nonzero_bits because some
1654 machines (maybe most) will actually do the sign-extension
1655 and this is the conservative approach.
1657 ??? For 2.5, try to tighten up the MD files in this regard
1658 instead of this kludge. */
1660 if (GET_MODE_PRECISION (GET_MODE (x
)) < BITS_PER_WORD
1661 && CONST_INT_P (src
)
1663 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (src
)))
1664 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (GET_MODE (x
)));
1667 /* Don't call nonzero_bits if it cannot change anything. */
1668 if (rsp
->nonzero_bits
!= ~(unsigned HOST_WIDE_INT
) 0)
1669 rsp
->nonzero_bits
|= nonzero_bits (src
, nonzero_bits_mode
);
1670 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1671 if (rsp
->sign_bit_copies
== 0
1672 || rsp
->sign_bit_copies
> num
)
1673 rsp
->sign_bit_copies
= num
;
1677 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1678 rsp
->sign_bit_copies
= 1;
1683 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1684 optionally insns that were previously combined into I3 or that will be
1685 combined into the merger of INSN and I3. The order is PRED, PRED2,
1686 INSN, SUCC, SUCC2, I3.
1688 Return 0 if the combination is not allowed for any reason.
1690 If the combination is allowed, *PDEST will be set to the single
1691 destination of INSN and *PSRC to the single source, and this function
1695 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
,
1696 rtx pred2 ATTRIBUTE_UNUSED
, rtx succ
, rtx succ2
,
1697 rtx
*pdest
, rtx
*psrc
)
1706 bool all_adjacent
= true;
1707 int (*is_volatile_p
) (const_rtx
);
1713 if (next_active_insn (succ2
) != i3
)
1714 all_adjacent
= false;
1715 if (next_active_insn (succ
) != succ2
)
1716 all_adjacent
= false;
1718 else if (next_active_insn (succ
) != i3
)
1719 all_adjacent
= false;
1720 if (next_active_insn (insn
) != succ
)
1721 all_adjacent
= false;
1723 else if (next_active_insn (insn
) != i3
)
1724 all_adjacent
= false;
1726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1727 or a PARALLEL consisting of such a SET and CLOBBERs.
1729 If INSN has CLOBBER parallel parts, ignore them for our processing.
1730 By definition, these happen during the execution of the insn. When it
1731 is merged with another insn, all bets are off. If they are, in fact,
1732 needed and aren't also supplied in I3, they may be added by
1733 recog_for_combine. Otherwise, it won't match.
1735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1738 Get the source and destination of INSN. If more than one, can't
1741 if (GET_CODE (PATTERN (insn
)) == SET
)
1742 set
= PATTERN (insn
);
1743 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1744 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1746 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1748 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1750 switch (GET_CODE (elt
))
1752 /* This is important to combine floating point insns
1753 for the SH4 port. */
1755 /* Combining an isolated USE doesn't make sense.
1756 We depend here on combinable_i3pat to reject them. */
1757 /* The code below this loop only verifies that the inputs of
1758 the SET in INSN do not change. We call reg_set_between_p
1759 to verify that the REG in the USE does not change between
1761 If the USE in INSN was for a pseudo register, the matching
1762 insn pattern will likely match any register; combining this
1763 with any other USE would only be safe if we knew that the
1764 used registers have identical values, or if there was
1765 something to tell them apart, e.g. different modes. For
1766 now, we forgo such complicated tests and simply disallow
1767 combining of USES of pseudo registers with any other USE. */
1768 if (REG_P (XEXP (elt
, 0))
1769 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1771 rtx i3pat
= PATTERN (i3
);
1772 int i
= XVECLEN (i3pat
, 0) - 1;
1773 unsigned int regno
= REGNO (XEXP (elt
, 0));
1777 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1779 if (GET_CODE (i3elt
) == USE
1780 && REG_P (XEXP (i3elt
, 0))
1781 && (REGNO (XEXP (i3elt
, 0)) == regno
1782 ? reg_set_between_p (XEXP (elt
, 0),
1783 PREV_INSN (insn
), i3
)
1784 : regno
>= FIRST_PSEUDO_REGISTER
))
1791 /* We can ignore CLOBBERs. */
1796 /* Ignore SETs whose result isn't used but not those that
1797 have side-effects. */
1798 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1799 && insn_nothrow_p (insn
)
1800 && !side_effects_p (elt
))
1803 /* If we have already found a SET, this is a second one and
1804 so we cannot combine with this insn. */
1812 /* Anything else means we can't combine. */
1818 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1819 so don't do anything with it. */
1820 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1829 /* The simplification in expand_field_assignment may call back to
1830 get_last_value, so set safe guard here. */
1831 subst_low_luid
= DF_INSN_LUID (insn
);
1833 set
= expand_field_assignment (set
);
1834 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1836 /* Don't eliminate a store in the stack pointer. */
1837 if (dest
== stack_pointer_rtx
1838 /* Don't combine with an insn that sets a register to itself if it has
1839 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1840 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1841 /* Can't merge an ASM_OPERANDS. */
1842 || GET_CODE (src
) == ASM_OPERANDS
1843 /* Can't merge a function call. */
1844 || GET_CODE (src
) == CALL
1845 /* Don't eliminate a function call argument. */
1847 && (find_reg_fusage (i3
, USE
, dest
)
1849 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1850 && global_regs
[REGNO (dest
)])))
1851 /* Don't substitute into an incremented register. */
1852 || FIND_REG_INC_NOTE (i3
, dest
)
1853 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1854 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1855 /* Don't substitute into a non-local goto, this confuses CFG. */
1856 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1857 /* Make sure that DEST is not used after SUCC but before I3. */
1860 && (reg_used_between_p (dest
, succ2
, i3
)
1861 || reg_used_between_p (dest
, succ
, succ2
)))
1862 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1863 /* Make sure that the value that is to be substituted for the register
1864 does not use any registers whose values alter in between. However,
1865 If the insns are adjacent, a use can't cross a set even though we
1866 think it might (this can happen for a sequence of insns each setting
1867 the same destination; last_set of that register might point to
1868 a NOTE). If INSN has a REG_EQUIV note, the register is always
1869 equivalent to the memory so the substitution is valid even if there
1870 are intervening stores. Also, don't move a volatile asm or
1871 UNSPEC_VOLATILE across any other insns. */
1874 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1875 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1876 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1877 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1878 /* Don't combine across a CALL_INSN, because that would possibly
1879 change whether the life span of some REGs crosses calls or not,
1880 and it is a pain to update that information.
1881 Exception: if source is a constant, moving it later can't hurt.
1882 Accept that as a special case. */
1883 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1886 /* DEST must either be a REG or CC0. */
1889 /* If register alignment is being enforced for multi-word items in all
1890 cases except for parameters, it is possible to have a register copy
1891 insn referencing a hard register that is not allowed to contain the
1892 mode being copied and which would not be valid as an operand of most
1893 insns. Eliminate this problem by not combining with such an insn.
1895 Also, on some machines we don't want to extend the life of a hard
1899 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1901 /* Don't extend the life of a hard register unless it is
1902 user variable (if we have few registers) or it can't
1903 fit into the desired register (meaning something special
1905 Also avoid substituting a return register into I3, because
1906 reload can't handle a conflict with constraints of other
1908 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1909 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1912 else if (GET_CODE (dest
) != CC0
)
1916 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1917 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1918 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
1920 /* Don't substitute for a register intended as a clobberable
1922 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
1923 if (rtx_equal_p (reg
, dest
))
1926 /* If the clobber represents an earlyclobber operand, we must not
1927 substitute an expression containing the clobbered register.
1928 As we do not analyze the constraint strings here, we have to
1929 make the conservative assumption. However, if the register is
1930 a fixed hard reg, the clobber cannot represent any operand;
1931 we leave it up to the machine description to either accept or
1932 reject use-and-clobber patterns. */
1934 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1935 || !fixed_regs
[REGNO (reg
)])
1936 if (reg_overlap_mentioned_p (reg
, src
))
1940 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1941 or not), reject, unless nothing volatile comes between it and I3 */
1943 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1945 /* Make sure neither succ nor succ2 contains a volatile reference. */
1946 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
1948 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1950 /* We'll check insns between INSN and I3 below. */
1953 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1954 to be an explicit register variable, and was chosen for a reason. */
1956 if (GET_CODE (src
) == ASM_OPERANDS
1957 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1960 /* If INSN contains volatile references (specifically volatile MEMs),
1961 we cannot combine across any other volatile references.
1962 Even if INSN doesn't contain volatile references, any intervening
1963 volatile insn might affect machine state. */
1965 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
1969 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1970 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
1973 /* If INSN contains an autoincrement or autodecrement, make sure that
1974 register is not used between there and I3, and not already used in
1975 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1976 Also insist that I3 not be a jump; if it were one
1977 and the incremented register were spilled, we would lose. */
1980 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1981 if (REG_NOTE_KIND (link
) == REG_INC
1983 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1984 || (pred
!= NULL_RTX
1985 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
1986 || (pred2
!= NULL_RTX
1987 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
1988 || (succ
!= NULL_RTX
1989 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
1990 || (succ2
!= NULL_RTX
1991 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
1992 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1997 /* Don't combine an insn that follows a CC0-setting insn.
1998 An insn that uses CC0 must not be separated from the one that sets it.
1999 We do, however, allow I2 to follow a CC0-setting insn if that insn
2000 is passed as I1; in that case it will be deleted also.
2001 We also allow combining in this case if all the insns are adjacent
2002 because that would leave the two CC0 insns adjacent as well.
2003 It would be more logical to test whether CC0 occurs inside I1 or I2,
2004 but that would be much slower, and this ought to be equivalent. */
2006 p
= prev_nonnote_insn (insn
);
2007 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2012 /* If we get here, we have passed all the tests and the combination is
2021 /* LOC is the location within I3 that contains its pattern or the component
2022 of a PARALLEL of the pattern. We validate that it is valid for combining.
2024 One problem is if I3 modifies its output, as opposed to replacing it
2025 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2026 doing so would produce an insn that is not equivalent to the original insns.
2030 (set (reg:DI 101) (reg:DI 100))
2031 (set (subreg:SI (reg:DI 101) 0) <foo>)
2033 This is NOT equivalent to:
2035 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2036 (set (reg:DI 101) (reg:DI 100))])
2038 Not only does this modify 100 (in which case it might still be valid
2039 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2041 We can also run into a problem if I2 sets a register that I1
2042 uses and I1 gets directly substituted into I3 (not via I2). In that
2043 case, we would be getting the wrong value of I2DEST into I3, so we
2044 must reject the combination. This case occurs when I2 and I1 both
2045 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2046 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2047 of a SET must prevent combination from occurring. The same situation
2048 can occur for I0, in which case I0_NOT_IN_SRC is set.
2050 Before doing the above check, we first try to expand a field assignment
2051 into a set of logical operations.
2053 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2054 we place a register that is both set and used within I3. If more than one
2055 such register is detected, we fail.
2057 Return 1 if the combination is valid, zero otherwise. */
2060 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2061 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2065 if (GET_CODE (x
) == SET
)
2068 rtx dest
= SET_DEST (set
);
2069 rtx src
= SET_SRC (set
);
2070 rtx inner_dest
= dest
;
2073 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2074 || GET_CODE (inner_dest
) == SUBREG
2075 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2076 inner_dest
= XEXP (inner_dest
, 0);
2078 /* Check for the case where I3 modifies its output, as discussed
2079 above. We don't want to prevent pseudos from being combined
2080 into the address of a MEM, so only prevent the combination if
2081 i1 or i2 set the same MEM. */
2082 if ((inner_dest
!= dest
&&
2083 (!MEM_P (inner_dest
)
2084 || rtx_equal_p (i2dest
, inner_dest
)
2085 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2086 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2087 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2088 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2089 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2091 /* This is the same test done in can_combine_p except we can't test
2092 all_adjacent; we don't have to, since this instruction will stay
2093 in place, thus we are not considering increasing the lifetime of
2096 Also, if this insn sets a function argument, combining it with
2097 something that might need a spill could clobber a previous
2098 function argument; the all_adjacent test in can_combine_p also
2099 checks this; here, we do a more specific test for this case. */
2101 || (REG_P (inner_dest
)
2102 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2103 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2104 GET_MODE (inner_dest
))))
2105 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2106 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2109 /* If DEST is used in I3, it is being killed in this insn, so
2110 record that for later. We have to consider paradoxical
2111 subregs here, since they kill the whole register, but we
2112 ignore partial subregs, STRICT_LOW_PART, etc.
2113 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2114 STACK_POINTER_REGNUM, since these are always considered to be
2115 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2117 if (GET_CODE (subdest
) == SUBREG
2118 && (GET_MODE_SIZE (GET_MODE (subdest
))
2119 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2120 subdest
= SUBREG_REG (subdest
);
2123 && reg_referenced_p (subdest
, PATTERN (i3
))
2124 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2125 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2126 && REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
2128 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2129 && (REGNO (subdest
) != ARG_POINTER_REGNUM
2130 || ! fixed_regs
[REGNO (subdest
)])
2132 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2134 if (*pi3dest_killed
)
2137 *pi3dest_killed
= subdest
;
2141 else if (GET_CODE (x
) == PARALLEL
)
2145 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2146 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2147 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2154 /* Return 1 if X is an arithmetic expression that contains a multiplication
2155 and division. We don't count multiplications by powers of two here. */
2158 contains_muldiv (rtx x
)
2160 switch (GET_CODE (x
))
2162 case MOD
: case DIV
: case UMOD
: case UDIV
:
2166 return ! (CONST_INT_P (XEXP (x
, 1))
2167 && exact_log2 (UINTVAL (XEXP (x
, 1))) >= 0);
2170 return contains_muldiv (XEXP (x
, 0))
2171 || contains_muldiv (XEXP (x
, 1));
2174 return contains_muldiv (XEXP (x
, 0));
2180 /* Determine whether INSN can be used in a combination. Return nonzero if
2181 not. This is used in try_combine to detect early some cases where we
2182 can't perform combinations. */
2185 cant_combine_insn_p (rtx insn
)
2190 /* If this isn't really an insn, we can't do anything.
2191 This can occur when flow deletes an insn that it has merged into an
2192 auto-increment address. */
2193 if (! INSN_P (insn
))
2196 /* Never combine loads and stores involving hard regs that are likely
2197 to be spilled. The register allocator can usually handle such
2198 reg-reg moves by tying. If we allow the combiner to make
2199 substitutions of likely-spilled regs, reload might die.
2200 As an exception, we allow combinations involving fixed regs; these are
2201 not available to the register allocator so there's no risk involved. */
2203 set
= single_set (insn
);
2206 src
= SET_SRC (set
);
2207 dest
= SET_DEST (set
);
2208 if (GET_CODE (src
) == SUBREG
)
2209 src
= SUBREG_REG (src
);
2210 if (GET_CODE (dest
) == SUBREG
)
2211 dest
= SUBREG_REG (dest
);
2212 if (REG_P (src
) && REG_P (dest
)
2213 && ((HARD_REGISTER_P (src
)
2214 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2215 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2216 || (HARD_REGISTER_P (dest
)
2217 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2218 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2224 struct likely_spilled_retval_info
2226 unsigned regno
, nregs
;
2230 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2231 hard registers that are known to be written to / clobbered in full. */
2233 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2235 struct likely_spilled_retval_info
*const info
=
2236 (struct likely_spilled_retval_info
*) data
;
2237 unsigned regno
, nregs
;
2240 if (!REG_P (XEXP (set
, 0)))
2243 if (regno
>= info
->regno
+ info
->nregs
)
2245 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
2246 if (regno
+ nregs
<= info
->regno
)
2248 new_mask
= (2U << (nregs
- 1)) - 1;
2249 if (regno
< info
->regno
)
2250 new_mask
>>= info
->regno
- regno
;
2252 new_mask
<<= regno
- info
->regno
;
2253 info
->mask
&= ~new_mask
;
2256 /* Return nonzero iff part of the return value is live during INSN, and
2257 it is likely spilled. This can happen when more than one insn is needed
2258 to copy the return value, e.g. when we consider to combine into the
2259 second copy insn for a complex value. */
2262 likely_spilled_retval_p (rtx insn
)
2264 rtx use
= BB_END (this_basic_block
);
2266 unsigned regno
, nregs
;
2267 /* We assume here that no machine mode needs more than
2268 32 hard registers when the value overlaps with a register
2269 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2271 struct likely_spilled_retval_info info
;
2273 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2275 reg
= XEXP (PATTERN (use
), 0);
2276 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2278 regno
= REGNO (reg
);
2279 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
2282 mask
= (2U << (nregs
- 1)) - 1;
2284 /* Disregard parts of the return value that are set later. */
2288 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2290 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2293 /* Check if any of the (probably) live return value registers is
2298 if ((mask
& 1 << nregs
)
2299 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2305 /* Adjust INSN after we made a change to its destination.
2307 Changing the destination can invalidate notes that say something about
2308 the results of the insn and a LOG_LINK pointing to the insn. */
2311 adjust_for_new_dest (rtx insn
)
2313 /* For notes, be conservative and simply remove them. */
2314 remove_reg_equal_equiv_notes (insn
);
2316 /* The new insn will have a destination that was previously the destination
2317 of an insn just above it. Call distribute_links to make a LOG_LINK from
2318 the next use of that destination. */
2319 distribute_links (alloc_insn_link (insn
, NULL
));
2321 df_insn_rescan (insn
);
2324 /* Return TRUE if combine can reuse reg X in mode MODE.
2325 ADDED_SETS is nonzero if the original set is still required. */
2327 can_change_dest_mode (rtx x
, int added_sets
, enum machine_mode mode
)
2335 /* Allow hard registers if the new mode is legal, and occupies no more
2336 registers than the old mode. */
2337 if (regno
< FIRST_PSEUDO_REGISTER
)
2338 return (HARD_REGNO_MODE_OK (regno
, mode
)
2339 && (hard_regno_nregs
[regno
][GET_MODE (x
)]
2340 >= hard_regno_nregs
[regno
][mode
]));
2342 /* Or a pseudo that is only used once. */
2343 return (REG_N_SETS (regno
) == 1 && !added_sets
2344 && !REG_USERVAR_P (x
));
2348 /* Check whether X, the destination of a set, refers to part of
2349 the register specified by REG. */
2352 reg_subword_p (rtx x
, rtx reg
)
2354 /* Check that reg is an integer mode register. */
2355 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2358 if (GET_CODE (x
) == STRICT_LOW_PART
2359 || GET_CODE (x
) == ZERO_EXTRACT
)
2362 return GET_CODE (x
) == SUBREG
2363 && SUBREG_REG (x
) == reg
2364 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2367 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2368 Note that the INSN should be deleted *after* removing dead edges, so
2369 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2370 but not for a (set (pc) (label_ref FOO)). */
2373 update_cfg_for_uncondjump (rtx insn
)
2375 basic_block bb
= BLOCK_FOR_INSN (insn
);
2376 gcc_assert (BB_END (bb
) == insn
);
2378 purge_dead_edges (bb
);
2381 if (EDGE_COUNT (bb
->succs
) == 1)
2385 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2387 /* Remove barriers from the footer if there are any. */
2388 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2389 if (BARRIER_P (insn
))
2391 if (PREV_INSN (insn
))
2392 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2394 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2395 if (NEXT_INSN (insn
))
2396 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2398 else if (LABEL_P (insn
))
2403 /* Try to combine the insns I0, I1 and I2 into I3.
2404 Here I0, I1 and I2 appear earlier than I3.
2405 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2408 If we are combining more than two insns and the resulting insn is not
2409 recognized, try splitting it into two insns. If that happens, I2 and I3
2410 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2411 Otherwise, I0, I1 and I2 are pseudo-deleted.
2413 Return 0 if the combination does not work. Then nothing is changed.
2414 If we did the combination, return the insn at which combine should
2417 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2418 new direct jump instruction.
2420 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2421 been I3 passed to an earlier try_combine within the same basic
2425 try_combine (rtx i3
, rtx i2
, rtx i1
, rtx i0
, int *new_direct_jump_p
,
2426 rtx last_combined_insn
)
2428 /* New patterns for I3 and I2, respectively. */
2429 rtx newpat
, newi2pat
= 0;
2430 rtvec newpat_vec_with_clobbers
= 0;
2431 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2432 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2434 int added_sets_0
, added_sets_1
, added_sets_2
;
2435 /* Total number of SETs to put into I3. */
2437 /* Nonzero if I2's or I1's body now appears in I3. */
2438 int i2_is_used
= 0, i1_is_used
= 0;
2439 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2440 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2441 /* Contains I3 if the destination of I3 is used in its source, which means
2442 that the old life of I3 is being killed. If that usage is placed into
2443 I2 and not in I3, a REG_DEAD note must be made. */
2444 rtx i3dest_killed
= 0;
2445 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2446 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2447 /* Copy of SET_SRC of I1 and I0, if needed. */
2448 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2449 /* Set if I2DEST was reused as a scratch register. */
2450 bool i2scratch
= false;
2451 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2452 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2453 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2454 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2455 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2456 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2457 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2458 /* Notes that must be added to REG_NOTES in I3 and I2. */
2459 rtx new_i3_notes
, new_i2_notes
;
2460 /* Notes that we substituted I3 into I2 instead of the normal case. */
2461 int i3_subst_into_i2
= 0;
2462 /* Notes that I1, I2 or I3 is a MULT operation. */
2465 int changed_i3_dest
= 0;
2469 struct insn_link
*link
;
2471 rtx new_other_notes
;
2474 /* Only try four-insn combinations when there's high likelihood of
2475 success. Look for simple insns, such as loads of constants or
2476 binary operations involving a constant. */
2483 if (!flag_expensive_optimizations
)
2486 for (i
= 0; i
< 4; i
++)
2488 rtx insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2489 rtx set
= single_set (insn
);
2493 src
= SET_SRC (set
);
2494 if (CONSTANT_P (src
))
2499 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2501 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2502 || GET_CODE (src
) == LSHIFTRT
)
2505 if (ngood
< 2 && nshift
< 2)
2509 /* Exit early if one of the insns involved can't be used for
2511 if (cant_combine_insn_p (i3
)
2512 || cant_combine_insn_p (i2
)
2513 || (i1
&& cant_combine_insn_p (i1
))
2514 || (i0
&& cant_combine_insn_p (i0
))
2515 || likely_spilled_retval_p (i3
))
2519 undobuf
.other_insn
= 0;
2521 /* Reset the hard register usage information. */
2522 CLEAR_HARD_REG_SET (newpat_used_regs
);
2524 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2527 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2528 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2530 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2531 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2533 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2534 INSN_UID (i2
), INSN_UID (i3
));
2537 /* If multiple insns feed into one of I2 or I3, they can be in any
2538 order. To simplify the code below, reorder them in sequence. */
2539 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2540 temp
= i2
, i2
= i0
, i0
= temp
;
2541 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2542 temp
= i1
, i1
= i0
, i0
= temp
;
2543 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2544 temp
= i1
, i1
= i2
, i2
= temp
;
2546 added_links_insn
= 0;
2548 /* First check for one important special case that the code below will
2549 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2550 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2551 we may be able to replace that destination with the destination of I3.
2552 This occurs in the common code where we compute both a quotient and
2553 remainder into a structure, in which case we want to do the computation
2554 directly into the structure to avoid register-register copies.
2556 Note that this case handles both multiple sets in I2 and also cases
2557 where I2 has a number of CLOBBERs inside the PARALLEL.
2559 We make very conservative checks below and only try to handle the
2560 most common cases of this. For example, we only handle the case
2561 where I2 and I3 are adjacent to avoid making difficult register
2564 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2565 && REG_P (SET_SRC (PATTERN (i3
)))
2566 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2567 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2568 && GET_CODE (PATTERN (i2
)) == PARALLEL
2569 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2570 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2571 below would need to check what is inside (and reg_overlap_mentioned_p
2572 doesn't support those codes anyway). Don't allow those destinations;
2573 the resulting insn isn't likely to be recognized anyway. */
2574 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2575 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2576 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2577 SET_DEST (PATTERN (i3
)))
2578 && next_active_insn (i2
) == i3
)
2580 rtx p2
= PATTERN (i2
);
2582 /* Make sure that the destination of I3,
2583 which we are going to substitute into one output of I2,
2584 is not used within another output of I2. We must avoid making this:
2585 (parallel [(set (mem (reg 69)) ...)
2586 (set (reg 69) ...)])
2587 which is not well-defined as to order of actions.
2588 (Besides, reload can't handle output reloads for this.)
2590 The problem can also happen if the dest of I3 is a memory ref,
2591 if another dest in I2 is an indirect memory ref. */
2592 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2593 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2594 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2595 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2596 SET_DEST (XVECEXP (p2
, 0, i
))))
2599 if (i
== XVECLEN (p2
, 0))
2600 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2601 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2602 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2607 subst_low_luid
= DF_INSN_LUID (i2
);
2609 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2610 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2611 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2612 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2614 /* Replace the dest in I2 with our dest and make the resulting
2615 insn the new pattern for I3. Then skip to where we validate
2616 the pattern. Everything was set up above. */
2617 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2619 i3_subst_into_i2
= 1;
2620 goto validate_replacement
;
2624 /* If I2 is setting a pseudo to a constant and I3 is setting some
2625 sub-part of it to another constant, merge them by making a new
2628 && (temp
= single_set (i2
)) != 0
2629 && CONST_SCALAR_INT_P (SET_SRC (temp
))
2630 && GET_CODE (PATTERN (i3
)) == SET
2631 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2632 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp
)))
2634 rtx dest
= SET_DEST (PATTERN (i3
));
2638 /* There are not explicit tests to make sure that this is not a
2639 float, but there is code here that would not be correct if it
2641 gcc_assert (GET_MODE_CLASS (GET_MODE (SET_SRC (temp
))) != MODE_FLOAT
);
2643 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2645 if (CONST_INT_P (XEXP (dest
, 1))
2646 && CONST_INT_P (XEXP (dest
, 2)))
2648 width
= INTVAL (XEXP (dest
, 1));
2649 offset
= INTVAL (XEXP (dest
, 2));
2650 dest
= XEXP (dest
, 0);
2651 if (BITS_BIG_ENDIAN
)
2652 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2657 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2658 dest
= XEXP (dest
, 0);
2659 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2665 /* If this is the low part, we're done. */
2666 if (subreg_lowpart_p (dest
))
2668 /* Handle the case where inner is twice the size of outer. */
2669 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2670 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2671 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2672 /* Otherwise give up for now. */
2678 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp
)))
2679 <= HOST_BITS_PER_DOUBLE_INT
))
2682 rtx inner
= SET_SRC (PATTERN (i3
));
2683 rtx outer
= SET_SRC (temp
);
2685 o
= rtx_to_double_int (outer
);
2686 i
= rtx_to_double_int (inner
);
2688 m
= double_int::mask (width
);
2690 m
= m
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2691 i
= i
.llshift (offset
, HOST_BITS_PER_DOUBLE_INT
);
2692 o
= o
.and_not (m
) | i
;
2696 subst_low_luid
= DF_INSN_LUID (i2
);
2697 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2698 i2dest
= SET_DEST (temp
);
2699 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2701 /* Replace the source in I2 with the new constant and make the
2702 resulting insn the new pattern for I3. Then skip to where we
2703 validate the pattern. Everything was set up above. */
2704 SUBST (SET_SRC (temp
),
2705 immed_double_int_const (o
, GET_MODE (SET_DEST (temp
))));
2707 newpat
= PATTERN (i2
);
2709 /* The dest of I3 has been replaced with the dest of I2. */
2710 changed_i3_dest
= 1;
2711 goto validate_replacement
;
2716 /* If we have no I1 and I2 looks like:
2717 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2719 make up a dummy I1 that is
2722 (set (reg:CC X) (compare:CC Y (const_int 0)))
2724 (We can ignore any trailing CLOBBERs.)
2726 This undoes a previous combination and allows us to match a branch-and-
2729 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
2730 && XVECLEN (PATTERN (i2
), 0) >= 2
2731 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
2732 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2734 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2735 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2736 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
2737 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)))
2738 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2739 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
2741 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
2742 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
2747 /* We make I1 with the same INSN_UID as I2. This gives it
2748 the same DF_INSN_LUID for value tracking. Our fake I1 will
2749 never appear in the insn stream so giving it the same INSN_UID
2750 as I2 will not cause a problem. */
2752 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
2753 BLOCK_FOR_INSN (i2
), XVECEXP (PATTERN (i2
), 0, 1),
2754 INSN_LOCATION (i2
), -1, NULL_RTX
);
2756 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2757 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2758 SET_DEST (PATTERN (i1
)));
2759 SUBST_LINK (LOG_LINKS (i2
), alloc_insn_link (i1
, LOG_LINKS (i2
)));
2764 /* Verify that I2 and I1 are valid for combining. */
2765 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL_RTX
, NULL_RTX
, &i2dest
, &i2src
)
2766 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL_RTX
, i2
, NULL_RTX
,
2768 || (i0
&& ! can_combine_p (i0
, i3
, NULL_RTX
, NULL_RTX
, i1
, i2
,
2775 /* Record whether I2DEST is used in I2SRC and similarly for the other
2776 cases. Knowing this will help in register status updating below. */
2777 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2778 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2779 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2780 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2781 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2782 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2783 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2784 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2785 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2787 /* For the earlier insns, determine which of the subsequent ones they
2789 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2790 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2791 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2792 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2793 && reg_overlap_mentioned_p (i0dest
, i2src
))));
2795 /* Ensure that I3's pattern can be the destination of combines. */
2796 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
2797 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
2798 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
2799 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
2806 /* See if any of the insns is a MULT operation. Unless one is, we will
2807 reject a combination that is, since it must be slower. Be conservative
2809 if (GET_CODE (i2src
) == MULT
2810 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
2811 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
2812 || (GET_CODE (PATTERN (i3
)) == SET
2813 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
2816 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2817 We used to do this EXCEPT in one case: I3 has a post-inc in an
2818 output operand. However, that exception can give rise to insns like
2820 which is a famous insn on the PDP-11 where the value of r3 used as the
2821 source was model-dependent. Avoid this sort of thing. */
2824 if (!(GET_CODE (PATTERN (i3
)) == SET
2825 && REG_P (SET_SRC (PATTERN (i3
)))
2826 && MEM_P (SET_DEST (PATTERN (i3
)))
2827 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
2828 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
2829 /* It's not the exception. */
2834 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
2835 if (REG_NOTE_KIND (link
) == REG_INC
2836 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
2838 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
2846 /* See if the SETs in I1 or I2 need to be kept around in the merged
2847 instruction: whenever the value set there is still needed past I3.
2848 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2850 For the SET in I1, we have two cases: if I1 and I2 independently feed
2851 into I3, the set in I1 needs to be kept around unless I1DEST dies
2852 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2853 in I1 needs to be kept around unless I1DEST dies or is set in either
2854 I2 or I3. The same considerations apply to I0. */
2856 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
2859 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
2860 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
2865 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
2866 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
2867 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
2868 && dead_or_set_p (i2
, i0dest
)));
2872 /* We are about to copy insns for the case where they need to be kept
2873 around. Check that they can be copied in the merged instruction. */
2875 if (targetm
.cannot_copy_insn_p
2876 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
2877 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
2878 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
2884 /* If the set in I2 needs to be kept around, we must make a copy of
2885 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2886 PATTERN (I2), we are only substituting for the original I1DEST, not into
2887 an already-substituted copy. This also prevents making self-referential
2888 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2893 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2894 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, copy_rtx (i2src
));
2896 i2pat
= copy_rtx (PATTERN (i2
));
2901 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
2902 i1pat
= gen_rtx_SET (VOIDmode
, i1dest
, copy_rtx (i1src
));
2904 i1pat
= copy_rtx (PATTERN (i1
));
2909 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
2910 i0pat
= gen_rtx_SET (VOIDmode
, i0dest
, copy_rtx (i0src
));
2912 i0pat
= copy_rtx (PATTERN (i0
));
2917 /* Substitute in the latest insn for the regs set by the earlier ones. */
2919 maxreg
= max_reg_num ();
2924 /* Many machines that don't use CC0 have insns that can both perform an
2925 arithmetic operation and set the condition code. These operations will
2926 be represented as a PARALLEL with the first element of the vector
2927 being a COMPARE of an arithmetic operation with the constant zero.
2928 The second element of the vector will set some pseudo to the result
2929 of the same arithmetic operation. If we simplify the COMPARE, we won't
2930 match such a pattern and so will generate an extra insn. Here we test
2931 for this case, where both the comparison and the operation result are
2932 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2933 I2SRC. Later we will make the PARALLEL that contains I2. */
2935 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
2936 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
2937 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
2938 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
2941 rtx
*cc_use_loc
= NULL
, cc_use_insn
= NULL_RTX
;
2942 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
2943 enum machine_mode compare_mode
, orig_compare_mode
;
2944 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
2946 newpat
= PATTERN (i3
);
2947 newpat_dest
= SET_DEST (newpat
);
2948 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
2950 if (undobuf
.other_insn
== 0
2951 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
2954 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
2955 compare_code
= simplify_compare_const (compare_code
,
2957 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
2960 /* Do the rest only if op1 is const0_rtx, which may be the
2961 result of simplification. */
2962 if (op1
== const0_rtx
)
2964 /* If a single use of the CC is found, prepare to modify it
2965 when SELECT_CC_MODE returns a new CC-class mode, or when
2966 the above simplify_compare_const() returned a new comparison
2967 operator. undobuf.other_insn is assigned the CC use insn
2968 when modifying it. */
2971 #ifdef SELECT_CC_MODE
2972 enum machine_mode new_mode
2973 = SELECT_CC_MODE (compare_code
, op0
, op1
);
2974 if (new_mode
!= orig_compare_mode
2975 && can_change_dest_mode (SET_DEST (newpat
),
2976 added_sets_2
, new_mode
))
2978 unsigned int regno
= REGNO (newpat_dest
);
2979 compare_mode
= new_mode
;
2980 if (regno
< FIRST_PSEUDO_REGISTER
)
2981 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
2984 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
2985 newpat_dest
= regno_reg_rtx
[regno
];
2989 /* Cases for modifying the CC-using comparison. */
2990 if (compare_code
!= orig_compare_code
2991 /* ??? Do we need to verify the zero rtx? */
2992 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
2994 /* Replace cc_use_loc with entire new RTX. */
2996 gen_rtx_fmt_ee (compare_code
, compare_mode
,
2997 newpat_dest
, const0_rtx
));
2998 undobuf
.other_insn
= cc_use_insn
;
3000 else if (compare_mode
!= orig_compare_mode
)
3002 /* Just replace the CC reg with a new mode. */
3003 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3004 undobuf
.other_insn
= cc_use_insn
;
3008 /* Now we modify the current newpat:
3009 First, SET_DEST(newpat) is updated if the CC mode has been
3010 altered. For targets without SELECT_CC_MODE, this should be
3012 if (compare_mode
!= orig_compare_mode
)
3013 SUBST (SET_DEST (newpat
), newpat_dest
);
3014 /* This is always done to propagate i2src into newpat. */
3015 SUBST (SET_SRC (newpat
),
3016 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3017 /* Create new version of i2pat if needed; the below PARALLEL
3018 creation needs this to work correctly. */
3019 if (! rtx_equal_p (i2src
, op0
))
3020 i2pat
= gen_rtx_SET (VOIDmode
, i2dest
, op0
);
3026 if (i2_is_used
== 0)
3028 /* It is possible that the source of I2 or I1 may be performing
3029 an unneeded operation, such as a ZERO_EXTEND of something
3030 that is known to have the high part zero. Handle that case
3031 by letting subst look at the inner insns.
3033 Another way to do this would be to have a function that tries
3034 to simplify a single insn instead of merging two or more
3035 insns. We don't do this because of the potential of infinite
3036 loops and because of the potential extra memory required.
3037 However, doing it the way we are is a bit of a kludge and
3038 doesn't catch all cases.
3040 But only do this if -fexpensive-optimizations since it slows
3041 things down and doesn't usually win.
3043 This is not done in the COMPARE case above because the
3044 unmodified I2PAT is used in the PARALLEL and so a pattern
3045 with a modified I2SRC would not match. */
3047 if (flag_expensive_optimizations
)
3049 /* Pass pc_rtx so no substitutions are done, just
3053 subst_low_luid
= DF_INSN_LUID (i1
);
3054 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3057 subst_low_luid
= DF_INSN_LUID (i2
);
3058 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3061 n_occurrences
= 0; /* `subst' counts here */
3062 subst_low_luid
= DF_INSN_LUID (i2
);
3064 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3065 copy of I2SRC each time we substitute it, in order to avoid creating
3066 self-referential RTL when we will be substituting I1SRC for I1DEST
3067 later. Likewise if I0 feeds into I2, either directly or indirectly
3068 through I1, and I0DEST is in I0SRC. */
3069 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3070 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3071 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3072 && i0dest_in_i0src
));
3075 /* Record whether I2's body now appears within I3's body. */
3076 i2_is_used
= n_occurrences
;
3079 /* If we already got a failure, don't try to do more. Otherwise, try to
3080 substitute I1 if we have it. */
3082 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3084 /* Check that an autoincrement side-effect on I1 has not been lost.
3085 This happens if I1DEST is mentioned in I2 and dies there, and
3086 has disappeared from the new pattern. */
3087 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3089 && dead_or_set_p (i2
, i1dest
)
3090 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3091 /* Before we can do this substitution, we must redo the test done
3092 above (see detailed comments there) that ensures I1DEST isn't
3093 mentioned in any SETs in NEWPAT that are field assignments. */
3094 || !combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3102 subst_low_luid
= DF_INSN_LUID (i1
);
3104 /* If the following substitution will modify I1SRC, make a copy of it
3105 for the case where it is substituted for I1DEST in I2PAT later. */
3106 if (added_sets_2
&& i1_feeds_i2_n
)
3107 i1src_copy
= copy_rtx (i1src
);
3109 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3110 copy of I1SRC each time we substitute it, in order to avoid creating
3111 self-referential RTL when we will be substituting I0SRC for I0DEST
3113 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3114 i0_feeds_i1_n
&& i0dest_in_i0src
);
3117 /* Record whether I1's body now appears within I3's body. */
3118 i1_is_used
= n_occurrences
;
3121 /* Likewise for I0 if we have it. */
3123 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3125 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3126 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3127 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3128 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3129 || !combinable_i3pat (NULL_RTX
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3136 /* If the following substitution will modify I0SRC, make a copy of it
3137 for the case where it is substituted for I0DEST in I1PAT later. */
3138 if (added_sets_1
&& i0_feeds_i1_n
)
3139 i0src_copy
= copy_rtx (i0src
);
3140 /* And a copy for I0DEST in I2PAT substitution. */
3141 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3142 || (i0_feeds_i2_n
)))
3143 i0src_copy2
= copy_rtx (i0src
);
3146 subst_low_luid
= DF_INSN_LUID (i0
);
3147 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3151 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3152 to count all the ways that I2SRC and I1SRC can be used. */
3153 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3154 && i2_is_used
+ added_sets_2
> 1)
3155 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3156 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3158 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3159 && (n_occurrences
+ added_sets_0
3160 + (added_sets_1
&& i0_feeds_i1_n
)
3161 + (added_sets_2
&& i0_feeds_i2_n
)
3163 /* Fail if we tried to make a new register. */
3164 || max_reg_num () != maxreg
3165 /* Fail if we couldn't do something and have a CLOBBER. */
3166 || GET_CODE (newpat
) == CLOBBER
3167 /* Fail if this new pattern is a MULT and we didn't have one before
3168 at the outer level. */
3169 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3176 /* If the actions of the earlier insns must be kept
3177 in addition to substituting them into the latest one,
3178 we must make a new PARALLEL for the latest insn
3179 to hold additional the SETs. */
3181 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3183 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3186 if (GET_CODE (newpat
) == PARALLEL
)
3188 rtvec old
= XVEC (newpat
, 0);
3189 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3190 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3191 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3192 sizeof (old
->elem
[0]) * old
->num_elem
);
3197 total_sets
= 1 + extra_sets
;
3198 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3199 XVECEXP (newpat
, 0, 0) = old
;
3203 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3209 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3211 XVECEXP (newpat
, 0, --total_sets
) = t
;
3217 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3218 i0_feeds_i1_n
&& i0dest_in_i0src
);
3219 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3220 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3222 XVECEXP (newpat
, 0, --total_sets
) = t
;
3226 validate_replacement
:
3228 /* Note which hard regs this insn has as inputs. */
3229 mark_used_regs_combine (newpat
);
3231 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3232 consider splitting this pattern, we might need these clobbers. */
3233 if (i1
&& GET_CODE (newpat
) == PARALLEL
3234 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3236 int len
= XVECLEN (newpat
, 0);
3238 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3239 for (i
= 0; i
< len
; i
++)
3240 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3243 /* Is the result of combination a valid instruction? */
3244 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3246 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3247 the second SET's destination is a register that is unused and isn't
3248 marked as an instruction that might trap in an EH region. In that case,
3249 we just need the first SET. This can occur when simplifying a divmod
3250 insn. We *must* test for this case here because the code below that
3251 splits two independent SETs doesn't handle this case correctly when it
3252 updates the register status.
3254 It's pointless doing this if we originally had two sets, one from
3255 i3, and one from i2. Combining then splitting the parallel results
3256 in the original i2 again plus an invalid insn (which we delete).
3257 The net effect is only to move instructions around, which makes
3258 debug info less accurate.
3260 Also check the case where the first SET's destination is unused.
3261 That would not cause incorrect code, but does cause an unneeded
3264 if (insn_code_number
< 0
3265 && !(added_sets_2
&& i1
== 0)
3266 && GET_CODE (newpat
) == PARALLEL
3267 && XVECLEN (newpat
, 0) == 2
3268 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3269 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3270 && asm_noperands (newpat
) < 0)
3272 rtx set0
= XVECEXP (newpat
, 0, 0);
3273 rtx set1
= XVECEXP (newpat
, 0, 1);
3275 if (((REG_P (SET_DEST (set1
))
3276 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3277 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3278 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3279 && insn_nothrow_p (i3
)
3280 && !side_effects_p (SET_SRC (set1
)))
3283 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3286 else if (((REG_P (SET_DEST (set0
))
3287 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3288 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3289 && find_reg_note (i3
, REG_UNUSED
,
3290 SUBREG_REG (SET_DEST (set0
)))))
3291 && insn_nothrow_p (i3
)
3292 && !side_effects_p (SET_SRC (set0
)))
3295 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3297 if (insn_code_number
>= 0)
3298 changed_i3_dest
= 1;
3302 /* If we were combining three insns and the result is a simple SET
3303 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3304 insns. There are two ways to do this. It can be split using a
3305 machine-specific method (like when you have an addition of a large
3306 constant) or by combine in the function find_split_point. */
3308 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3309 && asm_noperands (newpat
) < 0)
3311 rtx parallel
, m_split
, *split
;
3313 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3314 use I2DEST as a scratch register will help. In the latter case,
3315 convert I2DEST to the mode of the source of NEWPAT if we can. */
3317 m_split
= combine_split_insns (newpat
, i3
);
3319 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3320 inputs of NEWPAT. */
3322 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3323 possible to try that as a scratch reg. This would require adding
3324 more code to make it work though. */
3326 if (m_split
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3328 enum machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3330 /* First try to split using the original register as a
3331 scratch register. */
3332 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3333 gen_rtvec (2, newpat
,
3334 gen_rtx_CLOBBER (VOIDmode
,
3336 m_split
= combine_split_insns (parallel
, i3
);
3338 /* If that didn't work, try changing the mode of I2DEST if
3341 && new_mode
!= GET_MODE (i2dest
)
3342 && new_mode
!= VOIDmode
3343 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3345 enum machine_mode old_mode
= GET_MODE (i2dest
);
3348 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3349 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3352 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3353 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3356 parallel
= (gen_rtx_PARALLEL
3358 gen_rtvec (2, newpat
,
3359 gen_rtx_CLOBBER (VOIDmode
,
3361 m_split
= combine_split_insns (parallel
, i3
);
3364 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3368 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3369 buf
= undobuf
.undos
;
3370 undobuf
.undos
= buf
->next
;
3371 buf
->next
= undobuf
.frees
;
3372 undobuf
.frees
= buf
;
3376 i2scratch
= m_split
!= 0;
3379 /* If recog_for_combine has discarded clobbers, try to use them
3380 again for the split. */
3381 if (m_split
== 0 && newpat_vec_with_clobbers
)
3383 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3384 m_split
= combine_split_insns (parallel
, i3
);
3387 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
3389 m_split
= PATTERN (m_split
);
3390 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
3391 if (insn_code_number
>= 0)
3394 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
3395 && (next_nonnote_nondebug_insn (i2
) == i3
3396 || ! use_crosses_set_p (PATTERN (m_split
), DF_INSN_LUID (i2
))))
3399 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
3400 newi2pat
= PATTERN (m_split
);
3402 i3set
= single_set (NEXT_INSN (m_split
));
3403 i2set
= single_set (m_split
);
3405 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3407 /* If I2 or I3 has multiple SETs, we won't know how to track
3408 register status, so don't use these insns. If I2's destination
3409 is used between I2 and I3, we also can't use these insns. */
3411 if (i2_code_number
>= 0 && i2set
&& i3set
3412 && (next_nonnote_nondebug_insn (i2
) == i3
3413 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3414 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3416 if (insn_code_number
>= 0)
3419 /* It is possible that both insns now set the destination of I3.
3420 If so, we must show an extra use of it. */
3422 if (insn_code_number
>= 0)
3424 rtx new_i3_dest
= SET_DEST (i3set
);
3425 rtx new_i2_dest
= SET_DEST (i2set
);
3427 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3428 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3429 || GET_CODE (new_i3_dest
) == SUBREG
)
3430 new_i3_dest
= XEXP (new_i3_dest
, 0);
3432 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3433 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3434 || GET_CODE (new_i2_dest
) == SUBREG
)
3435 new_i2_dest
= XEXP (new_i2_dest
, 0);
3437 if (REG_P (new_i3_dest
)
3438 && REG_P (new_i2_dest
)
3439 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
3440 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3444 /* If we can split it and use I2DEST, go ahead and see if that
3445 helps things be recognized. Verify that none of the registers
3446 are set between I2 and I3. */
3447 if (insn_code_number
< 0
3448 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3452 /* We need I2DEST in the proper mode. If it is a hard register
3453 or the only use of a pseudo, we can change its mode.
3454 Make sure we don't change a hard register to have a mode that
3455 isn't valid for it, or change the number of registers. */
3456 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3457 || GET_MODE (*split
) == VOIDmode
3458 || can_change_dest_mode (i2dest
, added_sets_2
,
3460 && (next_nonnote_nondebug_insn (i2
) == i3
3461 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3462 /* We can't overwrite I2DEST if its value is still used by
3464 && ! reg_referenced_p (i2dest
, newpat
))
3466 rtx newdest
= i2dest
;
3467 enum rtx_code split_code
= GET_CODE (*split
);
3468 enum machine_mode split_mode
= GET_MODE (*split
);
3469 bool subst_done
= false;
3470 newi2pat
= NULL_RTX
;
3474 /* *SPLIT may be part of I2SRC, so make sure we have the
3475 original expression around for later debug processing.
3476 We should not need I2SRC any more in other cases. */
3477 if (MAY_HAVE_DEBUG_INSNS
)
3478 i2src
= copy_rtx (i2src
);
3482 /* Get NEWDEST as a register in the proper mode. We have already
3483 validated that we can do this. */
3484 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3486 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3487 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3490 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3491 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3495 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3496 an ASHIFT. This can occur if it was inside a PLUS and hence
3497 appeared to be a memory address. This is a kludge. */
3498 if (split_code
== MULT
3499 && CONST_INT_P (XEXP (*split
, 1))
3500 && INTVAL (XEXP (*split
, 1)) > 0
3501 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3503 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3504 XEXP (*split
, 0), GEN_INT (i
)));
3505 /* Update split_code because we may not have a multiply
3507 split_code
= GET_CODE (*split
);
3510 #ifdef INSN_SCHEDULING
3511 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3512 be written as a ZERO_EXTEND. */
3513 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3515 #ifdef LOAD_EXTEND_OP
3516 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3517 what it really is. */
3518 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3520 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3521 SUBREG_REG (*split
)));
3524 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3525 SUBREG_REG (*split
)));
3529 /* Attempt to split binary operators using arithmetic identities. */
3530 if (BINARY_P (SET_SRC (newpat
))
3531 && split_mode
== GET_MODE (SET_SRC (newpat
))
3532 && ! side_effects_p (SET_SRC (newpat
)))
3534 rtx setsrc
= SET_SRC (newpat
);
3535 enum machine_mode mode
= GET_MODE (setsrc
);
3536 enum rtx_code code
= GET_CODE (setsrc
);
3537 rtx src_op0
= XEXP (setsrc
, 0);
3538 rtx src_op1
= XEXP (setsrc
, 1);
3540 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3541 if (rtx_equal_p (src_op0
, src_op1
))
3543 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, src_op0
);
3544 SUBST (XEXP (setsrc
, 0), newdest
);
3545 SUBST (XEXP (setsrc
, 1), newdest
);
3548 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3549 else if ((code
== PLUS
|| code
== MULT
)
3550 && GET_CODE (src_op0
) == code
3551 && GET_CODE (XEXP (src_op0
, 0)) == code
3552 && (INTEGRAL_MODE_P (mode
)
3553 || (FLOAT_MODE_P (mode
)
3554 && flag_unsafe_math_optimizations
)))
3556 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3557 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3558 rtx r
= XEXP (src_op0
, 1);
3561 /* Split both "((X op Y) op X) op Y" and
3562 "((X op Y) op Y) op X" as "T op T" where T is
3564 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3565 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3567 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
,
3569 SUBST (XEXP (setsrc
, 0), newdest
);
3570 SUBST (XEXP (setsrc
, 1), newdest
);
3573 /* Split "((X op X) op Y) op Y)" as "T op T" where
3575 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3577 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3578 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, tmp
);
3579 SUBST (XEXP (setsrc
, 0), newdest
);
3580 SUBST (XEXP (setsrc
, 1), newdest
);
3588 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
3589 SUBST (*split
, newdest
);
3592 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3594 /* recog_for_combine might have added CLOBBERs to newi2pat.
3595 Make sure NEWPAT does not depend on the clobbered regs. */
3596 if (GET_CODE (newi2pat
) == PARALLEL
)
3597 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3598 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3600 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3601 if (reg_overlap_mentioned_p (reg
, newpat
))
3608 /* If the split point was a MULT and we didn't have one before,
3609 don't use one now. */
3610 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3611 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3615 /* Check for a case where we loaded from memory in a narrow mode and
3616 then sign extended it, but we need both registers. In that case,
3617 we have a PARALLEL with both loads from the same memory location.
3618 We can split this into a load from memory followed by a register-register
3619 copy. This saves at least one insn, more if register allocation can
3622 We cannot do this if the destination of the first assignment is a
3623 condition code register or cc0. We eliminate this case by making sure
3624 the SET_DEST and SET_SRC have the same mode.
3626 We cannot do this if the destination of the second assignment is
3627 a register that we have already assumed is zero-extended. Similarly
3628 for a SUBREG of such a register. */
3630 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3631 && GET_CODE (newpat
) == PARALLEL
3632 && XVECLEN (newpat
, 0) == 2
3633 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3634 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3635 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3636 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3637 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3638 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3639 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3640 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3642 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3643 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3644 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3646 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3647 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3648 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3649 && (reg_stat
[REGNO (temp
)].nonzero_bits
3650 != GET_MODE_MASK (word_mode
))))
3651 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3652 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3654 && reg_stat
[REGNO (temp
)].nonzero_bits
!= 0
3655 && GET_MODE_PRECISION (GET_MODE (temp
)) < BITS_PER_WORD
3656 && GET_MODE_PRECISION (GET_MODE (temp
)) < HOST_BITS_PER_INT
3657 && (reg_stat
[REGNO (temp
)].nonzero_bits
3658 != GET_MODE_MASK (word_mode
)))))
3659 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3660 SET_SRC (XVECEXP (newpat
, 0, 1)))
3661 && ! find_reg_note (i3
, REG_UNUSED
,
3662 SET_DEST (XVECEXP (newpat
, 0, 0))))
3666 newi2pat
= XVECEXP (newpat
, 0, 0);
3667 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3668 newpat
= XVECEXP (newpat
, 0, 1);
3669 SUBST (SET_SRC (newpat
),
3670 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3671 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3673 if (i2_code_number
>= 0)
3674 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3676 if (insn_code_number
>= 0)
3680 /* Similarly, check for a case where we have a PARALLEL of two independent
3681 SETs but we started with three insns. In this case, we can do the sets
3682 as two separate insns. This case occurs when some SET allows two
3683 other insns to combine, but the destination of that SET is still live. */
3685 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3686 && GET_CODE (newpat
) == PARALLEL
3687 && XVECLEN (newpat
, 0) == 2
3688 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3689 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3690 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3691 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3692 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3693 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3694 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3695 XVECEXP (newpat
, 0, 0))
3696 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3697 XVECEXP (newpat
, 0, 1))
3698 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3699 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3701 /* Normally, it doesn't matter which of the two is done first,
3702 but the one that references cc0 can't be the second, and
3703 one which uses any regs/memory set in between i2 and i3 can't
3705 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3708 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0))
3712 newi2pat
= XVECEXP (newpat
, 0, 1);
3713 newpat
= XVECEXP (newpat
, 0, 0);
3715 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 0)),
3718 && !reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 1))
3722 newi2pat
= XVECEXP (newpat
, 0, 0);
3723 newpat
= XVECEXP (newpat
, 0, 1);
3731 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3733 if (i2_code_number
>= 0)
3735 /* recog_for_combine might have added CLOBBERs to newi2pat.
3736 Make sure NEWPAT does not depend on the clobbered regs. */
3737 if (GET_CODE (newi2pat
) == PARALLEL
)
3739 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3740 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3742 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3743 if (reg_overlap_mentioned_p (reg
, newpat
))
3751 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3755 /* If it still isn't recognized, fail and change things back the way they
3757 if ((insn_code_number
< 0
3758 /* Is the result a reasonable ASM_OPERANDS? */
3759 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
3765 /* If we had to change another insn, make sure it is valid also. */
3766 if (undobuf
.other_insn
)
3768 CLEAR_HARD_REG_SET (newpat_used_regs
);
3770 other_pat
= PATTERN (undobuf
.other_insn
);
3771 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
3774 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
3782 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3783 they are adjacent to each other or not. */
3785 rtx p
= prev_nonnote_insn (i3
);
3786 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
3787 && sets_cc0_p (newi2pat
))
3795 /* Only allow this combination if insn_rtx_costs reports that the
3796 replacement instructions are cheaper than the originals. */
3797 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
3803 if (MAY_HAVE_DEBUG_INSNS
)
3807 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
3808 if (undo
->kind
== UNDO_MODE
)
3810 rtx reg
= *undo
->where
.r
;
3811 enum machine_mode new_mode
= GET_MODE (reg
);
3812 enum machine_mode old_mode
= undo
->old_contents
.m
;
3814 /* Temporarily revert mode back. */
3815 adjust_reg_mode (reg
, old_mode
);
3817 if (reg
== i2dest
&& i2scratch
)
3819 /* If we used i2dest as a scratch register with a
3820 different mode, substitute it for the original
3821 i2src while its original mode is temporarily
3822 restored, and then clear i2scratch so that we don't
3823 do it again later. */
3824 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
3827 /* Put back the new mode. */
3828 adjust_reg_mode (reg
, new_mode
);
3832 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
3838 last
= last_combined_insn
;
3843 last
= undobuf
.other_insn
;
3845 if (DF_INSN_LUID (last
)
3846 < DF_INSN_LUID (last_combined_insn
))
3847 last
= last_combined_insn
;
3850 /* We're dealing with a reg that changed mode but not
3851 meaning, so we want to turn it into a subreg for
3852 the new mode. However, because of REG sharing and
3853 because its mode had already changed, we have to do
3854 it in two steps. First, replace any debug uses of
3855 reg, with its original mode temporarily restored,
3856 with this copy we have created; then, replace the
3857 copy with the SUBREG of the original shared reg,
3858 once again changed to the new mode. */
3859 propagate_for_debug (first
, last
, reg
, tempreg
,
3861 adjust_reg_mode (reg
, new_mode
);
3862 propagate_for_debug (first
, last
, tempreg
,
3863 lowpart_subreg (old_mode
, reg
, new_mode
),
3869 /* If we will be able to accept this, we have made a
3870 change to the destination of I3. This requires us to
3871 do a few adjustments. */
3873 if (changed_i3_dest
)
3875 PATTERN (i3
) = newpat
;
3876 adjust_for_new_dest (i3
);
3879 /* We now know that we can do this combination. Merge the insns and
3880 update the status of registers and LOG_LINKS. */
3882 if (undobuf
.other_insn
)
3886 PATTERN (undobuf
.other_insn
) = other_pat
;
3888 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3889 are still valid. Then add any non-duplicate notes added by
3890 recog_for_combine. */
3891 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
3893 next
= XEXP (note
, 1);
3895 if (REG_NOTE_KIND (note
) == REG_UNUSED
3896 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
3897 remove_note (undobuf
.other_insn
, note
);
3900 distribute_notes (new_other_notes
, undobuf
.other_insn
,
3901 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
3908 struct insn_link
*link
;
3911 /* I3 now uses what used to be its destination and which is now
3912 I2's destination. This requires us to do a few adjustments. */
3913 PATTERN (i3
) = newpat
;
3914 adjust_for_new_dest (i3
);
3916 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3919 However, some later insn might be using I2's dest and have
3920 a LOG_LINK pointing at I3. We must remove this link.
3921 The simplest way to remove the link is to point it at I1,
3922 which we know will be a NOTE. */
3924 /* newi2pat is usually a SET here; however, recog_for_combine might
3925 have added some clobbers. */
3926 if (GET_CODE (newi2pat
) == PARALLEL
)
3927 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
3929 ni2dest
= SET_DEST (newi2pat
);
3931 for (insn
= NEXT_INSN (i3
);
3932 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
3933 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
3934 insn
= NEXT_INSN (insn
))
3936 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
3938 FOR_EACH_LOG_LINK (link
, insn
)
3939 if (link
->insn
== i3
)
3948 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
3949 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
3952 /* Compute which registers we expect to eliminate. newi2pat may be setting
3953 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3954 same as i3dest, in which case newi2pat may be setting i1dest. */
3955 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
3956 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
3959 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
3960 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
3963 rtx elim_i0
= (i0
== 0 || i0dest_in_i0src
3964 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
3968 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3970 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
3971 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
3973 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
3975 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
3977 /* Ensure that we do not have something that should not be shared but
3978 occurs multiple times in the new insns. Check this by first
3979 resetting all the `used' flags and then copying anything is shared. */
3981 reset_used_flags (i3notes
);
3982 reset_used_flags (i2notes
);
3983 reset_used_flags (i1notes
);
3984 reset_used_flags (i0notes
);
3985 reset_used_flags (newpat
);
3986 reset_used_flags (newi2pat
);
3987 if (undobuf
.other_insn
)
3988 reset_used_flags (PATTERN (undobuf
.other_insn
));
3990 i3notes
= copy_rtx_if_shared (i3notes
);
3991 i2notes
= copy_rtx_if_shared (i2notes
);
3992 i1notes
= copy_rtx_if_shared (i1notes
);
3993 i0notes
= copy_rtx_if_shared (i0notes
);
3994 newpat
= copy_rtx_if_shared (newpat
);
3995 newi2pat
= copy_rtx_if_shared (newi2pat
);
3996 if (undobuf
.other_insn
)
3997 reset_used_flags (PATTERN (undobuf
.other_insn
));
3999 INSN_CODE (i3
) = insn_code_number
;
4000 PATTERN (i3
) = newpat
;
4002 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4004 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4006 reset_used_flags (call_usage
);
4007 call_usage
= copy_rtx (call_usage
);
4011 /* I2SRC must still be meaningful at this point. Some splitting
4012 operations can invalidate I2SRC, but those operations do not
4015 replace_rtx (call_usage
, i2dest
, i2src
);
4019 replace_rtx (call_usage
, i1dest
, i1src
);
4021 replace_rtx (call_usage
, i0dest
, i0src
);
4023 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4026 if (undobuf
.other_insn
)
4027 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4029 /* We had one special case above where I2 had more than one set and
4030 we replaced a destination of one of those sets with the destination
4031 of I3. In that case, we have to update LOG_LINKS of insns later
4032 in this basic block. Note that this (expensive) case is rare.
4034 Also, in this case, we must pretend that all REG_NOTEs for I2
4035 actually came from I3, so that REG_UNUSED notes from I2 will be
4036 properly handled. */
4038 if (i3_subst_into_i2
)
4040 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4041 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4042 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4043 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4044 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4045 && ! find_reg_note (i2
, REG_UNUSED
,
4046 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4047 for (temp
= NEXT_INSN (i2
);
4048 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
4049 || BB_HEAD (this_basic_block
) != temp
);
4050 temp
= NEXT_INSN (temp
))
4051 if (temp
!= i3
&& INSN_P (temp
))
4052 FOR_EACH_LOG_LINK (link
, temp
)
4053 if (link
->insn
== i2
)
4059 while (XEXP (link
, 1))
4060 link
= XEXP (link
, 1);
4061 XEXP (link
, 1) = i2notes
;
4068 LOG_LINKS (i3
) = NULL
;
4070 LOG_LINKS (i2
) = NULL
;
4075 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4076 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4078 INSN_CODE (i2
) = i2_code_number
;
4079 PATTERN (i2
) = newi2pat
;
4083 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4084 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4086 SET_INSN_DELETED (i2
);
4091 LOG_LINKS (i1
) = NULL
;
4093 if (MAY_HAVE_DEBUG_INSNS
)
4094 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4096 SET_INSN_DELETED (i1
);
4101 LOG_LINKS (i0
) = NULL
;
4103 if (MAY_HAVE_DEBUG_INSNS
)
4104 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4106 SET_INSN_DELETED (i0
);
4109 /* Get death notes for everything that is now used in either I3 or
4110 I2 and used to die in a previous insn. If we built two new
4111 patterns, move from I1 to I2 then I2 to I3 so that we get the
4112 proper movement on registers that I2 modifies. */
4115 from_luid
= DF_INSN_LUID (i0
);
4117 from_luid
= DF_INSN_LUID (i1
);
4119 from_luid
= DF_INSN_LUID (i2
);
4121 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4122 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4124 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4126 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
4127 elim_i2
, elim_i1
, elim_i0
);
4129 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
4130 elim_i2
, elim_i1
, elim_i0
);
4132 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
4133 elim_i2
, elim_i1
, elim_i0
);
4135 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL_RTX
,
4136 elim_i2
, elim_i1
, elim_i0
);
4138 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4139 elim_i2
, elim_i1
, elim_i0
);
4141 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4142 know these are REG_UNUSED and want them to go to the desired insn,
4143 so we always pass it as i3. */
4145 if (newi2pat
&& new_i2_notes
)
4146 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4150 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
,
4153 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4154 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4155 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4156 in that case, it might delete I2. Similarly for I2 and I1.
4157 Show an additional death due to the REG_DEAD note we make here. If
4158 we discard it in distribute_notes, we will decrement it again. */
4162 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4163 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4164 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, elim_i2
,
4167 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4168 elim_i2
, elim_i1
, elim_i0
);
4171 if (i2dest_in_i2src
)
4173 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4174 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4175 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4176 NULL_RTX
, NULL_RTX
);
4178 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4179 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4182 if (i1dest_in_i1src
)
4184 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4185 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4186 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4187 NULL_RTX
, NULL_RTX
);
4189 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4190 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4193 if (i0dest_in_i0src
)
4195 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4196 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4197 distribute_notes (new_note
, NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
,
4198 NULL_RTX
, NULL_RTX
);
4200 distribute_notes (new_note
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
4201 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4204 distribute_links (i3links
);
4205 distribute_links (i2links
);
4206 distribute_links (i1links
);
4207 distribute_links (i0links
);
4211 struct insn_link
*link
;
4212 rtx i2_insn
= 0, i2_val
= 0, set
;
4214 /* The insn that used to set this register doesn't exist, and
4215 this life of the register may not exist either. See if one of
4216 I3's links points to an insn that sets I2DEST. If it does,
4217 that is now the last known value for I2DEST. If we don't update
4218 this and I2 set the register to a value that depended on its old
4219 contents, we will get confused. If this insn is used, thing
4220 will be set correctly in combine_instructions. */
4221 FOR_EACH_LOG_LINK (link
, i3
)
4222 if ((set
= single_set (link
->insn
)) != 0
4223 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4224 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4226 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4228 /* If the reg formerly set in I2 died only once and that was in I3,
4229 zero its use count so it won't make `reload' do any work. */
4231 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4232 && ! i2dest_in_i2src
)
4233 INC_REG_N_SETS (REGNO (i2dest
), -1);
4236 if (i1
&& REG_P (i1dest
))
4238 struct insn_link
*link
;
4239 rtx i1_insn
= 0, i1_val
= 0, set
;
4241 FOR_EACH_LOG_LINK (link
, i3
)
4242 if ((set
= single_set (link
->insn
)) != 0
4243 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4244 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4246 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4248 if (! added_sets_1
&& ! i1dest_in_i1src
)
4249 INC_REG_N_SETS (REGNO (i1dest
), -1);
4252 if (i0
&& REG_P (i0dest
))
4254 struct insn_link
*link
;
4255 rtx i0_insn
= 0, i0_val
= 0, set
;
4257 FOR_EACH_LOG_LINK (link
, i3
)
4258 if ((set
= single_set (link
->insn
)) != 0
4259 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4260 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4262 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4264 if (! added_sets_0
&& ! i0dest_in_i0src
)
4265 INC_REG_N_SETS (REGNO (i0dest
), -1);
4268 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4269 been made to this insn. The order of
4270 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4271 can affect nonzero_bits of newpat */
4273 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4274 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4277 if (undobuf
.other_insn
!= NULL_RTX
)
4281 fprintf (dump_file
, "modifying other_insn ");
4282 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4284 df_insn_rescan (undobuf
.other_insn
);
4287 if (i0
&& !(NOTE_P(i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4291 fprintf (dump_file
, "modifying insn i1 ");
4292 dump_insn_slim (dump_file
, i0
);
4294 df_insn_rescan (i0
);
4297 if (i1
&& !(NOTE_P(i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4301 fprintf (dump_file
, "modifying insn i1 ");
4302 dump_insn_slim (dump_file
, i1
);
4304 df_insn_rescan (i1
);
4307 if (i2
&& !(NOTE_P(i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4311 fprintf (dump_file
, "modifying insn i2 ");
4312 dump_insn_slim (dump_file
, i2
);
4314 df_insn_rescan (i2
);
4317 if (i3
&& !(NOTE_P(i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4321 fprintf (dump_file
, "modifying insn i3 ");
4322 dump_insn_slim (dump_file
, i3
);
4324 df_insn_rescan (i3
);
4327 /* Set new_direct_jump_p if a new return or simple jump instruction
4328 has been created. Adjust the CFG accordingly. */
4330 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4332 *new_direct_jump_p
= 1;
4333 mark_jump_label (PATTERN (i3
), i3
, 0);
4334 update_cfg_for_uncondjump (i3
);
4337 if (undobuf
.other_insn
!= NULL_RTX
4338 && (returnjump_p (undobuf
.other_insn
)
4339 || any_uncondjump_p (undobuf
.other_insn
)))
4341 *new_direct_jump_p
= 1;
4342 update_cfg_for_uncondjump (undobuf
.other_insn
);
4345 /* A noop might also need cleaning up of CFG, if it comes from the
4346 simplification of a jump. */
4348 && GET_CODE (newpat
) == SET
4349 && SET_SRC (newpat
) == pc_rtx
4350 && SET_DEST (newpat
) == pc_rtx
)
4352 *new_direct_jump_p
= 1;
4353 update_cfg_for_uncondjump (i3
);
4356 if (undobuf
.other_insn
!= NULL_RTX
4357 && JUMP_P (undobuf
.other_insn
)
4358 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4359 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4360 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4362 *new_direct_jump_p
= 1;
4363 update_cfg_for_uncondjump (undobuf
.other_insn
);
4366 combine_successes
++;
4369 if (added_links_insn
4370 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4371 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4372 return added_links_insn
;
4374 return newi2pat
? i2
: i3
;
4377 /* Undo all the modifications recorded in undobuf. */
4382 struct undo
*undo
, *next
;
4384 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4390 *undo
->where
.r
= undo
->old_contents
.r
;
4393 *undo
->where
.i
= undo
->old_contents
.i
;
4396 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4399 *undo
->where
.l
= undo
->old_contents
.l
;
4405 undo
->next
= undobuf
.frees
;
4406 undobuf
.frees
= undo
;
4412 /* We've committed to accepting the changes we made. Move all
4413 of the undos to the free list. */
4418 struct undo
*undo
, *next
;
4420 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4423 undo
->next
= undobuf
.frees
;
4424 undobuf
.frees
= undo
;
4429 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4430 where we have an arithmetic expression and return that point. LOC will
4433 try_combine will call this function to see if an insn can be split into
4437 find_split_point (rtx
*loc
, rtx insn
, bool set_src
)
4440 enum rtx_code code
= GET_CODE (x
);
4442 unsigned HOST_WIDE_INT len
= 0;
4443 HOST_WIDE_INT pos
= 0;
4445 rtx inner
= NULL_RTX
;
4447 /* First special-case some codes. */
4451 #ifdef INSN_SCHEDULING
4452 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4454 if (MEM_P (SUBREG_REG (x
)))
4457 return find_split_point (&SUBREG_REG (x
), insn
, false);
4461 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4462 using LO_SUM and HIGH. */
4463 if (GET_CODE (XEXP (x
, 0)) == CONST
4464 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
4466 enum machine_mode address_mode
= get_address_mode (x
);
4469 gen_rtx_LO_SUM (address_mode
,
4470 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4472 return &XEXP (XEXP (x
, 0), 0);
4476 /* If we have a PLUS whose second operand is a constant and the
4477 address is not valid, perhaps will can split it up using
4478 the machine-specific way to split large constants. We use
4479 the first pseudo-reg (one of the virtual regs) as a placeholder;
4480 it will not remain in the result. */
4481 if (GET_CODE (XEXP (x
, 0)) == PLUS
4482 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4483 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4484 MEM_ADDR_SPACE (x
)))
4486 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4487 rtx seq
= combine_split_insns (gen_rtx_SET (VOIDmode
, reg
,
4491 /* This should have produced two insns, each of which sets our
4492 placeholder. If the source of the second is a valid address,
4493 we can make put both sources together and make a split point
4497 && NEXT_INSN (seq
) != NULL_RTX
4498 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4499 && NONJUMP_INSN_P (seq
)
4500 && GET_CODE (PATTERN (seq
)) == SET
4501 && SET_DEST (PATTERN (seq
)) == reg
4502 && ! reg_mentioned_p (reg
,
4503 SET_SRC (PATTERN (seq
)))
4504 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4505 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4506 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4507 && memory_address_addr_space_p
4508 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4509 MEM_ADDR_SPACE (x
)))
4511 rtx src1
= SET_SRC (PATTERN (seq
));
4512 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4514 /* Replace the placeholder in SRC2 with SRC1. If we can
4515 find where in SRC2 it was placed, that can become our
4516 split point and we can replace this address with SRC2.
4517 Just try two obvious places. */
4519 src2
= replace_rtx (src2
, reg
, src1
);
4521 if (XEXP (src2
, 0) == src1
)
4522 split
= &XEXP (src2
, 0);
4523 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4524 && XEXP (XEXP (src2
, 0), 0) == src1
)
4525 split
= &XEXP (XEXP (src2
, 0), 0);
4529 SUBST (XEXP (x
, 0), src2
);
4534 /* If that didn't work, perhaps the first operand is complex and
4535 needs to be computed separately, so make a split point there.
4536 This will occur on machines that just support REG + CONST
4537 and have a constant moved through some previous computation. */
4539 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4540 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4541 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4542 return &XEXP (XEXP (x
, 0), 0);
4545 /* If we have a PLUS whose first operand is complex, try computing it
4546 separately by making a split there. */
4547 if (GET_CODE (XEXP (x
, 0)) == PLUS
4548 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4550 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4551 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4552 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4553 return &XEXP (XEXP (x
, 0), 0);
4558 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4559 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4560 we need to put the operand into a register. So split at that
4563 if (SET_DEST (x
) == cc0_rtx
4564 && GET_CODE (SET_SRC (x
)) != COMPARE
4565 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4566 && !OBJECT_P (SET_SRC (x
))
4567 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4568 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4569 return &SET_SRC (x
);
4572 /* See if we can split SET_SRC as it stands. */
4573 split
= find_split_point (&SET_SRC (x
), insn
, true);
4574 if (split
&& split
!= &SET_SRC (x
))
4577 /* See if we can split SET_DEST as it stands. */
4578 split
= find_split_point (&SET_DEST (x
), insn
, false);
4579 if (split
&& split
!= &SET_DEST (x
))
4582 /* See if this is a bitfield assignment with everything constant. If
4583 so, this is an IOR of an AND, so split it into that. */
4584 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4585 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4586 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4587 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4588 && CONST_INT_P (SET_SRC (x
))
4589 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4590 + INTVAL (XEXP (SET_DEST (x
), 2)))
4591 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4592 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4594 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4595 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4596 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4597 rtx dest
= XEXP (SET_DEST (x
), 0);
4598 enum machine_mode mode
= GET_MODE (dest
);
4599 unsigned HOST_WIDE_INT mask
4600 = ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
4603 if (BITS_BIG_ENDIAN
)
4604 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4606 or_mask
= gen_int_mode (src
<< pos
, mode
);
4609 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4612 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4614 simplify_gen_binary (IOR
, mode
,
4615 simplify_gen_binary (AND
, mode
,
4620 SUBST (SET_DEST (x
), dest
);
4622 split
= find_split_point (&SET_SRC (x
), insn
, true);
4623 if (split
&& split
!= &SET_SRC (x
))
4627 /* Otherwise, see if this is an operation that we can split into two.
4628 If so, try to split that. */
4629 code
= GET_CODE (SET_SRC (x
));
4634 /* If we are AND'ing with a large constant that is only a single
4635 bit and the result is only being used in a context where we
4636 need to know if it is zero or nonzero, replace it with a bit
4637 extraction. This will avoid the large constant, which might
4638 have taken more than one insn to make. If the constant were
4639 not a valid argument to the AND but took only one insn to make,
4640 this is no worse, but if it took more than one insn, it will
4643 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4644 && REG_P (XEXP (SET_SRC (x
), 0))
4645 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4646 && REG_P (SET_DEST (x
))
4647 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
4648 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4649 && XEXP (*split
, 0) == SET_DEST (x
)
4650 && XEXP (*split
, 1) == const0_rtx
)
4652 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4653 XEXP (SET_SRC (x
), 0),
4654 pos
, NULL_RTX
, 1, 1, 0, 0);
4655 if (extraction
!= 0)
4657 SUBST (SET_SRC (x
), extraction
);
4658 return find_split_point (loc
, insn
, false);
4664 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4665 is known to be on, this can be converted into a NEG of a shift. */
4666 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4667 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4668 && 1 <= (pos
= exact_log2
4669 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4670 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4672 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4676 gen_rtx_LSHIFTRT (mode
,
4677 XEXP (SET_SRC (x
), 0),
4680 split
= find_split_point (&SET_SRC (x
), insn
, true);
4681 if (split
&& split
!= &SET_SRC (x
))
4687 inner
= XEXP (SET_SRC (x
), 0);
4689 /* We can't optimize if either mode is a partial integer
4690 mode as we don't know how many bits are significant
4692 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4693 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4697 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4703 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4704 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4706 inner
= XEXP (SET_SRC (x
), 0);
4707 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4708 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4710 if (BITS_BIG_ENDIAN
)
4711 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4712 unsignedp
= (code
== ZERO_EXTRACT
);
4721 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
4723 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
4725 /* For unsigned, we have a choice of a shift followed by an
4726 AND or two shifts. Use two shifts for field sizes where the
4727 constant might be too large. We assume here that we can
4728 always at least get 8-bit constants in an AND insn, which is
4729 true for every current RISC. */
4731 if (unsignedp
&& len
<= 8)
4736 (mode
, gen_lowpart (mode
, inner
),
4738 GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
)
4741 split
= find_split_point (&SET_SRC (x
), insn
, true);
4742 if (split
&& split
!= &SET_SRC (x
))
4749 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
4750 gen_rtx_ASHIFT (mode
,
4751 gen_lowpart (mode
, inner
),
4752 GEN_INT (GET_MODE_PRECISION (mode
)
4754 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
4756 split
= find_split_point (&SET_SRC (x
), insn
, true);
4757 if (split
&& split
!= &SET_SRC (x
))
4762 /* See if this is a simple operation with a constant as the second
4763 operand. It might be that this constant is out of range and hence
4764 could be used as a split point. */
4765 if (BINARY_P (SET_SRC (x
))
4766 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
4767 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
4768 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
4769 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
4770 return &XEXP (SET_SRC (x
), 1);
4772 /* Finally, see if this is a simple operation with its first operand
4773 not in a register. The operation might require this operand in a
4774 register, so return it as a split point. We can always do this
4775 because if the first operand were another operation, we would have
4776 already found it as a split point. */
4777 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
4778 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
4779 return &XEXP (SET_SRC (x
), 0);
4785 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4786 it is better to write this as (not (ior A B)) so we can split it.
4787 Similarly for IOR. */
4788 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
4791 gen_rtx_NOT (GET_MODE (x
),
4792 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
4794 XEXP (XEXP (x
, 0), 0),
4795 XEXP (XEXP (x
, 1), 0))));
4796 return find_split_point (loc
, insn
, set_src
);
4799 /* Many RISC machines have a large set of logical insns. If the
4800 second operand is a NOT, put it first so we will try to split the
4801 other operand first. */
4802 if (GET_CODE (XEXP (x
, 1)) == NOT
)
4804 rtx tem
= XEXP (x
, 0);
4805 SUBST (XEXP (x
, 0), XEXP (x
, 1));
4806 SUBST (XEXP (x
, 1), tem
);
4812 /* Canonicalization can produce (minus A (mult B C)), where C is a
4813 constant. It may be better to try splitting (plus (mult B -C) A)
4814 instead if this isn't a multiply by a power of two. */
4815 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
4816 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4817 && exact_log2 (INTVAL (XEXP (XEXP (x
, 1), 1))) < 0)
4819 enum machine_mode mode
= GET_MODE (x
);
4820 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
4821 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
4822 SUBST (*loc
, gen_rtx_PLUS (mode
, gen_rtx_MULT (mode
,
4823 XEXP (XEXP (x
, 1), 0),
4824 GEN_INT (other_int
)),
4826 return find_split_point (loc
, insn
, set_src
);
4829 /* Split at a multiply-accumulate instruction. However if this is
4830 the SET_SRC, we likely do not have such an instruction and it's
4831 worthless to try this split. */
4832 if (!set_src
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4839 /* Otherwise, select our actions depending on our rtx class. */
4840 switch (GET_RTX_CLASS (code
))
4842 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4844 split
= find_split_point (&XEXP (x
, 2), insn
, false);
4847 /* ... fall through ... */
4849 case RTX_COMM_ARITH
:
4851 case RTX_COMM_COMPARE
:
4852 split
= find_split_point (&XEXP (x
, 1), insn
, false);
4855 /* ... fall through ... */
4857 /* Some machines have (and (shift ...) ...) insns. If X is not
4858 an AND, but XEXP (X, 0) is, use it as our split point. */
4859 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
4860 return &XEXP (x
, 0);
4862 split
= find_split_point (&XEXP (x
, 0), insn
, false);
4868 /* Otherwise, we don't have a split point. */
4873 /* Throughout X, replace FROM with TO, and return the result.
4874 The result is TO if X is FROM;
4875 otherwise the result is X, but its contents may have been modified.
4876 If they were modified, a record was made in undobuf so that
4877 undo_all will (among other things) return X to its original state.
4879 If the number of changes necessary is too much to record to undo,
4880 the excess changes are not made, so the result is invalid.
4881 The changes already made can still be undone.
4882 undobuf.num_undo is incremented for such changes, so by testing that
4883 the caller can tell whether the result is valid.
4885 `n_occurrences' is incremented each time FROM is replaced.
4887 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4889 IN_COND is nonzero if we are at the top level of a condition.
4891 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4892 by copying if `n_occurrences' is nonzero. */
4895 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
4897 enum rtx_code code
= GET_CODE (x
);
4898 enum machine_mode op0_mode
= VOIDmode
;
4903 /* Two expressions are equal if they are identical copies of a shared
4904 RTX or if they are both registers with the same register number
4907 #define COMBINE_RTX_EQUAL_P(X,Y) \
4909 || (REG_P (X) && REG_P (Y) \
4910 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4912 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
4915 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
4918 /* If X and FROM are the same register but different modes, they
4919 will not have been seen as equal above. However, the log links code
4920 will make a LOG_LINKS entry for that case. If we do nothing, we
4921 will try to rerecognize our original insn and, when it succeeds,
4922 we will delete the feeding insn, which is incorrect.
4924 So force this insn not to match in this (rare) case. */
4925 if (! in_dest
&& code
== REG
&& REG_P (from
)
4926 && reg_overlap_mentioned_p (x
, from
))
4927 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
4929 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4930 of which may contain things that can be combined. */
4931 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
4934 /* It is possible to have a subexpression appear twice in the insn.
4935 Suppose that FROM is a register that appears within TO.
4936 Then, after that subexpression has been scanned once by `subst',
4937 the second time it is scanned, TO may be found. If we were
4938 to scan TO here, we would find FROM within it and create a
4939 self-referent rtl structure which is completely wrong. */
4940 if (COMBINE_RTX_EQUAL_P (x
, to
))
4943 /* Parallel asm_operands need special attention because all of the
4944 inputs are shared across the arms. Furthermore, unsharing the
4945 rtl results in recognition failures. Failure to handle this case
4946 specially can result in circular rtl.
4948 Solve this by doing a normal pass across the first entry of the
4949 parallel, and only processing the SET_DESTs of the subsequent
4952 if (code
== PARALLEL
4953 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
4954 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
4956 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
4958 /* If this substitution failed, this whole thing fails. */
4959 if (GET_CODE (new_rtx
) == CLOBBER
4960 && XEXP (new_rtx
, 0) == const0_rtx
)
4963 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
4965 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
4967 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
4970 && GET_CODE (dest
) != CC0
4971 && GET_CODE (dest
) != PC
)
4973 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
4975 /* If this substitution failed, this whole thing fails. */
4976 if (GET_CODE (new_rtx
) == CLOBBER
4977 && XEXP (new_rtx
, 0) == const0_rtx
)
4980 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
4986 len
= GET_RTX_LENGTH (code
);
4987 fmt
= GET_RTX_FORMAT (code
);
4989 /* We don't need to process a SET_DEST that is a register, CC0,
4990 or PC, so set up to skip this common case. All other cases
4991 where we want to suppress replacing something inside a
4992 SET_SRC are handled via the IN_DEST operand. */
4994 && (REG_P (SET_DEST (x
))
4995 || GET_CODE (SET_DEST (x
)) == CC0
4996 || GET_CODE (SET_DEST (x
)) == PC
))
4999 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5002 op0_mode
= GET_MODE (XEXP (x
, 0));
5004 for (i
= 0; i
< len
; i
++)
5009 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5011 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5013 new_rtx
= (unique_copy
&& n_occurrences
5014 ? copy_rtx (to
) : to
);
5019 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5022 /* If this substitution failed, this whole thing
5024 if (GET_CODE (new_rtx
) == CLOBBER
5025 && XEXP (new_rtx
, 0) == const0_rtx
)
5029 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5032 else if (fmt
[i
] == 'e')
5034 /* If this is a register being set, ignore it. */
5035 new_rtx
= XEXP (x
, i
);
5038 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5040 || code
== STRICT_LOW_PART
))
5043 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5045 /* In general, don't install a subreg involving two
5046 modes not tieable. It can worsen register
5047 allocation, and can even make invalid reload
5048 insns, since the reg inside may need to be copied
5049 from in the outside mode, and that may be invalid
5050 if it is an fp reg copied in integer mode.
5052 We allow two exceptions to this: It is valid if
5053 it is inside another SUBREG and the mode of that
5054 SUBREG and the mode of the inside of TO is
5055 tieable and it is valid if X is a SET that copies
5058 if (GET_CODE (to
) == SUBREG
5059 && ! MODES_TIEABLE_P (GET_MODE (to
),
5060 GET_MODE (SUBREG_REG (to
)))
5061 && ! (code
== SUBREG
5062 && MODES_TIEABLE_P (GET_MODE (x
),
5063 GET_MODE (SUBREG_REG (to
))))
5065 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
5068 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5070 #ifdef CANNOT_CHANGE_MODE_CLASS
5073 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5074 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
5077 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5080 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5084 /* If we are in a SET_DEST, suppress most cases unless we
5085 have gone inside a MEM, in which case we want to
5086 simplify the address. We assume here that things that
5087 are actually part of the destination have their inner
5088 parts in the first expression. This is true for SUBREG,
5089 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5090 things aside from REG and MEM that should appear in a
5092 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5094 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5095 || code
== ZERO_EXTRACT
))
5098 code
== IF_THEN_ELSE
&& i
== 0,
5101 /* If we found that we will have to reject this combination,
5102 indicate that by returning the CLOBBER ourselves, rather than
5103 an expression containing it. This will speed things up as
5104 well as prevent accidents where two CLOBBERs are considered
5105 to be equal, thus producing an incorrect simplification. */
5107 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5110 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5112 enum machine_mode mode
= GET_MODE (x
);
5114 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5115 GET_MODE (SUBREG_REG (x
)),
5118 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5120 else if (CONST_INT_P (new_rtx
)
5121 && GET_CODE (x
) == ZERO_EXTEND
)
5123 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5124 new_rtx
, GET_MODE (XEXP (x
, 0)));
5128 SUBST (XEXP (x
, i
), new_rtx
);
5133 /* Check if we are loading something from the constant pool via float
5134 extension; in this case we would undo compress_float_constant
5135 optimization and degenerate constant load to an immediate value. */
5136 if (GET_CODE (x
) == FLOAT_EXTEND
5137 && MEM_P (XEXP (x
, 0))
5138 && MEM_READONLY_P (XEXP (x
, 0)))
5140 rtx tmp
= avoid_constant_pool_reference (x
);
5145 /* Try to simplify X. If the simplification changed the code, it is likely
5146 that further simplification will help, so loop, but limit the number
5147 of repetitions that will be performed. */
5149 for (i
= 0; i
< 4; i
++)
5151 /* If X is sufficiently simple, don't bother trying to do anything
5153 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5154 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5156 if (GET_CODE (x
) == code
)
5159 code
= GET_CODE (x
);
5161 /* We no longer know the original mode of operand 0 since we
5162 have changed the form of X) */
5163 op0_mode
= VOIDmode
;
5169 /* Simplify X, a piece of RTL. We just operate on the expression at the
5170 outer level; call `subst' to simplify recursively. Return the new
5173 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5174 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5178 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int in_dest
,
5181 enum rtx_code code
= GET_CODE (x
);
5182 enum machine_mode mode
= GET_MODE (x
);
5186 /* If this is a commutative operation, put a constant last and a complex
5187 expression first. We don't need to do this for comparisons here. */
5188 if (COMMUTATIVE_ARITH_P (x
)
5189 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5192 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5193 SUBST (XEXP (x
, 1), temp
);
5196 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5197 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5198 things. Check for cases where both arms are testing the same
5201 Don't do anything if all operands are very simple. */
5204 && ((!OBJECT_P (XEXP (x
, 0))
5205 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5206 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5207 || (!OBJECT_P (XEXP (x
, 1))
5208 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5209 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5211 && (!OBJECT_P (XEXP (x
, 0))
5212 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5213 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5215 rtx cond
, true_rtx
, false_rtx
;
5217 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5219 /* If everything is a comparison, what we have is highly unlikely
5220 to be simpler, so don't use it. */
5221 && ! (COMPARISON_P (x
)
5222 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5224 rtx cop1
= const0_rtx
;
5225 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5227 if (cond_code
== NE
&& COMPARISON_P (cond
))
5230 /* Simplify the alternative arms; this may collapse the true and
5231 false arms to store-flag values. Be careful to use copy_rtx
5232 here since true_rtx or false_rtx might share RTL with x as a
5233 result of the if_then_else_cond call above. */
5234 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5235 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5237 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5238 is unlikely to be simpler. */
5239 if (general_operand (true_rtx
, VOIDmode
)
5240 && general_operand (false_rtx
, VOIDmode
))
5242 enum rtx_code reversed
;
5244 /* Restarting if we generate a store-flag expression will cause
5245 us to loop. Just drop through in this case. */
5247 /* If the result values are STORE_FLAG_VALUE and zero, we can
5248 just make the comparison operation. */
5249 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5250 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5252 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5253 && ((reversed
= reversed_comparison_code_parts
5254 (cond_code
, cond
, cop1
, NULL
))
5256 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5259 /* Likewise, we can make the negate of a comparison operation
5260 if the result values are - STORE_FLAG_VALUE and zero. */
5261 else if (CONST_INT_P (true_rtx
)
5262 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5263 && false_rtx
== const0_rtx
)
5264 x
= simplify_gen_unary (NEG
, mode
,
5265 simplify_gen_relational (cond_code
,
5269 else if (CONST_INT_P (false_rtx
)
5270 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5271 && true_rtx
== const0_rtx
5272 && ((reversed
= reversed_comparison_code_parts
5273 (cond_code
, cond
, cop1
, NULL
))
5275 x
= simplify_gen_unary (NEG
, mode
,
5276 simplify_gen_relational (reversed
,
5281 return gen_rtx_IF_THEN_ELSE (mode
,
5282 simplify_gen_relational (cond_code
,
5287 true_rtx
, false_rtx
);
5289 code
= GET_CODE (x
);
5290 op0_mode
= VOIDmode
;
5295 /* Try to fold this expression in case we have constants that weren't
5298 switch (GET_RTX_CLASS (code
))
5301 if (op0_mode
== VOIDmode
)
5302 op0_mode
= GET_MODE (XEXP (x
, 0));
5303 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5306 case RTX_COMM_COMPARE
:
5308 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5309 if (cmp_mode
== VOIDmode
)
5311 cmp_mode
= GET_MODE (XEXP (x
, 1));
5312 if (cmp_mode
== VOIDmode
)
5313 cmp_mode
= op0_mode
;
5315 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5316 XEXP (x
, 0), XEXP (x
, 1));
5319 case RTX_COMM_ARITH
:
5321 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5323 case RTX_BITFIELD_OPS
:
5325 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5326 XEXP (x
, 1), XEXP (x
, 2));
5335 code
= GET_CODE (temp
);
5336 op0_mode
= VOIDmode
;
5337 mode
= GET_MODE (temp
);
5340 /* First see if we can apply the inverse distributive law. */
5341 if (code
== PLUS
|| code
== MINUS
5342 || code
== AND
|| code
== IOR
|| code
== XOR
)
5344 x
= apply_distributive_law (x
);
5345 code
= GET_CODE (x
);
5346 op0_mode
= VOIDmode
;
5349 /* If CODE is an associative operation not otherwise handled, see if we
5350 can associate some operands. This can win if they are constants or
5351 if they are logically related (i.e. (a & b) & a). */
5352 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5353 || code
== AND
|| code
== IOR
|| code
== XOR
5354 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5355 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5356 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5358 if (GET_CODE (XEXP (x
, 0)) == code
)
5360 rtx other
= XEXP (XEXP (x
, 0), 0);
5361 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5362 rtx inner_op1
= XEXP (x
, 1);
5365 /* Make sure we pass the constant operand if any as the second
5366 one if this is a commutative operation. */
5367 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5369 rtx tem
= inner_op0
;
5370 inner_op0
= inner_op1
;
5373 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5374 : code
== DIV
? MULT
5376 mode
, inner_op0
, inner_op1
);
5378 /* For commutative operations, try the other pair if that one
5380 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5382 other
= XEXP (XEXP (x
, 0), 1);
5383 inner
= simplify_binary_operation (code
, mode
,
5384 XEXP (XEXP (x
, 0), 0),
5389 return simplify_gen_binary (code
, mode
, other
, inner
);
5393 /* A little bit of algebraic simplification here. */
5397 /* Ensure that our address has any ASHIFTs converted to MULT in case
5398 address-recognizing predicates are called later. */
5399 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5400 SUBST (XEXP (x
, 0), temp
);
5404 if (op0_mode
== VOIDmode
)
5405 op0_mode
= GET_MODE (SUBREG_REG (x
));
5407 /* See if this can be moved to simplify_subreg. */
5408 if (CONSTANT_P (SUBREG_REG (x
))
5409 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5410 /* Don't call gen_lowpart if the inner mode
5411 is VOIDmode and we cannot simplify it, as SUBREG without
5412 inner mode is invalid. */
5413 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5414 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5415 return gen_lowpart (mode
, SUBREG_REG (x
));
5417 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5421 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5427 /* Don't change the mode of the MEM if that would change the meaning
5429 if (MEM_P (SUBREG_REG (x
))
5430 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5431 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5432 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5433 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5435 /* Note that we cannot do any narrowing for non-constants since
5436 we might have been counting on using the fact that some bits were
5437 zero. We now do this in the SET. */
5442 temp
= expand_compound_operation (XEXP (x
, 0));
5444 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5445 replaced by (lshiftrt X C). This will convert
5446 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5448 if (GET_CODE (temp
) == ASHIFTRT
5449 && CONST_INT_P (XEXP (temp
, 1))
5450 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5451 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5452 INTVAL (XEXP (temp
, 1)));
5454 /* If X has only a single bit that might be nonzero, say, bit I, convert
5455 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5456 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5457 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5458 or a SUBREG of one since we'd be making the expression more
5459 complex if it was just a register. */
5462 && ! (GET_CODE (temp
) == SUBREG
5463 && REG_P (SUBREG_REG (temp
)))
5464 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5466 rtx temp1
= simplify_shift_const
5467 (NULL_RTX
, ASHIFTRT
, mode
,
5468 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5469 GET_MODE_PRECISION (mode
) - 1 - i
),
5470 GET_MODE_PRECISION (mode
) - 1 - i
);
5472 /* If all we did was surround TEMP with the two shifts, we
5473 haven't improved anything, so don't use it. Otherwise,
5474 we are better off with TEMP1. */
5475 if (GET_CODE (temp1
) != ASHIFTRT
5476 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5477 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5483 /* We can't handle truncation to a partial integer mode here
5484 because we don't know the real bitsize of the partial
5486 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5489 if (HWI_COMPUTABLE_MODE_P (mode
))
5491 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5492 GET_MODE_MASK (mode
), 0));
5494 /* We can truncate a constant value and return it. */
5495 if (CONST_INT_P (XEXP (x
, 0)))
5496 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5498 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5499 whose value is a comparison can be replaced with a subreg if
5500 STORE_FLAG_VALUE permits. */
5501 if (HWI_COMPUTABLE_MODE_P (mode
)
5502 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5503 && (temp
= get_last_value (XEXP (x
, 0)))
5504 && COMPARISON_P (temp
))
5505 return gen_lowpart (mode
, XEXP (x
, 0));
5509 /* (const (const X)) can become (const X). Do it this way rather than
5510 returning the inner CONST since CONST can be shared with a
5512 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5513 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5518 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5519 can add in an offset. find_split_point will split this address up
5520 again if it doesn't match. */
5521 if (GET_CODE (XEXP (x
, 0)) == HIGH
5522 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5528 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5529 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5530 bit-field and can be replaced by either a sign_extend or a
5531 sign_extract. The `and' may be a zero_extend and the two
5532 <c>, -<c> constants may be reversed. */
5533 if (GET_CODE (XEXP (x
, 0)) == XOR
5534 && CONST_INT_P (XEXP (x
, 1))
5535 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5536 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5537 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5538 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5539 && HWI_COMPUTABLE_MODE_P (mode
)
5540 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5541 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5542 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5543 == ((unsigned HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
5544 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5545 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5546 == (unsigned int) i
+ 1))))
5547 return simplify_shift_const
5548 (NULL_RTX
, ASHIFTRT
, mode
,
5549 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5550 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5551 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5552 GET_MODE_PRECISION (mode
) - (i
+ 1));
5554 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5555 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5556 the bitsize of the mode - 1. This allows simplification of
5557 "a = (b & 8) == 0;" */
5558 if (XEXP (x
, 1) == constm1_rtx
5559 && !REG_P (XEXP (x
, 0))
5560 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5561 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5562 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5563 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5564 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5565 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5566 GET_MODE_PRECISION (mode
) - 1),
5567 GET_MODE_PRECISION (mode
) - 1);
5569 /* If we are adding two things that have no bits in common, convert
5570 the addition into an IOR. This will often be further simplified,
5571 for example in cases like ((a & 1) + (a & 2)), which can
5574 if (HWI_COMPUTABLE_MODE_P (mode
)
5575 && (nonzero_bits (XEXP (x
, 0), mode
)
5576 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5578 /* Try to simplify the expression further. */
5579 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5580 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5582 /* If we could, great. If not, do not go ahead with the IOR
5583 replacement, since PLUS appears in many special purpose
5584 address arithmetic instructions. */
5585 if (GET_CODE (temp
) != CLOBBER
5586 && (GET_CODE (temp
) != IOR
5587 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5588 || XEXP (temp
, 1) != XEXP (x
, 1))
5589 && (XEXP (temp
, 0) != XEXP (x
, 1)
5590 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5596 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5597 (and <foo> (const_int pow2-1)) */
5598 if (GET_CODE (XEXP (x
, 1)) == AND
5599 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5600 && exact_log2 (-UINTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
5601 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5602 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5603 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5607 /* If we have (mult (plus A B) C), apply the distributive law and then
5608 the inverse distributive law to see if things simplify. This
5609 occurs mostly in addresses, often when unrolling loops. */
5611 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5613 rtx result
= distribute_and_simplify_rtx (x
, 0);
5618 /* Try simplify a*(b/c) as (a*b)/c. */
5619 if (FLOAT_MODE_P (mode
) && flag_associative_math
5620 && GET_CODE (XEXP (x
, 0)) == DIV
)
5622 rtx tem
= simplify_binary_operation (MULT
, mode
,
5623 XEXP (XEXP (x
, 0), 0),
5626 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5631 /* If this is a divide by a power of two, treat it as a shift if
5632 its first operand is a shift. */
5633 if (CONST_INT_P (XEXP (x
, 1))
5634 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5635 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5636 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5637 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5638 || GET_CODE (XEXP (x
, 0)) == ROTATE
5639 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5640 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5644 case GT
: case GTU
: case GE
: case GEU
:
5645 case LT
: case LTU
: case LE
: case LEU
:
5646 case UNEQ
: case LTGT
:
5647 case UNGT
: case UNGE
:
5648 case UNLT
: case UNLE
:
5649 case UNORDERED
: case ORDERED
:
5650 /* If the first operand is a condition code, we can't do anything
5652 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5653 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5654 && ! CC0_P (XEXP (x
, 0))))
5656 rtx op0
= XEXP (x
, 0);
5657 rtx op1
= XEXP (x
, 1);
5658 enum rtx_code new_code
;
5660 if (GET_CODE (op0
) == COMPARE
)
5661 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5663 /* Simplify our comparison, if possible. */
5664 new_code
= simplify_comparison (code
, &op0
, &op1
);
5666 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5667 if only the low-order bit is possibly nonzero in X (such as when
5668 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5669 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5670 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5673 Remove any ZERO_EXTRACT we made when thinking this was a
5674 comparison. It may now be simpler to use, e.g., an AND. If a
5675 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5676 the call to make_compound_operation in the SET case.
5678 Don't apply these optimizations if the caller would
5679 prefer a comparison rather than a value.
5680 E.g., for the condition in an IF_THEN_ELSE most targets need
5681 an explicit comparison. */
5686 else if (STORE_FLAG_VALUE
== 1
5687 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5688 && op1
== const0_rtx
5689 && mode
== GET_MODE (op0
)
5690 && nonzero_bits (op0
, mode
) == 1)
5691 return gen_lowpart (mode
,
5692 expand_compound_operation (op0
));
5694 else if (STORE_FLAG_VALUE
== 1
5695 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5696 && op1
== const0_rtx
5697 && mode
== GET_MODE (op0
)
5698 && (num_sign_bit_copies (op0
, mode
)
5699 == GET_MODE_PRECISION (mode
)))
5701 op0
= expand_compound_operation (op0
);
5702 return simplify_gen_unary (NEG
, mode
,
5703 gen_lowpart (mode
, op0
),
5707 else if (STORE_FLAG_VALUE
== 1
5708 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5709 && op1
== const0_rtx
5710 && mode
== GET_MODE (op0
)
5711 && nonzero_bits (op0
, mode
) == 1)
5713 op0
= expand_compound_operation (op0
);
5714 return simplify_gen_binary (XOR
, mode
,
5715 gen_lowpart (mode
, op0
),
5719 else if (STORE_FLAG_VALUE
== 1
5720 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5721 && op1
== const0_rtx
5722 && mode
== GET_MODE (op0
)
5723 && (num_sign_bit_copies (op0
, mode
)
5724 == GET_MODE_PRECISION (mode
)))
5726 op0
= expand_compound_operation (op0
);
5727 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
5730 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5735 else if (STORE_FLAG_VALUE
== -1
5736 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5737 && op1
== const0_rtx
5738 && (num_sign_bit_copies (op0
, mode
)
5739 == GET_MODE_PRECISION (mode
)))
5740 return gen_lowpart (mode
,
5741 expand_compound_operation (op0
));
5743 else if (STORE_FLAG_VALUE
== -1
5744 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5745 && op1
== const0_rtx
5746 && mode
== GET_MODE (op0
)
5747 && nonzero_bits (op0
, mode
) == 1)
5749 op0
= expand_compound_operation (op0
);
5750 return simplify_gen_unary (NEG
, mode
,
5751 gen_lowpart (mode
, op0
),
5755 else if (STORE_FLAG_VALUE
== -1
5756 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5757 && op1
== const0_rtx
5758 && mode
== GET_MODE (op0
)
5759 && (num_sign_bit_copies (op0
, mode
)
5760 == GET_MODE_PRECISION (mode
)))
5762 op0
= expand_compound_operation (op0
);
5763 return simplify_gen_unary (NOT
, mode
,
5764 gen_lowpart (mode
, op0
),
5768 /* If X is 0/1, (eq X 0) is X-1. */
5769 else if (STORE_FLAG_VALUE
== -1
5770 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
5771 && op1
== const0_rtx
5772 && mode
== GET_MODE (op0
)
5773 && nonzero_bits (op0
, mode
) == 1)
5775 op0
= expand_compound_operation (op0
);
5776 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
5779 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5780 one bit that might be nonzero, we can convert (ne x 0) to
5781 (ashift x c) where C puts the bit in the sign bit. Remove any
5782 AND with STORE_FLAG_VALUE when we are done, since we are only
5783 going to test the sign bit. */
5784 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
5785 && HWI_COMPUTABLE_MODE_P (mode
)
5786 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
5787 && op1
== const0_rtx
5788 && mode
== GET_MODE (op0
)
5789 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
5791 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5792 expand_compound_operation (op0
),
5793 GET_MODE_PRECISION (mode
) - 1 - i
);
5794 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
5800 /* If the code changed, return a whole new comparison. */
5801 if (new_code
!= code
)
5802 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
5804 /* Otherwise, keep this operation, but maybe change its operands.
5805 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5806 SUBST (XEXP (x
, 0), op0
);
5807 SUBST (XEXP (x
, 1), op1
);
5812 return simplify_if_then_else (x
);
5818 /* If we are processing SET_DEST, we are done. */
5822 return expand_compound_operation (x
);
5825 return simplify_set (x
);
5829 return simplify_logical (x
);
5836 /* If this is a shift by a constant amount, simplify it. */
5837 if (CONST_INT_P (XEXP (x
, 1)))
5838 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
5839 INTVAL (XEXP (x
, 1)));
5841 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
5843 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
5844 ((unsigned HOST_WIDE_INT
) 1
5845 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
5857 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5860 simplify_if_then_else (rtx x
)
5862 enum machine_mode mode
= GET_MODE (x
);
5863 rtx cond
= XEXP (x
, 0);
5864 rtx true_rtx
= XEXP (x
, 1);
5865 rtx false_rtx
= XEXP (x
, 2);
5866 enum rtx_code true_code
= GET_CODE (cond
);
5867 int comparison_p
= COMPARISON_P (cond
);
5870 enum rtx_code false_code
;
5873 /* Simplify storing of the truth value. */
5874 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5875 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
5876 XEXP (cond
, 0), XEXP (cond
, 1));
5878 /* Also when the truth value has to be reversed. */
5880 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5881 && (reversed
= reversed_comparison (cond
, mode
)))
5884 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5885 in it is being compared against certain values. Get the true and false
5886 comparisons and see if that says anything about the value of each arm. */
5889 && ((false_code
= reversed_comparison_code (cond
, NULL
))
5891 && REG_P (XEXP (cond
, 0)))
5894 rtx from
= XEXP (cond
, 0);
5895 rtx true_val
= XEXP (cond
, 1);
5896 rtx false_val
= true_val
;
5899 /* If FALSE_CODE is EQ, swap the codes and arms. */
5901 if (false_code
== EQ
)
5903 swapped
= 1, true_code
= EQ
, false_code
= NE
;
5904 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5907 /* If we are comparing against zero and the expression being tested has
5908 only a single bit that might be nonzero, that is its value when it is
5909 not equal to zero. Similarly if it is known to be -1 or 0. */
5911 if (true_code
== EQ
&& true_val
== const0_rtx
5912 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
5915 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
5917 else if (true_code
== EQ
&& true_val
== const0_rtx
5918 && (num_sign_bit_copies (from
, GET_MODE (from
))
5919 == GET_MODE_PRECISION (GET_MODE (from
))))
5922 false_val
= constm1_rtx
;
5925 /* Now simplify an arm if we know the value of the register in the
5926 branch and it is used in the arm. Be careful due to the potential
5927 of locally-shared RTL. */
5929 if (reg_mentioned_p (from
, true_rtx
))
5930 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
5932 pc_rtx
, pc_rtx
, 0, 0, 0);
5933 if (reg_mentioned_p (from
, false_rtx
))
5934 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
5936 pc_rtx
, pc_rtx
, 0, 0, 0);
5938 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
5939 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
5941 true_rtx
= XEXP (x
, 1);
5942 false_rtx
= XEXP (x
, 2);
5943 true_code
= GET_CODE (cond
);
5946 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5947 reversed, do so to avoid needing two sets of patterns for
5948 subtract-and-branch insns. Similarly if we have a constant in the true
5949 arm, the false arm is the same as the first operand of the comparison, or
5950 the false arm is more complicated than the true arm. */
5953 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
5954 && (true_rtx
== pc_rtx
5955 || (CONSTANT_P (true_rtx
)
5956 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
5957 || true_rtx
== const0_rtx
5958 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
5959 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
5960 && !OBJECT_P (false_rtx
))
5961 || reg_mentioned_p (true_rtx
, false_rtx
)
5962 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
5964 true_code
= reversed_comparison_code (cond
, NULL
);
5965 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
5966 SUBST (XEXP (x
, 1), false_rtx
);
5967 SUBST (XEXP (x
, 2), true_rtx
);
5969 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
5972 /* It is possible that the conditional has been simplified out. */
5973 true_code
= GET_CODE (cond
);
5974 comparison_p
= COMPARISON_P (cond
);
5977 /* If the two arms are identical, we don't need the comparison. */
5979 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
5982 /* Convert a == b ? b : a to "a". */
5983 if (true_code
== EQ
&& ! side_effects_p (cond
)
5984 && !HONOR_NANS (mode
)
5985 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
5986 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
5988 else if (true_code
== NE
&& ! side_effects_p (cond
)
5989 && !HONOR_NANS (mode
)
5990 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
5991 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
5994 /* Look for cases where we have (abs x) or (neg (abs X)). */
5996 if (GET_MODE_CLASS (mode
) == MODE_INT
5998 && XEXP (cond
, 1) == const0_rtx
5999 && GET_CODE (false_rtx
) == NEG
6000 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6001 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6002 && ! side_effects_p (true_rtx
))
6007 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6011 simplify_gen_unary (NEG
, mode
,
6012 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6018 /* Look for MIN or MAX. */
6020 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6022 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6023 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6024 && ! side_effects_p (cond
))
6029 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6032 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6035 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6038 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6043 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6044 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6045 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6046 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6047 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6048 neither 1 or -1, but it isn't worth checking for. */
6050 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6052 && GET_MODE_CLASS (mode
) == MODE_INT
6053 && ! side_effects_p (x
))
6055 rtx t
= make_compound_operation (true_rtx
, SET
);
6056 rtx f
= make_compound_operation (false_rtx
, SET
);
6057 rtx cond_op0
= XEXP (cond
, 0);
6058 rtx cond_op1
= XEXP (cond
, 1);
6059 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6060 enum machine_mode m
= mode
;
6061 rtx z
= 0, c1
= NULL_RTX
;
6063 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6064 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6065 || GET_CODE (t
) == ASHIFT
6066 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6067 && rtx_equal_p (XEXP (t
, 0), f
))
6068 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6070 /* If an identity-zero op is commutative, check whether there
6071 would be a match if we swapped the operands. */
6072 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6073 || GET_CODE (t
) == XOR
)
6074 && rtx_equal_p (XEXP (t
, 1), f
))
6075 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6076 else if (GET_CODE (t
) == SIGN_EXTEND
6077 && (GET_CODE (XEXP (t
, 0)) == PLUS
6078 || GET_CODE (XEXP (t
, 0)) == MINUS
6079 || GET_CODE (XEXP (t
, 0)) == IOR
6080 || GET_CODE (XEXP (t
, 0)) == XOR
6081 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6082 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6083 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6084 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6085 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6086 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6087 && (num_sign_bit_copies (f
, GET_MODE (f
))
6089 (GET_MODE_PRECISION (mode
)
6090 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6092 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6093 extend_op
= SIGN_EXTEND
;
6094 m
= GET_MODE (XEXP (t
, 0));
6096 else if (GET_CODE (t
) == SIGN_EXTEND
6097 && (GET_CODE (XEXP (t
, 0)) == PLUS
6098 || GET_CODE (XEXP (t
, 0)) == IOR
6099 || GET_CODE (XEXP (t
, 0)) == XOR
)
6100 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6101 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6102 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6103 && (num_sign_bit_copies (f
, GET_MODE (f
))
6105 (GET_MODE_PRECISION (mode
)
6106 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6108 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6109 extend_op
= SIGN_EXTEND
;
6110 m
= GET_MODE (XEXP (t
, 0));
6112 else if (GET_CODE (t
) == ZERO_EXTEND
6113 && (GET_CODE (XEXP (t
, 0)) == PLUS
6114 || GET_CODE (XEXP (t
, 0)) == MINUS
6115 || GET_CODE (XEXP (t
, 0)) == IOR
6116 || GET_CODE (XEXP (t
, 0)) == XOR
6117 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6118 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6119 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6120 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6121 && HWI_COMPUTABLE_MODE_P (mode
)
6122 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6123 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6124 && ((nonzero_bits (f
, GET_MODE (f
))
6125 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6128 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6129 extend_op
= ZERO_EXTEND
;
6130 m
= GET_MODE (XEXP (t
, 0));
6132 else if (GET_CODE (t
) == ZERO_EXTEND
6133 && (GET_CODE (XEXP (t
, 0)) == PLUS
6134 || GET_CODE (XEXP (t
, 0)) == IOR
6135 || GET_CODE (XEXP (t
, 0)) == XOR
)
6136 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6137 && HWI_COMPUTABLE_MODE_P (mode
)
6138 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6139 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6140 && ((nonzero_bits (f
, GET_MODE (f
))
6141 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6144 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6145 extend_op
= ZERO_EXTEND
;
6146 m
= GET_MODE (XEXP (t
, 0));
6151 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6152 cond_op0
, cond_op1
),
6153 pc_rtx
, pc_rtx
, 0, 0, 0);
6154 temp
= simplify_gen_binary (MULT
, m
, temp
,
6155 simplify_gen_binary (MULT
, m
, c1
,
6157 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6158 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6160 if (extend_op
!= UNKNOWN
)
6161 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6167 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6168 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6169 negation of a single bit, we can convert this operation to a shift. We
6170 can actually do this more generally, but it doesn't seem worth it. */
6172 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6173 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6174 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6175 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6176 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6177 == GET_MODE_PRECISION (mode
))
6178 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6180 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6181 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6183 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6184 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6185 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6186 && GET_MODE (XEXP (cond
, 0)) == mode
6187 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6188 == nonzero_bits (XEXP (cond
, 0), mode
)
6189 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6190 return XEXP (cond
, 0);
6195 /* Simplify X, a SET expression. Return the new expression. */
6198 simplify_set (rtx x
)
6200 rtx src
= SET_SRC (x
);
6201 rtx dest
= SET_DEST (x
);
6202 enum machine_mode mode
6203 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6207 /* (set (pc) (return)) gets written as (return). */
6208 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6211 /* Now that we know for sure which bits of SRC we are using, see if we can
6212 simplify the expression for the object knowing that we only need the
6215 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6217 src
= force_to_mode (src
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
6218 SUBST (SET_SRC (x
), src
);
6221 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6222 the comparison result and try to simplify it unless we already have used
6223 undobuf.other_insn. */
6224 if ((GET_MODE_CLASS (mode
) == MODE_CC
6225 || GET_CODE (src
) == COMPARE
6227 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6228 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6229 && COMPARISON_P (*cc_use
)
6230 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6232 enum rtx_code old_code
= GET_CODE (*cc_use
);
6233 enum rtx_code new_code
;
6235 int other_changed
= 0;
6236 rtx inner_compare
= NULL_RTX
;
6237 enum machine_mode compare_mode
= GET_MODE (dest
);
6239 if (GET_CODE (src
) == COMPARE
)
6241 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6242 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6244 inner_compare
= op0
;
6245 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6249 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6251 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6254 new_code
= old_code
;
6255 else if (!CONSTANT_P (tmp
))
6257 new_code
= GET_CODE (tmp
);
6258 op0
= XEXP (tmp
, 0);
6259 op1
= XEXP (tmp
, 1);
6263 rtx pat
= PATTERN (other_insn
);
6264 undobuf
.other_insn
= other_insn
;
6265 SUBST (*cc_use
, tmp
);
6267 /* Attempt to simplify CC user. */
6268 if (GET_CODE (pat
) == SET
)
6270 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6271 if (new_rtx
!= NULL_RTX
)
6272 SUBST (SET_SRC (pat
), new_rtx
);
6275 /* Convert X into a no-op move. */
6276 SUBST (SET_DEST (x
), pc_rtx
);
6277 SUBST (SET_SRC (x
), pc_rtx
);
6281 /* Simplify our comparison, if possible. */
6282 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6284 #ifdef SELECT_CC_MODE
6285 /* If this machine has CC modes other than CCmode, check to see if we
6286 need to use a different CC mode here. */
6287 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6288 compare_mode
= GET_MODE (op0
);
6289 else if (inner_compare
6290 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6291 && new_code
== old_code
6292 && op0
== XEXP (inner_compare
, 0)
6293 && op1
== XEXP (inner_compare
, 1))
6294 compare_mode
= GET_MODE (inner_compare
);
6296 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6299 /* If the mode changed, we have to change SET_DEST, the mode in the
6300 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6301 a hard register, just build new versions with the proper mode. If it
6302 is a pseudo, we lose unless it is only time we set the pseudo, in
6303 which case we can safely change its mode. */
6304 if (compare_mode
!= GET_MODE (dest
))
6306 if (can_change_dest_mode (dest
, 0, compare_mode
))
6308 unsigned int regno
= REGNO (dest
);
6311 if (regno
< FIRST_PSEUDO_REGISTER
)
6312 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6315 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6316 new_dest
= regno_reg_rtx
[regno
];
6319 SUBST (SET_DEST (x
), new_dest
);
6320 SUBST (XEXP (*cc_use
, 0), new_dest
);
6327 #endif /* SELECT_CC_MODE */
6329 /* If the code changed, we have to build a new comparison in
6330 undobuf.other_insn. */
6331 if (new_code
!= old_code
)
6333 int other_changed_previously
= other_changed
;
6334 unsigned HOST_WIDE_INT mask
;
6335 rtx old_cc_use
= *cc_use
;
6337 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6341 /* If the only change we made was to change an EQ into an NE or
6342 vice versa, OP0 has only one bit that might be nonzero, and OP1
6343 is zero, check if changing the user of the condition code will
6344 produce a valid insn. If it won't, we can keep the original code
6345 in that insn by surrounding our operation with an XOR. */
6347 if (((old_code
== NE
&& new_code
== EQ
)
6348 || (old_code
== EQ
&& new_code
== NE
))
6349 && ! other_changed_previously
&& op1
== const0_rtx
6350 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6351 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
6353 rtx pat
= PATTERN (other_insn
), note
= 0;
6355 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6356 && ! check_asm_operands (pat
)))
6358 *cc_use
= old_cc_use
;
6361 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
),
6362 op0
, GEN_INT (mask
));
6368 undobuf
.other_insn
= other_insn
;
6370 /* Otherwise, if we didn't previously have a COMPARE in the
6371 correct mode, we need one. */
6372 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
6374 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6377 else if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6379 SUBST (SET_SRC (x
), op0
);
6382 /* Otherwise, update the COMPARE if needed. */
6383 else if (XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6385 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6391 /* Get SET_SRC in a form where we have placed back any
6392 compound expressions. Then do the checks below. */
6393 src
= make_compound_operation (src
, SET
);
6394 SUBST (SET_SRC (x
), src
);
6397 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6398 and X being a REG or (subreg (reg)), we may be able to convert this to
6399 (set (subreg:m2 x) (op)).
6401 We can always do this if M1 is narrower than M2 because that means that
6402 we only care about the low bits of the result.
6404 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6405 perform a narrower operation than requested since the high-order bits will
6406 be undefined. On machine where it is defined, this transformation is safe
6407 as long as M1 and M2 have the same number of words. */
6409 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6410 && !OBJECT_P (SUBREG_REG (src
))
6411 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6413 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6414 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6415 #ifndef WORD_REGISTER_OPERATIONS
6416 && (GET_MODE_SIZE (GET_MODE (src
))
6417 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
6419 #ifdef CANNOT_CHANGE_MODE_CLASS
6420 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6421 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6422 GET_MODE (SUBREG_REG (src
)),
6426 || (GET_CODE (dest
) == SUBREG
6427 && REG_P (SUBREG_REG (dest
)))))
6429 SUBST (SET_DEST (x
),
6430 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6432 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6434 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6438 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6441 && GET_CODE (src
) == SUBREG
6442 && subreg_lowpart_p (src
)
6443 && (GET_MODE_PRECISION (GET_MODE (src
))
6444 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6446 rtx inner
= SUBREG_REG (src
);
6447 enum machine_mode inner_mode
= GET_MODE (inner
);
6449 /* Here we make sure that we don't have a sign bit on. */
6450 if (val_signbit_known_clear_p (GET_MODE (src
),
6451 nonzero_bits (inner
, inner_mode
)))
6453 SUBST (SET_SRC (x
), inner
);
6459 #ifdef LOAD_EXTEND_OP
6460 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6461 would require a paradoxical subreg. Replace the subreg with a
6462 zero_extend to avoid the reload that would otherwise be required. */
6464 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6465 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6466 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6467 && SUBREG_BYTE (src
) == 0
6468 && paradoxical_subreg_p (src
)
6469 && MEM_P (SUBREG_REG (src
)))
6472 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6473 GET_MODE (src
), SUBREG_REG (src
)));
6479 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6480 are comparing an item known to be 0 or -1 against 0, use a logical
6481 operation instead. Check for one of the arms being an IOR of the other
6482 arm with some value. We compute three terms to be IOR'ed together. In
6483 practice, at most two will be nonzero. Then we do the IOR's. */
6485 if (GET_CODE (dest
) != PC
6486 && GET_CODE (src
) == IF_THEN_ELSE
6487 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6488 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6489 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6490 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6491 #ifdef HAVE_conditional_move
6492 && ! can_conditionally_move_p (GET_MODE (src
))
6494 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6495 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6496 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6497 && ! side_effects_p (src
))
6499 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6500 ? XEXP (src
, 1) : XEXP (src
, 2));
6501 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6502 ? XEXP (src
, 2) : XEXP (src
, 1));
6503 rtx term1
= const0_rtx
, term2
, term3
;
6505 if (GET_CODE (true_rtx
) == IOR
6506 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6507 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6508 else if (GET_CODE (true_rtx
) == IOR
6509 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6510 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6511 else if (GET_CODE (false_rtx
) == IOR
6512 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6513 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6514 else if (GET_CODE (false_rtx
) == IOR
6515 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6516 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6518 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6519 XEXP (XEXP (src
, 0), 0), true_rtx
);
6520 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6521 simplify_gen_unary (NOT
, GET_MODE (src
),
6522 XEXP (XEXP (src
, 0), 0),
6527 simplify_gen_binary (IOR
, GET_MODE (src
),
6528 simplify_gen_binary (IOR
, GET_MODE (src
),
6535 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6536 whole thing fail. */
6537 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6539 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6542 /* Convert this into a field assignment operation, if possible. */
6543 return make_field_assignment (x
);
6546 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6550 simplify_logical (rtx x
)
6552 enum machine_mode mode
= GET_MODE (x
);
6553 rtx op0
= XEXP (x
, 0);
6554 rtx op1
= XEXP (x
, 1);
6556 switch (GET_CODE (x
))
6559 /* We can call simplify_and_const_int only if we don't lose
6560 any (sign) bits when converting INTVAL (op1) to
6561 "unsigned HOST_WIDE_INT". */
6562 if (CONST_INT_P (op1
)
6563 && (HWI_COMPUTABLE_MODE_P (mode
)
6564 || INTVAL (op1
) > 0))
6566 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6567 if (GET_CODE (x
) != AND
)
6574 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6575 apply the distributive law and then the inverse distributive
6576 law to see if things simplify. */
6577 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6579 rtx result
= distribute_and_simplify_rtx (x
, 0);
6583 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6585 rtx result
= distribute_and_simplify_rtx (x
, 1);
6592 /* If we have (ior (and A B) C), apply the distributive law and then
6593 the inverse distributive law to see if things simplify. */
6595 if (GET_CODE (op0
) == AND
)
6597 rtx result
= distribute_and_simplify_rtx (x
, 0);
6602 if (GET_CODE (op1
) == AND
)
6604 rtx result
= distribute_and_simplify_rtx (x
, 1);
6617 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6618 operations" because they can be replaced with two more basic operations.
6619 ZERO_EXTEND is also considered "compound" because it can be replaced with
6620 an AND operation, which is simpler, though only one operation.
6622 The function expand_compound_operation is called with an rtx expression
6623 and will convert it to the appropriate shifts and AND operations,
6624 simplifying at each stage.
6626 The function make_compound_operation is called to convert an expression
6627 consisting of shifts and ANDs into the equivalent compound expression.
6628 It is the inverse of this function, loosely speaking. */
6631 expand_compound_operation (rtx x
)
6633 unsigned HOST_WIDE_INT pos
= 0, len
;
6635 unsigned int modewidth
;
6638 switch (GET_CODE (x
))
6643 /* We can't necessarily use a const_int for a multiword mode;
6644 it depends on implicitly extending the value.
6645 Since we don't know the right way to extend it,
6646 we can't tell whether the implicit way is right.
6648 Even for a mode that is no wider than a const_int,
6649 we can't win, because we need to sign extend one of its bits through
6650 the rest of it, and we don't know which bit. */
6651 if (CONST_INT_P (XEXP (x
, 0)))
6654 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6655 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6656 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6657 reloaded. If not for that, MEM's would very rarely be safe.
6659 Reject MODEs bigger than a word, because we might not be able
6660 to reference a two-register group starting with an arbitrary register
6661 (and currently gen_lowpart might crash for a SUBREG). */
6663 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6666 /* Reject MODEs that aren't scalar integers because turning vector
6667 or complex modes into shifts causes problems. */
6669 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6672 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6673 /* If the inner object has VOIDmode (the only way this can happen
6674 is if it is an ASM_OPERANDS), we can't do anything since we don't
6675 know how much masking to do. */
6684 /* ... fall through ... */
6687 /* If the operand is a CLOBBER, just return it. */
6688 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
6691 if (!CONST_INT_P (XEXP (x
, 1))
6692 || !CONST_INT_P (XEXP (x
, 2))
6693 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
6696 /* Reject MODEs that aren't scalar integers because turning vector
6697 or complex modes into shifts causes problems. */
6699 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6702 len
= INTVAL (XEXP (x
, 1));
6703 pos
= INTVAL (XEXP (x
, 2));
6705 /* This should stay within the object being extracted, fail otherwise. */
6706 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
6709 if (BITS_BIG_ENDIAN
)
6710 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
6717 /* Convert sign extension to zero extension, if we know that the high
6718 bit is not set, as this is easier to optimize. It will be converted
6719 back to cheaper alternative in make_extraction. */
6720 if (GET_CODE (x
) == SIGN_EXTEND
6721 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6722 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6723 & ~(((unsigned HOST_WIDE_INT
)
6724 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
6728 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
6729 rtx temp2
= expand_compound_operation (temp
);
6731 /* Make sure this is a profitable operation. */
6732 if (set_src_cost (x
, optimize_this_for_speed_p
)
6733 > set_src_cost (temp2
, optimize_this_for_speed_p
))
6735 else if (set_src_cost (x
, optimize_this_for_speed_p
)
6736 > set_src_cost (temp
, optimize_this_for_speed_p
))
6742 /* We can optimize some special cases of ZERO_EXTEND. */
6743 if (GET_CODE (x
) == ZERO_EXTEND
)
6745 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6746 know that the last value didn't have any inappropriate bits
6748 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6749 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6750 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6751 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
6752 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6753 return XEXP (XEXP (x
, 0), 0);
6755 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6756 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6757 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6758 && subreg_lowpart_p (XEXP (x
, 0))
6759 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
6760 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
6761 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6762 return SUBREG_REG (XEXP (x
, 0));
6764 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6765 is a comparison and STORE_FLAG_VALUE permits. This is like
6766 the first case, but it works even when GET_MODE (x) is larger
6767 than HOST_WIDE_INT. */
6768 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
6769 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
6770 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
6771 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6772 <= HOST_BITS_PER_WIDE_INT
)
6773 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6774 return XEXP (XEXP (x
, 0), 0);
6776 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6777 if (GET_CODE (XEXP (x
, 0)) == SUBREG
6778 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
6779 && subreg_lowpart_p (XEXP (x
, 0))
6780 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
6781 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
6782 <= HOST_BITS_PER_WIDE_INT
)
6783 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6784 return SUBREG_REG (XEXP (x
, 0));
6788 /* If we reach here, we want to return a pair of shifts. The inner
6789 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6790 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6791 logical depending on the value of UNSIGNEDP.
6793 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6794 converted into an AND of a shift.
6796 We must check for the case where the left shift would have a negative
6797 count. This can happen in a case like (x >> 31) & 255 on machines
6798 that can't shift by a constant. On those machines, we would first
6799 combine the shift with the AND to produce a variable-position
6800 extraction. Then the constant of 31 would be substituted in
6801 to produce such a position. */
6803 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
6804 if (modewidth
>= pos
+ len
)
6806 enum machine_mode mode
= GET_MODE (x
);
6807 tem
= gen_lowpart (mode
, XEXP (x
, 0));
6808 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
6810 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6811 tem
, modewidth
- pos
- len
);
6812 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
6813 mode
, tem
, modewidth
- len
);
6815 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
6816 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
6817 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
6820 ((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6822 /* Any other cases we can't handle. */
6825 /* If we couldn't do this for some reason, return the original
6827 if (GET_CODE (tem
) == CLOBBER
)
6833 /* X is a SET which contains an assignment of one object into
6834 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6835 or certain SUBREGS). If possible, convert it into a series of
6838 We half-heartedly support variable positions, but do not at all
6839 support variable lengths. */
6842 expand_field_assignment (const_rtx x
)
6845 rtx pos
; /* Always counts from low bit. */
6847 rtx mask
, cleared
, masked
;
6848 enum machine_mode compute_mode
;
6850 /* Loop until we find something we can't simplify. */
6853 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
6854 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
6856 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
6857 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
6858 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
6860 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
6861 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
6863 inner
= XEXP (SET_DEST (x
), 0);
6864 len
= INTVAL (XEXP (SET_DEST (x
), 1));
6865 pos
= XEXP (SET_DEST (x
), 2);
6867 /* A constant position should stay within the width of INNER. */
6868 if (CONST_INT_P (pos
)
6869 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
6872 if (BITS_BIG_ENDIAN
)
6874 if (CONST_INT_P (pos
))
6875 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
6877 else if (GET_CODE (pos
) == MINUS
6878 && CONST_INT_P (XEXP (pos
, 1))
6879 && (INTVAL (XEXP (pos
, 1))
6880 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
6881 /* If position is ADJUST - X, new position is X. */
6882 pos
= XEXP (pos
, 0);
6884 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
6885 GEN_INT (GET_MODE_PRECISION (
6892 /* A SUBREG between two modes that occupy the same numbers of words
6893 can be done by moving the SUBREG to the source. */
6894 else if (GET_CODE (SET_DEST (x
)) == SUBREG
6895 /* We need SUBREGs to compute nonzero_bits properly. */
6896 && nonzero_sign_valid
6897 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
6898 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
6899 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
6900 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
6902 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
6904 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
6911 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
6912 inner
= SUBREG_REG (inner
);
6914 compute_mode
= GET_MODE (inner
);
6916 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6917 if (! SCALAR_INT_MODE_P (compute_mode
))
6919 enum machine_mode imode
;
6921 /* Don't do anything for vector or complex integral types. */
6922 if (! FLOAT_MODE_P (compute_mode
))
6925 /* Try to find an integral mode to pun with. */
6926 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
6927 if (imode
== BLKmode
)
6930 compute_mode
= imode
;
6931 inner
= gen_lowpart (imode
, inner
);
6934 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6935 if (len
>= HOST_BITS_PER_WIDE_INT
)
6938 /* Now compute the equivalent expression. Make a copy of INNER
6939 for the SET_DEST in case it is a MEM into which we will substitute;
6940 we don't want shared RTL in that case. */
6941 mask
= GEN_INT (((unsigned HOST_WIDE_INT
) 1 << len
) - 1);
6942 cleared
= simplify_gen_binary (AND
, compute_mode
,
6943 simplify_gen_unary (NOT
, compute_mode
,
6944 simplify_gen_binary (ASHIFT
,
6949 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
6950 simplify_gen_binary (
6952 gen_lowpart (compute_mode
, SET_SRC (x
)),
6956 x
= gen_rtx_SET (VOIDmode
, copy_rtx (inner
),
6957 simplify_gen_binary (IOR
, compute_mode
,
6964 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6965 it is an RTX that represents the (variable) starting position; otherwise,
6966 POS is the (constant) starting bit position. Both are counted from the LSB.
6968 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
6970 IN_DEST is nonzero if this is a reference in the destination of a SET.
6971 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6972 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6975 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6976 ZERO_EXTRACT should be built even for bits starting at bit 0.
6978 MODE is the desired mode of the result (if IN_DEST == 0).
6980 The result is an RTX for the extraction or NULL_RTX if the target
6984 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
6985 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
6986 int in_dest
, int in_compare
)
6988 /* This mode describes the size of the storage area
6989 to fetch the overall value from. Within that, we
6990 ignore the POS lowest bits, etc. */
6991 enum machine_mode is_mode
= GET_MODE (inner
);
6992 enum machine_mode inner_mode
;
6993 enum machine_mode wanted_inner_mode
;
6994 enum machine_mode wanted_inner_reg_mode
= word_mode
;
6995 enum machine_mode pos_mode
= word_mode
;
6996 enum machine_mode extraction_mode
= word_mode
;
6997 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
6999 rtx orig_pos_rtx
= pos_rtx
;
7000 HOST_WIDE_INT orig_pos
;
7002 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7003 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7005 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7007 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7008 consider just the QI as the memory to extract from.
7009 The subreg adds or removes high bits; its mode is
7010 irrelevant to the meaning of this extraction,
7011 since POS and LEN count from the lsb. */
7012 if (MEM_P (SUBREG_REG (inner
)))
7013 is_mode
= GET_MODE (SUBREG_REG (inner
));
7014 inner
= SUBREG_REG (inner
);
7016 else if (GET_CODE (inner
) == ASHIFT
7017 && CONST_INT_P (XEXP (inner
, 1))
7018 && pos_rtx
== 0 && pos
== 0
7019 && len
> UINTVAL (XEXP (inner
, 1)))
7021 /* We're extracting the least significant bits of an rtx
7022 (ashift X (const_int C)), where LEN > C. Extract the
7023 least significant (LEN - C) bits of X, giving an rtx
7024 whose mode is MODE, then shift it left C times. */
7025 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7026 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7027 unsignedp
, in_dest
, in_compare
);
7029 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7031 else if (GET_CODE (inner
) == TRUNCATE
)
7032 inner
= XEXP (inner
, 0);
7034 inner_mode
= GET_MODE (inner
);
7036 /* See if this can be done without an extraction. We never can if the
7037 width of the field is not the same as that of some integer mode. For
7038 registers, we can only avoid the extraction if the position is at the
7039 low-order bit and this is either not in the destination or we have the
7040 appropriate STRICT_LOW_PART operation available.
7042 For MEM, we can avoid an extract if the field starts on an appropriate
7043 boundary and we can change the mode of the memory reference. */
7045 if (tmode
!= BLKmode
7046 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7048 && (inner_mode
== tmode
7050 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7051 || reg_truncated_to_mode (tmode
, inner
))
7054 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7055 || (MEM_P (inner
) && pos_rtx
== 0
7057 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7058 : BITS_PER_UNIT
)) == 0
7059 /* We can't do this if we are widening INNER_MODE (it
7060 may not be aligned, for one thing). */
7061 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7062 && (inner_mode
== tmode
7063 || (! mode_dependent_address_p (XEXP (inner
, 0),
7064 MEM_ADDR_SPACE (inner
))
7065 && ! MEM_VOLATILE_P (inner
))))))
7067 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7068 field. If the original and current mode are the same, we need not
7069 adjust the offset. Otherwise, we do if bytes big endian.
7071 If INNER is not a MEM, get a piece consisting of just the field
7072 of interest (in this case POS % BITS_PER_WORD must be 0). */
7076 HOST_WIDE_INT offset
;
7078 /* POS counts from lsb, but make OFFSET count in memory order. */
7079 if (BYTES_BIG_ENDIAN
)
7080 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7082 offset
= pos
/ BITS_PER_UNIT
;
7084 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7086 else if (REG_P (inner
))
7088 if (tmode
!= inner_mode
)
7090 /* We can't call gen_lowpart in a DEST since we
7091 always want a SUBREG (see below) and it would sometimes
7092 return a new hard register. */
7095 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7097 if (WORDS_BIG_ENDIAN
7098 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7099 final_word
= ((GET_MODE_SIZE (inner_mode
)
7100 - GET_MODE_SIZE (tmode
))
7101 / UNITS_PER_WORD
) - final_word
;
7103 final_word
*= UNITS_PER_WORD
;
7104 if (BYTES_BIG_ENDIAN
&&
7105 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7106 final_word
+= (GET_MODE_SIZE (inner_mode
)
7107 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7109 /* Avoid creating invalid subregs, for example when
7110 simplifying (x>>32)&255. */
7111 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7114 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7117 new_rtx
= gen_lowpart (tmode
, inner
);
7123 new_rtx
= force_to_mode (inner
, tmode
,
7124 len
>= HOST_BITS_PER_WIDE_INT
7125 ? ~(unsigned HOST_WIDE_INT
) 0
7126 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7129 /* If this extraction is going into the destination of a SET,
7130 make a STRICT_LOW_PART unless we made a MEM. */
7133 return (MEM_P (new_rtx
) ? new_rtx
7134 : (GET_CODE (new_rtx
) != SUBREG
7135 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7136 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7141 if (CONST_SCALAR_INT_P (new_rtx
))
7142 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7143 mode
, new_rtx
, tmode
);
7145 /* If we know that no extraneous bits are set, and that the high
7146 bit is not set, convert the extraction to the cheaper of
7147 sign and zero extension, that are equivalent in these cases. */
7148 if (flag_expensive_optimizations
7149 && (HWI_COMPUTABLE_MODE_P (tmode
)
7150 && ((nonzero_bits (new_rtx
, tmode
)
7151 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7154 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7155 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7157 /* Prefer ZERO_EXTENSION, since it gives more information to
7159 if (set_src_cost (temp
, optimize_this_for_speed_p
)
7160 <= set_src_cost (temp1
, optimize_this_for_speed_p
))
7165 /* Otherwise, sign- or zero-extend unless we already are in the
7168 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7172 /* Unless this is a COMPARE or we have a funny memory reference,
7173 don't do anything with zero-extending field extracts starting at
7174 the low-order bit since they are simple AND operations. */
7175 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7176 && ! in_compare
&& unsignedp
)
7179 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7180 if the position is not a constant and the length is not 1. In all
7181 other cases, we would only be going outside our object in cases when
7182 an original shift would have been undefined. */
7184 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7185 || (pos_rtx
!= 0 && len
!= 1)))
7188 enum extraction_pattern pattern
= (in_dest
? EP_insv
7189 : unsignedp
? EP_extzv
: EP_extv
);
7191 /* If INNER is not from memory, we want it to have the mode of a register
7192 extraction pattern's structure operand, or word_mode if there is no
7193 such pattern. The same applies to extraction_mode and pos_mode
7194 and their respective operands.
7196 For memory, assume that the desired extraction_mode and pos_mode
7197 are the same as for a register operation, since at present we don't
7198 have named patterns for aligned memory structures. */
7199 struct extraction_insn insn
;
7200 if (get_best_reg_extraction_insn (&insn
, pattern
,
7201 GET_MODE_BITSIZE (inner_mode
), mode
))
7203 wanted_inner_reg_mode
= insn
.struct_mode
;
7204 pos_mode
= insn
.pos_mode
;
7205 extraction_mode
= insn
.field_mode
;
7208 /* Never narrow an object, since that might not be safe. */
7210 if (mode
!= VOIDmode
7211 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7212 extraction_mode
= mode
;
7215 wanted_inner_mode
= wanted_inner_reg_mode
;
7218 /* Be careful not to go beyond the extracted object and maintain the
7219 natural alignment of the memory. */
7220 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7221 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7222 > GET_MODE_BITSIZE (wanted_inner_mode
))
7224 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7225 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7231 if (BITS_BIG_ENDIAN
)
7233 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7234 BITS_BIG_ENDIAN style. If position is constant, compute new
7235 position. Otherwise, build subtraction.
7236 Note that POS is relative to the mode of the original argument.
7237 If it's a MEM we need to recompute POS relative to that.
7238 However, if we're extracting from (or inserting into) a register,
7239 we want to recompute POS relative to wanted_inner_mode. */
7240 int width
= (MEM_P (inner
)
7241 ? GET_MODE_BITSIZE (is_mode
)
7242 : GET_MODE_BITSIZE (wanted_inner_mode
));
7245 pos
= width
- len
- pos
;
7248 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
7249 /* POS may be less than 0 now, but we check for that below.
7250 Note that it can only be less than 0 if !MEM_P (inner). */
7253 /* If INNER has a wider mode, and this is a constant extraction, try to
7254 make it smaller and adjust the byte to point to the byte containing
7256 if (wanted_inner_mode
!= VOIDmode
7257 && inner_mode
!= wanted_inner_mode
7259 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7261 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7262 && ! MEM_VOLATILE_P (inner
))
7266 /* The computations below will be correct if the machine is big
7267 endian in both bits and bytes or little endian in bits and bytes.
7268 If it is mixed, we must adjust. */
7270 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7271 adjust OFFSET to compensate. */
7272 if (BYTES_BIG_ENDIAN
7273 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7274 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7276 /* We can now move to the desired byte. */
7277 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7278 * GET_MODE_SIZE (wanted_inner_mode
);
7279 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7281 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7282 && is_mode
!= wanted_inner_mode
)
7283 offset
= (GET_MODE_SIZE (is_mode
)
7284 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7286 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7289 /* If INNER is not memory, get it into the proper mode. If we are changing
7290 its mode, POS must be a constant and smaller than the size of the new
7292 else if (!MEM_P (inner
))
7294 /* On the LHS, don't create paradoxical subregs implicitely truncating
7295 the register unless TRULY_NOOP_TRUNCATION. */
7297 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7301 if (GET_MODE (inner
) != wanted_inner_mode
7303 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7309 inner
= force_to_mode (inner
, wanted_inner_mode
,
7311 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7312 ? ~(unsigned HOST_WIDE_INT
) 0
7313 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
7318 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7319 have to zero extend. Otherwise, we can just use a SUBREG. */
7321 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7323 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
7325 /* If we know that no extraneous bits are set, and that the high
7326 bit is not set, convert extraction to cheaper one - either
7327 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7329 if (flag_expensive_optimizations
7330 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7331 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7332 & ~(((unsigned HOST_WIDE_INT
)
7333 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7337 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
7339 /* Prefer ZERO_EXTENSION, since it gives more information to
7341 if (set_src_cost (temp1
, optimize_this_for_speed_p
)
7342 < set_src_cost (temp
, optimize_this_for_speed_p
))
7348 /* Make POS_RTX unless we already have it and it is correct. If we don't
7349 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7351 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7352 pos_rtx
= orig_pos_rtx
;
7354 else if (pos_rtx
== 0)
7355 pos_rtx
= GEN_INT (pos
);
7357 /* Make the required operation. See if we can use existing rtx. */
7358 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7359 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7361 new_rtx
= gen_lowpart (mode
, new_rtx
);
7366 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7367 with any other operations in X. Return X without that shift if so. */
7370 extract_left_shift (rtx x
, int count
)
7372 enum rtx_code code
= GET_CODE (x
);
7373 enum machine_mode mode
= GET_MODE (x
);
7379 /* This is the shift itself. If it is wide enough, we will return
7380 either the value being shifted if the shift count is equal to
7381 COUNT or a shift for the difference. */
7382 if (CONST_INT_P (XEXP (x
, 1))
7383 && INTVAL (XEXP (x
, 1)) >= count
)
7384 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7385 INTVAL (XEXP (x
, 1)) - count
);
7389 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7390 return simplify_gen_unary (code
, mode
, tem
, mode
);
7394 case PLUS
: case IOR
: case XOR
: case AND
:
7395 /* If we can safely shift this constant and we find the inner shift,
7396 make a new operation. */
7397 if (CONST_INT_P (XEXP (x
, 1))
7398 && (UINTVAL (XEXP (x
, 1))
7399 & ((((unsigned HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
7400 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7401 return simplify_gen_binary (code
, mode
, tem
,
7402 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
7413 /* Look at the expression rooted at X. Look for expressions
7414 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7415 Form these expressions.
7417 Return the new rtx, usually just X.
7419 Also, for machines like the VAX that don't have logical shift insns,
7420 try to convert logical to arithmetic shift operations in cases where
7421 they are equivalent. This undoes the canonicalizations to logical
7422 shifts done elsewhere.
7424 We try, as much as possible, to re-use rtl expressions to save memory.
7426 IN_CODE says what kind of expression we are processing. Normally, it is
7427 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7428 being kludges), it is MEM. When processing the arguments of a comparison
7429 or a COMPARE against zero, it is COMPARE. */
7432 make_compound_operation (rtx x
, enum rtx_code in_code
)
7434 enum rtx_code code
= GET_CODE (x
);
7435 enum machine_mode mode
= GET_MODE (x
);
7436 int mode_width
= GET_MODE_PRECISION (mode
);
7438 enum rtx_code next_code
;
7444 /* Select the code to be used in recursive calls. Once we are inside an
7445 address, we stay there. If we have a comparison, set to COMPARE,
7446 but once inside, go back to our default of SET. */
7448 next_code
= (code
== MEM
? MEM
7449 : ((code
== PLUS
|| code
== MINUS
)
7450 && SCALAR_INT_MODE_P (mode
)) ? MEM
7451 : ((code
== COMPARE
|| COMPARISON_P (x
))
7452 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7453 : in_code
== COMPARE
? SET
: in_code
);
7455 /* Process depending on the code of this operation. If NEW is set
7456 nonzero, it will be returned. */
7461 /* Convert shifts by constants into multiplications if inside
7463 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7464 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7465 && INTVAL (XEXP (x
, 1)) >= 0
7466 && SCALAR_INT_MODE_P (mode
))
7468 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7469 HOST_WIDE_INT multval
= (HOST_WIDE_INT
) 1 << count
;
7471 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7472 if (GET_CODE (new_rtx
) == NEG
)
7474 new_rtx
= XEXP (new_rtx
, 0);
7477 multval
= trunc_int_for_mode (multval
, mode
);
7478 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, GEN_INT (multval
));
7485 lhs
= make_compound_operation (lhs
, next_code
);
7486 rhs
= make_compound_operation (rhs
, next_code
);
7487 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7488 && SCALAR_INT_MODE_P (mode
))
7490 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7492 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7494 else if (GET_CODE (lhs
) == MULT
7495 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7497 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7498 simplify_gen_unary (NEG
, mode
,
7501 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7505 SUBST (XEXP (x
, 0), lhs
);
7506 SUBST (XEXP (x
, 1), rhs
);
7509 x
= gen_lowpart (mode
, new_rtx
);
7515 lhs
= make_compound_operation (lhs
, next_code
);
7516 rhs
= make_compound_operation (rhs
, next_code
);
7517 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7518 && SCALAR_INT_MODE_P (mode
))
7520 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7522 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7524 else if (GET_CODE (rhs
) == MULT
7525 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7527 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7528 simplify_gen_unary (NEG
, mode
,
7531 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7535 SUBST (XEXP (x
, 0), lhs
);
7536 SUBST (XEXP (x
, 1), rhs
);
7539 return gen_lowpart (mode
, new_rtx
);
7542 /* If the second operand is not a constant, we can't do anything
7544 if (!CONST_INT_P (XEXP (x
, 1)))
7547 /* If the constant is a power of two minus one and the first operand
7548 is a logical right shift, make an extraction. */
7549 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7550 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7552 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7553 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7554 0, in_code
== COMPARE
);
7557 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7558 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7559 && subreg_lowpart_p (XEXP (x
, 0))
7560 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7561 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7563 new_rtx
= make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
7565 new_rtx
= make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new_rtx
, 0,
7566 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
7567 0, in_code
== COMPARE
);
7569 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7570 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7571 || GET_CODE (XEXP (x
, 0)) == IOR
)
7572 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7573 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7574 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7576 /* Apply the distributive law, and then try to make extractions. */
7577 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7578 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7580 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7582 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7585 /* If we are have (and (rotate X C) M) and C is larger than the number
7586 of bits in M, this is an extraction. */
7588 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7589 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7590 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7591 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7593 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7594 new_rtx
= make_extraction (mode
, new_rtx
,
7595 (GET_MODE_PRECISION (mode
)
7596 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7597 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7600 /* On machines without logical shifts, if the operand of the AND is
7601 a logical shift and our mask turns off all the propagated sign
7602 bits, we can replace the logical shift with an arithmetic shift. */
7603 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7604 && !have_insn_for (LSHIFTRT
, mode
)
7605 && have_insn_for (ASHIFTRT
, mode
)
7606 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7607 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7608 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7609 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7611 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7613 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7614 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7616 gen_rtx_ASHIFTRT (mode
,
7617 make_compound_operation
7618 (XEXP (XEXP (x
, 0), 0), next_code
),
7619 XEXP (XEXP (x
, 0), 1)));
7622 /* If the constant is one less than a power of two, this might be
7623 representable by an extraction even if no shift is present.
7624 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7625 we are in a COMPARE. */
7626 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7627 new_rtx
= make_extraction (mode
,
7628 make_compound_operation (XEXP (x
, 0),
7630 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7632 /* If we are in a comparison and this is an AND with a power of two,
7633 convert this into the appropriate bit extract. */
7634 else if (in_code
== COMPARE
7635 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7636 new_rtx
= make_extraction (mode
,
7637 make_compound_operation (XEXP (x
, 0),
7639 i
, NULL_RTX
, 1, 1, 0, 1);
7644 /* If the sign bit is known to be zero, replace this with an
7645 arithmetic shift. */
7646 if (have_insn_for (ASHIFTRT
, mode
)
7647 && ! have_insn_for (LSHIFTRT
, mode
)
7648 && mode_width
<= HOST_BITS_PER_WIDE_INT
7649 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
7651 new_rtx
= gen_rtx_ASHIFTRT (mode
,
7652 make_compound_operation (XEXP (x
, 0),
7658 /* ... fall through ... */
7664 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7665 this is a SIGN_EXTRACT. */
7666 if (CONST_INT_P (rhs
)
7667 && GET_CODE (lhs
) == ASHIFT
7668 && CONST_INT_P (XEXP (lhs
, 1))
7669 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
7670 && INTVAL (XEXP (lhs
, 1)) >= 0
7671 && INTVAL (rhs
) < mode_width
)
7673 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
7674 new_rtx
= make_extraction (mode
, new_rtx
,
7675 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
7676 NULL_RTX
, mode_width
- INTVAL (rhs
),
7677 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7681 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7682 If so, try to merge the shifts into a SIGN_EXTEND. We could
7683 also do this for some cases of SIGN_EXTRACT, but it doesn't
7684 seem worth the effort; the case checked for occurs on Alpha. */
7687 && ! (GET_CODE (lhs
) == SUBREG
7688 && (OBJECT_P (SUBREG_REG (lhs
))))
7689 && CONST_INT_P (rhs
)
7690 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
7691 && INTVAL (rhs
) < mode_width
7692 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
7693 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
7694 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
7695 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
7700 /* Call ourselves recursively on the inner expression. If we are
7701 narrowing the object and it has a different RTL code from
7702 what it originally did, do this SUBREG as a force_to_mode. */
7704 rtx inner
= SUBREG_REG (x
), simplified
;
7706 tem
= make_compound_operation (inner
, in_code
);
7709 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
7713 if (GET_CODE (tem
) != GET_CODE (inner
)
7714 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
7715 && subreg_lowpart_p (x
))
7718 = force_to_mode (tem
, mode
, ~(unsigned HOST_WIDE_INT
) 0, 0);
7720 /* If we have something other than a SUBREG, we might have
7721 done an expansion, so rerun ourselves. */
7722 if (GET_CODE (newer
) != SUBREG
)
7723 newer
= make_compound_operation (newer
, in_code
);
7725 /* force_to_mode can expand compounds. If it just re-expanded the
7726 compound, use gen_lowpart to convert to the desired mode. */
7727 if (rtx_equal_p (newer
, x
)
7728 /* Likewise if it re-expanded the compound only partially.
7729 This happens for SUBREG of ZERO_EXTRACT if they extract
7730 the same number of bits. */
7731 || (GET_CODE (newer
) == SUBREG
7732 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
7733 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
7734 && GET_CODE (inner
) == AND
7735 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
7736 return gen_lowpart (GET_MODE (x
), tem
);
7752 x
= gen_lowpart (mode
, new_rtx
);
7753 code
= GET_CODE (x
);
7756 /* Now recursively process each operand of this operation. We need to
7757 handle ZERO_EXTEND specially so that we don't lose track of the
7759 if (GET_CODE (x
) == ZERO_EXTEND
)
7761 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7762 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7763 new_rtx
, GET_MODE (XEXP (x
, 0)));
7766 SUBST (XEXP (x
, 0), new_rtx
);
7770 fmt
= GET_RTX_FORMAT (code
);
7771 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
7774 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
7775 SUBST (XEXP (x
, i
), new_rtx
);
7777 else if (fmt
[i
] == 'E')
7778 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7780 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
7781 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
7785 /* If this is a commutative operation, the changes to the operands
7786 may have made it noncanonical. */
7787 if (COMMUTATIVE_ARITH_P (x
)
7788 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
7791 SUBST (XEXP (x
, 0), XEXP (x
, 1));
7792 SUBST (XEXP (x
, 1), tem
);
7798 /* Given M see if it is a value that would select a field of bits
7799 within an item, but not the entire word. Return -1 if not.
7800 Otherwise, return the starting position of the field, where 0 is the
7803 *PLEN is set to the length of the field. */
7806 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
7808 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7809 int pos
= m
? ctz_hwi (m
) : -1;
7813 /* Now shift off the low-order zero bits and see if we have a
7814 power of two minus 1. */
7815 len
= exact_log2 ((m
>> pos
) + 1);
7824 /* If X refers to a register that equals REG in value, replace these
7825 references with REG. */
7827 canon_reg_for_combine (rtx x
, rtx reg
)
7834 enum rtx_code code
= GET_CODE (x
);
7835 switch (GET_RTX_CLASS (code
))
7838 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7839 if (op0
!= XEXP (x
, 0))
7840 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
7845 case RTX_COMM_ARITH
:
7846 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7847 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7848 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7849 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
7853 case RTX_COMM_COMPARE
:
7854 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7855 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7856 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
7857 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
7858 GET_MODE (op0
), op0
, op1
);
7862 case RTX_BITFIELD_OPS
:
7863 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
7864 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
7865 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
7866 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
7867 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
7868 GET_MODE (op0
), op0
, op1
, op2
);
7873 if (rtx_equal_p (get_last_value (reg
), x
)
7874 || rtx_equal_p (reg
, get_last_value (x
)))
7883 fmt
= GET_RTX_FORMAT (code
);
7885 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7888 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
7889 if (op
!= XEXP (x
, i
))
7899 else if (fmt
[i
] == 'E')
7902 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
7904 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
7905 if (op
!= XVECEXP (x
, i
, j
))
7912 XVECEXP (x
, i
, j
) = op
;
7923 /* Return X converted to MODE. If the value is already truncated to
7924 MODE we can just return a subreg even though in the general case we
7925 would need an explicit truncation. */
7928 gen_lowpart_or_truncate (enum machine_mode mode
, rtx x
)
7930 if (!CONST_INT_P (x
)
7931 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
7932 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
7933 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
7935 /* Bit-cast X into an integer mode. */
7936 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
7937 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
7938 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
7942 return gen_lowpart (mode
, x
);
7945 /* See if X can be simplified knowing that we will only refer to it in
7946 MODE and will only refer to those bits that are nonzero in MASK.
7947 If other bits are being computed or if masking operations are done
7948 that select a superset of the bits in MASK, they can sometimes be
7951 Return a possibly simplified expression, but always convert X to
7952 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7954 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7955 are all off in X. This is used when X will be complemented, by either
7956 NOT, NEG, or XOR. */
7959 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
7962 enum rtx_code code
= GET_CODE (x
);
7963 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
7964 enum machine_mode op_mode
;
7965 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
7968 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7969 code below will do the wrong thing since the mode of such an
7970 expression is VOIDmode.
7972 Also do nothing if X is a CLOBBER; this can happen if X was
7973 the return value from a call to gen_lowpart. */
7974 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
7977 /* We want to perform the operation is its present mode unless we know
7978 that the operation is valid in MODE, in which case we do the operation
7980 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
7981 && have_insn_for (code
, mode
))
7982 ? mode
: GET_MODE (x
));
7984 /* It is not valid to do a right-shift in a narrower mode
7985 than the one it came in with. */
7986 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
7987 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
7988 op_mode
= GET_MODE (x
);
7990 /* Truncate MASK to fit OP_MODE. */
7992 mask
&= GET_MODE_MASK (op_mode
);
7994 /* When we have an arithmetic operation, or a shift whose count we
7995 do not know, we need to assume that all bits up to the highest-order
7996 bit in MASK will be needed. This is how we form such a mask. */
7997 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
7998 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
8000 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
8003 /* Determine what bits of X are guaranteed to be (non)zero. */
8004 nonzero
= nonzero_bits (x
, mode
);
8006 /* If none of the bits in X are needed, return a zero. */
8007 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8010 /* If X is a CONST_INT, return a new one. Do this here since the
8011 test below will fail. */
8012 if (CONST_INT_P (x
))
8014 if (SCALAR_INT_MODE_P (mode
))
8015 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8018 x
= GEN_INT (INTVAL (x
) & mask
);
8019 return gen_lowpart_common (mode
, x
);
8023 /* If X is narrower than MODE and we want all the bits in X's mode, just
8024 get X in the proper mode. */
8025 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8026 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8027 return gen_lowpart (mode
, x
);
8029 /* We can ignore the effect of a SUBREG if it narrows the mode or
8030 if the constant masks to zero all the bits the mode doesn't have. */
8031 if (GET_CODE (x
) == SUBREG
8032 && subreg_lowpart_p (x
)
8033 && ((GET_MODE_SIZE (GET_MODE (x
))
8034 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8036 & GET_MODE_MASK (GET_MODE (x
))
8037 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8038 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8040 /* The arithmetic simplifications here only work for scalar integer modes. */
8041 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8042 return gen_lowpart_or_truncate (mode
, x
);
8047 /* If X is a (clobber (const_int)), return it since we know we are
8048 generating something that won't match. */
8055 x
= expand_compound_operation (x
);
8056 if (GET_CODE (x
) != code
)
8057 return force_to_mode (x
, mode
, mask
, next_select
);
8061 /* Similarly for a truncate. */
8062 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8065 /* If this is an AND with a constant, convert it into an AND
8066 whose constant is the AND of that constant with MASK. If it
8067 remains an AND of MASK, delete it since it is redundant. */
8069 if (CONST_INT_P (XEXP (x
, 1)))
8071 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8072 mask
& INTVAL (XEXP (x
, 1)));
8074 /* If X is still an AND, see if it is an AND with a mask that
8075 is just some low-order bits. If so, and it is MASK, we don't
8078 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8079 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8083 /* If it remains an AND, try making another AND with the bits
8084 in the mode mask that aren't in MASK turned on. If the
8085 constant in the AND is wide enough, this might make a
8086 cheaper constant. */
8088 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8089 && GET_MODE_MASK (GET_MODE (x
)) != mask
8090 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8092 unsigned HOST_WIDE_INT cval
8093 = UINTVAL (XEXP (x
, 1))
8094 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8095 int width
= GET_MODE_PRECISION (GET_MODE (x
));
8098 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8099 number, sign extend it. */
8100 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
8101 && (cval
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8102 cval
|= (unsigned HOST_WIDE_INT
) -1 << width
;
8104 y
= simplify_gen_binary (AND
, GET_MODE (x
),
8105 XEXP (x
, 0), GEN_INT (cval
));
8106 if (set_src_cost (y
, optimize_this_for_speed_p
)
8107 < set_src_cost (x
, optimize_this_for_speed_p
))
8117 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8118 low-order bits (as in an alignment operation) and FOO is already
8119 aligned to that boundary, mask C1 to that boundary as well.
8120 This may eliminate that PLUS and, later, the AND. */
8123 unsigned int width
= GET_MODE_PRECISION (mode
);
8124 unsigned HOST_WIDE_INT smask
= mask
;
8126 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8127 number, sign extend it. */
8129 if (width
< HOST_BITS_PER_WIDE_INT
8130 && (smask
& ((unsigned HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
8131 smask
|= (unsigned HOST_WIDE_INT
) (-1) << width
;
8133 if (CONST_INT_P (XEXP (x
, 1))
8134 && exact_log2 (- smask
) >= 0
8135 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8136 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8137 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8138 (INTVAL (XEXP (x
, 1)) & smask
)),
8139 mode
, smask
, next_select
);
8142 /* ... fall through ... */
8145 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8146 most significant bit in MASK since carries from those bits will
8147 affect the bits we are interested in. */
8152 /* If X is (minus C Y) where C's least set bit is larger than any bit
8153 in the mask, then we may replace with (neg Y). */
8154 if (CONST_INT_P (XEXP (x
, 0))
8155 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
8156 & -INTVAL (XEXP (x
, 0))))
8159 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8161 return force_to_mode (x
, mode
, mask
, next_select
);
8164 /* Similarly, if C contains every bit in the fuller_mask, then we may
8165 replace with (not Y). */
8166 if (CONST_INT_P (XEXP (x
, 0))
8167 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8169 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8170 XEXP (x
, 1), GET_MODE (x
));
8171 return force_to_mode (x
, mode
, mask
, next_select
);
8179 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8180 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8181 operation which may be a bitfield extraction. Ensure that the
8182 constant we form is not wider than the mode of X. */
8184 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8185 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8186 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8187 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8188 && CONST_INT_P (XEXP (x
, 1))
8189 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8190 + floor_log2 (INTVAL (XEXP (x
, 1))))
8191 < GET_MODE_PRECISION (GET_MODE (x
)))
8192 && (UINTVAL (XEXP (x
, 1))
8193 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8195 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
8196 << INTVAL (XEXP (XEXP (x
, 0), 1)));
8197 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8198 XEXP (XEXP (x
, 0), 0), temp
);
8199 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8200 XEXP (XEXP (x
, 0), 1));
8201 return force_to_mode (x
, mode
, mask
, next_select
);
8205 /* For most binary operations, just propagate into the operation and
8206 change the mode if we have an operation of that mode. */
8208 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8209 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8211 /* If we ended up truncating both operands, truncate the result of the
8212 operation instead. */
8213 if (GET_CODE (op0
) == TRUNCATE
8214 && GET_CODE (op1
) == TRUNCATE
)
8216 op0
= XEXP (op0
, 0);
8217 op1
= XEXP (op1
, 0);
8220 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8221 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8223 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8224 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8228 /* For left shifts, do the same, but just for the first operand.
8229 However, we cannot do anything with shifts where we cannot
8230 guarantee that the counts are smaller than the size of the mode
8231 because such a count will have a different meaning in a
8234 if (! (CONST_INT_P (XEXP (x
, 1))
8235 && INTVAL (XEXP (x
, 1)) >= 0
8236 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8237 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8238 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8239 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8242 /* If the shift count is a constant and we can do arithmetic in
8243 the mode of the shift, refine which bits we need. Otherwise, use the
8244 conservative form of the mask. */
8245 if (CONST_INT_P (XEXP (x
, 1))
8246 && INTVAL (XEXP (x
, 1)) >= 0
8247 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8248 && HWI_COMPUTABLE_MODE_P (op_mode
))
8249 mask
>>= INTVAL (XEXP (x
, 1));
8253 op0
= gen_lowpart_or_truncate (op_mode
,
8254 force_to_mode (XEXP (x
, 0), op_mode
,
8255 mask
, next_select
));
8257 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8258 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8262 /* Here we can only do something if the shift count is a constant,
8263 this shift constant is valid for the host, and we can do arithmetic
8266 if (CONST_INT_P (XEXP (x
, 1))
8267 && INTVAL (XEXP (x
, 1)) >= 0
8268 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8269 && HWI_COMPUTABLE_MODE_P (op_mode
))
8271 rtx inner
= XEXP (x
, 0);
8272 unsigned HOST_WIDE_INT inner_mask
;
8274 /* Select the mask of the bits we need for the shift operand. */
8275 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8277 /* We can only change the mode of the shift if we can do arithmetic
8278 in the mode of the shift and INNER_MASK is no wider than the
8279 width of X's mode. */
8280 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8281 op_mode
= GET_MODE (x
);
8283 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8285 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8286 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8289 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8290 shift and AND produces only copies of the sign bit (C2 is one less
8291 than a power of two), we can do this with just a shift. */
8293 if (GET_CODE (x
) == LSHIFTRT
8294 && CONST_INT_P (XEXP (x
, 1))
8295 /* The shift puts one of the sign bit copies in the least significant
8297 && ((INTVAL (XEXP (x
, 1))
8298 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8299 >= GET_MODE_PRECISION (GET_MODE (x
)))
8300 && exact_log2 (mask
+ 1) >= 0
8301 /* Number of bits left after the shift must be more than the mask
8303 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8304 <= GET_MODE_PRECISION (GET_MODE (x
)))
8305 /* Must be more sign bit copies than the mask needs. */
8306 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8307 >= exact_log2 (mask
+ 1)))
8308 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8309 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8310 - exact_log2 (mask
+ 1)));
8315 /* If we are just looking for the sign bit, we don't need this shift at
8316 all, even if it has a variable count. */
8317 if (val_signbit_p (GET_MODE (x
), mask
))
8318 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8320 /* If this is a shift by a constant, get a mask that contains those bits
8321 that are not copies of the sign bit. We then have two cases: If
8322 MASK only includes those bits, this can be a logical shift, which may
8323 allow simplifications. If MASK is a single-bit field not within
8324 those bits, we are requesting a copy of the sign bit and hence can
8325 shift the sign bit to the appropriate location. */
8327 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8328 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8332 /* If the considered data is wider than HOST_WIDE_INT, we can't
8333 represent a mask for all its bits in a single scalar.
8334 But we only care about the lower bits, so calculate these. */
8336 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8338 nonzero
= ~(unsigned HOST_WIDE_INT
) 0;
8340 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8341 is the number of bits a full-width mask would have set.
8342 We need only shift if these are fewer than nonzero can
8343 hold. If not, we must keep all bits set in nonzero. */
8345 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8346 < HOST_BITS_PER_WIDE_INT
)
8347 nonzero
>>= INTVAL (XEXP (x
, 1))
8348 + HOST_BITS_PER_WIDE_INT
8349 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8353 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8354 nonzero
>>= INTVAL (XEXP (x
, 1));
8357 if ((mask
& ~nonzero
) == 0)
8359 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8360 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8361 if (GET_CODE (x
) != ASHIFTRT
)
8362 return force_to_mode (x
, mode
, mask
, next_select
);
8365 else if ((i
= exact_log2 (mask
)) >= 0)
8367 x
= simplify_shift_const
8368 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8369 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8371 if (GET_CODE (x
) != ASHIFTRT
)
8372 return force_to_mode (x
, mode
, mask
, next_select
);
8376 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8377 even if the shift count isn't a constant. */
8379 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8380 XEXP (x
, 0), XEXP (x
, 1));
8384 /* If this is a zero- or sign-extension operation that just affects bits
8385 we don't care about, remove it. Be sure the call above returned
8386 something that is still a shift. */
8388 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8389 && CONST_INT_P (XEXP (x
, 1))
8390 && INTVAL (XEXP (x
, 1)) >= 0
8391 && (INTVAL (XEXP (x
, 1))
8392 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8393 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8394 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8395 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8402 /* If the shift count is constant and we can do computations
8403 in the mode of X, compute where the bits we care about are.
8404 Otherwise, we can't do anything. Don't change the mode of
8405 the shift or propagate MODE into the shift, though. */
8406 if (CONST_INT_P (XEXP (x
, 1))
8407 && INTVAL (XEXP (x
, 1)) >= 0)
8409 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8410 GET_MODE (x
), GEN_INT (mask
),
8412 if (temp
&& CONST_INT_P (temp
))
8414 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8415 INTVAL (temp
), next_select
));
8420 /* If we just want the low-order bit, the NEG isn't needed since it
8421 won't change the low-order bit. */
8423 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8425 /* We need any bits less significant than the most significant bit in
8426 MASK since carries from those bits will affect the bits we are
8432 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8433 same as the XOR case above. Ensure that the constant we form is not
8434 wider than the mode of X. */
8436 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8437 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8438 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8439 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8440 < GET_MODE_PRECISION (GET_MODE (x
)))
8441 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8443 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8445 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8446 XEXP (XEXP (x
, 0), 0), temp
);
8447 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8448 temp
, XEXP (XEXP (x
, 0), 1));
8450 return force_to_mode (x
, mode
, mask
, next_select
);
8453 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8454 use the full mask inside the NOT. */
8458 op0
= gen_lowpart_or_truncate (op_mode
,
8459 force_to_mode (XEXP (x
, 0), mode
, mask
,
8461 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8462 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8466 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8467 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8468 which is equal to STORE_FLAG_VALUE. */
8469 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8470 && XEXP (x
, 1) == const0_rtx
8471 && GET_MODE (XEXP (x
, 0)) == mode
8472 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
8473 && (nonzero_bits (XEXP (x
, 0), mode
)
8474 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8475 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8480 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8481 written in a narrower mode. We play it safe and do not do so. */
8484 gen_lowpart_or_truncate (GET_MODE (x
),
8485 force_to_mode (XEXP (x
, 1), mode
,
8486 mask
, next_select
)));
8488 gen_lowpart_or_truncate (GET_MODE (x
),
8489 force_to_mode (XEXP (x
, 2), mode
,
8490 mask
, next_select
)));
8497 /* Ensure we return a value of the proper mode. */
8498 return gen_lowpart_or_truncate (mode
, x
);
8501 /* Return nonzero if X is an expression that has one of two values depending on
8502 whether some other value is zero or nonzero. In that case, we return the
8503 value that is being tested, *PTRUE is set to the value if the rtx being
8504 returned has a nonzero value, and *PFALSE is set to the other alternative.
8506 If we return zero, we set *PTRUE and *PFALSE to X. */
8509 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8511 enum machine_mode mode
= GET_MODE (x
);
8512 enum rtx_code code
= GET_CODE (x
);
8513 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8514 unsigned HOST_WIDE_INT nz
;
8516 /* If we are comparing a value against zero, we are done. */
8517 if ((code
== NE
|| code
== EQ
)
8518 && XEXP (x
, 1) == const0_rtx
)
8520 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8521 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8525 /* If this is a unary operation whose operand has one of two values, apply
8526 our opcode to compute those values. */
8527 else if (UNARY_P (x
)
8528 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8530 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8531 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8532 GET_MODE (XEXP (x
, 0)));
8536 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8537 make can't possibly match and would suppress other optimizations. */
8538 else if (code
== COMPARE
)
8541 /* If this is a binary operation, see if either side has only one of two
8542 values. If either one does or if both do and they are conditional on
8543 the same value, compute the new true and false values. */
8544 else if (BINARY_P (x
))
8546 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8547 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8549 if ((cond0
!= 0 || cond1
!= 0)
8550 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8552 /* If if_then_else_cond returned zero, then true/false are the
8553 same rtl. We must copy one of them to prevent invalid rtl
8556 true0
= copy_rtx (true0
);
8557 else if (cond1
== 0)
8558 true1
= copy_rtx (true1
);
8560 if (COMPARISON_P (x
))
8562 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8564 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8569 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8570 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8573 return cond0
? cond0
: cond1
;
8576 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8577 operands is zero when the other is nonzero, and vice-versa,
8578 and STORE_FLAG_VALUE is 1 or -1. */
8580 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8581 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8583 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8585 rtx op0
= XEXP (XEXP (x
, 0), 1);
8586 rtx op1
= XEXP (XEXP (x
, 1), 1);
8588 cond0
= XEXP (XEXP (x
, 0), 0);
8589 cond1
= XEXP (XEXP (x
, 1), 0);
8591 if (COMPARISON_P (cond0
)
8592 && COMPARISON_P (cond1
)
8593 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8594 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8595 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8596 || ((swap_condition (GET_CODE (cond0
))
8597 == reversed_comparison_code (cond1
, NULL
))
8598 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8599 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8600 && ! side_effects_p (x
))
8602 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
8603 *pfalse
= simplify_gen_binary (MULT
, mode
,
8605 ? simplify_gen_unary (NEG
, mode
,
8613 /* Similarly for MULT, AND and UMIN, except that for these the result
8615 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8616 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
8617 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8619 cond0
= XEXP (XEXP (x
, 0), 0);
8620 cond1
= XEXP (XEXP (x
, 1), 0);
8622 if (COMPARISON_P (cond0
)
8623 && COMPARISON_P (cond1
)
8624 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
8625 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
8626 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
8627 || ((swap_condition (GET_CODE (cond0
))
8628 == reversed_comparison_code (cond1
, NULL
))
8629 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
8630 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
8631 && ! side_effects_p (x
))
8633 *ptrue
= *pfalse
= const0_rtx
;
8639 else if (code
== IF_THEN_ELSE
)
8641 /* If we have IF_THEN_ELSE already, extract the condition and
8642 canonicalize it if it is NE or EQ. */
8643 cond0
= XEXP (x
, 0);
8644 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
8645 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
8646 return XEXP (cond0
, 0);
8647 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
8649 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
8650 return XEXP (cond0
, 0);
8656 /* If X is a SUBREG, we can narrow both the true and false values
8657 if the inner expression, if there is a condition. */
8658 else if (code
== SUBREG
8659 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
8662 true0
= simplify_gen_subreg (mode
, true0
,
8663 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8664 false0
= simplify_gen_subreg (mode
, false0
,
8665 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
8666 if (true0
&& false0
)
8674 /* If X is a constant, this isn't special and will cause confusions
8675 if we treat it as such. Likewise if it is equivalent to a constant. */
8676 else if (CONSTANT_P (x
)
8677 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
8680 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8681 will be least confusing to the rest of the compiler. */
8682 else if (mode
== BImode
)
8684 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
8688 /* If X is known to be either 0 or -1, those are the true and
8689 false values when testing X. */
8690 else if (x
== constm1_rtx
|| x
== const0_rtx
8691 || (mode
!= VOIDmode
8692 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
8694 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
8698 /* Likewise for 0 or a single bit. */
8699 else if (HWI_COMPUTABLE_MODE_P (mode
)
8700 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
8702 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
8706 /* Otherwise fail; show no condition with true and false values the same. */
8707 *ptrue
= *pfalse
= x
;
8711 /* Return the value of expression X given the fact that condition COND
8712 is known to be true when applied to REG as its first operand and VAL
8713 as its second. X is known to not be shared and so can be modified in
8716 We only handle the simplest cases, and specifically those cases that
8717 arise with IF_THEN_ELSE expressions. */
8720 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
8722 enum rtx_code code
= GET_CODE (x
);
8727 if (side_effects_p (x
))
8730 /* If either operand of the condition is a floating point value,
8731 then we have to avoid collapsing an EQ comparison. */
8733 && rtx_equal_p (x
, reg
)
8734 && ! FLOAT_MODE_P (GET_MODE (x
))
8735 && ! FLOAT_MODE_P (GET_MODE (val
)))
8738 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
8741 /* If X is (abs REG) and we know something about REG's relationship
8742 with zero, we may be able to simplify this. */
8744 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
8747 case GE
: case GT
: case EQ
:
8750 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
8752 GET_MODE (XEXP (x
, 0)));
8757 /* The only other cases we handle are MIN, MAX, and comparisons if the
8758 operands are the same as REG and VAL. */
8760 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
8762 if (rtx_equal_p (XEXP (x
, 0), val
))
8763 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
8765 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
8767 if (COMPARISON_P (x
))
8769 if (comparison_dominates_p (cond
, code
))
8770 return const_true_rtx
;
8772 code
= reversed_comparison_code (x
, NULL
);
8774 && comparison_dominates_p (cond
, code
))
8779 else if (code
== SMAX
|| code
== SMIN
8780 || code
== UMIN
|| code
== UMAX
)
8782 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
8784 /* Do not reverse the condition when it is NE or EQ.
8785 This is because we cannot conclude anything about
8786 the value of 'SMAX (x, y)' when x is not equal to y,
8787 but we can when x equals y. */
8788 if ((code
== SMAX
|| code
== UMAX
)
8789 && ! (cond
== EQ
|| cond
== NE
))
8790 cond
= reverse_condition (cond
);
8795 return unsignedp
? x
: XEXP (x
, 1);
8797 return unsignedp
? x
: XEXP (x
, 0);
8799 return unsignedp
? XEXP (x
, 1) : x
;
8801 return unsignedp
? XEXP (x
, 0) : x
;
8808 else if (code
== SUBREG
)
8810 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
8811 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
8813 if (SUBREG_REG (x
) != r
)
8815 /* We must simplify subreg here, before we lose track of the
8816 original inner_mode. */
8817 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
8818 inner_mode
, SUBREG_BYTE (x
));
8822 SUBST (SUBREG_REG (x
), r
);
8827 /* We don't have to handle SIGN_EXTEND here, because even in the
8828 case of replacing something with a modeless CONST_INT, a
8829 CONST_INT is already (supposed to be) a valid sign extension for
8830 its narrower mode, which implies it's already properly
8831 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8832 story is different. */
8833 else if (code
== ZERO_EXTEND
)
8835 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
8836 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
8838 if (XEXP (x
, 0) != r
)
8840 /* We must simplify the zero_extend here, before we lose
8841 track of the original inner_mode. */
8842 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8847 SUBST (XEXP (x
, 0), r
);
8853 fmt
= GET_RTX_FORMAT (code
);
8854 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8857 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
8858 else if (fmt
[i
] == 'E')
8859 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8860 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
8867 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8868 assignment as a field assignment. */
8871 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
8873 if (x
== y
|| rtx_equal_p (x
, y
))
8876 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
8879 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8880 Note that all SUBREGs of MEM are paradoxical; otherwise they
8881 would have been rewritten. */
8882 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
8883 && MEM_P (SUBREG_REG (y
))
8884 && rtx_equal_p (SUBREG_REG (y
),
8885 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
8888 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
8889 && MEM_P (SUBREG_REG (x
))
8890 && rtx_equal_p (SUBREG_REG (x
),
8891 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
8894 /* We used to see if get_last_value of X and Y were the same but that's
8895 not correct. In one direction, we'll cause the assignment to have
8896 the wrong destination and in the case, we'll import a register into this
8897 insn that might have already have been dead. So fail if none of the
8898 above cases are true. */
8902 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8903 Return that assignment if so.
8905 We only handle the most common cases. */
8908 make_field_assignment (rtx x
)
8910 rtx dest
= SET_DEST (x
);
8911 rtx src
= SET_SRC (x
);
8916 unsigned HOST_WIDE_INT len
;
8918 enum machine_mode mode
;
8920 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8921 a clear of a one-bit field. We will have changed it to
8922 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8925 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
8926 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
8927 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
8928 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8930 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8933 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8937 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
8938 && subreg_lowpart_p (XEXP (src
, 0))
8939 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
8940 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
8941 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
8942 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
8943 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
8944 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8946 assign
= make_extraction (VOIDmode
, dest
, 0,
8947 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
8950 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
8954 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8956 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
8957 && XEXP (XEXP (src
, 0), 0) == const1_rtx
8958 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
8960 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
8963 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
8967 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8968 SRC is an AND with all bits of that field set, then we can discard
8970 if (GET_CODE (dest
) == ZERO_EXTRACT
8971 && CONST_INT_P (XEXP (dest
, 1))
8972 && GET_CODE (src
) == AND
8973 && CONST_INT_P (XEXP (src
, 1)))
8975 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
8976 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
8977 unsigned HOST_WIDE_INT ze_mask
;
8979 if (width
>= HOST_BITS_PER_WIDE_INT
)
8982 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
8984 /* Complete overlap. We can remove the source AND. */
8985 if ((and_mask
& ze_mask
) == ze_mask
)
8986 return gen_rtx_SET (VOIDmode
, dest
, XEXP (src
, 0));
8988 /* Partial overlap. We can reduce the source AND. */
8989 if ((and_mask
& ze_mask
) != and_mask
)
8991 mode
= GET_MODE (src
);
8992 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
8993 gen_int_mode (and_mask
& ze_mask
, mode
));
8994 return gen_rtx_SET (VOIDmode
, dest
, src
);
8998 /* The other case we handle is assignments into a constant-position
8999 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9000 a mask that has all one bits except for a group of zero bits and
9001 OTHER is known to have zeros where C1 has ones, this is such an
9002 assignment. Compute the position and length from C1. Shift OTHER
9003 to the appropriate position, force it to the required mode, and
9004 make the extraction. Check for the AND in both operands. */
9006 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9009 rhs
= expand_compound_operation (XEXP (src
, 0));
9010 lhs
= expand_compound_operation (XEXP (src
, 1));
9012 if (GET_CODE (rhs
) == AND
9013 && CONST_INT_P (XEXP (rhs
, 1))
9014 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9015 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9016 else if (GET_CODE (lhs
) == AND
9017 && CONST_INT_P (XEXP (lhs
, 1))
9018 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9019 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9023 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9024 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9025 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9026 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9029 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9033 /* The mode to use for the source is the mode of the assignment, or of
9034 what is inside a possible STRICT_LOW_PART. */
9035 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9036 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9038 /* Shift OTHER right POS places and make it the source, restricting it
9039 to the proper length and mode. */
9041 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9045 src
= force_to_mode (src
, mode
,
9046 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9047 ? ~(unsigned HOST_WIDE_INT
) 0
9048 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
9051 /* If SRC is masked by an AND that does not make a difference in
9052 the value being stored, strip it. */
9053 if (GET_CODE (assign
) == ZERO_EXTRACT
9054 && CONST_INT_P (XEXP (assign
, 1))
9055 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9056 && GET_CODE (src
) == AND
9057 && CONST_INT_P (XEXP (src
, 1))
9058 && UINTVAL (XEXP (src
, 1))
9059 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1)
9060 src
= XEXP (src
, 0);
9062 return gen_rtx_SET (VOIDmode
, assign
, src
);
9065 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9069 apply_distributive_law (rtx x
)
9071 enum rtx_code code
= GET_CODE (x
);
9072 enum rtx_code inner_code
;
9073 rtx lhs
, rhs
, other
;
9076 /* Distributivity is not true for floating point as it can change the
9077 value. So we don't do it unless -funsafe-math-optimizations. */
9078 if (FLOAT_MODE_P (GET_MODE (x
))
9079 && ! flag_unsafe_math_optimizations
)
9082 /* The outer operation can only be one of the following: */
9083 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9084 && code
!= PLUS
&& code
!= MINUS
)
9090 /* If either operand is a primitive we can't do anything, so get out
9092 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9095 lhs
= expand_compound_operation (lhs
);
9096 rhs
= expand_compound_operation (rhs
);
9097 inner_code
= GET_CODE (lhs
);
9098 if (inner_code
!= GET_CODE (rhs
))
9101 /* See if the inner and outer operations distribute. */
9108 /* These all distribute except over PLUS. */
9109 if (code
== PLUS
|| code
== MINUS
)
9114 if (code
!= PLUS
&& code
!= MINUS
)
9119 /* This is also a multiply, so it distributes over everything. */
9122 /* This used to handle SUBREG, but this turned out to be counter-
9123 productive, since (subreg (op ...)) usually is not handled by
9124 insn patterns, and this "optimization" therefore transformed
9125 recognizable patterns into unrecognizable ones. Therefore the
9126 SUBREG case was removed from here.
9128 It is possible that distributing SUBREG over arithmetic operations
9129 leads to an intermediate result than can then be optimized further,
9130 e.g. by moving the outer SUBREG to the other side of a SET as done
9131 in simplify_set. This seems to have been the original intent of
9132 handling SUBREGs here.
9134 However, with current GCC this does not appear to actually happen,
9135 at least on major platforms. If some case is found where removing
9136 the SUBREG case here prevents follow-on optimizations, distributing
9137 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9143 /* Set LHS and RHS to the inner operands (A and B in the example
9144 above) and set OTHER to the common operand (C in the example).
9145 There is only one way to do this unless the inner operation is
9147 if (COMMUTATIVE_ARITH_P (lhs
)
9148 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9149 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9150 else if (COMMUTATIVE_ARITH_P (lhs
)
9151 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9152 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9153 else if (COMMUTATIVE_ARITH_P (lhs
)
9154 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9155 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9156 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9157 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9161 /* Form the new inner operation, seeing if it simplifies first. */
9162 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9164 /* There is one exception to the general way of distributing:
9165 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9166 if (code
== XOR
&& inner_code
== IOR
)
9169 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9172 /* We may be able to continuing distributing the result, so call
9173 ourselves recursively on the inner operation before forming the
9174 outer operation, which we return. */
9175 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9176 apply_distributive_law (tem
), other
);
9179 /* See if X is of the form (* (+ A B) C), and if so convert to
9180 (+ (* A C) (* B C)) and try to simplify.
9182 Most of the time, this results in no change. However, if some of
9183 the operands are the same or inverses of each other, simplifications
9186 For example, (and (ior A B) (not B)) can occur as the result of
9187 expanding a bit field assignment. When we apply the distributive
9188 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9189 which then simplifies to (and (A (not B))).
9191 Note that no checks happen on the validity of applying the inverse
9192 distributive law. This is pointless since we can do it in the
9193 few places where this routine is called.
9195 N is the index of the term that is decomposed (the arithmetic operation,
9196 i.e. (+ A B) in the first example above). !N is the index of the term that
9197 is distributed, i.e. of C in the first example above. */
9199 distribute_and_simplify_rtx (rtx x
, int n
)
9201 enum machine_mode mode
;
9202 enum rtx_code outer_code
, inner_code
;
9203 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9205 /* Distributivity is not true for floating point as it can change the
9206 value. So we don't do it unless -funsafe-math-optimizations. */
9207 if (FLOAT_MODE_P (GET_MODE (x
))
9208 && ! flag_unsafe_math_optimizations
)
9211 decomposed
= XEXP (x
, n
);
9212 if (!ARITHMETIC_P (decomposed
))
9215 mode
= GET_MODE (x
);
9216 outer_code
= GET_CODE (x
);
9217 distributed
= XEXP (x
, !n
);
9219 inner_code
= GET_CODE (decomposed
);
9220 inner_op0
= XEXP (decomposed
, 0);
9221 inner_op1
= XEXP (decomposed
, 1);
9223 /* Special case (and (xor B C) (not A)), which is equivalent to
9224 (xor (ior A B) (ior A C)) */
9225 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9227 distributed
= XEXP (distributed
, 0);
9233 /* Distribute the second term. */
9234 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9235 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9239 /* Distribute the first term. */
9240 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9241 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9244 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9246 if (GET_CODE (tmp
) != outer_code
9247 && (set_src_cost (tmp
, optimize_this_for_speed_p
)
9248 < set_src_cost (x
, optimize_this_for_speed_p
)))
9254 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9255 in MODE. Return an equivalent form, if different from (and VAROP
9256 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9259 simplify_and_const_int_1 (enum machine_mode mode
, rtx varop
,
9260 unsigned HOST_WIDE_INT constop
)
9262 unsigned HOST_WIDE_INT nonzero
;
9263 unsigned HOST_WIDE_INT orig_constop
;
9268 orig_constop
= constop
;
9269 if (GET_CODE (varop
) == CLOBBER
)
9272 /* Simplify VAROP knowing that we will be only looking at some of the
9275 Note by passing in CONSTOP, we guarantee that the bits not set in
9276 CONSTOP are not significant and will never be examined. We must
9277 ensure that is the case by explicitly masking out those bits
9278 before returning. */
9279 varop
= force_to_mode (varop
, mode
, constop
, 0);
9281 /* If VAROP is a CLOBBER, we will fail so return it. */
9282 if (GET_CODE (varop
) == CLOBBER
)
9285 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9286 to VAROP and return the new constant. */
9287 if (CONST_INT_P (varop
))
9288 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9290 /* See what bits may be nonzero in VAROP. Unlike the general case of
9291 a call to nonzero_bits, here we don't care about bits outside
9294 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9296 /* Turn off all bits in the constant that are known to already be zero.
9297 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9298 which is tested below. */
9302 /* If we don't have any bits left, return zero. */
9306 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9307 a power of two, we can replace this with an ASHIFT. */
9308 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9309 && (i
= exact_log2 (constop
)) >= 0)
9310 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9312 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9313 or XOR, then try to apply the distributive law. This may eliminate
9314 operations if either branch can be simplified because of the AND.
9315 It may also make some cases more complex, but those cases probably
9316 won't match a pattern either with or without this. */
9318 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9322 apply_distributive_law
9323 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9324 simplify_and_const_int (NULL_RTX
,
9328 simplify_and_const_int (NULL_RTX
,
9333 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9334 the AND and see if one of the operands simplifies to zero. If so, we
9335 may eliminate it. */
9337 if (GET_CODE (varop
) == PLUS
9338 && exact_log2 (constop
+ 1) >= 0)
9342 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9343 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9344 if (o0
== const0_rtx
)
9346 if (o1
== const0_rtx
)
9350 /* Make a SUBREG if necessary. If we can't make it, fail. */
9351 varop
= gen_lowpart (mode
, varop
);
9352 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9355 /* If we are only masking insignificant bits, return VAROP. */
9356 if (constop
== nonzero
)
9359 if (varop
== orig_varop
&& constop
== orig_constop
)
9362 /* Otherwise, return an AND. */
9363 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9367 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9370 Return an equivalent form, if different from X. Otherwise, return X. If
9371 X is zero, we are to always construct the equivalent form. */
9374 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
9375 unsigned HOST_WIDE_INT constop
)
9377 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9382 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9383 gen_int_mode (constop
, mode
));
9384 if (GET_MODE (x
) != mode
)
9385 x
= gen_lowpart (mode
, x
);
9389 /* Given a REG, X, compute which bits in X can be nonzero.
9390 We don't care about bits outside of those defined in MODE.
9392 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9393 a shift, AND, or zero_extract, we can do better. */
9396 reg_nonzero_bits_for_combine (const_rtx x
, enum machine_mode mode
,
9397 const_rtx known_x ATTRIBUTE_UNUSED
,
9398 enum machine_mode known_mode ATTRIBUTE_UNUSED
,
9399 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9400 unsigned HOST_WIDE_INT
*nonzero
)
9405 /* If X is a register whose nonzero bits value is current, use it.
9406 Otherwise, if X is a register whose value we can find, use that
9407 value. Otherwise, use the previously-computed global nonzero bits
9408 for this register. */
9410 rsp
= ®_stat
[REGNO (x
)];
9411 if (rsp
->last_set_value
!= 0
9412 && (rsp
->last_set_mode
== mode
9413 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9414 && GET_MODE_CLASS (mode
) == MODE_INT
))
9415 && ((rsp
->last_set_label
>= label_tick_ebb_start
9416 && rsp
->last_set_label
< label_tick
)
9417 || (rsp
->last_set_label
== label_tick
9418 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9419 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9420 && REG_N_SETS (REGNO (x
)) == 1
9422 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9424 *nonzero
&= rsp
->last_set_nonzero_bits
;
9428 tem
= get_last_value (x
);
9432 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9433 /* If X is narrower than MODE and TEM is a non-negative
9434 constant that would appear negative in the mode of X,
9435 sign-extend it for use in reg_nonzero_bits because some
9436 machines (maybe most) will actually do the sign-extension
9437 and this is the conservative approach.
9439 ??? For 2.5, try to tighten up the MD files in this regard
9440 instead of this kludge. */
9442 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
)
9443 && CONST_INT_P (tem
)
9445 && val_signbit_known_set_p (GET_MODE (x
), INTVAL (tem
)))
9446 tem
= GEN_INT (INTVAL (tem
) | ~GET_MODE_MASK (GET_MODE (x
)));
9450 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9452 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9454 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9455 /* We don't know anything about the upper bits. */
9456 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9463 /* Return the number of bits at the high-order end of X that are known to
9464 be equal to the sign bit. X will be used in mode MODE; if MODE is
9465 VOIDmode, X will be used in its own mode. The returned value will always
9466 be between 1 and the number of bits in MODE. */
9469 reg_num_sign_bit_copies_for_combine (const_rtx x
, enum machine_mode mode
,
9470 const_rtx known_x ATTRIBUTE_UNUSED
,
9471 enum machine_mode known_mode
9473 unsigned int known_ret ATTRIBUTE_UNUSED
,
9474 unsigned int *result
)
9479 rsp
= ®_stat
[REGNO (x
)];
9480 if (rsp
->last_set_value
!= 0
9481 && rsp
->last_set_mode
== mode
9482 && ((rsp
->last_set_label
>= label_tick_ebb_start
9483 && rsp
->last_set_label
< label_tick
)
9484 || (rsp
->last_set_label
== label_tick
9485 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9486 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9487 && REG_N_SETS (REGNO (x
)) == 1
9489 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), REGNO (x
)))))
9491 *result
= rsp
->last_set_sign_bit_copies
;
9495 tem
= get_last_value (x
);
9499 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9500 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9501 *result
= rsp
->sign_bit_copies
;
9506 /* Return the number of "extended" bits there are in X, when interpreted
9507 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9508 unsigned quantities, this is the number of high-order zero bits.
9509 For signed quantities, this is the number of copies of the sign bit
9510 minus 1. In both case, this function returns the number of "spare"
9511 bits. For example, if two quantities for which this function returns
9512 at least 1 are added, the addition is known not to overflow.
9514 This function will always return 0 unless called during combine, which
9515 implies that it must be called from a define_split. */
9518 extended_count (const_rtx x
, enum machine_mode mode
, int unsignedp
)
9520 if (nonzero_sign_valid
== 0)
9524 ? (HWI_COMPUTABLE_MODE_P (mode
)
9525 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9526 - floor_log2 (nonzero_bits (x
, mode
)))
9528 : num_sign_bit_copies (x
, mode
) - 1);
9531 /* This function is called from `simplify_shift_const' to merge two
9532 outer operations. Specifically, we have already found that we need
9533 to perform operation *POP0 with constant *PCONST0 at the outermost
9534 position. We would now like to also perform OP1 with constant CONST1
9535 (with *POP0 being done last).
9537 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9538 the resulting operation. *PCOMP_P is set to 1 if we would need to
9539 complement the innermost operand, otherwise it is unchanged.
9541 MODE is the mode in which the operation will be done. No bits outside
9542 the width of this mode matter. It is assumed that the width of this mode
9543 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9545 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9546 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9547 result is simply *PCONST0.
9549 If the resulting operation cannot be expressed as one operation, we
9550 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9553 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
9555 enum rtx_code op0
= *pop0
;
9556 HOST_WIDE_INT const0
= *pconst0
;
9558 const0
&= GET_MODE_MASK (mode
);
9559 const1
&= GET_MODE_MASK (mode
);
9561 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9565 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9568 if (op1
== UNKNOWN
|| op0
== SET
)
9571 else if (op0
== UNKNOWN
)
9572 op0
= op1
, const0
= const1
;
9574 else if (op0
== op1
)
9598 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9599 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9602 /* If the two constants aren't the same, we can't do anything. The
9603 remaining six cases can all be done. */
9604 else if (const0
!= const1
)
9612 /* (a & b) | b == b */
9614 else /* op1 == XOR */
9615 /* (a ^ b) | b == a | b */
9621 /* (a & b) ^ b == (~a) & b */
9622 op0
= AND
, *pcomp_p
= 1;
9623 else /* op1 == IOR */
9624 /* (a | b) ^ b == a & ~b */
9625 op0
= AND
, const0
= ~const0
;
9630 /* (a | b) & b == b */
9632 else /* op1 == XOR */
9633 /* (a ^ b) & b) == (~a) & b */
9640 /* Check for NO-OP cases. */
9641 const0
&= GET_MODE_MASK (mode
);
9643 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9645 else if (const0
== 0 && op0
== AND
)
9647 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9653 /* ??? Slightly redundant with the above mask, but not entirely.
9654 Moving this above means we'd have to sign-extend the mode mask
9655 for the final test. */
9656 if (op0
!= UNKNOWN
&& op0
!= NEG
)
9657 *pconst0
= trunc_int_for_mode (const0
, mode
);
9662 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9663 the shift in. The original shift operation CODE is performed on OP in
9664 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9665 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9666 result of the shift is subject to operation OUTER_CODE with operand
9669 static enum machine_mode
9670 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
9671 enum machine_mode orig_mode
, enum machine_mode mode
,
9672 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
9674 if (orig_mode
== mode
)
9676 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
9678 /* In general we can't perform in wider mode for right shift and rotate. */
9682 /* We can still widen if the bits brought in from the left are identical
9683 to the sign bit of ORIG_MODE. */
9684 if (num_sign_bit_copies (op
, mode
)
9685 > (unsigned) (GET_MODE_PRECISION (mode
)
9686 - GET_MODE_PRECISION (orig_mode
)))
9691 /* Similarly here but with zero bits. */
9692 if (HWI_COMPUTABLE_MODE_P (mode
)
9693 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
9696 /* We can also widen if the bits brought in will be masked off. This
9697 operation is performed in ORIG_MODE. */
9698 if (outer_code
== AND
)
9700 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
9703 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
9719 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9720 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9721 if we cannot simplify it. Otherwise, return a simplified value.
9723 The shift is normally computed in the widest mode we find in VAROP, as
9724 long as it isn't a different number of words than RESULT_MODE. Exceptions
9725 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9728 simplify_shift_const_1 (enum rtx_code code
, enum machine_mode result_mode
,
9729 rtx varop
, int orig_count
)
9731 enum rtx_code orig_code
= code
;
9732 rtx orig_varop
= varop
;
9734 enum machine_mode mode
= result_mode
;
9735 enum machine_mode shift_mode
, tmode
;
9736 unsigned int mode_words
9737 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9738 /* We form (outer_op (code varop count) (outer_const)). */
9739 enum rtx_code outer_op
= UNKNOWN
;
9740 HOST_WIDE_INT outer_const
= 0;
9741 int complement_p
= 0;
9744 /* Make sure and truncate the "natural" shift on the way in. We don't
9745 want to do this inside the loop as it makes it more difficult to
9747 if (SHIFT_COUNT_TRUNCATED
)
9748 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9750 /* If we were given an invalid count, don't do anything except exactly
9751 what was requested. */
9753 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
9758 /* Unless one of the branches of the `if' in this loop does a `continue',
9759 we will `break' the loop after the `if'. */
9763 /* If we have an operand of (clobber (const_int 0)), fail. */
9764 if (GET_CODE (varop
) == CLOBBER
)
9767 /* Convert ROTATERT to ROTATE. */
9768 if (code
== ROTATERT
)
9770 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
9772 if (VECTOR_MODE_P (result_mode
))
9773 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9775 count
= bitsize
- count
;
9778 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
9779 mode
, outer_op
, outer_const
);
9781 /* Handle cases where the count is greater than the size of the mode
9782 minus 1. For ASHIFT, use the size minus one as the count (this can
9783 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9784 take the count modulo the size. For other shifts, the result is
9787 Since these shifts are being produced by the compiler by combining
9788 multiple operations, each of which are defined, we know what the
9789 result is supposed to be. */
9791 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
9793 if (code
== ASHIFTRT
)
9794 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9795 else if (code
== ROTATE
|| code
== ROTATERT
)
9796 count
%= GET_MODE_PRECISION (shift_mode
);
9799 /* We can't simply return zero because there may be an
9807 /* If we discovered we had to complement VAROP, leave. Making a NOT
9808 here would cause an infinite loop. */
9812 /* An arithmetic right shift of a quantity known to be -1 or 0
9814 if (code
== ASHIFTRT
9815 && (num_sign_bit_copies (varop
, shift_mode
)
9816 == GET_MODE_PRECISION (shift_mode
)))
9822 /* If we are doing an arithmetic right shift and discarding all but
9823 the sign bit copies, this is equivalent to doing a shift by the
9824 bitsize minus one. Convert it into that shift because it will often
9825 allow other simplifications. */
9827 if (code
== ASHIFTRT
9828 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9829 >= GET_MODE_PRECISION (shift_mode
)))
9830 count
= GET_MODE_PRECISION (shift_mode
) - 1;
9832 /* We simplify the tests below and elsewhere by converting
9833 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9834 `make_compound_operation' will convert it to an ASHIFTRT for
9835 those machines (such as VAX) that don't have an LSHIFTRT. */
9836 if (code
== ASHIFTRT
9837 && val_signbit_known_clear_p (shift_mode
,
9838 nonzero_bits (varop
, shift_mode
)))
9841 if (((code
== LSHIFTRT
9842 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9843 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9845 && HWI_COMPUTABLE_MODE_P (shift_mode
)
9846 && !((nonzero_bits (varop
, shift_mode
) << count
)
9847 & GET_MODE_MASK (shift_mode
))))
9848 && !side_effects_p (varop
))
9851 switch (GET_CODE (varop
))
9857 new_rtx
= expand_compound_operation (varop
);
9858 if (new_rtx
!= varop
)
9866 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9867 minus the width of a smaller mode, we can do this with a
9868 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9869 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9870 && ! mode_dependent_address_p (XEXP (varop
, 0),
9871 MEM_ADDR_SPACE (varop
))
9872 && ! MEM_VOLATILE_P (varop
)
9873 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9874 MODE_INT
, 1)) != BLKmode
)
9876 new_rtx
= adjust_address_nv (varop
, tmode
,
9877 BYTES_BIG_ENDIAN
? 0
9878 : count
/ BITS_PER_UNIT
);
9880 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9881 : ZERO_EXTEND
, mode
, new_rtx
);
9888 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9889 the same number of words as what we've seen so far. Then store
9890 the widest mode in MODE. */
9891 if (subreg_lowpart_p (varop
)
9892 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9893 > GET_MODE_SIZE (GET_MODE (varop
)))
9894 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9895 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9897 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
9898 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
9900 varop
= SUBREG_REG (varop
);
9901 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9902 mode
= GET_MODE (varop
);
9908 /* Some machines use MULT instead of ASHIFT because MULT
9909 is cheaper. But it is still better on those machines to
9910 merge two shifts into one. */
9911 if (CONST_INT_P (XEXP (varop
, 1))
9912 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9915 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
9917 GEN_INT (exact_log2 (
9918 UINTVAL (XEXP (varop
, 1)))));
9924 /* Similar, for when divides are cheaper. */
9925 if (CONST_INT_P (XEXP (varop
, 1))
9926 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
9929 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
9931 GEN_INT (exact_log2 (
9932 UINTVAL (XEXP (varop
, 1)))));
9938 /* If we are extracting just the sign bit of an arithmetic
9939 right shift, that shift is not needed. However, the sign
9940 bit of a wider mode may be different from what would be
9941 interpreted as the sign bit in a narrower mode, so, if
9942 the result is narrower, don't discard the shift. */
9943 if (code
== LSHIFTRT
9944 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
9945 && (GET_MODE_BITSIZE (result_mode
)
9946 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9948 varop
= XEXP (varop
, 0);
9952 /* ... fall through ... */
9957 /* Here we have two nested shifts. The result is usually the
9958 AND of a new shift with a mask. We compute the result below. */
9959 if (CONST_INT_P (XEXP (varop
, 1))
9960 && INTVAL (XEXP (varop
, 1)) >= 0
9961 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
9962 && HWI_COMPUTABLE_MODE_P (result_mode
)
9963 && HWI_COMPUTABLE_MODE_P (mode
)
9964 && !VECTOR_MODE_P (result_mode
))
9966 enum rtx_code first_code
= GET_CODE (varop
);
9967 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9968 unsigned HOST_WIDE_INT mask
;
9971 /* We have one common special case. We can't do any merging if
9972 the inner code is an ASHIFTRT of a smaller mode. However, if
9973 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9974 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9975 we can convert it to
9976 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
9977 This simplifies certain SIGN_EXTEND operations. */
9978 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9979 && count
== (GET_MODE_PRECISION (result_mode
)
9980 - GET_MODE_PRECISION (GET_MODE (varop
))))
9982 /* C3 has the low-order C1 bits zero. */
9984 mask
= GET_MODE_MASK (mode
)
9985 & ~(((unsigned HOST_WIDE_INT
) 1 << first_count
) - 1);
9987 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9988 XEXP (varop
, 0), mask
);
9989 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9991 count
= first_count
;
9996 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9997 than C1 high-order bits equal to the sign bit, we can convert
9998 this to either an ASHIFT or an ASHIFTRT depending on the
10001 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10003 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10004 && GET_MODE (varop
) == shift_mode
10005 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10008 varop
= XEXP (varop
, 0);
10009 count
-= first_count
;
10019 /* There are some cases we can't do. If CODE is ASHIFTRT,
10020 we can only do this if FIRST_CODE is also ASHIFTRT.
10022 We can't do the case when CODE is ROTATE and FIRST_CODE is
10025 If the mode of this shift is not the mode of the outer shift,
10026 we can't do this if either shift is a right shift or ROTATE.
10028 Finally, we can't do any of these if the mode is too wide
10029 unless the codes are the same.
10031 Handle the case where the shift codes are the same
10034 if (code
== first_code
)
10036 if (GET_MODE (varop
) != result_mode
10037 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10038 || code
== ROTATE
))
10041 count
+= first_count
;
10042 varop
= XEXP (varop
, 0);
10046 if (code
== ASHIFTRT
10047 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10048 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10049 || (GET_MODE (varop
) != result_mode
10050 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10051 || first_code
== ROTATE
10052 || code
== ROTATE
)))
10055 /* To compute the mask to apply after the shift, shift the
10056 nonzero bits of the inner shift the same way the
10057 outer shift will. */
10059 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
10062 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10065 /* Give up if we can't compute an outer operation to use. */
10067 || !CONST_INT_P (mask_rtx
)
10068 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10070 result_mode
, &complement_p
))
10073 /* If the shifts are in the same direction, we add the
10074 counts. Otherwise, we subtract them. */
10075 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10076 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10077 count
+= first_count
;
10079 count
-= first_count
;
10081 /* If COUNT is positive, the new shift is usually CODE,
10082 except for the two exceptions below, in which case it is
10083 FIRST_CODE. If the count is negative, FIRST_CODE should
10086 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10087 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10089 else if (count
< 0)
10090 code
= first_code
, count
= -count
;
10092 varop
= XEXP (varop
, 0);
10096 /* If we have (A << B << C) for any shift, we can convert this to
10097 (A << C << B). This wins if A is a constant. Only try this if
10098 B is not a constant. */
10100 else if (GET_CODE (varop
) == code
10101 && CONST_INT_P (XEXP (varop
, 0))
10102 && !CONST_INT_P (XEXP (varop
, 1)))
10104 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10107 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10114 if (VECTOR_MODE_P (mode
))
10117 /* Make this fit the case below. */
10118 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10124 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10125 with C the size of VAROP - 1 and the shift is logical if
10126 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10127 we have an (le X 0) operation. If we have an arithmetic shift
10128 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10129 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10131 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10132 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10133 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10134 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10135 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10136 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10139 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10142 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10143 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10148 /* If we have (shift (logical)), move the logical to the outside
10149 to allow it to possibly combine with another logical and the
10150 shift to combine with another shift. This also canonicalizes to
10151 what a ZERO_EXTRACT looks like. Also, some machines have
10152 (and (shift)) insns. */
10154 if (CONST_INT_P (XEXP (varop
, 1))
10155 /* We can't do this if we have (ashiftrt (xor)) and the
10156 constant has its sign bit set in shift_mode. */
10157 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10158 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10160 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10162 GEN_INT (count
))) != 0
10163 && CONST_INT_P (new_rtx
)
10164 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10165 INTVAL (new_rtx
), result_mode
, &complement_p
))
10167 varop
= XEXP (varop
, 0);
10171 /* If we can't do that, try to simplify the shift in each arm of the
10172 logical expression, make a new logical expression, and apply
10173 the inverse distributive law. This also can't be done
10174 for some (ashiftrt (xor)). */
10175 if (CONST_INT_P (XEXP (varop
, 1))
10176 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10177 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10180 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10181 XEXP (varop
, 0), count
);
10182 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10183 XEXP (varop
, 1), count
);
10185 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10187 varop
= apply_distributive_law (varop
);
10195 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10196 says that the sign bit can be tested, FOO has mode MODE, C is
10197 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10198 that may be nonzero. */
10199 if (code
== LSHIFTRT
10200 && XEXP (varop
, 1) == const0_rtx
10201 && GET_MODE (XEXP (varop
, 0)) == result_mode
10202 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10203 && HWI_COMPUTABLE_MODE_P (result_mode
)
10204 && STORE_FLAG_VALUE
== -1
10205 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10206 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10209 varop
= XEXP (varop
, 0);
10216 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10217 than the number of bits in the mode is equivalent to A. */
10218 if (code
== LSHIFTRT
10219 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10220 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10222 varop
= XEXP (varop
, 0);
10227 /* NEG commutes with ASHIFT since it is multiplication. Move the
10228 NEG outside to allow shifts to combine. */
10230 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10233 varop
= XEXP (varop
, 0);
10239 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10240 is one less than the number of bits in the mode is
10241 equivalent to (xor A 1). */
10242 if (code
== LSHIFTRT
10243 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10244 && XEXP (varop
, 1) == constm1_rtx
10245 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10246 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10250 varop
= XEXP (varop
, 0);
10254 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10255 that might be nonzero in BAR are those being shifted out and those
10256 bits are known zero in FOO, we can replace the PLUS with FOO.
10257 Similarly in the other operand order. This code occurs when
10258 we are computing the size of a variable-size array. */
10260 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10261 && count
< HOST_BITS_PER_WIDE_INT
10262 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10263 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10264 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10266 varop
= XEXP (varop
, 0);
10269 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10270 && count
< HOST_BITS_PER_WIDE_INT
10271 && HWI_COMPUTABLE_MODE_P (result_mode
)
10272 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10274 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10275 & nonzero_bits (XEXP (varop
, 1),
10278 varop
= XEXP (varop
, 1);
10282 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10284 && CONST_INT_P (XEXP (varop
, 1))
10285 && (new_rtx
= simplify_const_binary_operation (ASHIFT
, result_mode
,
10287 GEN_INT (count
))) != 0
10288 && CONST_INT_P (new_rtx
)
10289 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10290 INTVAL (new_rtx
), result_mode
, &complement_p
))
10292 varop
= XEXP (varop
, 0);
10296 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10297 signbit', and attempt to change the PLUS to an XOR and move it to
10298 the outer operation as is done above in the AND/IOR/XOR case
10299 leg for shift(logical). See details in logical handling above
10300 for reasoning in doing so. */
10301 if (code
== LSHIFTRT
10302 && CONST_INT_P (XEXP (varop
, 1))
10303 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10304 && (new_rtx
= simplify_const_binary_operation (code
, result_mode
,
10306 GEN_INT (count
))) != 0
10307 && CONST_INT_P (new_rtx
)
10308 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10309 INTVAL (new_rtx
), result_mode
, &complement_p
))
10311 varop
= XEXP (varop
, 0);
10318 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10319 with C the size of VAROP - 1 and the shift is logical if
10320 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10321 we have a (gt X 0) operation. If the shift is arithmetic with
10322 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10323 we have a (neg (gt X 0)) operation. */
10325 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10326 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10327 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10328 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10329 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10330 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10331 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10334 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10337 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10338 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10345 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10346 if the truncate does not affect the value. */
10347 if (code
== LSHIFTRT
10348 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10349 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10350 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10351 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10352 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10354 rtx varop_inner
= XEXP (varop
, 0);
10357 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10358 XEXP (varop_inner
, 0),
10360 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10361 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10374 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10375 outer_op
, outer_const
);
10377 /* We have now finished analyzing the shift. The result should be
10378 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10379 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10380 to the result of the shift. OUTER_CONST is the relevant constant,
10381 but we must turn off all bits turned off in the shift. */
10383 if (outer_op
== UNKNOWN
10384 && orig_code
== code
&& orig_count
== count
10385 && varop
== orig_varop
10386 && shift_mode
== GET_MODE (varop
))
10389 /* Make a SUBREG if necessary. If we can't make it, fail. */
10390 varop
= gen_lowpart (shift_mode
, varop
);
10391 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10394 /* If we have an outer operation and we just made a shift, it is
10395 possible that we could have simplified the shift were it not
10396 for the outer operation. So try to do the simplification
10399 if (outer_op
!= UNKNOWN
)
10400 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10405 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10407 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10408 turn off all the bits that the shift would have turned off. */
10409 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10410 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10411 GET_MODE_MASK (result_mode
) >> orig_count
);
10413 /* Do the remainder of the processing in RESULT_MODE. */
10414 x
= gen_lowpart_or_truncate (result_mode
, x
);
10416 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10419 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10421 if (outer_op
!= UNKNOWN
)
10423 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10424 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10425 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10427 if (outer_op
== AND
)
10428 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10429 else if (outer_op
== SET
)
10431 /* This means that we have determined that the result is
10432 equivalent to a constant. This should be rare. */
10433 if (!side_effects_p (x
))
10434 x
= GEN_INT (outer_const
);
10436 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10437 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10439 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10440 GEN_INT (outer_const
));
10446 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10447 The result of the shift is RESULT_MODE. If we cannot simplify it,
10448 return X or, if it is NULL, synthesize the expression with
10449 simplify_gen_binary. Otherwise, return a simplified value.
10451 The shift is normally computed in the widest mode we find in VAROP, as
10452 long as it isn't a different number of words than RESULT_MODE. Exceptions
10453 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10456 simplify_shift_const (rtx x
, enum rtx_code code
, enum machine_mode result_mode
,
10457 rtx varop
, int count
)
10459 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10464 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10465 if (GET_MODE (x
) != result_mode
)
10466 x
= gen_lowpart (result_mode
, x
);
10471 /* Like recog, but we receive the address of a pointer to a new pattern.
10472 We try to match the rtx that the pointer points to.
10473 If that fails, we may try to modify or replace the pattern,
10474 storing the replacement into the same pointer object.
10476 Modifications include deletion or addition of CLOBBERs.
10478 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10479 the CLOBBERs are placed.
10481 The value is the final insn code from the pattern ultimately matched,
10485 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
10487 rtx pat
= *pnewpat
;
10488 rtx pat_without_clobbers
;
10489 int insn_code_number
;
10490 int num_clobbers_to_add
= 0;
10492 rtx notes
= NULL_RTX
;
10493 rtx old_notes
, old_pat
;
10496 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10497 we use to indicate that something didn't match. If we find such a
10498 thing, force rejection. */
10499 if (GET_CODE (pat
) == PARALLEL
)
10500 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10501 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10502 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10505 old_pat
= PATTERN (insn
);
10506 old_notes
= REG_NOTES (insn
);
10507 PATTERN (insn
) = pat
;
10508 REG_NOTES (insn
) = NULL_RTX
;
10510 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10511 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10513 if (insn_code_number
< 0)
10514 fputs ("Failed to match this instruction:\n", dump_file
);
10516 fputs ("Successfully matched this instruction:\n", dump_file
);
10517 print_rtl_single (dump_file
, pat
);
10520 /* If it isn't, there is the possibility that we previously had an insn
10521 that clobbered some register as a side effect, but the combined
10522 insn doesn't need to do that. So try once more without the clobbers
10523 unless this represents an ASM insn. */
10525 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10526 && GET_CODE (pat
) == PARALLEL
)
10530 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
10531 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
10534 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
10538 SUBST_INT (XVECLEN (pat
, 0), pos
);
10541 pat
= XVECEXP (pat
, 0, 0);
10543 PATTERN (insn
) = pat
;
10544 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10545 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10547 if (insn_code_number
< 0)
10548 fputs ("Failed to match this instruction:\n", dump_file
);
10550 fputs ("Successfully matched this instruction:\n", dump_file
);
10551 print_rtl_single (dump_file
, pat
);
10555 pat_without_clobbers
= pat
;
10557 PATTERN (insn
) = old_pat
;
10558 REG_NOTES (insn
) = old_notes
;
10560 /* Recognize all noop sets, these will be killed by followup pass. */
10561 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
10562 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
10564 /* If we had any clobbers to add, make a new pattern than contains
10565 them. Then check to make sure that all of them are dead. */
10566 if (num_clobbers_to_add
)
10568 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
10569 rtvec_alloc (GET_CODE (pat
) == PARALLEL
10570 ? (XVECLEN (pat
, 0)
10571 + num_clobbers_to_add
)
10572 : num_clobbers_to_add
+ 1));
10574 if (GET_CODE (pat
) == PARALLEL
)
10575 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
10576 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
10578 XVECEXP (newpat
, 0, 0) = pat
;
10580 add_clobbers (newpat
, insn_code_number
);
10582 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
10583 i
< XVECLEN (newpat
, 0); i
++)
10585 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
10586 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
10588 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
10590 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
10591 notes
= alloc_reg_note (REG_UNUSED
,
10592 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
10598 if (insn_code_number
>= 0
10599 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
10601 old_pat
= PATTERN (insn
);
10602 old_notes
= REG_NOTES (insn
);
10603 old_icode
= INSN_CODE (insn
);
10604 PATTERN (insn
) = pat
;
10605 REG_NOTES (insn
) = notes
;
10607 /* Allow targets to reject combined insn. */
10608 if (!targetm
.legitimate_combined_insn (insn
))
10610 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10611 fputs ("Instruction not appropriate for target.",
10614 /* Callers expect recog_for_combine to strip
10615 clobbers from the pattern on failure. */
10616 pat
= pat_without_clobbers
;
10619 insn_code_number
= -1;
10622 PATTERN (insn
) = old_pat
;
10623 REG_NOTES (insn
) = old_notes
;
10624 INSN_CODE (insn
) = old_icode
;
10630 return insn_code_number
;
10633 /* Like gen_lowpart_general but for use by combine. In combine it
10634 is not possible to create any new pseudoregs. However, it is
10635 safe to create invalid memory addresses, because combine will
10636 try to recognize them and all they will do is make the combine
10639 If for some reason this cannot do its job, an rtx
10640 (clobber (const_int 0)) is returned.
10641 An insn containing that will not be recognized. */
10644 gen_lowpart_for_combine (enum machine_mode omode
, rtx x
)
10646 enum machine_mode imode
= GET_MODE (x
);
10647 unsigned int osize
= GET_MODE_SIZE (omode
);
10648 unsigned int isize
= GET_MODE_SIZE (imode
);
10651 if (omode
== imode
)
10654 /* We can only support MODE being wider than a word if X is a
10655 constant integer or has a mode the same size. */
10656 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
10657 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
10660 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10661 won't know what to do. So we will strip off the SUBREG here and
10662 process normally. */
10663 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
10665 x
= SUBREG_REG (x
);
10667 /* For use in case we fall down into the address adjustments
10668 further below, we need to adjust the known mode and size of
10669 x; imode and isize, since we just adjusted x. */
10670 imode
= GET_MODE (x
);
10672 if (imode
== omode
)
10675 isize
= GET_MODE_SIZE (imode
);
10678 result
= gen_lowpart_common (omode
, x
);
10687 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10689 if (MEM_VOLATILE_P (x
)
10690 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
10693 /* If we want to refer to something bigger than the original memref,
10694 generate a paradoxical subreg instead. That will force a reload
10695 of the original memref X. */
10697 return gen_rtx_SUBREG (omode
, x
, 0);
10699 if (WORDS_BIG_ENDIAN
)
10700 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
10702 /* Adjust the address so that the address-after-the-data is
10704 if (BYTES_BIG_ENDIAN
)
10705 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
10707 return adjust_address_nv (x
, omode
, offset
);
10710 /* If X is a comparison operator, rewrite it in a new mode. This
10711 probably won't match, but may allow further simplifications. */
10712 else if (COMPARISON_P (x
))
10713 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
10715 /* If we couldn't simplify X any other way, just enclose it in a
10716 SUBREG. Normally, this SUBREG won't match, but some patterns may
10717 include an explicit SUBREG or we may simplify it further in combine. */
10723 offset
= subreg_lowpart_offset (omode
, imode
);
10724 if (imode
== VOIDmode
)
10726 imode
= int_mode_for_mode (omode
);
10727 x
= gen_lowpart_common (imode
, x
);
10731 res
= simplify_gen_subreg (omode
, x
, imode
, offset
);
10737 return gen_rtx_CLOBBER (omode
, const0_rtx
);
10740 /* Try to simplify a comparison between OP0 and a constant OP1,
10741 where CODE is the comparison code that will be tested, into a
10742 (CODE OP0 const0_rtx) form.
10744 The result is a possibly different comparison code to use.
10745 *POP1 may be updated. */
10747 static enum rtx_code
10748 simplify_compare_const (enum rtx_code code
, rtx op0
, rtx
*pop1
)
10750 enum machine_mode mode
= GET_MODE (op0
);
10751 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
10752 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
10754 /* Get the constant we are comparing against and turn off all bits
10755 not on in our mode. */
10756 if (mode
!= VOIDmode
)
10757 const_op
= trunc_int_for_mode (const_op
, mode
);
10759 /* If we are comparing against a constant power of two and the value
10760 being compared can only have that single bit nonzero (e.g., it was
10761 `and'ed with that bit), we can replace this with a comparison
10764 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10765 || code
== LT
|| code
== LTU
)
10766 && mode_width
<= HOST_BITS_PER_WIDE_INT
10767 && exact_log2 (const_op
) >= 0
10768 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10770 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10774 /* Similarly, if we are comparing a value known to be either -1 or
10775 0 with -1, change it to the opposite comparison against zero. */
10777 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10778 || code
== GEU
|| code
== LTU
)
10779 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10781 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10785 /* Do some canonicalizations based on the comparison code. We prefer
10786 comparisons against zero and then prefer equality comparisons.
10787 If we can reduce the size of a constant, we will do that too. */
10791 /* < C is equivalent to <= (C - 1) */
10796 /* ... fall through to LE case below. */
10802 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10809 /* If we are doing a <= 0 comparison on a value known to have
10810 a zero sign bit, we can replace this with == 0. */
10811 else if (const_op
== 0
10812 && mode_width
<= HOST_BITS_PER_WIDE_INT
10813 && (nonzero_bits (op0
, mode
)
10814 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10820 /* >= C is equivalent to > (C - 1). */
10825 /* ... fall through to GT below. */
10831 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10838 /* If we are doing a > 0 comparison on a value known to have
10839 a zero sign bit, we can replace this with != 0. */
10840 else if (const_op
== 0
10841 && mode_width
<= HOST_BITS_PER_WIDE_INT
10842 && (nonzero_bits (op0
, mode
)
10843 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10849 /* < C is equivalent to <= (C - 1). */
10854 /* ... fall through ... */
10856 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10857 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10858 && (unsigned HOST_WIDE_INT
) const_op
10859 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10869 /* unsigned <= 0 is equivalent to == 0 */
10872 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10873 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10874 && (unsigned HOST_WIDE_INT
) const_op
10875 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10883 /* >= C is equivalent to > (C - 1). */
10888 /* ... fall through ... */
10891 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10892 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10893 && (unsigned HOST_WIDE_INT
) const_op
10894 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1))
10904 /* unsigned > 0 is equivalent to != 0 */
10907 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10908 else if (mode_width
<= HOST_BITS_PER_WIDE_INT
10909 && (unsigned HOST_WIDE_INT
) const_op
10910 == ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1)
10921 *pop1
= GEN_INT (const_op
);
10925 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10926 comparison code that will be tested.
10928 The result is a possibly different comparison code to use. *POP0 and
10929 *POP1 may be updated.
10931 It is possible that we might detect that a comparison is either always
10932 true or always false. However, we do not perform general constant
10933 folding in combine, so this knowledge isn't useful. Such tautologies
10934 should have been detected earlier. Hence we ignore all such cases. */
10936 static enum rtx_code
10937 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10943 enum machine_mode mode
, tmode
;
10945 /* Try a few ways of applying the same transformation to both operands. */
10948 #ifndef WORD_REGISTER_OPERATIONS
10949 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10950 so check specially. */
10951 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10952 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10953 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10954 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10955 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10956 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10957 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10958 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10959 && CONST_INT_P (XEXP (op0
, 1))
10960 && XEXP (op0
, 1) == XEXP (op1
, 1)
10961 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10962 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10963 && (INTVAL (XEXP (op0
, 1))
10964 == (GET_MODE_PRECISION (GET_MODE (op0
))
10965 - (GET_MODE_PRECISION
10966 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10968 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10969 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10973 /* If both operands are the same constant shift, see if we can ignore the
10974 shift. We can if the shift is a rotate or if the bits shifted out of
10975 this shift are known to be zero for both inputs and if the type of
10976 comparison is compatible with the shift. */
10977 if (GET_CODE (op0
) == GET_CODE (op1
)
10978 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0
))
10979 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10980 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10981 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10982 || (GET_CODE (op0
) == ASHIFTRT
10983 && (code
!= GTU
&& code
!= LTU
10984 && code
!= GEU
&& code
!= LEU
)))
10985 && CONST_INT_P (XEXP (op0
, 1))
10986 && INTVAL (XEXP (op0
, 1)) >= 0
10987 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10988 && XEXP (op0
, 1) == XEXP (op1
, 1))
10990 enum machine_mode mode
= GET_MODE (op0
);
10991 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10992 int shift_count
= INTVAL (XEXP (op0
, 1));
10994 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10995 mask
&= (mask
>> shift_count
) << shift_count
;
10996 else if (GET_CODE (op0
) == ASHIFT
)
10997 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10999 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11000 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11001 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11006 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11007 SUBREGs are of the same mode, and, in both cases, the AND would
11008 be redundant if the comparison was done in the narrower mode,
11009 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11010 and the operand's possibly nonzero bits are 0xffffff01; in that case
11011 if we only care about QImode, we don't need the AND). This case
11012 occurs if the output mode of an scc insn is not SImode and
11013 STORE_FLAG_VALUE == 1 (e.g., the 386).
11015 Similarly, check for a case where the AND's are ZERO_EXTEND
11016 operations from some narrower mode even though a SUBREG is not
11019 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11020 && CONST_INT_P (XEXP (op0
, 1))
11021 && CONST_INT_P (XEXP (op1
, 1)))
11023 rtx inner_op0
= XEXP (op0
, 0);
11024 rtx inner_op1
= XEXP (op1
, 0);
11025 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11026 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11029 if (paradoxical_subreg_p (inner_op0
)
11030 && GET_CODE (inner_op1
) == SUBREG
11031 && (GET_MODE (SUBREG_REG (inner_op0
))
11032 == GET_MODE (SUBREG_REG (inner_op1
)))
11033 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11034 <= HOST_BITS_PER_WIDE_INT
)
11035 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11036 GET_MODE (SUBREG_REG (inner_op0
)))))
11037 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11038 GET_MODE (SUBREG_REG (inner_op1
))))))
11040 op0
= SUBREG_REG (inner_op0
);
11041 op1
= SUBREG_REG (inner_op1
);
11043 /* The resulting comparison is always unsigned since we masked
11044 off the original sign bit. */
11045 code
= unsigned_condition (code
);
11051 for (tmode
= GET_CLASS_NARROWEST_MODE
11052 (GET_MODE_CLASS (GET_MODE (op0
)));
11053 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11054 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11056 op0
= gen_lowpart (tmode
, inner_op0
);
11057 op1
= gen_lowpart (tmode
, inner_op1
);
11058 code
= unsigned_condition (code
);
11067 /* If both operands are NOT, we can strip off the outer operation
11068 and adjust the comparison code for swapped operands; similarly for
11069 NEG, except that this must be an equality comparison. */
11070 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11071 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11072 && (code
== EQ
|| code
== NE
)))
11073 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11079 /* If the first operand is a constant, swap the operands and adjust the
11080 comparison code appropriately, but don't do this if the second operand
11081 is already a constant integer. */
11082 if (swap_commutative_operands_p (op0
, op1
))
11084 tem
= op0
, op0
= op1
, op1
= tem
;
11085 code
= swap_condition (code
);
11088 /* We now enter a loop during which we will try to simplify the comparison.
11089 For the most part, we only are concerned with comparisons with zero,
11090 but some things may really be comparisons with zero but not start
11091 out looking that way. */
11093 while (CONST_INT_P (op1
))
11095 enum machine_mode mode
= GET_MODE (op0
);
11096 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11097 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11098 int equality_comparison_p
;
11099 int sign_bit_comparison_p
;
11100 int unsigned_comparison_p
;
11101 HOST_WIDE_INT const_op
;
11103 /* We only want to handle integral modes. This catches VOIDmode,
11104 CCmode, and the floating-point modes. An exception is that we
11105 can handle VOIDmode if OP0 is a COMPARE or a comparison
11108 if (GET_MODE_CLASS (mode
) != MODE_INT
11109 && ! (mode
== VOIDmode
11110 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11113 /* Try to simplify the compare to constant, possibly changing the
11114 comparison op, and/or changing op1 to zero. */
11115 code
= simplify_compare_const (code
, op0
, &op1
);
11116 const_op
= INTVAL (op1
);
11118 /* Compute some predicates to simplify code below. */
11120 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11121 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11122 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11125 /* If this is a sign bit comparison and we can do arithmetic in
11126 MODE, say that we will only be needing the sign bit of OP0. */
11127 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11128 op0
= force_to_mode (op0
, mode
,
11129 (unsigned HOST_WIDE_INT
) 1
11130 << (GET_MODE_PRECISION (mode
) - 1),
11133 /* Now try cases based on the opcode of OP0. If none of the cases
11134 does a "continue", we exit this loop immediately after the
11137 switch (GET_CODE (op0
))
11140 /* If we are extracting a single bit from a variable position in
11141 a constant that has only a single bit set and are comparing it
11142 with zero, we can convert this into an equality comparison
11143 between the position and the location of the single bit. */
11144 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11145 have already reduced the shift count modulo the word size. */
11146 if (!SHIFT_COUNT_TRUNCATED
11147 && CONST_INT_P (XEXP (op0
, 0))
11148 && XEXP (op0
, 1) == const1_rtx
11149 && equality_comparison_p
&& const_op
== 0
11150 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11152 if (BITS_BIG_ENDIAN
)
11153 i
= BITS_PER_WORD
- 1 - i
;
11155 op0
= XEXP (op0
, 2);
11159 /* Result is nonzero iff shift count is equal to I. */
11160 code
= reverse_condition (code
);
11164 /* ... fall through ... */
11167 tem
= expand_compound_operation (op0
);
11176 /* If testing for equality, we can take the NOT of the constant. */
11177 if (equality_comparison_p
11178 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11180 op0
= XEXP (op0
, 0);
11185 /* If just looking at the sign bit, reverse the sense of the
11187 if (sign_bit_comparison_p
)
11189 op0
= XEXP (op0
, 0);
11190 code
= (code
== GE
? LT
: GE
);
11196 /* If testing for equality, we can take the NEG of the constant. */
11197 if (equality_comparison_p
11198 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11200 op0
= XEXP (op0
, 0);
11205 /* The remaining cases only apply to comparisons with zero. */
11209 /* When X is ABS or is known positive,
11210 (neg X) is < 0 if and only if X != 0. */
11212 if (sign_bit_comparison_p
11213 && (GET_CODE (XEXP (op0
, 0)) == ABS
11214 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11215 && (nonzero_bits (XEXP (op0
, 0), mode
)
11216 & ((unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11219 op0
= XEXP (op0
, 0);
11220 code
= (code
== LT
? NE
: EQ
);
11224 /* If we have NEG of something whose two high-order bits are the
11225 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11226 if (num_sign_bit_copies (op0
, mode
) >= 2)
11228 op0
= XEXP (op0
, 0);
11229 code
= swap_condition (code
);
11235 /* If we are testing equality and our count is a constant, we
11236 can perform the inverse operation on our RHS. */
11237 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11238 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11239 op1
, XEXP (op0
, 1))) != 0)
11241 op0
= XEXP (op0
, 0);
11246 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11247 a particular bit. Convert it to an AND of a constant of that
11248 bit. This will be converted into a ZERO_EXTRACT. */
11249 if (const_op
== 0 && sign_bit_comparison_p
11250 && CONST_INT_P (XEXP (op0
, 1))
11251 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11253 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11254 ((unsigned HOST_WIDE_INT
) 1
11256 - INTVAL (XEXP (op0
, 1)))));
11257 code
= (code
== LT
? NE
: EQ
);
11261 /* Fall through. */
11264 /* ABS is ignorable inside an equality comparison with zero. */
11265 if (const_op
== 0 && equality_comparison_p
)
11267 op0
= XEXP (op0
, 0);
11273 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11274 (compare FOO CONST) if CONST fits in FOO's mode and we
11275 are either testing inequality or have an unsigned
11276 comparison with ZERO_EXTEND or a signed comparison with
11277 SIGN_EXTEND. But don't do it if we don't have a compare
11278 insn of the given mode, since we'd have to revert it
11279 later on, and then we wouldn't know whether to sign- or
11281 mode
= GET_MODE (XEXP (op0
, 0));
11282 if (GET_MODE_CLASS (mode
) == MODE_INT
11283 && ! unsigned_comparison_p
11284 && HWI_COMPUTABLE_MODE_P (mode
)
11285 && trunc_int_for_mode (const_op
, mode
) == const_op
11286 && have_insn_for (COMPARE
, mode
))
11288 op0
= XEXP (op0
, 0);
11294 /* Check for the case where we are comparing A - C1 with C2, that is
11296 (subreg:MODE (plus (A) (-C1))) op (C2)
11298 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11299 comparison in the wider mode. One of the following two conditions
11300 must be true in order for this to be valid:
11302 1. The mode extension results in the same bit pattern being added
11303 on both sides and the comparison is equality or unsigned. As
11304 C2 has been truncated to fit in MODE, the pattern can only be
11307 2. The mode extension results in the sign bit being copied on
11310 The difficulty here is that we have predicates for A but not for
11311 (A - C1) so we need to check that C1 is within proper bounds so
11312 as to perturbate A as little as possible. */
11314 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11315 && subreg_lowpart_p (op0
)
11316 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11317 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11318 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11320 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11321 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11322 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11325 && (unsigned HOST_WIDE_INT
) c1
11326 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)
11327 && (equality_comparison_p
|| unsigned_comparison_p
)
11328 /* (A - C1) zero-extends if it is positive and sign-extends
11329 if it is negative, C2 both zero- and sign-extends. */
11330 && ((0 == (nonzero_bits (a
, inner_mode
)
11331 & ~GET_MODE_MASK (mode
))
11333 /* (A - C1) sign-extends if it is positive and 1-extends
11334 if it is negative, C2 both sign- and 1-extends. */
11335 || (num_sign_bit_copies (a
, inner_mode
)
11336 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11339 || ((unsigned HOST_WIDE_INT
) c1
11340 < (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 2)
11341 /* (A - C1) always sign-extends, like C2. */
11342 && num_sign_bit_copies (a
, inner_mode
)
11343 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11344 - (mode_width
- 1))))
11346 op0
= SUBREG_REG (op0
);
11351 /* If the inner mode is narrower and we are extracting the low part,
11352 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11353 if (subreg_lowpart_p (op0
)
11354 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11355 /* Fall through */ ;
11359 /* ... fall through ... */
11362 mode
= GET_MODE (XEXP (op0
, 0));
11363 if (GET_MODE_CLASS (mode
) == MODE_INT
11364 && (unsigned_comparison_p
|| equality_comparison_p
)
11365 && HWI_COMPUTABLE_MODE_P (mode
)
11366 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11368 && have_insn_for (COMPARE
, mode
))
11370 op0
= XEXP (op0
, 0);
11376 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11377 this for equality comparisons due to pathological cases involving
11379 if (equality_comparison_p
11380 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11381 op1
, XEXP (op0
, 1))))
11383 op0
= XEXP (op0
, 0);
11388 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11389 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11390 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11392 op0
= XEXP (XEXP (op0
, 0), 0);
11393 code
= (code
== LT
? EQ
: NE
);
11399 /* We used to optimize signed comparisons against zero, but that
11400 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11401 arrive here as equality comparisons, or (GEU, LTU) are
11402 optimized away. No need to special-case them. */
11404 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11405 (eq B (minus A C)), whichever simplifies. We can only do
11406 this for equality comparisons due to pathological cases involving
11408 if (equality_comparison_p
11409 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11410 XEXP (op0
, 1), op1
)))
11412 op0
= XEXP (op0
, 0);
11417 if (equality_comparison_p
11418 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11419 XEXP (op0
, 0), op1
)))
11421 op0
= XEXP (op0
, 1);
11426 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11427 of bits in X minus 1, is one iff X > 0. */
11428 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
11429 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11430 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
11431 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11433 op0
= XEXP (op0
, 1);
11434 code
= (code
== GE
? LE
: GT
);
11440 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11441 if C is zero or B is a constant. */
11442 if (equality_comparison_p
11443 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
11444 XEXP (op0
, 1), op1
)))
11446 op0
= XEXP (op0
, 0);
11453 case UNEQ
: case LTGT
:
11454 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
11455 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
11456 case UNORDERED
: case ORDERED
:
11457 /* We can't do anything if OP0 is a condition code value, rather
11458 than an actual data value. */
11460 || CC0_P (XEXP (op0
, 0))
11461 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
11464 /* Get the two operands being compared. */
11465 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
11466 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
11468 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
11470 /* Check for the cases where we simply want the result of the
11471 earlier test or the opposite of that result. */
11472 if (code
== NE
|| code
== EQ
11473 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
11474 && (code
== LT
|| code
== GE
)))
11476 enum rtx_code new_code
;
11477 if (code
== LT
|| code
== NE
)
11478 new_code
= GET_CODE (op0
);
11480 new_code
= reversed_comparison_code (op0
, NULL
);
11482 if (new_code
!= UNKNOWN
)
11493 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11495 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
11496 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
11497 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
11499 op0
= XEXP (op0
, 1);
11500 code
= (code
== GE
? GT
: LE
);
11506 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11507 will be converted to a ZERO_EXTRACT later. */
11508 if (const_op
== 0 && equality_comparison_p
11509 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11510 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
11512 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
11513 XEXP (XEXP (op0
, 0), 1));
11514 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11518 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11519 zero and X is a comparison and C1 and C2 describe only bits set
11520 in STORE_FLAG_VALUE, we can compare with X. */
11521 if (const_op
== 0 && equality_comparison_p
11522 && mode_width
<= HOST_BITS_PER_WIDE_INT
11523 && CONST_INT_P (XEXP (op0
, 1))
11524 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
11525 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11526 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
11527 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
11529 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11530 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
11531 if ((~STORE_FLAG_VALUE
& mask
) == 0
11532 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
11533 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
11534 && COMPARISON_P (tem
))))
11536 op0
= XEXP (XEXP (op0
, 0), 0);
11541 /* If we are doing an equality comparison of an AND of a bit equal
11542 to the sign bit, replace this with a LT or GE comparison of
11543 the underlying value. */
11544 if (equality_comparison_p
11546 && CONST_INT_P (XEXP (op0
, 1))
11547 && mode_width
<= HOST_BITS_PER_WIDE_INT
11548 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
11549 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
11551 op0
= XEXP (op0
, 0);
11552 code
= (code
== EQ
? GE
: LT
);
11556 /* If this AND operation is really a ZERO_EXTEND from a narrower
11557 mode, the constant fits within that mode, and this is either an
11558 equality or unsigned comparison, try to do this comparison in
11563 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11564 -> (ne:DI (reg:SI 4) (const_int 0))
11566 unless TRULY_NOOP_TRUNCATION allows it or the register is
11567 known to hold a value of the required mode the
11568 transformation is invalid. */
11569 if ((equality_comparison_p
|| unsigned_comparison_p
)
11570 && CONST_INT_P (XEXP (op0
, 1))
11571 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
11572 & GET_MODE_MASK (mode
))
11574 && const_op
>> i
== 0
11575 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
11576 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode
, GET_MODE (op0
))
11577 || (REG_P (XEXP (op0
, 0))
11578 && reg_truncated_to_mode (tmode
, XEXP (op0
, 0)))))
11580 op0
= gen_lowpart (tmode
, XEXP (op0
, 0));
11584 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11585 fits in both M1 and M2 and the SUBREG is either paradoxical
11586 or represents the low part, permute the SUBREG and the AND
11588 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
11590 unsigned HOST_WIDE_INT c1
;
11591 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
11592 /* Require an integral mode, to avoid creating something like
11594 if (SCALAR_INT_MODE_P (tmode
)
11595 /* It is unsafe to commute the AND into the SUBREG if the
11596 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11597 not defined. As originally written the upper bits
11598 have a defined value due to the AND operation.
11599 However, if we commute the AND inside the SUBREG then
11600 they no longer have defined values and the meaning of
11601 the code has been changed. */
11603 #ifdef WORD_REGISTER_OPERATIONS
11604 || (mode_width
> GET_MODE_PRECISION (tmode
)
11605 && mode_width
<= BITS_PER_WORD
)
11607 || (mode_width
<= GET_MODE_PRECISION (tmode
)
11608 && subreg_lowpart_p (XEXP (op0
, 0))))
11609 && CONST_INT_P (XEXP (op0
, 1))
11610 && mode_width
<= HOST_BITS_PER_WIDE_INT
11611 && HWI_COMPUTABLE_MODE_P (tmode
)
11612 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
11613 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
11615 && c1
!= GET_MODE_MASK (tmode
))
11617 op0
= simplify_gen_binary (AND
, tmode
,
11618 SUBREG_REG (XEXP (op0
, 0)),
11619 gen_int_mode (c1
, tmode
));
11620 op0
= gen_lowpart (mode
, op0
);
11625 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11626 if (const_op
== 0 && equality_comparison_p
11627 && XEXP (op0
, 1) == const1_rtx
11628 && GET_CODE (XEXP (op0
, 0)) == NOT
)
11630 op0
= simplify_and_const_int (NULL_RTX
, mode
,
11631 XEXP (XEXP (op0
, 0), 0), 1);
11632 code
= (code
== NE
? EQ
: NE
);
11636 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11637 (eq (and (lshiftrt X) 1) 0).
11638 Also handle the case where (not X) is expressed using xor. */
11639 if (const_op
== 0 && equality_comparison_p
11640 && XEXP (op0
, 1) == const1_rtx
11641 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
11643 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
11644 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
11646 if (GET_CODE (shift_op
) == NOT
11647 || (GET_CODE (shift_op
) == XOR
11648 && CONST_INT_P (XEXP (shift_op
, 1))
11649 && CONST_INT_P (shift_count
)
11650 && HWI_COMPUTABLE_MODE_P (mode
)
11651 && (UINTVAL (XEXP (shift_op
, 1))
11652 == (unsigned HOST_WIDE_INT
) 1
11653 << INTVAL (shift_count
))))
11656 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
11657 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
11658 code
= (code
== NE
? EQ
: NE
);
11665 /* If we have (compare (ashift FOO N) (const_int C)) and
11666 the high order N bits of FOO (N+1 if an inequality comparison)
11667 are known to be zero, we can do this by comparing FOO with C
11668 shifted right N bits so long as the low-order N bits of C are
11670 if (CONST_INT_P (XEXP (op0
, 1))
11671 && INTVAL (XEXP (op0
, 1)) >= 0
11672 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11673 < HOST_BITS_PER_WIDE_INT
)
11674 && (((unsigned HOST_WIDE_INT
) const_op
11675 & (((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1)))
11677 && mode_width
<= HOST_BITS_PER_WIDE_INT
11678 && (nonzero_bits (XEXP (op0
, 0), mode
)
11679 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11680 + ! equality_comparison_p
))) == 0)
11682 /* We must perform a logical shift, not an arithmetic one,
11683 as we want the top N bits of C to be zero. */
11684 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11686 temp
>>= INTVAL (XEXP (op0
, 1));
11687 op1
= gen_int_mode (temp
, mode
);
11688 op0
= XEXP (op0
, 0);
11692 /* If we are doing a sign bit comparison, it means we are testing
11693 a particular bit. Convert it to the appropriate AND. */
11694 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11695 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11697 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11698 ((unsigned HOST_WIDE_INT
) 1
11700 - INTVAL (XEXP (op0
, 1)))));
11701 code
= (code
== LT
? NE
: EQ
);
11705 /* If this an equality comparison with zero and we are shifting
11706 the low bit to the sign bit, we can convert this to an AND of the
11708 if (const_op
== 0 && equality_comparison_p
11709 && CONST_INT_P (XEXP (op0
, 1))
11710 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11712 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
11718 /* If this is an equality comparison with zero, we can do this
11719 as a logical shift, which might be much simpler. */
11720 if (equality_comparison_p
&& const_op
== 0
11721 && CONST_INT_P (XEXP (op0
, 1)))
11723 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11725 INTVAL (XEXP (op0
, 1)));
11729 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11730 do the comparison in a narrower mode. */
11731 if (! unsigned_comparison_p
11732 && CONST_INT_P (XEXP (op0
, 1))
11733 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11734 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11735 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11736 MODE_INT
, 1)) != BLKmode
11737 && (((unsigned HOST_WIDE_INT
) const_op
11738 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11739 <= GET_MODE_MASK (tmode
)))
11741 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
11745 /* Likewise if OP0 is a PLUS of a sign extension with a
11746 constant, which is usually represented with the PLUS
11747 between the shifts. */
11748 if (! unsigned_comparison_p
11749 && CONST_INT_P (XEXP (op0
, 1))
11750 && GET_CODE (XEXP (op0
, 0)) == PLUS
11751 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
11752 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11753 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11754 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11755 MODE_INT
, 1)) != BLKmode
11756 && (((unsigned HOST_WIDE_INT
) const_op
11757 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11758 <= GET_MODE_MASK (tmode
)))
11760 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11761 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11762 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
11763 add_const
, XEXP (op0
, 1));
11765 op0
= simplify_gen_binary (PLUS
, tmode
,
11766 gen_lowpart (tmode
, inner
),
11771 /* ... fall through ... */
11773 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11774 the low order N bits of FOO are known to be zero, we can do this
11775 by comparing FOO with C shifted left N bits so long as no
11776 overflow occurs. Even if the low order N bits of FOO aren't known
11777 to be zero, if the comparison is >= or < we can use the same
11778 optimization and for > or <= by setting all the low
11779 order N bits in the comparison constant. */
11780 if (CONST_INT_P (XEXP (op0
, 1))
11781 && INTVAL (XEXP (op0
, 1)) > 0
11782 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11783 && mode_width
<= HOST_BITS_PER_WIDE_INT
11784 && (((unsigned HOST_WIDE_INT
) const_op
11785 + (GET_CODE (op0
) != LSHIFTRT
11786 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11789 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11791 unsigned HOST_WIDE_INT low_bits
11792 = (nonzero_bits (XEXP (op0
, 0), mode
)
11793 & (((unsigned HOST_WIDE_INT
) 1
11794 << INTVAL (XEXP (op0
, 1))) - 1));
11795 if (low_bits
== 0 || !equality_comparison_p
)
11797 /* If the shift was logical, then we must make the condition
11799 if (GET_CODE (op0
) == LSHIFTRT
)
11800 code
= unsigned_condition (code
);
11802 const_op
<<= INTVAL (XEXP (op0
, 1));
11804 && (code
== GT
|| code
== GTU
11805 || code
== LE
|| code
== LEU
))
11807 |= (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1);
11808 op1
= GEN_INT (const_op
);
11809 op0
= XEXP (op0
, 0);
11814 /* If we are using this shift to extract just the sign bit, we
11815 can replace this with an LT or GE comparison. */
11817 && (equality_comparison_p
|| sign_bit_comparison_p
)
11818 && CONST_INT_P (XEXP (op0
, 1))
11819 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
11821 op0
= XEXP (op0
, 0);
11822 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11834 /* Now make any compound operations involved in this comparison. Then,
11835 check for an outmost SUBREG on OP0 that is not doing anything or is
11836 paradoxical. The latter transformation must only be performed when
11837 it is known that the "extra" bits will be the same in op0 and op1 or
11838 that they don't matter. There are three cases to consider:
11840 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11841 care bits and we can assume they have any convenient value. So
11842 making the transformation is safe.
11844 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11845 In this case the upper bits of op0 are undefined. We should not make
11846 the simplification in that case as we do not know the contents of
11849 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11850 UNKNOWN. In that case we know those bits are zeros or ones. We must
11851 also be sure that they are the same as the upper bits of op1.
11853 We can never remove a SUBREG for a non-equality comparison because
11854 the sign bit is in a different place in the underlying object. */
11856 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11857 op1
= make_compound_operation (op1
, SET
);
11859 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11860 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11861 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11862 && (code
== NE
|| code
== EQ
))
11864 if (paradoxical_subreg_p (op0
))
11866 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11868 if (REG_P (SUBREG_REG (op0
)))
11870 op0
= SUBREG_REG (op0
);
11871 op1
= gen_lowpart (GET_MODE (op0
), op1
);
11874 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
11875 <= HOST_BITS_PER_WIDE_INT
)
11876 && (nonzero_bits (SUBREG_REG (op0
),
11877 GET_MODE (SUBREG_REG (op0
)))
11878 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11880 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
11882 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11883 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11884 op0
= SUBREG_REG (op0
), op1
= tem
;
11888 /* We now do the opposite procedure: Some machines don't have compare
11889 insns in all modes. If OP0's mode is an integer mode smaller than a
11890 word and we can't do a compare in that mode, see if there is a larger
11891 mode for which we can do the compare. There are a number of cases in
11892 which we can use the wider mode. */
11894 mode
= GET_MODE (op0
);
11895 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11896 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11897 && ! have_insn_for (COMPARE
, mode
))
11898 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11899 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
11900 tmode
= GET_MODE_WIDER_MODE (tmode
))
11901 if (have_insn_for (COMPARE
, tmode
))
11905 /* If this is a test for negative, we can make an explicit
11906 test of the sign bit. Test this first so we can use
11907 a paradoxical subreg to extend OP0. */
11909 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11910 && HWI_COMPUTABLE_MODE_P (mode
))
11912 op0
= simplify_gen_binary (AND
, tmode
,
11913 gen_lowpart (tmode
, op0
),
11914 GEN_INT ((unsigned HOST_WIDE_INT
) 1
11915 << (GET_MODE_BITSIZE (mode
)
11917 code
= (code
== LT
) ? NE
: EQ
;
11921 /* If the only nonzero bits in OP0 and OP1 are those in the
11922 narrower mode and this is an equality or unsigned comparison,
11923 we can use the wider mode. Similarly for sign-extended
11924 values, in which case it is true for all comparisons. */
11925 zero_extended
= ((code
== EQ
|| code
== NE
11926 || code
== GEU
|| code
== GTU
11927 || code
== LEU
|| code
== LTU
)
11928 && (nonzero_bits (op0
, tmode
)
11929 & ~GET_MODE_MASK (mode
)) == 0
11930 && ((CONST_INT_P (op1
)
11931 || (nonzero_bits (op1
, tmode
)
11932 & ~GET_MODE_MASK (mode
)) == 0)));
11935 || ((num_sign_bit_copies (op0
, tmode
)
11936 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11937 - GET_MODE_PRECISION (mode
)))
11938 && (num_sign_bit_copies (op1
, tmode
)
11939 > (unsigned int) (GET_MODE_PRECISION (tmode
)
11940 - GET_MODE_PRECISION (mode
)))))
11942 /* If OP0 is an AND and we don't have an AND in MODE either,
11943 make a new AND in the proper mode. */
11944 if (GET_CODE (op0
) == AND
11945 && !have_insn_for (AND
, mode
))
11946 op0
= simplify_gen_binary (AND
, tmode
,
11947 gen_lowpart (tmode
,
11949 gen_lowpart (tmode
,
11955 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
11956 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
11960 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
11961 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
11968 /* If this machine only supports a subset of valid comparisons, see if we
11969 can convert an unsupported one into a supported one. */
11970 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
11978 /* Utility function for record_value_for_reg. Count number of
11983 enum rtx_code code
= GET_CODE (x
);
11987 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
11988 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
11990 rtx x0
= XEXP (x
, 0);
11991 rtx x1
= XEXP (x
, 1);
11994 return 1 + 2 * count_rtxs (x0
);
11996 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
11997 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
11998 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11999 return 2 + 2 * count_rtxs (x0
)
12000 + count_rtxs (x
== XEXP (x1
, 0)
12001 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12003 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12004 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12005 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12006 return 2 + 2 * count_rtxs (x1
)
12007 + count_rtxs (x
== XEXP (x0
, 0)
12008 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12011 fmt
= GET_RTX_FORMAT (code
);
12012 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12014 ret
+= count_rtxs (XEXP (x
, i
));
12015 else if (fmt
[i
] == 'E')
12016 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12017 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12022 /* Utility function for following routine. Called when X is part of a value
12023 being stored into last_set_value. Sets last_set_table_tick
12024 for each register mentioned. Similar to mention_regs in cse.c */
12027 update_table_tick (rtx x
)
12029 enum rtx_code code
= GET_CODE (x
);
12030 const char *fmt
= GET_RTX_FORMAT (code
);
12035 unsigned int regno
= REGNO (x
);
12036 unsigned int endregno
= END_REGNO (x
);
12039 for (r
= regno
; r
< endregno
; r
++)
12041 reg_stat_type
*rsp
= ®_stat
[r
];
12042 rsp
->last_set_table_tick
= label_tick
;
12048 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12051 /* Check for identical subexpressions. If x contains
12052 identical subexpression we only have to traverse one of
12054 if (i
== 0 && ARITHMETIC_P (x
))
12056 /* Note that at this point x1 has already been
12058 rtx x0
= XEXP (x
, 0);
12059 rtx x1
= XEXP (x
, 1);
12061 /* If x0 and x1 are identical then there is no need to
12066 /* If x0 is identical to a subexpression of x1 then while
12067 processing x1, x0 has already been processed. Thus we
12068 are done with x. */
12069 if (ARITHMETIC_P (x1
)
12070 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12073 /* If x1 is identical to a subexpression of x0 then we
12074 still have to process the rest of x0. */
12075 if (ARITHMETIC_P (x0
)
12076 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12078 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12083 update_table_tick (XEXP (x
, i
));
12085 else if (fmt
[i
] == 'E')
12086 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12087 update_table_tick (XVECEXP (x
, i
, j
));
12090 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12091 are saying that the register is clobbered and we no longer know its
12092 value. If INSN is zero, don't update reg_stat[].last_set; this is
12093 only permitted with VALUE also zero and is used to invalidate the
12097 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
12099 unsigned int regno
= REGNO (reg
);
12100 unsigned int endregno
= END_REGNO (reg
);
12102 reg_stat_type
*rsp
;
12104 /* If VALUE contains REG and we have a previous value for REG, substitute
12105 the previous value. */
12106 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12110 /* Set things up so get_last_value is allowed to see anything set up to
12112 subst_low_luid
= DF_INSN_LUID (insn
);
12113 tem
= get_last_value (reg
);
12115 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12116 it isn't going to be useful and will take a lot of time to process,
12117 so just use the CLOBBER. */
12121 if (ARITHMETIC_P (tem
)
12122 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12123 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12124 tem
= XEXP (tem
, 0);
12125 else if (count_occurrences (value
, reg
, 1) >= 2)
12127 /* If there are two or more occurrences of REG in VALUE,
12128 prevent the value from growing too much. */
12129 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12130 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12133 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12137 /* For each register modified, show we don't know its value, that
12138 we don't know about its bitwise content, that its value has been
12139 updated, and that we don't know the location of the death of the
12141 for (i
= regno
; i
< endregno
; i
++)
12143 rsp
= ®_stat
[i
];
12146 rsp
->last_set
= insn
;
12148 rsp
->last_set_value
= 0;
12149 rsp
->last_set_mode
= VOIDmode
;
12150 rsp
->last_set_nonzero_bits
= 0;
12151 rsp
->last_set_sign_bit_copies
= 0;
12152 rsp
->last_death
= 0;
12153 rsp
->truncated_to_mode
= VOIDmode
;
12156 /* Mark registers that are being referenced in this value. */
12158 update_table_tick (value
);
12160 /* Now update the status of each register being set.
12161 If someone is using this register in this block, set this register
12162 to invalid since we will get confused between the two lives in this
12163 basic block. This makes using this register always invalid. In cse, we
12164 scan the table to invalidate all entries using this register, but this
12165 is too much work for us. */
12167 for (i
= regno
; i
< endregno
; i
++)
12169 rsp
= ®_stat
[i
];
12170 rsp
->last_set_label
= label_tick
;
12172 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12173 rsp
->last_set_invalid
= 1;
12175 rsp
->last_set_invalid
= 0;
12178 /* The value being assigned might refer to X (like in "x++;"). In that
12179 case, we must replace it with (clobber (const_int 0)) to prevent
12181 rsp
= ®_stat
[regno
];
12182 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12184 value
= copy_rtx (value
);
12185 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12189 /* For the main register being modified, update the value, the mode, the
12190 nonzero bits, and the number of sign bit copies. */
12192 rsp
->last_set_value
= value
;
12196 enum machine_mode mode
= GET_MODE (reg
);
12197 subst_low_luid
= DF_INSN_LUID (insn
);
12198 rsp
->last_set_mode
= mode
;
12199 if (GET_MODE_CLASS (mode
) == MODE_INT
12200 && HWI_COMPUTABLE_MODE_P (mode
))
12201 mode
= nonzero_bits_mode
;
12202 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12203 rsp
->last_set_sign_bit_copies
12204 = num_sign_bit_copies (value
, GET_MODE (reg
));
12208 /* Called via note_stores from record_dead_and_set_regs to handle one
12209 SET or CLOBBER in an insn. DATA is the instruction in which the
12210 set is occurring. */
12213 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12215 rtx record_dead_insn
= (rtx
) data
;
12217 if (GET_CODE (dest
) == SUBREG
)
12218 dest
= SUBREG_REG (dest
);
12220 if (!record_dead_insn
)
12223 record_value_for_reg (dest
, NULL_RTX
, NULL_RTX
);
12229 /* If we are setting the whole register, we know its value. Otherwise
12230 show that we don't know the value. We can handle SUBREG in
12232 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12233 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12234 else if (GET_CODE (setter
) == SET
12235 && GET_CODE (SET_DEST (setter
)) == SUBREG
12236 && SUBREG_REG (SET_DEST (setter
)) == dest
12237 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12238 && subreg_lowpart_p (SET_DEST (setter
)))
12239 record_value_for_reg (dest
, record_dead_insn
,
12240 gen_lowpart (GET_MODE (dest
),
12241 SET_SRC (setter
)));
12243 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12245 else if (MEM_P (dest
)
12246 /* Ignore pushes, they clobber nothing. */
12247 && ! push_operand (dest
, GET_MODE (dest
)))
12248 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12251 /* Update the records of when each REG was most recently set or killed
12252 for the things done by INSN. This is the last thing done in processing
12253 INSN in the combiner loop.
12255 We update reg_stat[], in particular fields last_set, last_set_value,
12256 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12257 last_death, and also the similar information mem_last_set (which insn
12258 most recently modified memory) and last_call_luid (which insn was the
12259 most recent subroutine call). */
12262 record_dead_and_set_regs (rtx insn
)
12267 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12269 if (REG_NOTE_KIND (link
) == REG_DEAD
12270 && REG_P (XEXP (link
, 0)))
12272 unsigned int regno
= REGNO (XEXP (link
, 0));
12273 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12275 for (i
= regno
; i
< endregno
; i
++)
12277 reg_stat_type
*rsp
;
12279 rsp
= ®_stat
[i
];
12280 rsp
->last_death
= insn
;
12283 else if (REG_NOTE_KIND (link
) == REG_INC
)
12284 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12289 hard_reg_set_iterator hrsi
;
12290 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12292 reg_stat_type
*rsp
;
12294 rsp
= ®_stat
[i
];
12295 rsp
->last_set_invalid
= 1;
12296 rsp
->last_set
= insn
;
12297 rsp
->last_set_value
= 0;
12298 rsp
->last_set_mode
= VOIDmode
;
12299 rsp
->last_set_nonzero_bits
= 0;
12300 rsp
->last_set_sign_bit_copies
= 0;
12301 rsp
->last_death
= 0;
12302 rsp
->truncated_to_mode
= VOIDmode
;
12305 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12307 /* We can't combine into a call pattern. Remember, though, that
12308 the return value register is set at this LUID. We could
12309 still replace a register with the return value from the
12310 wrong subroutine call! */
12311 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12314 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12317 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12318 register present in the SUBREG, so for each such SUBREG go back and
12319 adjust nonzero and sign bit information of the registers that are
12320 known to have some zero/sign bits set.
12322 This is needed because when combine blows the SUBREGs away, the
12323 information on zero/sign bits is lost and further combines can be
12324 missed because of that. */
12327 record_promoted_value (rtx insn
, rtx subreg
)
12329 struct insn_link
*links
;
12331 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12332 enum machine_mode mode
= GET_MODE (subreg
);
12334 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12337 for (links
= LOG_LINKS (insn
); links
;)
12339 reg_stat_type
*rsp
;
12341 insn
= links
->insn
;
12342 set
= single_set (insn
);
12344 if (! set
|| !REG_P (SET_DEST (set
))
12345 || REGNO (SET_DEST (set
)) != regno
12346 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12348 links
= links
->next
;
12352 rsp
= ®_stat
[regno
];
12353 if (rsp
->last_set
== insn
)
12355 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
12356 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12359 if (REG_P (SET_SRC (set
)))
12361 regno
= REGNO (SET_SRC (set
));
12362 links
= LOG_LINKS (insn
);
12369 /* Check if X, a register, is known to contain a value already
12370 truncated to MODE. In this case we can use a subreg to refer to
12371 the truncated value even though in the generic case we would need
12372 an explicit truncation. */
12375 reg_truncated_to_mode (enum machine_mode mode
, const_rtx x
)
12377 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12378 enum machine_mode truncated
= rsp
->truncated_to_mode
;
12381 || rsp
->truncation_label
< label_tick_ebb_start
)
12383 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12385 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12390 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12391 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12392 might be able to turn a truncate into a subreg using this information.
12393 Return -1 if traversing *P is complete or 0 otherwise. */
12396 record_truncated_value (rtx
*p
, void *data ATTRIBUTE_UNUSED
)
12399 enum machine_mode truncated_mode
;
12400 reg_stat_type
*rsp
;
12402 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12404 enum machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12405 truncated_mode
= GET_MODE (x
);
12407 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12410 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12413 x
= SUBREG_REG (x
);
12415 /* ??? For hard-regs we now record everything. We might be able to
12416 optimize this using last_set_mode. */
12417 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12418 truncated_mode
= GET_MODE (x
);
12422 rsp
= ®_stat
[REGNO (x
)];
12423 if (rsp
->truncated_to_mode
== 0
12424 || rsp
->truncation_label
< label_tick_ebb_start
12425 || (GET_MODE_SIZE (truncated_mode
)
12426 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
12428 rsp
->truncated_to_mode
= truncated_mode
;
12429 rsp
->truncation_label
= label_tick
;
12435 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12436 the modes they are used in. This can help truning TRUNCATEs into
12440 record_truncated_values (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
12442 for_each_rtx (x
, record_truncated_value
, NULL
);
12445 /* Scan X for promoted SUBREGs. For each one found,
12446 note what it implies to the registers used in it. */
12449 check_promoted_subreg (rtx insn
, rtx x
)
12451 if (GET_CODE (x
) == SUBREG
12452 && SUBREG_PROMOTED_VAR_P (x
)
12453 && REG_P (SUBREG_REG (x
)))
12454 record_promoted_value (insn
, x
);
12457 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
12460 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
12464 check_promoted_subreg (insn
, XEXP (x
, i
));
12468 if (XVEC (x
, i
) != 0)
12469 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12470 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
12476 /* Verify that all the registers and memory references mentioned in *LOC are
12477 still valid. *LOC was part of a value set in INSN when label_tick was
12478 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12479 the invalid references with (clobber (const_int 0)) and return 1. This
12480 replacement is useful because we often can get useful information about
12481 the form of a value (e.g., if it was produced by a shift that always
12482 produces -1 or 0) even though we don't know exactly what registers it
12483 was produced from. */
12486 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
12489 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
12490 int len
= GET_RTX_LENGTH (GET_CODE (x
));
12495 unsigned int regno
= REGNO (x
);
12496 unsigned int endregno
= END_REGNO (x
);
12499 for (j
= regno
; j
< endregno
; j
++)
12501 reg_stat_type
*rsp
= ®_stat
[j
];
12502 if (rsp
->last_set_invalid
12503 /* If this is a pseudo-register that was only set once and not
12504 live at the beginning of the function, it is always valid. */
12505 || (! (regno
>= FIRST_PSEUDO_REGISTER
12506 && REG_N_SETS (regno
) == 1
12507 && (!REGNO_REG_SET_P
12508 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
)))
12509 && rsp
->last_set_label
> tick
))
12512 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12519 /* If this is a memory reference, make sure that there were no stores after
12520 it that might have clobbered the value. We don't have alias info, so we
12521 assume any store invalidates it. Moreover, we only have local UIDs, so
12522 we also assume that there were stores in the intervening basic blocks. */
12523 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
12524 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
12527 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
12531 for (i
= 0; i
< len
; i
++)
12535 /* Check for identical subexpressions. If x contains
12536 identical subexpression we only have to traverse one of
12538 if (i
== 1 && ARITHMETIC_P (x
))
12540 /* Note that at this point x0 has already been checked
12541 and found valid. */
12542 rtx x0
= XEXP (x
, 0);
12543 rtx x1
= XEXP (x
, 1);
12545 /* If x0 and x1 are identical then x is also valid. */
12549 /* If x1 is identical to a subexpression of x0 then
12550 while checking x0, x1 has already been checked. Thus
12551 it is valid and so as x. */
12552 if (ARITHMETIC_P (x0
)
12553 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12556 /* If x0 is identical to a subexpression of x1 then x is
12557 valid iff the rest of x1 is valid. */
12558 if (ARITHMETIC_P (x1
)
12559 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12561 get_last_value_validate (&XEXP (x1
,
12562 x0
== XEXP (x1
, 0) ? 1 : 0),
12563 insn
, tick
, replace
);
12566 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
12570 else if (fmt
[i
] == 'E')
12571 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12572 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
12573 insn
, tick
, replace
) == 0)
12577 /* If we haven't found a reason for it to be invalid, it is valid. */
12581 /* Get the last value assigned to X, if known. Some registers
12582 in the value may be replaced with (clobber (const_int 0)) if their value
12583 is known longer known reliably. */
12586 get_last_value (const_rtx x
)
12588 unsigned int regno
;
12590 reg_stat_type
*rsp
;
12592 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12593 then convert it to the desired mode. If this is a paradoxical SUBREG,
12594 we cannot predict what values the "extra" bits might have. */
12595 if (GET_CODE (x
) == SUBREG
12596 && subreg_lowpart_p (x
)
12597 && !paradoxical_subreg_p (x
)
12598 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
12599 return gen_lowpart (GET_MODE (x
), value
);
12605 rsp
= ®_stat
[regno
];
12606 value
= rsp
->last_set_value
;
12608 /* If we don't have a value, or if it isn't for this basic block and
12609 it's either a hard register, set more than once, or it's a live
12610 at the beginning of the function, return 0.
12612 Because if it's not live at the beginning of the function then the reg
12613 is always set before being used (is never used without being set).
12614 And, if it's set only once, and it's always set before use, then all
12615 uses must have the same last value, even if it's not from this basic
12619 || (rsp
->last_set_label
< label_tick_ebb_start
12620 && (regno
< FIRST_PSEUDO_REGISTER
12621 || REG_N_SETS (regno
) != 1
12623 (DF_LR_IN (ENTRY_BLOCK_PTR
->next_bb
), regno
))))
12626 /* If the value was set in a later insn than the ones we are processing,
12627 we can't use it even if the register was only set once. */
12628 if (rsp
->last_set_label
== label_tick
12629 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
12632 /* If the value has all its registers valid, return it. */
12633 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
12636 /* Otherwise, make a copy and replace any invalid register with
12637 (clobber (const_int 0)). If that fails for some reason, return 0. */
12639 value
= copy_rtx (value
);
12640 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
12646 /* Return nonzero if expression X refers to a REG or to memory
12647 that is set in an instruction more recent than FROM_LUID. */
12650 use_crosses_set_p (const_rtx x
, int from_luid
)
12654 enum rtx_code code
= GET_CODE (x
);
12658 unsigned int regno
= REGNO (x
);
12659 unsigned endreg
= END_REGNO (x
);
12661 #ifdef PUSH_ROUNDING
12662 /* Don't allow uses of the stack pointer to be moved,
12663 because we don't know whether the move crosses a push insn. */
12664 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
12667 for (; regno
< endreg
; regno
++)
12669 reg_stat_type
*rsp
= ®_stat
[regno
];
12671 && rsp
->last_set_label
== label_tick
12672 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
12678 if (code
== MEM
&& mem_last_set
> from_luid
)
12681 fmt
= GET_RTX_FORMAT (code
);
12683 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12688 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12689 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
12692 else if (fmt
[i
] == 'e'
12693 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
12699 /* Define three variables used for communication between the following
12702 static unsigned int reg_dead_regno
, reg_dead_endregno
;
12703 static int reg_dead_flag
;
12705 /* Function called via note_stores from reg_dead_at_p.
12707 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12708 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12711 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
12713 unsigned int regno
, endregno
;
12718 regno
= REGNO (dest
);
12719 endregno
= END_REGNO (dest
);
12720 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
12721 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
12724 /* Return nonzero if REG is known to be dead at INSN.
12726 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12727 referencing REG, it is dead. If we hit a SET referencing REG, it is
12728 live. Otherwise, see if it is live or dead at the start of the basic
12729 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12730 must be assumed to be always live. */
12733 reg_dead_at_p (rtx reg
, rtx insn
)
12738 /* Set variables for reg_dead_at_p_1. */
12739 reg_dead_regno
= REGNO (reg
);
12740 reg_dead_endregno
= END_REGNO (reg
);
12744 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12745 we allow the machine description to decide whether use-and-clobber
12746 patterns are OK. */
12747 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
12749 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12750 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
12754 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12755 beginning of basic block. */
12756 block
= BLOCK_FOR_INSN (insn
);
12761 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
12763 return reg_dead_flag
== 1 ? 1 : 0;
12765 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
12769 if (insn
== BB_HEAD (block
))
12772 insn
= PREV_INSN (insn
);
12775 /* Look at live-in sets for the basic block that we were in. */
12776 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12777 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
12783 /* Note hard registers in X that are used. */
12786 mark_used_regs_combine (rtx x
)
12788 RTX_CODE code
= GET_CODE (x
);
12789 unsigned int regno
;
12800 case ADDR_DIFF_VEC
:
12803 /* CC0 must die in the insn after it is set, so we don't need to take
12804 special note of it here. */
12810 /* If we are clobbering a MEM, mark any hard registers inside the
12811 address as used. */
12812 if (MEM_P (XEXP (x
, 0)))
12813 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12818 /* A hard reg in a wide mode may really be multiple registers.
12819 If so, mark all of them just like the first. */
12820 if (regno
< FIRST_PSEUDO_REGISTER
)
12822 /* None of this applies to the stack, frame or arg pointers. */
12823 if (regno
== STACK_POINTER_REGNUM
12824 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12825 || regno
== HARD_FRAME_POINTER_REGNUM
12827 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12828 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12830 || regno
== FRAME_POINTER_REGNUM
)
12833 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
12839 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12841 rtx testreg
= SET_DEST (x
);
12843 while (GET_CODE (testreg
) == SUBREG
12844 || GET_CODE (testreg
) == ZERO_EXTRACT
12845 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12846 testreg
= XEXP (testreg
, 0);
12848 if (MEM_P (testreg
))
12849 mark_used_regs_combine (XEXP (testreg
, 0));
12851 mark_used_regs_combine (SET_SRC (x
));
12859 /* Recursively scan the operands of this expression. */
12862 const char *fmt
= GET_RTX_FORMAT (code
);
12864 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12867 mark_used_regs_combine (XEXP (x
, i
));
12868 else if (fmt
[i
] == 'E')
12872 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12873 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12879 /* Remove register number REGNO from the dead registers list of INSN.
12881 Return the note used to record the death, if there was one. */
12884 remove_death (unsigned int regno
, rtx insn
)
12886 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12889 remove_note (insn
, note
);
12894 /* For each register (hardware or pseudo) used within expression X, if its
12895 death is in an instruction with luid between FROM_LUID (inclusive) and
12896 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12897 list headed by PNOTES.
12899 That said, don't move registers killed by maybe_kill_insn.
12901 This is done when X is being merged by combination into TO_INSN. These
12902 notes will then be distributed as needed. */
12905 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx to_insn
,
12910 enum rtx_code code
= GET_CODE (x
);
12914 unsigned int regno
= REGNO (x
);
12915 rtx where_dead
= reg_stat
[regno
].last_death
;
12917 /* Don't move the register if it gets killed in between from and to. */
12918 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12919 && ! reg_referenced_p (x
, maybe_kill_insn
))
12923 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
12924 && DF_INSN_LUID (where_dead
) >= from_luid
12925 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
12927 rtx note
= remove_death (regno
, where_dead
);
12929 /* It is possible for the call above to return 0. This can occur
12930 when last_death points to I2 or I1 that we combined with.
12931 In that case make a new note.
12933 We must also check for the case where X is a hard register
12934 and NOTE is a death note for a range of hard registers
12935 including X. In that case, we must put REG_DEAD notes for
12936 the remaining registers in place of NOTE. */
12938 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12939 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12940 > GET_MODE_SIZE (GET_MODE (x
))))
12942 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12943 unsigned int deadend
= END_HARD_REGNO (XEXP (note
, 0));
12944 unsigned int ourend
= END_HARD_REGNO (x
);
12947 for (i
= deadregno
; i
< deadend
; i
++)
12948 if (i
< regno
|| i
>= ourend
)
12949 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
12952 /* If we didn't find any note, or if we found a REG_DEAD note that
12953 covers only part of the given reg, and we have a multi-reg hard
12954 register, then to be safe we must check for REG_DEAD notes
12955 for each register other than the first. They could have
12956 their own REG_DEAD notes lying around. */
12957 else if ((note
== 0
12959 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12960 < GET_MODE_SIZE (GET_MODE (x
)))))
12961 && regno
< FIRST_PSEUDO_REGISTER
12962 && hard_regno_nregs
[regno
][GET_MODE (x
)] > 1)
12964 unsigned int ourend
= END_HARD_REGNO (x
);
12965 unsigned int i
, offset
;
12969 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
12973 for (i
= regno
+ offset
; i
< ourend
; i
++)
12974 move_deaths (regno_reg_rtx
[i
],
12975 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
12978 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12980 XEXP (note
, 1) = *pnotes
;
12984 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
12990 else if (GET_CODE (x
) == SET
)
12992 rtx dest
= SET_DEST (x
);
12994 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
12996 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12997 that accesses one word of a multi-word item, some
12998 piece of everything register in the expression is used by
12999 this insn, so remove any old death. */
13000 /* ??? So why do we test for equality of the sizes? */
13002 if (GET_CODE (dest
) == ZERO_EXTRACT
13003 || GET_CODE (dest
) == STRICT_LOW_PART
13004 || (GET_CODE (dest
) == SUBREG
13005 && (((GET_MODE_SIZE (GET_MODE (dest
))
13006 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13007 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13008 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13010 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13014 /* If this is some other SUBREG, we know it replaces the entire
13015 value, so use that as the destination. */
13016 if (GET_CODE (dest
) == SUBREG
)
13017 dest
= SUBREG_REG (dest
);
13019 /* If this is a MEM, adjust deaths of anything used in the address.
13020 For a REG (the only other possibility), the entire value is
13021 being replaced so the old value is not used in this insn. */
13024 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13029 else if (GET_CODE (x
) == CLOBBER
)
13032 len
= GET_RTX_LENGTH (code
);
13033 fmt
= GET_RTX_FORMAT (code
);
13035 for (i
= 0; i
< len
; i
++)
13040 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13041 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13044 else if (fmt
[i
] == 'e')
13045 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13049 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13050 pattern of an insn. X must be a REG. */
13053 reg_bitfield_target_p (rtx x
, rtx body
)
13057 if (GET_CODE (body
) == SET
)
13059 rtx dest
= SET_DEST (body
);
13061 unsigned int regno
, tregno
, endregno
, endtregno
;
13063 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13064 target
= XEXP (dest
, 0);
13065 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13066 target
= SUBREG_REG (XEXP (dest
, 0));
13070 if (GET_CODE (target
) == SUBREG
)
13071 target
= SUBREG_REG (target
);
13073 if (!REG_P (target
))
13076 tregno
= REGNO (target
), regno
= REGNO (x
);
13077 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13078 return target
== x
;
13080 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13081 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13083 return endregno
> tregno
&& regno
< endtregno
;
13086 else if (GET_CODE (body
) == PARALLEL
)
13087 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13088 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13094 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13095 as appropriate. I3 and I2 are the insns resulting from the combination
13096 insns including FROM (I2 may be zero).
13098 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13099 not need REG_DEAD notes because they are being substituted for. This
13100 saves searching in the most common cases.
13102 Each note in the list is either ignored or placed on some insns, depending
13103 on the type of note. */
13106 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
, rtx elim_i2
,
13107 rtx elim_i1
, rtx elim_i0
)
13109 rtx note
, next_note
;
13112 for (note
= notes
; note
; note
= next_note
)
13114 rtx place
= 0, place2
= 0;
13116 next_note
= XEXP (note
, 1);
13117 switch (REG_NOTE_KIND (note
))
13121 /* Doesn't matter much where we put this, as long as it's somewhere.
13122 It is preferable to keep these notes on branches, which is most
13123 likely to be i3. */
13127 case REG_NON_LOCAL_GOTO
:
13132 gcc_assert (i2
&& JUMP_P (i2
));
13137 case REG_EH_REGION
:
13138 /* These notes must remain with the call or trapping instruction. */
13141 else if (i2
&& CALL_P (i2
))
13145 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13146 if (may_trap_p (i3
))
13148 else if (i2
&& may_trap_p (i2
))
13150 /* ??? Otherwise assume we've combined things such that we
13151 can now prove that the instructions can't trap. Drop the
13152 note in this case. */
13156 case REG_ARGS_SIZE
:
13157 /* ??? How to distribute between i3-i1. Assume i3 contains the
13158 entire adjustment. Assert i3 contains at least some adjust. */
13159 if (!noop_move_p (i3
))
13161 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13162 /* fixup_args_size_notes looks at REG_NORETURN note,
13163 so ensure the note is placed there first. */
13167 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13168 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13172 XEXP (n
, 1) = REG_NOTES (i3
);
13173 REG_NOTES (i3
) = n
;
13177 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13178 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13179 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13180 gcc_assert (old_size
!= args_size
13182 && !ACCUMULATE_OUTGOING_ARGS
13183 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13190 /* These notes must remain with the call. It should not be
13191 possible for both I2 and I3 to be a call. */
13196 gcc_assert (i2
&& CALL_P (i2
));
13202 /* Any clobbers for i3 may still exist, and so we must process
13203 REG_UNUSED notes from that insn.
13205 Any clobbers from i2 or i1 can only exist if they were added by
13206 recog_for_combine. In that case, recog_for_combine created the
13207 necessary REG_UNUSED notes. Trying to keep any original
13208 REG_UNUSED notes from these insns can cause incorrect output
13209 if it is for the same register as the original i3 dest.
13210 In that case, we will notice that the register is set in i3,
13211 and then add a REG_UNUSED note for the destination of i3, which
13212 is wrong. However, it is possible to have REG_UNUSED notes from
13213 i2 or i1 for register which were both used and clobbered, so
13214 we keep notes from i2 or i1 if they will turn into REG_DEAD
13217 /* If this register is set or clobbered in I3, put the note there
13218 unless there is one already. */
13219 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13221 if (from_insn
!= i3
)
13224 if (! (REG_P (XEXP (note
, 0))
13225 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13226 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13229 /* Otherwise, if this register is used by I3, then this register
13230 now dies here, so we must put a REG_DEAD note here unless there
13232 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13233 && ! (REG_P (XEXP (note
, 0))
13234 ? find_regno_note (i3
, REG_DEAD
,
13235 REGNO (XEXP (note
, 0)))
13236 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13238 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13246 /* These notes say something about results of an insn. We can
13247 only support them if they used to be on I3 in which case they
13248 remain on I3. Otherwise they are ignored.
13250 If the note refers to an expression that is not a constant, we
13251 must also ignore the note since we cannot tell whether the
13252 equivalence is still true. It might be possible to do
13253 slightly better than this (we only have a problem if I2DEST
13254 or I1DEST is present in the expression), but it doesn't
13255 seem worth the trouble. */
13257 if (from_insn
== i3
13258 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13263 /* These notes say something about how a register is used. They must
13264 be present on any use of the register in I2 or I3. */
13265 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13268 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13277 case REG_LABEL_TARGET
:
13278 case REG_LABEL_OPERAND
:
13279 /* This can show up in several ways -- either directly in the
13280 pattern, or hidden off in the constant pool with (or without?)
13281 a REG_EQUAL note. */
13282 /* ??? Ignore the without-reg_equal-note problem for now. */
13283 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13284 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13285 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13286 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
13290 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13291 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13292 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
13293 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
13301 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13302 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13304 if (place
&& JUMP_P (place
)
13305 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13306 && (JUMP_LABEL (place
) == NULL
13307 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13309 rtx label
= JUMP_LABEL (place
);
13312 JUMP_LABEL (place
) = XEXP (note
, 0);
13313 else if (LABEL_P (label
))
13314 LABEL_NUSES (label
)--;
13317 if (place2
&& JUMP_P (place2
)
13318 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13319 && (JUMP_LABEL (place2
) == NULL
13320 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13322 rtx label
= JUMP_LABEL (place2
);
13325 JUMP_LABEL (place2
) = XEXP (note
, 0);
13326 else if (LABEL_P (label
))
13327 LABEL_NUSES (label
)--;
13333 /* This note says something about the value of a register prior
13334 to the execution of an insn. It is too much trouble to see
13335 if the note is still correct in all situations. It is better
13336 to simply delete it. */
13340 /* If we replaced the right hand side of FROM_INSN with a
13341 REG_EQUAL note, the original use of the dying register
13342 will not have been combined into I3 and I2. In such cases,
13343 FROM_INSN is guaranteed to be the first of the combined
13344 instructions, so we simply need to search back before
13345 FROM_INSN for the previous use or set of this register,
13346 then alter the notes there appropriately.
13348 If the register is used as an input in I3, it dies there.
13349 Similarly for I2, if it is nonzero and adjacent to I3.
13351 If the register is not used as an input in either I3 or I2
13352 and it is not one of the registers we were supposed to eliminate,
13353 there are two possibilities. We might have a non-adjacent I2
13354 or we might have somehow eliminated an additional register
13355 from a computation. For example, we might have had A & B where
13356 we discover that B will always be zero. In this case we will
13357 eliminate the reference to A.
13359 In both cases, we must search to see if we can find a previous
13360 use of A and put the death note there. */
13363 && from_insn
== i2mod
13364 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13369 && CALL_P (from_insn
)
13370 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13372 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13374 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13375 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13377 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13379 && reg_overlap_mentioned_p (XEXP (note
, 0),
13381 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13382 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13389 basic_block bb
= this_basic_block
;
13391 for (tem
= PREV_INSN (tem
); place
== 0; tem
= PREV_INSN (tem
))
13393 if (!NONDEBUG_INSN_P (tem
))
13395 if (tem
== BB_HEAD (bb
))
13400 /* If the register is being set at TEM, see if that is all
13401 TEM is doing. If so, delete TEM. Otherwise, make this
13402 into a REG_UNUSED note instead. Don't delete sets to
13403 global register vars. */
13404 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
13405 || !global_regs
[REGNO (XEXP (note
, 0))])
13406 && reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
13408 rtx set
= single_set (tem
);
13409 rtx inner_dest
= 0;
13411 rtx cc0_setter
= NULL_RTX
;
13415 for (inner_dest
= SET_DEST (set
);
13416 (GET_CODE (inner_dest
) == STRICT_LOW_PART
13417 || GET_CODE (inner_dest
) == SUBREG
13418 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
13419 inner_dest
= XEXP (inner_dest
, 0))
13422 /* Verify that it was the set, and not a clobber that
13423 modified the register.
13425 CC0 targets must be careful to maintain setter/user
13426 pairs. If we cannot delete the setter due to side
13427 effects, mark the user with an UNUSED note instead
13430 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
13431 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
13433 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
13434 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
13435 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
13439 /* Move the notes and links of TEM elsewhere.
13440 This might delete other dead insns recursively.
13441 First set the pattern to something that won't use
13443 rtx old_notes
= REG_NOTES (tem
);
13445 PATTERN (tem
) = pc_rtx
;
13446 REG_NOTES (tem
) = NULL
;
13448 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
,
13449 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13450 distribute_links (LOG_LINKS (tem
));
13452 SET_INSN_DELETED (tem
);
13457 /* Delete the setter too. */
13460 PATTERN (cc0_setter
) = pc_rtx
;
13461 old_notes
= REG_NOTES (cc0_setter
);
13462 REG_NOTES (cc0_setter
) = NULL
;
13464 distribute_notes (old_notes
, cc0_setter
,
13465 cc0_setter
, NULL_RTX
,
13466 NULL_RTX
, NULL_RTX
, NULL_RTX
);
13467 distribute_links (LOG_LINKS (cc0_setter
));
13469 SET_INSN_DELETED (cc0_setter
);
13470 if (cc0_setter
== i2
)
13477 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
13479 /* If there isn't already a REG_UNUSED note, put one
13480 here. Do not place a REG_DEAD note, even if
13481 the register is also used here; that would not
13482 match the algorithm used in lifetime analysis
13483 and can cause the consistency check in the
13484 scheduler to fail. */
13485 if (! find_regno_note (tem
, REG_UNUSED
,
13486 REGNO (XEXP (note
, 0))))
13491 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
13493 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
13497 /* If we are doing a 3->2 combination, and we have a
13498 register which formerly died in i3 and was not used
13499 by i2, which now no longer dies in i3 and is used in
13500 i2 but does not die in i2, and place is between i2
13501 and i3, then we may need to move a link from place to
13503 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
13505 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
13506 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13508 struct insn_link
*links
= LOG_LINKS (place
);
13509 LOG_LINKS (place
) = NULL
;
13510 distribute_links (links
);
13515 if (tem
== BB_HEAD (bb
))
13521 /* If the register is set or already dead at PLACE, we needn't do
13522 anything with this note if it is still a REG_DEAD note.
13523 We check here if it is set at all, not if is it totally replaced,
13524 which is what `dead_or_set_p' checks, so also check for it being
13527 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
13529 unsigned int regno
= REGNO (XEXP (note
, 0));
13530 reg_stat_type
*rsp
= ®_stat
[regno
];
13532 if (dead_or_set_p (place
, XEXP (note
, 0))
13533 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
13535 /* Unless the register previously died in PLACE, clear
13536 last_death. [I no longer understand why this is
13538 if (rsp
->last_death
!= place
)
13539 rsp
->last_death
= 0;
13543 rsp
->last_death
= place
;
13545 /* If this is a death note for a hard reg that is occupying
13546 multiple registers, ensure that we are still using all
13547 parts of the object. If we find a piece of the object
13548 that is unused, we must arrange for an appropriate REG_DEAD
13549 note to be added for it. However, we can't just emit a USE
13550 and tag the note to it, since the register might actually
13551 be dead; so we recourse, and the recursive call then finds
13552 the previous insn that used this register. */
13554 if (place
&& regno
< FIRST_PSEUDO_REGISTER
13555 && hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))] > 1)
13557 unsigned int endregno
= END_HARD_REGNO (XEXP (note
, 0));
13561 for (i
= regno
; i
< endregno
; i
++)
13562 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
13563 && ! find_regno_fusage (place
, USE
, i
))
13564 || dead_or_set_regno_p (place
, i
))
13569 /* Put only REG_DEAD notes for pieces that are
13570 not already dead or set. */
13572 for (i
= regno
; i
< endregno
;
13573 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
13575 rtx piece
= regno_reg_rtx
[i
];
13576 basic_block bb
= this_basic_block
;
13578 if (! dead_or_set_p (place
, piece
)
13579 && ! reg_bitfield_target_p (piece
,
13582 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
13585 distribute_notes (new_note
, place
, place
,
13586 NULL_RTX
, NULL_RTX
, NULL_RTX
,
13589 else if (! refers_to_regno_p (i
, i
+ 1,
13590 PATTERN (place
), 0)
13591 && ! find_regno_fusage (place
, USE
, i
))
13592 for (tem
= PREV_INSN (place
); ;
13593 tem
= PREV_INSN (tem
))
13595 if (!NONDEBUG_INSN_P (tem
))
13597 if (tem
== BB_HEAD (bb
))
13601 if (dead_or_set_p (tem
, piece
)
13602 || reg_bitfield_target_p (piece
,
13605 add_reg_note (tem
, REG_UNUSED
, piece
);
13619 /* Any other notes should not be present at this point in the
13621 gcc_unreachable ();
13626 XEXP (note
, 1) = REG_NOTES (place
);
13627 REG_NOTES (place
) = note
;
13631 add_reg_note (place2
, REG_NOTE_KIND (note
), XEXP (note
, 0));
13635 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13636 I3, I2, and I1 to new locations. This is also called to add a link
13637 pointing at I3 when I3's destination is changed. */
13640 distribute_links (struct insn_link
*links
)
13642 struct insn_link
*link
, *next_link
;
13644 for (link
= links
; link
; link
= next_link
)
13650 next_link
= link
->next
;
13652 /* If the insn that this link points to is a NOTE or isn't a single
13653 set, ignore it. In the latter case, it isn't clear what we
13654 can do other than ignore the link, since we can't tell which
13655 register it was for. Such links wouldn't be used by combine
13658 It is not possible for the destination of the target of the link to
13659 have been changed by combine. The only potential of this is if we
13660 replace I3, I2, and I1 by I3 and I2. But in that case the
13661 destination of I2 also remains unchanged. */
13663 if (NOTE_P (link
->insn
)
13664 || (set
= single_set (link
->insn
)) == 0)
13667 reg
= SET_DEST (set
);
13668 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
13669 || GET_CODE (reg
) == STRICT_LOW_PART
)
13670 reg
= XEXP (reg
, 0);
13672 /* A LOG_LINK is defined as being placed on the first insn that uses
13673 a register and points to the insn that sets the register. Start
13674 searching at the next insn after the target of the link and stop
13675 when we reach a set of the register or the end of the basic block.
13677 Note that this correctly handles the link that used to point from
13678 I3 to I2. Also note that not much searching is typically done here
13679 since most links don't point very far away. */
13681 for (insn
= NEXT_INSN (link
->insn
);
13682 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
13683 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
13684 insn
= NEXT_INSN (insn
))
13685 if (DEBUG_INSN_P (insn
))
13687 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
13689 if (reg_referenced_p (reg
, PATTERN (insn
)))
13693 else if (CALL_P (insn
)
13694 && find_reg_fusage (insn
, USE
, reg
))
13699 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
13702 /* If we found a place to put the link, place it there unless there
13703 is already a link to the same insn as LINK at that point. */
13707 struct insn_link
*link2
;
13709 FOR_EACH_LOG_LINK (link2
, place
)
13710 if (link2
->insn
== link
->insn
)
13715 link
->next
= LOG_LINKS (place
);
13716 LOG_LINKS (place
) = link
;
13718 /* Set added_links_insn to the earliest insn we added a
13720 if (added_links_insn
== 0
13721 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
13722 added_links_insn
= place
;
13728 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13729 Check whether the expression pointer to by LOC is a register or
13730 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13731 Otherwise return zero. */
13734 unmentioned_reg_p_1 (rtx
*loc
, void *expr
)
13739 && (REG_P (x
) || MEM_P (x
))
13740 && ! reg_mentioned_p (x
, (rtx
) expr
))
13745 /* Check for any register or memory mentioned in EQUIV that is not
13746 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13747 of EXPR where some registers may have been replaced by constants. */
13750 unmentioned_reg_p (rtx equiv
, rtx expr
)
13752 return for_each_rtx (&equiv
, unmentioned_reg_p_1
, expr
);
13755 DEBUG_FUNCTION
void
13756 dump_combine_stats (FILE *file
)
13760 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13761 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13765 dump_combine_total_stats (FILE *file
)
13769 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13770 total_attempts
, total_merges
, total_extras
, total_successes
);
13774 gate_handle_combine (void)
13776 return (optimize
> 0);
13779 /* Try combining insns through substitution. */
13780 static unsigned int
13781 rest_of_handle_combine (void)
13783 int rebuild_jump_labels_after_combine
;
13785 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
13786 df_note_add_problem ();
13789 regstat_init_n_sets_and_refs ();
13791 rebuild_jump_labels_after_combine
13792 = combine_instructions (get_insns (), max_reg_num ());
13794 /* Combining insns may have turned an indirect jump into a
13795 direct jump. Rebuild the JUMP_LABEL fields of jumping
13797 if (rebuild_jump_labels_after_combine
)
13799 timevar_push (TV_JUMP
);
13800 rebuild_jump_labels (get_insns ());
13802 timevar_pop (TV_JUMP
);
13805 regstat_free_n_sets_and_refs ();
13809 struct rtl_opt_pass pass_combine
=
13813 "combine", /* name */
13814 OPTGROUP_NONE
, /* optinfo_flags */
13815 gate_handle_combine
, /* gate */
13816 rest_of_handle_combine
, /* execute */
13819 0, /* static_pass_number */
13820 TV_COMBINE
, /* tv_id */
13821 PROP_cfglayout
, /* properties_required */
13822 0, /* properties_provided */
13823 0, /* properties_destroyed */
13824 0, /* todo_flags_start */
13825 TODO_df_finish
| TODO_verify_rtl_sharing
|
13826 TODO_ggc_collect
, /* todo_flags_finish */