1 /* Discovery of auto-inc and auto-dec instructions.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
3 Contributed by Kenneth Zadeck <zadeck@naturalbridge.com>
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "insn-config.h"
36 #include "tree-pass.h"
38 #include "print-rtl.h"
41 /* This pass was originally removed from flow.c. However there is
42 almost nothing that remains of that code.
44 There are (4) basic forms that are matched:
69 This uses a post-add, but it's handled as FORM_PRE_ADD because
70 the "increment" insn appears before the memory access.
89 (For this case to be true, b must not be assigned or used between
90 the *a and the assignment to b. B must also be a Pmode reg.)
110 There are three types of values of c.
112 1) c is a constant equal to the width of the value being accessed by
113 the pointer. This is useful for machines that have
114 HAVE_PRE_INCREMENT, HAVE_POST_INCREMENT, HAVE_PRE_DECREMENT or
115 HAVE_POST_DECREMENT defined.
117 2) c is a constant not equal to the width of the value being accessed
118 by the pointer. This is useful for machines that have
119 HAVE_PRE_MODIFY_DISP, HAVE_POST_MODIFY_DISP defined.
121 3) c is a register. This is useful for machines that have
122 HAVE_PRE_MODIFY_REG, HAVE_POST_MODIFY_REG
124 The is one special case: if a already had an offset equal to it +-
125 its width and that offset is equal to -c when the increment was
126 before the ref or +c if the increment was after the ref, then if we
127 can do the combination but switch the pre/post bit. */
139 /* The states of the second operands of mem refs and inc insns. If no
140 second operand of the mem_ref was found, it is assumed to just be
141 ZERO. SIZE is the size of the mode accessed in the memref. The
142 ANY is used for constants that are not +-size or 0. REG is used if
143 the forms are reg1 + reg2. */
148 INC_NEG_SIZE
, /* == +size */
149 INC_POS_SIZE
, /* == -size */
150 INC_NEG_ANY
, /* == some -constant */
151 INC_POS_ANY
, /* == some +constant */
152 INC_REG
, /* == some register */
156 /* The eight forms that pre/post inc/dec can take. */
160 SIMPLE_PRE_INC
, /* ++size */
161 SIMPLE_POST_INC
, /* size++ */
162 SIMPLE_PRE_DEC
, /* --size */
163 SIMPLE_POST_DEC
, /* size-- */
164 DISP_PRE
, /* ++con */
165 DISP_POST
, /* con++ */
170 /* Tmp mem rtx for use in cost modeling. */
173 static enum inc_state
174 set_inc_state (HOST_WIDE_INT val
, poly_int64 size
)
179 return known_eq (val
, -size
) ? INC_NEG_SIZE
: INC_NEG_ANY
;
181 return known_eq (val
, size
) ? INC_POS_SIZE
: INC_POS_ANY
;
184 /* The DECISION_TABLE that describes what form, if any, the increment
185 or decrement will take. It is a three dimensional table. The first
186 index is the type of constant or register found as the second
187 operand of the inc insn. The second index is the type of constant
188 or register found as the second operand of the memory reference (if
189 no second operand exists, 0 is used). The third index is the form
190 and location (relative to the mem reference) of inc insn. */
192 static bool initialized
= false;
193 static enum gen_form decision_table
[INC_last
][INC_last
][FORM_last
];
196 init_decision_table (void)
200 if (HAVE_PRE_INCREMENT
|| HAVE_PRE_MODIFY_DISP
)
202 /* Prefer the simple form if both are available. */
203 value
= (HAVE_PRE_INCREMENT
) ? SIMPLE_PRE_INC
: DISP_PRE
;
205 decision_table
[INC_POS_SIZE
][INC_ZERO
][FORM_PRE_ADD
] = value
;
206 decision_table
[INC_POS_SIZE
][INC_ZERO
][FORM_PRE_INC
] = value
;
208 decision_table
[INC_POS_SIZE
][INC_POS_SIZE
][FORM_POST_ADD
] = value
;
209 decision_table
[INC_POS_SIZE
][INC_POS_SIZE
][FORM_POST_INC
] = value
;
212 if (HAVE_POST_INCREMENT
|| HAVE_POST_MODIFY_DISP
)
214 /* Prefer the simple form if both are available. */
215 value
= (HAVE_POST_INCREMENT
) ? SIMPLE_POST_INC
: DISP_POST
;
217 decision_table
[INC_POS_SIZE
][INC_ZERO
][FORM_POST_ADD
] = value
;
218 decision_table
[INC_POS_SIZE
][INC_ZERO
][FORM_POST_INC
] = value
;
220 decision_table
[INC_POS_SIZE
][INC_NEG_SIZE
][FORM_PRE_ADD
] = value
;
221 decision_table
[INC_POS_SIZE
][INC_NEG_SIZE
][FORM_PRE_INC
] = value
;
224 if (HAVE_PRE_DECREMENT
|| HAVE_PRE_MODIFY_DISP
)
226 /* Prefer the simple form if both are available. */
227 value
= (HAVE_PRE_DECREMENT
) ? SIMPLE_PRE_DEC
: DISP_PRE
;
229 decision_table
[INC_NEG_SIZE
][INC_ZERO
][FORM_PRE_ADD
] = value
;
230 decision_table
[INC_NEG_SIZE
][INC_ZERO
][FORM_PRE_INC
] = value
;
232 decision_table
[INC_NEG_SIZE
][INC_NEG_SIZE
][FORM_POST_ADD
] = value
;
233 decision_table
[INC_NEG_SIZE
][INC_NEG_SIZE
][FORM_POST_INC
] = value
;
236 if (HAVE_POST_DECREMENT
|| HAVE_POST_MODIFY_DISP
)
238 /* Prefer the simple form if both are available. */
239 value
= (HAVE_POST_DECREMENT
) ? SIMPLE_POST_DEC
: DISP_POST
;
241 decision_table
[INC_NEG_SIZE
][INC_ZERO
][FORM_POST_ADD
] = value
;
242 decision_table
[INC_NEG_SIZE
][INC_ZERO
][FORM_POST_INC
] = value
;
244 decision_table
[INC_NEG_SIZE
][INC_POS_SIZE
][FORM_PRE_ADD
] = value
;
245 decision_table
[INC_NEG_SIZE
][INC_POS_SIZE
][FORM_PRE_INC
] = value
;
248 if (HAVE_PRE_MODIFY_DISP
)
250 decision_table
[INC_POS_ANY
][INC_ZERO
][FORM_PRE_ADD
] = DISP_PRE
;
251 decision_table
[INC_POS_ANY
][INC_ZERO
][FORM_PRE_INC
] = DISP_PRE
;
253 decision_table
[INC_POS_ANY
][INC_POS_ANY
][FORM_POST_ADD
] = DISP_PRE
;
254 decision_table
[INC_POS_ANY
][INC_POS_ANY
][FORM_POST_INC
] = DISP_PRE
;
256 decision_table
[INC_NEG_ANY
][INC_ZERO
][FORM_PRE_ADD
] = DISP_PRE
;
257 decision_table
[INC_NEG_ANY
][INC_ZERO
][FORM_PRE_INC
] = DISP_PRE
;
259 decision_table
[INC_NEG_ANY
][INC_NEG_ANY
][FORM_POST_ADD
] = DISP_PRE
;
260 decision_table
[INC_NEG_ANY
][INC_NEG_ANY
][FORM_POST_INC
] = DISP_PRE
;
263 if (HAVE_POST_MODIFY_DISP
)
265 decision_table
[INC_POS_ANY
][INC_ZERO
][FORM_POST_ADD
] = DISP_POST
;
266 decision_table
[INC_POS_ANY
][INC_ZERO
][FORM_POST_INC
] = DISP_POST
;
268 decision_table
[INC_POS_ANY
][INC_NEG_ANY
][FORM_PRE_ADD
] = DISP_POST
;
269 decision_table
[INC_POS_ANY
][INC_NEG_ANY
][FORM_PRE_INC
] = DISP_POST
;
271 decision_table
[INC_NEG_ANY
][INC_ZERO
][FORM_POST_ADD
] = DISP_POST
;
272 decision_table
[INC_NEG_ANY
][INC_ZERO
][FORM_POST_INC
] = DISP_POST
;
274 decision_table
[INC_NEG_ANY
][INC_POS_ANY
][FORM_PRE_ADD
] = DISP_POST
;
275 decision_table
[INC_NEG_ANY
][INC_POS_ANY
][FORM_PRE_INC
] = DISP_POST
;
278 /* This is much simpler than the other cases because we do not look
279 for the reg1-reg2 case. Note that we do not have a INC_POS_REG
280 and INC_NEG_REG states. Most of the use of such states would be
281 on a target that had an R1 - R2 update address form.
283 There is the remote possibility that you could also catch a = a +
284 b; *(a - b) as a postdecrement of (a + b). However, it is
285 unclear if *(a - b) would ever be generated on a machine that did
286 not have that kind of addressing mode. The IA-64 and RS6000 will
287 not do this, and I cannot speak for any other. If any
288 architecture does have an a-b update for, these cases should be
290 if (HAVE_PRE_MODIFY_REG
)
292 decision_table
[INC_REG
][INC_ZERO
][FORM_PRE_ADD
] = REG_PRE
;
293 decision_table
[INC_REG
][INC_ZERO
][FORM_PRE_INC
] = REG_PRE
;
295 decision_table
[INC_REG
][INC_REG
][FORM_POST_ADD
] = REG_PRE
;
296 decision_table
[INC_REG
][INC_REG
][FORM_POST_INC
] = REG_PRE
;
299 if (HAVE_POST_MODIFY_REG
)
301 decision_table
[INC_REG
][INC_ZERO
][FORM_POST_ADD
] = REG_POST
;
302 decision_table
[INC_REG
][INC_ZERO
][FORM_POST_INC
] = REG_POST
;
308 /* Parsed fields of an inc insn of the form "reg_res = reg0+reg1" or
309 "reg_res = reg0+c". */
311 static struct inc_insn
313 rtx_insn
*insn
; /* The insn being parsed. */
314 rtx pat
; /* The pattern of the insn. */
315 bool reg1_is_const
; /* True if reg1 is const, false if reg1 is a reg. */
320 enum inc_state reg1_state
;/* The form of the const if reg1 is a const. */
321 HOST_WIDE_INT reg1_val
;/* Value if reg1 is const. */
325 /* Dump the parsed inc insn to FILE. */
328 dump_inc_insn (FILE *file
)
330 const char *f
= ((inc_insn
.form
== FORM_PRE_ADD
)
331 || (inc_insn
.form
== FORM_PRE_INC
)) ? "pre" : "post";
333 dump_insn_slim (file
, inc_insn
.insn
);
335 switch (inc_insn
.form
)
339 if (inc_insn
.reg1_is_const
)
340 fprintf (file
, "found %s add(%d) r[%d]=r[%d]+%d\n",
341 f
, INSN_UID (inc_insn
.insn
),
342 REGNO (inc_insn
.reg_res
),
343 REGNO (inc_insn
.reg0
), (int) inc_insn
.reg1_val
);
345 fprintf (file
, "found %s add(%d) r[%d]=r[%d]+r[%d]\n",
346 f
, INSN_UID (inc_insn
.insn
),
347 REGNO (inc_insn
.reg_res
),
348 REGNO (inc_insn
.reg0
), REGNO (inc_insn
.reg1
));
353 if (inc_insn
.reg1_is_const
)
354 fprintf (file
, "found %s inc(%d) r[%d]+=%d\n",
355 f
, INSN_UID (inc_insn
.insn
),
356 REGNO (inc_insn
.reg_res
), (int) inc_insn
.reg1_val
);
358 fprintf (file
, "found %s inc(%d) r[%d]+=r[%d]\n",
359 f
, INSN_UID (inc_insn
.insn
),
360 REGNO (inc_insn
.reg_res
), REGNO (inc_insn
.reg1
));
369 /* Parsed fields of a mem ref of the form "*(reg0+reg1)" or "*(reg0+c)". */
371 static struct mem_insn
373 rtx_insn
*insn
; /* The insn being parsed. */
374 rtx pat
; /* The pattern of the insn. */
375 rtx
*mem_loc
; /* The address of the field that holds the mem */
376 /* that is to be replaced. */
377 bool reg1_is_const
; /* True if reg1 is const, false if reg1 is a reg. */
379 rtx reg1
; /* This is either a reg or a const depending on
381 enum inc_state reg1_state
;/* The form of the const if reg1 is a const. */
382 HOST_WIDE_INT reg1_val
;/* Value if reg1 is const. */
386 /* Dump the parsed mem insn to FILE. */
389 dump_mem_insn (FILE *file
)
391 dump_insn_slim (file
, mem_insn
.insn
);
393 if (mem_insn
.reg1_is_const
)
394 fprintf (file
, "found mem(%d) *(r[%d]+%d)\n",
395 INSN_UID (mem_insn
.insn
),
396 REGNO (mem_insn
.reg0
), (int) mem_insn
.reg1_val
);
398 fprintf (file
, "found mem(%d) *(r[%d]+r[%d])\n",
399 INSN_UID (mem_insn
.insn
),
400 REGNO (mem_insn
.reg0
), REGNO (mem_insn
.reg1
));
404 /* The following three arrays contain pointers to instructions. They
405 are indexed by REGNO. At any point in the basic block where we are
406 looking these three arrays contain, respectively, the next insn
407 that uses REGNO, the next inc or add insn that uses REGNO and the
408 next insn that sets REGNO.
410 The arrays are not cleared when we move from block to block so
411 whenever an insn is retrieved from these arrays, it's block number
412 must be compared with the current block.
415 static rtx_insn
**reg_next_debug_use
= NULL
;
416 static rtx_insn
**reg_next_use
= NULL
;
417 static rtx_insn
**reg_next_inc_use
= NULL
;
418 static rtx_insn
**reg_next_def
= NULL
;
421 /* Move dead note that match PATTERN to TO_INSN from FROM_INSN. We do
422 not really care about moving any other notes from the inc or add
423 insn. Moving the REG_EQUAL and REG_EQUIV is clearly wrong and it
424 does not appear that there are any other kinds of relevant notes. */
427 move_dead_notes (rtx_insn
*to_insn
, rtx_insn
*from_insn
, rtx pattern
)
431 rtx prev_note
= NULL
;
433 for (note
= REG_NOTES (from_insn
); note
; note
= next_note
)
435 next_note
= XEXP (note
, 1);
437 if ((REG_NOTE_KIND (note
) == REG_DEAD
)
438 && pattern
== XEXP (note
, 0))
440 XEXP (note
, 1) = REG_NOTES (to_insn
);
441 REG_NOTES (to_insn
) = note
;
443 XEXP (prev_note
, 1) = next_note
;
445 REG_NOTES (from_insn
) = next_note
;
447 else prev_note
= note
;
451 /* Change mem_insn.mem_loc so that uses NEW_ADDR which has an
452 increment of INC_REG. To have reached this point, the change is a
453 legitimate one from a dataflow point of view. The only questions
454 are is this a valid change to the instruction and is this a
455 profitable change to the instruction. */
458 attempt_change (rtx new_addr
, rtx inc_reg
)
460 /* There are four cases: For the two cases that involve an add
461 instruction, we are going to have to delete the add and insert a
462 mov. We are going to assume that the mov is free. This is
463 fairly early in the backend and there are a lot of opportunities
464 for removing that move later. In particular, there is the case
465 where the move may be dead, this is what dead code elimination
466 passes are for. The two cases where we have an inc insn will be
469 basic_block bb
= BLOCK_FOR_INSN (mem_insn
.insn
);
470 rtx_insn
*mov_insn
= NULL
;
472 rtx mem
= *mem_insn
.mem_loc
;
473 machine_mode mode
= GET_MODE (mem
);
474 int align
= MEM_ALIGN (mem
);
478 bool speed
= optimize_bb_for_speed_p (bb
);
480 PUT_MODE (mem_tmp
, mode
);
481 XEXP (mem_tmp
, 0) = new_addr
;
482 set_mem_align (mem_tmp
, align
);
484 old_cost
= (set_src_cost (mem
, mode
, speed
)
485 + set_rtx_cost (PATTERN (inc_insn
.insn
), speed
));
487 new_cost
= set_src_cost (mem_tmp
, mode
, speed
);
489 /* In the FORM_PRE_ADD and FORM_POST_ADD cases we emit an extra move
490 whose cost we should account for. */
491 if (inc_insn
.form
== FORM_PRE_ADD
492 || inc_insn
.form
== FORM_POST_ADD
)
495 emit_move_insn (inc_insn
.reg_res
, inc_insn
.reg0
);
496 mov_insn
= get_insns ();
498 new_cost
+= seq_cost (mov_insn
, speed
);
501 /* The first item of business is to see if this is profitable. */
502 if (old_cost
< new_cost
)
505 fprintf (dump_file
, "cost failure old=%d new=%d\n", old_cost
, new_cost
);
509 /* Jump through a lot of hoops to keep the attributes up to date. We
510 do not want to call one of the change address variants that take
511 an offset even though we know the offset in many cases. These
512 assume you are changing where the address is pointing by the
514 new_mem
= replace_equiv_address_nv (mem
, new_addr
);
515 if (! validate_change (mem_insn
.insn
, mem_insn
.mem_loc
, new_mem
, 0))
518 fprintf (dump_file
, "validation failure\n");
522 /* From here to the end of the function we are committed to the
523 change, i.e. nothing fails. Generate any necessary movs, move
524 any regnotes, and fix up the reg_next_{use,inc_use,def}. */
525 switch (inc_insn
.form
)
528 /* Replace the addition with a move. Do it at the location of
529 the addition since the operand of the addition may change
530 before the memory reference. */
531 gcc_assert (mov_insn
);
532 emit_insn_before (mov_insn
, inc_insn
.insn
);
533 regno
= REGNO (inc_insn
.reg0
);
534 /* ??? Could REGNO possibly be used in MEM_INSN other than in
535 the MEM address, and still die there, so that move_dead_notes
536 would incorrectly move the note? */
537 if (reg_next_use
[regno
] == mem_insn
.insn
)
538 move_dead_notes (mov_insn
, mem_insn
.insn
, inc_insn
.reg0
);
540 move_dead_notes (mov_insn
, inc_insn
.insn
, inc_insn
.reg0
);
542 regno
= REGNO (inc_insn
.reg_res
);
543 if (reg_next_debug_use
&& reg_next_debug_use
[regno
]
544 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
)
546 rtx adjres
= gen_rtx_PLUS (GET_MODE (inc_insn
.reg_res
),
547 inc_insn
.reg_res
, inc_insn
.reg1
);
549 fprintf (dump_file
, "adjusting debug insns\n");
550 propagate_for_debug (PREV_INSN (reg_next_debug_use
[regno
]),
552 inc_insn
.reg_res
, adjres
, bb
);
553 reg_next_debug_use
[regno
] = NULL
;
555 reg_next_def
[regno
] = mov_insn
;
556 reg_next_use
[regno
] = NULL
;
558 regno
= REGNO (inc_insn
.reg0
);
559 if (reg_next_debug_use
&& reg_next_debug_use
[regno
]
560 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
561 && find_reg_note (mov_insn
, REG_DEAD
, inc_insn
.reg0
))
564 fprintf (dump_file
, "remapping debug insns\n");
565 propagate_for_debug (PREV_INSN (reg_next_debug_use
[regno
]),
567 inc_insn
.reg0
, inc_insn
.reg_res
, bb
);
568 reg_next_debug_use
[regno
] = NULL
;
570 reg_next_use
[regno
] = mov_insn
;
571 df_recompute_luids (bb
);
575 regno
= REGNO (inc_insn
.reg_res
);
576 if (reg_next_debug_use
&& reg_next_debug_use
[regno
]
577 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
)
579 rtx adjres
= gen_rtx_MINUS (GET_MODE (inc_insn
.reg_res
),
580 inc_insn
.reg_res
, inc_insn
.reg1
);
582 fprintf (dump_file
, "adjusting debug insns\n");
583 propagate_for_debug (PREV_INSN (reg_next_debug_use
[regno
]),
585 inc_insn
.reg_res
, adjres
, bb
);
586 reg_next_debug_use
[regno
] = NULL
;
588 if (reg_next_use
[regno
] == reg_next_inc_use
[regno
])
589 reg_next_inc_use
[regno
] = NULL
;
593 regno
= REGNO (inc_insn
.reg_res
);
594 /* Despite the fall-through, we won't run this twice: we'll have
595 already cleared reg_next_debug_use[regno] before falling
597 if (reg_next_debug_use
&& reg_next_debug_use
[regno
]
598 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
)
600 rtx adjres
= gen_rtx_PLUS (GET_MODE (inc_insn
.reg_res
),
601 inc_insn
.reg_res
, inc_insn
.reg1
);
603 fprintf (dump_file
, "adjusting debug insns\n");
604 propagate_for_debug (PREV_INSN (reg_next_debug_use
[regno
]),
606 inc_insn
.reg_res
, adjres
, bb
);
607 if (DF_INSN_LUID (mem_insn
.insn
)
608 < DF_INSN_LUID (reg_next_debug_use
[regno
]))
609 reg_next_debug_use
[regno
] = NULL
;
611 reg_next_def
[regno
] = mem_insn
.insn
;
612 reg_next_use
[regno
] = NULL
;
617 gcc_assert (mov_insn
);
618 emit_insn_before (mov_insn
, mem_insn
.insn
);
619 move_dead_notes (mov_insn
, inc_insn
.insn
, inc_insn
.reg0
);
621 /* Do not move anything to the mov insn because the instruction
622 pointer for the main iteration has not yet hit that. It is
623 still pointing to the mem insn. */
624 regno
= REGNO (inc_insn
.reg_res
);
625 /* The pseudo is now set earlier, so it must have been dead in
626 that range, and dead registers cannot be referenced in debug
628 gcc_assert (!(reg_next_debug_use
&& reg_next_debug_use
[regno
]
629 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
));
630 reg_next_def
[regno
] = mem_insn
.insn
;
631 reg_next_use
[regno
] = NULL
;
633 regno
= REGNO (inc_insn
.reg0
);
634 if (reg_next_debug_use
&& reg_next_debug_use
[regno
]
635 && BLOCK_FOR_INSN (reg_next_debug_use
[regno
]) == bb
636 && find_reg_note (mov_insn
, REG_DEAD
, inc_insn
.reg0
))
639 fprintf (dump_file
, "remapping debug insns\n");
640 propagate_for_debug (PREV_INSN (reg_next_debug_use
[regno
]),
642 inc_insn
.reg0
, inc_insn
.reg_res
, bb
);
643 reg_next_debug_use
[regno
] = NULL
;
645 reg_next_use
[regno
] = mem_insn
.insn
;
646 if ((reg_next_use
[regno
] == reg_next_inc_use
[regno
])
647 || (reg_next_inc_use
[regno
] == inc_insn
.insn
))
648 reg_next_inc_use
[regno
] = NULL
;
649 df_recompute_luids (bb
);
657 if (!inc_insn
.reg1_is_const
)
659 regno
= REGNO (inc_insn
.reg1
);
660 reg_next_use
[regno
] = mem_insn
.insn
;
661 if ((reg_next_use
[regno
] == reg_next_inc_use
[regno
])
662 || (reg_next_inc_use
[regno
] == inc_insn
.insn
))
663 reg_next_inc_use
[regno
] = NULL
;
666 delete_insn (inc_insn
.insn
);
668 if (dump_file
&& mov_insn
)
670 fprintf (dump_file
, "inserting mov ");
671 dump_insn_slim (dump_file
, mov_insn
);
674 /* Record that this insn has an implicit side effect. */
675 add_reg_note (mem_insn
.insn
, REG_INC
, inc_reg
);
679 fprintf (dump_file
, "****success ");
680 dump_insn_slim (dump_file
, mem_insn
.insn
);
687 /* Try to combine the instruction in INC_INSN with the instruction in
688 MEM_INSN. First the form is determined using the DECISION_TABLE
689 and the results of parsing the INC_INSN and the MEM_INSN.
690 Assuming the form is ok, a prototype new address is built which is
691 passed to ATTEMPT_CHANGE for final processing. */
696 enum gen_form gen_form
;
697 rtx mem
= *mem_insn
.mem_loc
;
698 rtx inc_reg
= inc_insn
.form
== FORM_POST_ADD
?
699 inc_insn
.reg_res
: mem_insn
.reg0
;
701 /* The width of the mem being accessed. */
702 poly_int64 size
= GET_MODE_SIZE (GET_MODE (mem
));
703 rtx_insn
*last_insn
= NULL
;
704 machine_mode reg_mode
= GET_MODE (inc_reg
);
706 switch (inc_insn
.form
)
710 last_insn
= mem_insn
.insn
;
714 last_insn
= inc_insn
.insn
;
721 /* Cannot handle auto inc of the stack. */
722 if (inc_reg
== stack_pointer_rtx
)
725 fprintf (dump_file
, "cannot inc stack %d failure\n", REGNO (inc_reg
));
729 /* Look to see if the inc register is dead after the memory
730 reference. If it is, do not do the combination. */
731 if (find_regno_note (last_insn
, REG_DEAD
, REGNO (inc_reg
)))
734 fprintf (dump_file
, "dead failure %d\n", REGNO (inc_reg
));
738 mem_insn
.reg1_state
= (mem_insn
.reg1_is_const
)
739 ? set_inc_state (mem_insn
.reg1_val
, size
) : INC_REG
;
740 inc_insn
.reg1_state
= (inc_insn
.reg1_is_const
)
741 ? set_inc_state (inc_insn
.reg1_val
, size
) : INC_REG
;
743 /* Now get the form that we are generating. */
744 gen_form
= decision_table
745 [inc_insn
.reg1_state
][mem_insn
.reg1_state
][inc_insn
.form
];
747 if (dbg_cnt (auto_inc_dec
) == false)
756 case SIMPLE_PRE_INC
: /* ++size */
758 fprintf (dump_file
, "trying SIMPLE_PRE_INC\n");
759 return attempt_change (gen_rtx_PRE_INC (reg_mode
, inc_reg
), inc_reg
);
761 case SIMPLE_POST_INC
: /* size++ */
763 fprintf (dump_file
, "trying SIMPLE_POST_INC\n");
764 return attempt_change (gen_rtx_POST_INC (reg_mode
, inc_reg
), inc_reg
);
766 case SIMPLE_PRE_DEC
: /* --size */
768 fprintf (dump_file
, "trying SIMPLE_PRE_DEC\n");
769 return attempt_change (gen_rtx_PRE_DEC (reg_mode
, inc_reg
), inc_reg
);
771 case SIMPLE_POST_DEC
: /* size-- */
773 fprintf (dump_file
, "trying SIMPLE_POST_DEC\n");
774 return attempt_change (gen_rtx_POST_DEC (reg_mode
, inc_reg
), inc_reg
);
776 case DISP_PRE
: /* ++con */
778 fprintf (dump_file
, "trying DISP_PRE\n");
779 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode
,
781 gen_rtx_PLUS (reg_mode
,
786 case DISP_POST
: /* con++ */
788 fprintf (dump_file
, "trying POST_DISP\n");
789 return attempt_change (gen_rtx_POST_MODIFY (reg_mode
,
791 gen_rtx_PLUS (reg_mode
,
796 case REG_PRE
: /* ++reg */
798 fprintf (dump_file
, "trying PRE_REG\n");
799 return attempt_change (gen_rtx_PRE_MODIFY (reg_mode
,
801 gen_rtx_PLUS (reg_mode
,
806 case REG_POST
: /* reg++ */
808 fprintf (dump_file
, "trying POST_REG\n");
809 return attempt_change (gen_rtx_POST_MODIFY (reg_mode
,
811 gen_rtx_PLUS (reg_mode
,
818 /* Return the next insn that uses (if reg_next_use is passed in
819 NEXT_ARRAY) or defines (if reg_next_def is passed in NEXT_ARRAY)
823 get_next_ref (int regno
, basic_block bb
, rtx_insn
**next_array
)
825 rtx_insn
*insn
= next_array
[regno
];
827 /* Lazy about cleaning out the next_arrays. */
828 if (insn
&& BLOCK_FOR_INSN (insn
) != bb
)
830 next_array
[regno
] = NULL
;
838 /* Return true if INSN is of a form "a = b op c" where a and b are
839 regs. op is + if c is a reg and +|- if c is a const. Fill in
840 INC_INSN with what is found.
842 This function is called in two contexts, if BEFORE_MEM is true,
843 this is called for each insn in the basic block. If BEFORE_MEM is
844 false, it is called for the instruction in the block that uses the
845 index register for some memory reference that is currently being
849 parse_add_or_inc (rtx_insn
*insn
, bool before_mem
)
851 rtx pat
= single_set (insn
);
855 /* Result must be single reg. */
856 if (!REG_P (SET_DEST (pat
)))
859 if ((GET_CODE (SET_SRC (pat
)) != PLUS
)
860 && (GET_CODE (SET_SRC (pat
)) != MINUS
))
863 if (!REG_P (XEXP (SET_SRC (pat
), 0)))
866 inc_insn
.insn
= insn
;
868 inc_insn
.reg_res
= SET_DEST (pat
);
869 inc_insn
.reg0
= XEXP (SET_SRC (pat
), 0);
871 /* Block any auto increment of the frame pointer since it expands into
872 an addition and cannot be removed by copy propagation. */
873 if (inc_insn
.reg0
== frame_pointer_rtx
)
876 if (rtx_equal_p (inc_insn
.reg_res
, inc_insn
.reg0
))
877 inc_insn
.form
= before_mem
? FORM_PRE_INC
: FORM_POST_INC
;
879 inc_insn
.form
= before_mem
? FORM_PRE_ADD
: FORM_POST_ADD
;
881 if (CONST_INT_P (XEXP (SET_SRC (pat
), 1)))
883 /* Process a = b + c where c is a const. */
884 inc_insn
.reg1_is_const
= true;
885 if (GET_CODE (SET_SRC (pat
)) == PLUS
)
887 inc_insn
.reg1
= XEXP (SET_SRC (pat
), 1);
888 inc_insn
.reg1_val
= INTVAL (inc_insn
.reg1
);
892 inc_insn
.reg1_val
= -INTVAL (XEXP (SET_SRC (pat
), 1));
893 inc_insn
.reg1
= GEN_INT (inc_insn
.reg1_val
);
897 else if ((HAVE_PRE_MODIFY_REG
|| HAVE_POST_MODIFY_REG
)
898 && (REG_P (XEXP (SET_SRC (pat
), 1)))
899 && GET_CODE (SET_SRC (pat
)) == PLUS
)
901 /* Process a = b + c where c is a reg. */
902 inc_insn
.reg1
= XEXP (SET_SRC (pat
), 1);
903 inc_insn
.reg1_is_const
= false;
905 if (inc_insn
.form
== FORM_PRE_INC
906 || inc_insn
.form
== FORM_POST_INC
)
908 else if (rtx_equal_p (inc_insn
.reg_res
, inc_insn
.reg1
))
910 /* Reverse the two operands and turn *_ADD into *_INC since
912 std::swap (inc_insn
.reg0
, inc_insn
.reg1
);
913 inc_insn
.form
= before_mem
? FORM_PRE_INC
: FORM_POST_INC
;
924 /* A recursive function that checks all of the mem uses in
925 ADDRESS_OF_X to see if any single one of them is compatible with
926 what has been found in inc_insn. To avoid accidental matches, we
927 will only find MEMs with FINDREG, be it inc_insn.reg_res, be it
930 -1 is returned for success. 0 is returned if nothing was found and
931 1 is returned for failure. */
934 find_address (rtx
*address_of_x
, rtx findreg
)
936 rtx x
= *address_of_x
;
937 enum rtx_code code
= GET_CODE (x
);
938 const char *const fmt
= GET_RTX_FORMAT (code
);
943 if (code
== MEM
&& findreg
== inc_insn
.reg_res
944 && rtx_equal_p (XEXP (x
, 0), inc_insn
.reg_res
))
946 /* Match with *reg_res. */
947 mem_insn
.mem_loc
= address_of_x
;
948 mem_insn
.reg0
= inc_insn
.reg_res
;
949 mem_insn
.reg1_is_const
= true;
950 mem_insn
.reg1_val
= 0;
951 mem_insn
.reg1
= GEN_INT (0);
954 if (code
== MEM
&& inc_insn
.reg1_is_const
&& inc_insn
.reg0
955 && findreg
== inc_insn
.reg0
956 && rtx_equal_p (XEXP (x
, 0), inc_insn
.reg0
))
958 /* Match with *reg0, assumed to be equivalent to
959 *(reg_res - reg1_val); callers must check whether this is the case. */
960 mem_insn
.mem_loc
= address_of_x
;
961 mem_insn
.reg0
= inc_insn
.reg_res
;
962 mem_insn
.reg1_is_const
= true;
963 mem_insn
.reg1_val
= -inc_insn
.reg1_val
;
964 mem_insn
.reg1
= GEN_INT (mem_insn
.reg1_val
);
967 if (code
== MEM
&& findreg
== inc_insn
.reg_res
968 && GET_CODE (XEXP (x
, 0)) == PLUS
969 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), inc_insn
.reg_res
))
971 rtx b
= XEXP (XEXP (x
, 0), 1);
972 mem_insn
.mem_loc
= address_of_x
;
973 mem_insn
.reg0
= inc_insn
.reg_res
;
975 mem_insn
.reg1_is_const
= inc_insn
.reg1_is_const
;
978 /* Match with *(reg0 + reg1) where reg1 is a const. */
979 HOST_WIDE_INT val
= INTVAL (b
);
980 if (inc_insn
.reg1_is_const
981 && (inc_insn
.reg1_val
== val
|| inc_insn
.reg1_val
== -val
))
983 mem_insn
.reg1_val
= val
;
987 else if (!inc_insn
.reg1_is_const
988 && rtx_equal_p (inc_insn
.reg1
, b
))
989 /* Match with *(reg0 + reg1). */
993 if (code
== SIGN_EXTRACT
|| code
== ZERO_EXTRACT
)
995 /* If REG occurs inside a MEM used in a bit-field reference,
996 that is unacceptable. */
997 if (find_address (&XEXP (x
, 0), findreg
))
1001 if (x
== inc_insn
.reg_res
)
1004 /* Time for some deep diving. */
1005 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1009 tem
= find_address (&XEXP (x
, i
), findreg
);
1010 /* If this is the first use, let it go so the rest of the
1011 insn can be checked. */
1015 /* More than one match was found. */
1018 else if (fmt
[i
] == 'E')
1021 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1023 tem
= find_address (&XVECEXP (x
, i
, j
), findreg
);
1024 /* If this is the first use, let it go so the rest of
1025 the insn can be checked. */
1029 /* More than one match was found. */
1037 /* Once a suitable mem reference has been found and the MEM_INSN
1038 structure has been filled in, FIND_INC is called to see if there is
1039 a suitable add or inc insn that follows the mem reference and
1040 determine if it is suitable to merge.
1042 In the case where the MEM_INSN has two registers in the reference,
1043 this function may be called recursively. The first time looking
1044 for an add of the first register, and if that fails, looking for an
1045 add of the second register. The FIRST_TRY parameter is used to
1046 only allow the parameters to be reversed once. */
1049 find_inc (bool first_try
)
1052 basic_block bb
= BLOCK_FOR_INSN (mem_insn
.insn
);
1053 rtx_insn
*other_insn
;
1056 /* Make sure this reg appears only once in this insn. */
1057 if (count_occurrences (PATTERN (mem_insn
.insn
), mem_insn
.reg0
, 1) != 1)
1060 fprintf (dump_file
, "mem count failure\n");
1065 dump_mem_insn (dump_file
);
1067 /* Find the next use that is an inc. */
1068 insn
= get_next_ref (REGNO (mem_insn
.reg0
),
1069 BLOCK_FOR_INSN (mem_insn
.insn
),
1074 /* Even though we know the next use is an add or inc because it came
1075 from the reg_next_inc_use, we must still reparse. */
1076 if (!parse_add_or_inc (insn
, false))
1078 /* Next use was not an add. Look for one extra case. It could be
1085 if we reverse the operands in the mem ref we would
1086 find this. Only try it once though. */
1087 if (first_try
&& !mem_insn
.reg1_is_const
)
1089 std::swap (mem_insn
.reg0
, mem_insn
.reg1
);
1090 return find_inc (false);
1096 /* Need to assure that none of the operands of the inc instruction are
1097 assigned to by the mem insn. */
1098 FOR_EACH_INSN_DEF (def
, mem_insn
.insn
)
1100 unsigned int regno
= DF_REF_REGNO (def
);
1101 if ((regno
== REGNO (inc_insn
.reg0
))
1102 || (regno
== REGNO (inc_insn
.reg_res
)))
1105 fprintf (dump_file
, "inc conflicts with store failure.\n");
1108 if (!inc_insn
.reg1_is_const
&& (regno
== REGNO (inc_insn
.reg1
)))
1111 fprintf (dump_file
, "inc conflicts with store failure.\n");
1117 dump_inc_insn (dump_file
);
1119 if (inc_insn
.form
== FORM_POST_ADD
)
1121 /* Make sure that there is no insn that assigns to inc_insn.res
1122 between the mem_insn and the inc_insn. */
1123 rtx_insn
*other_insn
= get_next_ref (REGNO (inc_insn
.reg_res
),
1124 BLOCK_FOR_INSN (mem_insn
.insn
),
1126 if (other_insn
!= inc_insn
.insn
)
1130 "result of add is assigned to between mem and inc insns.\n");
1134 other_insn
= get_next_ref (REGNO (inc_insn
.reg_res
),
1135 BLOCK_FOR_INSN (mem_insn
.insn
),
1138 && (other_insn
!= inc_insn
.insn
)
1139 && (DF_INSN_LUID (inc_insn
.insn
) > DF_INSN_LUID (other_insn
)))
1143 "result of add is used between mem and inc insns.\n");
1147 /* For the post_add to work, the result_reg of the inc must not be
1148 used in the mem insn since this will become the new index
1150 if (reg_overlap_mentioned_p (inc_insn
.reg_res
, PATTERN (mem_insn
.insn
)))
1153 fprintf (dump_file
, "base reg replacement failure.\n");
1158 if (mem_insn
.reg1_is_const
)
1160 if (mem_insn
.reg1_val
== 0)
1162 if (!inc_insn
.reg1_is_const
)
1164 /* The mem looks like *r0 and the rhs of the add has two
1166 int luid
= DF_INSN_LUID (inc_insn
.insn
);
1167 if (inc_insn
.form
== FORM_POST_ADD
)
1169 /* The trick is that we are not going to increment r0,
1170 we are going to increment the result of the add insn.
1171 For this trick to be correct, the result reg of
1172 the inc must be a valid addressing reg. */
1173 addr_space_t as
= MEM_ADDR_SPACE (*mem_insn
.mem_loc
);
1174 if (GET_MODE (inc_insn
.reg_res
)
1175 != targetm
.addr_space
.address_mode (as
))
1178 fprintf (dump_file
, "base reg mode failure.\n");
1182 /* We also need to make sure that the next use of
1183 inc result is after the inc. */
1185 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_use
);
1186 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1189 if (!rtx_equal_p (mem_insn
.reg0
, inc_insn
.reg0
))
1190 std::swap (inc_insn
.reg0
, inc_insn
.reg1
);
1194 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_def
);
1195 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1199 /* Both the inc/add and the mem have a constant. Need to check
1200 that the constants are ok. */
1201 else if ((mem_insn
.reg1_val
!= inc_insn
.reg1_val
)
1202 && (mem_insn
.reg1_val
!= -inc_insn
.reg1_val
))
1207 /* The mem insn is of the form *(a + b) where a and b are both
1208 regs. It may be that in order to match the add or inc we
1209 need to treat it as if it was *(b + a). It may also be that
1210 the add is of the form a + c where c does not match b and
1211 then we just abandon this. */
1213 int luid
= DF_INSN_LUID (inc_insn
.insn
);
1214 rtx_insn
*other_insn
;
1216 /* Make sure this reg appears only once in this insn. */
1217 if (count_occurrences (PATTERN (mem_insn
.insn
), mem_insn
.reg1
, 1) != 1)
1220 if (inc_insn
.form
== FORM_POST_ADD
)
1222 /* For this trick to be correct, the result reg of the inc
1223 must be a valid addressing reg. */
1224 addr_space_t as
= MEM_ADDR_SPACE (*mem_insn
.mem_loc
);
1225 if (GET_MODE (inc_insn
.reg_res
)
1226 != targetm
.addr_space
.address_mode (as
))
1229 fprintf (dump_file
, "base reg mode failure.\n");
1233 if (rtx_equal_p (mem_insn
.reg0
, inc_insn
.reg0
))
1235 if (!rtx_equal_p (mem_insn
.reg1
, inc_insn
.reg1
))
1237 /* See comment above on find_inc (false) call. */
1240 std::swap (mem_insn
.reg0
, mem_insn
.reg1
);
1241 return find_inc (false);
1247 /* Need to check that there are no assignments to b
1248 before the add insn. */
1250 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_def
);
1251 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1253 /* All ok for the next step. */
1257 /* We know that mem_insn.reg0 must equal inc_insn.reg1
1258 or else we would not have found the inc insn. */
1259 std::swap (mem_insn
.reg0
, mem_insn
.reg1
);
1260 if (!rtx_equal_p (mem_insn
.reg0
, inc_insn
.reg0
))
1262 /* See comment above on find_inc (false) call. */
1264 return find_inc (false);
1268 /* To have gotten here know that.
1273 We also know that the lhs of the inc is not b or a. We
1274 need to make sure that there are no assignments to b
1275 between the mem ref and the inc. */
1278 = get_next_ref (REGNO (inc_insn
.reg0
), bb
, reg_next_def
);
1279 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1283 /* Need to check that the next use of the add result is later than
1284 add insn since this will be the reg incremented. */
1286 = get_next_ref (REGNO (inc_insn
.reg_res
), bb
, reg_next_use
);
1287 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1290 else /* FORM_POST_INC. There is less to check here because we
1291 know that operands must line up. */
1293 if (!rtx_equal_p (mem_insn
.reg1
, inc_insn
.reg1
))
1294 /* See comment above on find_inc (false) call. */
1298 std::swap (mem_insn
.reg0
, mem_insn
.reg1
);
1299 return find_inc (false);
1305 /* To have gotten here know that.
1310 We also know that the lhs of the inc is not b. We need to make
1311 sure that there are no assignments to b between the mem ref and
1314 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_def
);
1315 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1320 if (inc_insn
.form
== FORM_POST_INC
)
1323 = get_next_ref (REGNO (inc_insn
.reg0
), bb
, reg_next_use
);
1324 /* When we found inc_insn, we were looking for the
1325 next add or inc, not the next insn that used the
1326 reg. Because we are going to increment the reg
1327 in this form, we need to make sure that there
1328 were no intervening uses of reg. */
1329 if (inc_insn
.insn
!= other_insn
)
1333 return try_merge ();
1337 /* A recursive function that walks ADDRESS_OF_X to find all of the mem
1338 uses in pat that could be used as an auto inc or dec. It then
1339 calls FIND_INC for each one. */
1342 find_mem (rtx
*address_of_x
)
1344 rtx x
= *address_of_x
;
1345 enum rtx_code code
= GET_CODE (x
);
1346 const char *const fmt
= GET_RTX_FORMAT (code
);
1349 if (code
== MEM
&& REG_P (XEXP (x
, 0)))
1351 /* Match with *reg0. */
1352 mem_insn
.mem_loc
= address_of_x
;
1353 mem_insn
.reg0
= XEXP (x
, 0);
1354 mem_insn
.reg1_is_const
= true;
1355 mem_insn
.reg1_val
= 0;
1356 mem_insn
.reg1
= GEN_INT (0);
1357 if (find_inc (true))
1360 if (code
== MEM
&& GET_CODE (XEXP (x
, 0)) == PLUS
1361 && REG_P (XEXP (XEXP (x
, 0), 0)))
1363 rtx reg1
= XEXP (XEXP (x
, 0), 1);
1364 mem_insn
.mem_loc
= address_of_x
;
1365 mem_insn
.reg0
= XEXP (XEXP (x
, 0), 0);
1366 mem_insn
.reg1
= reg1
;
1367 if (CONST_INT_P (reg1
))
1369 mem_insn
.reg1_is_const
= true;
1370 /* Match with *(reg0 + c) where c is a const. */
1371 mem_insn
.reg1_val
= INTVAL (reg1
);
1372 if (find_inc (true))
1375 else if (REG_P (reg1
))
1377 /* Match with *(reg0 + reg1). */
1378 mem_insn
.reg1_is_const
= false;
1379 if (find_inc (true))
1384 if (code
== SIGN_EXTRACT
|| code
== ZERO_EXTRACT
)
1386 /* If REG occurs inside a MEM used in a bit-field reference,
1387 that is unacceptable. */
1391 /* Time for some deep diving. */
1392 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1396 if (find_mem (&XEXP (x
, i
)))
1399 else if (fmt
[i
] == 'E')
1402 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1403 if (find_mem (&XVECEXP (x
, i
, j
)))
1411 /* Try to combine all incs and decs by constant values with memory
1412 references in BB. */
1415 merge_in_block (int max_reg
, basic_block bb
)
1419 int success_in_block
= 0;
1422 fprintf (dump_file
, "\n\nstarting bb %d\n", bb
->index
);
1424 FOR_BB_INSNS_REVERSE_SAFE (bb
, insn
, curr
)
1426 bool insn_is_add_or_inc
= true;
1428 if (!NONDEBUG_INSN_P (insn
))
1430 if (DEBUG_BIND_INSN_P (insn
))
1432 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
1436 dump_insn_slim (dump_file
, insn
);
1438 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
1439 reg_next_debug_use
[DF_REF_REGNO (use
)] = insn
;
1444 /* Reload should handle auto-inc within a jump correctly, while LRA
1445 is known to have issues with autoinc. */
1446 if (JUMP_P (insn
) && targetm
.lra_p ())
1450 dump_insn_slim (dump_file
, insn
);
1452 /* Does this instruction increment or decrement a register? */
1453 if (parse_add_or_inc (insn
, true))
1455 int regno
= REGNO (inc_insn
.reg_res
);
1456 /* Cannot handle case where there are three separate regs
1457 before a mem ref. Too many moves would be needed to be
1459 if ((inc_insn
.form
== FORM_PRE_INC
) || inc_insn
.reg1_is_const
)
1461 mem_insn
.insn
= get_next_ref (regno
, bb
, reg_next_use
);
1465 if (!inc_insn
.reg1_is_const
)
1467 /* We are only here if we are going to try a
1468 HAVE_*_MODIFY_REG type transformation. c is a
1469 reg and we must sure that the path from the
1470 inc_insn to the mem_insn.insn is both def and use
1471 clear of c because the inc insn is going to move
1472 into the mem_insn.insn. */
1473 int luid
= DF_INSN_LUID (mem_insn
.insn
);
1474 rtx_insn
*other_insn
1475 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_use
);
1477 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1481 = get_next_ref (REGNO (inc_insn
.reg1
), bb
, reg_next_def
);
1483 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1488 dump_inc_insn (dump_file
);
1490 if (ok
&& find_address (&PATTERN (mem_insn
.insn
),
1491 inc_insn
.reg_res
) == -1)
1494 dump_mem_insn (dump_file
);
1498 insn_is_add_or_inc
= false;
1503 if (insn_is_add_or_inc
1504 /* find_address will only recognize an address
1505 with a reg0 that's not reg_res when
1506 reg1_is_const, so cut it off early if we
1507 already know it won't match. */
1508 && inc_insn
.reg1_is_const
1510 && inc_insn
.reg0
!= inc_insn
.reg_res
)
1512 /* If we identified an inc_insn that uses two
1513 different pseudos, it's of the form
1515 (set reg_res (plus reg0 reg1))
1517 where reg1 is a constant (*).
1519 The next use of reg_res was not identified by
1520 find_address as a mem_insn that we could turn
1521 into auto-inc, so see if we find a suitable
1522 MEM in the next use of reg0, as long as it's
1523 before any subsequent use of reg_res:
1525 ... (mem (... reg0 ...)) ...
1529 In this case, we can turn the plus into a
1530 copy, and the reg0 in the MEM address into a
1531 post_inc of reg_res:
1535 ... (mem (... (post_add reg_res reg1) ...)) ...
1537 reg_res will then have the correct value at
1538 subsequent uses, and reg0 will remain
1541 (*) We could support non-const reg1, but then
1542 we'd have to check that reg1 remains
1543 unchanged all the way to the modified MEM,
1544 and we'd have to extend find_address to
1545 represent a non-const negated reg1. */
1546 regno
= REGNO (inc_insn
.reg0
);
1547 rtx_insn
*reg0_use
= get_next_ref (regno
, bb
,
1550 /* Give up if the next use of reg0 is after the next
1551 use of reg_res (same insn is ok; we might have
1552 found a MEM with reg_res before, and that failed,
1553 but now we try reg0, which might work), or defs
1554 of reg_res (same insn is not ok, we'd introduce
1555 another def in the same insn) or reg0. */
1558 int luid
= DF_INSN_LUID (reg0_use
);
1560 /* It might seem pointless to introduce an
1561 auto-inc if there's no subsequent use of
1562 reg_res (i.e., mem_insn.insn == NULL), but
1563 the next use might be in the next iteration
1564 of a loop, and it won't hurt if we make the
1565 change even if it's not needed. */
1567 && luid
> DF_INSN_LUID (mem_insn
.insn
))
1570 rtx_insn
*other_insn
1571 = get_next_ref (REGNO (inc_insn
.reg_res
), bb
,
1574 if (other_insn
&& luid
>= DF_INSN_LUID (other_insn
))
1578 = get_next_ref (REGNO (inc_insn
.reg0
), bb
,
1581 if (other_insn
&& luid
> DF_INSN_LUID (other_insn
))
1585 mem_insn
.insn
= reg0_use
;
1588 && find_address (&PATTERN (mem_insn
.insn
),
1589 inc_insn
.reg0
) == -1)
1592 dump_mem_insn (dump_file
);
1596 insn_is_add_or_inc
= false;
1604 insn_is_add_or_inc
= false;
1605 mem_insn
.insn
= insn
;
1606 if (find_mem (&PATTERN (insn
)))
1610 /* If the inc insn was merged with a mem, the inc insn is gone
1611 and there is noting to update. */
1612 if (df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
))
1616 /* Need to update next use. */
1617 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
1619 if (reg_next_debug_use
)
1620 reg_next_debug_use
[DF_REF_REGNO (def
)] = NULL
;
1621 reg_next_use
[DF_REF_REGNO (def
)] = NULL
;
1622 reg_next_inc_use
[DF_REF_REGNO (def
)] = NULL
;
1623 reg_next_def
[DF_REF_REGNO (def
)] = insn
;
1626 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
1628 if (reg_next_debug_use
)
1629 /* This may seem surprising, but we know we may only
1630 modify the value of a REG between an insn and the
1631 next nondebug use thereof. Any debug uses after
1632 the next nondebug use can be left alone, the REG
1633 will hold the expected value there. */
1634 reg_next_debug_use
[DF_REF_REGNO (use
)] = NULL
;
1635 reg_next_use
[DF_REF_REGNO (use
)] = insn
;
1636 if (insn_is_add_or_inc
)
1637 reg_next_inc_use
[DF_REF_REGNO (use
)] = insn
;
1639 reg_next_inc_use
[DF_REF_REGNO (use
)] = NULL
;
1643 fprintf (dump_file
, "skipping update of deleted insn %d\n",
1647 /* If we were successful, try again. There may have been several
1648 opportunities that were interleaved. This is rare but
1649 gcc.c-torture/compile/pr17273.c actually exhibits this. */
1650 if (success_in_block
)
1652 /* In this case, we must clear these vectors since the trick of
1653 testing if the stale insn in the block will not work. */
1654 if (reg_next_debug_use
)
1655 memset (reg_next_debug_use
, 0, max_reg
* sizeof (rtx
));
1656 memset (reg_next_use
, 0, max_reg
* sizeof (rtx
));
1657 memset (reg_next_inc_use
, 0, max_reg
* sizeof (rtx
));
1658 memset (reg_next_def
, 0, max_reg
* sizeof (rtx
));
1659 df_recompute_luids (bb
);
1660 merge_in_block (max_reg
, bb
);
1664 /* Discover auto-inc auto-dec instructions. */
1668 const pass_data pass_data_inc_dec
=
1670 RTL_PASS
, /* type */
1671 "auto_inc_dec", /* name */
1672 OPTGROUP_NONE
, /* optinfo_flags */
1673 TV_AUTO_INC_DEC
, /* tv_id */
1674 0, /* properties_required */
1675 0, /* properties_provided */
1676 0, /* properties_destroyed */
1677 0, /* todo_flags_start */
1678 TODO_df_finish
, /* todo_flags_finish */
1681 class pass_inc_dec
: public rtl_opt_pass
1684 pass_inc_dec (gcc::context
*ctxt
)
1685 : rtl_opt_pass (pass_data_inc_dec
, ctxt
)
1688 /* opt_pass methods: */
1689 virtual bool gate (function
*)
1694 return (optimize
> 0 && flag_auto_inc_dec
);
1698 unsigned int execute (function
*);
1700 }; // class pass_inc_dec
1703 pass_inc_dec::execute (function
*fun ATTRIBUTE_UNUSED
)
1709 int max_reg
= max_reg_num ();
1712 init_decision_table ();
1714 mem_tmp
= gen_rtx_MEM (Pmode
, NULL_RTX
);
1716 df_note_add_problem ();
1719 if (MAY_HAVE_DEBUG_BIND_INSNS
)
1720 reg_next_debug_use
= XCNEWVEC (rtx_insn
*, max_reg
);
1722 /* An earlier function may have had debug binds. */
1723 reg_next_debug_use
= NULL
;
1724 reg_next_use
= XCNEWVEC (rtx_insn
*, max_reg
);
1725 reg_next_inc_use
= XCNEWVEC (rtx_insn
*, max_reg
);
1726 reg_next_def
= XCNEWVEC (rtx_insn
*, max_reg
);
1727 FOR_EACH_BB_FN (bb
, fun
)
1728 merge_in_block (max_reg
, bb
);
1730 free (reg_next_debug_use
);
1731 free (reg_next_use
);
1732 free (reg_next_inc_use
);
1733 free (reg_next_def
);
1743 make_pass_inc_dec (gcc::context
*ctxt
)
1745 return new pass_inc_dec (ctxt
);