[42/46] Add vec_info::replace_stmt
[official-gcc.git] / gcc / emit-rtl.c
blobe4b070486e87e60e069178046f98a19304167128
1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987-2018 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 /* Middle-to-low level generation of rtx code and insns.
23 This file contains support functions for creating rtl expressions
24 and manipulating them in the doubly-linked chain of insns.
26 The patterns of the insns are created by machine-dependent
27 routines in insn-emit.c, which is generated automatically from
28 the machine description. These routines make the individual rtx's
29 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
30 which are automatically generated from rtl.def; what is machine
31 dependent is the kind of rtx's they make and what arguments they
32 use. */
34 #include "config.h"
35 #include "system.h"
36 #include "coretypes.h"
37 #include "memmodel.h"
38 #include "backend.h"
39 #include "target.h"
40 #include "rtl.h"
41 #include "tree.h"
42 #include "df.h"
43 #include "tm_p.h"
44 #include "stringpool.h"
45 #include "insn-config.h"
46 #include "regs.h"
47 #include "emit-rtl.h"
48 #include "recog.h"
49 #include "diagnostic-core.h"
50 #include "alias.h"
51 #include "fold-const.h"
52 #include "varasm.h"
53 #include "cfgrtl.h"
54 #include "tree-eh.h"
55 #include "explow.h"
56 #include "expr.h"
57 #include "params.h"
58 #include "builtins.h"
59 #include "rtl-iter.h"
60 #include "stor-layout.h"
61 #include "opts.h"
62 #include "predict.h"
63 #include "rtx-vector-builder.h"
65 struct target_rtl default_target_rtl;
66 #if SWITCHABLE_TARGET
67 struct target_rtl *this_target_rtl = &default_target_rtl;
68 #endif
70 #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx)
72 /* Commonly used modes. */
74 scalar_int_mode byte_mode; /* Mode whose width is BITS_PER_UNIT. */
75 scalar_int_mode word_mode; /* Mode whose width is BITS_PER_WORD. */
76 scalar_int_mode ptr_mode; /* Mode whose width is POINTER_SIZE. */
78 /* Datastructures maintained for currently processed function in RTL form. */
80 struct rtl_data x_rtl;
82 /* Indexed by pseudo register number, gives the rtx for that pseudo.
83 Allocated in parallel with regno_pointer_align.
84 FIXME: We could put it into emit_status struct, but gengtype is not able to deal
85 with length attribute nested in top level structures. */
87 rtx * regno_reg_rtx;
89 /* This is *not* reset after each function. It gives each CODE_LABEL
90 in the entire compilation a unique label number. */
92 static GTY(()) int label_num = 1;
94 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
95 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
96 record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX
97 is set only for MODE_INT and MODE_VECTOR_INT modes. */
99 rtx const_tiny_rtx[4][(int) MAX_MACHINE_MODE];
101 rtx const_true_rtx;
103 REAL_VALUE_TYPE dconst0;
104 REAL_VALUE_TYPE dconst1;
105 REAL_VALUE_TYPE dconst2;
106 REAL_VALUE_TYPE dconstm1;
107 REAL_VALUE_TYPE dconsthalf;
109 /* Record fixed-point constant 0 and 1. */
110 FIXED_VALUE_TYPE fconst0[MAX_FCONST0];
111 FIXED_VALUE_TYPE fconst1[MAX_FCONST1];
113 /* We make one copy of (const_int C) where C is in
114 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
115 to save space during the compilation and simplify comparisons of
116 integers. */
118 rtx const_int_rtx[MAX_SAVED_CONST_INT * 2 + 1];
120 /* Standard pieces of rtx, to be substituted directly into things. */
121 rtx pc_rtx;
122 rtx ret_rtx;
123 rtx simple_return_rtx;
124 rtx cc0_rtx;
126 /* Marker used for denoting an INSN, which should never be accessed (i.e.,
127 this pointer should normally never be dereferenced), but is required to be
128 distinct from NULL_RTX. Currently used by peephole2 pass. */
129 rtx_insn *invalid_insn_rtx;
131 /* A hash table storing CONST_INTs whose absolute value is greater
132 than MAX_SAVED_CONST_INT. */
134 struct const_int_hasher : ggc_cache_ptr_hash<rtx_def>
136 typedef HOST_WIDE_INT compare_type;
138 static hashval_t hash (rtx i);
139 static bool equal (rtx i, HOST_WIDE_INT h);
142 static GTY ((cache)) hash_table<const_int_hasher> *const_int_htab;
144 struct const_wide_int_hasher : ggc_cache_ptr_hash<rtx_def>
146 static hashval_t hash (rtx x);
147 static bool equal (rtx x, rtx y);
150 static GTY ((cache)) hash_table<const_wide_int_hasher> *const_wide_int_htab;
152 struct const_poly_int_hasher : ggc_cache_ptr_hash<rtx_def>
154 typedef std::pair<machine_mode, poly_wide_int_ref> compare_type;
156 static hashval_t hash (rtx x);
157 static bool equal (rtx x, const compare_type &y);
160 static GTY ((cache)) hash_table<const_poly_int_hasher> *const_poly_int_htab;
162 /* A hash table storing register attribute structures. */
163 struct reg_attr_hasher : ggc_cache_ptr_hash<reg_attrs>
165 static hashval_t hash (reg_attrs *x);
166 static bool equal (reg_attrs *a, reg_attrs *b);
169 static GTY ((cache)) hash_table<reg_attr_hasher> *reg_attrs_htab;
171 /* A hash table storing all CONST_DOUBLEs. */
172 struct const_double_hasher : ggc_cache_ptr_hash<rtx_def>
174 static hashval_t hash (rtx x);
175 static bool equal (rtx x, rtx y);
178 static GTY ((cache)) hash_table<const_double_hasher> *const_double_htab;
180 /* A hash table storing all CONST_FIXEDs. */
181 struct const_fixed_hasher : ggc_cache_ptr_hash<rtx_def>
183 static hashval_t hash (rtx x);
184 static bool equal (rtx x, rtx y);
187 static GTY ((cache)) hash_table<const_fixed_hasher> *const_fixed_htab;
189 #define cur_insn_uid (crtl->emit.x_cur_insn_uid)
190 #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid)
191 #define first_label_num (crtl->emit.x_first_label_num)
193 static void set_used_decls (tree);
194 static void mark_label_nuses (rtx);
195 #if TARGET_SUPPORTS_WIDE_INT
196 static rtx lookup_const_wide_int (rtx);
197 #endif
198 static rtx lookup_const_double (rtx);
199 static rtx lookup_const_fixed (rtx);
200 static rtx gen_const_vector (machine_mode, int);
201 static void copy_rtx_if_shared_1 (rtx *orig);
203 /* Probability of the conditional branch currently proceeded by try_split. */
204 profile_probability split_branch_probability;
206 /* Returns a hash code for X (which is a really a CONST_INT). */
208 hashval_t
209 const_int_hasher::hash (rtx x)
211 return (hashval_t) INTVAL (x);
214 /* Returns nonzero if the value represented by X (which is really a
215 CONST_INT) is the same as that given by Y (which is really a
216 HOST_WIDE_INT *). */
218 bool
219 const_int_hasher::equal (rtx x, HOST_WIDE_INT y)
221 return (INTVAL (x) == y);
224 #if TARGET_SUPPORTS_WIDE_INT
225 /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */
227 hashval_t
228 const_wide_int_hasher::hash (rtx x)
230 int i;
231 unsigned HOST_WIDE_INT hash = 0;
232 const_rtx xr = x;
234 for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++)
235 hash += CONST_WIDE_INT_ELT (xr, i);
237 return (hashval_t) hash;
240 /* Returns nonzero if the value represented by X (which is really a
241 CONST_WIDE_INT) is the same as that given by Y (which is really a
242 CONST_WIDE_INT). */
244 bool
245 const_wide_int_hasher::equal (rtx x, rtx y)
247 int i;
248 const_rtx xr = x;
249 const_rtx yr = y;
250 if (CONST_WIDE_INT_NUNITS (xr) != CONST_WIDE_INT_NUNITS (yr))
251 return false;
253 for (i = 0; i < CONST_WIDE_INT_NUNITS (xr); i++)
254 if (CONST_WIDE_INT_ELT (xr, i) != CONST_WIDE_INT_ELT (yr, i))
255 return false;
257 return true;
259 #endif
261 /* Returns a hash code for CONST_POLY_INT X. */
263 hashval_t
264 const_poly_int_hasher::hash (rtx x)
266 inchash::hash h;
267 h.add_int (GET_MODE (x));
268 for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i)
269 h.add_wide_int (CONST_POLY_INT_COEFFS (x)[i]);
270 return h.end ();
273 /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */
275 bool
276 const_poly_int_hasher::equal (rtx x, const compare_type &y)
278 if (GET_MODE (x) != y.first)
279 return false;
280 for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i)
281 if (CONST_POLY_INT_COEFFS (x)[i] != y.second.coeffs[i])
282 return false;
283 return true;
286 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
287 hashval_t
288 const_double_hasher::hash (rtx x)
290 const_rtx const value = x;
291 hashval_t h;
293 if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (value) == VOIDmode)
294 h = CONST_DOUBLE_LOW (value) ^ CONST_DOUBLE_HIGH (value);
295 else
297 h = real_hash (CONST_DOUBLE_REAL_VALUE (value));
298 /* MODE is used in the comparison, so it should be in the hash. */
299 h ^= GET_MODE (value);
301 return h;
304 /* Returns nonzero if the value represented by X (really a ...)
305 is the same as that represented by Y (really a ...) */
306 bool
307 const_double_hasher::equal (rtx x, rtx y)
309 const_rtx const a = x, b = y;
311 if (GET_MODE (a) != GET_MODE (b))
312 return 0;
313 if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (a) == VOIDmode)
314 return (CONST_DOUBLE_LOW (a) == CONST_DOUBLE_LOW (b)
315 && CONST_DOUBLE_HIGH (a) == CONST_DOUBLE_HIGH (b));
316 else
317 return real_identical (CONST_DOUBLE_REAL_VALUE (a),
318 CONST_DOUBLE_REAL_VALUE (b));
321 /* Returns a hash code for X (which is really a CONST_FIXED). */
323 hashval_t
324 const_fixed_hasher::hash (rtx x)
326 const_rtx const value = x;
327 hashval_t h;
329 h = fixed_hash (CONST_FIXED_VALUE (value));
330 /* MODE is used in the comparison, so it should be in the hash. */
331 h ^= GET_MODE (value);
332 return h;
335 /* Returns nonzero if the value represented by X is the same as that
336 represented by Y. */
338 bool
339 const_fixed_hasher::equal (rtx x, rtx y)
341 const_rtx const a = x, b = y;
343 if (GET_MODE (a) != GET_MODE (b))
344 return 0;
345 return fixed_identical (CONST_FIXED_VALUE (a), CONST_FIXED_VALUE (b));
348 /* Return true if the given memory attributes are equal. */
350 bool
351 mem_attrs_eq_p (const struct mem_attrs *p, const struct mem_attrs *q)
353 if (p == q)
354 return true;
355 if (!p || !q)
356 return false;
357 return (p->alias == q->alias
358 && p->offset_known_p == q->offset_known_p
359 && (!p->offset_known_p || known_eq (p->offset, q->offset))
360 && p->size_known_p == q->size_known_p
361 && (!p->size_known_p || known_eq (p->size, q->size))
362 && p->align == q->align
363 && p->addrspace == q->addrspace
364 && (p->expr == q->expr
365 || (p->expr != NULL_TREE && q->expr != NULL_TREE
366 && operand_equal_p (p->expr, q->expr, 0))));
369 /* Set MEM's memory attributes so that they are the same as ATTRS. */
371 static void
372 set_mem_attrs (rtx mem, mem_attrs *attrs)
374 /* If everything is the default, we can just clear the attributes. */
375 if (mem_attrs_eq_p (attrs, mode_mem_attrs[(int) GET_MODE (mem)]))
377 MEM_ATTRS (mem) = 0;
378 return;
381 if (!MEM_ATTRS (mem)
382 || !mem_attrs_eq_p (attrs, MEM_ATTRS (mem)))
384 MEM_ATTRS (mem) = ggc_alloc<mem_attrs> ();
385 memcpy (MEM_ATTRS (mem), attrs, sizeof (mem_attrs));
389 /* Returns a hash code for X (which is a really a reg_attrs *). */
391 hashval_t
392 reg_attr_hasher::hash (reg_attrs *x)
394 const reg_attrs *const p = x;
396 inchash::hash h;
397 h.add_ptr (p->decl);
398 h.add_poly_hwi (p->offset);
399 return h.end ();
402 /* Returns nonzero if the value represented by X is the same as that given by
403 Y. */
405 bool
406 reg_attr_hasher::equal (reg_attrs *x, reg_attrs *y)
408 const reg_attrs *const p = x;
409 const reg_attrs *const q = y;
411 return (p->decl == q->decl && known_eq (p->offset, q->offset));
413 /* Allocate a new reg_attrs structure and insert it into the hash table if
414 one identical to it is not already in the table. We are doing this for
415 MEM of mode MODE. */
417 static reg_attrs *
418 get_reg_attrs (tree decl, poly_int64 offset)
420 reg_attrs attrs;
422 /* If everything is the default, we can just return zero. */
423 if (decl == 0 && known_eq (offset, 0))
424 return 0;
426 attrs.decl = decl;
427 attrs.offset = offset;
429 reg_attrs **slot = reg_attrs_htab->find_slot (&attrs, INSERT);
430 if (*slot == 0)
432 *slot = ggc_alloc<reg_attrs> ();
433 memcpy (*slot, &attrs, sizeof (reg_attrs));
436 return *slot;
440 #if !HAVE_blockage
441 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
442 and to block register equivalences to be seen across this insn. */
445 gen_blockage (void)
447 rtx x = gen_rtx_ASM_INPUT (VOIDmode, "");
448 MEM_VOLATILE_P (x) = true;
449 return x;
451 #endif
454 /* Set the mode and register number of X to MODE and REGNO. */
456 void
457 set_mode_and_regno (rtx x, machine_mode mode, unsigned int regno)
459 unsigned int nregs = (HARD_REGISTER_NUM_P (regno)
460 ? hard_regno_nregs (regno, mode)
461 : 1);
462 PUT_MODE_RAW (x, mode);
463 set_regno_raw (x, regno, nregs);
466 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
467 don't attempt to share with the various global pieces of rtl (such as
468 frame_pointer_rtx). */
471 gen_raw_REG (machine_mode mode, unsigned int regno)
473 rtx x = rtx_alloc (REG MEM_STAT_INFO);
474 set_mode_and_regno (x, mode, regno);
475 REG_ATTRS (x) = NULL;
476 ORIGINAL_REGNO (x) = regno;
477 return x;
480 /* There are some RTL codes that require special attention; the generation
481 functions do the raw handling. If you add to this list, modify
482 special_rtx in gengenrtl.c as well. */
484 rtx_expr_list *
485 gen_rtx_EXPR_LIST (machine_mode mode, rtx expr, rtx expr_list)
487 return as_a <rtx_expr_list *> (gen_rtx_fmt_ee (EXPR_LIST, mode, expr,
488 expr_list));
491 rtx_insn_list *
492 gen_rtx_INSN_LIST (machine_mode mode, rtx insn, rtx insn_list)
494 return as_a <rtx_insn_list *> (gen_rtx_fmt_ue (INSN_LIST, mode, insn,
495 insn_list));
498 rtx_insn *
499 gen_rtx_INSN (machine_mode mode, rtx_insn *prev_insn, rtx_insn *next_insn,
500 basic_block bb, rtx pattern, int location, int code,
501 rtx reg_notes)
503 return as_a <rtx_insn *> (gen_rtx_fmt_uuBeiie (INSN, mode,
504 prev_insn, next_insn,
505 bb, pattern, location, code,
506 reg_notes));
510 gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED, HOST_WIDE_INT arg)
512 if (arg >= - MAX_SAVED_CONST_INT && arg <= MAX_SAVED_CONST_INT)
513 return const_int_rtx[arg + MAX_SAVED_CONST_INT];
515 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
516 if (const_true_rtx && arg == STORE_FLAG_VALUE)
517 return const_true_rtx;
518 #endif
520 /* Look up the CONST_INT in the hash table. */
521 rtx *slot = const_int_htab->find_slot_with_hash (arg, (hashval_t) arg,
522 INSERT);
523 if (*slot == 0)
524 *slot = gen_rtx_raw_CONST_INT (VOIDmode, arg);
526 return *slot;
530 gen_int_mode (poly_int64 c, machine_mode mode)
532 c = trunc_int_for_mode (c, mode);
533 if (c.is_constant ())
534 return GEN_INT (c.coeffs[0]);
535 unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode));
536 return immed_wide_int_const (poly_wide_int::from (c, prec, SIGNED), mode);
539 /* CONST_DOUBLEs might be created from pairs of integers, or from
540 REAL_VALUE_TYPEs. Also, their length is known only at run time,
541 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
543 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
544 hash table. If so, return its counterpart; otherwise add it
545 to the hash table and return it. */
546 static rtx
547 lookup_const_double (rtx real)
549 rtx *slot = const_double_htab->find_slot (real, INSERT);
550 if (*slot == 0)
551 *slot = real;
553 return *slot;
556 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
557 VALUE in mode MODE. */
559 const_double_from_real_value (REAL_VALUE_TYPE value, machine_mode mode)
561 rtx real = rtx_alloc (CONST_DOUBLE);
562 PUT_MODE (real, mode);
564 real->u.rv = value;
566 return lookup_const_double (real);
569 /* Determine whether FIXED, a CONST_FIXED, already exists in the
570 hash table. If so, return its counterpart; otherwise add it
571 to the hash table and return it. */
573 static rtx
574 lookup_const_fixed (rtx fixed)
576 rtx *slot = const_fixed_htab->find_slot (fixed, INSERT);
577 if (*slot == 0)
578 *slot = fixed;
580 return *slot;
583 /* Return a CONST_FIXED rtx for a fixed-point value specified by
584 VALUE in mode MODE. */
587 const_fixed_from_fixed_value (FIXED_VALUE_TYPE value, machine_mode mode)
589 rtx fixed = rtx_alloc (CONST_FIXED);
590 PUT_MODE (fixed, mode);
592 fixed->u.fv = value;
594 return lookup_const_fixed (fixed);
597 #if TARGET_SUPPORTS_WIDE_INT == 0
598 /* Constructs double_int from rtx CST. */
600 double_int
601 rtx_to_double_int (const_rtx cst)
603 double_int r;
605 if (CONST_INT_P (cst))
606 r = double_int::from_shwi (INTVAL (cst));
607 else if (CONST_DOUBLE_AS_INT_P (cst))
609 r.low = CONST_DOUBLE_LOW (cst);
610 r.high = CONST_DOUBLE_HIGH (cst);
612 else
613 gcc_unreachable ();
615 return r;
617 #endif
619 #if TARGET_SUPPORTS_WIDE_INT
620 /* Determine whether CONST_WIDE_INT WINT already exists in the hash table.
621 If so, return its counterpart; otherwise add it to the hash table and
622 return it. */
624 static rtx
625 lookup_const_wide_int (rtx wint)
627 rtx *slot = const_wide_int_htab->find_slot (wint, INSERT);
628 if (*slot == 0)
629 *slot = wint;
631 return *slot;
633 #endif
635 /* Return an rtx constant for V, given that the constant has mode MODE.
636 The returned rtx will be a CONST_INT if V fits, otherwise it will be
637 a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT
638 (if TARGET_SUPPORTS_WIDE_INT). */
640 static rtx
641 immed_wide_int_const_1 (const wide_int_ref &v, machine_mode mode)
643 unsigned int len = v.get_len ();
644 /* Not scalar_int_mode because we also allow pointer bound modes. */
645 unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode));
647 /* Allow truncation but not extension since we do not know if the
648 number is signed or unsigned. */
649 gcc_assert (prec <= v.get_precision ());
651 if (len < 2 || prec <= HOST_BITS_PER_WIDE_INT)
652 return gen_int_mode (v.elt (0), mode);
654 #if TARGET_SUPPORTS_WIDE_INT
656 unsigned int i;
657 rtx value;
658 unsigned int blocks_needed
659 = (prec + HOST_BITS_PER_WIDE_INT - 1) / HOST_BITS_PER_WIDE_INT;
661 if (len > blocks_needed)
662 len = blocks_needed;
664 value = const_wide_int_alloc (len);
666 /* It is so tempting to just put the mode in here. Must control
667 myself ... */
668 PUT_MODE (value, VOIDmode);
669 CWI_PUT_NUM_ELEM (value, len);
671 for (i = 0; i < len; i++)
672 CONST_WIDE_INT_ELT (value, i) = v.elt (i);
674 return lookup_const_wide_int (value);
676 #else
677 return immed_double_const (v.elt (0), v.elt (1), mode);
678 #endif
681 #if TARGET_SUPPORTS_WIDE_INT == 0
682 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
683 of ints: I0 is the low-order word and I1 is the high-order word.
684 For values that are larger than HOST_BITS_PER_DOUBLE_INT, the
685 implied upper bits are copies of the high bit of i1. The value
686 itself is neither signed nor unsigned. Do not use this routine for
687 non-integer modes; convert to REAL_VALUE_TYPE and use
688 const_double_from_real_value. */
691 immed_double_const (HOST_WIDE_INT i0, HOST_WIDE_INT i1, machine_mode mode)
693 rtx value;
694 unsigned int i;
696 /* There are the following cases (note that there are no modes with
697 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT):
699 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
700 gen_int_mode.
701 2) If the value of the integer fits into HOST_WIDE_INT anyway
702 (i.e., i1 consists only from copies of the sign bit, and sign
703 of i0 and i1 are the same), then we return a CONST_INT for i0.
704 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
705 scalar_mode smode;
706 if (is_a <scalar_mode> (mode, &smode)
707 && GET_MODE_BITSIZE (smode) <= HOST_BITS_PER_WIDE_INT)
708 return gen_int_mode (i0, mode);
710 /* If this integer fits in one word, return a CONST_INT. */
711 if ((i1 == 0 && i0 >= 0) || (i1 == ~0 && i0 < 0))
712 return GEN_INT (i0);
714 /* We use VOIDmode for integers. */
715 value = rtx_alloc (CONST_DOUBLE);
716 PUT_MODE (value, VOIDmode);
718 CONST_DOUBLE_LOW (value) = i0;
719 CONST_DOUBLE_HIGH (value) = i1;
721 for (i = 2; i < (sizeof CONST_DOUBLE_FORMAT - 1); i++)
722 XWINT (value, i) = 0;
724 return lookup_const_double (value);
726 #endif
728 /* Return an rtx representation of C in mode MODE. */
731 immed_wide_int_const (const poly_wide_int_ref &c, machine_mode mode)
733 if (c.is_constant ())
734 return immed_wide_int_const_1 (c.coeffs[0], mode);
736 /* Not scalar_int_mode because we also allow pointer bound modes. */
737 unsigned int prec = GET_MODE_PRECISION (as_a <scalar_mode> (mode));
739 /* Allow truncation but not extension since we do not know if the
740 number is signed or unsigned. */
741 gcc_assert (prec <= c.coeffs[0].get_precision ());
742 poly_wide_int newc = poly_wide_int::from (c, prec, SIGNED);
744 /* See whether we already have an rtx for this constant. */
745 inchash::hash h;
746 h.add_int (mode);
747 for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i)
748 h.add_wide_int (newc.coeffs[i]);
749 const_poly_int_hasher::compare_type typed_value (mode, newc);
750 rtx *slot = const_poly_int_htab->find_slot_with_hash (typed_value,
751 h.end (), INSERT);
752 rtx x = *slot;
753 if (x)
754 return x;
756 /* Create a new rtx. There's a choice to be made here between installing
757 the actual mode of the rtx or leaving it as VOIDmode (for consistency
758 with CONST_INT). In practice the handling of the codes is different
759 enough that we get no benefit from using VOIDmode, and various places
760 assume that VOIDmode implies CONST_INT. Using the real mode seems like
761 the right long-term direction anyway. */
762 typedef trailing_wide_ints<NUM_POLY_INT_COEFFS> twi;
763 size_t extra_size = twi::extra_size (prec);
764 x = rtx_alloc_v (CONST_POLY_INT,
765 sizeof (struct const_poly_int_def) + extra_size);
766 PUT_MODE (x, mode);
767 CONST_POLY_INT_COEFFS (x).set_precision (prec);
768 for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i)
769 CONST_POLY_INT_COEFFS (x)[i] = newc.coeffs[i];
771 *slot = x;
772 return x;
776 gen_rtx_REG (machine_mode mode, unsigned int regno)
778 /* In case the MD file explicitly references the frame pointer, have
779 all such references point to the same frame pointer. This is
780 used during frame pointer elimination to distinguish the explicit
781 references to these registers from pseudos that happened to be
782 assigned to them.
784 If we have eliminated the frame pointer or arg pointer, we will
785 be using it as a normal register, for example as a spill
786 register. In such cases, we might be accessing it in a mode that
787 is not Pmode and therefore cannot use the pre-allocated rtx.
789 Also don't do this when we are making new REGs in reload, since
790 we don't want to get confused with the real pointers. */
792 if (mode == Pmode && !reload_in_progress && !lra_in_progress)
794 if (regno == FRAME_POINTER_REGNUM
795 && (!reload_completed || frame_pointer_needed))
796 return frame_pointer_rtx;
798 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
799 && regno == HARD_FRAME_POINTER_REGNUM
800 && (!reload_completed || frame_pointer_needed))
801 return hard_frame_pointer_rtx;
802 #if !HARD_FRAME_POINTER_IS_ARG_POINTER
803 if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
804 && regno == ARG_POINTER_REGNUM)
805 return arg_pointer_rtx;
806 #endif
807 #ifdef RETURN_ADDRESS_POINTER_REGNUM
808 if (regno == RETURN_ADDRESS_POINTER_REGNUM)
809 return return_address_pointer_rtx;
810 #endif
811 if (regno == (unsigned) PIC_OFFSET_TABLE_REGNUM
812 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
813 && fixed_regs[PIC_OFFSET_TABLE_REGNUM])
814 return pic_offset_table_rtx;
815 if (regno == STACK_POINTER_REGNUM)
816 return stack_pointer_rtx;
819 #if 0
820 /* If the per-function register table has been set up, try to re-use
821 an existing entry in that table to avoid useless generation of RTL.
823 This code is disabled for now until we can fix the various backends
824 which depend on having non-shared hard registers in some cases. Long
825 term we want to re-enable this code as it can significantly cut down
826 on the amount of useless RTL that gets generated.
828 We'll also need to fix some code that runs after reload that wants to
829 set ORIGINAL_REGNO. */
831 if (cfun
832 && cfun->emit
833 && regno_reg_rtx
834 && regno < FIRST_PSEUDO_REGISTER
835 && reg_raw_mode[regno] == mode)
836 return regno_reg_rtx[regno];
837 #endif
839 return gen_raw_REG (mode, regno);
843 gen_rtx_MEM (machine_mode mode, rtx addr)
845 rtx rt = gen_rtx_raw_MEM (mode, addr);
847 /* This field is not cleared by the mere allocation of the rtx, so
848 we clear it here. */
849 MEM_ATTRS (rt) = 0;
851 return rt;
854 /* Generate a memory referring to non-trapping constant memory. */
857 gen_const_mem (machine_mode mode, rtx addr)
859 rtx mem = gen_rtx_MEM (mode, addr);
860 MEM_READONLY_P (mem) = 1;
861 MEM_NOTRAP_P (mem) = 1;
862 return mem;
865 /* Generate a MEM referring to fixed portions of the frame, e.g., register
866 save areas. */
869 gen_frame_mem (machine_mode mode, rtx addr)
871 rtx mem = gen_rtx_MEM (mode, addr);
872 MEM_NOTRAP_P (mem) = 1;
873 set_mem_alias_set (mem, get_frame_alias_set ());
874 return mem;
877 /* Generate a MEM referring to a temporary use of the stack, not part
878 of the fixed stack frame. For example, something which is pushed
879 by a target splitter. */
881 gen_tmp_stack_mem (machine_mode mode, rtx addr)
883 rtx mem = gen_rtx_MEM (mode, addr);
884 MEM_NOTRAP_P (mem) = 1;
885 if (!cfun->calls_alloca)
886 set_mem_alias_set (mem, get_frame_alias_set ());
887 return mem;
890 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
891 this construct would be valid, and false otherwise. */
893 bool
894 validate_subreg (machine_mode omode, machine_mode imode,
895 const_rtx reg, poly_uint64 offset)
897 poly_uint64 isize = GET_MODE_SIZE (imode);
898 poly_uint64 osize = GET_MODE_SIZE (omode);
900 /* The sizes must be ordered, so that we know whether the subreg
901 is partial, paradoxical or complete. */
902 if (!ordered_p (isize, osize))
903 return false;
905 /* All subregs must be aligned. */
906 if (!multiple_p (offset, osize))
907 return false;
909 /* The subreg offset cannot be outside the inner object. */
910 if (maybe_ge (offset, isize))
911 return false;
913 poly_uint64 regsize = REGMODE_NATURAL_SIZE (imode);
915 /* ??? This should not be here. Temporarily continue to allow word_mode
916 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
917 Generally, backends are doing something sketchy but it'll take time to
918 fix them all. */
919 if (omode == word_mode)
921 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
922 is the culprit here, and not the backends. */
923 else if (known_ge (osize, regsize) && known_ge (isize, osize))
925 /* Allow component subregs of complex and vector. Though given the below
926 extraction rules, it's not always clear what that means. */
927 else if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
928 && GET_MODE_INNER (imode) == omode)
930 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
931 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
932 represent this. It's questionable if this ought to be represented at
933 all -- why can't this all be hidden in post-reload splitters that make
934 arbitrarily mode changes to the registers themselves. */
935 else if (VECTOR_MODE_P (omode) && GET_MODE_INNER (omode) == imode)
937 /* Subregs involving floating point modes are not allowed to
938 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
939 (subreg:SI (reg:DF) 0) isn't. */
940 else if (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode))
942 if (! (known_eq (isize, osize)
943 /* LRA can use subreg to store a floating point value in
944 an integer mode. Although the floating point and the
945 integer modes need the same number of hard registers,
946 the size of floating point mode can be less than the
947 integer mode. LRA also uses subregs for a register
948 should be used in different mode in on insn. */
949 || lra_in_progress))
950 return false;
953 /* Paradoxical subregs must have offset zero. */
954 if (maybe_gt (osize, isize))
955 return known_eq (offset, 0U);
957 /* This is a normal subreg. Verify that the offset is representable. */
959 /* For hard registers, we already have most of these rules collected in
960 subreg_offset_representable_p. */
961 if (reg && REG_P (reg) && HARD_REGISTER_P (reg))
963 unsigned int regno = REGNO (reg);
965 if ((COMPLEX_MODE_P (imode) || VECTOR_MODE_P (imode))
966 && GET_MODE_INNER (imode) == omode)
968 else if (!REG_CAN_CHANGE_MODE_P (regno, imode, omode))
969 return false;
971 return subreg_offset_representable_p (regno, imode, offset, omode);
974 /* The outer size must be ordered wrt the register size, otherwise
975 we wouldn't know at compile time how many registers the outer
976 mode occupies. */
977 if (!ordered_p (osize, regsize))
978 return false;
980 /* For pseudo registers, we want most of the same checks. Namely:
982 Assume that the pseudo register will be allocated to hard registers
983 that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE,
984 the remainder must correspond to the lowpart of the containing hard
985 register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset,
986 otherwise it is at the lowest offset.
988 Given that we've already checked the mode and offset alignment,
989 we only have to check subblock subregs here. */
990 if (maybe_lt (osize, regsize)
991 && ! (lra_in_progress && (FLOAT_MODE_P (imode) || FLOAT_MODE_P (omode))))
993 /* It is invalid for the target to pick a register size for a mode
994 that isn't ordered wrt to the size of that mode. */
995 poly_uint64 block_size = ordered_min (isize, regsize);
996 unsigned int start_reg;
997 poly_uint64 offset_within_reg;
998 if (!can_div_trunc_p (offset, block_size, &start_reg, &offset_within_reg)
999 || (BYTES_BIG_ENDIAN
1000 ? maybe_ne (offset_within_reg, block_size - osize)
1001 : maybe_ne (offset_within_reg, 0U)))
1002 return false;
1004 return true;
1008 gen_rtx_SUBREG (machine_mode mode, rtx reg, poly_uint64 offset)
1010 gcc_assert (validate_subreg (mode, GET_MODE (reg), reg, offset));
1011 return gen_rtx_raw_SUBREG (mode, reg, offset);
1014 /* Generate a SUBREG representing the least-significant part of REG if MODE
1015 is smaller than mode of REG, otherwise paradoxical SUBREG. */
1018 gen_lowpart_SUBREG (machine_mode mode, rtx reg)
1020 machine_mode inmode;
1022 inmode = GET_MODE (reg);
1023 if (inmode == VOIDmode)
1024 inmode = mode;
1025 return gen_rtx_SUBREG (mode, reg,
1026 subreg_lowpart_offset (mode, inmode));
1030 gen_rtx_VAR_LOCATION (machine_mode mode, tree decl, rtx loc,
1031 enum var_init_status status)
1033 rtx x = gen_rtx_fmt_te (VAR_LOCATION, mode, decl, loc);
1034 PAT_VAR_LOCATION_STATUS (x) = status;
1035 return x;
1039 /* Create an rtvec and stores within it the RTXen passed in the arguments. */
1041 rtvec
1042 gen_rtvec (int n, ...)
1044 int i;
1045 rtvec rt_val;
1046 va_list p;
1048 va_start (p, n);
1050 /* Don't allocate an empty rtvec... */
1051 if (n == 0)
1053 va_end (p);
1054 return NULL_RTVEC;
1057 rt_val = rtvec_alloc (n);
1059 for (i = 0; i < n; i++)
1060 rt_val->elem[i] = va_arg (p, rtx);
1062 va_end (p);
1063 return rt_val;
1066 rtvec
1067 gen_rtvec_v (int n, rtx *argp)
1069 int i;
1070 rtvec rt_val;
1072 /* Don't allocate an empty rtvec... */
1073 if (n == 0)
1074 return NULL_RTVEC;
1076 rt_val = rtvec_alloc (n);
1078 for (i = 0; i < n; i++)
1079 rt_val->elem[i] = *argp++;
1081 return rt_val;
1084 rtvec
1085 gen_rtvec_v (int n, rtx_insn **argp)
1087 int i;
1088 rtvec rt_val;
1090 /* Don't allocate an empty rtvec... */
1091 if (n == 0)
1092 return NULL_RTVEC;
1094 rt_val = rtvec_alloc (n);
1096 for (i = 0; i < n; i++)
1097 rt_val->elem[i] = *argp++;
1099 return rt_val;
1103 /* Return the number of bytes between the start of an OUTER_MODE
1104 in-memory value and the start of an INNER_MODE in-memory value,
1105 given that the former is a lowpart of the latter. It may be a
1106 paradoxical lowpart, in which case the offset will be negative
1107 on big-endian targets. */
1109 poly_int64
1110 byte_lowpart_offset (machine_mode outer_mode,
1111 machine_mode inner_mode)
1113 if (paradoxical_subreg_p (outer_mode, inner_mode))
1114 return -subreg_lowpart_offset (inner_mode, outer_mode);
1115 else
1116 return subreg_lowpart_offset (outer_mode, inner_mode);
1119 /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET)
1120 from address X. For paradoxical big-endian subregs this is a
1121 negative value, otherwise it's the same as OFFSET. */
1123 poly_int64
1124 subreg_memory_offset (machine_mode outer_mode, machine_mode inner_mode,
1125 poly_uint64 offset)
1127 if (paradoxical_subreg_p (outer_mode, inner_mode))
1129 gcc_assert (known_eq (offset, 0U));
1130 return -subreg_lowpart_offset (inner_mode, outer_mode);
1132 return offset;
1135 /* As above, but return the offset that existing subreg X would have
1136 if SUBREG_REG (X) were stored in memory. The only significant thing
1137 about the current SUBREG_REG is its mode. */
1139 poly_int64
1140 subreg_memory_offset (const_rtx x)
1142 return subreg_memory_offset (GET_MODE (x), GET_MODE (SUBREG_REG (x)),
1143 SUBREG_BYTE (x));
1146 /* Generate a REG rtx for a new pseudo register of mode MODE.
1147 This pseudo is assigned the next sequential register number. */
1150 gen_reg_rtx (machine_mode mode)
1152 rtx val;
1153 unsigned int align = GET_MODE_ALIGNMENT (mode);
1155 gcc_assert (can_create_pseudo_p ());
1157 /* If a virtual register with bigger mode alignment is generated,
1158 increase stack alignment estimation because it might be spilled
1159 to stack later. */
1160 if (SUPPORTS_STACK_ALIGNMENT
1161 && crtl->stack_alignment_estimated < align
1162 && !crtl->stack_realign_processed)
1164 unsigned int min_align = MINIMUM_ALIGNMENT (NULL, mode, align);
1165 if (crtl->stack_alignment_estimated < min_align)
1166 crtl->stack_alignment_estimated = min_align;
1169 if (generating_concat_p
1170 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
1171 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT))
1173 /* For complex modes, don't make a single pseudo.
1174 Instead, make a CONCAT of two pseudos.
1175 This allows noncontiguous allocation of the real and imaginary parts,
1176 which makes much better code. Besides, allocating DCmode
1177 pseudos overstrains reload on some machines like the 386. */
1178 rtx realpart, imagpart;
1179 machine_mode partmode = GET_MODE_INNER (mode);
1181 realpart = gen_reg_rtx (partmode);
1182 imagpart = gen_reg_rtx (partmode);
1183 return gen_rtx_CONCAT (mode, realpart, imagpart);
1186 /* Do not call gen_reg_rtx with uninitialized crtl. */
1187 gcc_assert (crtl->emit.regno_pointer_align_length);
1189 crtl->emit.ensure_regno_capacity ();
1190 gcc_assert (reg_rtx_no < crtl->emit.regno_pointer_align_length);
1192 val = gen_raw_REG (mode, reg_rtx_no);
1193 regno_reg_rtx[reg_rtx_no++] = val;
1194 return val;
1197 /* Make sure m_regno_pointer_align, and regno_reg_rtx are large
1198 enough to have elements in the range 0 <= idx <= reg_rtx_no. */
1200 void
1201 emit_status::ensure_regno_capacity ()
1203 int old_size = regno_pointer_align_length;
1205 if (reg_rtx_no < old_size)
1206 return;
1208 int new_size = old_size * 2;
1209 while (reg_rtx_no >= new_size)
1210 new_size *= 2;
1212 char *tmp = XRESIZEVEC (char, regno_pointer_align, new_size);
1213 memset (tmp + old_size, 0, new_size - old_size);
1214 regno_pointer_align = (unsigned char *) tmp;
1216 rtx *new1 = GGC_RESIZEVEC (rtx, regno_reg_rtx, new_size);
1217 memset (new1 + old_size, 0, (new_size - old_size) * sizeof (rtx));
1218 regno_reg_rtx = new1;
1220 crtl->emit.regno_pointer_align_length = new_size;
1223 /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */
1225 bool
1226 reg_is_parm_p (rtx reg)
1228 tree decl;
1230 gcc_assert (REG_P (reg));
1231 decl = REG_EXPR (reg);
1232 return (decl && TREE_CODE (decl) == PARM_DECL);
1235 /* Update NEW with the same attributes as REG, but with OFFSET added
1236 to the REG_OFFSET. */
1238 static void
1239 update_reg_offset (rtx new_rtx, rtx reg, poly_int64 offset)
1241 REG_ATTRS (new_rtx) = get_reg_attrs (REG_EXPR (reg),
1242 REG_OFFSET (reg) + offset);
1245 /* Generate a register with same attributes as REG, but with OFFSET
1246 added to the REG_OFFSET. */
1249 gen_rtx_REG_offset (rtx reg, machine_mode mode, unsigned int regno,
1250 poly_int64 offset)
1252 rtx new_rtx = gen_rtx_REG (mode, regno);
1254 update_reg_offset (new_rtx, reg, offset);
1255 return new_rtx;
1258 /* Generate a new pseudo-register with the same attributes as REG, but
1259 with OFFSET added to the REG_OFFSET. */
1262 gen_reg_rtx_offset (rtx reg, machine_mode mode, int offset)
1264 rtx new_rtx = gen_reg_rtx (mode);
1266 update_reg_offset (new_rtx, reg, offset);
1267 return new_rtx;
1270 /* Adjust REG in-place so that it has mode MODE. It is assumed that the
1271 new register is a (possibly paradoxical) lowpart of the old one. */
1273 void
1274 adjust_reg_mode (rtx reg, machine_mode mode)
1276 update_reg_offset (reg, reg, byte_lowpart_offset (mode, GET_MODE (reg)));
1277 PUT_MODE (reg, mode);
1280 /* Copy REG's attributes from X, if X has any attributes. If REG and X
1281 have different modes, REG is a (possibly paradoxical) lowpart of X. */
1283 void
1284 set_reg_attrs_from_value (rtx reg, rtx x)
1286 poly_int64 offset;
1287 bool can_be_reg_pointer = true;
1289 /* Don't call mark_reg_pointer for incompatible pointer sign
1290 extension. */
1291 while (GET_CODE (x) == SIGN_EXTEND
1292 || GET_CODE (x) == ZERO_EXTEND
1293 || GET_CODE (x) == TRUNCATE
1294 || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x)))
1296 #if defined(POINTERS_EXTEND_UNSIGNED)
1297 if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED)
1298 || (GET_CODE (x) == ZERO_EXTEND && ! POINTERS_EXTEND_UNSIGNED)
1299 || (paradoxical_subreg_p (x)
1300 && ! (SUBREG_PROMOTED_VAR_P (x)
1301 && SUBREG_CHECK_PROMOTED_SIGN (x,
1302 POINTERS_EXTEND_UNSIGNED))))
1303 && !targetm.have_ptr_extend ())
1304 can_be_reg_pointer = false;
1305 #endif
1306 x = XEXP (x, 0);
1309 /* Hard registers can be reused for multiple purposes within the same
1310 function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN
1311 on them is wrong. */
1312 if (HARD_REGISTER_P (reg))
1313 return;
1315 offset = byte_lowpart_offset (GET_MODE (reg), GET_MODE (x));
1316 if (MEM_P (x))
1318 if (MEM_OFFSET_KNOWN_P (x))
1319 REG_ATTRS (reg) = get_reg_attrs (MEM_EXPR (x),
1320 MEM_OFFSET (x) + offset);
1321 if (can_be_reg_pointer && MEM_POINTER (x))
1322 mark_reg_pointer (reg, 0);
1324 else if (REG_P (x))
1326 if (REG_ATTRS (x))
1327 update_reg_offset (reg, x, offset);
1328 if (can_be_reg_pointer && REG_POINTER (x))
1329 mark_reg_pointer (reg, REGNO_POINTER_ALIGN (REGNO (x)));
1333 /* Generate a REG rtx for a new pseudo register, copying the mode
1334 and attributes from X. */
1337 gen_reg_rtx_and_attrs (rtx x)
1339 rtx reg = gen_reg_rtx (GET_MODE (x));
1340 set_reg_attrs_from_value (reg, x);
1341 return reg;
1344 /* Set the register attributes for registers contained in PARM_RTX.
1345 Use needed values from memory attributes of MEM. */
1347 void
1348 set_reg_attrs_for_parm (rtx parm_rtx, rtx mem)
1350 if (REG_P (parm_rtx))
1351 set_reg_attrs_from_value (parm_rtx, mem);
1352 else if (GET_CODE (parm_rtx) == PARALLEL)
1354 /* Check for a NULL entry in the first slot, used to indicate that the
1355 parameter goes both on the stack and in registers. */
1356 int i = XEXP (XVECEXP (parm_rtx, 0, 0), 0) ? 0 : 1;
1357 for (; i < XVECLEN (parm_rtx, 0); i++)
1359 rtx x = XVECEXP (parm_rtx, 0, i);
1360 if (REG_P (XEXP (x, 0)))
1361 REG_ATTRS (XEXP (x, 0))
1362 = get_reg_attrs (MEM_EXPR (mem),
1363 INTVAL (XEXP (x, 1)));
1368 /* Set the REG_ATTRS for registers in value X, given that X represents
1369 decl T. */
1371 void
1372 set_reg_attrs_for_decl_rtl (tree t, rtx x)
1374 if (!t)
1375 return;
1376 tree tdecl = t;
1377 if (GET_CODE (x) == SUBREG)
1379 gcc_assert (subreg_lowpart_p (x));
1380 x = SUBREG_REG (x);
1382 if (REG_P (x))
1383 REG_ATTRS (x)
1384 = get_reg_attrs (t, byte_lowpart_offset (GET_MODE (x),
1385 DECL_P (tdecl)
1386 ? DECL_MODE (tdecl)
1387 : TYPE_MODE (TREE_TYPE (tdecl))));
1388 if (GET_CODE (x) == CONCAT)
1390 if (REG_P (XEXP (x, 0)))
1391 REG_ATTRS (XEXP (x, 0)) = get_reg_attrs (t, 0);
1392 if (REG_P (XEXP (x, 1)))
1393 REG_ATTRS (XEXP (x, 1))
1394 = get_reg_attrs (t, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x, 0))));
1396 if (GET_CODE (x) == PARALLEL)
1398 int i, start;
1400 /* Check for a NULL entry, used to indicate that the parameter goes
1401 both on the stack and in registers. */
1402 if (XEXP (XVECEXP (x, 0, 0), 0))
1403 start = 0;
1404 else
1405 start = 1;
1407 for (i = start; i < XVECLEN (x, 0); i++)
1409 rtx y = XVECEXP (x, 0, i);
1410 if (REG_P (XEXP (y, 0)))
1411 REG_ATTRS (XEXP (y, 0)) = get_reg_attrs (t, INTVAL (XEXP (y, 1)));
1416 /* Assign the RTX X to declaration T. */
1418 void
1419 set_decl_rtl (tree t, rtx x)
1421 DECL_WRTL_CHECK (t)->decl_with_rtl.rtl = x;
1422 if (x)
1423 set_reg_attrs_for_decl_rtl (t, x);
1426 /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true
1427 if the ABI requires the parameter to be passed by reference. */
1429 void
1430 set_decl_incoming_rtl (tree t, rtx x, bool by_reference_p)
1432 DECL_INCOMING_RTL (t) = x;
1433 if (x && !by_reference_p)
1434 set_reg_attrs_for_decl_rtl (t, x);
1437 /* Identify REG (which may be a CONCAT) as a user register. */
1439 void
1440 mark_user_reg (rtx reg)
1442 if (GET_CODE (reg) == CONCAT)
1444 REG_USERVAR_P (XEXP (reg, 0)) = 1;
1445 REG_USERVAR_P (XEXP (reg, 1)) = 1;
1447 else
1449 gcc_assert (REG_P (reg));
1450 REG_USERVAR_P (reg) = 1;
1454 /* Identify REG as a probable pointer register and show its alignment
1455 as ALIGN, if nonzero. */
1457 void
1458 mark_reg_pointer (rtx reg, int align)
1460 if (! REG_POINTER (reg))
1462 REG_POINTER (reg) = 1;
1464 if (align)
1465 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1467 else if (align && align < REGNO_POINTER_ALIGN (REGNO (reg)))
1468 /* We can no-longer be sure just how aligned this pointer is. */
1469 REGNO_POINTER_ALIGN (REGNO (reg)) = align;
1472 /* Return 1 plus largest pseudo reg number used in the current function. */
1475 max_reg_num (void)
1477 return reg_rtx_no;
1480 /* Return 1 + the largest label number used so far in the current function. */
1483 max_label_num (void)
1485 return label_num;
1488 /* Return first label number used in this function (if any were used). */
1491 get_first_label_num (void)
1493 return first_label_num;
1496 /* If the rtx for label was created during the expansion of a nested
1497 function, then first_label_num won't include this label number.
1498 Fix this now so that array indices work later. */
1500 void
1501 maybe_set_first_label_num (rtx_code_label *x)
1503 if (CODE_LABEL_NUMBER (x) < first_label_num)
1504 first_label_num = CODE_LABEL_NUMBER (x);
1507 /* For use by the RTL function loader, when mingling with normal
1508 functions.
1509 Ensure that label_num is greater than the label num of X, to avoid
1510 duplicate labels in the generated assembler. */
1512 void
1513 maybe_set_max_label_num (rtx_code_label *x)
1515 if (CODE_LABEL_NUMBER (x) >= label_num)
1516 label_num = CODE_LABEL_NUMBER (x) + 1;
1520 /* Return a value representing some low-order bits of X, where the number
1521 of low-order bits is given by MODE. Note that no conversion is done
1522 between floating-point and fixed-point values, rather, the bit
1523 representation is returned.
1525 This function handles the cases in common between gen_lowpart, below,
1526 and two variants in cse.c and combine.c. These are the cases that can
1527 be safely handled at all points in the compilation.
1529 If this is not a case we can handle, return 0. */
1532 gen_lowpart_common (machine_mode mode, rtx x)
1534 poly_uint64 msize = GET_MODE_SIZE (mode);
1535 machine_mode innermode;
1537 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1538 so we have to make one up. Yuk. */
1539 innermode = GET_MODE (x);
1540 if (CONST_INT_P (x)
1541 && known_le (msize * BITS_PER_UNIT,
1542 (unsigned HOST_WIDE_INT) HOST_BITS_PER_WIDE_INT))
1543 innermode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1544 else if (innermode == VOIDmode)
1545 innermode = int_mode_for_size (HOST_BITS_PER_DOUBLE_INT, 0).require ();
1547 gcc_assert (innermode != VOIDmode && innermode != BLKmode);
1549 if (innermode == mode)
1550 return x;
1552 /* The size of the outer and inner modes must be ordered. */
1553 poly_uint64 xsize = GET_MODE_SIZE (innermode);
1554 if (!ordered_p (msize, xsize))
1555 return 0;
1557 if (SCALAR_FLOAT_MODE_P (mode))
1559 /* Don't allow paradoxical FLOAT_MODE subregs. */
1560 if (maybe_gt (msize, xsize))
1561 return 0;
1563 else
1565 /* MODE must occupy no more of the underlying registers than X. */
1566 poly_uint64 regsize = REGMODE_NATURAL_SIZE (innermode);
1567 unsigned int mregs, xregs;
1568 if (!can_div_away_from_zero_p (msize, regsize, &mregs)
1569 || !can_div_away_from_zero_p (xsize, regsize, &xregs)
1570 || mregs > xregs)
1571 return 0;
1574 scalar_int_mode int_mode, int_innermode, from_mode;
1575 if ((GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
1576 && is_a <scalar_int_mode> (mode, &int_mode)
1577 && is_a <scalar_int_mode> (innermode, &int_innermode)
1578 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &from_mode))
1580 /* If we are getting the low-order part of something that has been
1581 sign- or zero-extended, we can either just use the object being
1582 extended or make a narrower extension. If we want an even smaller
1583 piece than the size of the object being extended, call ourselves
1584 recursively.
1586 This case is used mostly by combine and cse. */
1588 if (from_mode == int_mode)
1589 return XEXP (x, 0);
1590 else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (from_mode))
1591 return gen_lowpart_common (int_mode, XEXP (x, 0));
1592 else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode))
1593 return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
1595 else if (GET_CODE (x) == SUBREG || REG_P (x)
1596 || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
1597 || CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
1598 || CONST_POLY_INT_P (x))
1599 return lowpart_subreg (mode, x, innermode);
1601 /* Otherwise, we can't do this. */
1602 return 0;
1606 gen_highpart (machine_mode mode, rtx x)
1608 poly_uint64 msize = GET_MODE_SIZE (mode);
1609 rtx result;
1611 /* This case loses if X is a subreg. To catch bugs early,
1612 complain if an invalid MODE is used even in other cases. */
1613 gcc_assert (known_le (msize, (unsigned int) UNITS_PER_WORD)
1614 || known_eq (msize, GET_MODE_UNIT_SIZE (GET_MODE (x))));
1616 result = simplify_gen_subreg (mode, x, GET_MODE (x),
1617 subreg_highpart_offset (mode, GET_MODE (x)));
1618 gcc_assert (result);
1620 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1621 the target if we have a MEM. gen_highpart must return a valid operand,
1622 emitting code if necessary to do so. */
1623 if (MEM_P (result))
1625 result = validize_mem (result);
1626 gcc_assert (result);
1629 return result;
1632 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1633 be VOIDmode constant. */
1635 gen_highpart_mode (machine_mode outermode, machine_mode innermode, rtx exp)
1637 if (GET_MODE (exp) != VOIDmode)
1639 gcc_assert (GET_MODE (exp) == innermode);
1640 return gen_highpart (outermode, exp);
1642 return simplify_gen_subreg (outermode, exp, innermode,
1643 subreg_highpart_offset (outermode, innermode));
1646 /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has
1647 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1649 poly_uint64
1650 subreg_size_lowpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
1652 gcc_checking_assert (ordered_p (outer_bytes, inner_bytes));
1653 if (maybe_gt (outer_bytes, inner_bytes))
1654 /* Paradoxical subregs always have a SUBREG_BYTE of 0. */
1655 return 0;
1657 if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
1658 return inner_bytes - outer_bytes;
1659 else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN)
1660 return 0;
1661 else
1662 return subreg_size_offset_from_lsb (outer_bytes, inner_bytes, 0);
1665 /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has
1666 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1668 poly_uint64
1669 subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
1671 gcc_assert (known_ge (inner_bytes, outer_bytes));
1673 if (BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
1674 return 0;
1675 else if (!BYTES_BIG_ENDIAN && !WORDS_BIG_ENDIAN)
1676 return inner_bytes - outer_bytes;
1677 else
1678 return subreg_size_offset_from_lsb (outer_bytes, inner_bytes,
1679 (inner_bytes - outer_bytes)
1680 * BITS_PER_UNIT);
1683 /* Return 1 iff X, assumed to be a SUBREG,
1684 refers to the least significant part of its containing reg.
1685 If X is not a SUBREG, always return 1 (it is its own low part!). */
1688 subreg_lowpart_p (const_rtx x)
1690 if (GET_CODE (x) != SUBREG)
1691 return 1;
1692 else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
1693 return 0;
1695 return known_eq (subreg_lowpart_offset (GET_MODE (x),
1696 GET_MODE (SUBREG_REG (x))),
1697 SUBREG_BYTE (x));
1700 /* Return subword OFFSET of operand OP.
1701 The word number, OFFSET, is interpreted as the word number starting
1702 at the low-order address. OFFSET 0 is the low-order word if not
1703 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1705 If we cannot extract the required word, we return zero. Otherwise,
1706 an rtx corresponding to the requested word will be returned.
1708 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1709 reload has completed, a valid address will always be returned. After
1710 reload, if a valid address cannot be returned, we return zero.
1712 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1713 it is the responsibility of the caller.
1715 MODE is the mode of OP in case it is a CONST_INT.
1717 ??? This is still rather broken for some cases. The problem for the
1718 moment is that all callers of this thing provide no 'goal mode' to
1719 tell us to work with. This exists because all callers were written
1720 in a word based SUBREG world.
1721 Now use of this function can be deprecated by simplify_subreg in most
1722 cases.
1726 operand_subword (rtx op, poly_uint64 offset, int validate_address,
1727 machine_mode mode)
1729 if (mode == VOIDmode)
1730 mode = GET_MODE (op);
1732 gcc_assert (mode != VOIDmode);
1734 /* If OP is narrower than a word, fail. */
1735 if (mode != BLKmode
1736 && maybe_lt (GET_MODE_SIZE (mode), UNITS_PER_WORD))
1737 return 0;
1739 /* If we want a word outside OP, return zero. */
1740 if (mode != BLKmode
1741 && maybe_gt ((offset + 1) * UNITS_PER_WORD, GET_MODE_SIZE (mode)))
1742 return const0_rtx;
1744 /* Form a new MEM at the requested address. */
1745 if (MEM_P (op))
1747 rtx new_rtx = adjust_address_nv (op, word_mode, offset * UNITS_PER_WORD);
1749 if (! validate_address)
1750 return new_rtx;
1752 else if (reload_completed)
1754 if (! strict_memory_address_addr_space_p (word_mode,
1755 XEXP (new_rtx, 0),
1756 MEM_ADDR_SPACE (op)))
1757 return 0;
1759 else
1760 return replace_equiv_address (new_rtx, XEXP (new_rtx, 0));
1763 /* Rest can be handled by simplify_subreg. */
1764 return simplify_gen_subreg (word_mode, op, mode, (offset * UNITS_PER_WORD));
1767 /* Similar to `operand_subword', but never return 0. If we can't
1768 extract the required subword, put OP into a register and try again.
1769 The second attempt must succeed. We always validate the address in
1770 this case.
1772 MODE is the mode of OP, in case it is CONST_INT. */
1775 operand_subword_force (rtx op, poly_uint64 offset, machine_mode mode)
1777 rtx result = operand_subword (op, offset, 1, mode);
1779 if (result)
1780 return result;
1782 if (mode != BLKmode && mode != VOIDmode)
1784 /* If this is a register which can not be accessed by words, copy it
1785 to a pseudo register. */
1786 if (REG_P (op))
1787 op = copy_to_reg (op);
1788 else
1789 op = force_reg (mode, op);
1792 result = operand_subword (op, offset, 1, mode);
1793 gcc_assert (result);
1795 return result;
1798 mem_attrs::mem_attrs ()
1799 : expr (NULL_TREE),
1800 offset (0),
1801 size (0),
1802 alias (0),
1803 align (0),
1804 addrspace (ADDR_SPACE_GENERIC),
1805 offset_known_p (false),
1806 size_known_p (false)
1809 /* Returns 1 if both MEM_EXPR can be considered equal
1810 and 0 otherwise. */
1813 mem_expr_equal_p (const_tree expr1, const_tree expr2)
1815 if (expr1 == expr2)
1816 return 1;
1818 if (! expr1 || ! expr2)
1819 return 0;
1821 if (TREE_CODE (expr1) != TREE_CODE (expr2))
1822 return 0;
1824 return operand_equal_p (expr1, expr2, 0);
1827 /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN
1828 bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or
1829 -1 if not known. */
1832 get_mem_align_offset (rtx mem, unsigned int align)
1834 tree expr;
1835 poly_uint64 offset;
1837 /* This function can't use
1838 if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem)
1839 || (MAX (MEM_ALIGN (mem),
1840 MAX (align, get_object_alignment (MEM_EXPR (mem))))
1841 < align))
1842 return -1;
1843 else
1844 return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1);
1845 for two reasons:
1846 - COMPONENT_REFs in MEM_EXPR can have NULL first operand,
1847 for <variable>. get_inner_reference doesn't handle it and
1848 even if it did, the alignment in that case needs to be determined
1849 from DECL_FIELD_CONTEXT's TYPE_ALIGN.
1850 - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR
1851 isn't sufficiently aligned, the object it is in might be. */
1852 gcc_assert (MEM_P (mem));
1853 expr = MEM_EXPR (mem);
1854 if (expr == NULL_TREE || !MEM_OFFSET_KNOWN_P (mem))
1855 return -1;
1857 offset = MEM_OFFSET (mem);
1858 if (DECL_P (expr))
1860 if (DECL_ALIGN (expr) < align)
1861 return -1;
1863 else if (INDIRECT_REF_P (expr))
1865 if (TYPE_ALIGN (TREE_TYPE (expr)) < (unsigned int) align)
1866 return -1;
1868 else if (TREE_CODE (expr) == COMPONENT_REF)
1870 while (1)
1872 tree inner = TREE_OPERAND (expr, 0);
1873 tree field = TREE_OPERAND (expr, 1);
1874 tree byte_offset = component_ref_field_offset (expr);
1875 tree bit_offset = DECL_FIELD_BIT_OFFSET (field);
1877 poly_uint64 suboffset;
1878 if (!byte_offset
1879 || !poly_int_tree_p (byte_offset, &suboffset)
1880 || !tree_fits_uhwi_p (bit_offset))
1881 return -1;
1883 offset += suboffset;
1884 offset += tree_to_uhwi (bit_offset) / BITS_PER_UNIT;
1886 if (inner == NULL_TREE)
1888 if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field))
1889 < (unsigned int) align)
1890 return -1;
1891 break;
1893 else if (DECL_P (inner))
1895 if (DECL_ALIGN (inner) < align)
1896 return -1;
1897 break;
1899 else if (TREE_CODE (inner) != COMPONENT_REF)
1900 return -1;
1901 expr = inner;
1904 else
1905 return -1;
1907 HOST_WIDE_INT misalign;
1908 if (!known_misalignment (offset, align / BITS_PER_UNIT, &misalign))
1909 return -1;
1910 return misalign;
1913 /* Given REF (a MEM) and T, either the type of X or the expression
1914 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1915 if we are making a new object of this type. BITPOS is nonzero if
1916 there is an offset outstanding on T that will be applied later. */
1918 void
1919 set_mem_attributes_minus_bitpos (rtx ref, tree t, int objectp,
1920 poly_int64 bitpos)
1922 poly_int64 apply_bitpos = 0;
1923 tree type;
1924 struct mem_attrs attrs, *defattrs, *refattrs;
1925 addr_space_t as;
1927 /* It can happen that type_for_mode was given a mode for which there
1928 is no language-level type. In which case it returns NULL, which
1929 we can see here. */
1930 if (t == NULL_TREE)
1931 return;
1933 type = TYPE_P (t) ? t : TREE_TYPE (t);
1934 if (type == error_mark_node)
1935 return;
1937 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1938 wrong answer, as it assumes that DECL_RTL already has the right alias
1939 info. Callers should not set DECL_RTL until after the call to
1940 set_mem_attributes. */
1941 gcc_assert (!DECL_P (t) || ref != DECL_RTL_IF_SET (t));
1943 /* Get the alias set from the expression or type (perhaps using a
1944 front-end routine) and use it. */
1945 attrs.alias = get_alias_set (t);
1947 MEM_VOLATILE_P (ref) |= TYPE_VOLATILE (type);
1948 MEM_POINTER (ref) = POINTER_TYPE_P (type);
1950 /* Default values from pre-existing memory attributes if present. */
1951 refattrs = MEM_ATTRS (ref);
1952 if (refattrs)
1954 /* ??? Can this ever happen? Calling this routine on a MEM that
1955 already carries memory attributes should probably be invalid. */
1956 attrs.expr = refattrs->expr;
1957 attrs.offset_known_p = refattrs->offset_known_p;
1958 attrs.offset = refattrs->offset;
1959 attrs.size_known_p = refattrs->size_known_p;
1960 attrs.size = refattrs->size;
1961 attrs.align = refattrs->align;
1964 /* Otherwise, default values from the mode of the MEM reference. */
1965 else
1967 defattrs = mode_mem_attrs[(int) GET_MODE (ref)];
1968 gcc_assert (!defattrs->expr);
1969 gcc_assert (!defattrs->offset_known_p);
1971 /* Respect mode size. */
1972 attrs.size_known_p = defattrs->size_known_p;
1973 attrs.size = defattrs->size;
1974 /* ??? Is this really necessary? We probably should always get
1975 the size from the type below. */
1977 /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type;
1978 if T is an object, always compute the object alignment below. */
1979 if (TYPE_P (t))
1980 attrs.align = defattrs->align;
1981 else
1982 attrs.align = BITS_PER_UNIT;
1983 /* ??? If T is a type, respecting mode alignment may *also* be wrong
1984 e.g. if the type carries an alignment attribute. Should we be
1985 able to simply always use TYPE_ALIGN? */
1988 /* We can set the alignment from the type if we are making an object or if
1989 this is an INDIRECT_REF. */
1990 if (objectp || TREE_CODE (t) == INDIRECT_REF)
1991 attrs.align = MAX (attrs.align, TYPE_ALIGN (type));
1993 /* If the size is known, we can set that. */
1994 tree new_size = TYPE_SIZE_UNIT (type);
1996 /* The address-space is that of the type. */
1997 as = TYPE_ADDR_SPACE (type);
1999 /* If T is not a type, we may be able to deduce some more information about
2000 the expression. */
2001 if (! TYPE_P (t))
2003 tree base;
2005 if (TREE_THIS_VOLATILE (t))
2006 MEM_VOLATILE_P (ref) = 1;
2008 /* Now remove any conversions: they don't change what the underlying
2009 object is. Likewise for SAVE_EXPR. */
2010 while (CONVERT_EXPR_P (t)
2011 || TREE_CODE (t) == VIEW_CONVERT_EXPR
2012 || TREE_CODE (t) == SAVE_EXPR)
2013 t = TREE_OPERAND (t, 0);
2015 /* Note whether this expression can trap. */
2016 MEM_NOTRAP_P (ref) = !tree_could_trap_p (t);
2018 base = get_base_address (t);
2019 if (base)
2021 if (DECL_P (base)
2022 && TREE_READONLY (base)
2023 && (TREE_STATIC (base) || DECL_EXTERNAL (base))
2024 && !TREE_THIS_VOLATILE (base))
2025 MEM_READONLY_P (ref) = 1;
2027 /* Mark static const strings readonly as well. */
2028 if (TREE_CODE (base) == STRING_CST
2029 && TREE_READONLY (base)
2030 && TREE_STATIC (base))
2031 MEM_READONLY_P (ref) = 1;
2033 /* Address-space information is on the base object. */
2034 if (TREE_CODE (base) == MEM_REF
2035 || TREE_CODE (base) == TARGET_MEM_REF)
2036 as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base,
2037 0))));
2038 else
2039 as = TYPE_ADDR_SPACE (TREE_TYPE (base));
2042 /* If this expression uses it's parent's alias set, mark it such
2043 that we won't change it. */
2044 if (component_uses_parent_alias_set_from (t) != NULL_TREE)
2045 MEM_KEEP_ALIAS_SET_P (ref) = 1;
2047 /* If this is a decl, set the attributes of the MEM from it. */
2048 if (DECL_P (t))
2050 attrs.expr = t;
2051 attrs.offset_known_p = true;
2052 attrs.offset = 0;
2053 apply_bitpos = bitpos;
2054 new_size = DECL_SIZE_UNIT (t);
2057 /* ??? If we end up with a constant here do record a MEM_EXPR. */
2058 else if (CONSTANT_CLASS_P (t))
2061 /* If this is a field reference, record it. */
2062 else if (TREE_CODE (t) == COMPONENT_REF)
2064 attrs.expr = t;
2065 attrs.offset_known_p = true;
2066 attrs.offset = 0;
2067 apply_bitpos = bitpos;
2068 if (DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
2069 new_size = DECL_SIZE_UNIT (TREE_OPERAND (t, 1));
2072 /* If this is an array reference, look for an outer field reference. */
2073 else if (TREE_CODE (t) == ARRAY_REF)
2075 tree off_tree = size_zero_node;
2076 /* We can't modify t, because we use it at the end of the
2077 function. */
2078 tree t2 = t;
2082 tree index = TREE_OPERAND (t2, 1);
2083 tree low_bound = array_ref_low_bound (t2);
2084 tree unit_size = array_ref_element_size (t2);
2086 /* We assume all arrays have sizes that are a multiple of a byte.
2087 First subtract the lower bound, if any, in the type of the
2088 index, then convert to sizetype and multiply by the size of
2089 the array element. */
2090 if (! integer_zerop (low_bound))
2091 index = fold_build2 (MINUS_EXPR, TREE_TYPE (index),
2092 index, low_bound);
2094 off_tree = size_binop (PLUS_EXPR,
2095 size_binop (MULT_EXPR,
2096 fold_convert (sizetype,
2097 index),
2098 unit_size),
2099 off_tree);
2100 t2 = TREE_OPERAND (t2, 0);
2102 while (TREE_CODE (t2) == ARRAY_REF);
2104 if (DECL_P (t2)
2105 || (TREE_CODE (t2) == COMPONENT_REF
2106 /* For trailing arrays t2 doesn't have a size that
2107 covers all valid accesses. */
2108 && ! array_at_struct_end_p (t)))
2110 attrs.expr = t2;
2111 attrs.offset_known_p = false;
2112 if (poly_int_tree_p (off_tree, &attrs.offset))
2114 attrs.offset_known_p = true;
2115 apply_bitpos = bitpos;
2118 /* Else do not record a MEM_EXPR. */
2121 /* If this is an indirect reference, record it. */
2122 else if (TREE_CODE (t) == MEM_REF
2123 || TREE_CODE (t) == TARGET_MEM_REF)
2125 attrs.expr = t;
2126 attrs.offset_known_p = true;
2127 attrs.offset = 0;
2128 apply_bitpos = bitpos;
2131 /* Compute the alignment. */
2132 unsigned int obj_align;
2133 unsigned HOST_WIDE_INT obj_bitpos;
2134 get_object_alignment_1 (t, &obj_align, &obj_bitpos);
2135 unsigned int diff_align = known_alignment (obj_bitpos - bitpos);
2136 if (diff_align != 0)
2137 obj_align = MIN (obj_align, diff_align);
2138 attrs.align = MAX (attrs.align, obj_align);
2141 poly_uint64 const_size;
2142 if (poly_int_tree_p (new_size, &const_size))
2144 attrs.size_known_p = true;
2145 attrs.size = const_size;
2148 /* If we modified OFFSET based on T, then subtract the outstanding
2149 bit position offset. Similarly, increase the size of the accessed
2150 object to contain the negative offset. */
2151 if (maybe_ne (apply_bitpos, 0))
2153 gcc_assert (attrs.offset_known_p);
2154 poly_int64 bytepos = bits_to_bytes_round_down (apply_bitpos);
2155 attrs.offset -= bytepos;
2156 if (attrs.size_known_p)
2157 attrs.size += bytepos;
2160 /* Now set the attributes we computed above. */
2161 attrs.addrspace = as;
2162 set_mem_attrs (ref, &attrs);
2165 void
2166 set_mem_attributes (rtx ref, tree t, int objectp)
2168 set_mem_attributes_minus_bitpos (ref, t, objectp, 0);
2171 /* Set the alias set of MEM to SET. */
2173 void
2174 set_mem_alias_set (rtx mem, alias_set_type set)
2176 /* If the new and old alias sets don't conflict, something is wrong. */
2177 gcc_checking_assert (alias_sets_conflict_p (set, MEM_ALIAS_SET (mem)));
2178 mem_attrs attrs (*get_mem_attrs (mem));
2179 attrs.alias = set;
2180 set_mem_attrs (mem, &attrs);
2183 /* Set the address space of MEM to ADDRSPACE (target-defined). */
2185 void
2186 set_mem_addr_space (rtx mem, addr_space_t addrspace)
2188 mem_attrs attrs (*get_mem_attrs (mem));
2189 attrs.addrspace = addrspace;
2190 set_mem_attrs (mem, &attrs);
2193 /* Set the alignment of MEM to ALIGN bits. */
2195 void
2196 set_mem_align (rtx mem, unsigned int align)
2198 mem_attrs attrs (*get_mem_attrs (mem));
2199 attrs.align = align;
2200 set_mem_attrs (mem, &attrs);
2203 /* Set the expr for MEM to EXPR. */
2205 void
2206 set_mem_expr (rtx mem, tree expr)
2208 mem_attrs attrs (*get_mem_attrs (mem));
2209 attrs.expr = expr;
2210 set_mem_attrs (mem, &attrs);
2213 /* Set the offset of MEM to OFFSET. */
2215 void
2216 set_mem_offset (rtx mem, poly_int64 offset)
2218 mem_attrs attrs (*get_mem_attrs (mem));
2219 attrs.offset_known_p = true;
2220 attrs.offset = offset;
2221 set_mem_attrs (mem, &attrs);
2224 /* Clear the offset of MEM. */
2226 void
2227 clear_mem_offset (rtx mem)
2229 mem_attrs attrs (*get_mem_attrs (mem));
2230 attrs.offset_known_p = false;
2231 set_mem_attrs (mem, &attrs);
2234 /* Set the size of MEM to SIZE. */
2236 void
2237 set_mem_size (rtx mem, poly_int64 size)
2239 mem_attrs attrs (*get_mem_attrs (mem));
2240 attrs.size_known_p = true;
2241 attrs.size = size;
2242 set_mem_attrs (mem, &attrs);
2245 /* Clear the size of MEM. */
2247 void
2248 clear_mem_size (rtx mem)
2250 mem_attrs attrs (*get_mem_attrs (mem));
2251 attrs.size_known_p = false;
2252 set_mem_attrs (mem, &attrs);
2255 /* Return a memory reference like MEMREF, but with its mode changed to MODE
2256 and its address changed to ADDR. (VOIDmode means don't change the mode.
2257 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
2258 returned memory location is required to be valid. INPLACE is true if any
2259 changes can be made directly to MEMREF or false if MEMREF must be treated
2260 as immutable.
2262 The memory attributes are not changed. */
2264 static rtx
2265 change_address_1 (rtx memref, machine_mode mode, rtx addr, int validate,
2266 bool inplace)
2268 addr_space_t as;
2269 rtx new_rtx;
2271 gcc_assert (MEM_P (memref));
2272 as = MEM_ADDR_SPACE (memref);
2273 if (mode == VOIDmode)
2274 mode = GET_MODE (memref);
2275 if (addr == 0)
2276 addr = XEXP (memref, 0);
2277 if (mode == GET_MODE (memref) && addr == XEXP (memref, 0)
2278 && (!validate || memory_address_addr_space_p (mode, addr, as)))
2279 return memref;
2281 /* Don't validate address for LRA. LRA can make the address valid
2282 by itself in most efficient way. */
2283 if (validate && !lra_in_progress)
2285 if (reload_in_progress || reload_completed)
2286 gcc_assert (memory_address_addr_space_p (mode, addr, as));
2287 else
2288 addr = memory_address_addr_space (mode, addr, as);
2291 if (rtx_equal_p (addr, XEXP (memref, 0)) && mode == GET_MODE (memref))
2292 return memref;
2294 if (inplace)
2296 XEXP (memref, 0) = addr;
2297 return memref;
2300 new_rtx = gen_rtx_MEM (mode, addr);
2301 MEM_COPY_ATTRIBUTES (new_rtx, memref);
2302 return new_rtx;
2305 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
2306 way we are changing MEMREF, so we only preserve the alias set. */
2309 change_address (rtx memref, machine_mode mode, rtx addr)
2311 rtx new_rtx = change_address_1 (memref, mode, addr, 1, false);
2312 machine_mode mmode = GET_MODE (new_rtx);
2313 struct mem_attrs *defattrs;
2315 mem_attrs attrs (*get_mem_attrs (memref));
2316 defattrs = mode_mem_attrs[(int) mmode];
2317 attrs.expr = NULL_TREE;
2318 attrs.offset_known_p = false;
2319 attrs.size_known_p = defattrs->size_known_p;
2320 attrs.size = defattrs->size;
2321 attrs.align = defattrs->align;
2323 /* If there are no changes, just return the original memory reference. */
2324 if (new_rtx == memref)
2326 if (mem_attrs_eq_p (get_mem_attrs (memref), &attrs))
2327 return new_rtx;
2329 new_rtx = gen_rtx_MEM (mmode, XEXP (memref, 0));
2330 MEM_COPY_ATTRIBUTES (new_rtx, memref);
2333 set_mem_attrs (new_rtx, &attrs);
2334 return new_rtx;
2337 /* Return a memory reference like MEMREF, but with its mode changed
2338 to MODE and its address offset by OFFSET bytes. If VALIDATE is
2339 nonzero, the memory address is forced to be valid.
2340 If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS
2341 and the caller is responsible for adjusting MEMREF base register.
2342 If ADJUST_OBJECT is zero, the underlying object associated with the
2343 memory reference is left unchanged and the caller is responsible for
2344 dealing with it. Otherwise, if the new memory reference is outside
2345 the underlying object, even partially, then the object is dropped.
2346 SIZE, if nonzero, is the size of an access in cases where MODE
2347 has no inherent size. */
2350 adjust_address_1 (rtx memref, machine_mode mode, poly_int64 offset,
2351 int validate, int adjust_address, int adjust_object,
2352 poly_int64 size)
2354 rtx addr = XEXP (memref, 0);
2355 rtx new_rtx;
2356 scalar_int_mode address_mode;
2357 struct mem_attrs attrs (*get_mem_attrs (memref)), *defattrs;
2358 unsigned HOST_WIDE_INT max_align;
2359 #ifdef POINTERS_EXTEND_UNSIGNED
2360 scalar_int_mode pointer_mode
2361 = targetm.addr_space.pointer_mode (attrs.addrspace);
2362 #endif
2364 /* VOIDmode means no mode change for change_address_1. */
2365 if (mode == VOIDmode)
2366 mode = GET_MODE (memref);
2368 /* Take the size of non-BLKmode accesses from the mode. */
2369 defattrs = mode_mem_attrs[(int) mode];
2370 if (defattrs->size_known_p)
2371 size = defattrs->size;
2373 /* If there are no changes, just return the original memory reference. */
2374 if (mode == GET_MODE (memref)
2375 && known_eq (offset, 0)
2376 && (known_eq (size, 0)
2377 || (attrs.size_known_p && known_eq (attrs.size, size)))
2378 && (!validate || memory_address_addr_space_p (mode, addr,
2379 attrs.addrspace)))
2380 return memref;
2382 /* ??? Prefer to create garbage instead of creating shared rtl.
2383 This may happen even if offset is nonzero -- consider
2384 (plus (plus reg reg) const_int) -- so do this always. */
2385 addr = copy_rtx (addr);
2387 /* Convert a possibly large offset to a signed value within the
2388 range of the target address space. */
2389 address_mode = get_address_mode (memref);
2390 offset = trunc_int_for_mode (offset, address_mode);
2392 if (adjust_address)
2394 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
2395 object, we can merge it into the LO_SUM. */
2396 if (GET_MODE (memref) != BLKmode
2397 && GET_CODE (addr) == LO_SUM
2398 && known_in_range_p (offset,
2399 0, (GET_MODE_ALIGNMENT (GET_MODE (memref))
2400 / BITS_PER_UNIT)))
2401 addr = gen_rtx_LO_SUM (address_mode, XEXP (addr, 0),
2402 plus_constant (address_mode,
2403 XEXP (addr, 1), offset));
2404 #ifdef POINTERS_EXTEND_UNSIGNED
2405 /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid
2406 in that mode, we merge it into the ZERO_EXTEND. We take advantage of
2407 the fact that pointers are not allowed to overflow. */
2408 else if (POINTERS_EXTEND_UNSIGNED > 0
2409 && GET_CODE (addr) == ZERO_EXTEND
2410 && GET_MODE (XEXP (addr, 0)) == pointer_mode
2411 && known_eq (trunc_int_for_mode (offset, pointer_mode), offset))
2412 addr = gen_rtx_ZERO_EXTEND (address_mode,
2413 plus_constant (pointer_mode,
2414 XEXP (addr, 0), offset));
2415 #endif
2416 else
2417 addr = plus_constant (address_mode, addr, offset);
2420 new_rtx = change_address_1 (memref, mode, addr, validate, false);
2422 /* If the address is a REG, change_address_1 rightfully returns memref,
2423 but this would destroy memref's MEM_ATTRS. */
2424 if (new_rtx == memref && maybe_ne (offset, 0))
2425 new_rtx = copy_rtx (new_rtx);
2427 /* Conservatively drop the object if we don't know where we start from. */
2428 if (adjust_object && (!attrs.offset_known_p || !attrs.size_known_p))
2430 attrs.expr = NULL_TREE;
2431 attrs.alias = 0;
2434 /* Compute the new values of the memory attributes due to this adjustment.
2435 We add the offsets and update the alignment. */
2436 if (attrs.offset_known_p)
2438 attrs.offset += offset;
2440 /* Drop the object if the new left end is not within its bounds. */
2441 if (adjust_object && maybe_lt (attrs.offset, 0))
2443 attrs.expr = NULL_TREE;
2444 attrs.alias = 0;
2448 /* Compute the new alignment by taking the MIN of the alignment and the
2449 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
2450 if zero. */
2451 if (maybe_ne (offset, 0))
2453 max_align = known_alignment (offset) * BITS_PER_UNIT;
2454 attrs.align = MIN (attrs.align, max_align);
2457 if (maybe_ne (size, 0))
2459 /* Drop the object if the new right end is not within its bounds. */
2460 if (adjust_object && maybe_gt (offset + size, attrs.size))
2462 attrs.expr = NULL_TREE;
2463 attrs.alias = 0;
2465 attrs.size_known_p = true;
2466 attrs.size = size;
2468 else if (attrs.size_known_p)
2470 gcc_assert (!adjust_object);
2471 attrs.size -= offset;
2472 /* ??? The store_by_pieces machinery generates negative sizes,
2473 so don't assert for that here. */
2476 set_mem_attrs (new_rtx, &attrs);
2478 return new_rtx;
2481 /* Return a memory reference like MEMREF, but with its mode changed
2482 to MODE and its address changed to ADDR, which is assumed to be
2483 MEMREF offset by OFFSET bytes. If VALIDATE is
2484 nonzero, the memory address is forced to be valid. */
2487 adjust_automodify_address_1 (rtx memref, machine_mode mode, rtx addr,
2488 poly_int64 offset, int validate)
2490 memref = change_address_1 (memref, VOIDmode, addr, validate, false);
2491 return adjust_address_1 (memref, mode, offset, validate, 0, 0, 0);
2494 /* Return a memory reference like MEMREF, but whose address is changed by
2495 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
2496 known to be in OFFSET (possibly 1). */
2499 offset_address (rtx memref, rtx offset, unsigned HOST_WIDE_INT pow2)
2501 rtx new_rtx, addr = XEXP (memref, 0);
2502 machine_mode address_mode;
2503 struct mem_attrs *defattrs;
2505 mem_attrs attrs (*get_mem_attrs (memref));
2506 address_mode = get_address_mode (memref);
2507 new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset);
2509 /* At this point we don't know _why_ the address is invalid. It
2510 could have secondary memory references, multiplies or anything.
2512 However, if we did go and rearrange things, we can wind up not
2513 being able to recognize the magic around pic_offset_table_rtx.
2514 This stuff is fragile, and is yet another example of why it is
2515 bad to expose PIC machinery too early. */
2516 if (! memory_address_addr_space_p (GET_MODE (memref), new_rtx,
2517 attrs.addrspace)
2518 && GET_CODE (addr) == PLUS
2519 && XEXP (addr, 0) == pic_offset_table_rtx)
2521 addr = force_reg (GET_MODE (addr), addr);
2522 new_rtx = simplify_gen_binary (PLUS, address_mode, addr, offset);
2525 update_temp_slot_address (XEXP (memref, 0), new_rtx);
2526 new_rtx = change_address_1 (memref, VOIDmode, new_rtx, 1, false);
2528 /* If there are no changes, just return the original memory reference. */
2529 if (new_rtx == memref)
2530 return new_rtx;
2532 /* Update the alignment to reflect the offset. Reset the offset, which
2533 we don't know. */
2534 defattrs = mode_mem_attrs[(int) GET_MODE (new_rtx)];
2535 attrs.offset_known_p = false;
2536 attrs.size_known_p = defattrs->size_known_p;
2537 attrs.size = defattrs->size;
2538 attrs.align = MIN (attrs.align, pow2 * BITS_PER_UNIT);
2539 set_mem_attrs (new_rtx, &attrs);
2540 return new_rtx;
2543 /* Return a memory reference like MEMREF, but with its address changed to
2544 ADDR. The caller is asserting that the actual piece of memory pointed
2545 to is the same, just the form of the address is being changed, such as
2546 by putting something into a register. INPLACE is true if any changes
2547 can be made directly to MEMREF or false if MEMREF must be treated as
2548 immutable. */
2551 replace_equiv_address (rtx memref, rtx addr, bool inplace)
2553 /* change_address_1 copies the memory attribute structure without change
2554 and that's exactly what we want here. */
2555 update_temp_slot_address (XEXP (memref, 0), addr);
2556 return change_address_1 (memref, VOIDmode, addr, 1, inplace);
2559 /* Likewise, but the reference is not required to be valid. */
2562 replace_equiv_address_nv (rtx memref, rtx addr, bool inplace)
2564 return change_address_1 (memref, VOIDmode, addr, 0, inplace);
2567 /* Return a memory reference like MEMREF, but with its mode widened to
2568 MODE and offset by OFFSET. This would be used by targets that e.g.
2569 cannot issue QImode memory operations and have to use SImode memory
2570 operations plus masking logic. */
2573 widen_memory_access (rtx memref, machine_mode mode, poly_int64 offset)
2575 rtx new_rtx = adjust_address_1 (memref, mode, offset, 1, 1, 0, 0);
2576 poly_uint64 size = GET_MODE_SIZE (mode);
2578 /* If there are no changes, just return the original memory reference. */
2579 if (new_rtx == memref)
2580 return new_rtx;
2582 mem_attrs attrs (*get_mem_attrs (new_rtx));
2584 /* If we don't know what offset we were at within the expression, then
2585 we can't know if we've overstepped the bounds. */
2586 if (! attrs.offset_known_p)
2587 attrs.expr = NULL_TREE;
2589 while (attrs.expr)
2591 if (TREE_CODE (attrs.expr) == COMPONENT_REF)
2593 tree field = TREE_OPERAND (attrs.expr, 1);
2594 tree offset = component_ref_field_offset (attrs.expr);
2596 if (! DECL_SIZE_UNIT (field))
2598 attrs.expr = NULL_TREE;
2599 break;
2602 /* Is the field at least as large as the access? If so, ok,
2603 otherwise strip back to the containing structure. */
2604 if (poly_int_tree_p (DECL_SIZE_UNIT (field))
2605 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field)), size)
2606 && known_ge (attrs.offset, 0))
2607 break;
2609 poly_uint64 suboffset;
2610 if (!poly_int_tree_p (offset, &suboffset))
2612 attrs.expr = NULL_TREE;
2613 break;
2616 attrs.expr = TREE_OPERAND (attrs.expr, 0);
2617 attrs.offset += suboffset;
2618 attrs.offset += (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field))
2619 / BITS_PER_UNIT);
2621 /* Similarly for the decl. */
2622 else if (DECL_P (attrs.expr)
2623 && DECL_SIZE_UNIT (attrs.expr)
2624 && poly_int_tree_p (DECL_SIZE_UNIT (attrs.expr))
2625 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs.expr)),
2626 size)
2627 && known_ge (attrs.offset, 0))
2628 break;
2629 else
2631 /* The widened memory access overflows the expression, which means
2632 that it could alias another expression. Zap it. */
2633 attrs.expr = NULL_TREE;
2634 break;
2638 if (! attrs.expr)
2639 attrs.offset_known_p = false;
2641 /* The widened memory may alias other stuff, so zap the alias set. */
2642 /* ??? Maybe use get_alias_set on any remaining expression. */
2643 attrs.alias = 0;
2644 attrs.size_known_p = true;
2645 attrs.size = size;
2646 set_mem_attrs (new_rtx, &attrs);
2647 return new_rtx;
2650 /* A fake decl that is used as the MEM_EXPR of spill slots. */
2651 static GTY(()) tree spill_slot_decl;
2653 tree
2654 get_spill_slot_decl (bool force_build_p)
2656 tree d = spill_slot_decl;
2657 rtx rd;
2659 if (d || !force_build_p)
2660 return d;
2662 d = build_decl (DECL_SOURCE_LOCATION (current_function_decl),
2663 VAR_DECL, get_identifier ("%sfp"), void_type_node);
2664 DECL_ARTIFICIAL (d) = 1;
2665 DECL_IGNORED_P (d) = 1;
2666 TREE_USED (d) = 1;
2667 spill_slot_decl = d;
2669 rd = gen_rtx_MEM (BLKmode, frame_pointer_rtx);
2670 MEM_NOTRAP_P (rd) = 1;
2671 mem_attrs attrs (*mode_mem_attrs[(int) BLKmode]);
2672 attrs.alias = new_alias_set ();
2673 attrs.expr = d;
2674 set_mem_attrs (rd, &attrs);
2675 SET_DECL_RTL (d, rd);
2677 return d;
2680 /* Given MEM, a result from assign_stack_local, fill in the memory
2681 attributes as appropriate for a register allocator spill slot.
2682 These slots are not aliasable by other memory. We arrange for
2683 them all to use a single MEM_EXPR, so that the aliasing code can
2684 work properly in the case of shared spill slots. */
2686 void
2687 set_mem_attrs_for_spill (rtx mem)
2689 rtx addr;
2691 mem_attrs attrs (*get_mem_attrs (mem));
2692 attrs.expr = get_spill_slot_decl (true);
2693 attrs.alias = MEM_ALIAS_SET (DECL_RTL (attrs.expr));
2694 attrs.addrspace = ADDR_SPACE_GENERIC;
2696 /* We expect the incoming memory to be of the form:
2697 (mem:MODE (plus (reg sfp) (const_int offset)))
2698 with perhaps the plus missing for offset = 0. */
2699 addr = XEXP (mem, 0);
2700 attrs.offset_known_p = true;
2701 strip_offset (addr, &attrs.offset);
2703 set_mem_attrs (mem, &attrs);
2704 MEM_NOTRAP_P (mem) = 1;
2707 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2709 rtx_code_label *
2710 gen_label_rtx (void)
2712 return as_a <rtx_code_label *> (
2713 gen_rtx_CODE_LABEL (VOIDmode, NULL_RTX, NULL_RTX,
2714 NULL, label_num++, NULL));
2717 /* For procedure integration. */
2719 /* Install new pointers to the first and last insns in the chain.
2720 Also, set cur_insn_uid to one higher than the last in use.
2721 Used for an inline-procedure after copying the insn chain. */
2723 void
2724 set_new_first_and_last_insn (rtx_insn *first, rtx_insn *last)
2726 rtx_insn *insn;
2728 set_first_insn (first);
2729 set_last_insn (last);
2730 cur_insn_uid = 0;
2732 if (MIN_NONDEBUG_INSN_UID || MAY_HAVE_DEBUG_INSNS)
2734 int debug_count = 0;
2736 cur_insn_uid = MIN_NONDEBUG_INSN_UID - 1;
2737 cur_debug_insn_uid = 0;
2739 for (insn = first; insn; insn = NEXT_INSN (insn))
2740 if (INSN_UID (insn) < MIN_NONDEBUG_INSN_UID)
2741 cur_debug_insn_uid = MAX (cur_debug_insn_uid, INSN_UID (insn));
2742 else
2744 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2745 if (DEBUG_INSN_P (insn))
2746 debug_count++;
2749 if (debug_count)
2750 cur_debug_insn_uid = MIN_NONDEBUG_INSN_UID + debug_count;
2751 else
2752 cur_debug_insn_uid++;
2754 else
2755 for (insn = first; insn; insn = NEXT_INSN (insn))
2756 cur_insn_uid = MAX (cur_insn_uid, INSN_UID (insn));
2758 cur_insn_uid++;
2761 /* Go through all the RTL insn bodies and copy any invalid shared
2762 structure. This routine should only be called once. */
2764 static void
2765 unshare_all_rtl_1 (rtx_insn *insn)
2767 /* Unshare just about everything else. */
2768 unshare_all_rtl_in_chain (insn);
2770 /* Make sure the addresses of stack slots found outside the insn chain
2771 (such as, in DECL_RTL of a variable) are not shared
2772 with the insn chain.
2774 This special care is necessary when the stack slot MEM does not
2775 actually appear in the insn chain. If it does appear, its address
2776 is unshared from all else at that point. */
2777 unsigned int i;
2778 rtx temp;
2779 FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp)
2780 (*stack_slot_list)[i] = copy_rtx_if_shared (temp);
2783 /* Go through all the RTL insn bodies and copy any invalid shared
2784 structure, again. This is a fairly expensive thing to do so it
2785 should be done sparingly. */
2787 void
2788 unshare_all_rtl_again (rtx_insn *insn)
2790 rtx_insn *p;
2791 tree decl;
2793 for (p = insn; p; p = NEXT_INSN (p))
2794 if (INSN_P (p))
2796 reset_used_flags (PATTERN (p));
2797 reset_used_flags (REG_NOTES (p));
2798 if (CALL_P (p))
2799 reset_used_flags (CALL_INSN_FUNCTION_USAGE (p));
2802 /* Make sure that virtual stack slots are not shared. */
2803 set_used_decls (DECL_INITIAL (cfun->decl));
2805 /* Make sure that virtual parameters are not shared. */
2806 for (decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl))
2807 set_used_flags (DECL_RTL (decl));
2809 rtx temp;
2810 unsigned int i;
2811 FOR_EACH_VEC_SAFE_ELT (stack_slot_list, i, temp)
2812 reset_used_flags (temp);
2814 unshare_all_rtl_1 (insn);
2817 unsigned int
2818 unshare_all_rtl (void)
2820 unshare_all_rtl_1 (get_insns ());
2822 for (tree decl = DECL_ARGUMENTS (cfun->decl); decl; decl = DECL_CHAIN (decl))
2824 if (DECL_RTL_SET_P (decl))
2825 SET_DECL_RTL (decl, copy_rtx_if_shared (DECL_RTL (decl)));
2826 DECL_INCOMING_RTL (decl) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl));
2829 return 0;
2833 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2834 Recursively does the same for subexpressions. */
2836 static void
2837 verify_rtx_sharing (rtx orig, rtx insn)
2839 rtx x = orig;
2840 int i;
2841 enum rtx_code code;
2842 const char *format_ptr;
2844 if (x == 0)
2845 return;
2847 code = GET_CODE (x);
2849 /* These types may be freely shared. */
2851 switch (code)
2853 case REG:
2854 case DEBUG_EXPR:
2855 case VALUE:
2856 CASE_CONST_ANY:
2857 case SYMBOL_REF:
2858 case LABEL_REF:
2859 case CODE_LABEL:
2860 case PC:
2861 case CC0:
2862 case RETURN:
2863 case SIMPLE_RETURN:
2864 case SCRATCH:
2865 /* SCRATCH must be shared because they represent distinct values. */
2866 return;
2867 case CLOBBER:
2868 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
2869 clobbers or clobbers of hard registers that originated as pseudos.
2870 This is needed to allow safe register renaming. */
2871 if (REG_P (XEXP (x, 0))
2872 && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0)))
2873 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0))))
2874 return;
2875 break;
2877 case CONST:
2878 if (shared_const_p (orig))
2879 return;
2880 break;
2882 case MEM:
2883 /* A MEM is allowed to be shared if its address is constant. */
2884 if (CONSTANT_ADDRESS_P (XEXP (x, 0))
2885 || reload_completed || reload_in_progress)
2886 return;
2888 break;
2890 default:
2891 break;
2894 /* This rtx may not be shared. If it has already been seen,
2895 replace it with a copy of itself. */
2896 if (flag_checking && RTX_FLAG (x, used))
2898 error ("invalid rtl sharing found in the insn");
2899 debug_rtx (insn);
2900 error ("shared rtx");
2901 debug_rtx (x);
2902 internal_error ("internal consistency failure");
2904 gcc_assert (!RTX_FLAG (x, used));
2906 RTX_FLAG (x, used) = 1;
2908 /* Now scan the subexpressions recursively. */
2910 format_ptr = GET_RTX_FORMAT (code);
2912 for (i = 0; i < GET_RTX_LENGTH (code); i++)
2914 switch (*format_ptr++)
2916 case 'e':
2917 verify_rtx_sharing (XEXP (x, i), insn);
2918 break;
2920 case 'E':
2921 if (XVEC (x, i) != NULL)
2923 int j;
2924 int len = XVECLEN (x, i);
2926 for (j = 0; j < len; j++)
2928 /* We allow sharing of ASM_OPERANDS inside single
2929 instruction. */
2930 if (j && GET_CODE (XVECEXP (x, i, j)) == SET
2931 && (GET_CODE (SET_SRC (XVECEXP (x, i, j)))
2932 == ASM_OPERANDS))
2933 verify_rtx_sharing (SET_DEST (XVECEXP (x, i, j)), insn);
2934 else
2935 verify_rtx_sharing (XVECEXP (x, i, j), insn);
2938 break;
2941 return;
2944 /* Reset used-flags for INSN. */
2946 static void
2947 reset_insn_used_flags (rtx insn)
2949 gcc_assert (INSN_P (insn));
2950 reset_used_flags (PATTERN (insn));
2951 reset_used_flags (REG_NOTES (insn));
2952 if (CALL_P (insn))
2953 reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn));
2956 /* Go through all the RTL insn bodies and clear all the USED bits. */
2958 static void
2959 reset_all_used_flags (void)
2961 rtx_insn *p;
2963 for (p = get_insns (); p; p = NEXT_INSN (p))
2964 if (INSN_P (p))
2966 rtx pat = PATTERN (p);
2967 if (GET_CODE (pat) != SEQUENCE)
2968 reset_insn_used_flags (p);
2969 else
2971 gcc_assert (REG_NOTES (p) == NULL);
2972 for (int i = 0; i < XVECLEN (pat, 0); i++)
2974 rtx insn = XVECEXP (pat, 0, i);
2975 if (INSN_P (insn))
2976 reset_insn_used_flags (insn);
2982 /* Verify sharing in INSN. */
2984 static void
2985 verify_insn_sharing (rtx insn)
2987 gcc_assert (INSN_P (insn));
2988 verify_rtx_sharing (PATTERN (insn), insn);
2989 verify_rtx_sharing (REG_NOTES (insn), insn);
2990 if (CALL_P (insn))
2991 verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn), insn);
2994 /* Go through all the RTL insn bodies and check that there is no unexpected
2995 sharing in between the subexpressions. */
2997 DEBUG_FUNCTION void
2998 verify_rtl_sharing (void)
3000 rtx_insn *p;
3002 timevar_push (TV_VERIFY_RTL_SHARING);
3004 reset_all_used_flags ();
3006 for (p = get_insns (); p; p = NEXT_INSN (p))
3007 if (INSN_P (p))
3009 rtx pat = PATTERN (p);
3010 if (GET_CODE (pat) != SEQUENCE)
3011 verify_insn_sharing (p);
3012 else
3013 for (int i = 0; i < XVECLEN (pat, 0); i++)
3015 rtx insn = XVECEXP (pat, 0, i);
3016 if (INSN_P (insn))
3017 verify_insn_sharing (insn);
3021 reset_all_used_flags ();
3023 timevar_pop (TV_VERIFY_RTL_SHARING);
3026 /* Go through all the RTL insn bodies and copy any invalid shared structure.
3027 Assumes the mark bits are cleared at entry. */
3029 void
3030 unshare_all_rtl_in_chain (rtx_insn *insn)
3032 for (; insn; insn = NEXT_INSN (insn))
3033 if (INSN_P (insn))
3035 PATTERN (insn) = copy_rtx_if_shared (PATTERN (insn));
3036 REG_NOTES (insn) = copy_rtx_if_shared (REG_NOTES (insn));
3037 if (CALL_P (insn))
3038 CALL_INSN_FUNCTION_USAGE (insn)
3039 = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn));
3043 /* Go through all virtual stack slots of a function and mark them as
3044 shared. We never replace the DECL_RTLs themselves with a copy,
3045 but expressions mentioned into a DECL_RTL cannot be shared with
3046 expressions in the instruction stream.
3048 Note that reload may convert pseudo registers into memories in-place.
3049 Pseudo registers are always shared, but MEMs never are. Thus if we
3050 reset the used flags on MEMs in the instruction stream, we must set
3051 them again on MEMs that appear in DECL_RTLs. */
3053 static void
3054 set_used_decls (tree blk)
3056 tree t;
3058 /* Mark decls. */
3059 for (t = BLOCK_VARS (blk); t; t = DECL_CHAIN (t))
3060 if (DECL_RTL_SET_P (t))
3061 set_used_flags (DECL_RTL (t));
3063 /* Now process sub-blocks. */
3064 for (t = BLOCK_SUBBLOCKS (blk); t; t = BLOCK_CHAIN (t))
3065 set_used_decls (t);
3068 /* Mark ORIG as in use, and return a copy of it if it was already in use.
3069 Recursively does the same for subexpressions. Uses
3070 copy_rtx_if_shared_1 to reduce stack space. */
3073 copy_rtx_if_shared (rtx orig)
3075 copy_rtx_if_shared_1 (&orig);
3076 return orig;
3079 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
3080 use. Recursively does the same for subexpressions. */
3082 static void
3083 copy_rtx_if_shared_1 (rtx *orig1)
3085 rtx x;
3086 int i;
3087 enum rtx_code code;
3088 rtx *last_ptr;
3089 const char *format_ptr;
3090 int copied = 0;
3091 int length;
3093 /* Repeat is used to turn tail-recursion into iteration. */
3094 repeat:
3095 x = *orig1;
3097 if (x == 0)
3098 return;
3100 code = GET_CODE (x);
3102 /* These types may be freely shared. */
3104 switch (code)
3106 case REG:
3107 case DEBUG_EXPR:
3108 case VALUE:
3109 CASE_CONST_ANY:
3110 case SYMBOL_REF:
3111 case LABEL_REF:
3112 case CODE_LABEL:
3113 case PC:
3114 case CC0:
3115 case RETURN:
3116 case SIMPLE_RETURN:
3117 case SCRATCH:
3118 /* SCRATCH must be shared because they represent distinct values. */
3119 return;
3120 case CLOBBER:
3121 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
3122 clobbers or clobbers of hard registers that originated as pseudos.
3123 This is needed to allow safe register renaming. */
3124 if (REG_P (XEXP (x, 0))
3125 && HARD_REGISTER_NUM_P (REGNO (XEXP (x, 0)))
3126 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x, 0))))
3127 return;
3128 break;
3130 case CONST:
3131 if (shared_const_p (x))
3132 return;
3133 break;
3135 case DEBUG_INSN:
3136 case INSN:
3137 case JUMP_INSN:
3138 case CALL_INSN:
3139 case NOTE:
3140 case BARRIER:
3141 /* The chain of insns is not being copied. */
3142 return;
3144 default:
3145 break;
3148 /* This rtx may not be shared. If it has already been seen,
3149 replace it with a copy of itself. */
3151 if (RTX_FLAG (x, used))
3153 x = shallow_copy_rtx (x);
3154 copied = 1;
3156 RTX_FLAG (x, used) = 1;
3158 /* Now scan the subexpressions recursively.
3159 We can store any replaced subexpressions directly into X
3160 since we know X is not shared! Any vectors in X
3161 must be copied if X was copied. */
3163 format_ptr = GET_RTX_FORMAT (code);
3164 length = GET_RTX_LENGTH (code);
3165 last_ptr = NULL;
3167 for (i = 0; i < length; i++)
3169 switch (*format_ptr++)
3171 case 'e':
3172 if (last_ptr)
3173 copy_rtx_if_shared_1 (last_ptr);
3174 last_ptr = &XEXP (x, i);
3175 break;
3177 case 'E':
3178 if (XVEC (x, i) != NULL)
3180 int j;
3181 int len = XVECLEN (x, i);
3183 /* Copy the vector iff I copied the rtx and the length
3184 is nonzero. */
3185 if (copied && len > 0)
3186 XVEC (x, i) = gen_rtvec_v (len, XVEC (x, i)->elem);
3188 /* Call recursively on all inside the vector. */
3189 for (j = 0; j < len; j++)
3191 if (last_ptr)
3192 copy_rtx_if_shared_1 (last_ptr);
3193 last_ptr = &XVECEXP (x, i, j);
3196 break;
3199 *orig1 = x;
3200 if (last_ptr)
3202 orig1 = last_ptr;
3203 goto repeat;
3205 return;
3208 /* Set the USED bit in X and its non-shareable subparts to FLAG. */
3210 static void
3211 mark_used_flags (rtx x, int flag)
3213 int i, j;
3214 enum rtx_code code;
3215 const char *format_ptr;
3216 int length;
3218 /* Repeat is used to turn tail-recursion into iteration. */
3219 repeat:
3220 if (x == 0)
3221 return;
3223 code = GET_CODE (x);
3225 /* These types may be freely shared so we needn't do any resetting
3226 for them. */
3228 switch (code)
3230 case REG:
3231 case DEBUG_EXPR:
3232 case VALUE:
3233 CASE_CONST_ANY:
3234 case SYMBOL_REF:
3235 case CODE_LABEL:
3236 case PC:
3237 case CC0:
3238 case RETURN:
3239 case SIMPLE_RETURN:
3240 return;
3242 case DEBUG_INSN:
3243 case INSN:
3244 case JUMP_INSN:
3245 case CALL_INSN:
3246 case NOTE:
3247 case LABEL_REF:
3248 case BARRIER:
3249 /* The chain of insns is not being copied. */
3250 return;
3252 default:
3253 break;
3256 RTX_FLAG (x, used) = flag;
3258 format_ptr = GET_RTX_FORMAT (code);
3259 length = GET_RTX_LENGTH (code);
3261 for (i = 0; i < length; i++)
3263 switch (*format_ptr++)
3265 case 'e':
3266 if (i == length-1)
3268 x = XEXP (x, i);
3269 goto repeat;
3271 mark_used_flags (XEXP (x, i), flag);
3272 break;
3274 case 'E':
3275 for (j = 0; j < XVECLEN (x, i); j++)
3276 mark_used_flags (XVECEXP (x, i, j), flag);
3277 break;
3282 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
3283 to look for shared sub-parts. */
3285 void
3286 reset_used_flags (rtx x)
3288 mark_used_flags (x, 0);
3291 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
3292 to look for shared sub-parts. */
3294 void
3295 set_used_flags (rtx x)
3297 mark_used_flags (x, 1);
3300 /* Copy X if necessary so that it won't be altered by changes in OTHER.
3301 Return X or the rtx for the pseudo reg the value of X was copied into.
3302 OTHER must be valid as a SET_DEST. */
3305 make_safe_from (rtx x, rtx other)
3307 while (1)
3308 switch (GET_CODE (other))
3310 case SUBREG:
3311 other = SUBREG_REG (other);
3312 break;
3313 case STRICT_LOW_PART:
3314 case SIGN_EXTEND:
3315 case ZERO_EXTEND:
3316 other = XEXP (other, 0);
3317 break;
3318 default:
3319 goto done;
3321 done:
3322 if ((MEM_P (other)
3323 && ! CONSTANT_P (x)
3324 && !REG_P (x)
3325 && GET_CODE (x) != SUBREG)
3326 || (REG_P (other)
3327 && (REGNO (other) < FIRST_PSEUDO_REGISTER
3328 || reg_mentioned_p (other, x))))
3330 rtx temp = gen_reg_rtx (GET_MODE (x));
3331 emit_move_insn (temp, x);
3332 return temp;
3334 return x;
3337 /* Emission of insns (adding them to the doubly-linked list). */
3339 /* Return the last insn emitted, even if it is in a sequence now pushed. */
3341 rtx_insn *
3342 get_last_insn_anywhere (void)
3344 struct sequence_stack *seq;
3345 for (seq = get_current_sequence (); seq; seq = seq->next)
3346 if (seq->last != 0)
3347 return seq->last;
3348 return 0;
3351 /* Return the first nonnote insn emitted in current sequence or current
3352 function. This routine looks inside SEQUENCEs. */
3354 rtx_insn *
3355 get_first_nonnote_insn (void)
3357 rtx_insn *insn = get_insns ();
3359 if (insn)
3361 if (NOTE_P (insn))
3362 for (insn = next_insn (insn);
3363 insn && NOTE_P (insn);
3364 insn = next_insn (insn))
3365 continue;
3366 else
3368 if (NONJUMP_INSN_P (insn)
3369 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3370 insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0);
3374 return insn;
3377 /* Return the last nonnote insn emitted in current sequence or current
3378 function. This routine looks inside SEQUENCEs. */
3380 rtx_insn *
3381 get_last_nonnote_insn (void)
3383 rtx_insn *insn = get_last_insn ();
3385 if (insn)
3387 if (NOTE_P (insn))
3388 for (insn = previous_insn (insn);
3389 insn && NOTE_P (insn);
3390 insn = previous_insn (insn))
3391 continue;
3392 else
3394 if (NONJUMP_INSN_P (insn))
3395 if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
3396 insn = seq->insn (seq->len () - 1);
3400 return insn;
3403 /* Return the number of actual (non-debug) insns emitted in this
3404 function. */
3407 get_max_insn_count (void)
3409 int n = cur_insn_uid;
3411 /* The table size must be stable across -g, to avoid codegen
3412 differences due to debug insns, and not be affected by
3413 -fmin-insn-uid, to avoid excessive table size and to simplify
3414 debugging of -fcompare-debug failures. */
3415 if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID)
3416 n -= cur_debug_insn_uid;
3417 else
3418 n -= MIN_NONDEBUG_INSN_UID;
3420 return n;
3424 /* Return the next insn. If it is a SEQUENCE, return the first insn
3425 of the sequence. */
3427 rtx_insn *
3428 next_insn (rtx_insn *insn)
3430 if (insn)
3432 insn = NEXT_INSN (insn);
3433 if (insn && NONJUMP_INSN_P (insn)
3434 && GET_CODE (PATTERN (insn)) == SEQUENCE)
3435 insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0);
3438 return insn;
3441 /* Return the previous insn. If it is a SEQUENCE, return the last insn
3442 of the sequence. */
3444 rtx_insn *
3445 previous_insn (rtx_insn *insn)
3447 if (insn)
3449 insn = PREV_INSN (insn);
3450 if (insn && NONJUMP_INSN_P (insn))
3451 if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
3452 insn = seq->insn (seq->len () - 1);
3455 return insn;
3458 /* Return the next insn after INSN that is not a NOTE. This routine does not
3459 look inside SEQUENCEs. */
3461 rtx_insn *
3462 next_nonnote_insn (rtx_insn *insn)
3464 while (insn)
3466 insn = NEXT_INSN (insn);
3467 if (insn == 0 || !NOTE_P (insn))
3468 break;
3471 return insn;
3474 /* Return the next insn after INSN that is not a DEBUG_INSN. This
3475 routine does not look inside SEQUENCEs. */
3477 rtx_insn *
3478 next_nondebug_insn (rtx_insn *insn)
3480 while (insn)
3482 insn = NEXT_INSN (insn);
3483 if (insn == 0 || !DEBUG_INSN_P (insn))
3484 break;
3487 return insn;
3490 /* Return the previous insn before INSN that is not a NOTE. This routine does
3491 not look inside SEQUENCEs. */
3493 rtx_insn *
3494 prev_nonnote_insn (rtx_insn *insn)
3496 while (insn)
3498 insn = PREV_INSN (insn);
3499 if (insn == 0 || !NOTE_P (insn))
3500 break;
3503 return insn;
3506 /* Return the previous insn before INSN that is not a DEBUG_INSN.
3507 This routine does not look inside SEQUENCEs. */
3509 rtx_insn *
3510 prev_nondebug_insn (rtx_insn *insn)
3512 while (insn)
3514 insn = PREV_INSN (insn);
3515 if (insn == 0 || !DEBUG_INSN_P (insn))
3516 break;
3519 return insn;
3522 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN.
3523 This routine does not look inside SEQUENCEs. */
3525 rtx_insn *
3526 next_nonnote_nondebug_insn (rtx_insn *insn)
3528 while (insn)
3530 insn = NEXT_INSN (insn);
3531 if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn)))
3532 break;
3535 return insn;
3538 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN,
3539 but stop the search before we enter another basic block. This
3540 routine does not look inside SEQUENCEs. */
3542 rtx_insn *
3543 next_nonnote_nondebug_insn_bb (rtx_insn *insn)
3545 while (insn)
3547 insn = NEXT_INSN (insn);
3548 if (insn == 0)
3549 break;
3550 if (DEBUG_INSN_P (insn))
3551 continue;
3552 if (!NOTE_P (insn))
3553 break;
3554 if (NOTE_INSN_BASIC_BLOCK_P (insn))
3555 return NULL;
3558 return insn;
3561 /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN.
3562 This routine does not look inside SEQUENCEs. */
3564 rtx_insn *
3565 prev_nonnote_nondebug_insn (rtx_insn *insn)
3567 while (insn)
3569 insn = PREV_INSN (insn);
3570 if (insn == 0 || (!NOTE_P (insn) && !DEBUG_INSN_P (insn)))
3571 break;
3574 return insn;
3577 /* Return the previous insn before INSN that is not a NOTE nor
3578 DEBUG_INSN, but stop the search before we enter another basic
3579 block. This routine does not look inside SEQUENCEs. */
3581 rtx_insn *
3582 prev_nonnote_nondebug_insn_bb (rtx_insn *insn)
3584 while (insn)
3586 insn = PREV_INSN (insn);
3587 if (insn == 0)
3588 break;
3589 if (DEBUG_INSN_P (insn))
3590 continue;
3591 if (!NOTE_P (insn))
3592 break;
3593 if (NOTE_INSN_BASIC_BLOCK_P (insn))
3594 return NULL;
3597 return insn;
3600 /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN;
3601 or 0, if there is none. This routine does not look inside
3602 SEQUENCEs. */
3604 rtx_insn *
3605 next_real_insn (rtx_insn *insn)
3607 while (insn)
3609 insn = NEXT_INSN (insn);
3610 if (insn == 0 || INSN_P (insn))
3611 break;
3614 return insn;
3617 /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN;
3618 or 0, if there is none. This routine does not look inside
3619 SEQUENCEs. */
3621 rtx_insn *
3622 prev_real_insn (rtx_insn *insn)
3624 while (insn)
3626 insn = PREV_INSN (insn);
3627 if (insn == 0 || INSN_P (insn))
3628 break;
3631 return insn;
3634 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
3635 or 0, if there is none. This routine does not look inside
3636 SEQUENCEs. */
3638 rtx_insn *
3639 next_real_nondebug_insn (rtx uncast_insn)
3641 rtx_insn *insn = safe_as_a <rtx_insn *> (uncast_insn);
3643 while (insn)
3645 insn = NEXT_INSN (insn);
3646 if (insn == 0 || NONDEBUG_INSN_P (insn))
3647 break;
3650 return insn;
3653 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
3654 or 0, if there is none. This routine does not look inside
3655 SEQUENCEs. */
3657 rtx_insn *
3658 prev_real_nondebug_insn (rtx_insn *insn)
3660 while (insn)
3662 insn = PREV_INSN (insn);
3663 if (insn == 0 || NONDEBUG_INSN_P (insn))
3664 break;
3667 return insn;
3670 /* Return the last CALL_INSN in the current list, or 0 if there is none.
3671 This routine does not look inside SEQUENCEs. */
3673 rtx_call_insn *
3674 last_call_insn (void)
3676 rtx_insn *insn;
3678 for (insn = get_last_insn ();
3679 insn && !CALL_P (insn);
3680 insn = PREV_INSN (insn))
3683 return safe_as_a <rtx_call_insn *> (insn);
3686 /* Find the next insn after INSN that really does something. This routine
3687 does not look inside SEQUENCEs. After reload this also skips over
3688 standalone USE and CLOBBER insn. */
3691 active_insn_p (const rtx_insn *insn)
3693 return (CALL_P (insn) || JUMP_P (insn)
3694 || JUMP_TABLE_DATA_P (insn) /* FIXME */
3695 || (NONJUMP_INSN_P (insn)
3696 && (! reload_completed
3697 || (GET_CODE (PATTERN (insn)) != USE
3698 && GET_CODE (PATTERN (insn)) != CLOBBER))));
3701 rtx_insn *
3702 next_active_insn (rtx_insn *insn)
3704 while (insn)
3706 insn = NEXT_INSN (insn);
3707 if (insn == 0 || active_insn_p (insn))
3708 break;
3711 return insn;
3714 /* Find the last insn before INSN that really does something. This routine
3715 does not look inside SEQUENCEs. After reload this also skips over
3716 standalone USE and CLOBBER insn. */
3718 rtx_insn *
3719 prev_active_insn (rtx_insn *insn)
3721 while (insn)
3723 insn = PREV_INSN (insn);
3724 if (insn == 0 || active_insn_p (insn))
3725 break;
3728 return insn;
3731 /* Return the next insn that uses CC0 after INSN, which is assumed to
3732 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3733 applied to the result of this function should yield INSN).
3735 Normally, this is simply the next insn. However, if a REG_CC_USER note
3736 is present, it contains the insn that uses CC0.
3738 Return 0 if we can't find the insn. */
3740 rtx_insn *
3741 next_cc0_user (rtx_insn *insn)
3743 rtx note = find_reg_note (insn, REG_CC_USER, NULL_RTX);
3745 if (note)
3746 return safe_as_a <rtx_insn *> (XEXP (note, 0));
3748 insn = next_nonnote_insn (insn);
3749 if (insn && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
3750 insn = as_a <rtx_sequence *> (PATTERN (insn))->insn (0);
3752 if (insn && INSN_P (insn) && reg_mentioned_p (cc0_rtx, PATTERN (insn)))
3753 return insn;
3755 return 0;
3758 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3759 note, it is the previous insn. */
3761 rtx_insn *
3762 prev_cc0_setter (rtx_insn *insn)
3764 rtx note = find_reg_note (insn, REG_CC_SETTER, NULL_RTX);
3766 if (note)
3767 return safe_as_a <rtx_insn *> (XEXP (note, 0));
3769 insn = prev_nonnote_insn (insn);
3770 gcc_assert (sets_cc0_p (PATTERN (insn)));
3772 return insn;
3775 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3777 static int
3778 find_auto_inc (const_rtx x, const_rtx reg)
3780 subrtx_iterator::array_type array;
3781 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
3783 const_rtx x = *iter;
3784 if (GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC
3785 && rtx_equal_p (reg, XEXP (x, 0)))
3786 return true;
3788 return false;
3791 /* Increment the label uses for all labels present in rtx. */
3793 static void
3794 mark_label_nuses (rtx x)
3796 enum rtx_code code;
3797 int i, j;
3798 const char *fmt;
3800 code = GET_CODE (x);
3801 if (code == LABEL_REF && LABEL_P (label_ref_label (x)))
3802 LABEL_NUSES (label_ref_label (x))++;
3804 fmt = GET_RTX_FORMAT (code);
3805 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3807 if (fmt[i] == 'e')
3808 mark_label_nuses (XEXP (x, i));
3809 else if (fmt[i] == 'E')
3810 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3811 mark_label_nuses (XVECEXP (x, i, j));
3816 /* Try splitting insns that can be split for better scheduling.
3817 PAT is the pattern which might split.
3818 TRIAL is the insn providing PAT.
3819 LAST is nonzero if we should return the last insn of the sequence produced.
3821 If this routine succeeds in splitting, it returns the first or last
3822 replacement insn depending on the value of LAST. Otherwise, it
3823 returns TRIAL. If the insn to be returned can be split, it will be. */
3825 rtx_insn *
3826 try_split (rtx pat, rtx_insn *trial, int last)
3828 rtx_insn *before, *after;
3829 rtx note;
3830 rtx_insn *seq, *tem;
3831 profile_probability probability;
3832 rtx_insn *insn_last, *insn;
3833 int njumps = 0;
3834 rtx_insn *call_insn = NULL;
3836 /* We're not good at redistributing frame information. */
3837 if (RTX_FRAME_RELATED_P (trial))
3838 return trial;
3840 if (any_condjump_p (trial)
3841 && (note = find_reg_note (trial, REG_BR_PROB, 0)))
3842 split_branch_probability
3843 = profile_probability::from_reg_br_prob_note (XINT (note, 0));
3844 else
3845 split_branch_probability = profile_probability::uninitialized ();
3847 probability = split_branch_probability;
3849 seq = split_insns (pat, trial);
3851 split_branch_probability = profile_probability::uninitialized ();
3853 if (!seq)
3854 return trial;
3856 /* Avoid infinite loop if any insn of the result matches
3857 the original pattern. */
3858 insn_last = seq;
3859 while (1)
3861 if (INSN_P (insn_last)
3862 && rtx_equal_p (PATTERN (insn_last), pat))
3863 return trial;
3864 if (!NEXT_INSN (insn_last))
3865 break;
3866 insn_last = NEXT_INSN (insn_last);
3869 /* We will be adding the new sequence to the function. The splitters
3870 may have introduced invalid RTL sharing, so unshare the sequence now. */
3871 unshare_all_rtl_in_chain (seq);
3873 /* Mark labels and copy flags. */
3874 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3876 if (JUMP_P (insn))
3878 if (JUMP_P (trial))
3879 CROSSING_JUMP_P (insn) = CROSSING_JUMP_P (trial);
3880 mark_jump_label (PATTERN (insn), insn, 0);
3881 njumps++;
3882 if (probability.initialized_p ()
3883 && any_condjump_p (insn)
3884 && !find_reg_note (insn, REG_BR_PROB, 0))
3886 /* We can preserve the REG_BR_PROB notes only if exactly
3887 one jump is created, otherwise the machine description
3888 is responsible for this step using
3889 split_branch_probability variable. */
3890 gcc_assert (njumps == 1);
3891 add_reg_br_prob_note (insn, probability);
3896 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3897 in SEQ and copy any additional information across. */
3898 if (CALL_P (trial))
3900 for (insn = insn_last; insn ; insn = PREV_INSN (insn))
3901 if (CALL_P (insn))
3903 gcc_assert (call_insn == NULL_RTX);
3904 call_insn = insn;
3906 /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the
3907 target may have explicitly specified. */
3908 rtx *p = &CALL_INSN_FUNCTION_USAGE (insn);
3909 while (*p)
3910 p = &XEXP (*p, 1);
3911 *p = CALL_INSN_FUNCTION_USAGE (trial);
3913 /* If the old call was a sibling call, the new one must
3914 be too. */
3915 SIBLING_CALL_P (insn) = SIBLING_CALL_P (trial);
3919 /* Copy notes, particularly those related to the CFG. */
3920 for (note = REG_NOTES (trial); note; note = XEXP (note, 1))
3922 switch (REG_NOTE_KIND (note))
3924 case REG_EH_REGION:
3925 copy_reg_eh_region_note_backward (note, insn_last, NULL);
3926 break;
3928 case REG_NORETURN:
3929 case REG_SETJMP:
3930 case REG_TM:
3931 case REG_CALL_NOCF_CHECK:
3932 case REG_CALL_ARG_LOCATION:
3933 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3935 if (CALL_P (insn))
3936 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
3938 break;
3940 case REG_NON_LOCAL_GOTO:
3941 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3943 if (JUMP_P (insn))
3944 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
3946 break;
3948 case REG_INC:
3949 if (!AUTO_INC_DEC)
3950 break;
3952 for (insn = insn_last; insn != NULL_RTX; insn = PREV_INSN (insn))
3954 rtx reg = XEXP (note, 0);
3955 if (!FIND_REG_INC_NOTE (insn, reg)
3956 && find_auto_inc (PATTERN (insn), reg))
3957 add_reg_note (insn, REG_INC, reg);
3959 break;
3961 case REG_ARGS_SIZE:
3962 fixup_args_size_notes (NULL, insn_last, get_args_size (note));
3963 break;
3965 case REG_CALL_DECL:
3966 gcc_assert (call_insn != NULL_RTX);
3967 add_reg_note (call_insn, REG_NOTE_KIND (note), XEXP (note, 0));
3968 break;
3970 default:
3971 break;
3975 /* If there are LABELS inside the split insns increment the
3976 usage count so we don't delete the label. */
3977 if (INSN_P (trial))
3979 insn = insn_last;
3980 while (insn != NULL_RTX)
3982 /* JUMP_P insns have already been "marked" above. */
3983 if (NONJUMP_INSN_P (insn))
3984 mark_label_nuses (PATTERN (insn));
3986 insn = PREV_INSN (insn);
3990 before = PREV_INSN (trial);
3991 after = NEXT_INSN (trial);
3993 tem = emit_insn_after_setloc (seq, trial, INSN_LOCATION (trial));
3995 delete_insn (trial);
3997 /* Recursively call try_split for each new insn created; by the
3998 time control returns here that insn will be fully split, so
3999 set LAST and continue from the insn after the one returned.
4000 We can't use next_active_insn here since AFTER may be a note.
4001 Ignore deleted insns, which can be occur if not optimizing. */
4002 for (tem = NEXT_INSN (before); tem != after; tem = NEXT_INSN (tem))
4003 if (! tem->deleted () && INSN_P (tem))
4004 tem = try_split (PATTERN (tem), tem, 1);
4006 /* Return either the first or the last insn, depending on which was
4007 requested. */
4008 return last
4009 ? (after ? PREV_INSN (after) : get_last_insn ())
4010 : NEXT_INSN (before);
4013 /* Make and return an INSN rtx, initializing all its slots.
4014 Store PATTERN in the pattern slots. */
4016 rtx_insn *
4017 make_insn_raw (rtx pattern)
4019 rtx_insn *insn;
4021 insn = as_a <rtx_insn *> (rtx_alloc (INSN));
4023 INSN_UID (insn) = cur_insn_uid++;
4024 PATTERN (insn) = pattern;
4025 INSN_CODE (insn) = -1;
4026 REG_NOTES (insn) = NULL;
4027 INSN_LOCATION (insn) = curr_insn_location ();
4028 BLOCK_FOR_INSN (insn) = NULL;
4030 #ifdef ENABLE_RTL_CHECKING
4031 if (insn
4032 && INSN_P (insn)
4033 && (returnjump_p (insn)
4034 || (GET_CODE (insn) == SET
4035 && SET_DEST (insn) == pc_rtx)))
4037 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
4038 debug_rtx (insn);
4040 #endif
4042 return insn;
4045 /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */
4047 static rtx_insn *
4048 make_debug_insn_raw (rtx pattern)
4050 rtx_debug_insn *insn;
4052 insn = as_a <rtx_debug_insn *> (rtx_alloc (DEBUG_INSN));
4053 INSN_UID (insn) = cur_debug_insn_uid++;
4054 if (cur_debug_insn_uid > MIN_NONDEBUG_INSN_UID)
4055 INSN_UID (insn) = cur_insn_uid++;
4057 PATTERN (insn) = pattern;
4058 INSN_CODE (insn) = -1;
4059 REG_NOTES (insn) = NULL;
4060 INSN_LOCATION (insn) = curr_insn_location ();
4061 BLOCK_FOR_INSN (insn) = NULL;
4063 return insn;
4066 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
4068 static rtx_insn *
4069 make_jump_insn_raw (rtx pattern)
4071 rtx_jump_insn *insn;
4073 insn = as_a <rtx_jump_insn *> (rtx_alloc (JUMP_INSN));
4074 INSN_UID (insn) = cur_insn_uid++;
4076 PATTERN (insn) = pattern;
4077 INSN_CODE (insn) = -1;
4078 REG_NOTES (insn) = NULL;
4079 JUMP_LABEL (insn) = NULL;
4080 INSN_LOCATION (insn) = curr_insn_location ();
4081 BLOCK_FOR_INSN (insn) = NULL;
4083 return insn;
4086 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
4088 static rtx_insn *
4089 make_call_insn_raw (rtx pattern)
4091 rtx_call_insn *insn;
4093 insn = as_a <rtx_call_insn *> (rtx_alloc (CALL_INSN));
4094 INSN_UID (insn) = cur_insn_uid++;
4096 PATTERN (insn) = pattern;
4097 INSN_CODE (insn) = -1;
4098 REG_NOTES (insn) = NULL;
4099 CALL_INSN_FUNCTION_USAGE (insn) = NULL;
4100 INSN_LOCATION (insn) = curr_insn_location ();
4101 BLOCK_FOR_INSN (insn) = NULL;
4103 return insn;
4106 /* Like `make_insn_raw' but make a NOTE instead of an insn. */
4108 static rtx_note *
4109 make_note_raw (enum insn_note subtype)
4111 /* Some notes are never created this way at all. These notes are
4112 only created by patching out insns. */
4113 gcc_assert (subtype != NOTE_INSN_DELETED_LABEL
4114 && subtype != NOTE_INSN_DELETED_DEBUG_LABEL);
4116 rtx_note *note = as_a <rtx_note *> (rtx_alloc (NOTE));
4117 INSN_UID (note) = cur_insn_uid++;
4118 NOTE_KIND (note) = subtype;
4119 BLOCK_FOR_INSN (note) = NULL;
4120 memset (&NOTE_DATA (note), 0, sizeof (NOTE_DATA (note)));
4121 return note;
4124 /* Add INSN to the end of the doubly-linked list, between PREV and NEXT.
4125 INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects,
4126 but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */
4128 static inline void
4129 link_insn_into_chain (rtx_insn *insn, rtx_insn *prev, rtx_insn *next)
4131 SET_PREV_INSN (insn) = prev;
4132 SET_NEXT_INSN (insn) = next;
4133 if (prev != NULL)
4135 SET_NEXT_INSN (prev) = insn;
4136 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
4138 rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev));
4139 SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = insn;
4142 if (next != NULL)
4144 SET_PREV_INSN (next) = insn;
4145 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
4147 rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next));
4148 SET_PREV_INSN (sequence->insn (0)) = insn;
4152 if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
4154 rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (insn));
4155 SET_PREV_INSN (sequence->insn (0)) = prev;
4156 SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next;
4160 /* Add INSN to the end of the doubly-linked list.
4161 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
4163 void
4164 add_insn (rtx_insn *insn)
4166 rtx_insn *prev = get_last_insn ();
4167 link_insn_into_chain (insn, prev, NULL);
4168 if (get_insns () == NULL)
4169 set_first_insn (insn);
4170 set_last_insn (insn);
4173 /* Add INSN into the doubly-linked list after insn AFTER. */
4175 static void
4176 add_insn_after_nobb (rtx_insn *insn, rtx_insn *after)
4178 rtx_insn *next = NEXT_INSN (after);
4180 gcc_assert (!optimize || !after->deleted ());
4182 link_insn_into_chain (insn, after, next);
4184 if (next == NULL)
4186 struct sequence_stack *seq;
4188 for (seq = get_current_sequence (); seq; seq = seq->next)
4189 if (after == seq->last)
4191 seq->last = insn;
4192 break;
4197 /* Add INSN into the doubly-linked list before insn BEFORE. */
4199 static void
4200 add_insn_before_nobb (rtx_insn *insn, rtx_insn *before)
4202 rtx_insn *prev = PREV_INSN (before);
4204 gcc_assert (!optimize || !before->deleted ());
4206 link_insn_into_chain (insn, prev, before);
4208 if (prev == NULL)
4210 struct sequence_stack *seq;
4212 for (seq = get_current_sequence (); seq; seq = seq->next)
4213 if (before == seq->first)
4215 seq->first = insn;
4216 break;
4219 gcc_assert (seq);
4223 /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN.
4224 If BB is NULL, an attempt is made to infer the bb from before.
4226 This and the next function should be the only functions called
4227 to insert an insn once delay slots have been filled since only
4228 they know how to update a SEQUENCE. */
4230 void
4231 add_insn_after (rtx_insn *insn, rtx_insn *after, basic_block bb)
4233 add_insn_after_nobb (insn, after);
4234 if (!BARRIER_P (after)
4235 && !BARRIER_P (insn)
4236 && (bb = BLOCK_FOR_INSN (after)))
4238 set_block_for_insn (insn, bb);
4239 if (INSN_P (insn))
4240 df_insn_rescan (insn);
4241 /* Should not happen as first in the BB is always
4242 either NOTE or LABEL. */
4243 if (BB_END (bb) == after
4244 /* Avoid clobbering of structure when creating new BB. */
4245 && !BARRIER_P (insn)
4246 && !NOTE_INSN_BASIC_BLOCK_P (insn))
4247 BB_END (bb) = insn;
4251 /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN.
4252 If BB is NULL, an attempt is made to infer the bb from before.
4254 This and the previous function should be the only functions called
4255 to insert an insn once delay slots have been filled since only
4256 they know how to update a SEQUENCE. */
4258 void
4259 add_insn_before (rtx_insn *insn, rtx_insn *before, basic_block bb)
4261 add_insn_before_nobb (insn, before);
4263 if (!bb
4264 && !BARRIER_P (before)
4265 && !BARRIER_P (insn))
4266 bb = BLOCK_FOR_INSN (before);
4268 if (bb)
4270 set_block_for_insn (insn, bb);
4271 if (INSN_P (insn))
4272 df_insn_rescan (insn);
4273 /* Should not happen as first in the BB is always either NOTE or
4274 LABEL. */
4275 gcc_assert (BB_HEAD (bb) != insn
4276 /* Avoid clobbering of structure when creating new BB. */
4277 || BARRIER_P (insn)
4278 || NOTE_INSN_BASIC_BLOCK_P (insn));
4282 /* Replace insn with an deleted instruction note. */
4284 void
4285 set_insn_deleted (rtx_insn *insn)
4287 if (INSN_P (insn))
4288 df_insn_delete (insn);
4289 PUT_CODE (insn, NOTE);
4290 NOTE_KIND (insn) = NOTE_INSN_DELETED;
4294 /* Unlink INSN from the insn chain.
4296 This function knows how to handle sequences.
4298 This function does not invalidate data flow information associated with
4299 INSN (i.e. does not call df_insn_delete). That makes this function
4300 usable for only disconnecting an insn from the chain, and re-emit it
4301 elsewhere later.
4303 To later insert INSN elsewhere in the insn chain via add_insn and
4304 similar functions, PREV_INSN and NEXT_INSN must be nullified by
4305 the caller. Nullifying them here breaks many insn chain walks.
4307 To really delete an insn and related DF information, use delete_insn. */
4309 void
4310 remove_insn (rtx_insn *insn)
4312 rtx_insn *next = NEXT_INSN (insn);
4313 rtx_insn *prev = PREV_INSN (insn);
4314 basic_block bb;
4316 if (prev)
4318 SET_NEXT_INSN (prev) = next;
4319 if (NONJUMP_INSN_P (prev) && GET_CODE (PATTERN (prev)) == SEQUENCE)
4321 rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (prev));
4322 SET_NEXT_INSN (sequence->insn (sequence->len () - 1)) = next;
4325 else
4327 struct sequence_stack *seq;
4329 for (seq = get_current_sequence (); seq; seq = seq->next)
4330 if (insn == seq->first)
4332 seq->first = next;
4333 break;
4336 gcc_assert (seq);
4339 if (next)
4341 SET_PREV_INSN (next) = prev;
4342 if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
4344 rtx_sequence *sequence = as_a <rtx_sequence *> (PATTERN (next));
4345 SET_PREV_INSN (sequence->insn (0)) = prev;
4348 else
4350 struct sequence_stack *seq;
4352 for (seq = get_current_sequence (); seq; seq = seq->next)
4353 if (insn == seq->last)
4355 seq->last = prev;
4356 break;
4359 gcc_assert (seq);
4362 /* Fix up basic block boundaries, if necessary. */
4363 if (!BARRIER_P (insn)
4364 && (bb = BLOCK_FOR_INSN (insn)))
4366 if (BB_HEAD (bb) == insn)
4368 /* Never ever delete the basic block note without deleting whole
4369 basic block. */
4370 gcc_assert (!NOTE_P (insn));
4371 BB_HEAD (bb) = next;
4373 if (BB_END (bb) == insn)
4374 BB_END (bb) = prev;
4378 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
4380 void
4381 add_function_usage_to (rtx call_insn, rtx call_fusage)
4383 gcc_assert (call_insn && CALL_P (call_insn));
4385 /* Put the register usage information on the CALL. If there is already
4386 some usage information, put ours at the end. */
4387 if (CALL_INSN_FUNCTION_USAGE (call_insn))
4389 rtx link;
4391 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); XEXP (link, 1) != 0;
4392 link = XEXP (link, 1))
4395 XEXP (link, 1) = call_fusage;
4397 else
4398 CALL_INSN_FUNCTION_USAGE (call_insn) = call_fusage;
4401 /* Delete all insns made since FROM.
4402 FROM becomes the new last instruction. */
4404 void
4405 delete_insns_since (rtx_insn *from)
4407 if (from == 0)
4408 set_first_insn (0);
4409 else
4410 SET_NEXT_INSN (from) = 0;
4411 set_last_insn (from);
4414 /* This function is deprecated, please use sequences instead.
4416 Move a consecutive bunch of insns to a different place in the chain.
4417 The insns to be moved are those between FROM and TO.
4418 They are moved to a new position after the insn AFTER.
4419 AFTER must not be FROM or TO or any insn in between.
4421 This function does not know about SEQUENCEs and hence should not be
4422 called after delay-slot filling has been done. */
4424 void
4425 reorder_insns_nobb (rtx_insn *from, rtx_insn *to, rtx_insn *after)
4427 if (flag_checking)
4429 for (rtx_insn *x = from; x != to; x = NEXT_INSN (x))
4430 gcc_assert (after != x);
4431 gcc_assert (after != to);
4434 /* Splice this bunch out of where it is now. */
4435 if (PREV_INSN (from))
4436 SET_NEXT_INSN (PREV_INSN (from)) = NEXT_INSN (to);
4437 if (NEXT_INSN (to))
4438 SET_PREV_INSN (NEXT_INSN (to)) = PREV_INSN (from);
4439 if (get_last_insn () == to)
4440 set_last_insn (PREV_INSN (from));
4441 if (get_insns () == from)
4442 set_first_insn (NEXT_INSN (to));
4444 /* Make the new neighbors point to it and it to them. */
4445 if (NEXT_INSN (after))
4446 SET_PREV_INSN (NEXT_INSN (after)) = to;
4448 SET_NEXT_INSN (to) = NEXT_INSN (after);
4449 SET_PREV_INSN (from) = after;
4450 SET_NEXT_INSN (after) = from;
4451 if (after == get_last_insn ())
4452 set_last_insn (to);
4455 /* Same as function above, but take care to update BB boundaries. */
4456 void
4457 reorder_insns (rtx_insn *from, rtx_insn *to, rtx_insn *after)
4459 rtx_insn *prev = PREV_INSN (from);
4460 basic_block bb, bb2;
4462 reorder_insns_nobb (from, to, after);
4464 if (!BARRIER_P (after)
4465 && (bb = BLOCK_FOR_INSN (after)))
4467 rtx_insn *x;
4468 df_set_bb_dirty (bb);
4470 if (!BARRIER_P (from)
4471 && (bb2 = BLOCK_FOR_INSN (from)))
4473 if (BB_END (bb2) == to)
4474 BB_END (bb2) = prev;
4475 df_set_bb_dirty (bb2);
4478 if (BB_END (bb) == after)
4479 BB_END (bb) = to;
4481 for (x = from; x != NEXT_INSN (to); x = NEXT_INSN (x))
4482 if (!BARRIER_P (x))
4483 df_insn_change_bb (x, bb);
4488 /* Emit insn(s) of given code and pattern
4489 at a specified place within the doubly-linked list.
4491 All of the emit_foo global entry points accept an object
4492 X which is either an insn list or a PATTERN of a single
4493 instruction.
4495 There are thus a few canonical ways to generate code and
4496 emit it at a specific place in the instruction stream. For
4497 example, consider the instruction named SPOT and the fact that
4498 we would like to emit some instructions before SPOT. We might
4499 do it like this:
4501 start_sequence ();
4502 ... emit the new instructions ...
4503 insns_head = get_insns ();
4504 end_sequence ();
4506 emit_insn_before (insns_head, SPOT);
4508 It used to be common to generate SEQUENCE rtl instead, but that
4509 is a relic of the past which no longer occurs. The reason is that
4510 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
4511 generated would almost certainly die right after it was created. */
4513 static rtx_insn *
4514 emit_pattern_before_noloc (rtx x, rtx_insn *before, rtx_insn *last,
4515 basic_block bb,
4516 rtx_insn *(*make_raw) (rtx))
4518 rtx_insn *insn;
4520 gcc_assert (before);
4522 if (x == NULL_RTX)
4523 return last;
4525 switch (GET_CODE (x))
4527 case DEBUG_INSN:
4528 case INSN:
4529 case JUMP_INSN:
4530 case CALL_INSN:
4531 case CODE_LABEL:
4532 case BARRIER:
4533 case NOTE:
4534 insn = as_a <rtx_insn *> (x);
4535 while (insn)
4537 rtx_insn *next = NEXT_INSN (insn);
4538 add_insn_before (insn, before, bb);
4539 last = insn;
4540 insn = next;
4542 break;
4544 #ifdef ENABLE_RTL_CHECKING
4545 case SEQUENCE:
4546 gcc_unreachable ();
4547 break;
4548 #endif
4550 default:
4551 last = (*make_raw) (x);
4552 add_insn_before (last, before, bb);
4553 break;
4556 return last;
4559 /* Make X be output before the instruction BEFORE. */
4561 rtx_insn *
4562 emit_insn_before_noloc (rtx x, rtx_insn *before, basic_block bb)
4564 return emit_pattern_before_noloc (x, before, before, bb, make_insn_raw);
4567 /* Make an instruction with body X and code JUMP_INSN
4568 and output it before the instruction BEFORE. */
4570 rtx_jump_insn *
4571 emit_jump_insn_before_noloc (rtx x, rtx_insn *before)
4573 return as_a <rtx_jump_insn *> (
4574 emit_pattern_before_noloc (x, before, NULL, NULL,
4575 make_jump_insn_raw));
4578 /* Make an instruction with body X and code CALL_INSN
4579 and output it before the instruction BEFORE. */
4581 rtx_insn *
4582 emit_call_insn_before_noloc (rtx x, rtx_insn *before)
4584 return emit_pattern_before_noloc (x, before, NULL, NULL,
4585 make_call_insn_raw);
4588 /* Make an instruction with body X and code DEBUG_INSN
4589 and output it before the instruction BEFORE. */
4591 rtx_insn *
4592 emit_debug_insn_before_noloc (rtx x, rtx_insn *before)
4594 return emit_pattern_before_noloc (x, before, NULL, NULL,
4595 make_debug_insn_raw);
4598 /* Make an insn of code BARRIER
4599 and output it before the insn BEFORE. */
4601 rtx_barrier *
4602 emit_barrier_before (rtx_insn *before)
4604 rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER));
4606 INSN_UID (insn) = cur_insn_uid++;
4608 add_insn_before (insn, before, NULL);
4609 return insn;
4612 /* Emit the label LABEL before the insn BEFORE. */
4614 rtx_code_label *
4615 emit_label_before (rtx_code_label *label, rtx_insn *before)
4617 gcc_checking_assert (INSN_UID (label) == 0);
4618 INSN_UID (label) = cur_insn_uid++;
4619 add_insn_before (label, before, NULL);
4620 return label;
4623 /* Helper for emit_insn_after, handles lists of instructions
4624 efficiently. */
4626 static rtx_insn *
4627 emit_insn_after_1 (rtx_insn *first, rtx_insn *after, basic_block bb)
4629 rtx_insn *last;
4630 rtx_insn *after_after;
4631 if (!bb && !BARRIER_P (after))
4632 bb = BLOCK_FOR_INSN (after);
4634 if (bb)
4636 df_set_bb_dirty (bb);
4637 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
4638 if (!BARRIER_P (last))
4640 set_block_for_insn (last, bb);
4641 df_insn_rescan (last);
4643 if (!BARRIER_P (last))
4645 set_block_for_insn (last, bb);
4646 df_insn_rescan (last);
4648 if (BB_END (bb) == after)
4649 BB_END (bb) = last;
4651 else
4652 for (last = first; NEXT_INSN (last); last = NEXT_INSN (last))
4653 continue;
4655 after_after = NEXT_INSN (after);
4657 SET_NEXT_INSN (after) = first;
4658 SET_PREV_INSN (first) = after;
4659 SET_NEXT_INSN (last) = after_after;
4660 if (after_after)
4661 SET_PREV_INSN (after_after) = last;
4663 if (after == get_last_insn ())
4664 set_last_insn (last);
4666 return last;
4669 static rtx_insn *
4670 emit_pattern_after_noloc (rtx x, rtx_insn *after, basic_block bb,
4671 rtx_insn *(*make_raw)(rtx))
4673 rtx_insn *last = after;
4675 gcc_assert (after);
4677 if (x == NULL_RTX)
4678 return last;
4680 switch (GET_CODE (x))
4682 case DEBUG_INSN:
4683 case INSN:
4684 case JUMP_INSN:
4685 case CALL_INSN:
4686 case CODE_LABEL:
4687 case BARRIER:
4688 case NOTE:
4689 last = emit_insn_after_1 (as_a <rtx_insn *> (x), after, bb);
4690 break;
4692 #ifdef ENABLE_RTL_CHECKING
4693 case SEQUENCE:
4694 gcc_unreachable ();
4695 break;
4696 #endif
4698 default:
4699 last = (*make_raw) (x);
4700 add_insn_after (last, after, bb);
4701 break;
4704 return last;
4707 /* Make X be output after the insn AFTER and set the BB of insn. If
4708 BB is NULL, an attempt is made to infer the BB from AFTER. */
4710 rtx_insn *
4711 emit_insn_after_noloc (rtx x, rtx_insn *after, basic_block bb)
4713 return emit_pattern_after_noloc (x, after, bb, make_insn_raw);
4717 /* Make an insn of code JUMP_INSN with body X
4718 and output it after the insn AFTER. */
4720 rtx_jump_insn *
4721 emit_jump_insn_after_noloc (rtx x, rtx_insn *after)
4723 return as_a <rtx_jump_insn *> (
4724 emit_pattern_after_noloc (x, after, NULL, make_jump_insn_raw));
4727 /* Make an instruction with body X and code CALL_INSN
4728 and output it after the instruction AFTER. */
4730 rtx_insn *
4731 emit_call_insn_after_noloc (rtx x, rtx_insn *after)
4733 return emit_pattern_after_noloc (x, after, NULL, make_call_insn_raw);
4736 /* Make an instruction with body X and code CALL_INSN
4737 and output it after the instruction AFTER. */
4739 rtx_insn *
4740 emit_debug_insn_after_noloc (rtx x, rtx_insn *after)
4742 return emit_pattern_after_noloc (x, after, NULL, make_debug_insn_raw);
4745 /* Make an insn of code BARRIER
4746 and output it after the insn AFTER. */
4748 rtx_barrier *
4749 emit_barrier_after (rtx_insn *after)
4751 rtx_barrier *insn = as_a <rtx_barrier *> (rtx_alloc (BARRIER));
4753 INSN_UID (insn) = cur_insn_uid++;
4755 add_insn_after (insn, after, NULL);
4756 return insn;
4759 /* Emit the label LABEL after the insn AFTER. */
4761 rtx_insn *
4762 emit_label_after (rtx_insn *label, rtx_insn *after)
4764 gcc_checking_assert (INSN_UID (label) == 0);
4765 INSN_UID (label) = cur_insn_uid++;
4766 add_insn_after (label, after, NULL);
4767 return label;
4770 /* Notes require a bit of special handling: Some notes need to have their
4771 BLOCK_FOR_INSN set, others should never have it set, and some should
4772 have it set or clear depending on the context. */
4774 /* Return true iff a note of kind SUBTYPE should be emitted with routines
4775 that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the
4776 caller is asked to emit a note before BB_HEAD, or after BB_END. */
4778 static bool
4779 note_outside_basic_block_p (enum insn_note subtype, bool on_bb_boundary_p)
4781 switch (subtype)
4783 /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */
4784 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
4785 return true;
4787 /* Notes for var tracking and EH region markers can appear between or
4788 inside basic blocks. If the caller is emitting on the basic block
4789 boundary, do not set BLOCK_FOR_INSN on the new note. */
4790 case NOTE_INSN_VAR_LOCATION:
4791 case NOTE_INSN_EH_REGION_BEG:
4792 case NOTE_INSN_EH_REGION_END:
4793 return on_bb_boundary_p;
4795 /* Otherwise, BLOCK_FOR_INSN must be set. */
4796 default:
4797 return false;
4801 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4803 rtx_note *
4804 emit_note_after (enum insn_note subtype, rtx_insn *after)
4806 rtx_note *note = make_note_raw (subtype);
4807 basic_block bb = BARRIER_P (after) ? NULL : BLOCK_FOR_INSN (after);
4808 bool on_bb_boundary_p = (bb != NULL && BB_END (bb) == after);
4810 if (note_outside_basic_block_p (subtype, on_bb_boundary_p))
4811 add_insn_after_nobb (note, after);
4812 else
4813 add_insn_after (note, after, bb);
4814 return note;
4817 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
4819 rtx_note *
4820 emit_note_before (enum insn_note subtype, rtx_insn *before)
4822 rtx_note *note = make_note_raw (subtype);
4823 basic_block bb = BARRIER_P (before) ? NULL : BLOCK_FOR_INSN (before);
4824 bool on_bb_boundary_p = (bb != NULL && BB_HEAD (bb) == before);
4826 if (note_outside_basic_block_p (subtype, on_bb_boundary_p))
4827 add_insn_before_nobb (note, before);
4828 else
4829 add_insn_before (note, before, bb);
4830 return note;
4833 /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC.
4834 MAKE_RAW indicates how to turn PATTERN into a real insn. */
4836 static rtx_insn *
4837 emit_pattern_after_setloc (rtx pattern, rtx_insn *after, location_t loc,
4838 rtx_insn *(*make_raw) (rtx))
4840 rtx_insn *last = emit_pattern_after_noloc (pattern, after, NULL, make_raw);
4842 if (pattern == NULL_RTX || !loc)
4843 return last;
4845 after = NEXT_INSN (after);
4846 while (1)
4848 if (active_insn_p (after)
4849 && !JUMP_TABLE_DATA_P (after) /* FIXME */
4850 && !INSN_LOCATION (after))
4851 INSN_LOCATION (after) = loc;
4852 if (after == last)
4853 break;
4854 after = NEXT_INSN (after);
4856 return last;
4859 /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN
4860 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after
4861 any DEBUG_INSNs. */
4863 static rtx_insn *
4864 emit_pattern_after (rtx pattern, rtx_insn *after, bool skip_debug_insns,
4865 rtx_insn *(*make_raw) (rtx))
4867 rtx_insn *prev = after;
4869 if (skip_debug_insns)
4870 while (DEBUG_INSN_P (prev))
4871 prev = PREV_INSN (prev);
4873 if (INSN_P (prev))
4874 return emit_pattern_after_setloc (pattern, after, INSN_LOCATION (prev),
4875 make_raw);
4876 else
4877 return emit_pattern_after_noloc (pattern, after, NULL, make_raw);
4880 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4881 rtx_insn *
4882 emit_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc)
4884 return emit_pattern_after_setloc (pattern, after, loc, make_insn_raw);
4887 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4888 rtx_insn *
4889 emit_insn_after (rtx pattern, rtx_insn *after)
4891 return emit_pattern_after (pattern, after, true, make_insn_raw);
4894 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4895 rtx_jump_insn *
4896 emit_jump_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc)
4898 return as_a <rtx_jump_insn *> (
4899 emit_pattern_after_setloc (pattern, after, loc, make_jump_insn_raw));
4902 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4903 rtx_jump_insn *
4904 emit_jump_insn_after (rtx pattern, rtx_insn *after)
4906 return as_a <rtx_jump_insn *> (
4907 emit_pattern_after (pattern, after, true, make_jump_insn_raw));
4910 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4911 rtx_insn *
4912 emit_call_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc)
4914 return emit_pattern_after_setloc (pattern, after, loc, make_call_insn_raw);
4917 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4918 rtx_insn *
4919 emit_call_insn_after (rtx pattern, rtx_insn *after)
4921 return emit_pattern_after (pattern, after, true, make_call_insn_raw);
4924 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4925 rtx_insn *
4926 emit_debug_insn_after_setloc (rtx pattern, rtx_insn *after, location_t loc)
4928 return emit_pattern_after_setloc (pattern, after, loc, make_debug_insn_raw);
4931 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4932 rtx_insn *
4933 emit_debug_insn_after (rtx pattern, rtx_insn *after)
4935 return emit_pattern_after (pattern, after, false, make_debug_insn_raw);
4938 /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC.
4939 MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP
4940 indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN,
4941 CALL_INSN, etc. */
4943 static rtx_insn *
4944 emit_pattern_before_setloc (rtx pattern, rtx_insn *before, location_t loc,
4945 bool insnp, rtx_insn *(*make_raw) (rtx))
4947 rtx_insn *first = PREV_INSN (before);
4948 rtx_insn *last = emit_pattern_before_noloc (pattern, before,
4949 insnp ? before : NULL,
4950 NULL, make_raw);
4952 if (pattern == NULL_RTX || !loc)
4953 return last;
4955 if (!first)
4956 first = get_insns ();
4957 else
4958 first = NEXT_INSN (first);
4959 while (1)
4961 if (active_insn_p (first)
4962 && !JUMP_TABLE_DATA_P (first) /* FIXME */
4963 && !INSN_LOCATION (first))
4964 INSN_LOCATION (first) = loc;
4965 if (first == last)
4966 break;
4967 first = NEXT_INSN (first);
4969 return last;
4972 /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN
4973 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert
4974 before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an
4975 INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */
4977 static rtx_insn *
4978 emit_pattern_before (rtx pattern, rtx_insn *before, bool skip_debug_insns,
4979 bool insnp, rtx_insn *(*make_raw) (rtx))
4981 rtx_insn *next = before;
4983 if (skip_debug_insns)
4984 while (DEBUG_INSN_P (next))
4985 next = PREV_INSN (next);
4987 if (INSN_P (next))
4988 return emit_pattern_before_setloc (pattern, before, INSN_LOCATION (next),
4989 insnp, make_raw);
4990 else
4991 return emit_pattern_before_noloc (pattern, before,
4992 insnp ? before : NULL,
4993 NULL, make_raw);
4996 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
4997 rtx_insn *
4998 emit_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc)
5000 return emit_pattern_before_setloc (pattern, before, loc, true,
5001 make_insn_raw);
5004 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5005 rtx_insn *
5006 emit_insn_before (rtx pattern, rtx_insn *before)
5008 return emit_pattern_before (pattern, before, true, true, make_insn_raw);
5011 /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5012 rtx_jump_insn *
5013 emit_jump_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc)
5015 return as_a <rtx_jump_insn *> (
5016 emit_pattern_before_setloc (pattern, before, loc, false,
5017 make_jump_insn_raw));
5020 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5021 rtx_jump_insn *
5022 emit_jump_insn_before (rtx pattern, rtx_insn *before)
5024 return as_a <rtx_jump_insn *> (
5025 emit_pattern_before (pattern, before, true, false,
5026 make_jump_insn_raw));
5029 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5030 rtx_insn *
5031 emit_call_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc)
5033 return emit_pattern_before_setloc (pattern, before, loc, false,
5034 make_call_insn_raw);
5037 /* Like emit_call_insn_before_noloc,
5038 but set insn_location according to BEFORE. */
5039 rtx_insn *
5040 emit_call_insn_before (rtx pattern, rtx_insn *before)
5042 return emit_pattern_before (pattern, before, true, false,
5043 make_call_insn_raw);
5046 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5047 rtx_insn *
5048 emit_debug_insn_before_setloc (rtx pattern, rtx_insn *before, location_t loc)
5050 return emit_pattern_before_setloc (pattern, before, loc, false,
5051 make_debug_insn_raw);
5054 /* Like emit_debug_insn_before_noloc,
5055 but set insn_location according to BEFORE. */
5056 rtx_insn *
5057 emit_debug_insn_before (rtx pattern, rtx_insn *before)
5059 return emit_pattern_before (pattern, before, false, false,
5060 make_debug_insn_raw);
5063 /* Take X and emit it at the end of the doubly-linked
5064 INSN list.
5066 Returns the last insn emitted. */
5068 rtx_insn *
5069 emit_insn (rtx x)
5071 rtx_insn *last = get_last_insn ();
5072 rtx_insn *insn;
5074 if (x == NULL_RTX)
5075 return last;
5077 switch (GET_CODE (x))
5079 case DEBUG_INSN:
5080 case INSN:
5081 case JUMP_INSN:
5082 case CALL_INSN:
5083 case CODE_LABEL:
5084 case BARRIER:
5085 case NOTE:
5086 insn = as_a <rtx_insn *> (x);
5087 while (insn)
5089 rtx_insn *next = NEXT_INSN (insn);
5090 add_insn (insn);
5091 last = insn;
5092 insn = next;
5094 break;
5096 #ifdef ENABLE_RTL_CHECKING
5097 case JUMP_TABLE_DATA:
5098 case SEQUENCE:
5099 gcc_unreachable ();
5100 break;
5101 #endif
5103 default:
5104 last = make_insn_raw (x);
5105 add_insn (last);
5106 break;
5109 return last;
5112 /* Make an insn of code DEBUG_INSN with pattern X
5113 and add it to the end of the doubly-linked list. */
5115 rtx_insn *
5116 emit_debug_insn (rtx x)
5118 rtx_insn *last = get_last_insn ();
5119 rtx_insn *insn;
5121 if (x == NULL_RTX)
5122 return last;
5124 switch (GET_CODE (x))
5126 case DEBUG_INSN:
5127 case INSN:
5128 case JUMP_INSN:
5129 case CALL_INSN:
5130 case CODE_LABEL:
5131 case BARRIER:
5132 case NOTE:
5133 insn = as_a <rtx_insn *> (x);
5134 while (insn)
5136 rtx_insn *next = NEXT_INSN (insn);
5137 add_insn (insn);
5138 last = insn;
5139 insn = next;
5141 break;
5143 #ifdef ENABLE_RTL_CHECKING
5144 case JUMP_TABLE_DATA:
5145 case SEQUENCE:
5146 gcc_unreachable ();
5147 break;
5148 #endif
5150 default:
5151 last = make_debug_insn_raw (x);
5152 add_insn (last);
5153 break;
5156 return last;
5159 /* Make an insn of code JUMP_INSN with pattern X
5160 and add it to the end of the doubly-linked list. */
5162 rtx_insn *
5163 emit_jump_insn (rtx x)
5165 rtx_insn *last = NULL;
5166 rtx_insn *insn;
5168 switch (GET_CODE (x))
5170 case DEBUG_INSN:
5171 case INSN:
5172 case JUMP_INSN:
5173 case CALL_INSN:
5174 case CODE_LABEL:
5175 case BARRIER:
5176 case NOTE:
5177 insn = as_a <rtx_insn *> (x);
5178 while (insn)
5180 rtx_insn *next = NEXT_INSN (insn);
5181 add_insn (insn);
5182 last = insn;
5183 insn = next;
5185 break;
5187 #ifdef ENABLE_RTL_CHECKING
5188 case JUMP_TABLE_DATA:
5189 case SEQUENCE:
5190 gcc_unreachable ();
5191 break;
5192 #endif
5194 default:
5195 last = make_jump_insn_raw (x);
5196 add_insn (last);
5197 break;
5200 return last;
5203 /* Make an insn of code CALL_INSN with pattern X
5204 and add it to the end of the doubly-linked list. */
5206 rtx_insn *
5207 emit_call_insn (rtx x)
5209 rtx_insn *insn;
5211 switch (GET_CODE (x))
5213 case DEBUG_INSN:
5214 case INSN:
5215 case JUMP_INSN:
5216 case CALL_INSN:
5217 case CODE_LABEL:
5218 case BARRIER:
5219 case NOTE:
5220 insn = emit_insn (x);
5221 break;
5223 #ifdef ENABLE_RTL_CHECKING
5224 case SEQUENCE:
5225 case JUMP_TABLE_DATA:
5226 gcc_unreachable ();
5227 break;
5228 #endif
5230 default:
5231 insn = make_call_insn_raw (x);
5232 add_insn (insn);
5233 break;
5236 return insn;
5239 /* Add the label LABEL to the end of the doubly-linked list. */
5241 rtx_code_label *
5242 emit_label (rtx uncast_label)
5244 rtx_code_label *label = as_a <rtx_code_label *> (uncast_label);
5246 gcc_checking_assert (INSN_UID (label) == 0);
5247 INSN_UID (label) = cur_insn_uid++;
5248 add_insn (label);
5249 return label;
5252 /* Make an insn of code JUMP_TABLE_DATA
5253 and add it to the end of the doubly-linked list. */
5255 rtx_jump_table_data *
5256 emit_jump_table_data (rtx table)
5258 rtx_jump_table_data *jump_table_data =
5259 as_a <rtx_jump_table_data *> (rtx_alloc (JUMP_TABLE_DATA));
5260 INSN_UID (jump_table_data) = cur_insn_uid++;
5261 PATTERN (jump_table_data) = table;
5262 BLOCK_FOR_INSN (jump_table_data) = NULL;
5263 add_insn (jump_table_data);
5264 return jump_table_data;
5267 /* Make an insn of code BARRIER
5268 and add it to the end of the doubly-linked list. */
5270 rtx_barrier *
5271 emit_barrier (void)
5273 rtx_barrier *barrier = as_a <rtx_barrier *> (rtx_alloc (BARRIER));
5274 INSN_UID (barrier) = cur_insn_uid++;
5275 add_insn (barrier);
5276 return barrier;
5279 /* Emit a copy of note ORIG. */
5281 rtx_note *
5282 emit_note_copy (rtx_note *orig)
5284 enum insn_note kind = (enum insn_note) NOTE_KIND (orig);
5285 rtx_note *note = make_note_raw (kind);
5286 NOTE_DATA (note) = NOTE_DATA (orig);
5287 add_insn (note);
5288 return note;
5291 /* Make an insn of code NOTE or type NOTE_NO
5292 and add it to the end of the doubly-linked list. */
5294 rtx_note *
5295 emit_note (enum insn_note kind)
5297 rtx_note *note = make_note_raw (kind);
5298 add_insn (note);
5299 return note;
5302 /* Emit a clobber of lvalue X. */
5304 rtx_insn *
5305 emit_clobber (rtx x)
5307 /* CONCATs should not appear in the insn stream. */
5308 if (GET_CODE (x) == CONCAT)
5310 emit_clobber (XEXP (x, 0));
5311 return emit_clobber (XEXP (x, 1));
5313 return emit_insn (gen_rtx_CLOBBER (VOIDmode, x));
5316 /* Return a sequence of insns to clobber lvalue X. */
5318 rtx_insn *
5319 gen_clobber (rtx x)
5321 rtx_insn *seq;
5323 start_sequence ();
5324 emit_clobber (x);
5325 seq = get_insns ();
5326 end_sequence ();
5327 return seq;
5330 /* Emit a use of rvalue X. */
5332 rtx_insn *
5333 emit_use (rtx x)
5335 /* CONCATs should not appear in the insn stream. */
5336 if (GET_CODE (x) == CONCAT)
5338 emit_use (XEXP (x, 0));
5339 return emit_use (XEXP (x, 1));
5341 return emit_insn (gen_rtx_USE (VOIDmode, x));
5344 /* Return a sequence of insns to use rvalue X. */
5346 rtx_insn *
5347 gen_use (rtx x)
5349 rtx_insn *seq;
5351 start_sequence ();
5352 emit_use (x);
5353 seq = get_insns ();
5354 end_sequence ();
5355 return seq;
5358 /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction.
5359 Return the set in INSN that such notes describe, or NULL if the notes
5360 have no meaning for INSN. */
5363 set_for_reg_notes (rtx insn)
5365 rtx pat, reg;
5367 if (!INSN_P (insn))
5368 return NULL_RTX;
5370 pat = PATTERN (insn);
5371 if (GET_CODE (pat) == PARALLEL)
5373 /* We do not use single_set because that ignores SETs of unused
5374 registers. REG_EQUAL and REG_EQUIV notes really do require the
5375 PARALLEL to have a single SET. */
5376 if (multiple_sets (insn))
5377 return NULL_RTX;
5378 pat = XVECEXP (pat, 0, 0);
5381 if (GET_CODE (pat) != SET)
5382 return NULL_RTX;
5384 reg = SET_DEST (pat);
5386 /* Notes apply to the contents of a STRICT_LOW_PART. */
5387 if (GET_CODE (reg) == STRICT_LOW_PART
5388 || GET_CODE (reg) == ZERO_EXTRACT)
5389 reg = XEXP (reg, 0);
5391 /* Check that we have a register. */
5392 if (!(REG_P (reg) || GET_CODE (reg) == SUBREG))
5393 return NULL_RTX;
5395 return pat;
5398 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
5399 note of this type already exists, remove it first. */
5402 set_unique_reg_note (rtx insn, enum reg_note kind, rtx datum)
5404 rtx note = find_reg_note (insn, kind, NULL_RTX);
5406 switch (kind)
5408 case REG_EQUAL:
5409 case REG_EQUIV:
5410 /* We need to support the REG_EQUAL on USE trick of find_reloads. */
5411 if (!set_for_reg_notes (insn) && GET_CODE (PATTERN (insn)) != USE)
5412 return NULL_RTX;
5414 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
5415 It serves no useful purpose and breaks eliminate_regs. */
5416 if (GET_CODE (datum) == ASM_OPERANDS)
5417 return NULL_RTX;
5419 /* Notes with side effects are dangerous. Even if the side-effect
5420 initially mirrors one in PATTERN (INSN), later optimizations
5421 might alter the way that the final register value is calculated
5422 and so move or alter the side-effect in some way. The note would
5423 then no longer be a valid substitution for SET_SRC. */
5424 if (side_effects_p (datum))
5425 return NULL_RTX;
5426 break;
5428 default:
5429 break;
5432 if (note)
5433 XEXP (note, 0) = datum;
5434 else
5436 add_reg_note (insn, kind, datum);
5437 note = REG_NOTES (insn);
5440 switch (kind)
5442 case REG_EQUAL:
5443 case REG_EQUIV:
5444 df_notes_rescan (as_a <rtx_insn *> (insn));
5445 break;
5446 default:
5447 break;
5450 return note;
5453 /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */
5455 set_dst_reg_note (rtx insn, enum reg_note kind, rtx datum, rtx dst)
5457 rtx set = set_for_reg_notes (insn);
5459 if (set && SET_DEST (set) == dst)
5460 return set_unique_reg_note (insn, kind, datum);
5461 return NULL_RTX;
5464 /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a
5465 following barrier if the instruction needs one and if ALLOW_BARRIER_P
5466 is true.
5468 If X is a label, it is simply added into the insn chain. */
5470 rtx_insn *
5471 emit (rtx x, bool allow_barrier_p)
5473 enum rtx_code code = classify_insn (x);
5475 switch (code)
5477 case CODE_LABEL:
5478 return emit_label (x);
5479 case INSN:
5480 return emit_insn (x);
5481 case JUMP_INSN:
5483 rtx_insn *insn = emit_jump_insn (x);
5484 if (allow_barrier_p
5485 && (any_uncondjump_p (insn) || GET_CODE (x) == RETURN))
5486 return emit_barrier ();
5487 return insn;
5489 case CALL_INSN:
5490 return emit_call_insn (x);
5491 case DEBUG_INSN:
5492 return emit_debug_insn (x);
5493 default:
5494 gcc_unreachable ();
5498 /* Space for free sequence stack entries. */
5499 static GTY ((deletable)) struct sequence_stack *free_sequence_stack;
5501 /* Begin emitting insns to a sequence. If this sequence will contain
5502 something that might cause the compiler to pop arguments to function
5503 calls (because those pops have previously been deferred; see
5504 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
5505 before calling this function. That will ensure that the deferred
5506 pops are not accidentally emitted in the middle of this sequence. */
5508 void
5509 start_sequence (void)
5511 struct sequence_stack *tem;
5513 if (free_sequence_stack != NULL)
5515 tem = free_sequence_stack;
5516 free_sequence_stack = tem->next;
5518 else
5519 tem = ggc_alloc<sequence_stack> ();
5521 tem->next = get_current_sequence ()->next;
5522 tem->first = get_insns ();
5523 tem->last = get_last_insn ();
5524 get_current_sequence ()->next = tem;
5526 set_first_insn (0);
5527 set_last_insn (0);
5530 /* Set up the insn chain starting with FIRST as the current sequence,
5531 saving the previously current one. See the documentation for
5532 start_sequence for more information about how to use this function. */
5534 void
5535 push_to_sequence (rtx_insn *first)
5537 rtx_insn *last;
5539 start_sequence ();
5541 for (last = first; last && NEXT_INSN (last); last = NEXT_INSN (last))
5544 set_first_insn (first);
5545 set_last_insn (last);
5548 /* Like push_to_sequence, but take the last insn as an argument to avoid
5549 looping through the list. */
5551 void
5552 push_to_sequence2 (rtx_insn *first, rtx_insn *last)
5554 start_sequence ();
5556 set_first_insn (first);
5557 set_last_insn (last);
5560 /* Set up the outer-level insn chain
5561 as the current sequence, saving the previously current one. */
5563 void
5564 push_topmost_sequence (void)
5566 struct sequence_stack *top;
5568 start_sequence ();
5570 top = get_topmost_sequence ();
5571 set_first_insn (top->first);
5572 set_last_insn (top->last);
5575 /* After emitting to the outer-level insn chain, update the outer-level
5576 insn chain, and restore the previous saved state. */
5578 void
5579 pop_topmost_sequence (void)
5581 struct sequence_stack *top;
5583 top = get_topmost_sequence ();
5584 top->first = get_insns ();
5585 top->last = get_last_insn ();
5587 end_sequence ();
5590 /* After emitting to a sequence, restore previous saved state.
5592 To get the contents of the sequence just made, you must call
5593 `get_insns' *before* calling here.
5595 If the compiler might have deferred popping arguments while
5596 generating this sequence, and this sequence will not be immediately
5597 inserted into the instruction stream, use do_pending_stack_adjust
5598 before calling get_insns. That will ensure that the deferred
5599 pops are inserted into this sequence, and not into some random
5600 location in the instruction stream. See INHIBIT_DEFER_POP for more
5601 information about deferred popping of arguments. */
5603 void
5604 end_sequence (void)
5606 struct sequence_stack *tem = get_current_sequence ()->next;
5608 set_first_insn (tem->first);
5609 set_last_insn (tem->last);
5610 get_current_sequence ()->next = tem->next;
5612 memset (tem, 0, sizeof (*tem));
5613 tem->next = free_sequence_stack;
5614 free_sequence_stack = tem;
5617 /* Return 1 if currently emitting into a sequence. */
5620 in_sequence_p (void)
5622 return get_current_sequence ()->next != 0;
5625 /* Put the various virtual registers into REGNO_REG_RTX. */
5627 static void
5628 init_virtual_regs (void)
5630 regno_reg_rtx[VIRTUAL_INCOMING_ARGS_REGNUM] = virtual_incoming_args_rtx;
5631 regno_reg_rtx[VIRTUAL_STACK_VARS_REGNUM] = virtual_stack_vars_rtx;
5632 regno_reg_rtx[VIRTUAL_STACK_DYNAMIC_REGNUM] = virtual_stack_dynamic_rtx;
5633 regno_reg_rtx[VIRTUAL_OUTGOING_ARGS_REGNUM] = virtual_outgoing_args_rtx;
5634 regno_reg_rtx[VIRTUAL_CFA_REGNUM] = virtual_cfa_rtx;
5635 regno_reg_rtx[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM]
5636 = virtual_preferred_stack_boundary_rtx;
5640 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
5641 static rtx copy_insn_scratch_in[MAX_RECOG_OPERANDS];
5642 static rtx copy_insn_scratch_out[MAX_RECOG_OPERANDS];
5643 static int copy_insn_n_scratches;
5645 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5646 copied an ASM_OPERANDS.
5647 In that case, it is the original input-operand vector. */
5648 static rtvec orig_asm_operands_vector;
5650 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5651 copied an ASM_OPERANDS.
5652 In that case, it is the copied input-operand vector. */
5653 static rtvec copy_asm_operands_vector;
5655 /* Likewise for the constraints vector. */
5656 static rtvec orig_asm_constraints_vector;
5657 static rtvec copy_asm_constraints_vector;
5659 /* Recursively create a new copy of an rtx for copy_insn.
5660 This function differs from copy_rtx in that it handles SCRATCHes and
5661 ASM_OPERANDs properly.
5662 Normally, this function is not used directly; use copy_insn as front end.
5663 However, you could first copy an insn pattern with copy_insn and then use
5664 this function afterwards to properly copy any REG_NOTEs containing
5665 SCRATCHes. */
5668 copy_insn_1 (rtx orig)
5670 rtx copy;
5671 int i, j;
5672 RTX_CODE code;
5673 const char *format_ptr;
5675 if (orig == NULL)
5676 return NULL;
5678 code = GET_CODE (orig);
5680 switch (code)
5682 case REG:
5683 case DEBUG_EXPR:
5684 CASE_CONST_ANY:
5685 case SYMBOL_REF:
5686 case CODE_LABEL:
5687 case PC:
5688 case CC0:
5689 case RETURN:
5690 case SIMPLE_RETURN:
5691 return orig;
5692 case CLOBBER:
5693 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
5694 clobbers or clobbers of hard registers that originated as pseudos.
5695 This is needed to allow safe register renaming. */
5696 if (REG_P (XEXP (orig, 0))
5697 && HARD_REGISTER_NUM_P (REGNO (XEXP (orig, 0)))
5698 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig, 0))))
5699 return orig;
5700 break;
5702 case SCRATCH:
5703 for (i = 0; i < copy_insn_n_scratches; i++)
5704 if (copy_insn_scratch_in[i] == orig)
5705 return copy_insn_scratch_out[i];
5706 break;
5708 case CONST:
5709 if (shared_const_p (orig))
5710 return orig;
5711 break;
5713 /* A MEM with a constant address is not sharable. The problem is that
5714 the constant address may need to be reloaded. If the mem is shared,
5715 then reloading one copy of this mem will cause all copies to appear
5716 to have been reloaded. */
5718 default:
5719 break;
5722 /* Copy the various flags, fields, and other information. We assume
5723 that all fields need copying, and then clear the fields that should
5724 not be copied. That is the sensible default behavior, and forces
5725 us to explicitly document why we are *not* copying a flag. */
5726 copy = shallow_copy_rtx (orig);
5728 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
5729 if (INSN_P (orig))
5731 RTX_FLAG (copy, jump) = 0;
5732 RTX_FLAG (copy, call) = 0;
5733 RTX_FLAG (copy, frame_related) = 0;
5736 format_ptr = GET_RTX_FORMAT (GET_CODE (copy));
5738 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (copy)); i++)
5739 switch (*format_ptr++)
5741 case 'e':
5742 if (XEXP (orig, i) != NULL)
5743 XEXP (copy, i) = copy_insn_1 (XEXP (orig, i));
5744 break;
5746 case 'E':
5747 case 'V':
5748 if (XVEC (orig, i) == orig_asm_constraints_vector)
5749 XVEC (copy, i) = copy_asm_constraints_vector;
5750 else if (XVEC (orig, i) == orig_asm_operands_vector)
5751 XVEC (copy, i) = copy_asm_operands_vector;
5752 else if (XVEC (orig, i) != NULL)
5754 XVEC (copy, i) = rtvec_alloc (XVECLEN (orig, i));
5755 for (j = 0; j < XVECLEN (copy, i); j++)
5756 XVECEXP (copy, i, j) = copy_insn_1 (XVECEXP (orig, i, j));
5758 break;
5760 case 't':
5761 case 'w':
5762 case 'i':
5763 case 'p':
5764 case 's':
5765 case 'S':
5766 case 'u':
5767 case '0':
5768 /* These are left unchanged. */
5769 break;
5771 default:
5772 gcc_unreachable ();
5775 if (code == SCRATCH)
5777 i = copy_insn_n_scratches++;
5778 gcc_assert (i < MAX_RECOG_OPERANDS);
5779 copy_insn_scratch_in[i] = orig;
5780 copy_insn_scratch_out[i] = copy;
5782 else if (code == ASM_OPERANDS)
5784 orig_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (orig);
5785 copy_asm_operands_vector = ASM_OPERANDS_INPUT_VEC (copy);
5786 orig_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig);
5787 copy_asm_constraints_vector = ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy);
5790 return copy;
5793 /* Create a new copy of an rtx.
5794 This function differs from copy_rtx in that it handles SCRATCHes and
5795 ASM_OPERANDs properly.
5796 INSN doesn't really have to be a full INSN; it could be just the
5797 pattern. */
5799 copy_insn (rtx insn)
5801 copy_insn_n_scratches = 0;
5802 orig_asm_operands_vector = 0;
5803 orig_asm_constraints_vector = 0;
5804 copy_asm_operands_vector = 0;
5805 copy_asm_constraints_vector = 0;
5806 return copy_insn_1 (insn);
5809 /* Return a copy of INSN that can be used in a SEQUENCE delay slot,
5810 on that assumption that INSN itself remains in its original place. */
5812 rtx_insn *
5813 copy_delay_slot_insn (rtx_insn *insn)
5815 /* Copy INSN with its rtx_code, all its notes, location etc. */
5816 insn = as_a <rtx_insn *> (copy_rtx (insn));
5817 INSN_UID (insn) = cur_insn_uid++;
5818 return insn;
5821 /* Initialize data structures and variables in this file
5822 before generating rtl for each function. */
5824 void
5825 init_emit (void)
5827 set_first_insn (NULL);
5828 set_last_insn (NULL);
5829 if (MIN_NONDEBUG_INSN_UID)
5830 cur_insn_uid = MIN_NONDEBUG_INSN_UID;
5831 else
5832 cur_insn_uid = 1;
5833 cur_debug_insn_uid = 1;
5834 reg_rtx_no = LAST_VIRTUAL_REGISTER + 1;
5835 first_label_num = label_num;
5836 get_current_sequence ()->next = NULL;
5838 /* Init the tables that describe all the pseudo regs. */
5840 crtl->emit.regno_pointer_align_length = LAST_VIRTUAL_REGISTER + 101;
5842 crtl->emit.regno_pointer_align
5843 = XCNEWVEC (unsigned char, crtl->emit.regno_pointer_align_length);
5845 regno_reg_rtx
5846 = ggc_cleared_vec_alloc<rtx> (crtl->emit.regno_pointer_align_length);
5848 /* Put copies of all the hard registers into regno_reg_rtx. */
5849 memcpy (regno_reg_rtx,
5850 initial_regno_reg_rtx,
5851 FIRST_PSEUDO_REGISTER * sizeof (rtx));
5853 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
5854 init_virtual_regs ();
5856 /* Indicate that the virtual registers and stack locations are
5857 all pointers. */
5858 REG_POINTER (stack_pointer_rtx) = 1;
5859 REG_POINTER (frame_pointer_rtx) = 1;
5860 REG_POINTER (hard_frame_pointer_rtx) = 1;
5861 REG_POINTER (arg_pointer_rtx) = 1;
5863 REG_POINTER (virtual_incoming_args_rtx) = 1;
5864 REG_POINTER (virtual_stack_vars_rtx) = 1;
5865 REG_POINTER (virtual_stack_dynamic_rtx) = 1;
5866 REG_POINTER (virtual_outgoing_args_rtx) = 1;
5867 REG_POINTER (virtual_cfa_rtx) = 1;
5869 #ifdef STACK_BOUNDARY
5870 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = STACK_BOUNDARY;
5871 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
5872 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = STACK_BOUNDARY;
5873 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = STACK_BOUNDARY;
5875 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) = STACK_BOUNDARY;
5876 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM) = STACK_BOUNDARY;
5877 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) = STACK_BOUNDARY;
5878 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) = STACK_BOUNDARY;
5880 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM) = BITS_PER_WORD;
5881 #endif
5883 #ifdef INIT_EXPANDERS
5884 INIT_EXPANDERS;
5885 #endif
5888 /* Return the value of element I of CONST_VECTOR X as a wide_int. */
5890 wide_int
5891 const_vector_int_elt (const_rtx x, unsigned int i)
5893 /* First handle elements that are directly encoded. */
5894 machine_mode elt_mode = GET_MODE_INNER (GET_MODE (x));
5895 if (i < (unsigned int) XVECLEN (x, 0))
5896 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, i), elt_mode);
5898 /* Identify the pattern that contains element I and work out the index of
5899 the last encoded element for that pattern. */
5900 unsigned int encoded_nelts = const_vector_encoded_nelts (x);
5901 unsigned int npatterns = CONST_VECTOR_NPATTERNS (x);
5902 unsigned int count = i / npatterns;
5903 unsigned int pattern = i % npatterns;
5904 unsigned int final_i = encoded_nelts - npatterns + pattern;
5906 /* If there are no steps, the final encoded value is the right one. */
5907 if (!CONST_VECTOR_STEPPED_P (x))
5908 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x, final_i), elt_mode);
5910 /* Otherwise work out the value from the last two encoded elements. */
5911 rtx v1 = CONST_VECTOR_ENCODED_ELT (x, final_i - npatterns);
5912 rtx v2 = CONST_VECTOR_ENCODED_ELT (x, final_i);
5913 wide_int diff = wi::sub (rtx_mode_t (v2, elt_mode),
5914 rtx_mode_t (v1, elt_mode));
5915 return wi::add (rtx_mode_t (v2, elt_mode), (count - 2) * diff);
5918 /* Return the value of element I of CONST_VECTOR X. */
5921 const_vector_elt (const_rtx x, unsigned int i)
5923 /* First handle elements that are directly encoded. */
5924 if (i < (unsigned int) XVECLEN (x, 0))
5925 return CONST_VECTOR_ENCODED_ELT (x, i);
5927 /* If there are no steps, the final encoded value is the right one. */
5928 if (!CONST_VECTOR_STEPPED_P (x))
5930 /* Identify the pattern that contains element I and work out the index of
5931 the last encoded element for that pattern. */
5932 unsigned int encoded_nelts = const_vector_encoded_nelts (x);
5933 unsigned int npatterns = CONST_VECTOR_NPATTERNS (x);
5934 unsigned int pattern = i % npatterns;
5935 unsigned int final_i = encoded_nelts - npatterns + pattern;
5936 return CONST_VECTOR_ENCODED_ELT (x, final_i);
5939 /* Otherwise work out the value from the last two encoded elements. */
5940 return immed_wide_int_const (const_vector_int_elt (x, i),
5941 GET_MODE_INNER (GET_MODE (x)));
5944 /* Return true if X is a valid element for a CONST_VECTOR of the given
5945 mode. */
5947 bool
5948 valid_for_const_vector_p (machine_mode, rtx x)
5950 return (CONST_SCALAR_INT_P (x)
5951 || CONST_DOUBLE_AS_FLOAT_P (x)
5952 || CONST_FIXED_P (x));
5955 /* Generate a vector constant of mode MODE in which every element has
5956 value ELT. */
5959 gen_const_vec_duplicate (machine_mode mode, rtx elt)
5961 rtx_vector_builder builder (mode, 1, 1);
5962 builder.quick_push (elt);
5963 return builder.build ();
5966 /* Return a vector rtx of mode MODE in which every element has value X.
5967 The result will be a constant if X is constant. */
5970 gen_vec_duplicate (machine_mode mode, rtx x)
5972 if (valid_for_const_vector_p (mode, x))
5973 return gen_const_vec_duplicate (mode, x);
5974 return gen_rtx_VEC_DUPLICATE (mode, x);
5977 /* A subroutine of const_vec_series_p that handles the case in which:
5979 (GET_CODE (X) == CONST_VECTOR
5980 && CONST_VECTOR_NPATTERNS (X) == 1
5981 && !CONST_VECTOR_DUPLICATE_P (X))
5983 is known to hold. */
5985 bool
5986 const_vec_series_p_1 (const_rtx x, rtx *base_out, rtx *step_out)
5988 /* Stepped sequences are only defined for integers, to avoid specifying
5989 rounding behavior. */
5990 if (GET_MODE_CLASS (GET_MODE (x)) != MODE_VECTOR_INT)
5991 return false;
5993 /* A non-duplicated vector with two elements can always be seen as a
5994 series with a nonzero step. Longer vectors must have a stepped
5995 encoding. */
5996 if (maybe_ne (CONST_VECTOR_NUNITS (x), 2)
5997 && !CONST_VECTOR_STEPPED_P (x))
5998 return false;
6000 /* Calculate the step between the first and second elements. */
6001 scalar_mode inner = GET_MODE_INNER (GET_MODE (x));
6002 rtx base = CONST_VECTOR_ELT (x, 0);
6003 rtx step = simplify_binary_operation (MINUS, inner,
6004 CONST_VECTOR_ENCODED_ELT (x, 1), base);
6005 if (rtx_equal_p (step, CONST0_RTX (inner)))
6006 return false;
6008 /* If we have a stepped encoding, check that the step between the
6009 second and third elements is the same as STEP. */
6010 if (CONST_VECTOR_STEPPED_P (x))
6012 rtx diff = simplify_binary_operation (MINUS, inner,
6013 CONST_VECTOR_ENCODED_ELT (x, 2),
6014 CONST_VECTOR_ENCODED_ELT (x, 1));
6015 if (!rtx_equal_p (step, diff))
6016 return false;
6019 *base_out = base;
6020 *step_out = step;
6021 return true;
6024 /* Generate a vector constant of mode MODE in which element I has
6025 the value BASE + I * STEP. */
6028 gen_const_vec_series (machine_mode mode, rtx base, rtx step)
6030 gcc_assert (valid_for_const_vector_p (mode, base)
6031 && valid_for_const_vector_p (mode, step));
6033 rtx_vector_builder builder (mode, 1, 3);
6034 builder.quick_push (base);
6035 for (int i = 1; i < 3; ++i)
6036 builder.quick_push (simplify_gen_binary (PLUS, GET_MODE_INNER (mode),
6037 builder[i - 1], step));
6038 return builder.build ();
6041 /* Generate a vector of mode MODE in which element I has the value
6042 BASE + I * STEP. The result will be a constant if BASE and STEP
6043 are both constants. */
6046 gen_vec_series (machine_mode mode, rtx base, rtx step)
6048 if (step == const0_rtx)
6049 return gen_vec_duplicate (mode, base);
6050 if (valid_for_const_vector_p (mode, base)
6051 && valid_for_const_vector_p (mode, step))
6052 return gen_const_vec_series (mode, base, step);
6053 return gen_rtx_VEC_SERIES (mode, base, step);
6056 /* Generate a new vector constant for mode MODE and constant value
6057 CONSTANT. */
6059 static rtx
6060 gen_const_vector (machine_mode mode, int constant)
6062 machine_mode inner = GET_MODE_INNER (mode);
6064 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner));
6066 rtx el = const_tiny_rtx[constant][(int) inner];
6067 gcc_assert (el);
6069 return gen_const_vec_duplicate (mode, el);
6072 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
6073 all elements are zero, and the one vector when all elements are one. */
6075 gen_rtx_CONST_VECTOR (machine_mode mode, rtvec v)
6077 gcc_assert (known_eq (GET_MODE_NUNITS (mode), GET_NUM_ELEM (v)));
6079 /* If the values are all the same, check to see if we can use one of the
6080 standard constant vectors. */
6081 if (rtvec_all_equal_p (v))
6082 return gen_const_vec_duplicate (mode, RTVEC_ELT (v, 0));
6084 unsigned int nunits = GET_NUM_ELEM (v);
6085 rtx_vector_builder builder (mode, nunits, 1);
6086 for (unsigned int i = 0; i < nunits; ++i)
6087 builder.quick_push (RTVEC_ELT (v, i));
6088 return builder.build (v);
6091 /* Initialise global register information required by all functions. */
6093 void
6094 init_emit_regs (void)
6096 int i;
6097 machine_mode mode;
6098 mem_attrs *attrs;
6100 /* Reset register attributes */
6101 reg_attrs_htab->empty ();
6103 /* We need reg_raw_mode, so initialize the modes now. */
6104 init_reg_modes_target ();
6106 /* Assign register numbers to the globally defined register rtx. */
6107 stack_pointer_rtx = gen_raw_REG (Pmode, STACK_POINTER_REGNUM);
6108 frame_pointer_rtx = gen_raw_REG (Pmode, FRAME_POINTER_REGNUM);
6109 hard_frame_pointer_rtx = gen_raw_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
6110 arg_pointer_rtx = gen_raw_REG (Pmode, ARG_POINTER_REGNUM);
6111 virtual_incoming_args_rtx =
6112 gen_raw_REG (Pmode, VIRTUAL_INCOMING_ARGS_REGNUM);
6113 virtual_stack_vars_rtx =
6114 gen_raw_REG (Pmode, VIRTUAL_STACK_VARS_REGNUM);
6115 virtual_stack_dynamic_rtx =
6116 gen_raw_REG (Pmode, VIRTUAL_STACK_DYNAMIC_REGNUM);
6117 virtual_outgoing_args_rtx =
6118 gen_raw_REG (Pmode, VIRTUAL_OUTGOING_ARGS_REGNUM);
6119 virtual_cfa_rtx = gen_raw_REG (Pmode, VIRTUAL_CFA_REGNUM);
6120 virtual_preferred_stack_boundary_rtx =
6121 gen_raw_REG (Pmode, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM);
6123 /* Initialize RTL for commonly used hard registers. These are
6124 copied into regno_reg_rtx as we begin to compile each function. */
6125 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6126 initial_regno_reg_rtx[i] = gen_raw_REG (reg_raw_mode[i], i);
6128 #ifdef RETURN_ADDRESS_POINTER_REGNUM
6129 return_address_pointer_rtx
6130 = gen_raw_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM);
6131 #endif
6133 pic_offset_table_rtx = NULL_RTX;
6134 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6135 pic_offset_table_rtx = gen_raw_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
6137 for (i = 0; i < (int) MAX_MACHINE_MODE; i++)
6139 mode = (machine_mode) i;
6140 attrs = ggc_cleared_alloc<mem_attrs> ();
6141 attrs->align = BITS_PER_UNIT;
6142 attrs->addrspace = ADDR_SPACE_GENERIC;
6143 if (mode != BLKmode && mode != VOIDmode)
6145 attrs->size_known_p = true;
6146 attrs->size = GET_MODE_SIZE (mode);
6147 if (STRICT_ALIGNMENT)
6148 attrs->align = GET_MODE_ALIGNMENT (mode);
6150 mode_mem_attrs[i] = attrs;
6153 split_branch_probability = profile_probability::uninitialized ();
6156 /* Initialize global machine_mode variables. */
6158 void
6159 init_derived_machine_modes (void)
6161 opt_scalar_int_mode mode_iter, opt_byte_mode, opt_word_mode;
6162 FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
6164 scalar_int_mode mode = mode_iter.require ();
6166 if (GET_MODE_BITSIZE (mode) == BITS_PER_UNIT
6167 && !opt_byte_mode.exists ())
6168 opt_byte_mode = mode;
6170 if (GET_MODE_BITSIZE (mode) == BITS_PER_WORD
6171 && !opt_word_mode.exists ())
6172 opt_word_mode = mode;
6175 byte_mode = opt_byte_mode.require ();
6176 word_mode = opt_word_mode.require ();
6177 ptr_mode = as_a <scalar_int_mode>
6178 (mode_for_size (POINTER_SIZE, GET_MODE_CLASS (Pmode), 0).require ());
6181 /* Create some permanent unique rtl objects shared between all functions. */
6183 void
6184 init_emit_once (void)
6186 int i;
6187 machine_mode mode;
6188 scalar_float_mode double_mode;
6189 opt_scalar_mode smode_iter;
6191 /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
6192 CONST_FIXED, and memory attribute hash tables. */
6193 const_int_htab = hash_table<const_int_hasher>::create_ggc (37);
6195 #if TARGET_SUPPORTS_WIDE_INT
6196 const_wide_int_htab = hash_table<const_wide_int_hasher>::create_ggc (37);
6197 #endif
6198 const_double_htab = hash_table<const_double_hasher>::create_ggc (37);
6200 if (NUM_POLY_INT_COEFFS > 1)
6201 const_poly_int_htab = hash_table<const_poly_int_hasher>::create_ggc (37);
6203 const_fixed_htab = hash_table<const_fixed_hasher>::create_ggc (37);
6205 reg_attrs_htab = hash_table<reg_attr_hasher>::create_ggc (37);
6207 #ifdef INIT_EXPANDERS
6208 /* This is to initialize {init|mark|free}_machine_status before the first
6209 call to push_function_context_to. This is needed by the Chill front
6210 end which calls push_function_context_to before the first call to
6211 init_function_start. */
6212 INIT_EXPANDERS;
6213 #endif
6215 /* Create the unique rtx's for certain rtx codes and operand values. */
6217 /* Process stack-limiting command-line options. */
6218 if (opt_fstack_limit_symbol_arg != NULL)
6219 stack_limit_rtx
6220 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (opt_fstack_limit_symbol_arg));
6221 if (opt_fstack_limit_register_no >= 0)
6222 stack_limit_rtx = gen_rtx_REG (Pmode, opt_fstack_limit_register_no);
6224 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
6225 tries to use these variables. */
6226 for (i = - MAX_SAVED_CONST_INT; i <= MAX_SAVED_CONST_INT; i++)
6227 const_int_rtx[i + MAX_SAVED_CONST_INT] =
6228 gen_rtx_raw_CONST_INT (VOIDmode, (HOST_WIDE_INT) i);
6230 if (STORE_FLAG_VALUE >= - MAX_SAVED_CONST_INT
6231 && STORE_FLAG_VALUE <= MAX_SAVED_CONST_INT)
6232 const_true_rtx = const_int_rtx[STORE_FLAG_VALUE + MAX_SAVED_CONST_INT];
6233 else
6234 const_true_rtx = gen_rtx_CONST_INT (VOIDmode, STORE_FLAG_VALUE);
6236 double_mode = float_mode_for_size (DOUBLE_TYPE_SIZE).require ();
6238 real_from_integer (&dconst0, double_mode, 0, SIGNED);
6239 real_from_integer (&dconst1, double_mode, 1, SIGNED);
6240 real_from_integer (&dconst2, double_mode, 2, SIGNED);
6242 dconstm1 = dconst1;
6243 dconstm1.sign = 1;
6245 dconsthalf = dconst1;
6246 SET_REAL_EXP (&dconsthalf, REAL_EXP (&dconsthalf) - 1);
6248 for (i = 0; i < 3; i++)
6250 const REAL_VALUE_TYPE *const r =
6251 (i == 0 ? &dconst0 : i == 1 ? &dconst1 : &dconst2);
6253 FOR_EACH_MODE_IN_CLASS (mode, MODE_FLOAT)
6254 const_tiny_rtx[i][(int) mode] =
6255 const_double_from_real_value (*r, mode);
6257 FOR_EACH_MODE_IN_CLASS (mode, MODE_DECIMAL_FLOAT)
6258 const_tiny_rtx[i][(int) mode] =
6259 const_double_from_real_value (*r, mode);
6261 const_tiny_rtx[i][(int) VOIDmode] = GEN_INT (i);
6263 FOR_EACH_MODE_IN_CLASS (mode, MODE_INT)
6264 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
6266 for (mode = MIN_MODE_PARTIAL_INT;
6267 mode <= MAX_MODE_PARTIAL_INT;
6268 mode = (machine_mode)((int)(mode) + 1))
6269 const_tiny_rtx[i][(int) mode] = GEN_INT (i);
6272 const_tiny_rtx[3][(int) VOIDmode] = constm1_rtx;
6274 FOR_EACH_MODE_IN_CLASS (mode, MODE_INT)
6275 const_tiny_rtx[3][(int) mode] = constm1_rtx;
6277 /* For BImode, 1 and -1 are unsigned and signed interpretations
6278 of the same value. */
6279 const_tiny_rtx[0][(int) BImode] = const0_rtx;
6280 const_tiny_rtx[1][(int) BImode] = const_true_rtx;
6281 const_tiny_rtx[3][(int) BImode] = const_true_rtx;
6283 for (mode = MIN_MODE_PARTIAL_INT;
6284 mode <= MAX_MODE_PARTIAL_INT;
6285 mode = (machine_mode)((int)(mode) + 1))
6286 const_tiny_rtx[3][(int) mode] = constm1_rtx;
6288 FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_INT)
6290 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
6291 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
6294 FOR_EACH_MODE_IN_CLASS (mode, MODE_COMPLEX_FLOAT)
6296 rtx inner = const_tiny_rtx[0][(int)GET_MODE_INNER (mode)];
6297 const_tiny_rtx[0][(int) mode] = gen_rtx_CONCAT (mode, inner, inner);
6300 /* As for BImode, "all 1" and "all -1" are unsigned and signed
6301 interpretations of the same value. */
6302 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_BOOL)
6304 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6305 const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3);
6306 const_tiny_rtx[1][(int) mode] = const_tiny_rtx[3][(int) mode];
6309 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_INT)
6311 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6312 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
6313 const_tiny_rtx[3][(int) mode] = gen_const_vector (mode, 3);
6316 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FLOAT)
6318 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6319 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
6322 FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_FRACT)
6324 scalar_mode smode = smode_iter.require ();
6325 FCONST0 (smode).data.high = 0;
6326 FCONST0 (smode).data.low = 0;
6327 FCONST0 (smode).mode = smode;
6328 const_tiny_rtx[0][(int) smode]
6329 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode);
6332 FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UFRACT)
6334 scalar_mode smode = smode_iter.require ();
6335 FCONST0 (smode).data.high = 0;
6336 FCONST0 (smode).data.low = 0;
6337 FCONST0 (smode).mode = smode;
6338 const_tiny_rtx[0][(int) smode]
6339 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode);
6342 FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_ACCUM)
6344 scalar_mode smode = smode_iter.require ();
6345 FCONST0 (smode).data.high = 0;
6346 FCONST0 (smode).data.low = 0;
6347 FCONST0 (smode).mode = smode;
6348 const_tiny_rtx[0][(int) smode]
6349 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode);
6351 /* We store the value 1. */
6352 FCONST1 (smode).data.high = 0;
6353 FCONST1 (smode).data.low = 0;
6354 FCONST1 (smode).mode = smode;
6355 FCONST1 (smode).data
6356 = double_int_one.lshift (GET_MODE_FBIT (smode),
6357 HOST_BITS_PER_DOUBLE_INT,
6358 SIGNED_FIXED_POINT_MODE_P (smode));
6359 const_tiny_rtx[1][(int) smode]
6360 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode);
6363 FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_UACCUM)
6365 scalar_mode smode = smode_iter.require ();
6366 FCONST0 (smode).data.high = 0;
6367 FCONST0 (smode).data.low = 0;
6368 FCONST0 (smode).mode = smode;
6369 const_tiny_rtx[0][(int) smode]
6370 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode), smode);
6372 /* We store the value 1. */
6373 FCONST1 (smode).data.high = 0;
6374 FCONST1 (smode).data.low = 0;
6375 FCONST1 (smode).mode = smode;
6376 FCONST1 (smode).data
6377 = double_int_one.lshift (GET_MODE_FBIT (smode),
6378 HOST_BITS_PER_DOUBLE_INT,
6379 SIGNED_FIXED_POINT_MODE_P (smode));
6380 const_tiny_rtx[1][(int) smode]
6381 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode), smode);
6384 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_FRACT)
6386 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6389 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UFRACT)
6391 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6394 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_ACCUM)
6396 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6397 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
6400 FOR_EACH_MODE_IN_CLASS (mode, MODE_VECTOR_UACCUM)
6402 const_tiny_rtx[0][(int) mode] = gen_const_vector (mode, 0);
6403 const_tiny_rtx[1][(int) mode] = gen_const_vector (mode, 1);
6406 for (i = (int) CCmode; i < (int) MAX_MACHINE_MODE; ++i)
6407 if (GET_MODE_CLASS ((machine_mode) i) == MODE_CC)
6408 const_tiny_rtx[0][i] = const0_rtx;
6410 FOR_EACH_MODE_IN_CLASS (smode_iter, MODE_POINTER_BOUNDS)
6412 scalar_mode smode = smode_iter.require ();
6413 wide_int wi_zero = wi::zero (GET_MODE_PRECISION (smode));
6414 const_tiny_rtx[0][smode] = immed_wide_int_const (wi_zero, smode);
6417 pc_rtx = gen_rtx_fmt_ (PC, VOIDmode);
6418 ret_rtx = gen_rtx_fmt_ (RETURN, VOIDmode);
6419 simple_return_rtx = gen_rtx_fmt_ (SIMPLE_RETURN, VOIDmode);
6420 cc0_rtx = gen_rtx_fmt_ (CC0, VOIDmode);
6421 invalid_insn_rtx = gen_rtx_INSN (VOIDmode,
6422 /*prev_insn=*/NULL,
6423 /*next_insn=*/NULL,
6424 /*bb=*/NULL,
6425 /*pattern=*/NULL_RTX,
6426 /*location=*/-1,
6427 CODE_FOR_nothing,
6428 /*reg_notes=*/NULL_RTX);
6431 /* Produce exact duplicate of insn INSN after AFTER.
6432 Care updating of libcall regions if present. */
6434 rtx_insn *
6435 emit_copy_of_insn_after (rtx_insn *insn, rtx_insn *after)
6437 rtx_insn *new_rtx;
6438 rtx link;
6440 switch (GET_CODE (insn))
6442 case INSN:
6443 new_rtx = emit_insn_after (copy_insn (PATTERN (insn)), after);
6444 break;
6446 case JUMP_INSN:
6447 new_rtx = emit_jump_insn_after (copy_insn (PATTERN (insn)), after);
6448 CROSSING_JUMP_P (new_rtx) = CROSSING_JUMP_P (insn);
6449 break;
6451 case DEBUG_INSN:
6452 new_rtx = emit_debug_insn_after (copy_insn (PATTERN (insn)), after);
6453 break;
6455 case CALL_INSN:
6456 new_rtx = emit_call_insn_after (copy_insn (PATTERN (insn)), after);
6457 if (CALL_INSN_FUNCTION_USAGE (insn))
6458 CALL_INSN_FUNCTION_USAGE (new_rtx)
6459 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn));
6460 SIBLING_CALL_P (new_rtx) = SIBLING_CALL_P (insn);
6461 RTL_CONST_CALL_P (new_rtx) = RTL_CONST_CALL_P (insn);
6462 RTL_PURE_CALL_P (new_rtx) = RTL_PURE_CALL_P (insn);
6463 RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx)
6464 = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn);
6465 break;
6467 default:
6468 gcc_unreachable ();
6471 /* Update LABEL_NUSES. */
6472 mark_jump_label (PATTERN (new_rtx), new_rtx, 0);
6474 INSN_LOCATION (new_rtx) = INSN_LOCATION (insn);
6476 /* If the old insn is frame related, then so is the new one. This is
6477 primarily needed for IA-64 unwind info which marks epilogue insns,
6478 which may be duplicated by the basic block reordering code. */
6479 RTX_FRAME_RELATED_P (new_rtx) = RTX_FRAME_RELATED_P (insn);
6481 /* Locate the end of existing REG_NOTES in NEW_RTX. */
6482 rtx *ptail = &REG_NOTES (new_rtx);
6483 while (*ptail != NULL_RTX)
6484 ptail = &XEXP (*ptail, 1);
6486 /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label
6487 will make them. REG_LABEL_TARGETs are created there too, but are
6488 supposed to be sticky, so we copy them. */
6489 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
6490 if (REG_NOTE_KIND (link) != REG_LABEL_OPERAND)
6492 *ptail = duplicate_reg_note (link);
6493 ptail = &XEXP (*ptail, 1);
6496 INSN_CODE (new_rtx) = INSN_CODE (insn);
6497 return new_rtx;
6500 static GTY((deletable)) rtx hard_reg_clobbers [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
6502 gen_hard_reg_clobber (machine_mode mode, unsigned int regno)
6504 if (hard_reg_clobbers[mode][regno])
6505 return hard_reg_clobbers[mode][regno];
6506 else
6507 return (hard_reg_clobbers[mode][regno] =
6508 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno)));
6511 location_t prologue_location;
6512 location_t epilogue_location;
6514 /* Hold current location information and last location information, so the
6515 datastructures are built lazily only when some instructions in given
6516 place are needed. */
6517 static location_t curr_location;
6519 /* Allocate insn location datastructure. */
6520 void
6521 insn_locations_init (void)
6523 prologue_location = epilogue_location = 0;
6524 curr_location = UNKNOWN_LOCATION;
6527 /* At the end of emit stage, clear current location. */
6528 void
6529 insn_locations_finalize (void)
6531 epilogue_location = curr_location;
6532 curr_location = UNKNOWN_LOCATION;
6535 /* Set current location. */
6536 void
6537 set_curr_insn_location (location_t location)
6539 curr_location = location;
6542 /* Get current location. */
6543 location_t
6544 curr_insn_location (void)
6546 return curr_location;
6549 /* Return lexical scope block insn belongs to. */
6550 tree
6551 insn_scope (const rtx_insn *insn)
6553 return LOCATION_BLOCK (INSN_LOCATION (insn));
6556 /* Return line number of the statement that produced this insn. */
6558 insn_line (const rtx_insn *insn)
6560 return LOCATION_LINE (INSN_LOCATION (insn));
6563 /* Return source file of the statement that produced this insn. */
6564 const char *
6565 insn_file (const rtx_insn *insn)
6567 return LOCATION_FILE (INSN_LOCATION (insn));
6570 /* Return expanded location of the statement that produced this insn. */
6571 expanded_location
6572 insn_location (const rtx_insn *insn)
6574 return expand_location (INSN_LOCATION (insn));
6577 /* Return true if memory model MODEL requires a pre-operation (release-style)
6578 barrier or a post-operation (acquire-style) barrier. While not universal,
6579 this function matches behavior of several targets. */
6581 bool
6582 need_atomic_barrier_p (enum memmodel model, bool pre)
6584 switch (model & MEMMODEL_BASE_MASK)
6586 case MEMMODEL_RELAXED:
6587 case MEMMODEL_CONSUME:
6588 return false;
6589 case MEMMODEL_RELEASE:
6590 return pre;
6591 case MEMMODEL_ACQUIRE:
6592 return !pre;
6593 case MEMMODEL_ACQ_REL:
6594 case MEMMODEL_SEQ_CST:
6595 return true;
6596 default:
6597 gcc_unreachable ();
6601 /* Return a constant shift amount for shifting a value of mode MODE
6602 by VALUE bits. */
6605 gen_int_shift_amount (machine_mode, poly_int64 value)
6607 /* Use a 64-bit mode, to avoid any truncation.
6609 ??? Perhaps this should be automatically derived from the .md files
6610 instead, or perhaps have a target hook. */
6611 scalar_int_mode shift_mode = (BITS_PER_UNIT == 8
6612 ? DImode
6613 : int_mode_for_size (64, 0).require ());
6614 return gen_int_mode (value, shift_mode);
6617 /* Initialize fields of rtl_data related to stack alignment. */
6619 void
6620 rtl_data::init_stack_alignment ()
6622 stack_alignment_needed = STACK_BOUNDARY;
6623 max_used_stack_slot_alignment = STACK_BOUNDARY;
6624 stack_alignment_estimated = 0;
6625 preferred_stack_boundary = STACK_BOUNDARY;
6629 #include "gt-emit-rtl.h"