| blob | 03ad9280386f0d244632403507a63c473be4b941 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (LR_REGNO 65)
33 (CTR_REGNO 66)
34 (ARG_POINTER_REGNUM 67)
35 (CR0_REGNO 68)
36 (CR1_REGNO 69)
37 (CR2_REGNO 70)
38 (CR3_REGNO 71)
39 (CR4_REGNO 72)
40 (CR5_REGNO 73)
41 (CR6_REGNO 74)
42 (CR7_REGNO 75)
43 (MAX_CR_REGNO 75)
44 (CA_REGNO 76)
45 (FIRST_ALTIVEC_REGNO 77)
46 (LAST_ALTIVEC_REGNO 108)
47 (VRSAVE_REGNO 109)
48 (VSCR_REGNO 110)
49 (SPE_ACC_REGNO 111)
50 (SPEFSCR_REGNO 112)
51 (FRAME_POINTER_REGNUM 113)
53 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
54 (TOC_SAVE_OFFSET_32BIT 20)
55 (TOC_SAVE_OFFSET_64BIT 40)
57 ; Function TOC offset in the AIX function descriptor.
58 (AIX_FUNC_DESC_TOC_32BIT 4)
59 (AIX_FUNC_DESC_TOC_64BIT 8)
61 ; Static chain offset in the AIX function descriptor.
62 (AIX_FUNC_DESC_SC_32BIT 8)
63 (AIX_FUNC_DESC_SC_64BIT 16)
64 ])
66 ;;
67 ;; UNSPEC usage
68 ;;
70 (define_c_enum "unspec"
71 [UNSPEC_FRSP ; frsp for POWER machines
72 UNSPEC_PROBE_STACK ; probe stack memory reference
73 UNSPEC_TOCPTR ; address of a word pointing to the TOC
74 UNSPEC_TOC ; address of the TOC (more-or-less)
75 UNSPEC_MOVSI_GOT
76 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
77 UNSPEC_FCTIWZ
78 UNSPEC_FRIM
79 UNSPEC_FRIN
80 UNSPEC_FRIP
81 UNSPEC_FRIZ
82 UNSPEC_LD_MPIC ; load_macho_picbase
83 UNSPEC_MPIC_CORRECT ; macho_correct_pic
84 UNSPEC_TLSGD
85 UNSPEC_TLSLD
86 UNSPEC_MOVESI_FROM_CR
87 UNSPEC_MOVESI_TO_CR
88 UNSPEC_TLSDTPREL
89 UNSPEC_TLSDTPRELHA
90 UNSPEC_TLSDTPRELLO
91 UNSPEC_TLSGOTDTPREL
92 UNSPEC_TLSTPREL
93 UNSPEC_TLSTPRELHA
94 UNSPEC_TLSTPRELLO
95 UNSPEC_TLSGOTTPREL
96 UNSPEC_TLSTLS
97 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
98 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
99 UNSPEC_STFIWX
100 UNSPEC_POPCNTB
101 UNSPEC_FRES
102 UNSPEC_SP_SET
103 UNSPEC_SP_TEST
104 UNSPEC_SYNC
105 UNSPEC_LWSYNC
106 UNSPEC_SYNC_OP
107 UNSPEC_ATOMIC
108 UNSPEC_CMPXCHG
109 UNSPEC_XCHG
110 UNSPEC_AND
111 UNSPEC_DLMZB
112 UNSPEC_DLMZB_CR
113 UNSPEC_DLMZB_STRLEN
114 UNSPEC_RSQRT
115 UNSPEC_TOCREL
116 UNSPEC_MACHOPIC_OFFSET
117 UNSPEC_BPERM
118 UNSPEC_COPYSIGN
119 UNSPEC_PARITY
120 UNSPEC_FCTIW
121 UNSPEC_FCTID
122 UNSPEC_LFIWAX
123 UNSPEC_LFIWZX
124 UNSPEC_FCTIWUZ
125 UNSPEC_GRP_END_NOP
126 ])
128 ;;
129 ;; UNSPEC_VOLATILE usage
130 ;;
132 (define_c_enum "unspecv"
133 [UNSPECV_BLOCK
134 UNSPECV_LL ; load-locked
135 UNSPECV_SC ; store-conditional
136 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
137 UNSPECV_EH_RR ; eh_reg_restore
138 UNSPECV_ISYNC ; isync instruction
139 UNSPECV_MFTB ; move from time base
140 ])
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
178 (automata_option "ndfa")
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
205 (include "predicates.md")
206 (include "constraints.md")
208 (include "darwin.md")
210 \f
211 ;; Mode iterators
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "1")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
292 (define_mode_attr ptrload [(SI "lwz")
293 (DI "ld")])
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 rlwinm %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 andi. %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 andi. %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
656 (define_insn "extendqisi2"
657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
658 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
659 ""
660 "extsb %0,%1"
661 [(set_attr "type" "exts")])
663 (define_insn ""
664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
665 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
666 (const_int 0)))
667 (clobber (match_scratch:SI 2 "=r,r"))]
668 ""
669 "@
670 extsb. %2,%1
671 #"
672 [(set_attr "type" "compare")
673 (set_attr "length" "4,8")])
675 (define_split
676 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
677 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
678 (const_int 0)))
679 (clobber (match_scratch:SI 2 ""))]
680 "reload_completed"
681 [(set (match_dup 2)
682 (sign_extend:SI (match_dup 1)))
683 (set (match_dup 0)
684 (compare:CC (match_dup 2)
685 (const_int 0)))]
686 "")
688 (define_insn ""
689 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
690 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
691 (const_int 0)))
692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
693 (sign_extend:SI (match_dup 1)))]
694 ""
695 "@
696 extsb. %0,%1
697 #"
698 [(set_attr "type" "compare")
699 (set_attr "length" "4,8")])
701 (define_split
702 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
703 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
704 (const_int 0)))
705 (set (match_operand:SI 0 "gpc_reg_operand" "")
706 (sign_extend:SI (match_dup 1)))]
707 "reload_completed"
708 [(set (match_dup 0)
709 (sign_extend:SI (match_dup 1)))
710 (set (match_dup 2)
711 (compare:CC (match_dup 0)
712 (const_int 0)))]
713 "")
715 (define_insn ""
716 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
717 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
718 ""
719 "@
720 lbz%U1%X1 %0,%1
721 rlwinm %0,%1,0,0xff"
722 [(set_attr "type" "load,*")])
724 (define_insn ""
725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
726 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
727 (const_int 0)))
728 (clobber (match_scratch:HI 2 "=r,r"))]
729 ""
730 "@
731 andi. %2,%1,0xff
732 #"
733 [(set_attr "type" "fast_compare,compare")
734 (set_attr "length" "4,8")])
736 (define_split
737 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
738 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
739 (const_int 0)))
740 (clobber (match_scratch:HI 2 ""))]
741 "reload_completed"
742 [(set (match_dup 2)
743 (zero_extend:HI (match_dup 1)))
744 (set (match_dup 0)
745 (compare:CC (match_dup 2)
746 (const_int 0)))]
747 "")
749 (define_insn ""
750 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
751 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
752 (const_int 0)))
753 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
754 (zero_extend:HI (match_dup 1)))]
755 ""
756 "@
757 andi. %0,%1,0xff
758 #"
759 [(set_attr "type" "fast_compare,compare")
760 (set_attr "length" "4,8")])
762 (define_split
763 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
764 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
765 (const_int 0)))
766 (set (match_operand:HI 0 "gpc_reg_operand" "")
767 (zero_extend:HI (match_dup 1)))]
768 "reload_completed"
769 [(set (match_dup 0)
770 (zero_extend:HI (match_dup 1)))
771 (set (match_dup 2)
772 (compare:CC (match_dup 0)
773 (const_int 0)))]
774 "")
776 (define_insn "extendqihi2"
777 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
778 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
779 ""
780 "extsb %0,%1"
781 [(set_attr "type" "exts")])
783 (define_insn ""
784 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
785 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
786 (const_int 0)))
787 (clobber (match_scratch:HI 2 "=r,r"))]
788 ""
789 "@
790 extsb. %2,%1
791 #"
792 [(set_attr "type" "compare")
793 (set_attr "length" "4,8")])
795 (define_split
796 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
797 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
798 (const_int 0)))
799 (clobber (match_scratch:HI 2 ""))]
800 "reload_completed"
801 [(set (match_dup 2)
802 (sign_extend:HI (match_dup 1)))
803 (set (match_dup 0)
804 (compare:CC (match_dup 2)
805 (const_int 0)))]
806 "")
808 (define_insn ""
809 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
810 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
811 (const_int 0)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
813 (sign_extend:HI (match_dup 1)))]
814 ""
815 "@
816 extsb. %0,%1
817 #"
818 [(set_attr "type" "compare")
819 (set_attr "length" "4,8")])
821 (define_split
822 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
823 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
824 (const_int 0)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (sign_extend:HI (match_dup 1)))]
827 "reload_completed"
828 [(set (match_dup 0)
829 (sign_extend:HI (match_dup 1)))
830 (set (match_dup 2)
831 (compare:CC (match_dup 0)
832 (const_int 0)))]
833 "")
835 (define_expand "zero_extendhisi2"
836 [(set (match_operand:SI 0 "gpc_reg_operand" "")
837 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
838 ""
839 "")
841 (define_insn ""
842 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
843 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
844 ""
845 "@
846 lhz%U1%X1 %0,%1
847 rlwinm %0,%1,0,0xffff"
848 [(set_attr "type" "load,*")])
850 (define_insn ""
851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
852 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
853 (const_int 0)))
854 (clobber (match_scratch:SI 2 "=r,r"))]
855 ""
856 "@
857 andi. %2,%1,0xffff
858 #"
859 [(set_attr "type" "fast_compare,compare")
860 (set_attr "length" "4,8")])
862 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
865 (const_int 0)))
866 (clobber (match_scratch:SI 2 ""))]
867 "reload_completed"
868 [(set (match_dup 2)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 0)
871 (compare:CC (match_dup 2)
872 (const_int 0)))]
873 "")
875 (define_insn ""
876 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
878 (const_int 0)))
879 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
880 (zero_extend:SI (match_dup 1)))]
881 ""
882 "@
883 andi. %0,%1,0xffff
884 #"
885 [(set_attr "type" "fast_compare,compare")
886 (set_attr "length" "4,8")])
888 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (set (match_operand:SI 0 "gpc_reg_operand" "")
893 (zero_extend:SI (match_dup 1)))]
894 "reload_completed"
895 [(set (match_dup 0)
896 (zero_extend:SI (match_dup 1)))
897 (set (match_dup 2)
898 (compare:CC (match_dup 0)
899 (const_int 0)))]
900 "")
902 (define_expand "extendhisi2"
903 [(set (match_operand:SI 0 "gpc_reg_operand" "")
904 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
905 ""
906 "")
908 (define_insn ""
909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
910 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
911 "rs6000_gen_cell_microcode"
912 "@
913 lha%U1%X1 %0,%1
914 extsh %0,%1"
915 [(set_attr "type" "load_ext,exts")])
917 (define_insn ""
918 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
919 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
920 "!rs6000_gen_cell_microcode"
921 "extsh %0,%1"
922 [(set_attr "type" "exts")])
924 (define_insn ""
925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
926 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
927 (const_int 0)))
928 (clobber (match_scratch:SI 2 "=r,r"))]
929 ""
930 "@
931 extsh. %2,%1
932 #"
933 [(set_attr "type" "compare")
934 (set_attr "length" "4,8")])
936 (define_split
937 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
938 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
939 (const_int 0)))
940 (clobber (match_scratch:SI 2 ""))]
941 "reload_completed"
942 [(set (match_dup 2)
943 (sign_extend:SI (match_dup 1)))
944 (set (match_dup 0)
945 (compare:CC (match_dup 2)
946 (const_int 0)))]
947 "")
949 (define_insn ""
950 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
952 (const_int 0)))
953 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
954 (sign_extend:SI (match_dup 1)))]
955 ""
956 "@
957 extsh. %0,%1
958 #"
959 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")])
962 (define_split
963 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
965 (const_int 0)))
966 (set (match_operand:SI 0 "gpc_reg_operand" "")
967 (sign_extend:SI (match_dup 1)))]
968 "reload_completed"
969 [(set (match_dup 0)
970 (sign_extend:SI (match_dup 1)))
971 (set (match_dup 2)
972 (compare:CC (match_dup 0)
973 (const_int 0)))]
974 "")
975 \f
976 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
978 (define_insn "*macchwc"
979 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
980 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
981 (match_operand:SI 2 "gpc_reg_operand" "r")
982 (const_int 16))
983 (sign_extend:SI
984 (match_operand:HI 1 "gpc_reg_operand" "r")))
985 (match_operand:SI 4 "gpc_reg_operand" "0"))
986 (const_int 0)))
987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
988 (plus:SI (mult:SI (ashiftrt:SI
989 (match_dup 2)
990 (const_int 16))
991 (sign_extend:SI
992 (match_dup 1)))
993 (match_dup 4)))]
994 "TARGET_MULHW"
995 "macchw. %0,%1,%2"
996 [(set_attr "type" "imul3")])
998 (define_insn "*macchw"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1000 (plus:SI (mult:SI (ashiftrt:SI
1001 (match_operand:SI 2 "gpc_reg_operand" "r")
1002 (const_int 16))
1003 (sign_extend:SI
1004 (match_operand:HI 1 "gpc_reg_operand" "r")))
1005 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1006 "TARGET_MULHW"
1007 "macchw %0,%1,%2"
1008 [(set_attr "type" "imul3")])
1010 (define_insn "*macchwuc"
1011 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1012 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (const_int 16))
1015 (zero_extend:SI
1016 (match_operand:HI 1 "gpc_reg_operand" "r")))
1017 (match_operand:SI 4 "gpc_reg_operand" "0"))
1018 (const_int 0)))
1019 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1020 (plus:SI (mult:SI (lshiftrt:SI
1021 (match_dup 2)
1022 (const_int 16))
1023 (zero_extend:SI
1024 (match_dup 1)))
1025 (match_dup 4)))]
1026 "TARGET_MULHW"
1027 "macchwu. %0,%1,%2"
1028 [(set_attr "type" "imul3")])
1030 (define_insn "*macchwu"
1031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1032 (plus:SI (mult:SI (lshiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16))
1035 (zero_extend:SI
1036 (match_operand:HI 1 "gpc_reg_operand" "r")))
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "TARGET_MULHW"
1039 "macchwu %0,%1,%2"
1040 [(set_attr "type" "imul3")])
1042 (define_insn "*machhwc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1046 (const_int 16))
1047 (ashiftrt:SI
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (const_int 16)))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (ashiftrt:SI
1054 (match_dup 1)
1055 (const_int 16))
1056 (ashiftrt:SI
1057 (match_dup 2)
1058 (const_int 16)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "machhw. %0,%1,%2"
1062 [(set_attr "type" "imul3")])
1064 (define_insn "*machhw"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (ashiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1068 (const_int 16))
1069 (ashiftrt:SI
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (const_int 16)))
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "TARGET_MULHW"
1074 "machhw %0,%1,%2"
1075 [(set_attr "type" "imul3")])
1077 (define_insn "*machhwuc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1080 (match_operand:SI 1 "gpc_reg_operand" "%r")
1081 (const_int 16))
1082 (lshiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16)))
1085 (match_operand:SI 4 "gpc_reg_operand" "0"))
1086 (const_int 0)))
1087 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1088 (plus:SI (mult:SI (lshiftrt:SI
1089 (match_dup 1)
1090 (const_int 16))
1091 (lshiftrt:SI
1092 (match_dup 2)
1093 (const_int 16)))
1094 (match_dup 4)))]
1095 "TARGET_MULHW"
1096 "machhwu. %0,%1,%2"
1097 [(set_attr "type" "imul3")])
1099 (define_insn "*machhwu"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (plus:SI (mult:SI (lshiftrt:SI
1102 (match_operand:SI 1 "gpc_reg_operand" "%r")
1103 (const_int 16))
1104 (lshiftrt:SI
1105 (match_operand:SI 2 "gpc_reg_operand" "r")
1106 (const_int 16)))
1107 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1108 "TARGET_MULHW"
1109 "machhwu %0,%1,%2"
1110 [(set_attr "type" "imul3")])
1112 (define_insn "*maclhwc"
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1115 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1116 (sign_extend:SI
1117 (match_operand:HI 2 "gpc_reg_operand" "r")))
1118 (match_operand:SI 4 "gpc_reg_operand" "0"))
1119 (const_int 0)))
1120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (plus:SI (mult:SI (sign_extend:SI
1122 (match_dup 1))
1123 (sign_extend:SI
1124 (match_dup 2)))
1125 (match_dup 4)))]
1126 "TARGET_MULHW"
1127 "maclhw. %0,%1,%2"
1128 [(set_attr "type" "imul3")])
1130 (define_insn "*maclhw"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1132 (plus:SI (mult:SI (sign_extend:SI
1133 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1134 (sign_extend:SI
1135 (match_operand:HI 2 "gpc_reg_operand" "r")))
1136 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1137 "TARGET_MULHW"
1138 "maclhw %0,%1,%2"
1139 [(set_attr "type" "imul3")])
1141 (define_insn "*maclhwuc"
1142 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1143 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1144 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1145 (zero_extend:SI
1146 (match_operand:HI 2 "gpc_reg_operand" "r")))
1147 (match_operand:SI 4 "gpc_reg_operand" "0"))
1148 (const_int 0)))
1149 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1150 (plus:SI (mult:SI (zero_extend:SI
1151 (match_dup 1))
1152 (zero_extend:SI
1153 (match_dup 2)))
1154 (match_dup 4)))]
1155 "TARGET_MULHW"
1156 "maclhwu. %0,%1,%2"
1157 [(set_attr "type" "imul3")])
1159 (define_insn "*maclhwu"
1160 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1161 (plus:SI (mult:SI (zero_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1163 (zero_extend:SI
1164 (match_operand:HI 2 "gpc_reg_operand" "r")))
1165 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1166 "TARGET_MULHW"
1167 "maclhwu %0,%1,%2"
1168 [(set_attr "type" "imul3")])
1170 (define_insn "*nmacchwc"
1171 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1172 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1173 (mult:SI (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))
1176 (sign_extend:SI
1177 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1178 (const_int 0)))
1179 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1180 (minus:SI (match_dup 4)
1181 (mult:SI (ashiftrt:SI
1182 (match_dup 2)
1183 (const_int 16))
1184 (sign_extend:SI
1185 (match_dup 1)))))]
1186 "TARGET_MULHW"
1187 "nmacchw. %0,%1,%2"
1188 [(set_attr "type" "imul3")])
1190 (define_insn "*nmacchw"
1191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1192 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1193 (mult:SI (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16))
1196 (sign_extend:SI
1197 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1198 "TARGET_MULHW"
1199 "nmacchw %0,%1,%2"
1200 [(set_attr "type" "imul3")])
1202 (define_insn "*nmachhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (ashiftrt:SI
1206 (match_operand:SI 1 "gpc_reg_operand" "%r")
1207 (const_int 16))
1208 (ashiftrt:SI
1209 (match_operand:SI 2 "gpc_reg_operand" "r")
1210 (const_int 16))))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (minus:SI (match_dup 4)
1214 (mult:SI (ashiftrt:SI
1215 (match_dup 1)
1216 (const_int 16))
1217 (ashiftrt:SI
1218 (match_dup 2)
1219 (const_int 16)))))]
1220 "TARGET_MULHW"
1221 "nmachhw. %0,%1,%2"
1222 [(set_attr "type" "imul3")])
1224 (define_insn "*nmachhw"
1225 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1226 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1227 (mult:SI (ashiftrt:SI
1228 (match_operand:SI 1 "gpc_reg_operand" "%r")
1229 (const_int 16))
1230 (ashiftrt:SI
1231 (match_operand:SI 2 "gpc_reg_operand" "r")
1232 (const_int 16)))))]
1233 "TARGET_MULHW"
1234 "nmachhw %0,%1,%2"
1235 [(set_attr "type" "imul3")])
1237 (define_insn "*nmaclhwc"
1238 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1239 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1240 (mult:SI (sign_extend:SI
1241 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1242 (sign_extend:SI
1243 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1244 (const_int 0)))
1245 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (minus:SI (match_dup 4)
1247 (mult:SI (sign_extend:SI
1248 (match_dup 1))
1249 (sign_extend:SI
1250 (match_dup 2)))))]
1251 "TARGET_MULHW"
1252 "nmaclhw. %0,%1,%2"
1253 [(set_attr "type" "imul3")])
1255 (define_insn "*nmaclhw"
1256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1257 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1258 (mult:SI (sign_extend:SI
1259 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1260 (sign_extend:SI
1261 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1262 "TARGET_MULHW"
1263 "nmaclhw %0,%1,%2"
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*mulchwc"
1267 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1268 (compare:CC (mult:SI (ashiftrt:SI
1269 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (const_int 16))
1271 (sign_extend:SI
1272 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (ashiftrt:SI
1276 (match_dup 2)
1277 (const_int 16))
1278 (sign_extend:SI
1279 (match_dup 1))))]
1280 "TARGET_MULHW"
1281 "mulchw. %0,%1,%2"
1282 [(set_attr "type" "imul3")])
1284 (define_insn "*mulchw"
1285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1286 (mult:SI (ashiftrt:SI
1287 (match_operand:SI 2 "gpc_reg_operand" "r")
1288 (const_int 16))
1289 (sign_extend:SI
1290 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1291 "TARGET_MULHW"
1292 "mulchw %0,%1,%2"
1293 [(set_attr "type" "imul3")])
1295 (define_insn "*mulchwuc"
1296 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1297 (compare:CC (mult:SI (lshiftrt:SI
1298 (match_operand:SI 2 "gpc_reg_operand" "r")
1299 (const_int 16))
1300 (zero_extend:SI
1301 (match_operand:HI 1 "gpc_reg_operand" "r")))
1302 (const_int 0)))
1303 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1304 (mult:SI (lshiftrt:SI
1305 (match_dup 2)
1306 (const_int 16))
1307 (zero_extend:SI
1308 (match_dup 1))))]
1309 "TARGET_MULHW"
1310 "mulchwu. %0,%1,%2"
1311 [(set_attr "type" "imul3")])
1313 (define_insn "*mulchwu"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (lshiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16))
1318 (zero_extend:SI
1319 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1320 "TARGET_MULHW"
1321 "mulchwu %0,%1,%2"
1322 [(set_attr "type" "imul3")])
1324 (define_insn "*mulhhwc"
1325 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1326 (compare:CC (mult:SI (ashiftrt:SI
1327 (match_operand:SI 1 "gpc_reg_operand" "%r")
1328 (const_int 16))
1329 (ashiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16)))
1332 (const_int 0)))
1333 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (mult:SI (ashiftrt:SI
1335 (match_dup 1)
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_dup 2)
1339 (const_int 16))))]
1340 "TARGET_MULHW"
1341 "mulhhw. %0,%1,%2"
1342 [(set_attr "type" "imul3")])
1344 (define_insn "*mulhhw"
1345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1346 (mult:SI (ashiftrt:SI
1347 (match_operand:SI 1 "gpc_reg_operand" "%r")
1348 (const_int 16))
1349 (ashiftrt:SI
1350 (match_operand:SI 2 "gpc_reg_operand" "r")
1351 (const_int 16))))]
1352 "TARGET_MULHW"
1353 "mulhhw %0,%1,%2"
1354 [(set_attr "type" "imul3")])
1356 (define_insn "*mulhhwuc"
1357 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1358 (compare:CC (mult:SI (lshiftrt:SI
1359 (match_operand:SI 1 "gpc_reg_operand" "%r")
1360 (const_int 16))
1361 (lshiftrt:SI
1362 (match_operand:SI 2 "gpc_reg_operand" "r")
1363 (const_int 16)))
1364 (const_int 0)))
1365 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1366 (mult:SI (lshiftrt:SI
1367 (match_dup 1)
1368 (const_int 16))
1369 (lshiftrt:SI
1370 (match_dup 2)
1371 (const_int 16))))]
1372 "TARGET_MULHW"
1373 "mulhhwu. %0,%1,%2"
1374 [(set_attr "type" "imul3")])
1376 (define_insn "*mulhhwu"
1377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1378 (mult:SI (lshiftrt:SI
1379 (match_operand:SI 1 "gpc_reg_operand" "%r")
1380 (const_int 16))
1381 (lshiftrt:SI
1382 (match_operand:SI 2 "gpc_reg_operand" "r")
1383 (const_int 16))))]
1384 "TARGET_MULHW"
1385 "mulhhwu %0,%1,%2"
1386 [(set_attr "type" "imul3")])
1388 (define_insn "*mullhwc"
1389 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1390 (compare:CC (mult:SI (sign_extend:SI
1391 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1392 (sign_extend:SI
1393 (match_operand:HI 2 "gpc_reg_operand" "r")))
1394 (const_int 0)))
1395 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1396 (mult:SI (sign_extend:SI
1397 (match_dup 1))
1398 (sign_extend:SI
1399 (match_dup 2))))]
1400 "TARGET_MULHW"
1401 "mullhw. %0,%1,%2"
1402 [(set_attr "type" "imul3")])
1404 (define_insn "*mullhw"
1405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1406 (mult:SI (sign_extend:SI
1407 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1408 (sign_extend:SI
1409 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1410 "TARGET_MULHW"
1411 "mullhw %0,%1,%2"
1412 [(set_attr "type" "imul3")])
1414 (define_insn "*mullhwuc"
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1416 (compare:CC (mult:SI (zero_extend:SI
1417 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1418 (zero_extend:SI
1419 (match_operand:HI 2 "gpc_reg_operand" "r")))
1420 (const_int 0)))
1421 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1422 (mult:SI (zero_extend:SI
1423 (match_dup 1))
1424 (zero_extend:SI
1425 (match_dup 2))))]
1426 "TARGET_MULHW"
1427 "mullhwu. %0,%1,%2"
1428 [(set_attr "type" "imul3")])
1430 (define_insn "*mullhwu"
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (mult:SI (zero_extend:SI
1433 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1434 (zero_extend:SI
1435 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1436 "TARGET_MULHW"
1437 "mullhwu %0,%1,%2"
1438 [(set_attr "type" "imul3")])
1439 \f
1440 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1441 (define_insn "dlmzb"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1444 (match_operand:SI 2 "gpc_reg_operand" "r")]
1445 UNSPEC_DLMZB_CR))
1446 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1447 (unspec:SI [(match_dup 1)
1448 (match_dup 2)]
1449 UNSPEC_DLMZB))]
1450 "TARGET_DLMZB"
1451 "dlmzb. %0,%1,%2")
1453 (define_expand "strlensi"
1454 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1455 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1456 (match_operand:QI 2 "const_int_operand" "")
1457 (match_operand 3 "const_int_operand" "")]
1458 UNSPEC_DLMZB_STRLEN))
1459 (clobber (match_scratch:CC 4 "=x"))]
1460 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1461 {
1462 rtx result = operands[0];
1463 rtx src = operands[1];
1464 rtx search_char = operands[2];
1465 rtx align = operands[3];
1466 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1467 rtx loop_label, end_label, mem, cr0, cond;
1468 if (search_char != const0_rtx
1469 || GET_CODE (align) != CONST_INT
1470 || INTVAL (align) < 8)
1471 FAIL;
1472 word1 = gen_reg_rtx (SImode);
1473 word2 = gen_reg_rtx (SImode);
1474 scratch_dlmzb = gen_reg_rtx (SImode);
1475 scratch_string = gen_reg_rtx (Pmode);
1476 loop_label = gen_label_rtx ();
1477 end_label = gen_label_rtx ();
1478 addr = force_reg (Pmode, XEXP (src, 0));
1479 emit_move_insn (scratch_string, addr);
1480 emit_label (loop_label);
1481 mem = change_address (src, SImode, scratch_string);
1482 emit_move_insn (word1, mem);
1483 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1484 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1485 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1486 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1487 emit_jump_insn (gen_rtx_SET (VOIDmode,
1488 pc_rtx,
1489 gen_rtx_IF_THEN_ELSE (VOIDmode,
1490 cond,
1491 gen_rtx_LABEL_REF
1492 (VOIDmode,
1493 end_label),
1494 pc_rtx)));
1495 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1496 emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 pc_rtx,
1498 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1499 emit_barrier ();
1500 emit_label (end_label);
1501 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1502 emit_insn (gen_subsi3 (result, scratch_string, addr));
1503 emit_insn (gen_subsi3 (result, result, const1_rtx));
1504 DONE;
1505 })
1506 \f
1507 ;; Fixed-point arithmetic insns.
1509 (define_expand "add<mode>3"
1510 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1511 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1512 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1513 ""
1514 {
1515 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1516 {
1517 if (non_short_cint_operand (operands[2], DImode))
1518 FAIL;
1519 }
1520 else if (GET_CODE (operands[2]) == CONST_INT
1521 && ! add_operand (operands[2], <MODE>mode))
1522 {
1523 rtx tmp = ((!can_create_pseudo_p ()
1524 || rtx_equal_p (operands[0], operands[1]))
1525 ? operands[0] : gen_reg_rtx (<MODE>mode));
1527 HOST_WIDE_INT val = INTVAL (operands[2]);
1528 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1529 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1531 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1532 FAIL;
1534 /* The ordering here is important for the prolog expander.
1535 When space is allocated from the stack, adding 'low' first may
1536 produce a temporary deallocation (which would be bad). */
1537 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1538 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1539 DONE;
1540 }
1541 })
1543 ;; Discourage ai/addic because of carry but provide it in an alternative
1544 ;; allowing register zero as source.
1545 (define_insn "*add<mode>3_internal1"
1546 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1547 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1548 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1549 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1550 "@
1551 add %0,%1,%2
1552 addi %0,%1,%2
1553 addic %0,%1,%2
1554 addis %0,%1,%v2"
1555 [(set_attr "length" "4,4,4,4")])
1557 (define_insn "addsi3_high"
1558 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1559 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1560 (high:SI (match_operand 2 "" ""))))]
1561 "TARGET_MACHO && !TARGET_64BIT"
1562 "addis %0,%1,ha16(%2)"
1563 [(set_attr "length" "4")])
1565 (define_insn "*add<mode>3_internal2"
1566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1567 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1568 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1569 (const_int 0)))
1570 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1571 ""
1572 "@
1573 add. %3,%1,%2
1574 addic. %3,%1,%2
1575 #
1576 #"
1577 [(set_attr "type" "fast_compare,compare,compare,compare")
1578 (set_attr "length" "4,4,8,8")])
1580 (define_split
1581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1582 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1583 (match_operand:GPR 2 "reg_or_short_operand" ""))
1584 (const_int 0)))
1585 (clobber (match_scratch:GPR 3 ""))]
1586 "reload_completed"
1587 [(set (match_dup 3)
1588 (plus:GPR (match_dup 1)
1589 (match_dup 2)))
1590 (set (match_dup 0)
1591 (compare:CC (match_dup 3)
1592 (const_int 0)))]
1593 "")
1595 (define_insn "*add<mode>3_internal3"
1596 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1597 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1598 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1599 (const_int 0)))
1600 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1601 (plus:P (match_dup 1)
1602 (match_dup 2)))]
1603 ""
1604 "@
1605 add. %0,%1,%2
1606 addic. %0,%1,%2
1607 #
1608 #"
1609 [(set_attr "type" "fast_compare,compare,compare,compare")
1610 (set_attr "length" "4,4,8,8")])
1612 (define_split
1613 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1614 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1615 (match_operand:P 2 "reg_or_short_operand" ""))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "")
1618 (plus:P (match_dup 1) (match_dup 2)))]
1619 "reload_completed"
1620 [(set (match_dup 0)
1621 (plus:P (match_dup 1)
1622 (match_dup 2)))
1623 (set (match_dup 3)
1624 (compare:CC (match_dup 0)
1625 (const_int 0)))]
1626 "")
1628 ;; Split an add that we can't do in one insn into two insns, each of which
1629 ;; does one 16-bit part. This is used by combine. Note that the low-order
1630 ;; add should be last in case the result gets used in an address.
1632 (define_split
1633 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1634 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1635 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1636 ""
1637 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1638 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1639 {
1640 HOST_WIDE_INT val = INTVAL (operands[2]);
1641 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1642 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1644 operands[4] = GEN_INT (low);
1645 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1646 operands[3] = GEN_INT (rest);
1647 else if (can_create_pseudo_p ())
1648 {
1649 operands[3] = gen_reg_rtx (DImode);
1650 emit_move_insn (operands[3], operands[2]);
1651 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1652 DONE;
1653 }
1654 else
1655 FAIL;
1656 })
1658 (define_insn "one_cmpl<mode>2"
1659 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1660 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1661 ""
1662 "nor %0,%1,%1")
1664 (define_insn ""
1665 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1666 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1667 (const_int 0)))
1668 (clobber (match_scratch:P 2 "=r,r"))]
1669 ""
1670 "@
1671 nor. %2,%1,%1
1672 #"
1673 [(set_attr "type" "fast_compare,compare")
1674 (set_attr "length" "4,8")])
1676 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1679 (const_int 0)))
1680 (clobber (match_scratch:P 2 ""))]
1681 "reload_completed"
1682 [(set (match_dup 2)
1683 (not:P (match_dup 1)))
1684 (set (match_dup 0)
1685 (compare:CC (match_dup 2)
1686 (const_int 0)))]
1687 "")
1689 (define_insn ""
1690 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1692 (const_int 0)))
1693 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1694 (not:P (match_dup 1)))]
1695 ""
1696 "@
1697 nor. %0,%1,%1
1698 #"
1699 [(set_attr "type" "fast_compare,compare")
1700 (set_attr "length" "4,8")])
1702 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1705 (const_int 0)))
1706 (set (match_operand:P 0 "gpc_reg_operand" "")
1707 (not:P (match_dup 1)))]
1708 "reload_completed"
1709 [(set (match_dup 0)
1710 (not:P (match_dup 1)))
1711 (set (match_dup 2)
1712 (compare:CC (match_dup 0)
1713 (const_int 0)))]
1714 "")
1716 (define_insn ""
1717 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1718 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1719 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1720 ""
1721 "@
1722 subf %0,%2,%1
1723 subfic %0,%2,%1")
1725 (define_insn ""
1726 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1727 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1728 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1729 (const_int 0)))
1730 (clobber (match_scratch:P 3 "=r,r"))]
1731 ""
1732 "@
1733 subf. %3,%2,%1
1734 #"
1735 [(set_attr "type" "fast_compare")
1736 (set_attr "length" "4,8")])
1738 (define_split
1739 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1740 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1741 (match_operand:P 2 "gpc_reg_operand" ""))
1742 (const_int 0)))
1743 (clobber (match_scratch:P 3 ""))]
1744 "reload_completed"
1745 [(set (match_dup 3)
1746 (minus:P (match_dup 1)
1747 (match_dup 2)))
1748 (set (match_dup 0)
1749 (compare:CC (match_dup 3)
1750 (const_int 0)))]
1751 "")
1753 (define_insn ""
1754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1755 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1756 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1757 (const_int 0)))
1758 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1759 (minus:P (match_dup 1)
1760 (match_dup 2)))]
1761 ""
1762 "@
1763 subf. %0,%2,%1
1764 #"
1765 [(set_attr "type" "fast_compare")
1766 (set_attr "length" "4,8")])
1768 (define_split
1769 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1770 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1771 (match_operand:P 2 "gpc_reg_operand" ""))
1772 (const_int 0)))
1773 (set (match_operand:P 0 "gpc_reg_operand" "")
1774 (minus:P (match_dup 1)
1775 (match_dup 2)))]
1776 "reload_completed"
1777 [(set (match_dup 0)
1778 (minus:P (match_dup 1)
1779 (match_dup 2)))
1780 (set (match_dup 3)
1781 (compare:CC (match_dup 0)
1782 (const_int 0)))]
1783 "")
1785 (define_expand "sub<mode>3"
1786 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1787 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1788 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1789 ""
1790 "
1791 {
1792 if (GET_CODE (operands[2]) == CONST_INT)
1793 {
1794 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1795 negate_rtx (<MODE>mode, operands[2])));
1796 DONE;
1797 }
1798 }")
1800 (define_expand "neg<mode>2"
1801 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1802 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1803 ""
1804 "")
1806 (define_insn "*neg<mode>2_internal"
1807 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1808 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1809 ""
1810 "neg %0,%1")
1812 (define_insn ""
1813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1814 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1815 (const_int 0)))
1816 (clobber (match_scratch:P 2 "=r,r"))]
1817 ""
1818 "@
1819 neg. %2,%1
1820 #"
1821 [(set_attr "type" "fast_compare")
1822 (set_attr "length" "4,8")])
1824 (define_split
1825 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1826 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1827 (const_int 0)))
1828 (clobber (match_scratch:P 2 ""))]
1829 "reload_completed"
1830 [(set (match_dup 2)
1831 (neg:P (match_dup 1)))
1832 (set (match_dup 0)
1833 (compare:CC (match_dup 2)
1834 (const_int 0)))]
1835 "")
1837 (define_insn ""
1838 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1839 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1840 (const_int 0)))
1841 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1842 (neg:P (match_dup 1)))]
1843 ""
1844 "@
1845 neg. %0,%1
1846 #"
1847 [(set_attr "type" "fast_compare")
1848 (set_attr "length" "4,8")])
1850 (define_split
1851 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1852 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
1853 (const_int 0)))
1854 (set (match_operand:P 0 "gpc_reg_operand" "")
1855 (neg:P (match_dup 1)))]
1856 "reload_completed"
1857 [(set (match_dup 0)
1858 (neg:P (match_dup 1)))
1859 (set (match_dup 2)
1860 (compare:CC (match_dup 0)
1861 (const_int 0)))]
1862 "")
1864 (define_insn "clz<mode>2"
1865 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1866 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1867 ""
1868 "cntlz<wd> %0,%1"
1869 [(set_attr "type" "cntlz")])
1871 (define_expand "ctz<mode>2"
1872 [(set (match_dup 2)
1873 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1874 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1875 (match_dup 2)))
1876 (clobber (scratch:CC))])
1877 (set (match_dup 4) (clz:GPR (match_dup 3)))
1878 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1879 (minus:GPR (match_dup 5) (match_dup 4)))]
1880 ""
1881 {
1882 operands[2] = gen_reg_rtx (<MODE>mode);
1883 operands[3] = gen_reg_rtx (<MODE>mode);
1884 operands[4] = gen_reg_rtx (<MODE>mode);
1885 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
1886 })
1888 (define_expand "ffs<mode>2"
1889 [(set (match_dup 2)
1890 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
1891 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
1892 (match_dup 2)))
1893 (clobber (scratch:CC))])
1894 (set (match_dup 4) (clz:GPR (match_dup 3)))
1895 (set (match_operand:GPR 0 "gpc_reg_operand" "")
1896 (minus:GPR (match_dup 5) (match_dup 4)))]
1897 ""
1898 {
1899 operands[2] = gen_reg_rtx (<MODE>mode);
1900 operands[3] = gen_reg_rtx (<MODE>mode);
1901 operands[4] = gen_reg_rtx (<MODE>mode);
1902 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1903 })
1905 (define_insn "popcntb<mode>2"
1906 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1907 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
1908 UNSPEC_POPCNTB))]
1909 "TARGET_POPCNTB"
1910 "popcntb %0,%1"
1911 [(set_attr "length" "4")
1912 (set_attr "type" "popcnt")])
1914 (define_insn "popcntd<mode>2"
1915 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1916 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1917 "TARGET_POPCNTD"
1918 "popcnt<wd> %0,%1"
1919 [(set_attr "length" "4")
1920 (set_attr "type" "popcnt")])
1922 (define_expand "popcount<mode>2"
1923 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1924 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1925 "TARGET_POPCNTB || TARGET_POPCNTD"
1926 {
1927 rs6000_emit_popcount (operands[0], operands[1]);
1928 DONE;
1929 })
1931 (define_insn "parity<mode>2_cmpb"
1932 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1933 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
1934 "TARGET_CMPB && TARGET_POPCNTB"
1935 "prty<wd> %0,%1")
1937 (define_expand "parity<mode>2"
1938 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1939 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
1940 "TARGET_POPCNTB"
1941 {
1942 rs6000_emit_parity (operands[0], operands[1]);
1943 DONE;
1944 })
1946 ;; Since the hardware zeros the upper part of the register, save generating the
1947 ;; AND immediate if we are converting to unsigned
1948 (define_insn "*bswaphi2_extenddi"
1949 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
1950 (zero_extend:DI
1951 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1952 "TARGET_POWERPC64"
1953 "lhbrx %0,%y1"
1954 [(set_attr "length" "4")
1955 (set_attr "type" "load")])
1957 (define_insn "*bswaphi2_extendsi"
1958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1959 (zero_extend:SI
1960 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
1961 ""
1962 "lhbrx %0,%y1"
1963 [(set_attr "length" "4")
1964 (set_attr "type" "load")])
1966 (define_expand "bswaphi2"
1967 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1968 (bswap:HI
1969 (match_operand:HI 1 "reg_or_mem_operand" "")))
1970 (clobber (match_scratch:SI 2 ""))])]
1971 ""
1972 {
1973 if (!REG_P (operands[0]) && !REG_P (operands[1]))
1974 operands[1] = force_reg (HImode, operands[1]);
1975 })
1977 (define_insn "bswaphi2_internal"
1978 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
1979 (bswap:HI
1980 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
1981 (clobber (match_scratch:SI 2 "=X,X,&r"))]
1982 ""
1983 "@
1984 lhbrx %0,%y1
1985 sthbrx %1,%y0
1986 #"
1987 [(set_attr "length" "4,4,12")
1988 (set_attr "type" "load,store,*")])
1990 (define_split
1991 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1992 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
1993 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
1994 "reload_completed"
1995 [(set (match_dup 3)
1996 (zero_extract:SI (match_dup 4)
1997 (const_int 8)
1998 (const_int 16)))
1999 (set (match_dup 2)
2000 (and:SI (ashift:SI (match_dup 4)
2001 (const_int 8))
2002 (const_int 65280))) ;; 0xff00
2003 (set (match_dup 3)
2004 (ior:SI (match_dup 3)
2005 (match_dup 2)))]
2006 "
2007 {
2008 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2009 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2010 }")
2012 (define_insn "*bswapsi2_extenddi"
2013 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2014 (zero_extend:DI
2015 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2016 "TARGET_POWERPC64"
2017 "lwbrx %0,%y1"
2018 [(set_attr "length" "4")
2019 (set_attr "type" "load")])
2021 (define_expand "bswapsi2"
2022 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2023 (bswap:SI
2024 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2025 ""
2026 {
2027 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2028 operands[1] = force_reg (SImode, operands[1]);
2029 })
2031 (define_insn "*bswapsi2_internal"
2032 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2033 (bswap:SI
2034 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2035 ""
2036 "@
2037 lwbrx %0,%y1
2038 stwbrx %1,%y0
2039 #"
2040 [(set_attr "length" "4,4,12")
2041 (set_attr "type" "load,store,*")])
2043 (define_split
2044 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2045 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2046 "reload_completed"
2047 [(set (match_dup 0)
2048 (rotate:SI (match_dup 1) (const_int 8)))
2049 (set (zero_extract:SI (match_dup 0)
2050 (const_int 8)
2051 (const_int 0))
2052 (match_dup 1))
2053 (set (zero_extract:SI (match_dup 0)
2054 (const_int 8)
2055 (const_int 16))
2056 (rotate:SI (match_dup 1)
2057 (const_int 16)))]
2058 "")
2060 (define_expand "bswapdi2"
2061 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2062 (bswap:DI
2063 (match_operand:DI 1 "reg_or_mem_operand" "")))
2064 (clobber (match_scratch:DI 2 ""))
2065 (clobber (match_scratch:DI 3 ""))
2066 (clobber (match_scratch:DI 4 ""))])]
2067 ""
2068 {
2069 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2070 operands[1] = force_reg (DImode, operands[1]);
2072 if (!TARGET_POWERPC64)
2073 {
2074 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2075 that uses 64-bit registers needs the same scratch registers as 64-bit
2076 mode. */
2077 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2078 DONE;
2079 }
2080 })
2082 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2083 (define_insn "*bswapdi2_ldbrx"
2084 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2085 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2086 (clobber (match_scratch:DI 2 "=X,X,&r"))
2087 (clobber (match_scratch:DI 3 "=X,X,&r"))
2088 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2089 "TARGET_POWERPC64 && TARGET_LDBRX
2090 && (REG_P (operands[0]) || REG_P (operands[1]))"
2091 "@
2092 ldbrx %0,%y1
2093 stdbrx %1,%y0
2094 #"
2095 [(set_attr "length" "4,4,36")
2096 (set_attr "type" "load,store,*")])
2098 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2099 (define_insn "*bswapdi2_64bit"
2100 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2101 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2102 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2103 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2104 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2105 "TARGET_POWERPC64 && !TARGET_LDBRX
2106 && (REG_P (operands[0]) || REG_P (operands[1]))"
2107 "#"
2108 [(set_attr "length" "16,12,36")])
2110 (define_split
2111 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2112 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2113 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2114 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2115 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2116 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2117 [(const_int 0)]
2118 "
2119 {
2120 rtx dest = operands[0];
2121 rtx src = operands[1];
2122 rtx op2 = operands[2];
2123 rtx op3 = operands[3];
2124 rtx op4 = operands[4];
2125 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2126 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2127 rtx addr1;
2128 rtx addr2;
2129 rtx word_high;
2130 rtx word_low;
2132 addr1 = XEXP (src, 0);
2133 if (GET_CODE (addr1) == PLUS)
2134 {
2135 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2136 if (TARGET_AVOID_XFORM)
2137 {
2138 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2139 addr2 = op2;
2140 }
2141 else
2142 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2143 }
2144 else if (TARGET_AVOID_XFORM)
2145 {
2146 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2147 addr2 = op2;
2148 }
2149 else
2150 {
2151 emit_move_insn (op2, GEN_INT (4));
2152 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2153 }
2155 if (BYTES_BIG_ENDIAN)
2156 {
2157 word_high = change_address (src, SImode, addr1);
2158 word_low = change_address (src, SImode, addr2);
2159 }
2160 else
2161 {
2162 word_high = change_address (src, SImode, addr2);
2163 word_low = change_address (src, SImode, addr1);
2164 }
2166 emit_insn (gen_bswapsi2 (op3_32, word_low));
2167 emit_insn (gen_bswapsi2 (op4_32, word_high));
2168 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2169 emit_insn (gen_iordi3 (dest, dest, op4));
2170 }")
2172 (define_split
2173 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2174 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2175 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2176 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2177 (clobber (match_operand:DI 4 "" ""))]
2178 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2179 [(const_int 0)]
2180 "
2181 {
2182 rtx dest = operands[0];
2183 rtx src = operands[1];
2184 rtx op2 = operands[2];
2185 rtx op3 = operands[3];
2186 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2187 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2188 rtx addr1;
2189 rtx addr2;
2190 rtx word_high;
2191 rtx word_low;
2193 addr1 = XEXP (dest, 0);
2194 if (GET_CODE (addr1) == PLUS)
2195 {
2196 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2197 if (TARGET_AVOID_XFORM)
2198 {
2199 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2200 addr2 = op2;
2201 }
2202 else
2203 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2204 }
2205 else if (TARGET_AVOID_XFORM)
2206 {
2207 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2208 addr2 = op2;
2209 }
2210 else
2211 {
2212 emit_move_insn (op2, GEN_INT (4));
2213 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2214 }
2216 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2217 if (BYTES_BIG_ENDIAN)
2218 {
2219 word_high = change_address (dest, SImode, addr1);
2220 word_low = change_address (dest, SImode, addr2);
2221 emit_insn (gen_bswapsi2 (word_high, src_si));
2222 emit_insn (gen_bswapsi2 (word_low, op3_si));
2223 }
2224 else
2225 {
2226 word_high = change_address (dest, SImode, addr2);
2227 word_low = change_address (dest, SImode, addr1);
2228 emit_insn (gen_bswapsi2 (word_low, src_si));
2229 emit_insn (gen_bswapsi2 (word_high, op3_si));
2230 }
2231 }")
2233 (define_split
2234 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2235 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2236 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2237 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2238 (clobber (match_operand:DI 4 "" ""))]
2239 "TARGET_POWERPC64 && reload_completed"
2240 [(const_int 0)]
2241 "
2242 {
2243 rtx dest = operands[0];
2244 rtx src = operands[1];
2245 rtx op2 = operands[2];
2246 rtx op3 = operands[3];
2247 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2248 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2249 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2250 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2252 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2253 emit_insn (gen_bswapsi2 (dest_si, src_si));
2254 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2255 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2256 emit_insn (gen_iordi3 (dest, dest, op3));
2257 }")
2259 (define_insn "bswapdi2_32bit"
2260 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2261 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2262 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2263 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2264 "#"
2265 [(set_attr "length" "16,12,36")])
2267 (define_split
2268 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2269 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2270 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2271 "!TARGET_POWERPC64 && reload_completed"
2272 [(const_int 0)]
2273 "
2274 {
2275 rtx dest = operands[0];
2276 rtx src = operands[1];
2277 rtx op2 = operands[2];
2278 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2279 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2280 rtx addr1;
2281 rtx addr2;
2282 rtx word_high;
2283 rtx word_low;
2285 addr1 = XEXP (src, 0);
2286 if (GET_CODE (addr1) == PLUS)
2287 {
2288 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2289 if (TARGET_AVOID_XFORM)
2290 {
2291 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2292 addr2 = op2;
2293 }
2294 else
2295 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2296 }
2297 else if (TARGET_AVOID_XFORM)
2298 {
2299 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2300 addr2 = op2;
2301 }
2302 else
2303 {
2304 emit_move_insn (op2, GEN_INT (4));
2305 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2306 }
2308 if (BYTES_BIG_ENDIAN)
2309 {
2310 word_high = change_address (src, SImode, addr1);
2311 word_low = change_address (src, SImode, addr2);
2312 }
2313 else
2314 {
2315 word_high = change_address (src, SImode, addr2);
2316 word_low = change_address (src, SImode, addr1);
2317 }
2319 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2320 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2321 }")
2323 (define_split
2324 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2325 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2326 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2327 "!TARGET_POWERPC64 && reload_completed"
2328 [(const_int 0)]
2329 "
2330 {
2331 rtx dest = operands[0];
2332 rtx src = operands[1];
2333 rtx op2 = operands[2];
2334 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2335 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2336 rtx addr1;
2337 rtx addr2;
2338 rtx word_high;
2339 rtx word_low;
2341 addr1 = XEXP (dest, 0);
2342 if (GET_CODE (addr1) == PLUS)
2343 {
2344 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2345 if (TARGET_AVOID_XFORM)
2346 {
2347 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2348 addr2 = op2;
2349 }
2350 else
2351 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2352 }
2353 else if (TARGET_AVOID_XFORM)
2354 {
2355 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2356 addr2 = op2;
2357 }
2358 else
2359 {
2360 emit_move_insn (op2, GEN_INT (4));
2361 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2362 }
2364 if (BYTES_BIG_ENDIAN)
2365 {
2366 word_high = change_address (dest, SImode, addr1);
2367 word_low = change_address (dest, SImode, addr2);
2368 }
2369 else
2370 {
2371 word_high = change_address (dest, SImode, addr2);
2372 word_low = change_address (dest, SImode, addr1);
2373 }
2375 emit_insn (gen_bswapsi2 (word_high, src_low));
2376 emit_insn (gen_bswapsi2 (word_low, src_high));
2377 }")
2379 (define_split
2380 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2381 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2382 (clobber (match_operand:SI 2 "" ""))]
2383 "!TARGET_POWERPC64 && reload_completed"
2384 [(const_int 0)]
2385 "
2386 {
2387 rtx dest = operands[0];
2388 rtx src = operands[1];
2389 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2390 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2391 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2392 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2394 emit_insn (gen_bswapsi2 (dest_high, src_low));
2395 emit_insn (gen_bswapsi2 (dest_low, src_high));
2396 }")
2398 (define_insn "mulsi3"
2399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2400 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2401 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2402 ""
2403 "@
2404 mullw %0,%1,%2
2405 mulli %0,%1,%2"
2406 [(set (attr "type")
2407 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2408 (const_string "imul3")
2409 (match_operand:SI 2 "short_cint_operand" "")
2410 (const_string "imul2")]
2411 (const_string "imul")))])
2413 (define_insn "*mulsi3_internal1"
2414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2415 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2416 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2417 (const_int 0)))
2418 (clobber (match_scratch:SI 3 "=r,r"))]
2419 ""
2420 "@
2421 mullw. %3,%1,%2
2422 #"
2423 [(set_attr "type" "imul_compare")
2424 (set_attr "length" "4,8")])
2426 (define_split
2427 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2428 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2429 (match_operand:SI 2 "gpc_reg_operand" ""))
2430 (const_int 0)))
2431 (clobber (match_scratch:SI 3 ""))]
2432 "reload_completed"
2433 [(set (match_dup 3)
2434 (mult:SI (match_dup 1) (match_dup 2)))
2435 (set (match_dup 0)
2436 (compare:CC (match_dup 3)
2437 (const_int 0)))]
2438 "")
2440 (define_insn "*mulsi3_internal2"
2441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2442 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2443 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2444 (const_int 0)))
2445 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2446 (mult:SI (match_dup 1) (match_dup 2)))]
2447 ""
2448 "@
2449 mullw. %0,%1,%2
2450 #"
2451 [(set_attr "type" "imul_compare")
2452 (set_attr "length" "4,8")])
2454 (define_split
2455 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2456 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2457 (match_operand:SI 2 "gpc_reg_operand" ""))
2458 (const_int 0)))
2459 (set (match_operand:SI 0 "gpc_reg_operand" "")
2460 (mult:SI (match_dup 1) (match_dup 2)))]
2461 "reload_completed"
2462 [(set (match_dup 0)
2463 (mult:SI (match_dup 1) (match_dup 2)))
2464 (set (match_dup 3)
2465 (compare:CC (match_dup 0)
2466 (const_int 0)))]
2467 "")
2470 (define_insn "udiv<mode>3"
2471 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2472 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2473 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2474 ""
2475 "div<wd>u %0,%1,%2"
2476 [(set (attr "type")
2477 (cond [(match_operand:SI 0 "" "")
2478 (const_string "idiv")]
2479 (const_string "ldiv")))])
2482 ;; For powers of two we can do srai/aze for divide and then adjust for
2483 ;; modulus. If it isn't a power of two, force operands into register and do
2484 ;; a normal divide.
2485 (define_expand "div<mode>3"
2486 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2487 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2488 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2489 ""
2490 {
2491 if (GET_CODE (operands[2]) != CONST_INT
2492 || INTVAL (operands[2]) <= 0
2493 || exact_log2 (INTVAL (operands[2])) < 0)
2494 operands[2] = force_reg (<MODE>mode, operands[2]);
2495 })
2497 (define_insn "*div<mode>3"
2498 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2499 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2500 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2501 ""
2502 "div<wd> %0,%1,%2"
2503 [(set (attr "type")
2504 (cond [(match_operand:SI 0 "" "")
2505 (const_string "idiv")]
2506 (const_string "ldiv")))])
2508 (define_expand "mod<mode>3"
2509 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2510 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2511 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2512 ""
2513 "
2514 {
2515 int i;
2516 rtx temp1;
2517 rtx temp2;
2519 if (GET_CODE (operands[2]) != CONST_INT
2520 || INTVAL (operands[2]) <= 0
2521 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2522 FAIL;
2524 temp1 = gen_reg_rtx (<MODE>mode);
2525 temp2 = gen_reg_rtx (<MODE>mode);
2527 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2528 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2529 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2530 DONE;
2531 }")
2533 (define_insn ""
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2537 ""
2538 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2539 [(set_attr "type" "two")
2540 (set_attr "length" "8")])
2542 (define_insn ""
2543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2544 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2545 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2546 (const_int 0)))
2547 (clobber (match_scratch:P 3 "=r,r"))]
2548 ""
2549 "@
2550 sra<wd>i %3,%1,%p2\;addze. %3,%3
2551 #"
2552 [(set_attr "type" "compare")
2553 (set_attr "length" "8,12")
2554 (set_attr "cell_micro" "not")])
2556 (define_split
2557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2558 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2559 (match_operand:GPR 2 "exact_log2_cint_operand"
2560 ""))
2561 (const_int 0)))
2562 (clobber (match_scratch:GPR 3 ""))]
2563 "reload_completed"
2564 [(set (match_dup 3)
2565 (div:<MODE> (match_dup 1) (match_dup 2)))
2566 (set (match_dup 0)
2567 (compare:CC (match_dup 3)
2568 (const_int 0)))]
2569 "")
2571 (define_insn ""
2572 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2573 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2574 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2575 (const_int 0)))
2576 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2577 (div:P (match_dup 1) (match_dup 2)))]
2578 ""
2579 "@
2580 sra<wd>i %0,%1,%p2\;addze. %0,%0
2581 #"
2582 [(set_attr "type" "compare")
2583 (set_attr "length" "8,12")
2584 (set_attr "cell_micro" "not")])
2586 (define_split
2587 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2588 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2589 (match_operand:GPR 2 "exact_log2_cint_operand"
2590 ""))
2591 (const_int 0)))
2592 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2593 (div:GPR (match_dup 1) (match_dup 2)))]
2594 "reload_completed"
2595 [(set (match_dup 0)
2596 (div:<MODE> (match_dup 1) (match_dup 2)))
2597 (set (match_dup 3)
2598 (compare:CC (match_dup 0)
2599 (const_int 0)))]
2600 "")
2601 \f
2602 ;; Logical instructions
2603 ;; The logical instructions are mostly combined by using match_operator,
2604 ;; but the plain AND insns are somewhat different because there is no
2605 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2606 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2608 (define_expand "andsi3"
2609 [(parallel
2610 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2611 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2612 (match_operand:SI 2 "and_operand" "")))
2613 (clobber (match_scratch:CC 3 ""))])]
2614 ""
2615 "")
2617 (define_insn "andsi3_mc"
2618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2619 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2620 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2621 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2622 "rs6000_gen_cell_microcode"
2623 "@
2624 and %0,%1,%2
2625 rlwinm %0,%1,0,%m2,%M2
2626 andi. %0,%1,%b2
2627 andis. %0,%1,%u2"
2628 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2630 (define_insn "andsi3_nomc"
2631 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2632 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2633 (match_operand:SI 2 "and_operand" "?r,T")))
2634 (clobber (match_scratch:CC 3 "=X,X"))]
2635 "!rs6000_gen_cell_microcode"
2636 "@
2637 and %0,%1,%2
2638 rlwinm %0,%1,0,%m2,%M2")
2640 (define_insn "andsi3_internal0_nomc"
2641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2642 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2643 (match_operand:SI 2 "and_operand" "?r,T")))]
2644 "!rs6000_gen_cell_microcode"
2645 "@
2646 and %0,%1,%2
2647 rlwinm %0,%1,0,%m2,%M2")
2650 ;; Note to set cr's other than cr0 we do the and immediate and then
2651 ;; the test again -- this avoids a mfcr which on the higher end
2652 ;; machines causes an execution serialization
2654 (define_insn "*andsi3_internal2_mc"
2655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2656 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2657 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2658 (const_int 0)))
2659 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2660 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2661 "TARGET_32BIT && rs6000_gen_cell_microcode"
2662 "@
2663 and. %3,%1,%2
2664 andi. %3,%1,%b2
2665 andis. %3,%1,%u2
2666 rlwinm. %3,%1,0,%m2,%M2
2667 #
2668 #
2669 #
2670 #"
2671 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2672 compare,compare,compare,compare")
2673 (set_attr "length" "4,4,4,4,8,8,8,8")])
2675 (define_insn "*andsi3_internal3_mc"
2676 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2677 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2678 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2679 (const_int 0)))
2680 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2681 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2682 "TARGET_64BIT && rs6000_gen_cell_microcode"
2683 "@
2684 #
2685 andi. %3,%1,%b2
2686 andis. %3,%1,%u2
2687 rlwinm. %3,%1,0,%m2,%M2
2688 #
2689 #
2690 #
2691 #"
2692 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2693 compare,compare,compare")
2694 (set_attr "length" "8,4,4,4,8,8,8,8")])
2696 (define_split
2697 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2698 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2699 (match_operand:GPR 2 "and_operand" ""))
2700 (const_int 0)))
2701 (clobber (match_scratch:GPR 3 ""))
2702 (clobber (match_scratch:CC 4 ""))]
2703 "reload_completed"
2704 [(parallel [(set (match_dup 3)
2705 (and:<MODE> (match_dup 1)
2706 (match_dup 2)))
2707 (clobber (match_dup 4))])
2708 (set (match_dup 0)
2709 (compare:CC (match_dup 3)
2710 (const_int 0)))]
2711 "")
2713 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2714 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2716 (define_split
2717 [(set (match_operand:CC 0 "cc_reg_operand" "")
2718 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2719 (match_operand:SI 2 "gpc_reg_operand" ""))
2720 (const_int 0)))
2721 (clobber (match_scratch:SI 3 ""))
2722 (clobber (match_scratch:CC 4 ""))]
2723 "TARGET_POWERPC64 && reload_completed"
2724 [(parallel [(set (match_dup 3)
2725 (and:SI (match_dup 1)
2726 (match_dup 2)))
2727 (clobber (match_dup 4))])
2728 (set (match_dup 0)
2729 (compare:CC (match_dup 3)
2730 (const_int 0)))]
2731 "")
2733 (define_insn "*andsi3_internal4"
2734 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2735 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2736 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2737 (const_int 0)))
2738 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2739 (and:SI (match_dup 1)
2740 (match_dup 2)))
2741 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2742 "TARGET_32BIT && rs6000_gen_cell_microcode"
2743 "@
2744 and. %0,%1,%2
2745 andi. %0,%1,%b2
2746 andis. %0,%1,%u2
2747 rlwinm. %0,%1,0,%m2,%M2
2748 #
2749 #
2750 #
2751 #"
2752 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2753 compare,compare,compare,compare")
2754 (set_attr "length" "4,4,4,4,8,8,8,8")])
2756 (define_insn "*andsi3_internal5_mc"
2757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2758 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2759 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2760 (const_int 0)))
2761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2762 (and:SI (match_dup 1)
2763 (match_dup 2)))
2764 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2765 "TARGET_64BIT && rs6000_gen_cell_microcode"
2766 "@
2767 #
2768 andi. %0,%1,%b2
2769 andis. %0,%1,%u2
2770 rlwinm. %0,%1,0,%m2,%M2
2771 #
2772 #
2773 #
2774 #"
2775 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2776 compare,compare,compare")
2777 (set_attr "length" "8,4,4,4,8,8,8,8")])
2779 (define_split
2780 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2781 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2782 (match_operand:SI 2 "and_operand" ""))
2783 (const_int 0)))
2784 (set (match_operand:SI 0 "gpc_reg_operand" "")
2785 (and:SI (match_dup 1)
2786 (match_dup 2)))
2787 (clobber (match_scratch:CC 4 ""))]
2788 "reload_completed"
2789 [(parallel [(set (match_dup 0)
2790 (and:SI (match_dup 1)
2791 (match_dup 2)))
2792 (clobber (match_dup 4))])
2793 (set (match_dup 3)
2794 (compare:CC (match_dup 0)
2795 (const_int 0)))]
2796 "")
2798 (define_split
2799 [(set (match_operand:CC 3 "cc_reg_operand" "")
2800 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2801 (match_operand:SI 2 "gpc_reg_operand" ""))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (and:SI (match_dup 1)
2805 (match_dup 2)))
2806 (clobber (match_scratch:CC 4 ""))]
2807 "TARGET_POWERPC64 && reload_completed"
2808 [(parallel [(set (match_dup 0)
2809 (and:SI (match_dup 1)
2810 (match_dup 2)))
2811 (clobber (match_dup 4))])
2812 (set (match_dup 3)
2813 (compare:CC (match_dup 0)
2814 (const_int 0)))]
2815 "")
2817 ;; Handle the PowerPC64 rlwinm corner case
2819 (define_insn_and_split "*andsi3_internal6"
2820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2821 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2822 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2823 "TARGET_POWERPC64"
2824 "#"
2825 "TARGET_POWERPC64"
2826 [(set (match_dup 0)
2827 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2828 (match_dup 4)))
2829 (set (match_dup 0)
2830 (rotate:SI (match_dup 0) (match_dup 5)))]
2831 "
2832 {
2833 int mb = extract_MB (operands[2]);
2834 int me = extract_ME (operands[2]);
2835 operands[3] = GEN_INT (me + 1);
2836 operands[5] = GEN_INT (32 - (me + 1));
2837 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2838 }"
2839 [(set_attr "length" "8")])
2841 (define_expand "iorsi3"
2842 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2843 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2844 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2845 ""
2846 "
2847 {
2848 if (GET_CODE (operands[2]) == CONST_INT
2849 && ! logical_operand (operands[2], SImode))
2850 {
2851 HOST_WIDE_INT value = INTVAL (operands[2]);
2852 rtx tmp = ((!can_create_pseudo_p ()
2853 || rtx_equal_p (operands[0], operands[1]))
2854 ? operands[0] : gen_reg_rtx (SImode));
2856 emit_insn (gen_iorsi3 (tmp, operands[1],
2857 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2858 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2859 DONE;
2860 }
2861 }")
2863 (define_expand "xorsi3"
2864 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2865 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2866 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2867 ""
2868 "
2869 {
2870 if (GET_CODE (operands[2]) == CONST_INT
2871 && ! logical_operand (operands[2], SImode))
2872 {
2873 HOST_WIDE_INT value = INTVAL (operands[2]);
2874 rtx tmp = ((!can_create_pseudo_p ()
2875 || rtx_equal_p (operands[0], operands[1]))
2876 ? operands[0] : gen_reg_rtx (SImode));
2878 emit_insn (gen_xorsi3 (tmp, operands[1],
2879 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2880 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2881 DONE;
2882 }
2883 }")
2885 (define_insn "*boolsi3_internal1"
2886 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2887 (match_operator:SI 3 "boolean_or_operator"
2888 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2889 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2890 ""
2891 "@
2892 %q3 %0,%1,%2
2893 %q3i %0,%1,%b2
2894 %q3is %0,%1,%u2")
2896 (define_insn "*boolsi3_internal2"
2897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2898 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2899 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2900 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2901 (const_int 0)))
2902 (clobber (match_scratch:SI 3 "=r,r"))]
2903 "TARGET_32BIT"
2904 "@
2905 %q4. %3,%1,%2
2906 #"
2907 [(set_attr "type" "fast_compare,compare")
2908 (set_attr "length" "4,8")])
2910 (define_split
2911 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2912 (compare:CC (match_operator:SI 4 "boolean_operator"
2913 [(match_operand:SI 1 "gpc_reg_operand" "")
2914 (match_operand:SI 2 "gpc_reg_operand" "")])
2915 (const_int 0)))
2916 (clobber (match_scratch:SI 3 ""))]
2917 "TARGET_32BIT && reload_completed"
2918 [(set (match_dup 3) (match_dup 4))
2919 (set (match_dup 0)
2920 (compare:CC (match_dup 3)
2921 (const_int 0)))]
2922 "")
2924 (define_insn "*boolsi3_internal3"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2926 (compare:CC (match_operator:SI 4 "boolean_operator"
2927 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2929 (const_int 0)))
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2931 (match_dup 4))]
2932 "TARGET_32BIT"
2933 "@
2934 %q4. %0,%1,%2
2935 #"
2936 [(set_attr "type" "fast_compare,compare")
2937 (set_attr "length" "4,8")])
2939 (define_split
2940 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2941 (compare:CC (match_operator:SI 4 "boolean_operator"
2942 [(match_operand:SI 1 "gpc_reg_operand" "")
2943 (match_operand:SI 2 "gpc_reg_operand" "")])
2944 (const_int 0)))
2945 (set (match_operand:SI 0 "gpc_reg_operand" "")
2946 (match_dup 4))]
2947 "TARGET_32BIT && reload_completed"
2948 [(set (match_dup 0) (match_dup 4))
2949 (set (match_dup 3)
2950 (compare:CC (match_dup 0)
2951 (const_int 0)))]
2952 "")
2954 ;; Split a logical operation that we can't do in one insn into two insns,
2955 ;; each of which does one 16-bit part. This is used by combine.
2957 (define_split
2958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2959 (match_operator:SI 3 "boolean_or_operator"
2960 [(match_operand:SI 1 "gpc_reg_operand" "")
2961 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2962 ""
2963 [(set (match_dup 0) (match_dup 4))
2964 (set (match_dup 0) (match_dup 5))]
2965 "
2966 {
2967 rtx i;
2968 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2969 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2970 operands[1], i);
2971 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2972 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2973 operands[0], i);
2974 }")
2976 (define_insn "*boolcsi3_internal1"
2977 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2978 (match_operator:SI 3 "boolean_operator"
2979 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2980 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2981 ""
2982 "%q3 %0,%2,%1")
2984 (define_insn "*boolcsi3_internal2"
2985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2986 (compare:CC (match_operator:SI 4 "boolean_operator"
2987 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2988 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2989 (const_int 0)))
2990 (clobber (match_scratch:SI 3 "=r,r"))]
2991 "TARGET_32BIT"
2992 "@
2993 %q4. %3,%2,%1
2994 #"
2995 [(set_attr "type" "compare")
2996 (set_attr "length" "4,8")])
2998 (define_split
2999 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3000 (compare:CC (match_operator:SI 4 "boolean_operator"
3001 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3002 (match_operand:SI 2 "gpc_reg_operand" "")])
3003 (const_int 0)))
3004 (clobber (match_scratch:SI 3 ""))]
3005 "TARGET_32BIT && reload_completed"
3006 [(set (match_dup 3) (match_dup 4))
3007 (set (match_dup 0)
3008 (compare:CC (match_dup 3)
3009 (const_int 0)))]
3010 "")
3012 (define_insn "*boolcsi3_internal3"
3013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3014 (compare:CC (match_operator:SI 4 "boolean_operator"
3015 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3016 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3017 (const_int 0)))
3018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3019 (match_dup 4))]
3020 "TARGET_32BIT"
3021 "@
3022 %q4. %0,%2,%1
3023 #"
3024 [(set_attr "type" "compare")
3025 (set_attr "length" "4,8")])
3027 (define_split
3028 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3029 (compare:CC (match_operator:SI 4 "boolean_operator"
3030 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3031 (match_operand:SI 2 "gpc_reg_operand" "")])
3032 (const_int 0)))
3033 (set (match_operand:SI 0 "gpc_reg_operand" "")
3034 (match_dup 4))]
3035 "TARGET_32BIT && reload_completed"
3036 [(set (match_dup 0) (match_dup 4))
3037 (set (match_dup 3)
3038 (compare:CC (match_dup 0)
3039 (const_int 0)))]
3040 "")
3042 (define_insn "*boolccsi3_internal1"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (match_operator:SI 3 "boolean_operator"
3045 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3046 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3047 ""
3048 "%q3 %0,%1,%2")
3050 (define_insn "*boolccsi3_internal2"
3051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3052 (compare:CC (match_operator:SI 4 "boolean_operator"
3053 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3054 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3055 (const_int 0)))
3056 (clobber (match_scratch:SI 3 "=r,r"))]
3057 "TARGET_32BIT"
3058 "@
3059 %q4. %3,%1,%2
3060 #"
3061 [(set_attr "type" "fast_compare,compare")
3062 (set_attr "length" "4,8")])
3064 (define_split
3065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3066 (compare:CC (match_operator:SI 4 "boolean_operator"
3067 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3068 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3069 (const_int 0)))
3070 (clobber (match_scratch:SI 3 ""))]
3071 "TARGET_32BIT && reload_completed"
3072 [(set (match_dup 3) (match_dup 4))
3073 (set (match_dup 0)
3074 (compare:CC (match_dup 3)
3075 (const_int 0)))]
3076 "")
3078 (define_insn "*boolccsi3_internal3"
3079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3080 (compare:CC (match_operator:SI 4 "boolean_operator"
3081 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3082 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3083 (const_int 0)))
3084 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3085 (match_dup 4))]
3086 "TARGET_32BIT"
3087 "@
3088 %q4. %0,%1,%2
3089 #"
3090 [(set_attr "type" "fast_compare,compare")
3091 (set_attr "length" "4,8")])
3093 (define_split
3094 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3097 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "")
3100 (match_dup 4))]
3101 "TARGET_32BIT && reload_completed"
3102 [(set (match_dup 0) (match_dup 4))
3103 (set (match_dup 3)
3104 (compare:CC (match_dup 0)
3105 (const_int 0)))]
3106 "")
3107 \f
3108 ;; Rotate and shift insns, in all their variants. These support shifts,
3109 ;; field inserts and extracts, and various combinations thereof.
3110 (define_expand "insv"
3111 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3112 (match_operand:SI 1 "const_int_operand" "")
3113 (match_operand:SI 2 "const_int_operand" ""))
3114 (match_operand 3 "gpc_reg_operand" ""))]
3115 ""
3116 "
3117 {
3118 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3119 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3120 compiler if the address of the structure is taken later. Likewise, do
3121 not handle invalid E500 subregs. */
3122 if (GET_CODE (operands[0]) == SUBREG
3123 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3124 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3125 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3126 FAIL;
3128 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3129 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3130 operands[3]));
3131 else
3132 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3133 operands[3]));
3134 DONE;
3135 }")
3137 (define_insn "insvsi_internal"
3138 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3139 (match_operand:SI 1 "const_int_operand" "i")
3140 (match_operand:SI 2 "const_int_operand" "i"))
3141 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3142 ""
3143 "*
3144 {
3145 int start = INTVAL (operands[2]) & 31;
3146 int size = INTVAL (operands[1]) & 31;
3148 operands[4] = GEN_INT (32 - start - size);
3149 operands[1] = GEN_INT (start + size - 1);
3150 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3151 }"
3152 [(set_attr "type" "insert_word")])
3154 (define_insn "*insvsi_internal1"
3155 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3156 (match_operand:SI 1 "const_int_operand" "i")
3157 (match_operand:SI 2 "const_int_operand" "i"))
3158 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3159 (match_operand:SI 4 "const_int_operand" "i")))]
3160 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3161 "*
3162 {
3163 int shift = INTVAL (operands[4]) & 31;
3164 int start = INTVAL (operands[2]) & 31;
3165 int size = INTVAL (operands[1]) & 31;
3167 operands[4] = GEN_INT (shift - start - size);
3168 operands[1] = GEN_INT (start + size - 1);
3169 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3170 }"
3171 [(set_attr "type" "insert_word")])
3173 (define_insn "*insvsi_internal2"
3174 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3175 (match_operand:SI 1 "const_int_operand" "i")
3176 (match_operand:SI 2 "const_int_operand" "i"))
3177 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3178 (match_operand:SI 4 "const_int_operand" "i")))]
3179 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3180 "*
3181 {
3182 int shift = INTVAL (operands[4]) & 31;
3183 int start = INTVAL (operands[2]) & 31;
3184 int size = INTVAL (operands[1]) & 31;
3186 operands[4] = GEN_INT (32 - shift - start - size);
3187 operands[1] = GEN_INT (start + size - 1);
3188 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3189 }"
3190 [(set_attr "type" "insert_word")])
3192 (define_insn "*insvsi_internal3"
3193 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3194 (match_operand:SI 1 "const_int_operand" "i")
3195 (match_operand:SI 2 "const_int_operand" "i"))
3196 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3197 (match_operand:SI 4 "const_int_operand" "i")))]
3198 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3199 "*
3200 {
3201 int shift = INTVAL (operands[4]) & 31;
3202 int start = INTVAL (operands[2]) & 31;
3203 int size = INTVAL (operands[1]) & 31;
3205 operands[4] = GEN_INT (32 - shift - start - size);
3206 operands[1] = GEN_INT (start + size - 1);
3207 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3208 }"
3209 [(set_attr "type" "insert_word")])
3211 (define_insn "*insvsi_internal4"
3212 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3213 (match_operand:SI 1 "const_int_operand" "i")
3214 (match_operand:SI 2 "const_int_operand" "i"))
3215 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3216 (match_operand:SI 4 "const_int_operand" "i")
3217 (match_operand:SI 5 "const_int_operand" "i")))]
3218 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3219 "*
3220 {
3221 int extract_start = INTVAL (operands[5]) & 31;
3222 int extract_size = INTVAL (operands[4]) & 31;
3223 int insert_start = INTVAL (operands[2]) & 31;
3224 int insert_size = INTVAL (operands[1]) & 31;
3226 /* Align extract field with insert field */
3227 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3228 operands[1] = GEN_INT (insert_start + insert_size - 1);
3229 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3230 }"
3231 [(set_attr "type" "insert_word")])
3233 ;; combine patterns for rlwimi
3234 (define_insn "*insvsi_internal5"
3235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3236 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3237 (match_operand:SI 1 "mask_operand" "i"))
3238 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3239 (match_operand:SI 2 "const_int_operand" "i"))
3240 (match_operand:SI 5 "mask_operand" "i"))))]
3241 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3242 "*
3243 {
3244 int me = extract_ME(operands[5]);
3245 int mb = extract_MB(operands[5]);
3246 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3247 operands[2] = GEN_INT(mb);
3248 operands[1] = GEN_INT(me);
3249 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3250 }"
3251 [(set_attr "type" "insert_word")])
3253 (define_insn "*insvsi_internal6"
3254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3255 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3256 (match_operand:SI 2 "const_int_operand" "i"))
3257 (match_operand:SI 5 "mask_operand" "i"))
3258 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3259 (match_operand:SI 1 "mask_operand" "i"))))]
3260 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3261 "*
3262 {
3263 int me = extract_ME(operands[5]);
3264 int mb = extract_MB(operands[5]);
3265 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3266 operands[2] = GEN_INT(mb);
3267 operands[1] = GEN_INT(me);
3268 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3269 }"
3270 [(set_attr "type" "insert_word")])
3272 (define_insn "insvdi_internal"
3273 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3274 (match_operand:SI 1 "const_int_operand" "i")
3275 (match_operand:SI 2 "const_int_operand" "i"))
3276 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3277 "TARGET_POWERPC64"
3278 "*
3279 {
3280 int start = INTVAL (operands[2]) & 63;
3281 int size = INTVAL (operands[1]) & 63;
3283 operands[1] = GEN_INT (64 - start - size);
3284 return \"rldimi %0,%3,%H1,%H2\";
3285 }"
3286 [(set_attr "type" "insert_dword")])
3288 (define_insn "*insvdi_internal2"
3289 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3290 (match_operand:SI 1 "const_int_operand" "i")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3293 (match_operand:SI 4 "const_int_operand" "i")))]
3294 "TARGET_POWERPC64
3295 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3296 "*
3297 {
3298 int shift = INTVAL (operands[4]) & 63;
3299 int start = (INTVAL (operands[2]) & 63) - 32;
3300 int size = INTVAL (operands[1]) & 63;
3302 operands[4] = GEN_INT (64 - shift - start - size);
3303 operands[2] = GEN_INT (start);
3304 operands[1] = GEN_INT (start + size - 1);
3305 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3306 }")
3308 (define_insn "*insvdi_internal3"
3309 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3310 (match_operand:SI 1 "const_int_operand" "i")
3311 (match_operand:SI 2 "const_int_operand" "i"))
3312 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3313 (match_operand:SI 4 "const_int_operand" "i")))]
3314 "TARGET_POWERPC64
3315 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3316 "*
3317 {
3318 int shift = INTVAL (operands[4]) & 63;
3319 int start = (INTVAL (operands[2]) & 63) - 32;
3320 int size = INTVAL (operands[1]) & 63;
3322 operands[4] = GEN_INT (64 - shift - start - size);
3323 operands[2] = GEN_INT (start);
3324 operands[1] = GEN_INT (start + size - 1);
3325 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3326 }")
3328 (define_expand "extzv"
3329 [(set (match_operand 0 "gpc_reg_operand" "")
3330 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3331 (match_operand:SI 2 "const_int_operand" "")
3332 (match_operand:SI 3 "const_int_operand" "")))]
3333 ""
3334 "
3335 {
3336 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3337 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3338 compiler if the address of the structure is taken later. */
3339 if (GET_CODE (operands[0]) == SUBREG
3340 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3341 FAIL;
3343 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3344 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3345 operands[3]));
3346 else
3347 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3348 operands[3]));
3349 DONE;
3350 }")
3352 (define_insn "extzvsi_internal"
3353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3354 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3355 (match_operand:SI 2 "const_int_operand" "i")
3356 (match_operand:SI 3 "const_int_operand" "i")))]
3357 ""
3358 "*
3359 {
3360 int start = INTVAL (operands[3]) & 31;
3361 int size = INTVAL (operands[2]) & 31;
3363 if (start + size >= 32)
3364 operands[3] = const0_rtx;
3365 else
3366 operands[3] = GEN_INT (start + size);
3367 return \"rlwinm %0,%1,%3,%s2,31\";
3368 }")
3370 (define_insn "*extzvsi_internal1"
3371 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3372 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3373 (match_operand:SI 2 "const_int_operand" "i,i")
3374 (match_operand:SI 3 "const_int_operand" "i,i"))
3375 (const_int 0)))
3376 (clobber (match_scratch:SI 4 "=r,r"))]
3377 ""
3378 "*
3379 {
3380 int start = INTVAL (operands[3]) & 31;
3381 int size = INTVAL (operands[2]) & 31;
3383 /* Force split for non-cc0 compare. */
3384 if (which_alternative == 1)
3385 return \"#\";
3387 /* If the bit-field being tested fits in the upper or lower half of a
3388 word, it is possible to use andiu. or andil. to test it. This is
3389 useful because the condition register set-use delay is smaller for
3390 andi[ul]. than for rlinm. This doesn't work when the starting bit
3391 position is 0 because the LT and GT bits may be set wrong. */
3393 if ((start > 0 && start + size <= 16) || start >= 16)
3394 {
3395 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3396 - (1 << (16 - (start & 15) - size))));
3397 if (start < 16)
3398 return \"andis. %4,%1,%3\";
3399 else
3400 return \"andi. %4,%1,%3\";
3401 }
3403 if (start + size >= 32)
3404 operands[3] = const0_rtx;
3405 else
3406 operands[3] = GEN_INT (start + size);
3407 return \"rlwinm. %4,%1,%3,%s2,31\";
3408 }"
3409 [(set_attr "type" "delayed_compare")
3410 (set_attr "length" "4,8")])
3412 (define_split
3413 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3414 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3415 (match_operand:SI 2 "const_int_operand" "")
3416 (match_operand:SI 3 "const_int_operand" ""))
3417 (const_int 0)))
3418 (clobber (match_scratch:SI 4 ""))]
3419 "reload_completed"
3420 [(set (match_dup 4)
3421 (zero_extract:SI (match_dup 1) (match_dup 2)
3422 (match_dup 3)))
3423 (set (match_dup 0)
3424 (compare:CC (match_dup 4)
3425 (const_int 0)))]
3426 "")
3428 (define_insn "*extzvsi_internal2"
3429 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3430 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3431 (match_operand:SI 2 "const_int_operand" "i,i")
3432 (match_operand:SI 3 "const_int_operand" "i,i"))
3433 (const_int 0)))
3434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3435 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3436 ""
3437 "*
3438 {
3439 int start = INTVAL (operands[3]) & 31;
3440 int size = INTVAL (operands[2]) & 31;
3442 /* Force split for non-cc0 compare. */
3443 if (which_alternative == 1)
3444 return \"#\";
3446 /* Since we are using the output value, we can't ignore any need for
3447 a shift. The bit-field must end at the LSB. */
3448 if (start >= 16 && start + size == 32)
3449 {
3450 operands[3] = GEN_INT ((1 << size) - 1);
3451 return \"andi. %0,%1,%3\";
3452 }
3454 if (start + size >= 32)
3455 operands[3] = const0_rtx;
3456 else
3457 operands[3] = GEN_INT (start + size);
3458 return \"rlwinm. %0,%1,%3,%s2,31\";
3459 }"
3460 [(set_attr "type" "delayed_compare")
3461 (set_attr "length" "4,8")])
3463 (define_split
3464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3465 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3466 (match_operand:SI 2 "const_int_operand" "")
3467 (match_operand:SI 3 "const_int_operand" ""))
3468 (const_int 0)))
3469 (set (match_operand:SI 0 "gpc_reg_operand" "")
3470 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3471 "reload_completed"
3472 [(set (match_dup 0)
3473 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3474 (set (match_dup 4)
3475 (compare:CC (match_dup 0)
3476 (const_int 0)))]
3477 "")
3479 (define_insn "extzvdi_internal"
3480 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3481 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3482 (match_operand:SI 2 "const_int_operand" "i")
3483 (match_operand:SI 3 "const_int_operand" "i")))]
3484 "TARGET_POWERPC64"
3485 "*
3486 {
3487 int start = INTVAL (operands[3]) & 63;
3488 int size = INTVAL (operands[2]) & 63;
3490 if (start + size >= 64)
3491 operands[3] = const0_rtx;
3492 else
3493 operands[3] = GEN_INT (start + size);
3494 operands[2] = GEN_INT (64 - size);
3495 return \"rldicl %0,%1,%3,%2\";
3496 }")
3498 (define_insn "*extzvdi_internal1"
3499 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3500 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3501 (match_operand:SI 2 "const_int_operand" "i")
3502 (match_operand:SI 3 "const_int_operand" "i"))
3503 (const_int 0)))
3504 (clobber (match_scratch:DI 4 "=r"))]
3505 "TARGET_64BIT && rs6000_gen_cell_microcode"
3506 "*
3507 {
3508 int start = INTVAL (operands[3]) & 63;
3509 int size = INTVAL (operands[2]) & 63;
3511 if (start + size >= 64)
3512 operands[3] = const0_rtx;
3513 else
3514 operands[3] = GEN_INT (start + size);
3515 operands[2] = GEN_INT (64 - size);
3516 return \"rldicl. %4,%1,%3,%2\";
3517 }"
3518 [(set_attr "type" "compare")])
3520 (define_insn "*extzvdi_internal2"
3521 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3522 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3523 (match_operand:SI 2 "const_int_operand" "i")
3524 (match_operand:SI 3 "const_int_operand" "i"))
3525 (const_int 0)))
3526 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3527 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3528 "TARGET_64BIT && rs6000_gen_cell_microcode"
3529 "*
3530 {
3531 int start = INTVAL (operands[3]) & 63;
3532 int size = INTVAL (operands[2]) & 63;
3534 if (start + size >= 64)
3535 operands[3] = const0_rtx;
3536 else
3537 operands[3] = GEN_INT (start + size);
3538 operands[2] = GEN_INT (64 - size);
3539 return \"rldicl. %0,%1,%3,%2\";
3540 }"
3541 [(set_attr "type" "compare")])
3543 (define_insn "rotlsi3"
3544 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3545 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3546 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3547 ""
3548 "@
3549 rlwnm %0,%1,%2,0xffffffff
3550 rlwinm %0,%1,%h2,0xffffffff"
3551 [(set_attr "type" "var_shift_rotate,integer")])
3553 (define_insn "*rotlsi3_64"
3554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3555 (zero_extend:DI
3556 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3557 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3558 "TARGET_64BIT"
3559 "@
3560 rlwnm %0,%1,%2,0xffffffff
3561 rlwinm %0,%1,%h2,0xffffffff"
3562 [(set_attr "type" "var_shift_rotate,integer")])
3564 (define_insn "*rotlsi3_internal2"
3565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3566 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3567 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3568 (const_int 0)))
3569 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3570 ""
3571 "@
3572 rlwnm. %3,%1,%2,0xffffffff
3573 rlwinm. %3,%1,%h2,0xffffffff
3574 #
3575 #"
3576 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3577 (set_attr "length" "4,4,8,8")])
3579 (define_split
3580 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3581 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3582 (match_operand:SI 2 "reg_or_cint_operand" ""))
3583 (const_int 0)))
3584 (clobber (match_scratch:SI 3 ""))]
3585 "reload_completed"
3586 [(set (match_dup 3)
3587 (rotate:SI (match_dup 1) (match_dup 2)))
3588 (set (match_dup 0)
3589 (compare:CC (match_dup 3)
3590 (const_int 0)))]
3591 "")
3593 (define_insn "*rotlsi3_internal3"
3594 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3595 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3596 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3597 (const_int 0)))
3598 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3599 (rotate:SI (match_dup 1) (match_dup 2)))]
3600 ""
3601 "@
3602 rlwnm. %0,%1,%2,0xffffffff
3603 rlwinm. %0,%1,%h2,0xffffffff
3604 #
3605 #"
3606 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3607 (set_attr "length" "4,4,8,8")])
3609 (define_split
3610 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3611 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3612 (match_operand:SI 2 "reg_or_cint_operand" ""))
3613 (const_int 0)))
3614 (set (match_operand:SI 0 "gpc_reg_operand" "")
3615 (rotate:SI (match_dup 1) (match_dup 2)))]
3616 "reload_completed"
3617 [(set (match_dup 0)
3618 (rotate:SI (match_dup 1) (match_dup 2)))
3619 (set (match_dup 3)
3620 (compare:CC (match_dup 0)
3621 (const_int 0)))]
3622 "")
3624 (define_insn "*rotlsi3_internal4"
3625 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3626 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3627 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3628 (match_operand:SI 3 "mask_operand" "n,n")))]
3629 ""
3630 "@
3631 rlwnm %0,%1,%2,%m3,%M3
3632 rlwinm %0,%1,%h2,%m3,%M3"
3633 [(set_attr "type" "var_shift_rotate,integer")])
3635 (define_insn "*rotlsi3_internal5"
3636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3637 (compare:CC (and:SI
3638 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3639 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3640 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3641 (const_int 0)))
3642 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3643 ""
3644 "@
3645 rlwnm. %4,%1,%2,%m3,%M3
3646 rlwinm. %4,%1,%h2,%m3,%M3
3647 #
3648 #"
3649 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3650 (set_attr "length" "4,4,8,8")])
3652 (define_split
3653 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3654 (compare:CC (and:SI
3655 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3656 (match_operand:SI 2 "reg_or_cint_operand" ""))
3657 (match_operand:SI 3 "mask_operand" ""))
3658 (const_int 0)))
3659 (clobber (match_scratch:SI 4 ""))]
3660 "reload_completed"
3661 [(set (match_dup 4)
3662 (and:SI (rotate:SI (match_dup 1)
3663 (match_dup 2))
3664 (match_dup 3)))
3665 (set (match_dup 0)
3666 (compare:CC (match_dup 4)
3667 (const_int 0)))]
3668 "")
3670 (define_insn "*rotlsi3_internal6"
3671 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3672 (compare:CC (and:SI
3673 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3674 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3675 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3676 (const_int 0)))
3677 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3678 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3679 ""
3680 "@
3681 rlwnm. %0,%1,%2,%m3,%M3
3682 rlwinm. %0,%1,%h2,%m3,%M3
3683 #
3684 #"
3685 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3686 (set_attr "length" "4,4,8,8")])
3688 (define_split
3689 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3690 (compare:CC (and:SI
3691 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "reg_or_cint_operand" ""))
3693 (match_operand:SI 3 "mask_operand" ""))
3694 (const_int 0)))
3695 (set (match_operand:SI 0 "gpc_reg_operand" "")
3696 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3697 "reload_completed"
3698 [(set (match_dup 0)
3699 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3700 (set (match_dup 4)
3701 (compare:CC (match_dup 0)
3702 (const_int 0)))]
3703 "")
3705 (define_insn "*rotlsi3_internal7"
3706 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3707 (zero_extend:SI
3708 (subreg:QI
3709 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3710 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3711 ""
3712 "rlw%I2nm %0,%1,%h2,0xff"
3713 [(set (attr "cell_micro")
3714 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3715 (const_string "not")
3716 (const_string "always")))])
3718 (define_insn "*rotlsi3_internal8"
3719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3720 (compare:CC (zero_extend:SI
3721 (subreg:QI
3722 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3723 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3724 (const_int 0)))
3725 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3726 ""
3727 "@
3728 rlwnm. %3,%1,%2,0xff
3729 rlwinm. %3,%1,%h2,0xff
3730 #
3731 #"
3732 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3733 (set_attr "length" "4,4,8,8")])
3735 (define_split
3736 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3737 (compare:CC (zero_extend:SI
3738 (subreg:QI
3739 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3740 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3741 (const_int 0)))
3742 (clobber (match_scratch:SI 3 ""))]
3743 "reload_completed"
3744 [(set (match_dup 3)
3745 (zero_extend:SI (subreg:QI
3746 (rotate:SI (match_dup 1)
3747 (match_dup 2)) 0)))
3748 (set (match_dup 0)
3749 (compare:CC (match_dup 3)
3750 (const_int 0)))]
3751 "")
3753 (define_insn "*rotlsi3_internal9"
3754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3755 (compare:CC (zero_extend:SI
3756 (subreg:QI
3757 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3758 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3759 (const_int 0)))
3760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3761 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3762 ""
3763 "@
3764 rlwnm. %0,%1,%2,0xff
3765 rlwinm. %0,%1,%h2,0xff
3766 #
3767 #"
3768 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3769 (set_attr "length" "4,4,8,8")])
3771 (define_split
3772 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3773 (compare:CC (zero_extend:SI
3774 (subreg:QI
3775 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3776 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3777 (const_int 0)))
3778 (set (match_operand:SI 0 "gpc_reg_operand" "")
3779 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3780 "reload_completed"
3781 [(set (match_dup 0)
3782 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3783 (set (match_dup 3)
3784 (compare:CC (match_dup 0)
3785 (const_int 0)))]
3786 "")
3788 (define_insn "*rotlsi3_internal10"
3789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3790 (zero_extend:SI
3791 (subreg:HI
3792 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3793 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
3794 ""
3795 "@
3796 rlwnm %0,%1,%2,0xffff
3797 rlwinm %0,%1,%h2,0xffff"
3798 [(set_attr "type" "var_shift_rotate,integer")])
3801 (define_insn "*rotlsi3_internal11"
3802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3803 (compare:CC (zero_extend:SI
3804 (subreg:HI
3805 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3806 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3807 (const_int 0)))
3808 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3809 ""
3810 "@
3811 rlwnm. %3,%1,%2,0xffff
3812 rlwinm. %3,%1,%h2,0xffff
3813 #
3814 #"
3815 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3816 (set_attr "length" "4,4,8,8")])
3818 (define_split
3819 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3820 (compare:CC (zero_extend:SI
3821 (subreg:HI
3822 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3824 (const_int 0)))
3825 (clobber (match_scratch:SI 3 ""))]
3826 "reload_completed"
3827 [(set (match_dup 3)
3828 (zero_extend:SI (subreg:HI
3829 (rotate:SI (match_dup 1)
3830 (match_dup 2)) 0)))
3831 (set (match_dup 0)
3832 (compare:CC (match_dup 3)
3833 (const_int 0)))]
3834 "")
3836 (define_insn "*rotlsi3_internal12"
3837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3838 (compare:CC (zero_extend:SI
3839 (subreg:HI
3840 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3841 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
3842 (const_int 0)))
3843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3844 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3845 ""
3846 "@
3847 rlwnm. %0,%1,%2,0xffff
3848 rlwinm. %0,%1,%h2,0xffff
3849 #
3850 #"
3851 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3852 (set_attr "length" "4,4,8,8")])
3854 (define_split
3855 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3856 (compare:CC (zero_extend:SI
3857 (subreg:HI
3858 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3859 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3860 (const_int 0)))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "")
3862 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3863 "reload_completed"
3864 [(set (match_dup 0)
3865 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3866 (set (match_dup 3)
3867 (compare:CC (match_dup 0)
3868 (const_int 0)))]
3869 "")
3871 (define_insn "ashlsi3"
3872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3873 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3874 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3875 ""
3876 "@
3877 slw %0,%1,%2
3878 slwi %0,%1,%h2"
3879 [(set_attr "type" "var_shift_rotate,shift")])
3881 (define_insn "*ashlsi3_64"
3882 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3883 (zero_extend:DI
3884 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3885 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3886 "TARGET_POWERPC64"
3887 "@
3888 slw %0,%1,%2
3889 slwi %0,%1,%h2"
3890 [(set_attr "type" "var_shift_rotate,shift")])
3892 (define_insn ""
3893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3894 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3895 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3896 (const_int 0)))
3897 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3898 "TARGET_32BIT"
3899 "@
3900 slw. %3,%1,%2
3901 slwi. %3,%1,%h2
3902 #
3903 #"
3904 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3905 (set_attr "length" "4,4,8,8")])
3907 (define_split
3908 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3909 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3910 (match_operand:SI 2 "reg_or_cint_operand" ""))
3911 (const_int 0)))
3912 (clobber (match_scratch:SI 3 ""))]
3913 "TARGET_32BIT && reload_completed"
3914 [(set (match_dup 3)
3915 (ashift:SI (match_dup 1) (match_dup 2)))
3916 (set (match_dup 0)
3917 (compare:CC (match_dup 3)
3918 (const_int 0)))]
3919 "")
3921 (define_insn ""
3922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3923 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3924 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3925 (const_int 0)))
3926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3927 (ashift:SI (match_dup 1) (match_dup 2)))]
3928 "TARGET_32BIT"
3929 "@
3930 slw. %0,%1,%2
3931 slwi. %0,%1,%h2
3932 #
3933 #"
3934 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3935 (set_attr "length" "4,4,8,8")])
3937 (define_split
3938 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3939 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3940 (match_operand:SI 2 "reg_or_cint_operand" ""))
3941 (const_int 0)))
3942 (set (match_operand:SI 0 "gpc_reg_operand" "")
3943 (ashift:SI (match_dup 1) (match_dup 2)))]
3944 "TARGET_32BIT && reload_completed"
3945 [(set (match_dup 0)
3946 (ashift:SI (match_dup 1) (match_dup 2)))
3947 (set (match_dup 3)
3948 (compare:CC (match_dup 0)
3949 (const_int 0)))]
3950 "")
3952 (define_insn "rlwinm"
3953 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3954 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3955 (match_operand:SI 2 "const_int_operand" "i"))
3956 (match_operand:SI 3 "mask_operand" "n")))]
3957 "includes_lshift_p (operands[2], operands[3])"
3958 "rlwinm %0,%1,%h2,%m3,%M3")
3960 (define_insn ""
3961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3962 (compare:CC
3963 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3964 (match_operand:SI 2 "const_int_operand" "i,i"))
3965 (match_operand:SI 3 "mask_operand" "n,n"))
3966 (const_int 0)))
3967 (clobber (match_scratch:SI 4 "=r,r"))]
3968 "includes_lshift_p (operands[2], operands[3])"
3969 "@
3970 rlwinm. %4,%1,%h2,%m3,%M3
3971 #"
3972 [(set_attr "type" "delayed_compare")
3973 (set_attr "length" "4,8")])
3975 (define_split
3976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3977 (compare:CC
3978 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3979 (match_operand:SI 2 "const_int_operand" ""))
3980 (match_operand:SI 3 "mask_operand" ""))
3981 (const_int 0)))
3982 (clobber (match_scratch:SI 4 ""))]
3983 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
3984 [(set (match_dup 4)
3985 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3986 (match_dup 3)))
3987 (set (match_dup 0)
3988 (compare:CC (match_dup 4)
3989 (const_int 0)))]
3990 "")
3992 (define_insn ""
3993 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3994 (compare:CC
3995 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3996 (match_operand:SI 2 "const_int_operand" "i,i"))
3997 (match_operand:SI 3 "mask_operand" "n,n"))
3998 (const_int 0)))
3999 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4000 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4001 "includes_lshift_p (operands[2], operands[3])"
4002 "@
4003 rlwinm. %0,%1,%h2,%m3,%M3
4004 #"
4005 [(set_attr "type" "delayed_compare")
4006 (set_attr "length" "4,8")])
4008 (define_split
4009 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4010 (compare:CC
4011 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4012 (match_operand:SI 2 "const_int_operand" ""))
4013 (match_operand:SI 3 "mask_operand" ""))
4014 (const_int 0)))
4015 (set (match_operand:SI 0 "gpc_reg_operand" "")
4016 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4017 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4018 [(set (match_dup 0)
4019 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4020 (set (match_dup 4)
4021 (compare:CC (match_dup 0)
4022 (const_int 0)))]
4023 "")
4025 (define_insn "lshrsi3"
4026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4027 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4028 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4029 ""
4030 "@
4031 mr %0,%1
4032 srw %0,%1,%2
4033 srwi %0,%1,%h2"
4034 [(set_attr "type" "integer,var_shift_rotate,shift")])
4036 (define_insn "*lshrsi3_64"
4037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4038 (zero_extend:DI
4039 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4040 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4041 "TARGET_POWERPC64"
4042 "@
4043 srw %0,%1,%2
4044 srwi %0,%1,%h2"
4045 [(set_attr "type" "var_shift_rotate,shift")])
4047 (define_insn ""
4048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4049 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4050 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4051 (const_int 0)))
4052 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4053 "TARGET_32BIT"
4054 "@
4055 mr. %1,%1
4056 srw. %3,%1,%2
4057 srwi. %3,%1,%h2
4058 #
4059 #
4060 #"
4061 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4062 (set_attr "length" "4,4,4,8,8,8")])
4064 (define_split
4065 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4066 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4067 (match_operand:SI 2 "reg_or_cint_operand" ""))
4068 (const_int 0)))
4069 (clobber (match_scratch:SI 3 ""))]
4070 "TARGET_32BIT && reload_completed"
4071 [(set (match_dup 3)
4072 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4073 (set (match_dup 0)
4074 (compare:CC (match_dup 3)
4075 (const_int 0)))]
4076 "")
4078 (define_insn ""
4079 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4080 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4081 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4082 (const_int 0)))
4083 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4084 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4085 "TARGET_32BIT"
4086 "@
4087 mr. %0,%1
4088 srw. %0,%1,%2
4089 srwi. %0,%1,%h2
4090 #
4091 #
4092 #"
4093 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4094 (set_attr "length" "4,4,4,8,8,8")])
4096 (define_split
4097 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4098 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4099 (match_operand:SI 2 "reg_or_cint_operand" ""))
4100 (const_int 0)))
4101 (set (match_operand:SI 0 "gpc_reg_operand" "")
4102 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4103 "TARGET_32BIT && reload_completed"
4104 [(set (match_dup 0)
4105 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4106 (set (match_dup 3)
4107 (compare:CC (match_dup 0)
4108 (const_int 0)))]
4109 "")
4111 (define_insn ""
4112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4113 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4114 (match_operand:SI 2 "const_int_operand" "i"))
4115 (match_operand:SI 3 "mask_operand" "n")))]
4116 "includes_rshift_p (operands[2], operands[3])"
4117 "rlwinm %0,%1,%s2,%m3,%M3")
4119 (define_insn ""
4120 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4121 (compare:CC
4122 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4123 (match_operand:SI 2 "const_int_operand" "i,i"))
4124 (match_operand:SI 3 "mask_operand" "n,n"))
4125 (const_int 0)))
4126 (clobber (match_scratch:SI 4 "=r,r"))]
4127 "includes_rshift_p (operands[2], operands[3])"
4128 "@
4129 rlwinm. %4,%1,%s2,%m3,%M3
4130 #"
4131 [(set_attr "type" "delayed_compare")
4132 (set_attr "length" "4,8")])
4134 (define_split
4135 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4136 (compare:CC
4137 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4138 (match_operand:SI 2 "const_int_operand" ""))
4139 (match_operand:SI 3 "mask_operand" ""))
4140 (const_int 0)))
4141 (clobber (match_scratch:SI 4 ""))]
4142 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4143 [(set (match_dup 4)
4144 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4145 (match_dup 3)))
4146 (set (match_dup 0)
4147 (compare:CC (match_dup 4)
4148 (const_int 0)))]
4149 "")
4151 (define_insn ""
4152 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4153 (compare:CC
4154 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4155 (match_operand:SI 2 "const_int_operand" "i,i"))
4156 (match_operand:SI 3 "mask_operand" "n,n"))
4157 (const_int 0)))
4158 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4159 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4160 "includes_rshift_p (operands[2], operands[3])"
4161 "@
4162 rlwinm. %0,%1,%s2,%m3,%M3
4163 #"
4164 [(set_attr "type" "delayed_compare")
4165 (set_attr "length" "4,8")])
4167 (define_split
4168 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4169 (compare:CC
4170 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4171 (match_operand:SI 2 "const_int_operand" ""))
4172 (match_operand:SI 3 "mask_operand" ""))
4173 (const_int 0)))
4174 (set (match_operand:SI 0 "gpc_reg_operand" "")
4175 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4176 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4177 [(set (match_dup 0)
4178 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4179 (set (match_dup 4)
4180 (compare:CC (match_dup 0)
4181 (const_int 0)))]
4182 "")
4184 (define_insn ""
4185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4186 (zero_extend:SI
4187 (subreg:QI
4188 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4189 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4190 "includes_rshift_p (operands[2], GEN_INT (255))"
4191 "rlwinm %0,%1,%s2,0xff")
4193 (define_insn ""
4194 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4195 (compare:CC
4196 (zero_extend:SI
4197 (subreg:QI
4198 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4199 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4200 (const_int 0)))
4201 (clobber (match_scratch:SI 3 "=r,r"))]
4202 "includes_rshift_p (operands[2], GEN_INT (255))"
4203 "@
4204 rlwinm. %3,%1,%s2,0xff
4205 #"
4206 [(set_attr "type" "delayed_compare")
4207 (set_attr "length" "4,8")])
4209 (define_split
4210 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4211 (compare:CC
4212 (zero_extend:SI
4213 (subreg:QI
4214 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4215 (match_operand:SI 2 "const_int_operand" "")) 0))
4216 (const_int 0)))
4217 (clobber (match_scratch:SI 3 ""))]
4218 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4219 [(set (match_dup 3)
4220 (zero_extend:SI (subreg:QI
4221 (lshiftrt:SI (match_dup 1)
4222 (match_dup 2)) 0)))
4223 (set (match_dup 0)
4224 (compare:CC (match_dup 3)
4225 (const_int 0)))]
4226 "")
4228 (define_insn ""
4229 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4230 (compare:CC
4231 (zero_extend:SI
4232 (subreg:QI
4233 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4234 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4235 (const_int 0)))
4236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4237 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4238 "includes_rshift_p (operands[2], GEN_INT (255))"
4239 "@
4240 rlwinm. %0,%1,%s2,0xff
4241 #"
4242 [(set_attr "type" "delayed_compare")
4243 (set_attr "length" "4,8")])
4245 (define_split
4246 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4247 (compare:CC
4248 (zero_extend:SI
4249 (subreg:QI
4250 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4251 (match_operand:SI 2 "const_int_operand" "")) 0))
4252 (const_int 0)))
4253 (set (match_operand:SI 0 "gpc_reg_operand" "")
4254 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4255 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4256 [(set (match_dup 0)
4257 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4258 (set (match_dup 3)
4259 (compare:CC (match_dup 0)
4260 (const_int 0)))]
4261 "")
4263 (define_insn ""
4264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4265 (zero_extend:SI
4266 (subreg:HI
4267 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4268 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4269 "includes_rshift_p (operands[2], GEN_INT (65535))"
4270 "rlwinm %0,%1,%s2,0xffff")
4272 (define_insn ""
4273 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4274 (compare:CC
4275 (zero_extend:SI
4276 (subreg:HI
4277 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4278 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4279 (const_int 0)))
4280 (clobber (match_scratch:SI 3 "=r,r"))]
4281 "includes_rshift_p (operands[2], GEN_INT (65535))"
4282 "@
4283 rlwinm. %3,%1,%s2,0xffff
4284 #"
4285 [(set_attr "type" "delayed_compare")
4286 (set_attr "length" "4,8")])
4288 (define_split
4289 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4290 (compare:CC
4291 (zero_extend:SI
4292 (subreg:HI
4293 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4294 (match_operand:SI 2 "const_int_operand" "")) 0))
4295 (const_int 0)))
4296 (clobber (match_scratch:SI 3 ""))]
4297 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4298 [(set (match_dup 3)
4299 (zero_extend:SI (subreg:HI
4300 (lshiftrt:SI (match_dup 1)
4301 (match_dup 2)) 0)))
4302 (set (match_dup 0)
4303 (compare:CC (match_dup 3)
4304 (const_int 0)))]
4305 "")
4307 (define_insn ""
4308 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4309 (compare:CC
4310 (zero_extend:SI
4311 (subreg:HI
4312 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4313 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4314 (const_int 0)))
4315 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4316 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4317 "includes_rshift_p (operands[2], GEN_INT (65535))"
4318 "@
4319 rlwinm. %0,%1,%s2,0xffff
4320 #"
4321 [(set_attr "type" "delayed_compare")
4322 (set_attr "length" "4,8")])
4324 (define_split
4325 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4326 (compare:CC
4327 (zero_extend:SI
4328 (subreg:HI
4329 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4330 (match_operand:SI 2 "const_int_operand" "")) 0))
4331 (const_int 0)))
4332 (set (match_operand:SI 0 "gpc_reg_operand" "")
4333 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4334 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4335 [(set (match_dup 0)
4336 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4337 (set (match_dup 3)
4338 (compare:CC (match_dup 0)
4339 (const_int 0)))]
4340 "")
4342 (define_insn "ashrsi3"
4343 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4344 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4345 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4346 ""
4347 "@
4348 sraw %0,%1,%2
4349 srawi %0,%1,%h2"
4350 [(set_attr "type" "var_shift_rotate,shift")])
4352 (define_insn "*ashrsi3_64"
4353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4354 (sign_extend:DI
4355 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4357 "TARGET_POWERPC64"
4358 "@
4359 sraw %0,%1,%2
4360 srawi %0,%1,%h2"
4361 [(set_attr "type" "var_shift_rotate,shift")])
4363 (define_insn ""
4364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4365 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4367 (const_int 0)))
4368 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4369 ""
4370 "@
4371 sraw. %3,%1,%2
4372 srawi. %3,%1,%h2
4373 #
4374 #"
4375 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4376 (set_attr "length" "4,4,8,8")])
4378 (define_split
4379 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4380 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 3 ""))]
4384 "reload_completed"
4385 [(set (match_dup 3)
4386 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4387 (set (match_dup 0)
4388 (compare:CC (match_dup 3)
4389 (const_int 0)))]
4390 "")
4392 (define_insn ""
4393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4394 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4395 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4396 (const_int 0)))
4397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4398 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4399 ""
4400 "@
4401 sraw. %0,%1,%2
4402 srawi. %0,%1,%h2
4403 #
4404 #"
4405 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4406 (set_attr "length" "4,4,8,8")])
4407 \f
4408 ;; Builtins to replace a division to generate FRE reciprocal estimate
4409 ;; instructions and the necessary fixup instructions
4410 (define_expand "recip<mode>3"
4411 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4412 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4413 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4414 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4415 {
4416 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4417 DONE;
4418 })
4420 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4421 ;; hardware division. This is only done before register allocation and with
4422 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4423 (define_split
4424 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4425 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4426 (match_operand 2 "gpc_reg_operand" "")))]
4427 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4428 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4429 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4430 [(const_int 0)]
4431 {
4432 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4433 DONE;
4434 })
4436 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4437 ;; appropriate fixup.
4438 (define_expand "rsqrt<mode>2"
4439 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4440 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4441 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4442 {
4443 rs6000_emit_swrsqrt (operands[0], operands[1]);
4444 DONE;
4445 })
4446 \f
4447 (define_split
4448 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4449 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4450 (match_operand:SI 2 "reg_or_cint_operand" ""))
4451 (const_int 0)))
4452 (set (match_operand:SI 0 "gpc_reg_operand" "")
4453 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4454 "reload_completed"
4455 [(set (match_dup 0)
4456 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4457 (set (match_dup 3)
4458 (compare:CC (match_dup 0)
4459 (const_int 0)))]
4460 "")
4462 ;; Floating-point insns, excluding normal data motion.
4463 ;;
4464 ;; PowerPC has a full set of single-precision floating point instructions.
4465 ;;
4466 ;; For the POWER architecture, we pretend that we have both SFmode and
4467 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4468 ;; The only conversions we will do will be when storing to memory. In that
4469 ;; case, we will use the "frsp" instruction before storing.
4470 ;;
4471 ;; Note that when we store into a single-precision memory location, we need to
4472 ;; use the frsp insn first. If the register being stored isn't dead, we
4473 ;; need a scratch register for the frsp. But this is difficult when the store
4474 ;; is done by reload. It is not incorrect to do the frsp on the register in
4475 ;; this case, we just lose precision that we would have otherwise gotten but
4476 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4478 (define_expand "extendsfdf2"
4479 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4480 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4481 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4482 "")
4484 (define_insn_and_split "*extendsfdf2_fpr"
4485 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4486 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4487 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4488 "@
4489 #
4490 fmr %0,%1
4491 lfs%U1%X1 %0,%1"
4492 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4493 [(const_int 0)]
4494 {
4495 emit_note (NOTE_INSN_DELETED);
4496 DONE;
4497 }
4498 [(set_attr "type" "fp,fp,fpload")])
4500 (define_expand "truncdfsf2"
4501 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4502 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4503 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4504 "")
4506 (define_insn "*truncdfsf2_fpr"
4507 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4508 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4509 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4510 "frsp %0,%1"
4511 [(set_attr "type" "fp")])
4513 (define_expand "negsf2"
4514 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4515 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4516 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4517 "")
4519 (define_insn "*negsf2"
4520 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4521 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4522 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4523 "fneg %0,%1"
4524 [(set_attr "type" "fp")])
4526 (define_expand "abssf2"
4527 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4528 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4529 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4530 "")
4532 (define_insn "*abssf2"
4533 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4534 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4535 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4536 "fabs %0,%1"
4537 [(set_attr "type" "fp")])
4539 (define_insn ""
4540 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4541 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4543 "fnabs %0,%1"
4544 [(set_attr "type" "fp")])
4546 (define_expand "addsf3"
4547 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4548 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4549 (match_operand:SF 2 "gpc_reg_operand" "")))]
4550 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4551 "")
4553 (define_insn ""
4554 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4555 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4556 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4557 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4558 "fadds %0,%1,%2"
4559 [(set_attr "type" "fp")
4560 (set_attr "fp_type" "fp_addsub_s")])
4562 (define_expand "subsf3"
4563 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4564 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4565 (match_operand:SF 2 "gpc_reg_operand" "")))]
4566 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4567 "")
4569 (define_insn ""
4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4573 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4574 "fsubs %0,%1,%2"
4575 [(set_attr "type" "fp")
4576 (set_attr "fp_type" "fp_addsub_s")])
4578 (define_expand "mulsf3"
4579 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4580 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4581 (match_operand:SF 2 "gpc_reg_operand" "")))]
4582 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4583 "")
4585 (define_insn ""
4586 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4587 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4588 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4589 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4590 "fmuls %0,%1,%2"
4591 [(set_attr "type" "fp")
4592 (set_attr "fp_type" "fp_mul_s")])
4594 (define_expand "divsf3"
4595 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4596 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4597 (match_operand:SF 2 "gpc_reg_operand" "")))]
4598 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4599 "")
4601 (define_insn ""
4602 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4603 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4604 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4605 "TARGET_HARD_FLOAT && TARGET_FPRS
4606 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4607 "fdivs %0,%1,%2"
4608 [(set_attr "type" "sdiv")])
4610 (define_insn "fres"
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4613 "TARGET_FRES"
4614 "fres %0,%1"
4615 [(set_attr "type" "fp")])
4617 ; builtin fmaf support
4618 (define_insn "*fmasf4_fpr"
4619 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4620 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4621 (match_operand:SF 2 "gpc_reg_operand" "f")
4622 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4623 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4624 "fmadds %0,%1,%2,%3"
4625 [(set_attr "type" "fp")
4626 (set_attr "fp_type" "fp_maddsub_s")])
4628 (define_insn "*fmssf4_fpr"
4629 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4630 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4631 (match_operand:SF 2 "gpc_reg_operand" "f")
4632 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4633 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4634 "fmsubs %0,%1,%2,%3"
4635 [(set_attr "type" "fp")
4636 (set_attr "fp_type" "fp_maddsub_s")])
4638 (define_insn "*nfmasf4_fpr"
4639 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4640 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4641 (match_operand:SF 2 "gpc_reg_operand" "f")
4642 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4643 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4644 "fnmadds %0,%1,%2,%3"
4645 [(set_attr "type" "fp")
4646 (set_attr "fp_type" "fp_maddsub_s")])
4648 (define_insn "*nfmssf4_fpr"
4649 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4650 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4651 (match_operand:SF 2 "gpc_reg_operand" "f")
4652 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
4653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4654 "fnmsubs %0,%1,%2,%3"
4655 [(set_attr "type" "fp")
4656 (set_attr "fp_type" "fp_maddsub_s")])
4658 (define_expand "sqrtsf2"
4659 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4660 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4661 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
4662 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
4663 && !TARGET_SIMPLE_FPU"
4664 "")
4666 (define_insn ""
4667 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4668 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4669 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
4670 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
4671 "fsqrts %0,%1"
4672 [(set_attr "type" "ssqrt")])
4674 (define_insn "*rsqrtsf_internal1"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4676 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
4677 UNSPEC_RSQRT))]
4678 "TARGET_FRSQRTES"
4679 "frsqrtes %0,%1"
4680 [(set_attr "type" "fp")])
4682 (define_expand "copysign<mode>3"
4683 [(set (match_dup 3)
4684 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
4685 (set (match_dup 4)
4686 (neg:SFDF (abs:SFDF (match_dup 1))))
4687 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
4688 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
4689 (match_dup 5))
4690 (match_dup 3)
4691 (match_dup 4)))]
4692 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
4693 && ((TARGET_PPC_GFXOPT
4694 && !HONOR_NANS (<MODE>mode)
4695 && !HONOR_SIGNED_ZEROS (<MODE>mode))
4696 || TARGET_CMPB
4697 || VECTOR_UNIT_VSX_P (<MODE>mode))"
4698 {
4699 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
4700 {
4701 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
4702 operands[2]));
4703 DONE;
4704 }
4706 operands[3] = gen_reg_rtx (<MODE>mode);
4707 operands[4] = gen_reg_rtx (<MODE>mode);
4708 operands[5] = CONST0_RTX (<MODE>mode);
4709 })
4711 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
4712 ;; compiler from optimizing -0.0
4713 (define_insn "copysign<mode>3_fcpsgn"
4714 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
4715 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
4716 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
4717 UNSPEC_COPYSIGN))]
4718 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
4719 "fcpsgn %0,%2,%1"
4720 [(set_attr "type" "fp")])
4722 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4723 ;; fsel instruction and some auxiliary computations. Then we just have a
4724 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4725 ;; combine.
4726 (define_expand "smaxsf3"
4727 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4728 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4729 (match_operand:SF 2 "gpc_reg_operand" ""))
4730 (match_dup 1)
4731 (match_dup 2)))]
4732 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4733 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4734 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4736 (define_expand "sminsf3"
4737 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4738 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4739 (match_operand:SF 2 "gpc_reg_operand" ""))
4740 (match_dup 2)
4741 (match_dup 1)))]
4742 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4743 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4744 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4746 (define_split
4747 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4748 (match_operator:SF 3 "min_max_operator"
4749 [(match_operand:SF 1 "gpc_reg_operand" "")
4750 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4751 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
4752 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
4753 [(const_int 0)]
4754 "
4755 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4756 operands[1], operands[2]);
4757 DONE;
4758 }")
4760 (define_expand "mov<mode>cc"
4761 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4762 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
4763 (match_operand:GPR 2 "gpc_reg_operand" "")
4764 (match_operand:GPR 3 "gpc_reg_operand" "")))]
4765 "TARGET_ISEL<sel>"
4766 "
4767 {
4768 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4769 DONE;
4770 else
4771 FAIL;
4772 }")
4774 ;; We use the BASE_REGS for the isel input operands because, if rA is
4775 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4776 ;; because we may switch the operands and rB may end up being rA.
4777 ;;
4778 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4779 ;; leave out the mode in operand 4 and use one pattern, but reload can
4780 ;; change the mode underneath our feet and then gets confused trying
4781 ;; to reload the value.
4782 (define_insn "isel_signed_<mode>"
4783 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4784 (if_then_else:GPR
4785 (match_operator 1 "scc_comparison_operator"
4786 [(match_operand:CC 4 "cc_reg_operand" "y,y")
4787 (const_int 0)])
4788 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4789 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4790 "TARGET_ISEL<sel>"
4791 "*
4792 { return output_isel (operands); }"
4793 [(set_attr "type" "isel")
4794 (set_attr "length" "4")])
4796 (define_insn "isel_unsigned_<mode>"
4797 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4798 (if_then_else:GPR
4799 (match_operator 1 "scc_comparison_operator"
4800 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
4801 (const_int 0)])
4802 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4803 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4804 "TARGET_ISEL<sel>"
4805 "*
4806 { return output_isel (operands); }"
4807 [(set_attr "type" "isel")
4808 (set_attr "length" "4")])
4810 ;; These patterns can be useful for combine; they let combine know that
4811 ;; isel can handle reversed comparisons so long as the operands are
4812 ;; registers.
4814 (define_insn "*isel_reversed_signed_<mode>"
4815 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4816 (if_then_else:GPR
4817 (match_operator 1 "scc_rev_comparison_operator"
4818 [(match_operand:CC 4 "cc_reg_operand" "y")
4819 (const_int 0)])
4820 (match_operand:GPR 2 "gpc_reg_operand" "b")
4821 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4822 "TARGET_ISEL<sel>"
4823 "*
4824 { return output_isel (operands); }"
4825 [(set_attr "type" "isel")
4826 (set_attr "length" "4")])
4828 (define_insn "*isel_reversed_unsigned_<mode>"
4829 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4830 (if_then_else:GPR
4831 (match_operator 1 "scc_rev_comparison_operator"
4832 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4833 (const_int 0)])
4834 (match_operand:GPR 2 "gpc_reg_operand" "b")
4835 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4836 "TARGET_ISEL<sel>"
4837 "*
4838 { return output_isel (operands); }"
4839 [(set_attr "type" "isel")
4840 (set_attr "length" "4")])
4842 (define_expand "movsfcc"
4843 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4844 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4845 (match_operand:SF 2 "gpc_reg_operand" "")
4846 (match_operand:SF 3 "gpc_reg_operand" "")))]
4847 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4848 "
4849 {
4850 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4851 DONE;
4852 else
4853 FAIL;
4854 }")
4856 (define_insn "*fselsfsf4"
4857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4858 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4859 (match_operand:SF 4 "zero_fp_constant" "F"))
4860 (match_operand:SF 2 "gpc_reg_operand" "f")
4861 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4863 "fsel %0,%1,%2,%3"
4864 [(set_attr "type" "fp")])
4866 (define_insn "*fseldfsf4"
4867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4868 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
4869 (match_operand:DF 4 "zero_fp_constant" "F"))
4870 (match_operand:SF 2 "gpc_reg_operand" "f")
4871 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
4873 "fsel %0,%1,%2,%3"
4874 [(set_attr "type" "fp")])
4876 (define_expand "negdf2"
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4878 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4879 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4880 "")
4882 (define_insn "*negdf2_fpr"
4883 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4884 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4885 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4886 && !VECTOR_UNIT_VSX_P (DFmode)"
4887 "fneg %0,%1"
4888 [(set_attr "type" "fp")])
4890 (define_expand "absdf2"
4891 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4892 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
4893 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4894 "")
4896 (define_insn "*absdf2_fpr"
4897 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4898 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4899 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4900 && !VECTOR_UNIT_VSX_P (DFmode)"
4901 "fabs %0,%1"
4902 [(set_attr "type" "fp")])
4904 (define_insn "*nabsdf2_fpr"
4905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4906 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
4907 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4908 && !VECTOR_UNIT_VSX_P (DFmode)"
4909 "fnabs %0,%1"
4910 [(set_attr "type" "fp")])
4912 (define_expand "adddf3"
4913 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4914 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4915 (match_operand:DF 2 "gpc_reg_operand" "")))]
4916 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4917 "")
4919 (define_insn "*adddf3_fpr"
4920 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4921 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4922 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4923 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4924 && !VECTOR_UNIT_VSX_P (DFmode)"
4925 "fadd %0,%1,%2"
4926 [(set_attr "type" "fp")
4927 (set_attr "fp_type" "fp_addsub_d")])
4929 (define_expand "subdf3"
4930 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4931 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
4932 (match_operand:DF 2 "gpc_reg_operand" "")))]
4933 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4934 "")
4936 (define_insn "*subdf3_fpr"
4937 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4938 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4939 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4940 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4941 && !VECTOR_UNIT_VSX_P (DFmode)"
4942 "fsub %0,%1,%2"
4943 [(set_attr "type" "fp")
4944 (set_attr "fp_type" "fp_addsub_d")])
4946 (define_expand "muldf3"
4947 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4948 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
4949 (match_operand:DF 2 "gpc_reg_operand" "")))]
4950 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4951 "")
4953 (define_insn "*muldf3_fpr"
4954 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4955 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
4956 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4957 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4958 && !VECTOR_UNIT_VSX_P (DFmode)"
4959 "fmul %0,%1,%2"
4960 [(set_attr "type" "dmul")
4961 (set_attr "fp_type" "fp_mul_d")])
4963 (define_expand "divdf3"
4964 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4965 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
4966 (match_operand:DF 2 "gpc_reg_operand" "")))]
4967 "TARGET_HARD_FLOAT
4968 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
4969 && !TARGET_SIMPLE_FPU"
4970 "")
4972 (define_insn "*divdf3_fpr"
4973 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4974 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
4975 (match_operand:DF 2 "gpc_reg_operand" "d")))]
4976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
4977 && !VECTOR_UNIT_VSX_P (DFmode)"
4978 "fdiv %0,%1,%2"
4979 [(set_attr "type" "ddiv")])
4981 (define_insn "*fred_fpr"
4982 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4983 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
4984 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
4985 "fre %0,%1"
4986 [(set_attr "type" "fp")])
4988 (define_insn "*rsqrtdf_internal1"
4989 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
4990 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
4991 UNSPEC_RSQRT))]
4992 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
4993 "frsqrte %0,%1"
4994 [(set_attr "type" "fp")])
4996 ; builtin fma support
4997 (define_insn "*fmadf4_fpr"
4998 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4999 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5000 (match_operand:DF 2 "gpc_reg_operand" "f")
5001 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5002 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5003 && VECTOR_UNIT_NONE_P (DFmode)"
5004 "fmadd %0,%1,%2,%3"
5005 [(set_attr "type" "fp")
5006 (set_attr "fp_type" "fp_maddsub_d")])
5008 (define_insn "*fmsdf4_fpr"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5010 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5011 (match_operand:DF 2 "gpc_reg_operand" "f")
5012 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5013 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5014 && VECTOR_UNIT_NONE_P (DFmode)"
5015 "fmsub %0,%1,%2,%3"
5016 [(set_attr "type" "fp")
5017 (set_attr "fp_type" "fp_maddsub_d")])
5019 (define_insn "*nfmadf4_fpr"
5020 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5021 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5022 (match_operand:DF 2 "gpc_reg_operand" "f")
5023 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5024 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5025 && VECTOR_UNIT_NONE_P (DFmode)"
5026 "fnmadd %0,%1,%2,%3"
5027 [(set_attr "type" "fp")
5028 (set_attr "fp_type" "fp_maddsub_d")])
5030 (define_insn "*nfmsdf4_fpr"
5031 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5032 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5033 (match_operand:DF 2 "gpc_reg_operand" "f")
5034 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5035 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5036 && VECTOR_UNIT_NONE_P (DFmode)"
5037 "fnmsub %0,%1,%2,%3"
5038 [(set_attr "type" "fp")
5039 (set_attr "fp_type" "fp_maddsub_d")])
5041 (define_expand "sqrtdf2"
5042 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5043 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5044 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5045 "")
5047 (define_insn "*sqrtdf2_fpr"
5048 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5049 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5050 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5051 && !VECTOR_UNIT_VSX_P (DFmode)"
5052 "fsqrt %0,%1"
5053 [(set_attr "type" "dsqrt")])
5055 ;; The conditional move instructions allow us to perform max and min
5056 ;; operations even when
5058 (define_expand "smaxdf3"
5059 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5060 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5061 (match_operand:DF 2 "gpc_reg_operand" ""))
5062 (match_dup 1)
5063 (match_dup 2)))]
5064 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5065 && !flag_trapping_math"
5066 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5068 (define_expand "smindf3"
5069 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5070 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5071 (match_operand:DF 2 "gpc_reg_operand" ""))
5072 (match_dup 2)
5073 (match_dup 1)))]
5074 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5075 && !flag_trapping_math"
5076 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5078 (define_split
5079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5080 (match_operator:DF 3 "min_max_operator"
5081 [(match_operand:DF 1 "gpc_reg_operand" "")
5082 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5083 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5084 && !flag_trapping_math"
5085 [(const_int 0)]
5086 "
5087 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5088 operands[1], operands[2]);
5089 DONE;
5090 }")
5092 (define_expand "movdfcc"
5093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5094 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5095 (match_operand:DF 2 "gpc_reg_operand" "")
5096 (match_operand:DF 3 "gpc_reg_operand" "")))]
5097 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5098 "
5099 {
5100 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5101 DONE;
5102 else
5103 FAIL;
5104 }")
5106 (define_insn "*fseldfdf4"
5107 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5108 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5109 (match_operand:DF 4 "zero_fp_constant" "F"))
5110 (match_operand:DF 2 "gpc_reg_operand" "d")
5111 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5112 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5113 "fsel %0,%1,%2,%3"
5114 [(set_attr "type" "fp")])
5116 (define_insn "*fselsfdf4"
5117 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5118 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5119 (match_operand:SF 4 "zero_fp_constant" "F"))
5120 (match_operand:DF 2 "gpc_reg_operand" "d")
5121 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5122 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5123 "fsel %0,%1,%2,%3"
5124 [(set_attr "type" "fp")])
5125 \f
5126 ;; Conversions to and from floating-point.
5128 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5129 ; don't want to support putting SImode in FPR registers.
5130 (define_insn "lfiwax"
5131 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5132 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5133 UNSPEC_LFIWAX))]
5134 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5135 "lfiwax %0,%y1"
5136 [(set_attr "type" "fpload")])
5138 ; This split must be run before register allocation because it allocates the
5139 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5140 ; it earlier to allow for the combiner to merge insns together where it might
5141 ; not be needed and also in case the insns are deleted as dead code.
5143 (define_insn_and_split "floatsi<mode>2_lfiwax"
5144 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5145 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5146 (clobber (match_scratch:DI 2 "=d"))]
5147 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5148 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5149 "#"
5150 ""
5151 [(pc)]
5152 "
5153 {
5154 rtx dest = operands[0];
5155 rtx src = operands[1];
5156 rtx tmp;
5158 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5159 tmp = convert_to_mode (DImode, src, false);
5160 else
5161 {
5162 tmp = operands[2];
5163 if (GET_CODE (tmp) == SCRATCH)
5164 tmp = gen_reg_rtx (DImode);
5165 if (MEM_P (src))
5166 {
5167 src = rs6000_address_for_fpconvert (src);
5168 emit_insn (gen_lfiwax (tmp, src));
5169 }
5170 else
5171 {
5172 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5173 emit_move_insn (stack, src);
5174 emit_insn (gen_lfiwax (tmp, stack));
5175 }
5176 }
5177 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5178 DONE;
5179 }"
5180 [(set_attr "length" "12")
5181 (set_attr "type" "fpload")])
5183 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5184 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5185 (float:SFDF
5186 (sign_extend:DI
5187 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5188 (clobber (match_scratch:DI 2 "=0,d"))]
5189 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5190 && <SI_CONVERT_FP>"
5191 "#"
5192 ""
5193 [(pc)]
5194 "
5195 {
5196 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5197 if (GET_CODE (operands[2]) == SCRATCH)
5198 operands[2] = gen_reg_rtx (DImode);
5199 emit_insn (gen_lfiwax (operands[2], operands[1]));
5200 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5201 DONE;
5202 }"
5203 [(set_attr "length" "8")
5204 (set_attr "type" "fpload")])
5206 (define_insn "lfiwzx"
5207 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5208 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5209 UNSPEC_LFIWZX))]
5210 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5211 "lfiwzx %0,%y1"
5212 [(set_attr "type" "fpload")])
5214 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5215 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5216 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5217 (clobber (match_scratch:DI 2 "=d"))]
5218 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5219 && <SI_CONVERT_FP>"
5220 "#"
5221 ""
5222 [(pc)]
5223 "
5224 {
5225 rtx dest = operands[0];
5226 rtx src = operands[1];
5227 rtx tmp;
5229 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5230 tmp = convert_to_mode (DImode, src, true);
5231 else
5232 {
5233 tmp = operands[2];
5234 if (GET_CODE (tmp) == SCRATCH)
5235 tmp = gen_reg_rtx (DImode);
5236 if (MEM_P (src))
5237 {
5238 src = rs6000_address_for_fpconvert (src);
5239 emit_insn (gen_lfiwzx (tmp, src));
5240 }
5241 else
5242 {
5243 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5244 emit_move_insn (stack, src);
5245 emit_insn (gen_lfiwzx (tmp, stack));
5246 }
5247 }
5248 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5249 DONE;
5250 }"
5251 [(set_attr "length" "12")
5252 (set_attr "type" "fpload")])
5254 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5255 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5256 (unsigned_float:SFDF
5257 (zero_extend:DI
5258 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5259 (clobber (match_scratch:DI 2 "=0,d"))]
5260 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5261 && <SI_CONVERT_FP>"
5262 "#"
5263 ""
5264 [(pc)]
5265 "
5266 {
5267 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5268 if (GET_CODE (operands[2]) == SCRATCH)
5269 operands[2] = gen_reg_rtx (DImode);
5270 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5271 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5272 DONE;
5273 }"
5274 [(set_attr "length" "8")
5275 (set_attr "type" "fpload")])
5277 ; For each of these conversions, there is a define_expand, a define_insn
5278 ; with a '#' template, and a define_split (with C code). The idea is
5279 ; to allow constant folding with the template of the define_insn,
5280 ; then to have the insns split later (between sched1 and final).
5282 (define_expand "floatsidf2"
5283 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5284 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5285 (use (match_dup 2))
5286 (use (match_dup 3))
5287 (clobber (match_dup 4))
5288 (clobber (match_dup 5))
5289 (clobber (match_dup 6))])]
5290 "TARGET_HARD_FLOAT
5291 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5292 "
5293 {
5294 if (TARGET_E500_DOUBLE)
5295 {
5296 if (!REG_P (operands[1]))
5297 operands[1] = force_reg (SImode, operands[1]);
5298 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5299 DONE;
5300 }
5301 else if (TARGET_LFIWAX && TARGET_FCFID)
5302 {
5303 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5304 DONE;
5305 }
5306 else if (TARGET_FCFID)
5307 {
5308 rtx dreg = operands[1];
5309 if (!REG_P (dreg))
5310 dreg = force_reg (SImode, dreg);
5311 dreg = convert_to_mode (DImode, dreg, false);
5312 emit_insn (gen_floatdidf2 (operands[0], dreg));
5313 DONE;
5314 }
5316 if (!REG_P (operands[1]))
5317 operands[1] = force_reg (SImode, operands[1]);
5318 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5319 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5320 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5321 operands[5] = gen_reg_rtx (DFmode);
5322 operands[6] = gen_reg_rtx (SImode);
5323 }")
5325 (define_insn_and_split "*floatsidf2_internal"
5326 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5327 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5328 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5329 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5330 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5331 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5332 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5333 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5334 "#"
5335 ""
5336 [(pc)]
5337 "
5338 {
5339 rtx lowword, highword;
5340 gcc_assert (MEM_P (operands[4]));
5341 highword = adjust_address (operands[4], SImode, 0);
5342 lowword = adjust_address (operands[4], SImode, 4);
5343 if (! WORDS_BIG_ENDIAN)
5344 {
5345 rtx tmp;
5346 tmp = highword; highword = lowword; lowword = tmp;
5347 }
5349 emit_insn (gen_xorsi3 (operands[6], operands[1],
5350 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5351 emit_move_insn (lowword, operands[6]);
5352 emit_move_insn (highword, operands[2]);
5353 emit_move_insn (operands[5], operands[4]);
5354 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5355 DONE;
5356 }"
5357 [(set_attr "length" "24")
5358 (set_attr "type" "fp")])
5360 ;; If we don't have a direct conversion to single precision, don't enable this
5361 ;; conversion for 32-bit without fast math, because we don't have the insn to
5362 ;; generate the fixup swizzle to avoid double rounding problems.
5363 (define_expand "floatunssisf2"
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5365 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5366 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5367 && (!TARGET_FPRS
5368 || (TARGET_FPRS
5369 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5370 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5371 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5372 "
5373 {
5374 if (!TARGET_FPRS)
5375 {
5376 if (!REG_P (operands[1]))
5377 operands[1] = force_reg (SImode, operands[1]);
5378 }
5379 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5380 {
5381 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5382 DONE;
5383 }
5384 else
5385 {
5386 rtx dreg = operands[1];
5387 if (!REG_P (dreg))
5388 dreg = force_reg (SImode, dreg);
5389 dreg = convert_to_mode (DImode, dreg, true);
5390 emit_insn (gen_floatdisf2 (operands[0], dreg));
5391 DONE;
5392 }
5393 }")
5395 (define_expand "floatunssidf2"
5396 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5397 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5398 (use (match_dup 2))
5399 (use (match_dup 3))
5400 (clobber (match_dup 4))
5401 (clobber (match_dup 5))])]
5402 "TARGET_HARD_FLOAT
5403 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5404 "
5405 {
5406 if (TARGET_E500_DOUBLE)
5407 {
5408 if (!REG_P (operands[1]))
5409 operands[1] = force_reg (SImode, operands[1]);
5410 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5411 DONE;
5412 }
5413 else if (TARGET_LFIWZX && TARGET_FCFID)
5414 {
5415 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5416 DONE;
5417 }
5418 else if (TARGET_FCFID)
5419 {
5420 rtx dreg = operands[1];
5421 if (!REG_P (dreg))
5422 dreg = force_reg (SImode, dreg);
5423 dreg = convert_to_mode (DImode, dreg, true);
5424 emit_insn (gen_floatdidf2 (operands[0], dreg));
5425 DONE;
5426 }
5428 if (!REG_P (operands[1]))
5429 operands[1] = force_reg (SImode, operands[1]);
5430 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5431 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5432 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5433 operands[5] = gen_reg_rtx (DFmode);
5434 }")
5436 (define_insn_and_split "*floatunssidf2_internal"
5437 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5438 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5439 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5440 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5441 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5442 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5443 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5444 && !(TARGET_FCFID && TARGET_POWERPC64)"
5445 "#"
5446 ""
5447 [(pc)]
5448 "
5449 {
5450 rtx lowword, highword;
5451 gcc_assert (MEM_P (operands[4]));
5452 highword = adjust_address (operands[4], SImode, 0);
5453 lowword = adjust_address (operands[4], SImode, 4);
5454 if (! WORDS_BIG_ENDIAN)
5455 {
5456 rtx tmp;
5457 tmp = highword; highword = lowword; lowword = tmp;
5458 }
5460 emit_move_insn (lowword, operands[1]);
5461 emit_move_insn (highword, operands[2]);
5462 emit_move_insn (operands[5], operands[4]);
5463 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5464 DONE;
5465 }"
5466 [(set_attr "length" "20")
5467 (set_attr "type" "fp")])
5469 (define_expand "fix_trunc<mode>si2"
5470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5471 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5472 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5473 "
5474 {
5475 if (!<E500_CONVERT>)
5476 {
5477 rtx tmp, stack;
5479 if (TARGET_STFIWX)
5480 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5481 else
5482 {
5483 tmp = gen_reg_rtx (DImode);
5484 stack = rs6000_allocate_stack_temp (DImode, true, false);
5485 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5486 tmp, stack));
5487 }
5488 DONE;
5489 }
5490 }")
5492 ; Like the convert to float patterns, this insn must be split before
5493 ; register allocation so that it can allocate the memory slot if it
5494 ; needed
5495 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5496 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5497 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5498 (clobber (match_scratch:DI 2 "=d"))]
5499 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5500 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5501 && TARGET_STFIWX && can_create_pseudo_p ()"
5502 "#"
5503 ""
5504 [(pc)]
5505 {
5506 rtx dest = operands[0];
5507 rtx src = operands[1];
5508 rtx tmp = operands[2];
5510 if (GET_CODE (tmp) == SCRATCH)
5511 tmp = gen_reg_rtx (DImode);
5513 emit_insn (gen_fctiwz_<mode> (tmp, src));
5514 if (MEM_P (dest))
5515 {
5516 dest = rs6000_address_for_fpconvert (dest);
5517 emit_insn (gen_stfiwx (dest, tmp));
5518 DONE;
5519 }
5520 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5521 {
5522 dest = gen_lowpart (DImode, dest);
5523 emit_move_insn (dest, tmp);
5524 DONE;
5525 }
5526 else
5527 {
5528 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5529 emit_insn (gen_stfiwx (stack, tmp));
5530 emit_move_insn (dest, stack);
5531 DONE;
5532 }
5533 }
5534 [(set_attr "length" "12")
5535 (set_attr "type" "fp")])
5537 (define_insn_and_split "fix_trunc<mode>si2_internal"
5538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5539 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5540 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5541 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5543 "#"
5544 ""
5545 [(pc)]
5546 "
5547 {
5548 rtx lowword;
5549 gcc_assert (MEM_P (operands[3]));
5550 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5552 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5553 emit_move_insn (operands[3], operands[2]);
5554 emit_move_insn (operands[0], lowword);
5555 DONE;
5556 }"
5557 [(set_attr "length" "16")
5558 (set_attr "type" "fp")])
5560 (define_expand "fix_trunc<mode>di2"
5561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5562 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5563 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5564 && TARGET_FCFID"
5565 "")
5567 (define_insn "*fix_trunc<mode>di2_fctidz"
5568 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5569 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5570 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5571 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5572 "fctidz %0,%1"
5573 [(set_attr "type" "fp")])
5575 (define_expand "fixuns_trunc<mode>si2"
5576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5577 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5578 "TARGET_HARD_FLOAT
5579 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5580 || <E500_CONVERT>)"
5581 "
5582 {
5583 if (!<E500_CONVERT>)
5584 {
5585 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5586 DONE;
5587 }
5588 }")
5590 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5591 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5592 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5593 (clobber (match_scratch:DI 2 "=d"))]
5594 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5595 && TARGET_STFIWX && can_create_pseudo_p ()"
5596 "#"
5597 ""
5598 [(pc)]
5599 {
5600 rtx dest = operands[0];
5601 rtx src = operands[1];
5602 rtx tmp = operands[2];
5604 if (GET_CODE (tmp) == SCRATCH)
5605 tmp = gen_reg_rtx (DImode);
5607 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5608 if (MEM_P (dest))
5609 {
5610 dest = rs6000_address_for_fpconvert (dest);
5611 emit_insn (gen_stfiwx (dest, tmp));
5612 DONE;
5613 }
5614 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5615 {
5616 dest = gen_lowpart (DImode, dest);
5617 emit_move_insn (dest, tmp);
5618 DONE;
5619 }
5620 else
5621 {
5622 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5623 emit_insn (gen_stfiwx (stack, tmp));
5624 emit_move_insn (dest, stack);
5625 DONE;
5626 }
5627 }
5628 [(set_attr "length" "12")
5629 (set_attr "type" "fp")])
5631 (define_expand "fixuns_trunc<mode>di2"
5632 [(set (match_operand:DI 0 "register_operand" "")
5633 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5634 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5635 "")
5637 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5638 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5639 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
5640 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5641 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5642 "fctiduz %0,%1"
5643 [(set_attr "type" "fp")])
5645 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5646 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5647 ; because the first makes it clear that operand 0 is not live
5648 ; before the instruction.
5649 (define_insn "fctiwz_<mode>"
5650 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5651 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
5652 UNSPEC_FCTIWZ))]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5654 "fctiwz %0,%1"
5655 [(set_attr "type" "fp")])
5657 (define_insn "fctiwuz_<mode>"
5658 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5659 (unspec:DI [(unsigned_fix:SI
5660 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
5661 UNSPEC_FCTIWUZ))]
5662 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5663 "fctiwuz %0,%1"
5664 [(set_attr "type" "fp")])
5666 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5667 ;; since the friz instruction does not truncate the value if the floating
5668 ;; point value is < LONG_MIN or > LONG_MAX.
5669 (define_insn "*friz"
5670 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5671 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5672 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5673 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
5674 && !flag_trapping_math && TARGET_FRIZ"
5675 "friz %0,%1"
5676 [(set_attr "type" "fp")])
5678 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
5679 ;; load to properly sign extend the value, but at least doing a store, load
5680 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
5681 ;; if we have 32-bit memory ops
5682 (define_insn_and_split "*round32<mode>2_fprs"
5683 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5684 (float:SFDF
5685 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5686 (clobber (match_scratch:DI 2 "=d"))
5687 (clobber (match_scratch:DI 3 "=d"))]
5688 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5689 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5690 && can_create_pseudo_p ()"
5691 "#"
5692 ""
5693 [(pc)]
5694 {
5695 rtx dest = operands[0];
5696 rtx src = operands[1];
5697 rtx tmp1 = operands[2];
5698 rtx tmp2 = operands[3];
5699 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5701 if (GET_CODE (tmp1) == SCRATCH)
5702 tmp1 = gen_reg_rtx (DImode);
5703 if (GET_CODE (tmp2) == SCRATCH)
5704 tmp2 = gen_reg_rtx (DImode);
5706 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5707 emit_insn (gen_stfiwx (stack, tmp1));
5708 emit_insn (gen_lfiwax (tmp2, stack));
5709 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5710 DONE;
5711 }
5712 [(set_attr "type" "fpload")
5713 (set_attr "length" "16")])
5715 (define_insn_and_split "*roundu32<mode>2_fprs"
5716 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5717 (unsigned_float:SFDF
5718 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5719 (clobber (match_scratch:DI 2 "=d"))
5720 (clobber (match_scratch:DI 3 "=d"))]
5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5722 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
5723 && can_create_pseudo_p ()"
5724 "#"
5725 ""
5726 [(pc)]
5727 {
5728 rtx dest = operands[0];
5729 rtx src = operands[1];
5730 rtx tmp1 = operands[2];
5731 rtx tmp2 = operands[3];
5732 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5734 if (GET_CODE (tmp1) == SCRATCH)
5735 tmp1 = gen_reg_rtx (DImode);
5736 if (GET_CODE (tmp2) == SCRATCH)
5737 tmp2 = gen_reg_rtx (DImode);
5739 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5740 emit_insn (gen_stfiwx (stack, tmp1));
5741 emit_insn (gen_lfiwzx (tmp2, stack));
5742 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5743 DONE;
5744 }
5745 [(set_attr "type" "fpload")
5746 (set_attr "length" "16")])
5748 ;; No VSX equivalent to fctid
5749 (define_insn "lrint<mode>di2"
5750 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5751 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5752 UNSPEC_FCTID))]
5753 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5754 "fctid %0,%1"
5755 [(set_attr "type" "fp")])
5757 (define_expand "btrunc<mode>2"
5758 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5759 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5760 UNSPEC_FRIZ))]
5761 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5762 "")
5764 (define_insn "*btrunc<mode>2_fpr"
5765 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5766 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5767 UNSPEC_FRIZ))]
5768 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5769 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5770 "friz %0,%1"
5771 [(set_attr "type" "fp")])
5773 (define_expand "ceil<mode>2"
5774 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5775 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5776 UNSPEC_FRIP))]
5777 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5778 "")
5780 (define_insn "*ceil<mode>2_fpr"
5781 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5782 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5783 UNSPEC_FRIP))]
5784 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5785 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5786 "frip %0,%1"
5787 [(set_attr "type" "fp")])
5789 (define_expand "floor<mode>2"
5790 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5791 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5792 UNSPEC_FRIM))]
5793 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5794 "")
5796 (define_insn "*floor<mode>2_fpr"
5797 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5798 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5799 UNSPEC_FRIM))]
5800 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5801 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5802 "frim %0,%1"
5803 [(set_attr "type" "fp")])
5805 ;; No VSX equivalent to frin
5806 (define_insn "round<mode>2"
5807 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5808 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5809 UNSPEC_FRIN))]
5810 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
5811 "frin %0,%1"
5812 [(set_attr "type" "fp")])
5814 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5815 (define_insn "stfiwx"
5816 [(set (match_operand:SI 0 "memory_operand" "=Z")
5817 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
5818 UNSPEC_STFIWX))]
5819 "TARGET_PPC_GFXOPT"
5820 "stfiwx %1,%y0"
5821 [(set_attr "type" "fpstore")])
5823 ;; If we don't have a direct conversion to single precision, don't enable this
5824 ;; conversion for 32-bit without fast math, because we don't have the insn to
5825 ;; generate the fixup swizzle to avoid double rounding problems.
5826 (define_expand "floatsisf2"
5827 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5828 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5829 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5830 && (!TARGET_FPRS
5831 || (TARGET_FPRS
5832 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5833 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5834 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5835 "
5836 {
5837 if (!TARGET_FPRS)
5838 {
5839 if (!REG_P (operands[1]))
5840 operands[1] = force_reg (SImode, operands[1]);
5841 }
5842 else if (TARGET_FCFIDS && TARGET_LFIWAX)
5843 {
5844 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
5845 DONE;
5846 }
5847 else if (TARGET_FCFID && TARGET_LFIWAX)
5848 {
5849 rtx dfreg = gen_reg_rtx (DFmode);
5850 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
5851 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
5852 DONE;
5853 }
5854 else
5855 {
5856 rtx dreg = operands[1];
5857 if (!REG_P (dreg))
5858 dreg = force_reg (SImode, dreg);
5859 dreg = convert_to_mode (DImode, dreg, false);
5860 emit_insn (gen_floatdisf2 (operands[0], dreg));
5861 DONE;
5862 }
5863 }")
5865 (define_expand "floatdidf2"
5866 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5867 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
5868 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5869 "")
5871 (define_insn "*floatdidf2_fpr"
5872 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5873 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5874 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5875 && !VECTOR_UNIT_VSX_P (DFmode)"
5876 "fcfid %0,%1"
5877 [(set_attr "type" "fp")])
5879 ; Allow the combiner to merge source memory operands to the conversion so that
5880 ; the optimizer/register allocator doesn't try to load the value too early in a
5881 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
5882 ; hit. We will split after reload to avoid the trip through the GPRs
5884 (define_insn_and_split "*floatdidf2_mem"
5885 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5886 (float:DF (match_operand:DI 1 "memory_operand" "m")))
5887 (clobber (match_scratch:DI 2 "=d"))]
5888 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
5889 "#"
5890 "&& reload_completed"
5891 [(set (match_dup 2) (match_dup 1))
5892 (set (match_dup 0) (float:DF (match_dup 2)))]
5893 ""
5894 [(set_attr "length" "8")
5895 (set_attr "type" "fpload")])
5897 (define_expand "floatunsdidf2"
5898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5899 (unsigned_float:DF
5900 (match_operand:DI 1 "gpc_reg_operand" "")))]
5901 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5902 "")
5904 (define_insn "*floatunsdidf2_fcfidu"
5905 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5906 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5907 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
5908 "fcfidu %0,%1"
5909 [(set_attr "type" "fp")
5910 (set_attr "length" "4")])
5912 (define_insn_and_split "*floatunsdidf2_mem"
5913 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5914 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
5915 (clobber (match_scratch:DI 2 "=d"))]
5916 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5917 "#"
5918 "&& reload_completed"
5919 [(set (match_dup 2) (match_dup 1))
5920 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
5921 ""
5922 [(set_attr "length" "8")
5923 (set_attr "type" "fpload")])
5925 (define_expand "floatdisf2"
5926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5928 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5929 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
5930 "
5931 {
5932 if (!TARGET_FCFIDS)
5933 {
5934 rtx val = operands[1];
5935 if (!flag_unsafe_math_optimizations)
5936 {
5937 rtx label = gen_label_rtx ();
5938 val = gen_reg_rtx (DImode);
5939 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5940 emit_label (label);
5941 }
5942 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5943 DONE;
5944 }
5945 }")
5947 (define_insn "floatdisf2_fcfids"
5948 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5949 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
5950 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5951 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5952 "fcfids %0,%1"
5953 [(set_attr "type" "fp")])
5955 (define_insn_and_split "*floatdisf2_mem"
5956 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5957 (float:SF (match_operand:DI 1 "memory_operand" "m")))
5958 (clobber (match_scratch:DI 2 "=f"))]
5959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5960 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5961 "#"
5962 "&& reload_completed"
5963 [(pc)]
5964 "
5965 {
5966 emit_move_insn (operands[2], operands[1]);
5967 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
5968 DONE;
5969 }"
5970 [(set_attr "length" "8")])
5972 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5973 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5974 ;; from double rounding.
5975 ;; Instead of creating a new cpu type for two FP operations, just use fp
5976 (define_insn_and_split "floatdisf2_internal1"
5977 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5978 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
5979 (clobber (match_scratch:DF 2 "=d"))]
5980 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5981 "#"
5982 "&& reload_completed"
5983 [(set (match_dup 2)
5984 (float:DF (match_dup 1)))
5985 (set (match_dup 0)
5986 (float_truncate:SF (match_dup 2)))]
5987 ""
5988 [(set_attr "length" "8")
5989 (set_attr "type" "fp")])
5991 ;; Twiddles bits to avoid double rounding.
5992 ;; Bits that might be truncated when converting to DFmode are replaced
5993 ;; by a bit that won't be lost at that stage, but is below the SFmode
5994 ;; rounding position.
5995 (define_expand "floatdisf2_internal2"
5996 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5997 (const_int 53)))
5998 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5999 (const_int 2047)))
6000 (clobber (scratch:CC))])
6001 (set (match_dup 3) (plus:DI (match_dup 3)
6002 (const_int 1)))
6003 (set (match_dup 0) (plus:DI (match_dup 0)
6004 (const_int 2047)))
6005 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6006 (const_int 2)))
6007 (set (match_dup 0) (ior:DI (match_dup 0)
6008 (match_dup 1)))
6009 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6010 (const_int -2048)))
6011 (clobber (scratch:CC))])
6012 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6013 (label_ref (match_operand:DI 2 "" ""))
6014 (pc)))
6015 (set (match_dup 0) (match_dup 1))]
6016 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6017 "
6018 {
6019 operands[3] = gen_reg_rtx (DImode);
6020 operands[4] = gen_reg_rtx (CCUNSmode);
6021 }")
6023 (define_expand "floatunsdisf2"
6024 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6025 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6026 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6027 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6028 "")
6030 (define_insn "floatunsdisf2_fcfidus"
6031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6032 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6033 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6034 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6035 "fcfidus %0,%1"
6036 [(set_attr "type" "fp")])
6038 (define_insn_and_split "*floatunsdisf2_mem"
6039 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6040 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6041 (clobber (match_scratch:DI 2 "=f"))]
6042 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6043 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6044 "#"
6045 "&& reload_completed"
6046 [(pc)]
6047 "
6048 {
6049 emit_move_insn (operands[2], operands[1]);
6050 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6051 DONE;
6052 }"
6053 [(set_attr "length" "8")
6054 (set_attr "type" "fpload")])
6055 \f
6056 ;; Define the DImode operations that can be done in a small number
6057 ;; of instructions. The & constraints are to prevent the register
6058 ;; allocator from allocating registers that overlap with the inputs
6059 ;; (for example, having an input in 7,8 and an output in 6,7). We
6060 ;; also allow for the output being the same as one of the inputs.
6062 (define_insn "*adddi3_noppc64"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6064 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6065 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6066 "! TARGET_POWERPC64"
6067 "*
6068 {
6069 if (WORDS_BIG_ENDIAN)
6070 return (GET_CODE (operands[2])) != CONST_INT
6071 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6072 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6073 else
6074 return (GET_CODE (operands[2])) != CONST_INT
6075 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6076 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6077 }"
6078 [(set_attr "type" "two")
6079 (set_attr "length" "8")])
6081 (define_insn "*subdi3_noppc64"
6082 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6083 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6084 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6085 "! TARGET_POWERPC64"
6086 "*
6087 {
6088 if (WORDS_BIG_ENDIAN)
6089 return (GET_CODE (operands[1]) != CONST_INT)
6090 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6091 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6092 else
6093 return (GET_CODE (operands[1]) != CONST_INT)
6094 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6095 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6096 }"
6097 [(set_attr "type" "two")
6098 (set_attr "length" "8")])
6100 (define_insn "*negdi2_noppc64"
6101 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6102 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6103 "! TARGET_POWERPC64"
6104 "*
6105 {
6106 return (WORDS_BIG_ENDIAN)
6107 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6108 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6109 }"
6110 [(set_attr "type" "two")
6111 (set_attr "length" "8")])
6113 (define_insn "mulsidi3"
6114 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6115 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6116 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6117 "! TARGET_POWERPC64"
6118 {
6119 return (WORDS_BIG_ENDIAN)
6120 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6121 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6122 }
6123 [(set_attr "type" "imul")
6124 (set_attr "length" "8")])
6126 (define_split
6127 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6128 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6129 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6130 "! TARGET_POWERPC64 && reload_completed"
6131 [(set (match_dup 3)
6132 (truncate:SI
6133 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6134 (sign_extend:DI (match_dup 2)))
6135 (const_int 32))))
6136 (set (match_dup 4)
6137 (mult:SI (match_dup 1)
6138 (match_dup 2)))]
6139 "
6140 {
6141 int endian = (WORDS_BIG_ENDIAN == 0);
6142 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6143 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6144 }")
6146 (define_insn "umulsidi3"
6147 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6148 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6149 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6150 "! TARGET_POWERPC64"
6151 "*
6152 {
6153 return (WORDS_BIG_ENDIAN)
6154 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6155 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6156 }"
6157 [(set_attr "type" "imul")
6158 (set_attr "length" "8")])
6160 (define_split
6161 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6162 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6163 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6164 "! TARGET_POWERPC64 && reload_completed"
6165 [(set (match_dup 3)
6166 (truncate:SI
6167 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6168 (zero_extend:DI (match_dup 2)))
6169 (const_int 32))))
6170 (set (match_dup 4)
6171 (mult:SI (match_dup 1)
6172 (match_dup 2)))]
6173 "
6174 {
6175 int endian = (WORDS_BIG_ENDIAN == 0);
6176 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6177 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6178 }")
6180 (define_insn "smulsi3_highpart"
6181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6182 (truncate:SI
6183 (lshiftrt:DI (mult:DI (sign_extend:DI
6184 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6185 (sign_extend:DI
6186 (match_operand:SI 2 "gpc_reg_operand" "r")))
6187 (const_int 32))))]
6188 ""
6189 "mulhw %0,%1,%2"
6190 [(set_attr "type" "imul")])
6192 (define_insn "umulsi3_highpart"
6193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6194 (truncate:SI
6195 (lshiftrt:DI (mult:DI (zero_extend:DI
6196 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6197 (zero_extend:DI
6198 (match_operand:SI 2 "gpc_reg_operand" "r")))
6199 (const_int 32))))]
6200 ""
6201 "mulhwu %0,%1,%2"
6202 [(set_attr "type" "imul")])
6204 ;; Shift by a variable amount is too complex to be worth open-coding. We
6205 ;; just handle shifts by constants.
6206 (define_insn "ashrdi3_no_power"
6207 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6208 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6209 (match_operand:SI 2 "const_int_operand" "M,i")))]
6210 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6211 "@
6212 srawi %0,%1,31\;srawi %L0,%1,%h2
6213 srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2"
6214 [(set_attr "type" "two,three")
6215 (set_attr "length" "8,12")])
6217 (define_insn "*ashrdisi3_noppc64"
6218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6219 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6220 (const_int 32)) 4))]
6221 "TARGET_32BIT && !TARGET_POWERPC64"
6222 "*
6223 {
6224 if (REGNO (operands[0]) == REGNO (operands[1]))
6225 return \"\";
6226 else
6227 return \"mr %0,%1\";
6228 }"
6229 [(set_attr "length" "4")])
6231 \f
6232 ;; PowerPC64 DImode operations.
6234 (define_insn "muldi3"
6235 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6236 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6237 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6238 "TARGET_POWERPC64"
6239 "@
6240 mulld %0,%1,%2
6241 mulli %0,%1,%2"
6242 [(set (attr "type")
6243 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6244 (const_string "imul3")
6245 (match_operand:SI 2 "short_cint_operand" "")
6246 (const_string "imul2")]
6247 (const_string "lmul")))])
6249 (define_insn "*muldi3_internal1"
6250 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6251 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6252 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6253 (const_int 0)))
6254 (clobber (match_scratch:DI 3 "=r,r"))]
6255 "TARGET_POWERPC64"
6256 "@
6257 mulld. %3,%1,%2
6258 #"
6259 [(set_attr "type" "lmul_compare")
6260 (set_attr "length" "4,8")])
6262 (define_split
6263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6264 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6265 (match_operand:DI 2 "gpc_reg_operand" ""))
6266 (const_int 0)))
6267 (clobber (match_scratch:DI 3 ""))]
6268 "TARGET_POWERPC64 && reload_completed"
6269 [(set (match_dup 3)
6270 (mult:DI (match_dup 1) (match_dup 2)))
6271 (set (match_dup 0)
6272 (compare:CC (match_dup 3)
6273 (const_int 0)))]
6274 "")
6276 (define_insn "*muldi3_internal2"
6277 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6278 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6279 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6280 (const_int 0)))
6281 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6282 (mult:DI (match_dup 1) (match_dup 2)))]
6283 "TARGET_POWERPC64"
6284 "@
6285 mulld. %0,%1,%2
6286 #"
6287 [(set_attr "type" "lmul_compare")
6288 (set_attr "length" "4,8")])
6290 (define_split
6291 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6292 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "gpc_reg_operand" ""))
6294 (const_int 0)))
6295 (set (match_operand:DI 0 "gpc_reg_operand" "")
6296 (mult:DI (match_dup 1) (match_dup 2)))]
6297 "TARGET_POWERPC64 && reload_completed"
6298 [(set (match_dup 0)
6299 (mult:DI (match_dup 1) (match_dup 2)))
6300 (set (match_dup 3)
6301 (compare:CC (match_dup 0)
6302 (const_int 0)))]
6303 "")
6305 (define_insn "smuldi3_highpart"
6306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6307 (truncate:DI
6308 (lshiftrt:TI (mult:TI (sign_extend:TI
6309 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6310 (sign_extend:TI
6311 (match_operand:DI 2 "gpc_reg_operand" "r")))
6312 (const_int 64))))]
6313 "TARGET_POWERPC64"
6314 "mulhd %0,%1,%2"
6315 [(set_attr "type" "lmul")])
6317 (define_insn "umuldi3_highpart"
6318 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6319 (truncate:DI
6320 (lshiftrt:TI (mult:TI (zero_extend:TI
6321 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6322 (zero_extend:TI
6323 (match_operand:DI 2 "gpc_reg_operand" "r")))
6324 (const_int 64))))]
6325 "TARGET_POWERPC64"
6326 "mulhdu %0,%1,%2"
6327 [(set_attr "type" "lmul")])
6329 (define_insn "rotldi3"
6330 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6331 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6332 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6333 "TARGET_POWERPC64"
6334 "@
6335 rldcl %0,%1,%2,0
6336 rldicl %0,%1,%H2,0"
6337 [(set_attr "type" "var_shift_rotate,integer")])
6339 (define_insn "*rotldi3_internal2"
6340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6341 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6342 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6343 (const_int 0)))
6344 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6345 "TARGET_64BIT"
6346 "@
6347 rldcl. %3,%1,%2,0
6348 rldicl. %3,%1,%H2,0
6349 #
6350 #"
6351 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6352 (set_attr "length" "4,4,8,8")])
6354 (define_split
6355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6356 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6357 (match_operand:DI 2 "reg_or_cint_operand" ""))
6358 (const_int 0)))
6359 (clobber (match_scratch:DI 3 ""))]
6360 "TARGET_POWERPC64 && reload_completed"
6361 [(set (match_dup 3)
6362 (rotate:DI (match_dup 1) (match_dup 2)))
6363 (set (match_dup 0)
6364 (compare:CC (match_dup 3)
6365 (const_int 0)))]
6366 "")
6368 (define_insn "*rotldi3_internal3"
6369 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6370 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6371 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6372 (const_int 0)))
6373 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6374 (rotate:DI (match_dup 1) (match_dup 2)))]
6375 "TARGET_64BIT"
6376 "@
6377 rldcl. %0,%1,%2,0
6378 rldicl. %0,%1,%H2,0
6379 #
6380 #"
6381 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6382 (set_attr "length" "4,4,8,8")])
6384 (define_split
6385 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6386 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6387 (match_operand:DI 2 "reg_or_cint_operand" ""))
6388 (const_int 0)))
6389 (set (match_operand:DI 0 "gpc_reg_operand" "")
6390 (rotate:DI (match_dup 1) (match_dup 2)))]
6391 "TARGET_POWERPC64 && reload_completed"
6392 [(set (match_dup 0)
6393 (rotate:DI (match_dup 1) (match_dup 2)))
6394 (set (match_dup 3)
6395 (compare:CC (match_dup 0)
6396 (const_int 0)))]
6397 "")
6399 (define_insn "*rotldi3_internal4"
6400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6401 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6402 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6403 (match_operand:DI 3 "mask64_operand" "n,n")))]
6404 "TARGET_POWERPC64"
6405 "@
6406 rldc%B3 %0,%1,%2,%S3
6407 rldic%B3 %0,%1,%H2,%S3"
6408 [(set_attr "type" "var_shift_rotate,integer")])
6410 (define_insn "*rotldi3_internal5"
6411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6412 (compare:CC (and:DI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6415 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6416 (const_int 0)))
6417 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6418 "TARGET_64BIT"
6419 "@
6420 rldc%B3. %4,%1,%2,%S3
6421 rldic%B3. %4,%1,%H2,%S3
6422 #
6423 #"
6424 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6425 (set_attr "length" "4,4,8,8")])
6427 (define_split
6428 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6429 (compare:CC (and:DI
6430 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6431 (match_operand:DI 2 "reg_or_cint_operand" ""))
6432 (match_operand:DI 3 "mask64_operand" ""))
6433 (const_int 0)))
6434 (clobber (match_scratch:DI 4 ""))]
6435 "TARGET_POWERPC64 && reload_completed"
6436 [(set (match_dup 4)
6437 (and:DI (rotate:DI (match_dup 1)
6438 (match_dup 2))
6439 (match_dup 3)))
6440 (set (match_dup 0)
6441 (compare:CC (match_dup 4)
6442 (const_int 0)))]
6443 "")
6445 (define_insn "*rotldi3_internal6"
6446 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6447 (compare:CC (and:DI
6448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6449 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6450 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6451 (const_int 0)))
6452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6453 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6454 "TARGET_64BIT"
6455 "@
6456 rldc%B3. %0,%1,%2,%S3
6457 rldic%B3. %0,%1,%H2,%S3
6458 #
6459 #"
6460 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6461 (set_attr "length" "4,4,8,8")])
6463 (define_split
6464 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6465 (compare:CC (and:DI
6466 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6467 (match_operand:DI 2 "reg_or_cint_operand" ""))
6468 (match_operand:DI 3 "mask64_operand" ""))
6469 (const_int 0)))
6470 (set (match_operand:DI 0 "gpc_reg_operand" "")
6471 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6472 "TARGET_POWERPC64 && reload_completed"
6473 [(set (match_dup 0)
6474 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6475 (set (match_dup 4)
6476 (compare:CC (match_dup 0)
6477 (const_int 0)))]
6478 "")
6480 (define_insn "*rotldi3_internal7"
6481 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6482 (zero_extend:DI
6483 (subreg:QI
6484 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6485 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6486 "TARGET_POWERPC64"
6487 "@
6488 rldcl %0,%1,%2,56
6489 rldicl %0,%1,%H2,56"
6490 [(set_attr "type" "var_shift_rotate,integer")])
6492 (define_insn "*rotldi3_internal8"
6493 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6494 (compare:CC (zero_extend:DI
6495 (subreg:QI
6496 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6497 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6498 (const_int 0)))
6499 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6500 "TARGET_64BIT"
6501 "@
6502 rldcl. %3,%1,%2,56
6503 rldicl. %3,%1,%H2,56
6504 #
6505 #"
6506 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6507 (set_attr "length" "4,4,8,8")])
6509 (define_split
6510 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6511 (compare:CC (zero_extend:DI
6512 (subreg:QI
6513 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6514 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6515 (const_int 0)))
6516 (clobber (match_scratch:DI 3 ""))]
6517 "TARGET_POWERPC64 && reload_completed"
6518 [(set (match_dup 3)
6519 (zero_extend:DI (subreg:QI
6520 (rotate:DI (match_dup 1)
6521 (match_dup 2)) 0)))
6522 (set (match_dup 0)
6523 (compare:CC (match_dup 3)
6524 (const_int 0)))]
6525 "")
6527 (define_insn "*rotldi3_internal9"
6528 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6529 (compare:CC (zero_extend:DI
6530 (subreg:QI
6531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6532 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6533 (const_int 0)))
6534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6535 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6536 "TARGET_64BIT"
6537 "@
6538 rldcl. %0,%1,%2,56
6539 rldicl. %0,%1,%H2,56
6540 #
6541 #"
6542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6543 (set_attr "length" "4,4,8,8")])
6545 (define_split
6546 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6547 (compare:CC (zero_extend:DI
6548 (subreg:QI
6549 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6550 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6551 (const_int 0)))
6552 (set (match_operand:DI 0 "gpc_reg_operand" "")
6553 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6554 "TARGET_POWERPC64 && reload_completed"
6555 [(set (match_dup 0)
6556 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6557 (set (match_dup 3)
6558 (compare:CC (match_dup 0)
6559 (const_int 0)))]
6560 "")
6562 (define_insn "*rotldi3_internal10"
6563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6564 (zero_extend:DI
6565 (subreg:HI
6566 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6567 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6568 "TARGET_POWERPC64"
6569 "@
6570 rldcl %0,%1,%2,48
6571 rldicl %0,%1,%H2,48"
6572 [(set_attr "type" "var_shift_rotate,integer")])
6574 (define_insn "*rotldi3_internal11"
6575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6576 (compare:CC (zero_extend:DI
6577 (subreg:HI
6578 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6579 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6580 (const_int 0)))
6581 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6582 "TARGET_64BIT"
6583 "@
6584 rldcl. %3,%1,%2,48
6585 rldicl. %3,%1,%H2,48
6586 #
6587 #"
6588 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6589 (set_attr "length" "4,4,8,8")])
6591 (define_split
6592 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6593 (compare:CC (zero_extend:DI
6594 (subreg:HI
6595 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6596 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6597 (const_int 0)))
6598 (clobber (match_scratch:DI 3 ""))]
6599 "TARGET_POWERPC64 && reload_completed"
6600 [(set (match_dup 3)
6601 (zero_extend:DI (subreg:HI
6602 (rotate:DI (match_dup 1)
6603 (match_dup 2)) 0)))
6604 (set (match_dup 0)
6605 (compare:CC (match_dup 3)
6606 (const_int 0)))]
6607 "")
6609 (define_insn "*rotldi3_internal12"
6610 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6611 (compare:CC (zero_extend:DI
6612 (subreg:HI
6613 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6614 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6617 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6618 "TARGET_64BIT"
6619 "@
6620 rldcl. %0,%1,%2,48
6621 rldicl. %0,%1,%H2,48
6622 #
6623 #"
6624 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6625 (set_attr "length" "4,4,8,8")])
6627 (define_split
6628 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6629 (compare:CC (zero_extend:DI
6630 (subreg:HI
6631 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6632 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6633 (const_int 0)))
6634 (set (match_operand:DI 0 "gpc_reg_operand" "")
6635 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6636 "TARGET_POWERPC64 && reload_completed"
6637 [(set (match_dup 0)
6638 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6639 (set (match_dup 3)
6640 (compare:CC (match_dup 0)
6641 (const_int 0)))]
6642 "")
6644 (define_insn "*rotldi3_internal13"
6645 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6646 (zero_extend:DI
6647 (subreg:SI
6648 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6649 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
6650 "TARGET_POWERPC64"
6651 "@
6652 rldcl %0,%1,%2,32
6653 rldicl %0,%1,%H2,32"
6654 [(set_attr "type" "var_shift_rotate,integer")])
6656 (define_insn "*rotldi3_internal14"
6657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6658 (compare:CC (zero_extend:DI
6659 (subreg:SI
6660 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6661 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6664 "TARGET_64BIT"
6665 "@
6666 rldcl. %3,%1,%2,32
6667 rldicl. %3,%1,%H2,32
6668 #
6669 #"
6670 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6671 (set_attr "length" "4,4,8,8")])
6673 (define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6675 (compare:CC (zero_extend:DI
6676 (subreg:SI
6677 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6678 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6679 (const_int 0)))
6680 (clobber (match_scratch:DI 3 ""))]
6681 "TARGET_POWERPC64 && reload_completed"
6682 [(set (match_dup 3)
6683 (zero_extend:DI (subreg:SI
6684 (rotate:DI (match_dup 1)
6685 (match_dup 2)) 0)))
6686 (set (match_dup 0)
6687 (compare:CC (match_dup 3)
6688 (const_int 0)))]
6689 "")
6691 (define_insn "*rotldi3_internal15"
6692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6693 (compare:CC (zero_extend:DI
6694 (subreg:SI
6695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6696 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
6697 (const_int 0)))
6698 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6699 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6700 "TARGET_64BIT"
6701 "@
6702 rldcl. %0,%1,%2,32
6703 rldicl. %0,%1,%H2,32
6704 #
6705 #"
6706 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6707 (set_attr "length" "4,4,8,8")])
6709 (define_split
6710 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6711 (compare:CC (zero_extend:DI
6712 (subreg:SI
6713 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6714 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6715 (const_int 0)))
6716 (set (match_operand:DI 0 "gpc_reg_operand" "")
6717 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6718 "TARGET_POWERPC64 && reload_completed"
6719 [(set (match_dup 0)
6720 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6721 (set (match_dup 3)
6722 (compare:CC (match_dup 0)
6723 (const_int 0)))]
6724 "")
6726 (define_expand "ashldi3"
6727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6728 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6729 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6730 "TARGET_POWERPC64"
6731 "")
6733 (define_insn "*ashldi3_internal1"
6734 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6735 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6736 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6737 "TARGET_POWERPC64"
6738 "@
6739 sld %0,%1,%2
6740 sldi %0,%1,%H2"
6741 [(set_attr "type" "var_shift_rotate,shift")])
6743 (define_insn "*ashldi3_internal2"
6744 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6745 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6746 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6747 (const_int 0)))
6748 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6749 "TARGET_64BIT"
6750 "@
6751 sld. %3,%1,%2
6752 sldi. %3,%1,%H2
6753 #
6754 #"
6755 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6756 (set_attr "length" "4,4,8,8")])
6758 (define_split
6759 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6760 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6761 (match_operand:SI 2 "reg_or_cint_operand" ""))
6762 (const_int 0)))
6763 (clobber (match_scratch:DI 3 ""))]
6764 "TARGET_POWERPC64 && reload_completed"
6765 [(set (match_dup 3)
6766 (ashift:DI (match_dup 1) (match_dup 2)))
6767 (set (match_dup 0)
6768 (compare:CC (match_dup 3)
6769 (const_int 0)))]
6770 "")
6772 (define_insn "*ashldi3_internal3"
6773 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6774 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6775 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6776 (const_int 0)))
6777 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6778 (ashift:DI (match_dup 1) (match_dup 2)))]
6779 "TARGET_64BIT"
6780 "@
6781 sld. %0,%1,%2
6782 sldi. %0,%1,%H2
6783 #
6784 #"
6785 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6786 (set_attr "length" "4,4,8,8")])
6788 (define_split
6789 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6790 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6791 (match_operand:SI 2 "reg_or_cint_operand" ""))
6792 (const_int 0)))
6793 (set (match_operand:DI 0 "gpc_reg_operand" "")
6794 (ashift:DI (match_dup 1) (match_dup 2)))]
6795 "TARGET_POWERPC64 && reload_completed"
6796 [(set (match_dup 0)
6797 (ashift:DI (match_dup 1) (match_dup 2)))
6798 (set (match_dup 3)
6799 (compare:CC (match_dup 0)
6800 (const_int 0)))]
6801 "")
6803 (define_insn "*ashldi3_internal4"
6804 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6805 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6806 (match_operand:SI 2 "const_int_operand" "i"))
6807 (match_operand:DI 3 "const_int_operand" "n")))]
6808 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6809 "rldic %0,%1,%H2,%W3")
6811 (define_insn "ashldi3_internal5"
6812 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6813 (compare:CC
6814 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6815 (match_operand:SI 2 "const_int_operand" "i,i"))
6816 (match_operand:DI 3 "const_int_operand" "n,n"))
6817 (const_int 0)))
6818 (clobber (match_scratch:DI 4 "=r,r"))]
6819 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6820 "@
6821 rldic. %4,%1,%H2,%W3
6822 #"
6823 [(set_attr "type" "compare")
6824 (set_attr "length" "4,8")])
6826 (define_split
6827 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6828 (compare:CC
6829 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6830 (match_operand:SI 2 "const_int_operand" ""))
6831 (match_operand:DI 3 "const_int_operand" ""))
6832 (const_int 0)))
6833 (clobber (match_scratch:DI 4 ""))]
6834 "TARGET_POWERPC64 && reload_completed
6835 && includes_rldic_lshift_p (operands[2], operands[3])"
6836 [(set (match_dup 4)
6837 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6838 (match_dup 3)))
6839 (set (match_dup 0)
6840 (compare:CC (match_dup 4)
6841 (const_int 0)))]
6842 "")
6844 (define_insn "*ashldi3_internal6"
6845 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6846 (compare:CC
6847 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6848 (match_operand:SI 2 "const_int_operand" "i,i"))
6849 (match_operand:DI 3 "const_int_operand" "n,n"))
6850 (const_int 0)))
6851 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6852 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6853 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6854 "@
6855 rldic. %0,%1,%H2,%W3
6856 #"
6857 [(set_attr "type" "compare")
6858 (set_attr "length" "4,8")])
6860 (define_split
6861 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6862 (compare:CC
6863 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:SI 2 "const_int_operand" ""))
6865 (match_operand:DI 3 "const_int_operand" ""))
6866 (const_int 0)))
6867 (set (match_operand:DI 0 "gpc_reg_operand" "")
6868 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6869 "TARGET_POWERPC64 && reload_completed
6870 && includes_rldic_lshift_p (operands[2], operands[3])"
6871 [(set (match_dup 0)
6872 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6873 (match_dup 3)))
6874 (set (match_dup 4)
6875 (compare:CC (match_dup 0)
6876 (const_int 0)))]
6877 "")
6879 (define_insn "*ashldi3_internal7"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6881 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6882 (match_operand:SI 2 "const_int_operand" "i"))
6883 (match_operand:DI 3 "mask64_operand" "n")))]
6884 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6885 "rldicr %0,%1,%H2,%S3")
6887 (define_insn "ashldi3_internal8"
6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6889 (compare:CC
6890 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6891 (match_operand:SI 2 "const_int_operand" "i,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n"))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 4 "=r,r"))]
6895 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6896 "@
6897 rldicr. %4,%1,%H2,%S3
6898 #"
6899 [(set_attr "type" "compare")
6900 (set_attr "length" "4,8")])
6902 (define_split
6903 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6904 (compare:CC
6905 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6906 (match_operand:SI 2 "const_int_operand" ""))
6907 (match_operand:DI 3 "mask64_operand" ""))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 4 ""))]
6910 "TARGET_POWERPC64 && reload_completed
6911 && includes_rldicr_lshift_p (operands[2], operands[3])"
6912 [(set (match_dup 4)
6913 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6914 (match_dup 3)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 4)
6917 (const_int 0)))]
6918 "")
6920 (define_insn "*ashldi3_internal9"
6921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6922 (compare:CC
6923 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6924 (match_operand:SI 2 "const_int_operand" "i,i"))
6925 (match_operand:DI 3 "mask64_operand" "n,n"))
6926 (const_int 0)))
6927 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6928 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6929 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
6930 "@
6931 rldicr. %0,%1,%H2,%S3
6932 #"
6933 [(set_attr "type" "compare")
6934 (set_attr "length" "4,8")])
6936 (define_split
6937 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6938 (compare:CC
6939 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:SI 2 "const_int_operand" ""))
6941 (match_operand:DI 3 "mask64_operand" ""))
6942 (const_int 0)))
6943 (set (match_operand:DI 0 "gpc_reg_operand" "")
6944 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6945 "TARGET_POWERPC64 && reload_completed
6946 && includes_rldicr_lshift_p (operands[2], operands[3])"
6947 [(set (match_dup 0)
6948 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6949 (match_dup 3)))
6950 (set (match_dup 4)
6951 (compare:CC (match_dup 0)
6952 (const_int 0)))]
6953 "")
6955 (define_expand "lshrdi3"
6956 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6957 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6958 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6959 "TARGET_POWERPC64"
6960 "")
6962 (define_insn "*lshrdi3_internal1"
6963 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6964 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6965 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
6966 "TARGET_POWERPC64"
6967 "@
6968 srd %0,%1,%2
6969 srdi %0,%1,%H2"
6970 [(set_attr "type" "var_shift_rotate,shift")])
6972 (define_insn "*lshrdi3_internal2"
6973 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6974 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6975 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
6976 (const_int 0)))
6977 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6978 "TARGET_64BIT "
6979 "@
6980 srd. %3,%1,%2
6981 srdi. %3,%1,%H2
6982 #
6983 #"
6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
6987 (define_split
6988 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6989 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6990 (match_operand:SI 2 "reg_or_cint_operand" ""))
6991 (const_int 0)))
6992 (clobber (match_scratch:DI 3 ""))]
6993 "TARGET_POWERPC64 && reload_completed"
6994 [(set (match_dup 3)
6995 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6996 (set (match_dup 0)
6997 (compare:CC (match_dup 3)
6998 (const_int 0)))]
6999 "")
7001 (define_insn "*lshrdi3_internal3"
7002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7003 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7004 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7005 (const_int 0)))
7006 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7007 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7008 "TARGET_64BIT"
7009 "@
7010 srd. %0,%1,%2
7011 srdi. %0,%1,%H2
7012 #
7013 #"
7014 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7015 (set_attr "length" "4,4,8,8")])
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7019 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7020 (match_operand:SI 2 "reg_or_cint_operand" ""))
7021 (const_int 0)))
7022 (set (match_operand:DI 0 "gpc_reg_operand" "")
7023 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7024 "TARGET_POWERPC64 && reload_completed"
7025 [(set (match_dup 0)
7026 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7027 (set (match_dup 3)
7028 (compare:CC (match_dup 0)
7029 (const_int 0)))]
7030 "")
7032 (define_expand "ashrdi3"
7033 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7034 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7035 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7036 "WORDS_BIG_ENDIAN"
7037 "
7038 {
7039 if (TARGET_POWERPC64)
7040 ;
7041 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7042 && WORDS_BIG_ENDIAN)
7043 {
7044 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7045 DONE;
7046 }
7047 else
7048 FAIL;
7049 }")
7051 (define_insn "*ashrdi3_internal1"
7052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7053 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7054 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7055 "TARGET_POWERPC64"
7056 "@
7057 srad %0,%1,%2
7058 sradi %0,%1,%H2"
7059 [(set_attr "type" "var_shift_rotate,shift")])
7061 (define_insn "*ashrdi3_internal2"
7062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7063 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7064 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7065 (const_int 0)))
7066 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7067 "TARGET_64BIT"
7068 "@
7069 srad. %3,%1,%2
7070 sradi. %3,%1,%H2
7071 #
7072 #"
7073 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7074 (set_attr "length" "4,4,8,8")])
7076 (define_split
7077 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7078 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7079 (match_operand:SI 2 "reg_or_cint_operand" ""))
7080 (const_int 0)))
7081 (clobber (match_scratch:DI 3 ""))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 3)
7084 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7085 (set (match_dup 0)
7086 (compare:CC (match_dup 3)
7087 (const_int 0)))]
7088 "")
7090 (define_insn "*ashrdi3_internal3"
7091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7092 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7093 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7094 (const_int 0)))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7096 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7097 "TARGET_64BIT"
7098 "@
7099 srad. %0,%1,%2
7100 sradi. %0,%1,%H2
7101 #
7102 #"
7103 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7104 (set_attr "length" "4,4,8,8")])
7106 (define_split
7107 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7108 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7109 (match_operand:SI 2 "reg_or_cint_operand" ""))
7110 (const_int 0)))
7111 (set (match_operand:DI 0 "gpc_reg_operand" "")
7112 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7113 "TARGET_POWERPC64 && reload_completed"
7114 [(set (match_dup 0)
7115 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7116 (set (match_dup 3)
7117 (compare:CC (match_dup 0)
7118 (const_int 0)))]
7119 "")
7121 (define_expand "anddi3"
7122 [(parallel
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:DI 2 "and64_2_operand" "")))
7126 (clobber (match_scratch:CC 3 ""))])]
7127 "TARGET_POWERPC64"
7128 "")
7130 (define_insn "anddi3_mc"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7132 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7133 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7134 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7135 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7136 "@
7137 and %0,%1,%2
7138 rldic%B2 %0,%1,0,%S2
7139 rlwinm %0,%1,0,%m2,%M2
7140 andi. %0,%1,%b2
7141 andis. %0,%1,%u2
7142 #"
7143 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7144 (set_attr "length" "4,4,4,4,4,8")])
7146 (define_insn "anddi3_nomc"
7147 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7148 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7149 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7150 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7151 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7152 "@
7153 and %0,%1,%2
7154 rldic%B2 %0,%1,0,%S2
7155 rlwinm %0,%1,0,%m2,%M2
7156 #"
7157 [(set_attr "length" "4,4,4,8")])
7159 (define_split
7160 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7161 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7162 (match_operand:DI 2 "mask64_2_operand" "")))
7163 (clobber (match_scratch:CC 3 ""))]
7164 "TARGET_POWERPC64
7165 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7166 && !mask_operand (operands[2], DImode)
7167 && !mask64_operand (operands[2], DImode)"
7168 [(set (match_dup 0)
7169 (and:DI (rotate:DI (match_dup 1)
7170 (match_dup 4))
7171 (match_dup 5)))
7172 (set (match_dup 0)
7173 (and:DI (rotate:DI (match_dup 0)
7174 (match_dup 6))
7175 (match_dup 7)))]
7176 {
7177 build_mask64_2_operands (operands[2], &operands[4]);
7178 })
7180 (define_insn "*anddi3_internal2_mc"
7181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7182 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7183 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7184 (const_int 0)))
7185 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7186 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7187 "TARGET_64BIT && rs6000_gen_cell_microcode"
7188 "@
7189 and. %3,%1,%2
7190 rldic%B2. %3,%1,0,%S2
7191 rlwinm. %3,%1,0,%m2,%M2
7192 andi. %3,%1,%b2
7193 andis. %3,%1,%u2
7194 #
7195 #
7196 #
7197 #
7198 #
7199 #
7200 #"
7201 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7202 fast_compare,compare,compare,compare,compare,compare,\
7203 compare,compare")
7204 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7206 (define_split
7207 [(set (match_operand:CC 0 "cc_reg_operand" "")
7208 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7209 (match_operand:DI 2 "mask64_2_operand" ""))
7210 (const_int 0)))
7211 (clobber (match_scratch:DI 3 ""))
7212 (clobber (match_scratch:CC 4 ""))]
7213 "TARGET_64BIT && reload_completed
7214 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7215 && !mask_operand (operands[2], DImode)
7216 && !mask64_operand (operands[2], DImode)"
7217 [(set (match_dup 3)
7218 (and:DI (rotate:DI (match_dup 1)
7219 (match_dup 5))
7220 (match_dup 6)))
7221 (parallel [(set (match_dup 0)
7222 (compare:CC (and:DI (rotate:DI (match_dup 3)
7223 (match_dup 7))
7224 (match_dup 8))
7225 (const_int 0)))
7226 (clobber (match_dup 3))])]
7227 "
7228 {
7229 build_mask64_2_operands (operands[2], &operands[5]);
7230 }")
7232 (define_insn "*anddi3_internal3_mc"
7233 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7234 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7235 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7236 (const_int 0)))
7237 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7238 (and:DI (match_dup 1) (match_dup 2)))
7239 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7240 "TARGET_64BIT && rs6000_gen_cell_microcode"
7241 "@
7242 and. %0,%1,%2
7243 rldic%B2. %0,%1,0,%S2
7244 rlwinm. %0,%1,0,%m2,%M2
7245 andi. %0,%1,%b2
7246 andis. %0,%1,%u2
7247 #
7248 #
7249 #
7250 #
7251 #
7252 #
7253 #"
7254 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7255 fast_compare,compare,compare,compare,compare,compare,\
7256 compare,compare")
7257 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7259 (define_split
7260 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7261 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7262 (match_operand:DI 2 "and64_2_operand" ""))
7263 (const_int 0)))
7264 (set (match_operand:DI 0 "gpc_reg_operand" "")
7265 (and:DI (match_dup 1) (match_dup 2)))
7266 (clobber (match_scratch:CC 4 ""))]
7267 "TARGET_64BIT && reload_completed"
7268 [(parallel [(set (match_dup 0)
7269 (and:DI (match_dup 1) (match_dup 2)))
7270 (clobber (match_dup 4))])
7271 (set (match_dup 3)
7272 (compare:CC (match_dup 0)
7273 (const_int 0)))]
7274 "")
7276 (define_split
7277 [(set (match_operand:CC 3 "cc_reg_operand" "")
7278 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7279 (match_operand:DI 2 "mask64_2_operand" ""))
7280 (const_int 0)))
7281 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 (and:DI (match_dup 1) (match_dup 2)))
7283 (clobber (match_scratch:CC 4 ""))]
7284 "TARGET_64BIT && reload_completed
7285 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7286 && !mask_operand (operands[2], DImode)
7287 && !mask64_operand (operands[2], DImode)"
7288 [(set (match_dup 0)
7289 (and:DI (rotate:DI (match_dup 1)
7290 (match_dup 5))
7291 (match_dup 6)))
7292 (parallel [(set (match_dup 3)
7293 (compare:CC (and:DI (rotate:DI (match_dup 0)
7294 (match_dup 7))
7295 (match_dup 8))
7296 (const_int 0)))
7297 (set (match_dup 0)
7298 (and:DI (rotate:DI (match_dup 0)
7299 (match_dup 7))
7300 (match_dup 8)))])]
7301 "
7302 {
7303 build_mask64_2_operands (operands[2], &operands[5]);
7304 }")
7306 (define_expand "iordi3"
7307 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7308 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7309 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7310 "TARGET_POWERPC64"
7311 "
7312 {
7313 if (non_logical_cint_operand (operands[2], DImode))
7314 {
7315 HOST_WIDE_INT value;
7316 rtx tmp = ((!can_create_pseudo_p ()
7317 || rtx_equal_p (operands[0], operands[1]))
7318 ? operands[0] : gen_reg_rtx (DImode));
7320 if (GET_CODE (operands[2]) == CONST_INT)
7321 {
7322 value = INTVAL (operands[2]);
7323 emit_insn (gen_iordi3 (tmp, operands[1],
7324 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7325 }
7326 else
7327 {
7328 value = CONST_DOUBLE_LOW (operands[2]);
7329 emit_insn (gen_iordi3 (tmp, operands[1],
7330 immed_double_const (value
7331 & (~ (HOST_WIDE_INT) 0xffff),
7332 0, DImode)));
7333 }
7335 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7336 DONE;
7337 }
7338 }")
7340 (define_expand "xordi3"
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7342 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7344 "TARGET_POWERPC64"
7345 "
7346 {
7347 if (non_logical_cint_operand (operands[2], DImode))
7348 {
7349 HOST_WIDE_INT value;
7350 rtx tmp = ((!can_create_pseudo_p ()
7351 || rtx_equal_p (operands[0], operands[1]))
7352 ? operands[0] : gen_reg_rtx (DImode));
7354 if (GET_CODE (operands[2]) == CONST_INT)
7355 {
7356 value = INTVAL (operands[2]);
7357 emit_insn (gen_xordi3 (tmp, operands[1],
7358 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7359 }
7360 else
7361 {
7362 value = CONST_DOUBLE_LOW (operands[2]);
7363 emit_insn (gen_xordi3 (tmp, operands[1],
7364 immed_double_const (value
7365 & (~ (HOST_WIDE_INT) 0xffff),
7366 0, DImode)));
7367 }
7369 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7370 DONE;
7371 }
7372 }")
7374 (define_insn "*booldi3_internal1"
7375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7376 (match_operator:DI 3 "boolean_or_operator"
7377 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7378 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7379 "TARGET_POWERPC64"
7380 "@
7381 %q3 %0,%1,%2
7382 %q3i %0,%1,%b2
7383 %q3is %0,%1,%u2")
7385 (define_insn "*booldi3_internal2"
7386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7387 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7388 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7389 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7390 (const_int 0)))
7391 (clobber (match_scratch:DI 3 "=r,r"))]
7392 "TARGET_64BIT"
7393 "@
7394 %q4. %3,%1,%2
7395 #"
7396 [(set_attr "type" "fast_compare,compare")
7397 (set_attr "length" "4,8")])
7399 (define_split
7400 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7401 (compare:CC (match_operator:DI 4 "boolean_operator"
7402 [(match_operand:DI 1 "gpc_reg_operand" "")
7403 (match_operand:DI 2 "gpc_reg_operand" "")])
7404 (const_int 0)))
7405 (clobber (match_scratch:DI 3 ""))]
7406 "TARGET_POWERPC64 && reload_completed"
7407 [(set (match_dup 3) (match_dup 4))
7408 (set (match_dup 0)
7409 (compare:CC (match_dup 3)
7410 (const_int 0)))]
7411 "")
7413 (define_insn "*booldi3_internal3"
7414 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7415 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7416 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7417 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7418 (const_int 0)))
7419 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7420 (match_dup 4))]
7421 "TARGET_64BIT"
7422 "@
7423 %q4. %0,%1,%2
7424 #"
7425 [(set_attr "type" "fast_compare,compare")
7426 (set_attr "length" "4,8")])
7428 (define_split
7429 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7430 (compare:CC (match_operator:DI 4 "boolean_operator"
7431 [(match_operand:DI 1 "gpc_reg_operand" "")
7432 (match_operand:DI 2 "gpc_reg_operand" "")])
7433 (const_int 0)))
7434 (set (match_operand:DI 0 "gpc_reg_operand" "")
7435 (match_dup 4))]
7436 "TARGET_POWERPC64 && reload_completed"
7437 [(set (match_dup 0) (match_dup 4))
7438 (set (match_dup 3)
7439 (compare:CC (match_dup 0)
7440 (const_int 0)))]
7441 "")
7443 ;; Split a logical operation that we can't do in one insn into two insns,
7444 ;; each of which does one 16-bit part. This is used by combine.
7446 (define_split
7447 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7448 (match_operator:DI 3 "boolean_or_operator"
7449 [(match_operand:DI 1 "gpc_reg_operand" "")
7450 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7451 "TARGET_POWERPC64"
7452 [(set (match_dup 0) (match_dup 4))
7453 (set (match_dup 0) (match_dup 5))]
7454 "
7455 {
7456 rtx i3,i4;
7458 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7459 {
7460 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7461 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7462 0, DImode);
7463 i4 = GEN_INT (value & 0xffff);
7464 }
7465 else
7466 {
7467 i3 = GEN_INT (INTVAL (operands[2])
7468 & (~ (HOST_WIDE_INT) 0xffff));
7469 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7470 }
7471 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7472 operands[1], i3);
7473 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7474 operands[0], i4);
7475 }")
7477 (define_insn "*boolcdi3_internal1"
7478 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7479 (match_operator:DI 3 "boolean_operator"
7480 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7481 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7482 "TARGET_POWERPC64"
7483 "%q3 %0,%2,%1")
7485 (define_insn "*boolcdi3_internal2"
7486 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7487 (compare:CC (match_operator:DI 4 "boolean_operator"
7488 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7489 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7490 (const_int 0)))
7491 (clobber (match_scratch:DI 3 "=r,r"))]
7492 "TARGET_64BIT"
7493 "@
7494 %q4. %3,%2,%1
7495 #"
7496 [(set_attr "type" "fast_compare,compare")
7497 (set_attr "length" "4,8")])
7499 (define_split
7500 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7501 (compare:CC (match_operator:DI 4 "boolean_operator"
7502 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7503 (match_operand:DI 2 "gpc_reg_operand" "")])
7504 (const_int 0)))
7505 (clobber (match_scratch:DI 3 ""))]
7506 "TARGET_POWERPC64 && reload_completed"
7507 [(set (match_dup 3) (match_dup 4))
7508 (set (match_dup 0)
7509 (compare:CC (match_dup 3)
7510 (const_int 0)))]
7511 "")
7513 (define_insn "*boolcdi3_internal3"
7514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7515 (compare:CC (match_operator:DI 4 "boolean_operator"
7516 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7517 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7518 (const_int 0)))
7519 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7520 (match_dup 4))]
7521 "TARGET_64BIT"
7522 "@
7523 %q4. %0,%2,%1
7524 #"
7525 [(set_attr "type" "fast_compare,compare")
7526 (set_attr "length" "4,8")])
7528 (define_split
7529 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7530 (compare:CC (match_operator:DI 4 "boolean_operator"
7531 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7532 (match_operand:DI 2 "gpc_reg_operand" "")])
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "")
7535 (match_dup 4))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 0) (match_dup 4))
7538 (set (match_dup 3)
7539 (compare:CC (match_dup 0)
7540 (const_int 0)))]
7541 "")
7543 (define_insn "*boolccdi3_internal1"
7544 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7545 (match_operator:DI 3 "boolean_operator"
7546 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7547 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7548 "TARGET_POWERPC64"
7549 "%q3 %0,%1,%2")
7551 (define_insn "*boolccdi3_internal2"
7552 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7553 (compare:CC (match_operator:DI 4 "boolean_operator"
7554 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7555 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7556 (const_int 0)))
7557 (clobber (match_scratch:DI 3 "=r,r"))]
7558 "TARGET_64BIT"
7559 "@
7560 %q4. %3,%1,%2
7561 #"
7562 [(set_attr "type" "fast_compare,compare")
7563 (set_attr "length" "4,8")])
7565 (define_split
7566 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7567 (compare:CC (match_operator:DI 4 "boolean_operator"
7568 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7569 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7570 (const_int 0)))
7571 (clobber (match_scratch:DI 3 ""))]
7572 "TARGET_POWERPC64 && reload_completed"
7573 [(set (match_dup 3) (match_dup 4))
7574 (set (match_dup 0)
7575 (compare:CC (match_dup 3)
7576 (const_int 0)))]
7577 "")
7579 (define_insn "*boolccdi3_internal3"
7580 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7581 (compare:CC (match_operator:DI 4 "boolean_operator"
7582 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7583 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7584 (const_int 0)))
7585 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7586 (match_dup 4))]
7587 "TARGET_64BIT"
7588 "@
7589 %q4. %0,%1,%2
7590 #"
7591 [(set_attr "type" "fast_compare,compare")
7592 (set_attr "length" "4,8")])
7594 (define_split
7595 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7596 (compare:CC (match_operator:DI 4 "boolean_operator"
7597 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7598 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7599 (const_int 0)))
7600 (set (match_operand:DI 0 "gpc_reg_operand" "")
7601 (match_dup 4))]
7602 "TARGET_POWERPC64 && reload_completed"
7603 [(set (match_dup 0) (match_dup 4))
7604 (set (match_dup 3)
7605 (compare:CC (match_dup 0)
7606 (const_int 0)))]
7607 "")
7608 \f
7609 ;; Now define ways of moving data around.
7611 ;; Set up a register with a value from the GOT table
7613 (define_expand "movsi_got"
7614 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7615 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7616 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7617 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7618 "
7619 {
7620 if (GET_CODE (operands[1]) == CONST)
7621 {
7622 rtx offset = const0_rtx;
7623 HOST_WIDE_INT value;
7625 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7626 value = INTVAL (offset);
7627 if (value != 0)
7628 {
7629 rtx tmp = (!can_create_pseudo_p ()
7630 ? operands[0]
7631 : gen_reg_rtx (Pmode));
7632 emit_insn (gen_movsi_got (tmp, operands[1]));
7633 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7634 DONE;
7635 }
7636 }
7638 operands[2] = rs6000_got_register (operands[1]);
7639 }")
7641 (define_insn "*movsi_got_internal"
7642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7643 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7644 (match_operand:SI 2 "gpc_reg_operand" "b")]
7645 UNSPEC_MOVSI_GOT))]
7646 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7647 "lwz %0,%a1@got(%2)"
7648 [(set_attr "type" "load")])
7650 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7651 ;; didn't get allocated to a hard register.
7652 (define_split
7653 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7654 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7655 (match_operand:SI 2 "memory_operand" "")]
7656 UNSPEC_MOVSI_GOT))]
7657 "DEFAULT_ABI == ABI_V4
7658 && flag_pic == 1
7659 && (reload_in_progress || reload_completed)"
7660 [(set (match_dup 0) (match_dup 2))
7661 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7662 UNSPEC_MOVSI_GOT))]
7663 "")
7665 ;; For SI, we special-case integers that can't be loaded in one insn. We
7666 ;; do the load 16-bits at a time. We could do this by loading from memory,
7667 ;; and this is even supposed to be faster, but it is simpler not to get
7668 ;; integers in the TOC.
7669 (define_insn "movsi_low"
7670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7671 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7672 (match_operand 2 "" ""))))]
7673 "TARGET_MACHO && ! TARGET_64BIT"
7674 "lwz %0,lo16(%2)(%1)"
7675 [(set_attr "type" "load")
7676 (set_attr "length" "4")])
7678 (define_insn "*movsi_internal1"
7679 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
7680 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
7681 "!TARGET_SINGLE_FPU &&
7682 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7683 "@
7684 mr %0,%1
7685 la %0,%a1
7686 lwz%U1%X1 %0,%1
7687 stw%U0%X0 %1,%0
7688 li %0,%1
7689 lis %0,%v1
7690 #
7691 mf%1 %0
7692 mt%0 %1
7693 mt%0 %1
7694 nop"
7695 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
7696 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
7698 (define_insn "*movsi_internal1_single"
7699 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
7700 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
7701 "TARGET_SINGLE_FPU &&
7702 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
7703 "@
7704 mr %0,%1
7705 la %0,%a1
7706 lwz%U1%X1 %0,%1
7707 stw%U0%X0 %1,%0
7708 li %0,%1
7709 lis %0,%v1
7710 #
7711 mf%1 %0
7712 mt%0 %1
7713 mt%0 %1
7714 nop
7715 stfs%U0%X0 %1,%0
7716 lfs%U1%X1 %0,%1"
7717 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*")
7718 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7720 ;; Split a load of a large constant into the appropriate two-insn
7721 ;; sequence.
7723 (define_split
7724 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7725 (match_operand:SI 1 "const_int_operand" ""))]
7726 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7727 && (INTVAL (operands[1]) & 0xffff) != 0"
7728 [(set (match_dup 0)
7729 (match_dup 2))
7730 (set (match_dup 0)
7731 (ior:SI (match_dup 0)
7732 (match_dup 3)))]
7733 "
7734 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7736 if (tem == operands[0])
7737 DONE;
7738 else
7739 FAIL;
7740 }")
7742 (define_insn "*mov<mode>_internal2"
7743 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7744 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7745 (const_int 0)))
7746 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7747 ""
7748 "@
7749 cmp<wd>i %2,%0,0
7750 mr. %0,%1
7751 #"
7752 [(set_attr "type" "cmp,compare,cmp")
7753 (set_attr "length" "4,4,8")])
7755 (define_split
7756 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
7757 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7758 (const_int 0)))
7759 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7760 "reload_completed"
7761 [(set (match_dup 0) (match_dup 1))
7762 (set (match_dup 2)
7763 (compare:CC (match_dup 0)
7764 (const_int 0)))]
7765 "")
7766 \f
7767 (define_insn "*movhi_internal"
7768 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7769 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7770 "gpc_reg_operand (operands[0], HImode)
7771 || gpc_reg_operand (operands[1], HImode)"
7772 "@
7773 mr %0,%1
7774 lhz%U1%X1 %0,%1
7775 sth%U0%X0 %1,%0
7776 li %0,%w1
7777 mf%1 %0
7778 mt%0 %1
7779 nop"
7780 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7782 (define_expand "mov<mode>"
7783 [(set (match_operand:INT 0 "general_operand" "")
7784 (match_operand:INT 1 "any_operand" ""))]
7785 ""
7786 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7788 (define_insn "*movqi_internal"
7789 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
7790 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
7791 "gpc_reg_operand (operands[0], QImode)
7792 || gpc_reg_operand (operands[1], QImode)"
7793 "@
7794 mr %0,%1
7795 lbz%U1%X1 %0,%1
7796 stb%U0%X0 %1,%0
7797 li %0,%1
7798 mf%1 %0
7799 mt%0 %1
7800 nop"
7801 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
7802 \f
7803 ;; Here is how to move condition codes around. When we store CC data in
7804 ;; an integer register or memory, we store just the high-order 4 bits.
7805 ;; This lets us not shift in the most common case of CR0.
7806 (define_expand "movcc"
7807 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7808 (match_operand:CC 1 "nonimmediate_operand" ""))]
7809 ""
7810 "")
7812 (define_insn "*movcc_internal1"
7813 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
7814 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
7815 "register_operand (operands[0], CCmode)
7816 || register_operand (operands[1], CCmode)"
7817 "@
7818 mcrf %0,%1
7819 mtcrf 128,%1
7820 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
7821 crxor %0,%0,%0
7822 mfcr %0%Q1
7823 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
7824 mr %0,%1
7825 li %0,%1
7826 mf%1 %0
7827 mt%0 %1
7828 lwz%U1%X1 %0,%1
7829 stw%U0%U1 %1,%0"
7830 [(set (attr "type")
7831 (cond [(eq_attr "alternative" "0,3")
7832 (const_string "cr_logical")
7833 (eq_attr "alternative" "1,2")
7834 (const_string "mtcr")
7835 (eq_attr "alternative" "6,7")
7836 (const_string "integer")
7837 (eq_attr "alternative" "8")
7838 (const_string "mfjmpr")
7839 (eq_attr "alternative" "9")
7840 (const_string "mtjmpr")
7841 (eq_attr "alternative" "10")
7842 (const_string "load")
7843 (eq_attr "alternative" "11")
7844 (const_string "store")
7845 (match_test "TARGET_MFCRF")
7846 (const_string "mfcrf")
7847 ]
7848 (const_string "mfcr")))
7849 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
7850 \f
7851 ;; For floating-point, we normally deal with the floating-point registers
7852 ;; unless -msoft-float is used. The sole exception is that parameter passing
7853 ;; can produce floating-point values in fixed-point registers. Unless the
7854 ;; value is a simple constant or already in memory, we deal with this by
7855 ;; allocating memory and copying the value explicitly via that memory location.
7856 (define_expand "movsf"
7857 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7858 (match_operand:SF 1 "any_operand" ""))]
7859 ""
7860 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7862 (define_split
7863 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7864 (match_operand:SF 1 "const_double_operand" ""))]
7865 "reload_completed
7866 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7867 || (GET_CODE (operands[0]) == SUBREG
7868 && GET_CODE (SUBREG_REG (operands[0])) == REG
7869 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7870 [(set (match_dup 2) (match_dup 3))]
7871 "
7872 {
7873 long l;
7874 REAL_VALUE_TYPE rv;
7876 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7877 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7879 if (! TARGET_POWERPC64)
7880 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7881 else
7882 operands[2] = gen_lowpart (SImode, operands[0]);
7884 operands[3] = gen_int_mode (l, SImode);
7885 }")
7887 (define_insn "*movsf_hardfloat"
7888 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r")
7889 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))]
7890 "(gpc_reg_operand (operands[0], SFmode)
7891 || gpc_reg_operand (operands[1], SFmode))
7892 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
7893 "@
7894 mr %0,%1
7895 lwz%U1%X1 %0,%1
7896 stw%U0%X0 %1,%0
7897 fmr %0,%1
7898 lfs%U1%X1 %0,%1
7899 stfs%U0%X0 %1,%0
7900 mt%0 %1
7901 mf%1 %0
7902 nop
7903 #
7904 #"
7905 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*")
7906 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
7908 (define_insn "*movsf_softfloat"
7909 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
7910 (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
7911 "(gpc_reg_operand (operands[0], SFmode)
7912 || gpc_reg_operand (operands[1], SFmode))
7913 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
7914 "@
7915 mr %0,%1
7916 mt%0 %1
7917 mf%1 %0
7918 lwz%U1%X1 %0,%1
7919 stw%U0%X0 %1,%0
7920 li %0,%1
7921 lis %0,%v1
7922 #
7923 #
7924 nop"
7925 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
7926 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
7928 \f
7929 (define_expand "movdf"
7930 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7931 (match_operand:DF 1 "any_operand" ""))]
7932 ""
7933 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7935 (define_split
7936 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7937 (match_operand:DF 1 "const_int_operand" ""))]
7938 "! TARGET_POWERPC64 && reload_completed
7939 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7940 || (GET_CODE (operands[0]) == SUBREG
7941 && GET_CODE (SUBREG_REG (operands[0])) == REG
7942 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7943 [(set (match_dup 2) (match_dup 4))
7944 (set (match_dup 3) (match_dup 1))]
7945 "
7946 {
7947 int endian = (WORDS_BIG_ENDIAN == 0);
7948 HOST_WIDE_INT value = INTVAL (operands[1]);
7950 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7951 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7952 #if HOST_BITS_PER_WIDE_INT == 32
7953 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7954 #else
7955 operands[4] = GEN_INT (value >> 32);
7956 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7957 #endif
7958 }")
7960 (define_split
7961 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7962 (match_operand:DF 1 "const_double_operand" ""))]
7963 "! TARGET_POWERPC64 && reload_completed
7964 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7965 || (GET_CODE (operands[0]) == SUBREG
7966 && GET_CODE (SUBREG_REG (operands[0])) == REG
7967 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7968 [(set (match_dup 2) (match_dup 4))
7969 (set (match_dup 3) (match_dup 5))]
7970 "
7971 {
7972 int endian = (WORDS_BIG_ENDIAN == 0);
7973 long l[2];
7974 REAL_VALUE_TYPE rv;
7976 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7977 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7979 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7980 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7981 operands[4] = gen_int_mode (l[endian], SImode);
7982 operands[5] = gen_int_mode (l[1 - endian], SImode);
7983 }")
7985 (define_split
7986 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7987 (match_operand:DF 1 "const_double_operand" ""))]
7988 "TARGET_POWERPC64 && reload_completed
7989 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7990 || (GET_CODE (operands[0]) == SUBREG
7991 && GET_CODE (SUBREG_REG (operands[0])) == REG
7992 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7993 [(set (match_dup 2) (match_dup 3))]
7994 "
7995 {
7996 int endian = (WORDS_BIG_ENDIAN == 0);
7997 long l[2];
7998 REAL_VALUE_TYPE rv;
7999 #if HOST_BITS_PER_WIDE_INT >= 64
8000 HOST_WIDE_INT val;
8001 #endif
8003 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8004 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8006 operands[2] = gen_lowpart (DImode, operands[0]);
8007 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8008 #if HOST_BITS_PER_WIDE_INT >= 64
8009 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8010 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8012 operands[3] = gen_int_mode (val, DImode);
8013 #else
8014 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8015 #endif
8016 }")
8018 ;; Don't have reload use general registers to load a constant. It is
8019 ;; less efficient than loading the constant into an FP register, since
8020 ;; it will probably be used there.
8022 ;; The move constraints are ordered to prefer floating point registers before
8023 ;; general purpose registers to avoid doing a store and a load to get the value
8024 ;; into a floating point register when it is needed for a floating point
8025 ;; operation. Prefer traditional floating point registers over VSX registers,
8026 ;; since the D-form version of the memory instructions does not need a GPR for
8027 ;; reloading.
8029 (define_insn "*movdf_hardfloat32"
8030 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r")
8031 (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))]
8032 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8033 && (gpc_reg_operand (operands[0], DFmode)
8034 || gpc_reg_operand (operands[1], DFmode))"
8035 "@
8036 stfd%U0%X0 %1,%0
8037 lfd%U1%X1 %0,%1
8038 fmr %0,%1
8039 lxsd%U1x %x0,%y1
8040 lxsd%U1x %x0,%y1
8041 stxsd%U0x %x1,%y0
8042 stxsd%U0x %x1,%y0
8043 xxlor %x0,%x1,%x1
8044 xxlor %x0,%x1,%x1
8045 xxlxor %x0,%x0,%x0
8046 #
8047 #
8048 #
8049 #
8050 #
8051 #"
8052 [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*")
8053 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")])
8055 (define_insn "*movdf_softfloat32"
8056 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8057 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
8058 "! TARGET_POWERPC64
8059 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8060 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8061 && (gpc_reg_operand (operands[0], DFmode)
8062 || gpc_reg_operand (operands[1], DFmode))"
8063 "#"
8064 [(set_attr "type" "store,load,two,*,*,*")
8065 (set_attr "length" "8,8,8,8,12,16")])
8067 ;; Reload patterns to support gpr load/store with misaligned mem.
8068 ;; and multiple gpr load/store at offset >= 0xfffc
8069 (define_expand "reload_<mode>_store"
8070 [(parallel [(match_operand 0 "memory_operand" "=m")
8071 (match_operand 1 "gpc_reg_operand" "r")
8072 (match_operand:GPR 2 "register_operand" "=&b")])]
8073 ""
8074 {
8075 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8076 DONE;
8077 })
8079 (define_expand "reload_<mode>_load"
8080 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8081 (match_operand 1 "memory_operand" "m")
8082 (match_operand:GPR 2 "register_operand" "=b")])]
8083 ""
8084 {
8085 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8086 DONE;
8087 })
8089 ; ld/std require word-aligned displacements -> 'Y' constraint.
8090 ; List Y->r and r->Y before r->r for reload.
8091 (define_insn "*movdf_hardfloat64_mfpgpr"
8092 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8093 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8094 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8095 && TARGET_DOUBLE_FLOAT
8096 && (gpc_reg_operand (operands[0], DFmode)
8097 || gpc_reg_operand (operands[1], DFmode))"
8098 "@
8099 std%U0%X0 %1,%0
8100 ld%U1%X1 %0,%1
8101 mr %0,%1
8102 xxlor %x0,%x1,%x1
8103 xxlor %x0,%x1,%x1
8104 lxsd%U1x %x0,%y1
8105 lxsd%U1x %x0,%y1
8106 stxsd%U0x %x1,%y0
8107 stxsd%U0x %x1,%y0
8108 stfd%U0%X0 %1,%0
8109 lfd%U1%X1 %0,%1
8110 fmr %0,%1
8111 xxlxor %x0,%x0,%x0
8112 mt%0 %1
8113 mf%1 %0
8114 nop
8115 #
8116 #
8117 #
8118 mftgpr %0,%1
8119 mffgpr %0,%1"
8120 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8121 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8123 ; ld/std require word-aligned displacements -> 'Y' constraint.
8124 ; List Y->r and r->Y before r->r for reload.
8125 (define_insn "*movdf_hardfloat64"
8126 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r")
8127 (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))]
8128 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8129 && TARGET_DOUBLE_FLOAT
8130 && (gpc_reg_operand (operands[0], DFmode)
8131 || gpc_reg_operand (operands[1], DFmode))"
8132 "@
8133 stfd%U0%X0 %1,%0
8134 lfd%U1%X1 %0,%1
8135 fmr %0,%1
8136 std%U0%X0 %1,%0
8137 ld%U1%X1 %0,%1
8138 mr %0,%1
8139 lxsd%U1x %x0,%y1
8140 lxsd%U1x %x0,%y1
8141 stxsd%U0x %x1,%y0
8142 stxsd%U0x %x1,%y0
8143 xxlor %x0,%x1,%x1
8144 xxlor %x0,%x1,%x1
8145 xxlxor %x0,%x0,%x0
8146 mt%0 %1
8147 mf%1 %0
8148 nop
8149 #
8150 #
8151 #"
8152 [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8153 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8155 (define_insn "*movdf_softfloat64"
8156 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8157 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8158 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8159 && (gpc_reg_operand (operands[0], DFmode)
8160 || gpc_reg_operand (operands[1], DFmode))"
8161 "@
8162 std%U0%X0 %1,%0
8163 ld%U1%X1 %0,%1
8164 mr %0,%1
8165 mt%0 %1
8166 mf%1 %0
8167 #
8168 #
8169 #
8170 nop"
8171 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8172 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8173 \f
8174 (define_expand "movtf"
8175 [(set (match_operand:TF 0 "general_operand" "")
8176 (match_operand:TF 1 "any_operand" ""))]
8177 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8178 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8180 ;; It's important to list Y->r and r->Y before r->r because otherwise
8181 ;; reload, given m->r, will try to pick r->r and reload it, which
8182 ;; doesn't make progress.
8183 (define_insn_and_split "*movtf_internal"
8184 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8185 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
8186 "!TARGET_IEEEQUAD
8187 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8188 && (gpc_reg_operand (operands[0], TFmode)
8189 || gpc_reg_operand (operands[1], TFmode))"
8190 "#"
8191 "&& reload_completed"
8192 [(pc)]
8193 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8194 [(set_attr "length" "8,8,8,20,20,16")])
8196 (define_insn_and_split "*movtf_softfloat"
8197 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8198 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
8199 "!TARGET_IEEEQUAD
8200 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8201 && (gpc_reg_operand (operands[0], TFmode)
8202 || gpc_reg_operand (operands[1], TFmode))"
8203 "#"
8204 "&& reload_completed"
8205 [(pc)]
8206 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8207 [(set_attr "length" "20,20,16")])
8209 (define_expand "extenddftf2"
8210 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8211 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8212 "!TARGET_IEEEQUAD
8213 && TARGET_HARD_FLOAT
8214 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8215 && TARGET_LONG_DOUBLE_128"
8216 {
8217 if (TARGET_E500_DOUBLE)
8218 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8219 else
8220 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8221 DONE;
8222 })
8224 (define_expand "extenddftf2_fprs"
8225 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8226 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8227 (use (match_dup 2))])]
8228 "!TARGET_IEEEQUAD
8229 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8230 && TARGET_LONG_DOUBLE_128"
8231 {
8232 operands[2] = CONST0_RTX (DFmode);
8233 /* Generate GOT reference early for SVR4 PIC. */
8234 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8235 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8236 })
8238 (define_insn_and_split "*extenddftf2_internal"
8239 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8240 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8241 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8242 "!TARGET_IEEEQUAD
8243 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8244 && TARGET_LONG_DOUBLE_128"
8245 "#"
8246 "&& reload_completed"
8247 [(pc)]
8248 {
8249 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8250 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8251 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8252 operands[1]);
8253 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8254 operands[2]);
8255 DONE;
8256 })
8258 (define_expand "extendsftf2"
8259 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8260 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8261 "!TARGET_IEEEQUAD
8262 && TARGET_HARD_FLOAT
8263 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8264 && TARGET_LONG_DOUBLE_128"
8265 {
8266 rtx tmp = gen_reg_rtx (DFmode);
8267 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8268 emit_insn (gen_extenddftf2 (operands[0], tmp));
8269 DONE;
8270 })
8272 (define_expand "trunctfdf2"
8273 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8274 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8275 "!TARGET_IEEEQUAD
8276 && TARGET_HARD_FLOAT
8277 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8278 && TARGET_LONG_DOUBLE_128"
8279 "")
8281 (define_insn_and_split "trunctfdf2_internal1"
8282 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8283 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8284 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8285 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8286 "@
8287 #
8288 fmr %0,%1"
8289 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8290 [(const_int 0)]
8291 {
8292 emit_note (NOTE_INSN_DELETED);
8293 DONE;
8294 }
8295 [(set_attr "type" "fp")])
8297 (define_insn "trunctfdf2_internal2"
8298 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8299 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8300 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8301 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8302 && TARGET_LONG_DOUBLE_128"
8303 "fadd %0,%1,%L1"
8304 [(set_attr "type" "fp")
8305 (set_attr "fp_type" "fp_addsub_d")])
8307 (define_expand "trunctfsf2"
8308 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8309 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8310 "!TARGET_IEEEQUAD
8311 && TARGET_HARD_FLOAT
8312 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8313 && TARGET_LONG_DOUBLE_128"
8314 {
8315 if (TARGET_E500_DOUBLE)
8316 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8317 else
8318 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8319 DONE;
8320 })
8322 (define_insn_and_split "trunctfsf2_fprs"
8323 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8324 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8325 (clobber (match_scratch:DF 2 "=d"))]
8326 "!TARGET_IEEEQUAD
8327 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8328 && TARGET_LONG_DOUBLE_128"
8329 "#"
8330 "&& reload_completed"
8331 [(set (match_dup 2)
8332 (float_truncate:DF (match_dup 1)))
8333 (set (match_dup 0)
8334 (float_truncate:SF (match_dup 2)))]
8335 "")
8337 (define_expand "floatsitf2"
8338 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8339 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8340 "!TARGET_IEEEQUAD
8341 && TARGET_HARD_FLOAT
8342 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8343 && TARGET_LONG_DOUBLE_128"
8344 {
8345 rtx tmp = gen_reg_rtx (DFmode);
8346 expand_float (tmp, operands[1], false);
8347 emit_insn (gen_extenddftf2 (operands[0], tmp));
8348 DONE;
8349 })
8351 ; fadd, but rounding towards zero.
8352 ; This is probably not the optimal code sequence.
8353 (define_insn "fix_trunc_helper"
8354 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8355 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8356 UNSPEC_FIX_TRUNC_TF))
8357 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8358 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8359 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8360 [(set_attr "type" "fp")
8361 (set_attr "length" "20")])
8363 (define_expand "fix_trunctfsi2"
8364 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8365 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8366 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
8367 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8368 {
8369 if (TARGET_E500_DOUBLE)
8370 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8371 else
8372 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8373 DONE;
8374 })
8376 (define_expand "fix_trunctfsi2_fprs"
8377 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8378 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8379 (clobber (match_dup 2))
8380 (clobber (match_dup 3))
8381 (clobber (match_dup 4))
8382 (clobber (match_dup 5))])]
8383 "!TARGET_IEEEQUAD
8384 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8385 {
8386 operands[2] = gen_reg_rtx (DFmode);
8387 operands[3] = gen_reg_rtx (DFmode);
8388 operands[4] = gen_reg_rtx (DImode);
8389 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8390 })
8392 (define_insn_and_split "*fix_trunctfsi2_internal"
8393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8394 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8395 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8396 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8397 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8398 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8399 "!TARGET_IEEEQUAD
8400 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8401 "#"
8402 ""
8403 [(pc)]
8404 {
8405 rtx lowword;
8406 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8408 gcc_assert (MEM_P (operands[5]));
8409 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8411 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
8412 emit_move_insn (operands[5], operands[4]);
8413 emit_move_insn (operands[0], lowword);
8414 DONE;
8415 })
8417 (define_expand "negtf2"
8418 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8419 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8420 "!TARGET_IEEEQUAD
8421 && TARGET_HARD_FLOAT
8422 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8423 && TARGET_LONG_DOUBLE_128"
8424 "")
8426 (define_insn "negtf2_internal"
8427 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8428 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8429 "!TARGET_IEEEQUAD
8430 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8431 "*
8432 {
8433 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8434 return \"fneg %L0,%L1\;fneg %0,%1\";
8435 else
8436 return \"fneg %0,%1\;fneg %L0,%L1\";
8437 }"
8438 [(set_attr "type" "fp")
8439 (set_attr "length" "8")])
8441 (define_expand "abstf2"
8442 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8443 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8444 "!TARGET_IEEEQUAD
8445 && TARGET_HARD_FLOAT
8446 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8447 && TARGET_LONG_DOUBLE_128"
8448 "
8449 {
8450 rtx label = gen_label_rtx ();
8451 if (TARGET_E500_DOUBLE)
8452 {
8453 if (flag_finite_math_only && !flag_trapping_math)
8454 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8455 else
8456 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8457 }
8458 else
8459 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8460 emit_label (label);
8461 DONE;
8462 }")
8464 (define_expand "abstf2_internal"
8465 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8466 (match_operand:TF 1 "gpc_reg_operand" ""))
8467 (set (match_dup 3) (match_dup 5))
8468 (set (match_dup 5) (abs:DF (match_dup 5)))
8469 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8470 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8471 (label_ref (match_operand 2 "" ""))
8472 (pc)))
8473 (set (match_dup 6) (neg:DF (match_dup 6)))]
8474 "!TARGET_IEEEQUAD
8475 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8476 && TARGET_LONG_DOUBLE_128"
8477 "
8478 {
8479 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8480 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8481 operands[3] = gen_reg_rtx (DFmode);
8482 operands[4] = gen_reg_rtx (CCFPmode);
8483 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8484 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8485 }")
8486 \f
8487 ;; Next come the multi-word integer load and store and the load and store
8488 ;; multiple insns.
8490 ;; List r->r after r->Y, otherwise reload will try to reload a
8491 ;; non-offsettable address by using r->r which won't make progress.
8492 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
8493 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
8494 (define_insn "*movdi_internal32"
8495 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
8496 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
8497 "! TARGET_POWERPC64
8498 && (gpc_reg_operand (operands[0], DImode)
8499 || gpc_reg_operand (operands[1], DImode))"
8500 "@
8501 #
8502 #
8503 #
8504 stfd%U0%X0 %1,%0
8505 lfd%U1%X1 %0,%1
8506 fmr %0,%1
8507 #
8508 xxlxor %x0,%x0,%x0"
8509 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
8511 (define_split
8512 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8513 (match_operand:DI 1 "const_int_operand" ""))]
8514 "! TARGET_POWERPC64 && reload_completed
8515 && gpr_or_gpr_p (operands[0], operands[1])"
8516 [(set (match_dup 2) (match_dup 4))
8517 (set (match_dup 3) (match_dup 1))]
8518 "
8519 {
8520 HOST_WIDE_INT value = INTVAL (operands[1]);
8521 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8522 DImode);
8523 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8524 DImode);
8525 #if HOST_BITS_PER_WIDE_INT == 32
8526 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8527 #else
8528 operands[4] = GEN_INT (value >> 32);
8529 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8530 #endif
8531 }")
8533 (define_split
8534 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
8535 (match_operand:DIFD 1 "input_operand" ""))]
8536 "reload_completed && !TARGET_POWERPC64
8537 && gpr_or_gpr_p (operands[0], operands[1])"
8538 [(pc)]
8539 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8541 (define_insn "*movdi_mfpgpr"
8542 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
8543 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
8544 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8545 && (gpc_reg_operand (operands[0], DImode)
8546 || gpc_reg_operand (operands[1], DImode))"
8547 "@
8548 std%U0%X0 %1,%0
8549 ld%U1%X1 %0,%1
8550 mr %0,%1
8551 li %0,%1
8552 lis %0,%v1
8553 #
8554 stfd%U0%X0 %1,%0
8555 lfd%U1%X1 %0,%1
8556 fmr %0,%1
8557 mf%1 %0
8558 mt%0 %1
8559 nop
8560 mftgpr %0,%1
8561 mffgpr %0,%1"
8562 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8563 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
8565 (define_insn "*movdi_internal64"
8566 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
8567 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
8568 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
8569 && (gpc_reg_operand (operands[0], DImode)
8570 || gpc_reg_operand (operands[1], DImode))"
8571 "@
8572 std%U0%X0 %1,%0
8573 ld%U1%X1 %0,%1
8574 mr %0,%1
8575 li %0,%1
8576 lis %0,%v1
8577 #
8578 stfd%U0%X0 %1,%0
8579 lfd%U1%X1 %0,%1
8580 fmr %0,%1
8581 mf%1 %0
8582 mt%0 %1
8583 nop
8584 xxlxor %x0,%x0,%x0"
8585 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
8586 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8588 ;; immediate value valid for a single instruction hiding in a const_double
8589 (define_insn ""
8590 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8591 (match_operand:DI 1 "const_double_operand" "F"))]
8592 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8593 && GET_CODE (operands[1]) == CONST_DOUBLE
8594 && num_insns_constant (operands[1], DImode) == 1"
8595 "*
8596 {
8597 return ((unsigned HOST_WIDE_INT)
8598 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8599 ? \"li %0,%1\" : \"lis %0,%v1\";
8600 }")
8602 ;; Generate all one-bits and clear left or right.
8603 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8604 (define_split
8605 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8606 (match_operand:DI 1 "mask64_operand" ""))]
8607 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8608 [(set (match_dup 0) (const_int -1))
8609 (set (match_dup 0)
8610 (and:DI (rotate:DI (match_dup 0)
8611 (const_int 0))
8612 (match_dup 1)))]
8613 "")
8615 ;; Split a load of a large constant into the appropriate five-instruction
8616 ;; sequence. Handle anything in a constant number of insns.
8617 ;; When non-easy constants can go in the TOC, this should use
8618 ;; easy_fp_constant predicate.
8619 (define_split
8620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8621 (match_operand:DI 1 "const_int_operand" ""))]
8622 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8623 [(set (match_dup 0) (match_dup 2))
8624 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8625 "
8626 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8628 if (tem == operands[0])
8629 DONE;
8630 else
8631 FAIL;
8632 }")
8634 (define_split
8635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8636 (match_operand:DI 1 "const_double_operand" ""))]
8637 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8638 [(set (match_dup 0) (match_dup 2))
8639 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8640 "
8641 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8643 if (tem == operands[0])
8644 DONE;
8645 else
8646 FAIL;
8647 }")
8648 \f
8649 ;; TImode is similar, except that we usually want to compute the address into
8650 ;; a register and use lsi/stsi (the exception is during reload).
8652 (define_insn "*movti_string"
8653 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8654 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
8655 "! TARGET_POWERPC64
8656 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8657 "*
8658 {
8659 switch (which_alternative)
8660 {
8661 default:
8662 gcc_unreachable ();
8663 case 0:
8664 if (TARGET_STRING)
8665 return \"stswi %1,%P0,16\";
8666 case 1:
8667 return \"#\";
8668 case 2:
8669 /* If the address is not used in the output, we can use lsi. Otherwise,
8670 fall through to generating four loads. */
8671 if (TARGET_STRING
8672 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8673 return \"lswi %0,%P1,16\";
8674 /* ... fall through ... */
8675 case 3:
8676 case 4:
8677 case 5:
8678 return \"#\";
8679 }
8680 }"
8681 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
8682 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8683 (const_string "always")
8684 (const_string "conditional")))])
8686 (define_insn "*movti_ppc64"
8687 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
8688 (match_operand:TI 1 "input_operand" "r,Y,r"))]
8689 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8690 || gpc_reg_operand (operands[1], TImode)))
8691 && VECTOR_MEM_NONE_P (TImode)"
8692 "#"
8693 [(set_attr "type" "store,load,*")])
8695 (define_split
8696 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8697 (match_operand:TI 1 "const_double_operand" ""))]
8698 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
8699 [(set (match_dup 2) (match_dup 4))
8700 (set (match_dup 3) (match_dup 5))]
8701 "
8702 {
8703 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8704 TImode);
8705 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8706 TImode);
8707 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8708 {
8709 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8710 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8711 }
8712 else if (GET_CODE (operands[1]) == CONST_INT)
8713 {
8714 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8715 operands[5] = operands[1];
8716 }
8717 else
8718 FAIL;
8719 }")
8721 (define_split
8722 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8723 (match_operand:TI 1 "input_operand" ""))]
8724 "reload_completed && VECTOR_MEM_NONE_P (TImode)
8725 && gpr_or_gpr_p (operands[0], operands[1])"
8726 [(pc)]
8727 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8728 \f
8729 (define_expand "load_multiple"
8730 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8731 (match_operand:SI 1 "" ""))
8732 (use (match_operand:SI 2 "" ""))])]
8733 "TARGET_STRING && !TARGET_POWERPC64"
8734 "
8735 {
8736 int regno;
8737 int count;
8738 rtx op1;
8739 int i;
8741 /* Support only loading a constant number of fixed-point registers from
8742 memory and only bother with this if more than two; the machine
8743 doesn't support more than eight. */
8744 if (GET_CODE (operands[2]) != CONST_INT
8745 || INTVAL (operands[2]) <= 2
8746 || INTVAL (operands[2]) > 8
8747 || GET_CODE (operands[1]) != MEM
8748 || GET_CODE (operands[0]) != REG
8749 || REGNO (operands[0]) >= 32)
8750 FAIL;
8752 count = INTVAL (operands[2]);
8753 regno = REGNO (operands[0]);
8755 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8756 op1 = replace_equiv_address (operands[1],
8757 force_reg (SImode, XEXP (operands[1], 0)));
8759 for (i = 0; i < count; i++)
8760 XVECEXP (operands[3], 0, i)
8761 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8762 adjust_address_nv (op1, SImode, i * 4));
8763 }")
8765 (define_insn "*ldmsi8"
8766 [(match_parallel 0 "load_multiple_operation"
8767 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8768 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8769 (set (match_operand:SI 3 "gpc_reg_operand" "")
8770 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8771 (set (match_operand:SI 4 "gpc_reg_operand" "")
8772 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8773 (set (match_operand:SI 5 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8775 (set (match_operand:SI 6 "gpc_reg_operand" "")
8776 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8777 (set (match_operand:SI 7 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8779 (set (match_operand:SI 8 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8781 (set (match_operand:SI 9 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8783 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8784 "*
8785 { return rs6000_output_load_multiple (operands); }"
8786 [(set_attr "type" "load_ux")
8787 (set_attr "length" "32")])
8789 (define_insn "*ldmsi7"
8790 [(match_parallel 0 "load_multiple_operation"
8791 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8792 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8793 (set (match_operand:SI 3 "gpc_reg_operand" "")
8794 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8795 (set (match_operand:SI 4 "gpc_reg_operand" "")
8796 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8797 (set (match_operand:SI 5 "gpc_reg_operand" "")
8798 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8799 (set (match_operand:SI 6 "gpc_reg_operand" "")
8800 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8801 (set (match_operand:SI 7 "gpc_reg_operand" "")
8802 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8803 (set (match_operand:SI 8 "gpc_reg_operand" "")
8804 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8805 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8806 "*
8807 { return rs6000_output_load_multiple (operands); }"
8808 [(set_attr "type" "load_ux")
8809 (set_attr "length" "32")])
8811 (define_insn "*ldmsi6"
8812 [(match_parallel 0 "load_multiple_operation"
8813 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8814 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8815 (set (match_operand:SI 3 "gpc_reg_operand" "")
8816 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8817 (set (match_operand:SI 4 "gpc_reg_operand" "")
8818 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8819 (set (match_operand:SI 5 "gpc_reg_operand" "")
8820 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8821 (set (match_operand:SI 6 "gpc_reg_operand" "")
8822 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8823 (set (match_operand:SI 7 "gpc_reg_operand" "")
8824 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8825 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8826 "*
8827 { return rs6000_output_load_multiple (operands); }"
8828 [(set_attr "type" "load_ux")
8829 (set_attr "length" "32")])
8831 (define_insn "*ldmsi5"
8832 [(match_parallel 0 "load_multiple_operation"
8833 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8834 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8835 (set (match_operand:SI 3 "gpc_reg_operand" "")
8836 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8837 (set (match_operand:SI 4 "gpc_reg_operand" "")
8838 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8839 (set (match_operand:SI 5 "gpc_reg_operand" "")
8840 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8841 (set (match_operand:SI 6 "gpc_reg_operand" "")
8842 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8843 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8844 "*
8845 { return rs6000_output_load_multiple (operands); }"
8846 [(set_attr "type" "load_ux")
8847 (set_attr "length" "32")])
8849 (define_insn "*ldmsi4"
8850 [(match_parallel 0 "load_multiple_operation"
8851 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8852 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8853 (set (match_operand:SI 3 "gpc_reg_operand" "")
8854 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8855 (set (match_operand:SI 4 "gpc_reg_operand" "")
8856 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8857 (set (match_operand:SI 5 "gpc_reg_operand" "")
8858 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8859 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8860 "*
8861 { return rs6000_output_load_multiple (operands); }"
8862 [(set_attr "type" "load_ux")
8863 (set_attr "length" "32")])
8865 (define_insn "*ldmsi3"
8866 [(match_parallel 0 "load_multiple_operation"
8867 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8868 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8869 (set (match_operand:SI 3 "gpc_reg_operand" "")
8870 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8871 (set (match_operand:SI 4 "gpc_reg_operand" "")
8872 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8873 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8874 "*
8875 { return rs6000_output_load_multiple (operands); }"
8876 [(set_attr "type" "load_ux")
8877 (set_attr "length" "32")])
8879 (define_expand "store_multiple"
8880 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8881 (match_operand:SI 1 "" ""))
8882 (clobber (scratch:SI))
8883 (use (match_operand:SI 2 "" ""))])]
8884 "TARGET_STRING && !TARGET_POWERPC64"
8885 "
8886 {
8887 int regno;
8888 int count;
8889 rtx to;
8890 rtx op0;
8891 int i;
8893 /* Support only storing a constant number of fixed-point registers to
8894 memory and only bother with this if more than two; the machine
8895 doesn't support more than eight. */
8896 if (GET_CODE (operands[2]) != CONST_INT
8897 || INTVAL (operands[2]) <= 2
8898 || INTVAL (operands[2]) > 8
8899 || GET_CODE (operands[0]) != MEM
8900 || GET_CODE (operands[1]) != REG
8901 || REGNO (operands[1]) >= 32)
8902 FAIL;
8904 count = INTVAL (operands[2]);
8905 regno = REGNO (operands[1]);
8907 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8908 to = force_reg (SImode, XEXP (operands[0], 0));
8909 op0 = replace_equiv_address (operands[0], to);
8911 XVECEXP (operands[3], 0, 0)
8912 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8913 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8914 gen_rtx_SCRATCH (SImode));
8916 for (i = 1; i < count; i++)
8917 XVECEXP (operands[3], 0, i + 1)
8918 = gen_rtx_SET (VOIDmode,
8919 adjust_address_nv (op0, SImode, i * 4),
8920 gen_rtx_REG (SImode, regno + i));
8921 }")
8923 (define_insn "*stmsi8"
8924 [(match_parallel 0 "store_multiple_operation"
8925 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8926 (match_operand:SI 2 "gpc_reg_operand" "r"))
8927 (clobber (match_scratch:SI 3 "=X"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8929 (match_operand:SI 4 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8931 (match_operand:SI 5 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8933 (match_operand:SI 6 "gpc_reg_operand" "r"))
8934 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8935 (match_operand:SI 7 "gpc_reg_operand" "r"))
8936 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8937 (match_operand:SI 8 "gpc_reg_operand" "r"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8939 (match_operand:SI 9 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8941 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8942 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
8943 "stswi %2,%1,%O0"
8944 [(set_attr "type" "store_ux")
8945 (set_attr "cell_micro" "always")])
8947 (define_insn "*stmsi7"
8948 [(match_parallel 0 "store_multiple_operation"
8949 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8950 (match_operand:SI 2 "gpc_reg_operand" "r"))
8951 (clobber (match_scratch:SI 3 "=X"))
8952 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8953 (match_operand:SI 4 "gpc_reg_operand" "r"))
8954 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8955 (match_operand:SI 5 "gpc_reg_operand" "r"))
8956 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8957 (match_operand:SI 6 "gpc_reg_operand" "r"))
8958 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8959 (match_operand:SI 7 "gpc_reg_operand" "r"))
8960 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8961 (match_operand:SI 8 "gpc_reg_operand" "r"))
8962 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8963 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8964 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8965 "stswi %2,%1,%O0"
8966 [(set_attr "type" "store_ux")
8967 (set_attr "cell_micro" "always")])
8969 (define_insn "*stmsi6"
8970 [(match_parallel 0 "store_multiple_operation"
8971 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8972 (match_operand:SI 2 "gpc_reg_operand" "r"))
8973 (clobber (match_scratch:SI 3 "=X"))
8974 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8975 (match_operand:SI 4 "gpc_reg_operand" "r"))
8976 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8977 (match_operand:SI 5 "gpc_reg_operand" "r"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8979 (match_operand:SI 6 "gpc_reg_operand" "r"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8981 (match_operand:SI 7 "gpc_reg_operand" "r"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8983 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8984 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8985 "stswi %2,%1,%O0"
8986 [(set_attr "type" "store_ux")
8987 (set_attr "cell_micro" "always")])
8989 (define_insn "*stmsi5"
8990 [(match_parallel 0 "store_multiple_operation"
8991 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8992 (match_operand:SI 2 "gpc_reg_operand" "r"))
8993 (clobber (match_scratch:SI 3 "=X"))
8994 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8995 (match_operand:SI 4 "gpc_reg_operand" "r"))
8996 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8997 (match_operand:SI 5 "gpc_reg_operand" "r"))
8998 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8999 (match_operand:SI 6 "gpc_reg_operand" "r"))
9000 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9001 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9002 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9003 "stswi %2,%1,%O0"
9004 [(set_attr "type" "store_ux")
9005 (set_attr "cell_micro" "always")])
9007 (define_insn "*stmsi4"
9008 [(match_parallel 0 "store_multiple_operation"
9009 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9010 (match_operand:SI 2 "gpc_reg_operand" "r"))
9011 (clobber (match_scratch:SI 3 "=X"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9013 (match_operand:SI 4 "gpc_reg_operand" "r"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9015 (match_operand:SI 5 "gpc_reg_operand" "r"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9017 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9018 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9019 "stswi %2,%1,%O0"
9020 [(set_attr "type" "store_ux")
9021 (set_attr "cell_micro" "always")])
9023 (define_insn "*stmsi3"
9024 [(match_parallel 0 "store_multiple_operation"
9025 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9026 (match_operand:SI 2 "gpc_reg_operand" "r"))
9027 (clobber (match_scratch:SI 3 "=X"))
9028 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9029 (match_operand:SI 4 "gpc_reg_operand" "r"))
9030 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9031 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9032 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9033 "stswi %2,%1,%O0"
9034 [(set_attr "type" "store_ux")
9035 (set_attr "cell_micro" "always")])
9036 \f
9037 (define_expand "setmemsi"
9038 [(parallel [(set (match_operand:BLK 0 "" "")
9039 (match_operand 2 "const_int_operand" ""))
9040 (use (match_operand:SI 1 "" ""))
9041 (use (match_operand:SI 3 "" ""))])]
9042 ""
9043 "
9044 {
9045 /* If value to set is not zero, use the library routine. */
9046 if (operands[2] != const0_rtx)
9047 FAIL;
9049 if (expand_block_clear (operands))
9050 DONE;
9051 else
9052 FAIL;
9053 }")
9055 ;; String/block move insn.
9056 ;; Argument 0 is the destination
9057 ;; Argument 1 is the source
9058 ;; Argument 2 is the length
9059 ;; Argument 3 is the alignment
9061 (define_expand "movmemsi"
9062 [(parallel [(set (match_operand:BLK 0 "" "")
9063 (match_operand:BLK 1 "" ""))
9064 (use (match_operand:SI 2 "" ""))
9065 (use (match_operand:SI 3 "" ""))])]
9066 ""
9067 "
9068 {
9069 if (expand_block_move (operands))
9070 DONE;
9071 else
9072 FAIL;
9073 }")
9075 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9076 ;; register allocator doesn't have a clue about allocating 8 word registers.
9077 ;; rD/rS = r5 is preferred, efficient form.
9078 (define_expand "movmemsi_8reg"
9079 [(parallel [(set (match_operand 0 "" "")
9080 (match_operand 1 "" ""))
9081 (use (match_operand 2 "" ""))
9082 (use (match_operand 3 "" ""))
9083 (clobber (reg:SI 5))
9084 (clobber (reg:SI 6))
9085 (clobber (reg:SI 7))
9086 (clobber (reg:SI 8))
9087 (clobber (reg:SI 9))
9088 (clobber (reg:SI 10))
9089 (clobber (reg:SI 11))
9090 (clobber (reg:SI 12))
9091 (clobber (match_scratch:SI 4 ""))])]
9092 "TARGET_STRING"
9093 "")
9095 (define_insn ""
9096 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9097 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9098 (use (match_operand:SI 2 "immediate_operand" "i"))
9099 (use (match_operand:SI 3 "immediate_operand" "i"))
9100 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9101 (clobber (reg:SI 6))
9102 (clobber (reg:SI 7))
9103 (clobber (reg:SI 8))
9104 (clobber (reg:SI 9))
9105 (clobber (reg:SI 10))
9106 (clobber (reg:SI 11))
9107 (clobber (reg:SI 12))
9108 (clobber (match_scratch:SI 5 "=X"))]
9109 "TARGET_STRING
9110 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9111 || INTVAL (operands[2]) == 0)
9112 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9113 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9114 && REGNO (operands[4]) == 5"
9115 "lswi %4,%1,%2\;stswi %4,%0,%2"
9116 [(set_attr "type" "store_ux")
9117 (set_attr "cell_micro" "always")
9118 (set_attr "length" "8")])
9120 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9121 ;; register allocator doesn't have a clue about allocating 6 word registers.
9122 ;; rD/rS = r5 is preferred, efficient form.
9123 (define_expand "movmemsi_6reg"
9124 [(parallel [(set (match_operand 0 "" "")
9125 (match_operand 1 "" ""))
9126 (use (match_operand 2 "" ""))
9127 (use (match_operand 3 "" ""))
9128 (clobber (reg:SI 5))
9129 (clobber (reg:SI 6))
9130 (clobber (reg:SI 7))
9131 (clobber (reg:SI 8))
9132 (clobber (reg:SI 9))
9133 (clobber (reg:SI 10))
9134 (clobber (match_scratch:SI 4 ""))])]
9135 "TARGET_STRING"
9136 "")
9138 (define_insn ""
9139 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9140 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9141 (use (match_operand:SI 2 "immediate_operand" "i"))
9142 (use (match_operand:SI 3 "immediate_operand" "i"))
9143 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9144 (clobber (reg:SI 6))
9145 (clobber (reg:SI 7))
9146 (clobber (reg:SI 8))
9147 (clobber (reg:SI 9))
9148 (clobber (reg:SI 10))
9149 (clobber (match_scratch:SI 5 "=X"))]
9150 "TARGET_STRING
9151 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9152 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9153 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9154 && REGNO (operands[4]) == 5"
9155 "lswi %4,%1,%2\;stswi %4,%0,%2"
9156 [(set_attr "type" "store_ux")
9157 (set_attr "cell_micro" "always")
9158 (set_attr "length" "8")])
9160 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9161 ;; problems with TImode.
9162 ;; rD/rS = r5 is preferred, efficient form.
9163 (define_expand "movmemsi_4reg"
9164 [(parallel [(set (match_operand 0 "" "")
9165 (match_operand 1 "" ""))
9166 (use (match_operand 2 "" ""))
9167 (use (match_operand 3 "" ""))
9168 (clobber (reg:SI 5))
9169 (clobber (reg:SI 6))
9170 (clobber (reg:SI 7))
9171 (clobber (reg:SI 8))
9172 (clobber (match_scratch:SI 4 ""))])]
9173 "TARGET_STRING"
9174 "")
9176 (define_insn ""
9177 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9178 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9179 (use (match_operand:SI 2 "immediate_operand" "i"))
9180 (use (match_operand:SI 3 "immediate_operand" "i"))
9181 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9182 (clobber (reg:SI 6))
9183 (clobber (reg:SI 7))
9184 (clobber (reg:SI 8))
9185 (clobber (match_scratch:SI 5 "=X"))]
9186 "TARGET_STRING
9187 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9188 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9189 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9190 && REGNO (operands[4]) == 5"
9191 "lswi %4,%1,%2\;stswi %4,%0,%2"
9192 [(set_attr "type" "store_ux")
9193 (set_attr "cell_micro" "always")
9194 (set_attr "length" "8")])
9196 ;; Move up to 8 bytes at a time.
9197 (define_expand "movmemsi_2reg"
9198 [(parallel [(set (match_operand 0 "" "")
9199 (match_operand 1 "" ""))
9200 (use (match_operand 2 "" ""))
9201 (use (match_operand 3 "" ""))
9202 (clobber (match_scratch:DI 4 ""))
9203 (clobber (match_scratch:SI 5 ""))])]
9204 "TARGET_STRING && ! TARGET_POWERPC64"
9205 "")
9207 (define_insn ""
9208 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9209 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9210 (use (match_operand:SI 2 "immediate_operand" "i"))
9211 (use (match_operand:SI 3 "immediate_operand" "i"))
9212 (clobber (match_scratch:DI 4 "=&r"))
9213 (clobber (match_scratch:SI 5 "=X"))]
9214 "TARGET_STRING && ! TARGET_POWERPC64
9215 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9216 "lswi %4,%1,%2\;stswi %4,%0,%2"
9217 [(set_attr "type" "store_ux")
9218 (set_attr "cell_micro" "always")
9219 (set_attr "length" "8")])
9221 ;; Move up to 4 bytes at a time.
9222 (define_expand "movmemsi_1reg"
9223 [(parallel [(set (match_operand 0 "" "")
9224 (match_operand 1 "" ""))
9225 (use (match_operand 2 "" ""))
9226 (use (match_operand 3 "" ""))
9227 (clobber (match_scratch:SI 4 ""))
9228 (clobber (match_scratch:SI 5 ""))])]
9229 "TARGET_STRING"
9230 "")
9232 (define_insn ""
9233 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9234 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9235 (use (match_operand:SI 2 "immediate_operand" "i"))
9236 (use (match_operand:SI 3 "immediate_operand" "i"))
9237 (clobber (match_scratch:SI 4 "=&r"))
9238 (clobber (match_scratch:SI 5 "=X"))]
9239 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9240 "lswi %4,%1,%2\;stswi %4,%0,%2"
9241 [(set_attr "type" "store_ux")
9242 (set_attr "cell_micro" "always")
9243 (set_attr "length" "8")])
9244 \f
9245 ;; Define insns that do load or store with update. Some of these we can
9246 ;; get by using pre-decrement or pre-increment, but the hardware can also
9247 ;; do cases where the increment is not the size of the object.
9248 ;;
9249 ;; In all these cases, we use operands 0 and 1 for the register being
9250 ;; incremented because those are the operands that local-alloc will
9251 ;; tie and these are the pair most likely to be tieable (and the ones
9252 ;; that will benefit the most).
9254 (define_insn "*movdi_update1"
9255 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9256 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9257 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9258 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9259 (plus:DI (match_dup 1) (match_dup 2)))]
9260 "TARGET_POWERPC64 && TARGET_UPDATE
9261 && (!avoiding_indexed_address_p (DImode)
9262 || !gpc_reg_operand (operands[2], DImode))"
9263 "@
9264 ldux %3,%0,%2
9265 ldu %3,%2(%0)"
9266 [(set_attr "type" "load_ux,load_u")])
9268 (define_insn "movdi_<mode>_update"
9269 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9270 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9271 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9272 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9273 (plus:P (match_dup 1) (match_dup 2)))]
9274 "TARGET_POWERPC64 && TARGET_UPDATE
9275 && (!avoiding_indexed_address_p (Pmode)
9276 || !gpc_reg_operand (operands[2], Pmode)
9277 || (REG_P (operands[0])
9278 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9279 "@
9280 stdux %3,%0,%2
9281 stdu %3,%2(%0)"
9282 [(set_attr "type" "store_ux,store_u")])
9284 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9285 ;; needed for stack allocation, even if the user passes -mno-update.
9286 (define_insn "movdi_<mode>_update_stack"
9287 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9288 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9289 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9290 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9291 (plus:P (match_dup 1) (match_dup 2)))]
9292 "TARGET_POWERPC64"
9293 "@
9294 stdux %3,%0,%2
9295 stdu %3,%2(%0)"
9296 [(set_attr "type" "store_ux,store_u")])
9298 (define_insn "*movsi_update1"
9299 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9300 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9301 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9302 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9303 (plus:SI (match_dup 1) (match_dup 2)))]
9304 "TARGET_UPDATE
9305 && (!avoiding_indexed_address_p (SImode)
9306 || !gpc_reg_operand (operands[2], SImode))"
9307 "@
9308 lwzux %3,%0,%2
9309 lwzu %3,%2(%0)"
9310 [(set_attr "type" "load_ux,load_u")])
9312 (define_insn "*movsi_update2"
9313 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9314 (sign_extend:DI
9315 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9316 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9317 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9318 (plus:DI (match_dup 1) (match_dup 2)))]
9319 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9320 && !avoiding_indexed_address_p (DImode)"
9321 "lwaux %3,%0,%2"
9322 [(set_attr "type" "load_ext_ux")])
9324 (define_insn "movsi_update"
9325 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9326 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9327 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9328 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9329 (plus:SI (match_dup 1) (match_dup 2)))]
9330 "TARGET_UPDATE
9331 && (!avoiding_indexed_address_p (SImode)
9332 || !gpc_reg_operand (operands[2], SImode)
9333 || (REG_P (operands[0])
9334 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9335 "@
9336 stwux %3,%0,%2
9337 stwu %3,%2(%0)"
9338 [(set_attr "type" "store_ux,store_u")])
9340 ;; This is an unconditional pattern; needed for stack allocation, even
9341 ;; if the user passes -mno-update.
9342 (define_insn "movsi_update_stack"
9343 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9344 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9345 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9346 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9347 (plus:SI (match_dup 1) (match_dup 2)))]
9348 ""
9349 "@
9350 stwux %3,%0,%2
9351 stwu %3,%2(%0)"
9352 [(set_attr "type" "store_ux,store_u")])
9354 (define_insn "*movhi_update1"
9355 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9356 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9357 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9358 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9359 (plus:SI (match_dup 1) (match_dup 2)))]
9360 "TARGET_UPDATE
9361 && (!avoiding_indexed_address_p (SImode)
9362 || !gpc_reg_operand (operands[2], SImode))"
9363 "@
9364 lhzux %3,%0,%2
9365 lhzu %3,%2(%0)"
9366 [(set_attr "type" "load_ux,load_u")])
9368 (define_insn "*movhi_update2"
9369 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9370 (zero_extend:SI
9371 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9372 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9373 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9374 (plus:SI (match_dup 1) (match_dup 2)))]
9375 "TARGET_UPDATE
9376 && (!avoiding_indexed_address_p (SImode)
9377 || !gpc_reg_operand (operands[2], SImode))"
9378 "@
9379 lhzux %3,%0,%2
9380 lhzu %3,%2(%0)"
9381 [(set_attr "type" "load_ux,load_u")])
9383 (define_insn "*movhi_update3"
9384 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9385 (sign_extend:SI
9386 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9387 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9388 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9389 (plus:SI (match_dup 1) (match_dup 2)))]
9390 "TARGET_UPDATE && rs6000_gen_cell_microcode
9391 && (!avoiding_indexed_address_p (SImode)
9392 || !gpc_reg_operand (operands[2], SImode))"
9393 "@
9394 lhaux %3,%0,%2
9395 lhau %3,%2(%0)"
9396 [(set_attr "type" "load_ext_ux,load_ext_u")])
9398 (define_insn "*movhi_update4"
9399 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9400 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9401 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9402 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9403 (plus:SI (match_dup 1) (match_dup 2)))]
9404 "TARGET_UPDATE
9405 && (!avoiding_indexed_address_p (SImode)
9406 || !gpc_reg_operand (operands[2], SImode))"
9407 "@
9408 sthux %3,%0,%2
9409 sthu %3,%2(%0)"
9410 [(set_attr "type" "store_ux,store_u")])
9412 (define_insn "*movqi_update1"
9413 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9414 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9415 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9416 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9417 (plus:SI (match_dup 1) (match_dup 2)))]
9418 "TARGET_UPDATE
9419 && (!avoiding_indexed_address_p (SImode)
9420 || !gpc_reg_operand (operands[2], SImode))"
9421 "@
9422 lbzux %3,%0,%2
9423 lbzu %3,%2(%0)"
9424 [(set_attr "type" "load_ux,load_u")])
9426 (define_insn "*movqi_update2"
9427 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9428 (zero_extend:SI
9429 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9430 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9431 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9432 (plus:SI (match_dup 1) (match_dup 2)))]
9433 "TARGET_UPDATE
9434 && (!avoiding_indexed_address_p (SImode)
9435 || !gpc_reg_operand (operands[2], SImode))"
9436 "@
9437 lbzux %3,%0,%2
9438 lbzu %3,%2(%0)"
9439 [(set_attr "type" "load_ux,load_u")])
9441 (define_insn "*movqi_update3"
9442 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9443 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9444 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9445 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9446 (plus:SI (match_dup 1) (match_dup 2)))]
9447 "TARGET_UPDATE
9448 && (!avoiding_indexed_address_p (SImode)
9449 || !gpc_reg_operand (operands[2], SImode))"
9450 "@
9451 stbux %3,%0,%2
9452 stbu %3,%2(%0)"
9453 [(set_attr "type" "store_ux,store_u")])
9455 (define_insn "*movsf_update1"
9456 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9457 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9458 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9459 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9460 (plus:SI (match_dup 1) (match_dup 2)))]
9461 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9462 && (!avoiding_indexed_address_p (SImode)
9463 || !gpc_reg_operand (operands[2], SImode))"
9464 "@
9465 lfsux %3,%0,%2
9466 lfsu %3,%2(%0)"
9467 [(set_attr "type" "fpload_ux,fpload_u")])
9469 (define_insn "*movsf_update2"
9470 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9471 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9472 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9473 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9474 (plus:SI (match_dup 1) (match_dup 2)))]
9475 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9476 && (!avoiding_indexed_address_p (SImode)
9477 || !gpc_reg_operand (operands[2], SImode))"
9478 "@
9479 stfsux %3,%0,%2
9480 stfsu %3,%2(%0)"
9481 [(set_attr "type" "fpstore_ux,fpstore_u")])
9483 (define_insn "*movsf_update3"
9484 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9485 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9486 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9487 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9488 (plus:SI (match_dup 1) (match_dup 2)))]
9489 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9490 && (!avoiding_indexed_address_p (SImode)
9491 || !gpc_reg_operand (operands[2], SImode))"
9492 "@
9493 lwzux %3,%0,%2
9494 lwzu %3,%2(%0)"
9495 [(set_attr "type" "load_ux,load_u")])
9497 (define_insn "*movsf_update4"
9498 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9499 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9500 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9501 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9502 (plus:SI (match_dup 1) (match_dup 2)))]
9503 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9504 && (!avoiding_indexed_address_p (SImode)
9505 || !gpc_reg_operand (operands[2], SImode))"
9506 "@
9507 stwux %3,%0,%2
9508 stwu %3,%2(%0)"
9509 [(set_attr "type" "store_ux,store_u")])
9511 (define_insn "*movdf_update1"
9512 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9513 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9514 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9515 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9516 (plus:SI (match_dup 1) (match_dup 2)))]
9517 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9518 && (!avoiding_indexed_address_p (SImode)
9519 || !gpc_reg_operand (operands[2], SImode))"
9520 "@
9521 lfdux %3,%0,%2
9522 lfdu %3,%2(%0)"
9523 [(set_attr "type" "fpload_ux,fpload_u")])
9525 (define_insn "*movdf_update2"
9526 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9527 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9528 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9529 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9530 (plus:SI (match_dup 1) (match_dup 2)))]
9531 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9532 && (!avoiding_indexed_address_p (SImode)
9533 || !gpc_reg_operand (operands[2], SImode))"
9534 "@
9535 stfdux %3,%0,%2
9536 stfdu %3,%2(%0)"
9537 [(set_attr "type" "fpstore_ux,fpstore_u")])
9540 ;; After inserting conditional returns we can sometimes have
9541 ;; unnecessary register moves. Unfortunately we cannot have a
9542 ;; modeless peephole here, because some single SImode sets have early
9543 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9544 ;; sequences, using get_attr_length here will smash the operands
9545 ;; array. Neither is there an early_cobbler_p predicate.
9546 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9547 (define_peephole2
9548 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9549 (match_operand:DF 1 "any_operand" ""))
9550 (set (match_operand:DF 2 "gpc_reg_operand" "")
9551 (match_dup 0))]
9552 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9553 && peep2_reg_dead_p (2, operands[0])"
9554 [(set (match_dup 2) (match_dup 1))])
9556 (define_peephole2
9557 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9558 (match_operand:SF 1 "any_operand" ""))
9559 (set (match_operand:SF 2 "gpc_reg_operand" "")
9560 (match_dup 0))]
9561 "peep2_reg_dead_p (2, operands[0])"
9562 [(set (match_dup 2) (match_dup 1))])
9564 \f
9565 ;; TLS support.
9567 ;; Mode attributes for different ABIs.
9568 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9569 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9570 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9571 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9573 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9574 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9575 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9576 (match_operand 4 "" "g")))
9577 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9578 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9579 UNSPEC_TLSGD)
9580 (clobber (reg:SI LR_REGNO))]
9581 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9582 {
9583 if (TARGET_CMODEL != CMODEL_SMALL)
9584 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9585 "bl %z3\;nop";
9586 else
9587 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9588 }
9589 "&& TARGET_TLS_MARKERS"
9590 [(set (match_dup 0)
9591 (unspec:TLSmode [(match_dup 1)
9592 (match_dup 2)]
9593 UNSPEC_TLSGD))
9594 (parallel [(set (match_dup 0)
9595 (call (mem:TLSmode (match_dup 3))
9596 (match_dup 4)))
9597 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9598 (clobber (reg:SI LR_REGNO))])]
9599 ""
9600 [(set_attr "type" "two")
9601 (set (attr "length")
9602 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9603 (const_int 16)
9604 (const_int 12)))])
9606 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9607 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9608 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9609 (match_operand 4 "" "g")))
9610 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9611 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9612 UNSPEC_TLSGD)
9613 (clobber (reg:SI LR_REGNO))]
9614 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9615 {
9616 if (flag_pic)
9617 {
9618 if (TARGET_SECURE_PLT && flag_pic == 2)
9619 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9620 else
9621 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9622 }
9623 else
9624 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9625 }
9626 "&& TARGET_TLS_MARKERS"
9627 [(set (match_dup 0)
9628 (unspec:TLSmode [(match_dup 1)
9629 (match_dup 2)]
9630 UNSPEC_TLSGD))
9631 (parallel [(set (match_dup 0)
9632 (call (mem:TLSmode (match_dup 3))
9633 (match_dup 4)))
9634 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9635 (clobber (reg:SI LR_REGNO))])]
9636 ""
9637 [(set_attr "type" "two")
9638 (set_attr "length" "8")])
9640 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9641 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9642 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9643 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9644 UNSPEC_TLSGD))]
9645 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9646 "addi %0,%1,%2@got@tlsgd"
9647 "&& TARGET_CMODEL != CMODEL_SMALL"
9648 [(set (match_dup 3)
9649 (high:TLSmode
9650 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9651 (set (match_dup 0)
9652 (lo_sum:TLSmode (match_dup 3)
9653 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
9654 "
9655 {
9656 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9657 }"
9658 [(set (attr "length")
9659 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9660 (const_int 8)
9661 (const_int 4)))])
9663 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9664 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9665 (high:TLSmode
9666 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9667 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9668 UNSPEC_TLSGD)))]
9669 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9670 "addis %0,%1,%2@got@tlsgd@ha"
9671 [(set_attr "length" "4")])
9673 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9674 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9675 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9676 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9677 UNSPEC_TLSGD)))]
9678 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9679 "addi %0,%1,%2@got@tlsgd@l"
9680 [(set_attr "length" "4")])
9682 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9683 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9684 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9685 (match_operand 2 "" "g")))
9686 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9687 UNSPEC_TLSGD)
9688 (clobber (reg:SI LR_REGNO))]
9689 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9690 "bl %z1(%3@tlsgd)\;nop"
9691 [(set_attr "type" "branch")
9692 (set_attr "length" "8")])
9694 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9695 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9696 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9697 (match_operand 2 "" "g")))
9698 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9699 UNSPEC_TLSGD)
9700 (clobber (reg:SI LR_REGNO))]
9701 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9702 {
9703 if (flag_pic)
9704 {
9705 if (TARGET_SECURE_PLT && flag_pic == 2)
9706 return "bl %z1+32768(%3@tlsgd)@plt";
9707 return "bl %z1(%3@tlsgd)@plt";
9708 }
9709 return "bl %z1(%3@tlsgd)";
9710 }
9711 [(set_attr "type" "branch")
9712 (set_attr "length" "4")])
9714 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9715 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9716 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9717 (match_operand 3 "" "g")))
9718 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9719 UNSPEC_TLSLD)
9720 (clobber (reg:SI LR_REGNO))]
9721 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
9722 {
9723 if (TARGET_CMODEL != CMODEL_SMALL)
9724 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9725 "bl %z2\;nop";
9726 else
9727 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9728 }
9729 "&& TARGET_TLS_MARKERS"
9730 [(set (match_dup 0)
9731 (unspec:TLSmode [(match_dup 1)]
9732 UNSPEC_TLSLD))
9733 (parallel [(set (match_dup 0)
9734 (call (mem:TLSmode (match_dup 2))
9735 (match_dup 3)))
9736 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9737 (clobber (reg:SI LR_REGNO))])]
9738 ""
9739 [(set_attr "type" "two")
9740 (set (attr "length")
9741 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9742 (const_int 16)
9743 (const_int 12)))])
9745 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9746 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9747 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9748 (match_operand 3 "" "g")))
9749 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9750 UNSPEC_TLSLD)
9751 (clobber (reg:SI LR_REGNO))]
9752 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9753 {
9754 if (flag_pic)
9755 {
9756 if (TARGET_SECURE_PLT && flag_pic == 2)
9757 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9758 else
9759 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9760 }
9761 else
9762 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9763 }
9764 "&& TARGET_TLS_MARKERS"
9765 [(set (match_dup 0)
9766 (unspec:TLSmode [(match_dup 1)]
9767 UNSPEC_TLSLD))
9768 (parallel [(set (match_dup 0)
9769 (call (mem:TLSmode (match_dup 2))
9770 (match_dup 3)))
9771 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9772 (clobber (reg:SI LR_REGNO))])]
9773 ""
9774 [(set_attr "length" "8")])
9776 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9777 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9778 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9779 UNSPEC_TLSLD))]
9780 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9781 "addi %0,%1,%&@got@tlsld"
9782 "&& TARGET_CMODEL != CMODEL_SMALL"
9783 [(set (match_dup 2)
9784 (high:TLSmode
9785 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9786 (set (match_dup 0)
9787 (lo_sum:TLSmode (match_dup 2)
9788 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9789 "
9790 {
9791 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9792 }"
9793 [(set (attr "length")
9794 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9795 (const_int 8)
9796 (const_int 4)))])
9798 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9799 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9800 (high:TLSmode
9801 (unspec:TLSmode [(const_int 0)
9802 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9803 UNSPEC_TLSLD)))]
9804 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9805 "addis %0,%1,%&@got@tlsld@ha"
9806 [(set_attr "length" "4")])
9808 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9809 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9810 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9811 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
9812 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9813 "addi %0,%1,%&@got@tlsld@l"
9814 [(set_attr "length" "4")])
9816 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
9817 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9818 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9819 (match_operand 2 "" "g")))
9820 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9821 (clobber (reg:SI LR_REGNO))]
9822 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
9823 "bl %z1(%&@tlsld)\;nop"
9824 [(set_attr "type" "branch")
9825 (set_attr "length" "8")])
9827 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
9828 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9829 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9830 (match_operand 2 "" "g")))
9831 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9832 (clobber (reg:SI LR_REGNO))]
9833 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9834 {
9835 if (flag_pic)
9836 {
9837 if (TARGET_SECURE_PLT && flag_pic == 2)
9838 return "bl %z1+32768(%&@tlsld)@plt";
9839 return "bl %z1(%&@tlsld)@plt";
9840 }
9841 return "bl %z1(%&@tlsld)";
9842 }
9843 [(set_attr "type" "branch")
9844 (set_attr "length" "4")])
9846 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
9847 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9848 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9849 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9850 UNSPEC_TLSDTPREL))]
9851 "HAVE_AS_TLS"
9852 "addi %0,%1,%2@dtprel")
9854 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
9855 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9856 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9857 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9858 UNSPEC_TLSDTPRELHA))]
9859 "HAVE_AS_TLS"
9860 "addis %0,%1,%2@dtprel@ha")
9862 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
9863 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9864 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9865 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9866 UNSPEC_TLSDTPRELLO))]
9867 "HAVE_AS_TLS"
9868 "addi %0,%1,%2@dtprel@l")
9870 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
9871 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9872 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9873 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9874 UNSPEC_TLSGOTDTPREL))]
9875 "HAVE_AS_TLS"
9876 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
9877 "&& TARGET_CMODEL != CMODEL_SMALL"
9878 [(set (match_dup 3)
9879 (high:TLSmode
9880 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
9881 (set (match_dup 0)
9882 (lo_sum:TLSmode (match_dup 3)
9883 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
9884 "
9885 {
9886 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9887 }"
9888 [(set (attr "length")
9889 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9890 (const_int 8)
9891 (const_int 4)))])
9893 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
9894 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9895 (high:TLSmode
9896 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9897 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9898 UNSPEC_TLSGOTDTPREL)))]
9899 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9900 "addis %0,%1,%2@got@dtprel@ha"
9901 [(set_attr "length" "4")])
9903 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
9904 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9905 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9906 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9907 UNSPEC_TLSGOTDTPREL)))]
9908 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9909 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
9910 [(set_attr "length" "4")])
9912 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
9913 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9914 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9915 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9916 UNSPEC_TLSTPREL))]
9917 "HAVE_AS_TLS"
9918 "addi %0,%1,%2@tprel")
9920 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
9921 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9922 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9923 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9924 UNSPEC_TLSTPRELHA))]
9925 "HAVE_AS_TLS"
9926 "addis %0,%1,%2@tprel@ha")
9928 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
9929 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9930 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9931 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9932 UNSPEC_TLSTPRELLO))]
9933 "HAVE_AS_TLS"
9934 "addi %0,%1,%2@tprel@l")
9936 ;; "b" output constraint here and on tls_tls input to support linker tls
9937 ;; optimization. The linker may edit the instructions emitted by a
9938 ;; tls_got_tprel/tls_tls pair to addis,addi.
9939 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
9940 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9941 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9942 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9943 UNSPEC_TLSGOTTPREL))]
9944 "HAVE_AS_TLS"
9945 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
9946 "&& TARGET_CMODEL != CMODEL_SMALL"
9947 [(set (match_dup 3)
9948 (high:TLSmode
9949 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
9950 (set (match_dup 0)
9951 (lo_sum:TLSmode (match_dup 3)
9952 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
9953 "
9954 {
9955 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9956 }"
9957 [(set (attr "length")
9958 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9959 (const_int 8)
9960 (const_int 4)))])
9962 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
9963 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9964 (high:TLSmode
9965 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9966 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9967 UNSPEC_TLSGOTTPREL)))]
9968 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9969 "addis %0,%1,%2@got@tprel@ha"
9970 [(set_attr "length" "4")])
9972 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
9973 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9974 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9975 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9976 UNSPEC_TLSGOTTPREL)))]
9977 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9978 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
9979 [(set_attr "length" "4")])
9981 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
9982 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9983 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9984 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9985 UNSPEC_TLSTLS))]
9986 "TARGET_ELF && HAVE_AS_TLS"
9987 "add %0,%1,%2@tls")
9989 (define_expand "tls_get_tpointer"
9990 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9991 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
9992 "TARGET_XCOFF && HAVE_AS_TLS"
9993 "
9994 {
9995 emit_insn (gen_tls_get_tpointer_internal ());
9996 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
9997 DONE;
9998 }")
10000 (define_insn "tls_get_tpointer_internal"
10001 [(set (reg:SI 3)
10002 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
10003 (clobber (reg:SI LR_REGNO))]
10004 "TARGET_XCOFF && HAVE_AS_TLS"
10005 "bla __get_tpointer")
10007 (define_expand "tls_get_addr<mode>"
10008 [(set (match_operand:P 0 "gpc_reg_operand" "")
10009 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
10010 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
10011 "TARGET_XCOFF && HAVE_AS_TLS"
10012 "
10013 {
10014 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
10015 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
10016 emit_insn (gen_tls_get_addr_internal<mode> ());
10017 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
10018 DONE;
10019 }")
10021 (define_insn "tls_get_addr_internal<mode>"
10022 [(set (reg:P 3)
10023 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
10024 (clobber (reg:P 0))
10025 (clobber (reg:P 5))
10026 (clobber (reg:P 11))
10027 (clobber (reg:CC CR0_REGNO))
10028 (clobber (reg:P LR_REGNO))]
10029 "TARGET_XCOFF && HAVE_AS_TLS"
10030 "bla __tls_get_addr")
10031 \f
10032 ;; Next come insns related to the calling sequence.
10033 ;;
10034 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10035 ;; We move the back-chain and decrement the stack pointer.
10037 (define_expand "allocate_stack"
10038 [(set (match_operand 0 "gpc_reg_operand" "")
10039 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10040 (set (reg 1)
10041 (minus (reg 1) (match_dup 1)))]
10042 ""
10043 "
10044 { rtx chain = gen_reg_rtx (Pmode);
10045 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10046 rtx neg_op0;
10047 rtx insn, par, set, mem;
10049 emit_move_insn (chain, stack_bot);
10051 /* Check stack bounds if necessary. */
10052 if (crtl->limit_stack)
10053 {
10054 rtx available;
10055 available = expand_binop (Pmode, sub_optab,
10056 stack_pointer_rtx, stack_limit_rtx,
10057 NULL_RTX, 1, OPTAB_WIDEN);
10058 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10059 }
10061 if (GET_CODE (operands[1]) != CONST_INT
10062 || INTVAL (operands[1]) < -32767
10063 || INTVAL (operands[1]) > 32768)
10064 {
10065 neg_op0 = gen_reg_rtx (Pmode);
10066 if (TARGET_32BIT)
10067 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10068 else
10069 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10070 }
10071 else
10072 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10074 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10075 : gen_movdi_di_update_stack))
10076 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10077 chain));
10078 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10079 it now and set the alias set/attributes. The above gen_*_update
10080 calls will generate a PARALLEL with the MEM set being the first
10081 operation. */
10082 par = PATTERN (insn);
10083 gcc_assert (GET_CODE (par) == PARALLEL);
10084 set = XVECEXP (par, 0, 0);
10085 gcc_assert (GET_CODE (set) == SET);
10086 mem = SET_DEST (set);
10087 gcc_assert (MEM_P (mem));
10088 MEM_NOTRAP_P (mem) = 1;
10089 set_mem_alias_set (mem, get_frame_alias_set ());
10091 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10092 DONE;
10093 }")
10095 ;; These patterns say how to save and restore the stack pointer. We need not
10096 ;; save the stack pointer at function level since we are careful to
10097 ;; preserve the backchain. At block level, we have to restore the backchain
10098 ;; when we restore the stack pointer.
10099 ;;
10100 ;; For nonlocal gotos, we must save both the stack pointer and its
10101 ;; backchain and restore both. Note that in the nonlocal case, the
10102 ;; save area is a memory location.
10104 (define_expand "save_stack_function"
10105 [(match_operand 0 "any_operand" "")
10106 (match_operand 1 "any_operand" "")]
10107 ""
10108 "DONE;")
10110 (define_expand "restore_stack_function"
10111 [(match_operand 0 "any_operand" "")
10112 (match_operand 1 "any_operand" "")]
10113 ""
10114 "DONE;")
10116 ;; Adjust stack pointer (op0) to a new value (op1).
10117 ;; First copy old stack backchain to new location, and ensure that the
10118 ;; scheduler won't reorder the sp assignment before the backchain write.
10119 (define_expand "restore_stack_block"
10120 [(set (match_dup 2) (match_dup 3))
10121 (set (match_dup 4) (match_dup 2))
10122 (match_dup 5)
10123 (set (match_operand 0 "register_operand" "")
10124 (match_operand 1 "register_operand" ""))]
10125 ""
10126 "
10127 {
10128 rtvec p;
10130 operands[1] = force_reg (Pmode, operands[1]);
10131 operands[2] = gen_reg_rtx (Pmode);
10132 operands[3] = gen_frame_mem (Pmode, operands[0]);
10133 operands[4] = gen_frame_mem (Pmode, operands[1]);
10134 p = rtvec_alloc (1);
10135 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10136 gen_frame_mem (BLKmode, operands[0]),
10137 const0_rtx);
10138 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10139 }")
10141 (define_expand "save_stack_nonlocal"
10142 [(set (match_dup 3) (match_dup 4))
10143 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10144 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10145 ""
10146 "
10147 {
10148 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10150 /* Copy the backchain to the first word, sp to the second. */
10151 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10152 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10153 operands[3] = gen_reg_rtx (Pmode);
10154 operands[4] = gen_frame_mem (Pmode, operands[1]);
10155 }")
10157 (define_expand "restore_stack_nonlocal"
10158 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10159 (set (match_dup 3) (match_dup 4))
10160 (set (match_dup 5) (match_dup 2))
10161 (match_dup 6)
10162 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10163 ""
10164 "
10165 {
10166 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10167 rtvec p;
10169 /* Restore the backchain from the first word, sp from the second. */
10170 operands[2] = gen_reg_rtx (Pmode);
10171 operands[3] = gen_reg_rtx (Pmode);
10172 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10173 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10174 operands[5] = gen_frame_mem (Pmode, operands[3]);
10175 p = rtvec_alloc (1);
10176 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10177 gen_frame_mem (BLKmode, operands[0]),
10178 const0_rtx);
10179 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10180 }")
10181 \f
10182 ;; TOC register handling.
10184 ;; Code to initialize the TOC register...
10186 (define_insn "load_toc_aix_si"
10187 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10188 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10189 (use (reg:SI 2))])]
10190 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10191 "*
10192 {
10193 char buf[30];
10194 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10195 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10196 operands[2] = gen_rtx_REG (Pmode, 2);
10197 return \"lwz %0,%1(%2)\";
10198 }"
10199 [(set_attr "type" "load")])
10201 (define_insn "load_toc_aix_di"
10202 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10203 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10204 (use (reg:DI 2))])]
10205 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10206 "*
10207 {
10208 char buf[30];
10209 #ifdef TARGET_RELOCATABLE
10210 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10211 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10212 #else
10213 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10214 #endif
10215 if (TARGET_ELF)
10216 strcat (buf, \"@toc\");
10217 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10218 operands[2] = gen_rtx_REG (Pmode, 2);
10219 return \"ld %0,%1(%2)\";
10220 }"
10221 [(set_attr "type" "load")])
10223 (define_insn "load_toc_v4_pic_si"
10224 [(set (reg:SI LR_REGNO)
10225 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10226 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10227 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10228 [(set_attr "type" "branch")
10229 (set_attr "length" "4")])
10231 (define_expand "load_toc_v4_PIC_1"
10232 [(parallel [(set (reg:SI LR_REGNO)
10233 (match_operand:SI 0 "immediate_operand" "s"))
10234 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10235 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10236 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10237 "")
10239 (define_insn "load_toc_v4_PIC_1_normal"
10240 [(set (reg:SI LR_REGNO)
10241 (match_operand:SI 0 "immediate_operand" "s"))
10242 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10243 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10244 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10245 "bcl 20,31,%0\\n%0:"
10246 [(set_attr "type" "branch")
10247 (set_attr "length" "4")])
10249 (define_insn "load_toc_v4_PIC_1_476"
10250 [(set (reg:SI LR_REGNO)
10251 (match_operand:SI 0 "immediate_operand" "s"))
10252 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10253 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10254 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10255 "*
10256 {
10257 char name[32];
10258 static char templ[32];
10260 get_ppc476_thunk_name (name);
10261 sprintf (templ, \"bl %s\\n%%0:\", name);
10262 return templ;
10263 }"
10264 [(set_attr "type" "branch")
10265 (set_attr "length" "4")])
10267 (define_expand "load_toc_v4_PIC_1b"
10268 [(parallel [(set (reg:SI LR_REGNO)
10269 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10270 (label_ref (match_operand 1 "" ""))]
10271 UNSPEC_TOCPTR))
10272 (match_dup 1)])]
10273 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10274 "")
10276 (define_insn "load_toc_v4_PIC_1b_normal"
10277 [(set (reg:SI LR_REGNO)
10278 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10279 (label_ref (match_operand 1 "" ""))]
10280 UNSPEC_TOCPTR))
10281 (match_dup 1)]
10282 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10283 "bcl 20,31,$+8\;.long %0-$"
10284 [(set_attr "type" "branch")
10285 (set_attr "length" "8")])
10287 (define_insn "load_toc_v4_PIC_1b_476"
10288 [(set (reg:SI LR_REGNO)
10289 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10290 (label_ref (match_operand 1 "" ""))]
10291 UNSPEC_TOCPTR))
10292 (match_dup 1)]
10293 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10294 "*
10295 {
10296 char name[32];
10297 static char templ[32];
10299 get_ppc476_thunk_name (name);
10300 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10301 return templ;
10302 }"
10303 [(set_attr "type" "branch")
10304 (set_attr "length" "16")])
10306 (define_insn "load_toc_v4_PIC_2"
10307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10308 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10309 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10310 (match_operand:SI 3 "immediate_operand" "s")))))]
10311 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10312 "lwz %0,%2-%3(%1)"
10313 [(set_attr "type" "load")])
10315 (define_insn "load_toc_v4_PIC_3b"
10316 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10317 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10318 (high:SI
10319 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10320 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10321 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10322 "addis %0,%1,%2-%3@ha")
10324 (define_insn "load_toc_v4_PIC_3c"
10325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10326 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10327 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10328 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10329 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10330 "addi %0,%1,%2-%3@l")
10332 ;; If the TOC is shared over a translation unit, as happens with all
10333 ;; the kinds of PIC that we support, we need to restore the TOC
10334 ;; pointer only when jumping over units of translation.
10335 ;; On Darwin, we need to reload the picbase.
10337 (define_expand "builtin_setjmp_receiver"
10338 [(use (label_ref (match_operand 0 "" "")))]
10339 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10340 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10341 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10342 "
10343 {
10344 #if TARGET_MACHO
10345 if (DEFAULT_ABI == ABI_DARWIN)
10346 {
10347 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10348 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10349 rtx tmplabrtx;
10350 char tmplab[20];
10352 crtl->uses_pic_offset_table = 1;
10353 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10354 CODE_LABEL_NUMBER (operands[0]));
10355 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10357 emit_insn (gen_load_macho_picbase (tmplabrtx));
10358 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10359 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10360 }
10361 else
10362 #endif
10363 rs6000_emit_load_toc_table (FALSE);
10364 DONE;
10365 }")
10367 ;; Largetoc support
10368 (define_insn "*largetoc_high"
10369 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10370 (high:DI
10371 (unspec [(match_operand:DI 1 "" "")
10372 (match_operand:DI 2 "gpc_reg_operand" "b")]
10373 UNSPEC_TOCREL)))]
10374 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10375 "addis %0,%2,%1@toc@ha")
10377 (define_insn "*largetoc_high_aix<mode>"
10378 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10379 (high:P
10380 (unspec [(match_operand:P 1 "" "")
10381 (match_operand:P 2 "gpc_reg_operand" "b")]
10382 UNSPEC_TOCREL)))]
10383 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10384 "addis %0,%1@u(%2)")
10386 (define_insn "*largetoc_high_plus"
10387 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10388 (high:DI
10389 (plus:DI
10390 (unspec [(match_operand:DI 1 "" "")
10391 (match_operand:DI 2 "gpc_reg_operand" "b")]
10392 UNSPEC_TOCREL)
10393 (match_operand 3 "const_int_operand" "n"))))]
10394 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10395 "addis %0,%2,%1+%3@toc@ha")
10397 (define_insn "*largetoc_high_plus_aix<mode>"
10398 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10399 (high:P
10400 (plus:P
10401 (unspec [(match_operand:P 1 "" "")
10402 (match_operand:P 2 "gpc_reg_operand" "b")]
10403 UNSPEC_TOCREL)
10404 (match_operand 3 "const_int_operand" "n"))))]
10405 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10406 "addis %0,%1+%3@u(%2)")
10408 (define_insn "*largetoc_low"
10409 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10410 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10411 (match_operand:DI 2 "" "")))]
10412 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10413 "@
10414 addi %0,%1,%2@l
10415 addic %0,%1,%2@l")
10417 (define_insn "*largetoc_low_aix<mode>"
10418 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10419 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10420 (match_operand:P 2 "" "")))]
10421 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10422 "la %0,%2@l(%1)")
10424 (define_insn_and_split "*tocref<mode>"
10425 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10426 (match_operand:P 1 "small_toc_ref" "R"))]
10427 "TARGET_TOC"
10428 "la %0,%a1"
10429 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10430 [(set (match_dup 0) (high:P (match_dup 1)))
10431 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10433 ;; Elf specific ways of loading addresses for non-PIC code.
10434 ;; The output of this could be r0, but we make a very strong
10435 ;; preference for a base register because it will usually
10436 ;; be needed there.
10437 (define_insn "elf_high"
10438 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10439 (high:SI (match_operand 1 "" "")))]
10440 "TARGET_ELF && ! TARGET_64BIT"
10441 "lis %0,%1@ha")
10443 (define_insn "elf_low"
10444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10445 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10446 (match_operand 2 "" "")))]
10447 "TARGET_ELF && ! TARGET_64BIT"
10448 "@
10449 la %0,%2@l(%1)
10450 addic %0,%1,%K2")
10451 \f
10452 ;; Call and call_value insns
10453 (define_expand "call"
10454 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10455 (match_operand 1 "" ""))
10456 (use (match_operand 2 "" ""))
10457 (clobber (reg:SI LR_REGNO))])]
10458 ""
10459 "
10460 {
10461 #if TARGET_MACHO
10462 if (MACHOPIC_INDIRECT)
10463 operands[0] = machopic_indirect_call_target (operands[0]);
10464 #endif
10466 gcc_assert (GET_CODE (operands[0]) == MEM);
10467 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10469 operands[0] = XEXP (operands[0], 0);
10471 if (GET_CODE (operands[0]) != SYMBOL_REF
10472 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10473 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10474 {
10475 if (INTVAL (operands[2]) & CALL_LONG)
10476 operands[0] = rs6000_longcall_ref (operands[0]);
10478 switch (DEFAULT_ABI)
10479 {
10480 case ABI_V4:
10481 case ABI_DARWIN:
10482 operands[0] = force_reg (Pmode, operands[0]);
10483 break;
10485 case ABI_AIX:
10486 /* AIX function pointers are really pointers to a three word
10487 area. */
10488 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
10489 DONE;
10491 default:
10492 gcc_unreachable ();
10493 }
10494 }
10495 }")
10497 (define_expand "call_value"
10498 [(parallel [(set (match_operand 0 "" "")
10499 (call (mem:SI (match_operand 1 "address_operand" ""))
10500 (match_operand 2 "" "")))
10501 (use (match_operand 3 "" ""))
10502 (clobber (reg:SI LR_REGNO))])]
10503 ""
10504 "
10505 {
10506 #if TARGET_MACHO
10507 if (MACHOPIC_INDIRECT)
10508 operands[1] = machopic_indirect_call_target (operands[1]);
10509 #endif
10511 gcc_assert (GET_CODE (operands[1]) == MEM);
10512 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10514 operands[1] = XEXP (operands[1], 0);
10516 if (GET_CODE (operands[1]) != SYMBOL_REF
10517 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10518 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10519 {
10520 if (INTVAL (operands[3]) & CALL_LONG)
10521 operands[1] = rs6000_longcall_ref (operands[1]);
10523 switch (DEFAULT_ABI)
10524 {
10525 case ABI_V4:
10526 case ABI_DARWIN:
10527 operands[1] = force_reg (Pmode, operands[1]);
10528 break;
10530 case ABI_AIX:
10531 /* AIX function pointers are really pointers to a three word
10532 area. */
10533 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
10534 DONE;
10536 default:
10537 gcc_unreachable ();
10538 }
10539 }
10540 }")
10542 ;; Call to function in current module. No TOC pointer reload needed.
10543 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10544 ;; either the function was not prototyped, or it was prototyped as a
10545 ;; variable argument function. It is > 0 if FP registers were passed
10546 ;; and < 0 if they were not.
10548 (define_insn "*call_local32"
10549 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10550 (match_operand 1 "" "g,g"))
10551 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10552 (clobber (reg:SI LR_REGNO))]
10553 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10554 "*
10555 {
10556 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10557 output_asm_insn (\"crxor 6,6,6\", operands);
10559 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10560 output_asm_insn (\"creqv 6,6,6\", operands);
10562 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10563 }"
10564 [(set_attr "type" "branch")
10565 (set_attr "length" "4,8")])
10567 (define_insn "*call_local64"
10568 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10569 (match_operand 1 "" "g,g"))
10570 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10571 (clobber (reg:SI LR_REGNO))]
10572 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10573 "*
10574 {
10575 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10576 output_asm_insn (\"crxor 6,6,6\", operands);
10578 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10579 output_asm_insn (\"creqv 6,6,6\", operands);
10581 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10582 }"
10583 [(set_attr "type" "branch")
10584 (set_attr "length" "4,8")])
10586 (define_insn "*call_value_local32"
10587 [(set (match_operand 0 "" "")
10588 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10589 (match_operand 2 "" "g,g")))
10590 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10591 (clobber (reg:SI LR_REGNO))]
10592 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10593 "*
10594 {
10595 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10596 output_asm_insn (\"crxor 6,6,6\", operands);
10598 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10599 output_asm_insn (\"creqv 6,6,6\", operands);
10601 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10602 }"
10603 [(set_attr "type" "branch")
10604 (set_attr "length" "4,8")])
10607 (define_insn "*call_value_local64"
10608 [(set (match_operand 0 "" "")
10609 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10610 (match_operand 2 "" "g,g")))
10611 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10612 (clobber (reg:SI LR_REGNO))]
10613 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10614 "*
10615 {
10616 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10617 output_asm_insn (\"crxor 6,6,6\", operands);
10619 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10620 output_asm_insn (\"creqv 6,6,6\", operands);
10622 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10623 }"
10624 [(set_attr "type" "branch")
10625 (set_attr "length" "4,8")])
10627 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
10628 ;; Operand0 is the addresss of the function to call
10629 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10630 ;; Operand2 is the location in the function descriptor to load r2 from
10631 ;; Operand3 is the stack location to hold the current TOC pointer
10633 (define_insn "call_indirect_aix<ptrsize>"
10634 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10635 (match_operand 1 "" "g,g"))
10636 (use (match_operand:P 2 "memory_operand" "m,m"))
10637 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10638 (use (reg:P STATIC_CHAIN_REGNUM))
10639 (clobber (reg:P LR_REGNO))]
10640 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10641 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10642 [(set_attr "type" "jmpreg")
10643 (set_attr "length" "12")])
10645 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
10646 ;; Operand0 is the addresss of the function to call
10647 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
10648 ;; Operand2 is the location in the function descriptor to load r2 from
10649 ;; Operand3 is the stack location to hold the current TOC pointer
10651 (define_insn "call_indirect_aix<ptrsize>_nor11"
10652 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10653 (match_operand 1 "" "g,g"))
10654 (use (match_operand:P 2 "memory_operand" "m,m"))
10655 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
10656 (clobber (reg:P LR_REGNO))]
10657 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10658 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
10659 [(set_attr "type" "jmpreg")
10660 (set_attr "length" "12")])
10662 ;; Operand0 is the return result of the function
10663 ;; Operand1 is the addresss of the function to call
10664 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10665 ;; Operand3 is the location in the function descriptor to load r2 from
10666 ;; Operand4 is the stack location to hold the current TOC pointer
10668 (define_insn "call_value_indirect_aix<ptrsize>"
10669 [(set (match_operand 0 "" "")
10670 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10671 (match_operand 2 "" "g,g")))
10672 (use (match_operand:P 3 "memory_operand" "m,m"))
10673 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10674 (use (reg:P STATIC_CHAIN_REGNUM))
10675 (clobber (reg:P LR_REGNO))]
10676 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10677 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10678 [(set_attr "type" "jmpreg")
10679 (set_attr "length" "12")])
10681 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
10682 ;; Operand0 is the return result of the function
10683 ;; Operand1 is the addresss of the function to call
10684 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
10685 ;; Operand3 is the location in the function descriptor to load r2 from
10686 ;; Operand4 is the stack location to hold the current TOC pointer
10688 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
10689 [(set (match_operand 0 "" "")
10690 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10691 (match_operand 2 "" "g,g")))
10692 (use (match_operand:P 3 "memory_operand" "m,m"))
10693 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
10694 (clobber (reg:P LR_REGNO))]
10695 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
10696 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
10697 [(set_attr "type" "jmpreg")
10698 (set_attr "length" "12")])
10700 ;; Call to function which may be in another module. Restore the TOC
10701 ;; pointer (r2) after the call unless this is System V.
10702 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10703 ;; either the function was not prototyped, or it was prototyped as a
10704 ;; variable argument function. It is > 0 if FP registers were passed
10705 ;; and < 0 if they were not.
10707 (define_insn "*call_nonlocal_aix32"
10708 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10709 (match_operand 1 "" "g"))
10710 (use (match_operand:SI 2 "immediate_operand" "O"))
10711 (clobber (reg:SI LR_REGNO))]
10712 "TARGET_32BIT
10713 && DEFAULT_ABI == ABI_AIX
10714 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10715 "bl %z0\;nop"
10716 [(set_attr "type" "branch")
10717 (set_attr "length" "8")])
10719 (define_insn "*call_nonlocal_aix64"
10720 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10721 (match_operand 1 "" "g"))
10722 (use (match_operand:SI 2 "immediate_operand" "O"))
10723 (clobber (reg:SI LR_REGNO))]
10724 "TARGET_64BIT
10725 && DEFAULT_ABI == ABI_AIX
10726 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10727 "bl %z0\;nop"
10728 [(set_attr "type" "branch")
10729 (set_attr "length" "8")])
10731 (define_insn "*call_value_nonlocal_aix32"
10732 [(set (match_operand 0 "" "")
10733 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10734 (match_operand 2 "" "g")))
10735 (use (match_operand:SI 3 "immediate_operand" "O"))
10736 (clobber (reg:SI LR_REGNO))]
10737 "TARGET_32BIT
10738 && DEFAULT_ABI == ABI_AIX
10739 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10740 "bl %z1\;nop"
10741 [(set_attr "type" "branch")
10742 (set_attr "length" "8")])
10744 (define_insn "*call_value_nonlocal_aix64"
10745 [(set (match_operand 0 "" "")
10746 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10747 (match_operand 2 "" "g")))
10748 (use (match_operand:SI 3 "immediate_operand" "O"))
10749 (clobber (reg:SI LR_REGNO))]
10750 "TARGET_64BIT
10751 && DEFAULT_ABI == ABI_AIX
10752 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10753 "bl %z1\;nop"
10754 [(set_attr "type" "branch")
10755 (set_attr "length" "8")])
10757 ;; A function pointer under System V is just a normal pointer
10758 ;; operands[0] is the function pointer
10759 ;; operands[1] is the stack size to clean up
10760 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10761 ;; which indicates how to set cr1
10763 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10764 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10765 (match_operand 1 "" "g,g,g,g"))
10766 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10767 (clobber (reg:SI LR_REGNO))]
10768 "DEFAULT_ABI == ABI_V4
10769 || DEFAULT_ABI == ABI_DARWIN"
10770 {
10771 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10772 output_asm_insn ("crxor 6,6,6", operands);
10774 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10775 output_asm_insn ("creqv 6,6,6", operands);
10777 return "b%T0l";
10778 }
10779 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10780 (set_attr "length" "4,4,8,8")])
10782 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10783 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10784 (match_operand 1 "" "g,g"))
10785 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10786 (clobber (reg:SI LR_REGNO))]
10787 "(DEFAULT_ABI == ABI_DARWIN
10788 || (DEFAULT_ABI == ABI_V4
10789 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10790 {
10791 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10792 output_asm_insn ("crxor 6,6,6", operands);
10794 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10795 output_asm_insn ("creqv 6,6,6", operands);
10797 #if TARGET_MACHO
10798 return output_call(insn, operands, 0, 2);
10799 #else
10800 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10801 {
10802 gcc_assert (!TARGET_SECURE_PLT);
10803 return "bl %z0@plt";
10804 }
10805 else
10806 return "bl %z0";
10807 #endif
10808 }
10809 "DEFAULT_ABI == ABI_V4
10810 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10811 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10812 [(parallel [(call (mem:SI (match_dup 0))
10813 (match_dup 1))
10814 (use (match_dup 2))
10815 (use (match_dup 3))
10816 (clobber (reg:SI LR_REGNO))])]
10817 {
10818 operands[3] = pic_offset_table_rtx;
10819 }
10820 [(set_attr "type" "branch,branch")
10821 (set_attr "length" "4,8")])
10823 (define_insn "*call_nonlocal_sysv_secure<mode>"
10824 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10825 (match_operand 1 "" "g,g"))
10826 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10827 (use (match_operand:SI 3 "register_operand" "r,r"))
10828 (clobber (reg:SI LR_REGNO))]
10829 "(DEFAULT_ABI == ABI_V4
10830 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10831 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10832 {
10833 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10834 output_asm_insn ("crxor 6,6,6", operands);
10836 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10837 output_asm_insn ("creqv 6,6,6", operands);
10839 if (flag_pic == 2)
10840 /* The magic 32768 offset here and in the other sysv call insns
10841 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10842 See sysv4.h:toc_section. */
10843 return "bl %z0+32768@plt";
10844 else
10845 return "bl %z0@plt";
10846 }
10847 [(set_attr "type" "branch,branch")
10848 (set_attr "length" "4,8")])
10850 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10851 [(set (match_operand 0 "" "")
10852 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10853 (match_operand 2 "" "g,g,g,g")))
10854 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10855 (clobber (reg:SI LR_REGNO))]
10856 "DEFAULT_ABI == ABI_V4
10857 || DEFAULT_ABI == ABI_DARWIN"
10858 {
10859 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10860 output_asm_insn ("crxor 6,6,6", operands);
10862 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10863 output_asm_insn ("creqv 6,6,6", operands);
10865 return "b%T1l";
10866 }
10867 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10868 (set_attr "length" "4,4,8,8")])
10870 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10871 [(set (match_operand 0 "" "")
10872 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10873 (match_operand 2 "" "g,g")))
10874 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10875 (clobber (reg:SI LR_REGNO))]
10876 "(DEFAULT_ABI == ABI_DARWIN
10877 || (DEFAULT_ABI == ABI_V4
10878 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10879 {
10880 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10881 output_asm_insn ("crxor 6,6,6", operands);
10883 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10884 output_asm_insn ("creqv 6,6,6", operands);
10886 #if TARGET_MACHO
10887 return output_call(insn, operands, 1, 3);
10888 #else
10889 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10890 {
10891 gcc_assert (!TARGET_SECURE_PLT);
10892 return "bl %z1@plt";
10893 }
10894 else
10895 return "bl %z1";
10896 #endif
10897 }
10898 "DEFAULT_ABI == ABI_V4
10899 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10900 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10901 [(parallel [(set (match_dup 0)
10902 (call (mem:SI (match_dup 1))
10903 (match_dup 2)))
10904 (use (match_dup 3))
10905 (use (match_dup 4))
10906 (clobber (reg:SI LR_REGNO))])]
10907 {
10908 operands[4] = pic_offset_table_rtx;
10909 }
10910 [(set_attr "type" "branch,branch")
10911 (set_attr "length" "4,8")])
10913 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10914 [(set (match_operand 0 "" "")
10915 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10916 (match_operand 2 "" "g,g")))
10917 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10918 (use (match_operand:SI 4 "register_operand" "r,r"))
10919 (clobber (reg:SI LR_REGNO))]
10920 "(DEFAULT_ABI == ABI_V4
10921 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10922 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10923 {
10924 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10925 output_asm_insn ("crxor 6,6,6", operands);
10927 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10928 output_asm_insn ("creqv 6,6,6", operands);
10930 if (flag_pic == 2)
10931 return "bl %z1+32768@plt";
10932 else
10933 return "bl %z1@plt";
10934 }
10935 [(set_attr "type" "branch,branch")
10936 (set_attr "length" "4,8")])
10938 ;; Call subroutine returning any type.
10939 (define_expand "untyped_call"
10940 [(parallel [(call (match_operand 0 "" "")
10941 (const_int 0))
10942 (match_operand 1 "" "")
10943 (match_operand 2 "" "")])]
10944 ""
10945 "
10946 {
10947 int i;
10949 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10951 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10952 {
10953 rtx set = XVECEXP (operands[2], 0, i);
10954 emit_move_insn (SET_DEST (set), SET_SRC (set));
10955 }
10957 /* The optimizer does not know that the call sets the function value
10958 registers we stored in the result block. We avoid problems by
10959 claiming that all hard registers are used and clobbered at this
10960 point. */
10961 emit_insn (gen_blockage ());
10963 DONE;
10964 }")
10966 ;; sibling call patterns
10967 (define_expand "sibcall"
10968 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10969 (match_operand 1 "" ""))
10970 (use (match_operand 2 "" ""))
10971 (use (reg:SI LR_REGNO))
10972 (simple_return)])]
10973 ""
10974 "
10975 {
10976 #if TARGET_MACHO
10977 if (MACHOPIC_INDIRECT)
10978 operands[0] = machopic_indirect_call_target (operands[0]);
10979 #endif
10981 gcc_assert (GET_CODE (operands[0]) == MEM);
10982 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10984 operands[0] = XEXP (operands[0], 0);
10985 }")
10987 ;; this and similar patterns must be marked as using LR, otherwise
10988 ;; dataflow will try to delete the store into it. This is true
10989 ;; even when the actual reg to jump to is in CTR, when LR was
10990 ;; saved and restored around the PIC-setting BCL.
10991 (define_insn "*sibcall_local32"
10992 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10993 (match_operand 1 "" "g,g"))
10994 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10995 (use (reg:SI LR_REGNO))
10996 (simple_return)]
10997 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10998 "*
10999 {
11000 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11001 output_asm_insn (\"crxor 6,6,6\", operands);
11003 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11004 output_asm_insn (\"creqv 6,6,6\", operands);
11006 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11007 }"
11008 [(set_attr "type" "branch")
11009 (set_attr "length" "4,8")])
11011 (define_insn "*sibcall_local64"
11012 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11013 (match_operand 1 "" "g,g"))
11014 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11015 (use (reg:SI LR_REGNO))
11016 (simple_return)]
11017 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11018 "*
11019 {
11020 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11021 output_asm_insn (\"crxor 6,6,6\", operands);
11023 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11024 output_asm_insn (\"creqv 6,6,6\", operands);
11026 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11027 }"
11028 [(set_attr "type" "branch")
11029 (set_attr "length" "4,8")])
11031 (define_insn "*sibcall_value_local32"
11032 [(set (match_operand 0 "" "")
11033 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11034 (match_operand 2 "" "g,g")))
11035 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11036 (use (reg:SI LR_REGNO))
11037 (simple_return)]
11038 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11039 "*
11040 {
11041 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11042 output_asm_insn (\"crxor 6,6,6\", operands);
11044 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11045 output_asm_insn (\"creqv 6,6,6\", operands);
11047 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11048 }"
11049 [(set_attr "type" "branch")
11050 (set_attr "length" "4,8")])
11053 (define_insn "*sibcall_value_local64"
11054 [(set (match_operand 0 "" "")
11055 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11056 (match_operand 2 "" "g,g")))
11057 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11058 (use (reg:SI LR_REGNO))
11059 (simple_return)]
11060 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11061 "*
11062 {
11063 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11064 output_asm_insn (\"crxor 6,6,6\", operands);
11066 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11067 output_asm_insn (\"creqv 6,6,6\", operands);
11069 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11070 }"
11071 [(set_attr "type" "branch")
11072 (set_attr "length" "4,8")])
11074 (define_insn "*sibcall_nonlocal_aix<mode>"
11075 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11076 (match_operand 1 "" "g,g"))
11077 (use (match_operand:SI 2 "immediate_operand" "O,O"))
11078 (use (reg:SI LR_REGNO))
11079 (simple_return)]
11080 "DEFAULT_ABI == ABI_AIX
11081 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11082 "@
11083 b %z0
11084 b%T0"
11085 [(set_attr "type" "branch")
11086 (set_attr "length" "4")])
11088 (define_insn "*sibcall_value_nonlocal_aix<mode>"
11089 [(set (match_operand 0 "" "")
11090 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11091 (match_operand 2 "" "g,g")))
11092 (use (match_operand:SI 3 "immediate_operand" "O,O"))
11093 (use (reg:SI LR_REGNO))
11094 (simple_return)]
11095 "DEFAULT_ABI == ABI_AIX
11096 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11097 "@
11098 b %z1
11099 b%T1"
11100 [(set_attr "type" "branch")
11101 (set_attr "length" "4")])
11103 (define_insn "*sibcall_nonlocal_sysv<mode>"
11104 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11105 (match_operand 1 "" ""))
11106 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11107 (use (reg:SI LR_REGNO))
11108 (simple_return)]
11109 "(DEFAULT_ABI == ABI_DARWIN
11110 || DEFAULT_ABI == ABI_V4)
11111 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11112 "*
11113 {
11114 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11115 output_asm_insn (\"crxor 6,6,6\", operands);
11117 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11118 output_asm_insn (\"creqv 6,6,6\", operands);
11120 if (which_alternative >= 2)
11121 return \"b%T0\";
11122 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11123 {
11124 gcc_assert (!TARGET_SECURE_PLT);
11125 return \"b %z0@plt\";
11126 }
11127 else
11128 return \"b %z0\";
11129 }"
11130 [(set_attr "type" "branch")
11131 (set_attr "length" "4,8,4,8")])
11133 (define_expand "sibcall_value"
11134 [(parallel [(set (match_operand 0 "register_operand" "")
11135 (call (mem:SI (match_operand 1 "address_operand" ""))
11136 (match_operand 2 "" "")))
11137 (use (match_operand 3 "" ""))
11138 (use (reg:SI LR_REGNO))
11139 (simple_return)])]
11140 ""
11141 "
11142 {
11143 #if TARGET_MACHO
11144 if (MACHOPIC_INDIRECT)
11145 operands[1] = machopic_indirect_call_target (operands[1]);
11146 #endif
11148 gcc_assert (GET_CODE (operands[1]) == MEM);
11149 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11151 operands[1] = XEXP (operands[1], 0);
11152 }")
11154 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11155 [(set (match_operand 0 "" "")
11156 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11157 (match_operand 2 "" "")))
11158 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11159 (use (reg:SI LR_REGNO))
11160 (simple_return)]
11161 "(DEFAULT_ABI == ABI_DARWIN
11162 || DEFAULT_ABI == ABI_V4)
11163 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11164 "*
11165 {
11166 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11167 output_asm_insn (\"crxor 6,6,6\", operands);
11169 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11170 output_asm_insn (\"creqv 6,6,6\", operands);
11172 if (which_alternative >= 2)
11173 return \"b%T1\";
11174 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11175 {
11176 gcc_assert (!TARGET_SECURE_PLT);
11177 return \"b %z1@plt\";
11178 }
11179 else
11180 return \"b %z1\";
11181 }"
11182 [(set_attr "type" "branch")
11183 (set_attr "length" "4,8,4,8")])
11185 (define_expand "sibcall_epilogue"
11186 [(use (const_int 0))]
11187 ""
11188 {
11189 if (!TARGET_SCHED_PROLOG)
11190 emit_insn (gen_blockage ());
11191 rs6000_emit_epilogue (TRUE);
11192 DONE;
11193 })
11195 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11196 ;; all of memory. This blocks insns from being moved across this point.
11198 (define_insn "blockage"
11199 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11200 ""
11201 "")
11203 (define_expand "probe_stack"
11204 [(set (match_operand 0 "memory_operand" "=m")
11205 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11206 ""
11207 {
11208 if (TARGET_64BIT)
11209 emit_insn (gen_probe_stack_di (operands[0]));
11210 else
11211 emit_insn (gen_probe_stack_si (operands[0]));
11212 DONE;
11213 })
11215 (define_insn "probe_stack_<mode>"
11216 [(set (match_operand:P 0 "memory_operand" "=m")
11217 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
11218 ""
11219 {
11220 operands[1] = gen_rtx_REG (Pmode, 0);
11221 return "st<wd>%U0%X0 %1,%0";
11222 }
11223 [(set_attr "type" "store")
11224 (set_attr "length" "4")])
11226 (define_insn "probe_stack_range<P:mode>"
11227 [(set (match_operand:P 0 "register_operand" "=r")
11228 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11229 (match_operand:P 2 "register_operand" "r")]
11230 UNSPECV_PROBE_STACK_RANGE))]
11231 ""
11232 "* return output_probe_stack_range (operands[0], operands[2]);"
11233 [(set_attr "type" "three")])
11234 \f
11235 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11236 ;; signed & unsigned, and one type of branch.
11237 ;;
11238 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11239 ;; insns, and branches.
11241 (define_expand "cbranch<mode>4"
11242 [(use (match_operator 0 "rs6000_cbranch_operator"
11243 [(match_operand:GPR 1 "gpc_reg_operand" "")
11244 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11245 (use (match_operand 3 ""))]
11246 ""
11247 "
11248 {
11249 /* Take care of the possibility that operands[2] might be negative but
11250 this might be a logical operation. That insn doesn't exist. */
11251 if (GET_CODE (operands[2]) == CONST_INT
11252 && INTVAL (operands[2]) < 0)
11253 {
11254 operands[2] = force_reg (<MODE>mode, operands[2]);
11255 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11256 GET_MODE (operands[0]),
11257 operands[1], operands[2]);
11258 }
11260 rs6000_emit_cbranch (<MODE>mode, operands);
11261 DONE;
11262 }")
11264 (define_expand "cbranch<mode>4"
11265 [(use (match_operator 0 "rs6000_cbranch_operator"
11266 [(match_operand:FP 1 "gpc_reg_operand" "")
11267 (match_operand:FP 2 "gpc_reg_operand" "")]))
11268 (use (match_operand 3 ""))]
11269 ""
11270 "
11271 {
11272 rs6000_emit_cbranch (<MODE>mode, operands);
11273 DONE;
11274 }")
11276 (define_expand "cstore<mode>4"
11277 [(use (match_operator 1 "rs6000_cbranch_operator"
11278 [(match_operand:GPR 2 "gpc_reg_operand" "")
11279 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11280 (clobber (match_operand:SI 0 "register_operand"))]
11281 ""
11282 "
11283 {
11284 /* Take care of the possibility that operands[3] might be negative but
11285 this might be a logical operation. That insn doesn't exist. */
11286 if (GET_CODE (operands[3]) == CONST_INT
11287 && INTVAL (operands[3]) < 0)
11288 {
11289 operands[3] = force_reg (<MODE>mode, operands[3]);
11290 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11291 GET_MODE (operands[1]),
11292 operands[2], operands[3]);
11293 }
11295 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11296 For SEQ, likewise, except that comparisons with zero should be done
11297 with an scc insns. However, due to the order that combine see the
11298 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11299 the cases we don't want to handle or are best handled by portable
11300 code. */
11301 if (GET_CODE (operands[1]) == NE)
11302 FAIL;
11303 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11304 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11305 && operands[3] == const0_rtx)
11306 FAIL;
11307 rs6000_emit_sCOND (<MODE>mode, operands);
11308 DONE;
11309 }")
11311 (define_expand "cstore<mode>4"
11312 [(use (match_operator 1 "rs6000_cbranch_operator"
11313 [(match_operand:FP 2 "gpc_reg_operand" "")
11314 (match_operand:FP 3 "gpc_reg_operand" "")]))
11315 (clobber (match_operand:SI 0 "register_operand"))]
11316 ""
11317 "
11318 {
11319 rs6000_emit_sCOND (<MODE>mode, operands);
11320 DONE;
11321 }")
11324 (define_expand "stack_protect_set"
11325 [(match_operand 0 "memory_operand" "")
11326 (match_operand 1 "memory_operand" "")]
11327 ""
11328 {
11329 #ifdef TARGET_THREAD_SSP_OFFSET
11330 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11331 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11332 operands[1] = gen_rtx_MEM (Pmode, addr);
11333 #endif
11334 if (TARGET_64BIT)
11335 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11336 else
11337 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11338 DONE;
11339 })
11341 (define_insn "stack_protect_setsi"
11342 [(set (match_operand:SI 0 "memory_operand" "=m")
11343 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11344 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11345 "TARGET_32BIT"
11346 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11347 [(set_attr "type" "three")
11348 (set_attr "length" "12")])
11350 (define_insn "stack_protect_setdi"
11351 [(set (match_operand:DI 0 "memory_operand" "=Y")
11352 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11353 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11354 "TARGET_64BIT"
11355 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11356 [(set_attr "type" "three")
11357 (set_attr "length" "12")])
11359 (define_expand "stack_protect_test"
11360 [(match_operand 0 "memory_operand" "")
11361 (match_operand 1 "memory_operand" "")
11362 (match_operand 2 "" "")]
11363 ""
11364 {
11365 rtx test, op0, op1;
11366 #ifdef TARGET_THREAD_SSP_OFFSET
11367 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11368 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11369 operands[1] = gen_rtx_MEM (Pmode, addr);
11370 #endif
11371 op0 = operands[0];
11372 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11373 test = gen_rtx_EQ (VOIDmode, op0, op1);
11374 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11375 DONE;
11376 })
11378 (define_insn "stack_protect_testsi"
11379 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11380 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11381 (match_operand:SI 2 "memory_operand" "m,m")]
11382 UNSPEC_SP_TEST))
11383 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11384 (clobber (match_scratch:SI 3 "=&r,&r"))]
11385 "TARGET_32BIT"
11386 "@
11387 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11388 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11389 [(set_attr "length" "16,20")])
11391 (define_insn "stack_protect_testdi"
11392 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11393 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11394 (match_operand:DI 2 "memory_operand" "Y,Y")]
11395 UNSPEC_SP_TEST))
11396 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11397 (clobber (match_scratch:DI 3 "=&r,&r"))]
11398 "TARGET_64BIT"
11399 "@
11400 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11401 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11402 [(set_attr "length" "16,20")])
11404 \f
11405 ;; Here are the actual compare insns.
11406 (define_insn "*cmp<mode>_internal1"
11407 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11408 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11409 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11410 ""
11411 "cmp<wd>%I2 %0,%1,%2"
11412 [(set_attr "type" "cmp")])
11414 ;; If we are comparing a register for equality with a large constant,
11415 ;; we can do this with an XOR followed by a compare. But this is profitable
11416 ;; only if the large constant is only used for the comparison (and in this
11417 ;; case we already have a register to reuse as scratch).
11418 ;;
11419 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11420 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11422 (define_peephole2
11423 [(set (match_operand:SI 0 "register_operand")
11424 (match_operand:SI 1 "logical_const_operand" ""))
11425 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11426 [(match_dup 0)
11427 (match_operand:SI 2 "logical_const_operand" "")]))
11428 (set (match_operand:CC 4 "cc_reg_operand" "")
11429 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11430 (match_dup 0)))
11431 (set (pc)
11432 (if_then_else (match_operator 6 "equality_operator"
11433 [(match_dup 4) (const_int 0)])
11434 (match_operand 7 "" "")
11435 (match_operand 8 "" "")))]
11436 "peep2_reg_dead_p (3, operands[0])
11437 && peep2_reg_dead_p (4, operands[4])"
11438 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11439 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11440 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11442 {
11443 /* Get the constant we are comparing against, and see what it looks like
11444 when sign-extended from 16 to 32 bits. Then see what constant we could
11445 XOR with SEXTC to get the sign-extended value. */
11446 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11447 SImode,
11448 operands[1], operands[2]);
11449 HOST_WIDE_INT c = INTVAL (cnst);
11450 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11451 HOST_WIDE_INT xorv = c ^ sextc;
11453 operands[9] = GEN_INT (xorv);
11454 operands[10] = GEN_INT (sextc);
11455 })
11457 (define_insn "*cmpsi_internal2"
11458 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11459 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11460 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11461 ""
11462 "cmplw%I2 %0,%1,%b2"
11463 [(set_attr "type" "cmp")])
11465 (define_insn "*cmpdi_internal2"
11466 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11467 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11468 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11469 ""
11470 "cmpld%I2 %0,%1,%b2"
11471 [(set_attr "type" "cmp")])
11473 ;; The following two insns don't exist as single insns, but if we provide
11474 ;; them, we can swap an add and compare, which will enable us to overlap more
11475 ;; of the required delay between a compare and branch. We generate code for
11476 ;; them by splitting.
11478 (define_insn ""
11479 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11480 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11481 (match_operand:SI 2 "short_cint_operand" "i")))
11482 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11483 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11484 ""
11485 "#"
11486 [(set_attr "length" "8")])
11488 (define_insn ""
11489 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11490 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11491 (match_operand:SI 2 "u_short_cint_operand" "i")))
11492 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11493 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11494 ""
11495 "#"
11496 [(set_attr "length" "8")])
11498 (define_split
11499 [(set (match_operand:CC 3 "cc_reg_operand" "")
11500 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11501 (match_operand:SI 2 "short_cint_operand" "")))
11502 (set (match_operand:SI 0 "gpc_reg_operand" "")
11503 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11504 ""
11505 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11506 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11508 (define_split
11509 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11510 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11511 (match_operand:SI 2 "u_short_cint_operand" "")))
11512 (set (match_operand:SI 0 "gpc_reg_operand" "")
11513 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11514 ""
11515 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11516 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11518 (define_insn "*cmpsf_internal1"
11519 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11520 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11521 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11522 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
11523 "fcmpu %0,%1,%2"
11524 [(set_attr "type" "fpcompare")])
11526 (define_insn "*cmpdf_internal1"
11527 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11528 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
11529 (match_operand:DF 2 "gpc_reg_operand" "d")))]
11530 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
11531 && !VECTOR_UNIT_VSX_P (DFmode)"
11532 "fcmpu %0,%1,%2"
11533 [(set_attr "type" "fpcompare")])
11535 ;; Only need to compare second words if first words equal
11536 (define_insn "*cmptf_internal1"
11537 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11538 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11539 (match_operand:TF 2 "gpc_reg_operand" "d")))]
11540 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11541 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11542 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11543 [(set_attr "type" "fpcompare")
11544 (set_attr "length" "12")])
11546 (define_insn_and_split "*cmptf_internal2"
11547 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11548 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
11549 (match_operand:TF 2 "gpc_reg_operand" "d")))
11550 (clobber (match_scratch:DF 3 "=d"))
11551 (clobber (match_scratch:DF 4 "=d"))
11552 (clobber (match_scratch:DF 5 "=d"))
11553 (clobber (match_scratch:DF 6 "=d"))
11554 (clobber (match_scratch:DF 7 "=d"))
11555 (clobber (match_scratch:DF 8 "=d"))
11556 (clobber (match_scratch:DF 9 "=d"))
11557 (clobber (match_scratch:DF 10 "=d"))
11558 (clobber (match_scratch:GPR 11 "=b"))]
11559 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11560 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11561 "#"
11562 "&& reload_completed"
11563 [(set (match_dup 3) (match_dup 14))
11564 (set (match_dup 4) (match_dup 15))
11565 (set (match_dup 9) (abs:DF (match_dup 5)))
11566 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11567 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11568 (label_ref (match_dup 12))
11569 (pc)))
11570 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11571 (set (pc) (label_ref (match_dup 13)))
11572 (match_dup 12)
11573 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11574 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11575 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11576 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11577 (match_dup 13)]
11578 {
11579 REAL_VALUE_TYPE rv;
11580 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11581 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11583 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11584 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11585 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11586 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11587 operands[12] = gen_label_rtx ();
11588 operands[13] = gen_label_rtx ();
11589 real_inf (&rv);
11590 operands[14] = force_const_mem (DFmode,
11591 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11592 operands[15] = force_const_mem (DFmode,
11593 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11594 DFmode));
11595 if (TARGET_TOC)
11596 {
11597 rtx tocref;
11598 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11599 operands[14] = gen_const_mem (DFmode, tocref);
11600 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11601 operands[15] = gen_const_mem (DFmode, tocref);
11602 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11603 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11604 }
11605 })
11606 \f
11607 ;; Now we have the scc insns. We can do some combinations because of the
11608 ;; way the machine works.
11609 ;;
11610 ;; Note that this is probably faster if we can put an insn between the
11611 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11612 ;; cases the insns below which don't use an intermediate CR field will
11613 ;; be used instead.
11614 (define_insn ""
11615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11616 (match_operator:SI 1 "scc_comparison_operator"
11617 [(match_operand 2 "cc_reg_operand" "y")
11618 (const_int 0)]))]
11619 ""
11620 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11621 [(set (attr "type")
11622 (cond [(match_test "TARGET_MFCRF")
11623 (const_string "mfcrf")
11624 ]
11625 (const_string "mfcr")))
11626 (set_attr "length" "8")])
11628 ;; Same as above, but get the GT bit.
11629 (define_insn "move_from_CR_gt_bit"
11630 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11631 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11632 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11633 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11634 [(set_attr "type" "mfcr")
11635 (set_attr "length" "8")])
11637 ;; Same as above, but get the OV/ORDERED bit.
11638 (define_insn "move_from_CR_ov_bit"
11639 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11640 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11641 UNSPEC_MV_CR_OV))]
11642 "TARGET_ISEL"
11643 "mfcr %0\;rlwinm %0,%0,%t1,1"
11644 [(set_attr "type" "mfcr")
11645 (set_attr "length" "8")])
11647 (define_insn ""
11648 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11649 (match_operator:DI 1 "scc_comparison_operator"
11650 [(match_operand 2 "cc_reg_operand" "y")
11651 (const_int 0)]))]
11652 "TARGET_POWERPC64"
11653 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11654 [(set (attr "type")
11655 (cond [(match_test "TARGET_MFCRF")
11656 (const_string "mfcrf")
11657 ]
11658 (const_string "mfcr")))
11659 (set_attr "length" "8")])
11661 (define_insn ""
11662 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11663 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11664 [(match_operand 2 "cc_reg_operand" "y,y")
11665 (const_int 0)])
11666 (const_int 0)))
11667 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11668 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11669 "TARGET_32BIT"
11670 "@
11671 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11672 #"
11673 [(set_attr "type" "delayed_compare")
11674 (set_attr "length" "8,16")])
11676 (define_split
11677 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11678 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11679 [(match_operand 2 "cc_reg_operand" "")
11680 (const_int 0)])
11681 (const_int 0)))
11682 (set (match_operand:SI 3 "gpc_reg_operand" "")
11683 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11684 "TARGET_32BIT && reload_completed"
11685 [(set (match_dup 3)
11686 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11687 (set (match_dup 0)
11688 (compare:CC (match_dup 3)
11689 (const_int 0)))]
11690 "")
11692 (define_insn ""
11693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11694 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11695 [(match_operand 2 "cc_reg_operand" "y")
11696 (const_int 0)])
11697 (match_operand:SI 3 "const_int_operand" "n")))]
11698 ""
11699 "*
11700 {
11701 int is_bit = ccr_bit (operands[1], 1);
11702 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11703 int count;
11705 if (is_bit >= put_bit)
11706 count = is_bit - put_bit;
11707 else
11708 count = 32 - (put_bit - is_bit);
11710 operands[4] = GEN_INT (count);
11711 operands[5] = GEN_INT (put_bit);
11713 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11714 }"
11715 [(set (attr "type")
11716 (cond [(match_test "TARGET_MFCRF")
11717 (const_string "mfcrf")
11718 ]
11719 (const_string "mfcr")))
11720 (set_attr "length" "8")])
11722 (define_insn ""
11723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11724 (compare:CC
11725 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11726 [(match_operand 2 "cc_reg_operand" "y,y")
11727 (const_int 0)])
11728 (match_operand:SI 3 "const_int_operand" "n,n"))
11729 (const_int 0)))
11730 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11731 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11732 (match_dup 3)))]
11733 ""
11734 "*
11735 {
11736 int is_bit = ccr_bit (operands[1], 1);
11737 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11738 int count;
11740 /* Force split for non-cc0 compare. */
11741 if (which_alternative == 1)
11742 return \"#\";
11744 if (is_bit >= put_bit)
11745 count = is_bit - put_bit;
11746 else
11747 count = 32 - (put_bit - is_bit);
11749 operands[5] = GEN_INT (count);
11750 operands[6] = GEN_INT (put_bit);
11752 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11753 }"
11754 [(set_attr "type" "delayed_compare")
11755 (set_attr "length" "8,16")])
11757 (define_split
11758 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11759 (compare:CC
11760 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11761 [(match_operand 2 "cc_reg_operand" "")
11762 (const_int 0)])
11763 (match_operand:SI 3 "const_int_operand" ""))
11764 (const_int 0)))
11765 (set (match_operand:SI 4 "gpc_reg_operand" "")
11766 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11767 (match_dup 3)))]
11768 "reload_completed"
11769 [(set (match_dup 4)
11770 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11771 (match_dup 3)))
11772 (set (match_dup 0)
11773 (compare:CC (match_dup 4)
11774 (const_int 0)))]
11775 "")
11777 ;; There is a 3 cycle delay between consecutive mfcr instructions
11778 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11780 (define_peephole
11781 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11782 (match_operator:SI 1 "scc_comparison_operator"
11783 [(match_operand 2 "cc_reg_operand" "y")
11784 (const_int 0)]))
11785 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11786 (match_operator:SI 4 "scc_comparison_operator"
11787 [(match_operand 5 "cc_reg_operand" "y")
11788 (const_int 0)]))]
11789 "REGNO (operands[2]) != REGNO (operands[5])"
11790 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11791 [(set_attr "type" "mfcr")
11792 (set_attr "length" "12")])
11794 (define_peephole
11795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11796 (match_operator:DI 1 "scc_comparison_operator"
11797 [(match_operand 2 "cc_reg_operand" "y")
11798 (const_int 0)]))
11799 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11800 (match_operator:DI 4 "scc_comparison_operator"
11801 [(match_operand 5 "cc_reg_operand" "y")
11802 (const_int 0)]))]
11803 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11804 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
11805 [(set_attr "type" "mfcr")
11806 (set_attr "length" "12")])
11808 ;; There are some scc insns that can be done directly, without a compare.
11809 ;; These are faster because they don't involve the communications between
11810 ;; the FXU and branch units. In fact, we will be replacing all of the
11811 ;; integer scc insns here or in the portable methods in emit_store_flag.
11812 ;;
11813 ;; Also support (neg (scc ..)) since that construct is used to replace
11814 ;; branches, (plus (scc ..) ..) since that construct is common and
11815 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11816 ;; cases where it is no more expensive than (neg (scc ..)).
11818 ;; Have reload force a constant into a register for the simple insns that
11819 ;; otherwise won't accept constants. We do this because it is faster than
11820 ;; the cmp/mfcr sequence we would otherwise generate.
11822 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11823 (DI "rKJI")])
11825 (define_insn_and_split "*eq<mode>"
11826 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11827 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11828 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11829 ""
11830 "#"
11831 ""
11832 [(set (match_dup 0)
11833 (clz:GPR (match_dup 3)))
11834 (set (match_dup 0)
11835 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11836 {
11837 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11838 {
11839 /* Use output operand as intermediate. */
11840 operands[3] = operands[0];
11842 if (logical_operand (operands[2], <MODE>mode))
11843 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11844 gen_rtx_XOR (<MODE>mode,
11845 operands[1], operands[2])));
11846 else
11847 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11848 gen_rtx_PLUS (<MODE>mode, operands[1],
11849 negate_rtx (<MODE>mode,
11850 operands[2]))));
11851 }
11852 else
11853 operands[3] = operands[1];
11855 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11856 })
11858 (define_insn_and_split "*eq<mode>_compare"
11859 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11860 (compare:CC
11861 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11862 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11863 (const_int 0)))
11864 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11865 (eq:P (match_dup 1) (match_dup 2)))]
11866 "optimize_size"
11867 "#"
11868 "optimize_size"
11869 [(set (match_dup 0)
11870 (clz:P (match_dup 4)))
11871 (parallel [(set (match_dup 3)
11872 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11873 (const_int 0)))
11874 (set (match_dup 0)
11875 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11876 {
11877 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11878 {
11879 /* Use output operand as intermediate. */
11880 operands[4] = operands[0];
11882 if (logical_operand (operands[2], <MODE>mode))
11883 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11884 gen_rtx_XOR (<MODE>mode,
11885 operands[1], operands[2])));
11886 else
11887 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11888 gen_rtx_PLUS (<MODE>mode, operands[1],
11889 negate_rtx (<MODE>mode,
11890 operands[2]))));
11891 }
11892 else
11893 operands[4] = operands[1];
11895 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11896 })
11898 ;; We have insns of the form shown by the first define_insn below. If
11899 ;; there is something inside the comparison operation, we must split it.
11900 (define_split
11901 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11902 (plus:SI (match_operator 1 "comparison_operator"
11903 [(match_operand:SI 2 "" "")
11904 (match_operand:SI 3
11905 "reg_or_cint_operand" "")])
11906 (match_operand:SI 4 "gpc_reg_operand" "")))
11907 (clobber (match_operand:SI 5 "register_operand" ""))]
11908 "! gpc_reg_operand (operands[2], SImode)"
11909 [(set (match_dup 5) (match_dup 2))
11910 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
11911 (match_dup 4)))])
11913 (define_insn "*plus_eqsi"
11914 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11915 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11916 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11917 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11918 "TARGET_32BIT"
11919 "@
11920 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
11921 subfic %0,%1,0\;addze %0,%3
11922 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
11923 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
11924 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
11925 [(set_attr "type" "three,two,three,three,three")
11926 (set_attr "length" "12,8,12,12,12")])
11928 (define_insn "*compare_plus_eqsi"
11929 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11930 (compare:CC
11931 (plus:SI
11932 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11933 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11934 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11935 (const_int 0)))
11936 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11937 "TARGET_32BIT && optimize_size"
11938 "@
11939 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11940 subfic %4,%1,0\;addze. %4,%3
11941 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
11942 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
11943 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
11944 #
11945 #
11946 #
11947 #
11948 #"
11949 [(set_attr "type" "compare")
11950 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11952 (define_split
11953 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11954 (compare:CC
11955 (plus:SI
11956 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11957 (match_operand:SI 2 "scc_eq_operand" ""))
11958 (match_operand:SI 3 "gpc_reg_operand" ""))
11959 (const_int 0)))
11960 (clobber (match_scratch:SI 4 ""))]
11961 "TARGET_32BIT && optimize_size && reload_completed"
11962 [(set (match_dup 4)
11963 (plus:SI (eq:SI (match_dup 1)
11964 (match_dup 2))
11965 (match_dup 3)))
11966 (set (match_dup 0)
11967 (compare:CC (match_dup 4)
11968 (const_int 0)))]
11969 "")
11971 (define_insn "*plus_eqsi_compare"
11972 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11973 (compare:CC
11974 (plus:SI
11975 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11976 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11977 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11978 (const_int 0)))
11979 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11980 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
11981 "TARGET_32BIT && optimize_size"
11982 "@
11983 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11984 subfic %0,%1,0\;addze. %0,%3
11985 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
11986 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
11987 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
11988 #
11989 #
11990 #
11991 #
11992 #"
11993 [(set_attr "type" "compare")
11994 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11996 (define_split
11997 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11998 (compare:CC
11999 (plus:SI
12000 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12001 (match_operand:SI 2 "scc_eq_operand" ""))
12002 (match_operand:SI 3 "gpc_reg_operand" ""))
12003 (const_int 0)))
12004 (set (match_operand:SI 0 "gpc_reg_operand" "")
12005 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12006 "TARGET_32BIT && optimize_size && reload_completed"
12007 [(set (match_dup 0)
12008 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12009 (set (match_dup 4)
12010 (compare:CC (match_dup 0)
12011 (const_int 0)))]
12012 "")
12014 (define_insn "*neg_eq0<mode>"
12015 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12016 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12017 (const_int 0))))]
12018 ""
12019 "addic %0,%1,-1\;subfe %0,%0,%0"
12020 [(set_attr "type" "two")
12021 (set_attr "length" "8")])
12023 (define_insn_and_split "*neg_eq<mode>"
12024 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12025 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12026 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12027 ""
12028 "#"
12029 ""
12030 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12031 {
12032 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12033 {
12034 /* Use output operand as intermediate. */
12035 operands[3] = operands[0];
12037 if (logical_operand (operands[2], <MODE>mode))
12038 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12039 gen_rtx_XOR (<MODE>mode,
12040 operands[1], operands[2])));
12041 else
12042 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12043 gen_rtx_PLUS (<MODE>mode, operands[1],
12044 negate_rtx (<MODE>mode,
12045 operands[2]))));
12046 }
12047 else
12048 operands[3] = operands[1];
12049 })
12051 (define_insn "*ne0_<mode>"
12052 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12053 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12054 (const_int 0)))
12055 (clobber (match_scratch:P 2 "=&r"))]
12056 "!(TARGET_32BIT && TARGET_ISEL)"
12057 "addic %2,%1,-1\;subfe %0,%2,%1"
12058 [(set_attr "type" "two")
12059 (set_attr "length" "8")])
12061 (define_insn "*plus_ne0_<mode>"
12062 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12063 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
12064 (const_int 0))
12065 (match_operand:P 2 "gpc_reg_operand" "r")))
12066 (clobber (match_scratch:P 3 "=&r"))]
12067 ""
12068 "addic %3,%1,-1\;addze %0,%2"
12069 [(set_attr "type" "two")
12070 (set_attr "length" "8")])
12072 (define_insn "*compare_plus_ne0_<mode>"
12073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12074 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12075 (const_int 0))
12076 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12077 (const_int 0)))
12078 (clobber (match_scratch:P 3 "=&r,&r"))
12079 (clobber (match_scratch:P 4 "=X,&r"))]
12080 ""
12081 "@
12082 addic %3,%1,-1\;addze. %3,%2
12083 #"
12084 [(set_attr "type" "compare")
12085 (set_attr "length" "8,12")])
12087 (define_split
12088 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12089 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12090 (const_int 0))
12091 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12092 (clobber (match_scratch:P 3 ""))
12093 (clobber (match_scratch:P 4 ""))]
12094 "reload_completed"
12095 [(parallel [(set (match_dup 3)
12096 (plus:P (ne:P (match_dup 1)
12097 (const_int 0))
12098 (match_dup 2)))
12099 (clobber (match_dup 4))])
12100 (set (match_dup 0)
12101 (compare:CC (match_dup 3)
12102 (const_int 0)))]
12103 "")
12105 ; For combine.
12106 (define_insn "*compare_plus_ne0_<mode>_1"
12107 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12108 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12109 (const_int 0))
12110 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
12111 (clobber (match_scratch:P 3 "=&r,&r"))
12112 (clobber (match_scratch:P 4 "=X,&r"))]
12113 ""
12114 "@
12115 addic %3,%1,-1\;addze. %3,%2
12116 #"
12117 [(set_attr "type" "compare")
12118 (set_attr "length" "8,12")])
12120 (define_split
12121 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
12122 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
12123 (const_int 0))
12124 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
12125 (clobber (match_scratch:P 3 ""))
12126 (clobber (match_scratch:P 4 ""))]
12127 "reload_completed"
12128 [(parallel [(set (match_dup 3)
12129 (plus:P (ne:P (match_dup 1)
12130 (const_int 0))
12131 (match_dup 2)))
12132 (clobber (match_dup 4))])
12133 (set (match_dup 0)
12134 (compare:CC (match_dup 3)
12135 (const_int 0)))]
12136 "")
12138 (define_insn "*plus_ne0_<mode>_compare"
12139 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12140 (compare:CC
12141 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12142 (const_int 0))
12143 (match_operand:P 2 "gpc_reg_operand" "r,r"))
12144 (const_int 0)))
12145 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12146 (plus:P (ne:P (match_dup 1)
12147 (const_int 0))
12148 (match_dup 2)))
12149 (clobber (match_scratch:P 3 "=&r,&r"))]
12150 ""
12151 "@
12152 addic %3,%1,-1\;addze. %0,%2
12153 #"
12154 [(set_attr "type" "compare")
12155 (set_attr "length" "8,12")])
12157 (define_split
12158 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12159 (compare:CC
12160 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
12161 (const_int 0))
12162 (match_operand:P 2 "gpc_reg_operand" ""))
12163 (const_int 0)))
12164 (set (match_operand:P 0 "gpc_reg_operand" "")
12165 (plus:P (ne:P (match_dup 1)
12166 (const_int 0))
12167 (match_dup 2)))
12168 (clobber (match_scratch:P 3 ""))]
12169 "reload_completed"
12170 [(parallel [(set (match_dup 0)
12171 (plus:P (ne:P (match_dup 1)
12172 (const_int 0))
12173 (match_dup 2)))
12174 (clobber (match_dup 3))])
12175 (set (match_dup 4)
12176 (compare:CC (match_dup 0)
12177 (const_int 0)))]
12178 "")
12180 (define_insn "*leu<mode>"
12181 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12182 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12183 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12184 ""
12185 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12186 [(set_attr "type" "three")
12187 (set_attr "length" "12")])
12189 (define_insn "*leu<mode>_compare"
12190 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12191 (compare:CC
12192 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12193 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12194 (const_int 0)))
12195 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12196 (leu:P (match_dup 1) (match_dup 2)))]
12197 ""
12198 "@
12199 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12200 #"
12201 [(set_attr "type" "compare")
12202 (set_attr "length" "12,16")])
12204 (define_split
12205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12206 (compare:CC
12207 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12208 (match_operand:P 2 "reg_or_short_operand" ""))
12209 (const_int 0)))
12210 (set (match_operand:P 0 "gpc_reg_operand" "")
12211 (leu:P (match_dup 1) (match_dup 2)))]
12212 "reload_completed"
12213 [(set (match_dup 0)
12214 (leu:P (match_dup 1) (match_dup 2)))
12215 (set (match_dup 3)
12216 (compare:CC (match_dup 0)
12217 (const_int 0)))]
12218 "")
12220 (define_insn "*plus_leu<mode>"
12221 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12222 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12223 (match_operand:P 2 "reg_or_short_operand" "rI"))
12224 (match_operand:P 3 "gpc_reg_operand" "r")))]
12225 ""
12226 "subf%I2c %0,%1,%2\;addze %0,%3"
12227 [(set_attr "type" "two")
12228 (set_attr "length" "8")])
12230 (define_insn ""
12231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12232 (compare:CC
12233 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12234 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12235 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12236 (const_int 0)))
12237 (clobber (match_scratch:SI 4 "=&r,&r"))]
12238 "TARGET_32BIT"
12239 "@
12240 subf%I2c %4,%1,%2\;addze. %4,%3
12241 #"
12242 [(set_attr "type" "compare")
12243 (set_attr "length" "8,12")])
12245 (define_split
12246 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12247 (compare:CC
12248 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12249 (match_operand:SI 2 "reg_or_short_operand" ""))
12250 (match_operand:SI 3 "gpc_reg_operand" ""))
12251 (const_int 0)))
12252 (clobber (match_scratch:SI 4 ""))]
12253 "TARGET_32BIT && reload_completed"
12254 [(set (match_dup 4)
12255 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12256 (match_dup 3)))
12257 (set (match_dup 0)
12258 (compare:CC (match_dup 4)
12259 (const_int 0)))]
12260 "")
12262 (define_insn ""
12263 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12264 (compare:CC
12265 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12266 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12267 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12268 (const_int 0)))
12269 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12270 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12271 "TARGET_32BIT"
12272 "@
12273 subf%I2c %0,%1,%2\;addze. %0,%3
12274 #"
12275 [(set_attr "type" "compare")
12276 (set_attr "length" "8,12")])
12278 (define_split
12279 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12280 (compare:CC
12281 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12282 (match_operand:SI 2 "reg_or_short_operand" ""))
12283 (match_operand:SI 3 "gpc_reg_operand" ""))
12284 (const_int 0)))
12285 (set (match_operand:SI 0 "gpc_reg_operand" "")
12286 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12287 "TARGET_32BIT && reload_completed"
12288 [(set (match_dup 0)
12289 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12290 (set (match_dup 4)
12291 (compare:CC (match_dup 0)
12292 (const_int 0)))]
12293 "")
12295 (define_insn "*neg_leu<mode>"
12296 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12297 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12298 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12299 ""
12300 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
12301 [(set_attr "type" "three")
12302 (set_attr "length" "12")])
12304 (define_insn "*and_neg_leu<mode>"
12305 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12306 (and:P (neg:P
12307 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12308 (match_operand:P 2 "reg_or_short_operand" "rI")))
12309 (match_operand:P 3 "gpc_reg_operand" "r")))]
12310 ""
12311 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
12312 [(set_attr "type" "three")
12313 (set_attr "length" "12")])
12315 (define_insn ""
12316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12317 (compare:CC
12318 (and:SI (neg:SI
12319 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12320 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12321 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12322 (const_int 0)))
12323 (clobber (match_scratch:SI 4 "=&r,&r"))]
12324 "TARGET_32BIT"
12325 "@
12326 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
12327 #"
12328 [(set_attr "type" "compare")
12329 (set_attr "length" "12,16")])
12331 (define_split
12332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12333 (compare:CC
12334 (and:SI (neg:SI
12335 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12336 (match_operand:SI 2 "reg_or_short_operand" "")))
12337 (match_operand:SI 3 "gpc_reg_operand" ""))
12338 (const_int 0)))
12339 (clobber (match_scratch:SI 4 ""))]
12340 "TARGET_32BIT && reload_completed"
12341 [(set (match_dup 4)
12342 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12343 (match_dup 3)))
12344 (set (match_dup 0)
12345 (compare:CC (match_dup 4)
12346 (const_int 0)))]
12347 "")
12349 (define_insn ""
12350 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12351 (compare:CC
12352 (and:SI (neg:SI
12353 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12354 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12355 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12356 (const_int 0)))
12357 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12358 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12359 "TARGET_32BIT"
12360 "@
12361 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
12362 #"
12363 [(set_attr "type" "compare")
12364 (set_attr "length" "12,16")])
12366 (define_split
12367 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12368 (compare:CC
12369 (and:SI (neg:SI
12370 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12371 (match_operand:SI 2 "reg_or_short_operand" "")))
12372 (match_operand:SI 3 "gpc_reg_operand" ""))
12373 (const_int 0)))
12374 (set (match_operand:SI 0 "gpc_reg_operand" "")
12375 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12376 "TARGET_32BIT && reload_completed"
12377 [(set (match_dup 0)
12378 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12379 (match_dup 3)))
12380 (set (match_dup 4)
12381 (compare:CC (match_dup 0)
12382 (const_int 0)))]
12383 "")
12385 (define_insn_and_split "*ltu<mode>"
12386 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12387 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12388 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12389 ""
12390 "#"
12391 ""
12392 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12393 (set (match_dup 0) (neg:P (match_dup 0)))]
12394 "")
12396 (define_insn_and_split "*ltu<mode>_compare"
12397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12398 (compare:CC
12399 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12400 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12401 (const_int 0)))
12402 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12403 (ltu:P (match_dup 1) (match_dup 2)))]
12404 ""
12405 "#"
12406 ""
12407 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12408 (parallel [(set (match_dup 3)
12409 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12410 (set (match_dup 0) (neg:P (match_dup 0)))])]
12411 "")
12413 (define_insn_and_split "*plus_ltu<mode>"
12414 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12415 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12416 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12417 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12418 ""
12419 "#"
12420 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12421 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12422 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12423 "")
12425 (define_insn_and_split "*plus_ltu<mode>_compare"
12426 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12427 (compare:CC
12428 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12429 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12430 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12431 (const_int 0)))
12432 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12433 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12434 ""
12435 "#"
12436 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12437 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12438 (parallel [(set (match_dup 4)
12439 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12440 (const_int 0)))
12441 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12442 "")
12444 (define_insn "*neg_ltu<mode>"
12445 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12446 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12447 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12448 ""
12449 "@
12450 subfc %0,%2,%1\;subfe %0,%0,%0
12451 addic %0,%1,%n2\;subfe %0,%0,%0"
12452 [(set_attr "type" "two")
12453 (set_attr "length" "8")])
12455 (define_insn "*geu<mode>"
12456 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12457 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12458 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12459 ""
12460 "@
12461 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12462 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12463 [(set_attr "type" "three")
12464 (set_attr "length" "12")])
12466 (define_insn "*geu<mode>_compare"
12467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12468 (compare:CC
12469 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12470 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12471 (const_int 0)))
12472 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12473 (geu:P (match_dup 1) (match_dup 2)))]
12474 ""
12475 "@
12476 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
12477 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12478 #
12479 #"
12480 [(set_attr "type" "compare")
12481 (set_attr "length" "12,12,16,16")])
12483 (define_split
12484 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12485 (compare:CC
12486 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12487 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12488 (const_int 0)))
12489 (set (match_operand:P 0 "gpc_reg_operand" "")
12490 (geu:P (match_dup 1) (match_dup 2)))]
12491 "reload_completed"
12492 [(set (match_dup 0)
12493 (geu:P (match_dup 1) (match_dup 2)))
12494 (set (match_dup 3)
12495 (compare:CC (match_dup 0)
12496 (const_int 0)))]
12497 "")
12499 (define_insn "*plus_geu<mode>"
12500 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12501 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12502 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12503 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12504 ""
12505 "@
12506 subfc %0,%2,%1\;addze %0,%3
12507 addic %0,%1,%n2\;addze %0,%3"
12508 [(set_attr "type" "two")
12509 (set_attr "length" "8")])
12511 (define_insn ""
12512 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12513 (compare:CC
12514 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12515 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12516 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12517 (const_int 0)))
12518 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12519 "TARGET_32BIT"
12520 "@
12521 subfc %4,%2,%1\;addze. %4,%3
12522 addic %4,%1,%n2\;addze. %4,%3
12523 #
12524 #"
12525 [(set_attr "type" "compare")
12526 (set_attr "length" "8,8,12,12")])
12528 (define_split
12529 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12530 (compare:CC
12531 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12532 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12533 (match_operand:SI 3 "gpc_reg_operand" ""))
12534 (const_int 0)))
12535 (clobber (match_scratch:SI 4 ""))]
12536 "TARGET_32BIT && reload_completed"
12537 [(set (match_dup 4)
12538 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12539 (match_dup 3)))
12540 (set (match_dup 0)
12541 (compare:CC (match_dup 4)
12542 (const_int 0)))]
12543 "")
12545 (define_insn ""
12546 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12547 (compare:CC
12548 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12549 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12550 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12551 (const_int 0)))
12552 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12553 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12554 "TARGET_32BIT"
12555 "@
12556 subfc %0,%2,%1\;addze. %0,%3
12557 addic %0,%1,%n2\;addze. %0,%3
12558 #
12559 #"
12560 [(set_attr "type" "compare")
12561 (set_attr "length" "8,8,12,12")])
12563 (define_split
12564 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12565 (compare:CC
12566 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12567 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12568 (match_operand:SI 3 "gpc_reg_operand" ""))
12569 (const_int 0)))
12570 (set (match_operand:SI 0 "gpc_reg_operand" "")
12571 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12572 "TARGET_32BIT && reload_completed"
12573 [(set (match_dup 0)
12574 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12575 (set (match_dup 4)
12576 (compare:CC (match_dup 0)
12577 (const_int 0)))]
12578 "")
12580 (define_insn "*neg_geu<mode>"
12581 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12582 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12583 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
12584 ""
12585 "@
12586 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
12587 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
12588 [(set_attr "type" "three")
12589 (set_attr "length" "12")])
12591 (define_insn "*and_neg_geu<mode>"
12592 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12593 (and:P (neg:P
12594 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12595 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
12596 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
12597 ""
12598 "@
12599 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
12600 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
12601 [(set_attr "type" "three")
12602 (set_attr "length" "12")])
12604 (define_insn ""
12605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12606 (compare:CC
12607 (and:SI (neg:SI
12608 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12609 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12610 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12611 (const_int 0)))
12612 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12613 "TARGET_32BIT"
12614 "@
12615 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
12616 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
12617 #
12618 #"
12619 [(set_attr "type" "compare")
12620 (set_attr "length" "12,12,16,16")])
12622 (define_split
12623 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12624 (compare:CC
12625 (and:SI (neg:SI
12626 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12627 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12628 (match_operand:SI 3 "gpc_reg_operand" ""))
12629 (const_int 0)))
12630 (clobber (match_scratch:SI 4 ""))]
12631 "TARGET_32BIT && reload_completed"
12632 [(set (match_dup 4)
12633 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12634 (match_dup 3)))
12635 (set (match_dup 0)
12636 (compare:CC (match_dup 4)
12637 (const_int 0)))]
12638 "")
12640 (define_insn ""
12641 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12642 (compare:CC
12643 (and:SI (neg:SI
12644 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12645 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12646 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12647 (const_int 0)))
12648 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12649 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12650 "TARGET_32BIT"
12651 "@
12652 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
12653 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
12654 #
12655 #"
12656 [(set_attr "type" "compare")
12657 (set_attr "length" "12,12,16,16")])
12659 (define_split
12660 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12661 (compare:CC
12662 (and:SI (neg:SI
12663 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12664 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12665 (match_operand:SI 3 "gpc_reg_operand" ""))
12666 (const_int 0)))
12667 (set (match_operand:SI 0 "gpc_reg_operand" "")
12668 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12669 "TARGET_32BIT && reload_completed"
12670 [(set (match_dup 0)
12671 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12672 (set (match_dup 4)
12673 (compare:CC (match_dup 0)
12674 (const_int 0)))]
12675 "")
12677 (define_insn "*plus_gt0<mode>"
12678 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12679 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
12680 (const_int 0))
12681 (match_operand:P 2 "gpc_reg_operand" "r")))]
12682 ""
12683 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
12684 [(set_attr "type" "three")
12685 (set_attr "length" "12")])
12687 (define_insn ""
12688 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12689 (compare:CC
12690 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12691 (const_int 0))
12692 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12693 (const_int 0)))
12694 (clobber (match_scratch:SI 3 "=&r,&r"))]
12695 "TARGET_32BIT"
12696 "@
12697 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12698 #"
12699 [(set_attr "type" "compare")
12700 (set_attr "length" "12,16")])
12702 (define_split
12703 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12704 (compare:CC
12705 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12706 (const_int 0))
12707 (match_operand:SI 2 "gpc_reg_operand" ""))
12708 (const_int 0)))
12709 (clobber (match_scratch:SI 3 ""))]
12710 "TARGET_32BIT && reload_completed"
12711 [(set (match_dup 3)
12712 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12713 (match_dup 2)))
12714 (set (match_dup 0)
12715 (compare:CC (match_dup 3)
12716 (const_int 0)))]
12717 "")
12719 (define_insn ""
12720 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12721 (compare:CC
12722 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12723 (const_int 0))
12724 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12725 (const_int 0)))
12726 (clobber (match_scratch:DI 3 "=&r,&r"))]
12727 "TARGET_64BIT"
12728 "@
12729 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12730 #"
12731 [(set_attr "type" "compare")
12732 (set_attr "length" "12,16")])
12734 (define_split
12735 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12736 (compare:CC
12737 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12738 (const_int 0))
12739 (match_operand:DI 2 "gpc_reg_operand" ""))
12740 (const_int 0)))
12741 (clobber (match_scratch:DI 3 ""))]
12742 "TARGET_64BIT && reload_completed"
12743 [(set (match_dup 3)
12744 (plus:DI (gt:DI (match_dup 1) (const_int 0))
12745 (match_dup 2)))
12746 (set (match_dup 0)
12747 (compare:CC (match_dup 3)
12748 (const_int 0)))]
12749 "")
12751 (define_insn ""
12752 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12753 (compare:CC
12754 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12755 (const_int 0))
12756 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12757 (const_int 0)))
12758 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12759 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12760 "TARGET_32BIT"
12761 "@
12762 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12763 #"
12764 [(set_attr "type" "compare")
12765 (set_attr "length" "12,16")])
12767 (define_split
12768 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12769 (compare:CC
12770 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12771 (const_int 0))
12772 (match_operand:SI 2 "gpc_reg_operand" ""))
12773 (const_int 0)))
12774 (set (match_operand:SI 0 "gpc_reg_operand" "")
12775 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
12776 "TARGET_32BIT && reload_completed"
12777 [(set (match_dup 0)
12778 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12779 (set (match_dup 3)
12780 (compare:CC (match_dup 0)
12781 (const_int 0)))]
12782 "")
12784 (define_insn ""
12785 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12786 (compare:CC
12787 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12788 (const_int 0))
12789 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12790 (const_int 0)))
12791 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12792 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12793 "TARGET_64BIT"
12794 "@
12795 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
12796 #"
12797 [(set_attr "type" "compare")
12798 (set_attr "length" "12,16")])
12800 (define_split
12801 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
12802 (compare:CC
12803 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12804 (const_int 0))
12805 (match_operand:DI 2 "gpc_reg_operand" ""))
12806 (const_int 0)))
12807 (set (match_operand:DI 0 "gpc_reg_operand" "")
12808 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
12809 "TARGET_64BIT && reload_completed"
12810 [(set (match_dup 0)
12811 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12812 (set (match_dup 3)
12813 (compare:CC (match_dup 0)
12814 (const_int 0)))]
12815 "")
12817 (define_insn_and_split "*gtu<mode>"
12818 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12819 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12820 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12821 ""
12822 "#"
12823 ""
12824 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12825 (set (match_dup 0) (neg:P (match_dup 0)))]
12826 "")
12828 (define_insn_and_split "*gtu<mode>_compare"
12829 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12830 (compare:CC
12831 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12832 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12833 (const_int 0)))
12834 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12835 (gtu:P (match_dup 1) (match_dup 2)))]
12836 ""
12837 "#"
12838 ""
12839 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12840 (parallel [(set (match_dup 3)
12841 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12842 (set (match_dup 0) (neg:P (match_dup 0)))])]
12843 "")
12845 (define_insn_and_split "*plus_gtu<mode>"
12846 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12847 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12848 (match_operand:P 2 "reg_or_short_operand" "rI"))
12849 (match_operand:P 3 "reg_or_short_operand" "rI")))]
12850 ""
12851 "#"
12852 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12853 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12854 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12855 "")
12857 (define_insn_and_split "*plus_gtu<mode>_compare"
12858 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12859 (compare:CC
12860 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12861 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
12862 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12863 (const_int 0)))
12864 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12865 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12866 ""
12867 "#"
12868 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12869 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
12870 (parallel [(set (match_dup 4)
12871 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12872 (const_int 0)))
12873 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12874 "")
12876 (define_insn "*neg_gtu<mode>"
12877 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12878 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
12879 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12880 ""
12881 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12882 [(set_attr "type" "two")
12883 (set_attr "length" "8")])
12885 \f
12886 ;; Define both directions of branch and return. If we need a reload
12887 ;; register, we'd rather use CR0 since it is much easier to copy a
12888 ;; register CC value to there.
12890 (define_insn ""
12891 [(set (pc)
12892 (if_then_else (match_operator 1 "branch_comparison_operator"
12893 [(match_operand 2
12894 "cc_reg_operand" "y")
12895 (const_int 0)])
12896 (label_ref (match_operand 0 "" ""))
12897 (pc)))]
12898 ""
12899 "*
12900 {
12901 return output_cbranch (operands[1], \"%l0\", 0, insn);
12902 }"
12903 [(set_attr "type" "branch")])
12905 (define_insn ""
12906 [(set (pc)
12907 (if_then_else (match_operator 0 "branch_comparison_operator"
12908 [(match_operand 1
12909 "cc_reg_operand" "y")
12910 (const_int 0)])
12911 (any_return)
12912 (pc)))]
12913 "<return_pred>"
12914 "*
12915 {
12916 return output_cbranch (operands[0], NULL, 0, insn);
12917 }"
12918 [(set_attr "type" "jmpreg")
12919 (set_attr "length" "4")])
12921 (define_insn ""
12922 [(set (pc)
12923 (if_then_else (match_operator 1 "branch_comparison_operator"
12924 [(match_operand 2
12925 "cc_reg_operand" "y")
12926 (const_int 0)])
12927 (pc)
12928 (label_ref (match_operand 0 "" ""))))]
12929 ""
12930 "*
12931 {
12932 return output_cbranch (operands[1], \"%l0\", 1, insn);
12933 }"
12934 [(set_attr "type" "branch")])
12936 (define_insn ""
12937 [(set (pc)
12938 (if_then_else (match_operator 0 "branch_comparison_operator"
12939 [(match_operand 1
12940 "cc_reg_operand" "y")
12941 (const_int 0)])
12942 (pc)
12943 (any_return)))]
12944 "<return_pred>"
12945 "*
12946 {
12947 return output_cbranch (operands[0], NULL, 1, insn);
12948 }"
12949 [(set_attr "type" "jmpreg")
12950 (set_attr "length" "4")])
12952 ;; Logic on condition register values.
12954 ; This pattern matches things like
12955 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12956 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12957 ; (const_int 1)))
12958 ; which are generated by the branch logic.
12959 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
12961 (define_insn "*cceq_ior_compare"
12962 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12963 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12964 [(match_operator:SI 2
12965 "branch_positive_comparison_operator"
12966 [(match_operand 3
12967 "cc_reg_operand" "y,y")
12968 (const_int 0)])
12969 (match_operator:SI 4
12970 "branch_positive_comparison_operator"
12971 [(match_operand 5
12972 "cc_reg_operand" "0,y")
12973 (const_int 0)])])
12974 (const_int 1)))]
12975 ""
12976 "cr%q1 %E0,%j2,%j4"
12977 [(set_attr "type" "cr_logical,delayed_cr")])
12979 ; Why is the constant -1 here, but 1 in the previous pattern?
12980 ; Because ~1 has all but the low bit set.
12981 (define_insn ""
12982 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
12983 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12984 [(not:SI (match_operator:SI 2
12985 "branch_positive_comparison_operator"
12986 [(match_operand 3
12987 "cc_reg_operand" "y,y")
12988 (const_int 0)]))
12989 (match_operator:SI 4
12990 "branch_positive_comparison_operator"
12991 [(match_operand 5
12992 "cc_reg_operand" "0,y")
12993 (const_int 0)])])
12994 (const_int -1)))]
12995 ""
12996 "cr%q1 %E0,%j2,%j4"
12997 [(set_attr "type" "cr_logical,delayed_cr")])
12999 (define_insn "*cceq_rev_compare"
13000 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13001 (compare:CCEQ (match_operator:SI 1
13002 "branch_positive_comparison_operator"
13003 [(match_operand 2
13004 "cc_reg_operand" "0,y")
13005 (const_int 0)])
13006 (const_int 0)))]
13007 ""
13008 "crnot %E0,%j1"
13009 [(set_attr "type" "cr_logical,delayed_cr")])
13011 ;; If we are comparing the result of two comparisons, this can be done
13012 ;; using creqv or crxor.
13014 (define_insn_and_split ""
13015 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13016 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13017 [(match_operand 2 "cc_reg_operand" "y")
13018 (const_int 0)])
13019 (match_operator 3 "branch_comparison_operator"
13020 [(match_operand 4 "cc_reg_operand" "y")
13021 (const_int 0)])))]
13022 ""
13023 "#"
13024 ""
13025 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13026 (match_dup 5)))]
13027 "
13028 {
13029 int positive_1, positive_2;
13031 positive_1 = branch_positive_comparison_operator (operands[1],
13032 GET_MODE (operands[1]));
13033 positive_2 = branch_positive_comparison_operator (operands[3],
13034 GET_MODE (operands[3]));
13036 if (! positive_1)
13037 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13038 GET_CODE (operands[1])),
13039 SImode,
13040 operands[2], const0_rtx);
13041 else if (GET_MODE (operands[1]) != SImode)
13042 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13043 operands[2], const0_rtx);
13045 if (! positive_2)
13046 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13047 GET_CODE (operands[3])),
13048 SImode,
13049 operands[4], const0_rtx);
13050 else if (GET_MODE (operands[3]) != SImode)
13051 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13052 operands[4], const0_rtx);
13054 if (positive_1 == positive_2)
13055 {
13056 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13057 operands[5] = constm1_rtx;
13058 }
13059 else
13060 {
13061 operands[5] = const1_rtx;
13062 }
13063 }")
13065 ;; Unconditional branch and return.
13067 (define_insn "jump"
13068 [(set (pc)
13069 (label_ref (match_operand 0 "" "")))]
13070 ""
13071 "b %l0"
13072 [(set_attr "type" "branch")])
13074 (define_insn "<return_str>return"
13075 [(any_return)]
13076 "<return_pred>"
13077 "blr"
13078 [(set_attr "type" "jmpreg")])
13080 (define_expand "indirect_jump"
13081 [(set (pc) (match_operand 0 "register_operand" ""))])
13083 (define_insn "*indirect_jump<mode>"
13084 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13085 ""
13086 "@
13087 bctr
13088 blr"
13089 [(set_attr "type" "jmpreg")])
13091 ;; Table jump for switch statements:
13092 (define_expand "tablejump"
13093 [(use (match_operand 0 "" ""))
13094 (use (label_ref (match_operand 1 "" "")))]
13095 ""
13096 "
13097 {
13098 if (TARGET_32BIT)
13099 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13100 else
13101 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13102 DONE;
13103 }")
13105 (define_expand "tablejumpsi"
13106 [(set (match_dup 3)
13107 (plus:SI (match_operand:SI 0 "" "")
13108 (match_dup 2)))
13109 (parallel [(set (pc) (match_dup 3))
13110 (use (label_ref (match_operand 1 "" "")))])]
13111 "TARGET_32BIT"
13112 "
13113 { operands[0] = force_reg (SImode, operands[0]);
13114 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13115 operands[3] = gen_reg_rtx (SImode);
13116 }")
13118 (define_expand "tablejumpdi"
13119 [(set (match_dup 4)
13120 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13121 (set (match_dup 3)
13122 (plus:DI (match_dup 4)
13123 (match_dup 2)))
13124 (parallel [(set (pc) (match_dup 3))
13125 (use (label_ref (match_operand 1 "" "")))])]
13126 "TARGET_64BIT"
13127 "
13128 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13129 operands[3] = gen_reg_rtx (DImode);
13130 operands[4] = gen_reg_rtx (DImode);
13131 }")
13133 (define_insn "*tablejump<mode>_internal1"
13134 [(set (pc)
13135 (match_operand:P 0 "register_operand" "c,*l"))
13136 (use (label_ref (match_operand 1 "" "")))]
13137 ""
13138 "@
13139 bctr
13140 blr"
13141 [(set_attr "type" "jmpreg")])
13143 (define_insn "nop"
13144 [(const_int 0)]
13145 ""
13146 "nop")
13148 (define_insn "group_ending_nop"
13149 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13150 ""
13151 "*
13152 {
13153 if (rs6000_cpu_attr == CPU_POWER6)
13154 return \"ori 1,1,0\";
13155 return \"ori 2,2,0\";
13156 }")
13157 \f
13158 ;; Define the subtract-one-and-jump insns, starting with the template
13159 ;; so loop.c knows what to generate.
13161 (define_expand "doloop_end"
13162 [(use (match_operand 0 "" "")) ; loop pseudo
13163 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13164 (use (match_operand 2 "" "")) ; max iterations
13165 (use (match_operand 3 "" "")) ; loop level
13166 (use (match_operand 4 "" "")) ; label
13167 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0
13168 ""
13169 "
13170 {
13171 /* Only use this on innermost loops. */
13172 if (INTVAL (operands[3]) > 1)
13173 FAIL;
13174 if (TARGET_64BIT)
13175 {
13176 if (GET_MODE (operands[0]) != DImode)
13177 FAIL;
13178 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13179 }
13180 else
13181 {
13182 if (GET_MODE (operands[0]) != SImode)
13183 FAIL;
13184 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13185 }
13186 DONE;
13187 }")
13189 (define_expand "ctr<mode>"
13190 [(parallel [(set (pc)
13191 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13192 (const_int 1))
13193 (label_ref (match_operand 1 "" ""))
13194 (pc)))
13195 (set (match_dup 0)
13196 (plus:P (match_dup 0)
13197 (const_int -1)))
13198 (clobber (match_scratch:CC 2 ""))
13199 (clobber (match_scratch:P 3 ""))])]
13200 ""
13201 "")
13203 ;; We need to be able to do this for any operand, including MEM, or we
13204 ;; will cause reload to blow up since we don't allow output reloads on
13205 ;; JUMP_INSNs.
13206 ;; For the length attribute to be calculated correctly, the
13207 ;; label MUST be operand 0.
13209 (define_insn "*ctr<mode>_internal1"
13210 [(set (pc)
13211 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13212 (const_int 1))
13213 (label_ref (match_operand 0 "" ""))
13214 (pc)))
13215 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13216 (plus:P (match_dup 1)
13217 (const_int -1)))
13218 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13219 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13220 ""
13221 "*
13222 {
13223 if (which_alternative != 0)
13224 return \"#\";
13225 else if (get_attr_length (insn) == 4)
13226 return \"bdnz %l0\";
13227 else
13228 return \"bdz $+8\;b %l0\";
13229 }"
13230 [(set_attr "type" "branch")
13231 (set_attr "length" "*,12,16,16")])
13233 (define_insn "*ctr<mode>_internal2"
13234 [(set (pc)
13235 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13236 (const_int 1))
13237 (pc)
13238 (label_ref (match_operand 0 "" ""))))
13239 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13240 (plus:P (match_dup 1)
13241 (const_int -1)))
13242 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13243 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13244 ""
13245 "*
13246 {
13247 if (which_alternative != 0)
13248 return \"#\";
13249 else if (get_attr_length (insn) == 4)
13250 return \"bdz %l0\";
13251 else
13252 return \"bdnz $+8\;b %l0\";
13253 }"
13254 [(set_attr "type" "branch")
13255 (set_attr "length" "*,12,16,16")])
13257 ;; Similar but use EQ
13259 (define_insn "*ctr<mode>_internal5"
13260 [(set (pc)
13261 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13262 (const_int 1))
13263 (label_ref (match_operand 0 "" ""))
13264 (pc)))
13265 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13266 (plus:P (match_dup 1)
13267 (const_int -1)))
13268 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13269 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13270 ""
13271 "*
13272 {
13273 if (which_alternative != 0)
13274 return \"#\";
13275 else if (get_attr_length (insn) == 4)
13276 return \"bdz %l0\";
13277 else
13278 return \"bdnz $+8\;b %l0\";
13279 }"
13280 [(set_attr "type" "branch")
13281 (set_attr "length" "*,12,16,16")])
13283 (define_insn "*ctr<mode>_internal6"
13284 [(set (pc)
13285 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13286 (const_int 1))
13287 (pc)
13288 (label_ref (match_operand 0 "" ""))))
13289 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
13290 (plus:P (match_dup 1)
13291 (const_int -1)))
13292 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13293 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13294 ""
13295 "*
13296 {
13297 if (which_alternative != 0)
13298 return \"#\";
13299 else if (get_attr_length (insn) == 4)
13300 return \"bdnz %l0\";
13301 else
13302 return \"bdz $+8\;b %l0\";
13303 }"
13304 [(set_attr "type" "branch")
13305 (set_attr "length" "*,12,16,16")])
13307 ;; Now the splitters if we could not allocate the CTR register
13309 (define_split
13310 [(set (pc)
13311 (if_then_else (match_operator 2 "comparison_operator"
13312 [(match_operand:P 1 "gpc_reg_operand" "")
13313 (const_int 1)])
13314 (match_operand 5 "" "")
13315 (match_operand 6 "" "")))
13316 (set (match_operand:P 0 "gpc_reg_operand" "")
13317 (plus:P (match_dup 1) (const_int -1)))
13318 (clobber (match_scratch:CC 3 ""))
13319 (clobber (match_scratch:P 4 ""))]
13320 "reload_completed"
13321 [(parallel [(set (match_dup 3)
13322 (compare:CC (plus:P (match_dup 1)
13323 (const_int -1))
13324 (const_int 0)))
13325 (set (match_dup 0)
13326 (plus:P (match_dup 1)
13327 (const_int -1)))])
13328 (set (pc) (if_then_else (match_dup 7)
13329 (match_dup 5)
13330 (match_dup 6)))]
13331 "
13332 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13333 operands[3], const0_rtx); }")
13335 (define_split
13336 [(set (pc)
13337 (if_then_else (match_operator 2 "comparison_operator"
13338 [(match_operand:P 1 "gpc_reg_operand" "")
13339 (const_int 1)])
13340 (match_operand 5 "" "")
13341 (match_operand 6 "" "")))
13342 (set (match_operand:P 0 "nonimmediate_operand" "")
13343 (plus:P (match_dup 1) (const_int -1)))
13344 (clobber (match_scratch:CC 3 ""))
13345 (clobber (match_scratch:P 4 ""))]
13346 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13347 [(parallel [(set (match_dup 3)
13348 (compare:CC (plus:P (match_dup 1)
13349 (const_int -1))
13350 (const_int 0)))
13351 (set (match_dup 4)
13352 (plus:P (match_dup 1)
13353 (const_int -1)))])
13354 (set (match_dup 0)
13355 (match_dup 4))
13356 (set (pc) (if_then_else (match_dup 7)
13357 (match_dup 5)
13358 (match_dup 6)))]
13359 "
13360 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13361 operands[3], const0_rtx); }")
13362 \f
13363 (define_insn "trap"
13364 [(trap_if (const_int 1) (const_int 0))]
13365 ""
13366 "trap"
13367 [(set_attr "type" "trap")])
13369 (define_expand "ctrap<mode>4"
13370 [(trap_if (match_operator 0 "ordered_comparison_operator"
13371 [(match_operand:GPR 1 "register_operand")
13372 (match_operand:GPR 2 "reg_or_short_operand")])
13373 (match_operand 3 "zero_constant" ""))]
13374 ""
13375 "")
13377 (define_insn ""
13378 [(trap_if (match_operator 0 "ordered_comparison_operator"
13379 [(match_operand:GPR 1 "register_operand" "r")
13380 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13381 (const_int 0))]
13382 ""
13383 "t<wd>%V0%I2 %1,%2"
13384 [(set_attr "type" "trap")])
13385 \f
13386 ;; Insns related to generating the function prologue and epilogue.
13388 (define_expand "prologue"
13389 [(use (const_int 0))]
13390 ""
13391 {
13392 rs6000_emit_prologue ();
13393 if (!TARGET_SCHED_PROLOG)
13394 emit_insn (gen_blockage ());
13395 DONE;
13396 })
13398 (define_insn "*movesi_from_cr_one"
13399 [(match_parallel 0 "mfcr_operation"
13400 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13401 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13402 (match_operand 3 "immediate_operand" "n")]
13403 UNSPEC_MOVESI_FROM_CR))])]
13404 "TARGET_MFCRF"
13405 "*
13406 {
13407 int mask = 0;
13408 int i;
13409 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13410 {
13411 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13412 operands[4] = GEN_INT (mask);
13413 output_asm_insn (\"mfcr %1,%4\", operands);
13414 }
13415 return \"\";
13416 }"
13417 [(set_attr "type" "mfcrf")])
13419 (define_insn "movesi_from_cr"
13420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13421 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13422 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13423 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
13424 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
13425 UNSPEC_MOVESI_FROM_CR))]
13426 ""
13427 "mfcr %0"
13428 [(set_attr "type" "mfcr")])
13430 (define_insn "*stmw"
13431 [(match_parallel 0 "stmw_operation"
13432 [(set (match_operand:SI 1 "memory_operand" "=m")
13433 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13434 "TARGET_MULTIPLE"
13435 "stmw %2,%1"
13436 [(set_attr "type" "store_ux")])
13438 ; The following comment applies to:
13439 ; save_gpregs_*
13440 ; save_fpregs_*
13441 ; restore_gpregs*
13442 ; return_and_restore_gpregs*
13443 ; return_and_restore_fpregs*
13444 ; return_and_restore_fpregs_aix*
13445 ;
13446 ; The out-of-line save / restore functions expects one input argument.
13447 ; Since those are not standard call_insn's, we must avoid using
13448 ; MATCH_OPERAND for that argument. That way the register rename
13449 ; optimization will not try to rename this register.
13450 ; Each pattern is repeated for each possible register number used in
13451 ; various ABIs (r11, r1, and for some functions r12)
13453 (define_insn "*save_gpregs_<mode>_r11"
13454 [(match_parallel 0 "any_parallel_operand"
13455 [(clobber (reg:P 65))
13456 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13457 (use (reg:P 11))
13458 (set (match_operand:P 2 "memory_operand" "=m")
13459 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13460 ""
13461 "bl %1"
13462 [(set_attr "type" "branch")
13463 (set_attr "length" "4")])
13465 (define_insn "*save_gpregs_<mode>_r12"
13466 [(match_parallel 0 "any_parallel_operand"
13467 [(clobber (reg:P 65))
13468 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13469 (use (reg:P 12))
13470 (set (match_operand:P 2 "memory_operand" "=m")
13471 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13472 ""
13473 "bl %1"
13474 [(set_attr "type" "branch")
13475 (set_attr "length" "4")])
13477 (define_insn "*save_gpregs_<mode>_r1"
13478 [(match_parallel 0 "any_parallel_operand"
13479 [(clobber (reg:P 65))
13480 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13481 (use (reg:P 1))
13482 (set (match_operand:P 2 "memory_operand" "=m")
13483 (match_operand:P 3 "gpc_reg_operand" "r"))])]
13484 ""
13485 "bl %1"
13486 [(set_attr "type" "branch")
13487 (set_attr "length" "4")])
13489 (define_insn "*save_fpregs_<mode>_r11"
13490 [(match_parallel 0 "any_parallel_operand"
13491 [(clobber (reg:P 65))
13492 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13493 (use (reg:P 11))
13494 (set (match_operand:DF 2 "memory_operand" "=m")
13495 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13496 ""
13497 "bl %1"
13498 [(set_attr "type" "branch")
13499 (set_attr "length" "4")])
13501 (define_insn "*save_fpregs_<mode>_r12"
13502 [(match_parallel 0 "any_parallel_operand"
13503 [(clobber (reg:P 65))
13504 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13505 (use (reg:P 12))
13506 (set (match_operand:DF 2 "memory_operand" "=m")
13507 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13508 ""
13509 "bl %1"
13510 [(set_attr "type" "branch")
13511 (set_attr "length" "4")])
13513 (define_insn "*save_fpregs_<mode>_r1"
13514 [(match_parallel 0 "any_parallel_operand"
13515 [(clobber (reg:P 65))
13516 (use (match_operand:P 1 "symbol_ref_operand" "s"))
13517 (use (reg:P 1))
13518 (set (match_operand:DF 2 "memory_operand" "=m")
13519 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
13520 ""
13521 "bl %1"
13522 [(set_attr "type" "branch")
13523 (set_attr "length" "4")])
13525 ; This is to explain that changes to the stack pointer should
13526 ; not be moved over loads from or stores to stack memory.
13527 (define_insn "stack_tie"
13528 [(match_parallel 0 "tie_operand"
13529 [(set (mem:BLK (reg 1)) (const_int 0))])]
13530 ""
13531 ""
13532 [(set_attr "length" "0")])
13534 (define_expand "epilogue"
13535 [(use (const_int 0))]
13536 ""
13537 {
13538 if (!TARGET_SCHED_PROLOG)
13539 emit_insn (gen_blockage ());
13540 rs6000_emit_epilogue (FALSE);
13541 DONE;
13542 })
13544 ; On some processors, doing the mtcrf one CC register at a time is
13545 ; faster (like on the 604e). On others, doing them all at once is
13546 ; faster; for instance, on the 601 and 750.
13548 (define_expand "movsi_to_cr_one"
13549 [(set (match_operand:CC 0 "cc_reg_operand" "")
13550 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
13551 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
13552 ""
13553 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13555 (define_insn "*movsi_to_cr"
13556 [(match_parallel 0 "mtcrf_operation"
13557 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13558 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13559 (match_operand 3 "immediate_operand" "n")]
13560 UNSPEC_MOVESI_TO_CR))])]
13561 ""
13562 "*
13563 {
13564 int mask = 0;
13565 int i;
13566 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13567 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13568 operands[4] = GEN_INT (mask);
13569 return \"mtcrf %4,%2\";
13570 }"
13571 [(set_attr "type" "mtcr")])
13573 (define_insn "*mtcrfsi"
13574 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13575 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13576 (match_operand 2 "immediate_operand" "n")]
13577 UNSPEC_MOVESI_TO_CR))]
13578 "GET_CODE (operands[0]) == REG
13579 && CR_REGNO_P (REGNO (operands[0]))
13580 && GET_CODE (operands[2]) == CONST_INT
13581 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13582 "mtcrf %R0,%1"
13583 [(set_attr "type" "mtcr")])
13585 ; The load-multiple instructions have similar properties.
13586 ; Note that "load_multiple" is a name known to the machine-independent
13587 ; code that actually corresponds to the PowerPC load-string.
13589 (define_insn "*lmw"
13590 [(match_parallel 0 "lmw_operation"
13591 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13592 (match_operand:SI 2 "memory_operand" "m"))])]
13593 "TARGET_MULTIPLE"
13594 "lmw %1,%2"
13595 [(set_attr "type" "load_ux")
13596 (set_attr "cell_micro" "always")])
13598 (define_insn "*return_internal_<mode>"
13599 [(simple_return)
13600 (use (match_operand:P 0 "register_operand" "lc"))]
13601 ""
13602 "b%T0"
13603 [(set_attr "type" "jmpreg")])
13605 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13606 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
13608 ; The following comment applies to:
13609 ; save_gpregs_*
13610 ; save_fpregs_*
13611 ; restore_gpregs*
13612 ; return_and_restore_gpregs*
13613 ; return_and_restore_fpregs*
13614 ; return_and_restore_fpregs_aix*
13615 ;
13616 ; The out-of-line save / restore functions expects one input argument.
13617 ; Since those are not standard call_insn's, we must avoid using
13618 ; MATCH_OPERAND for that argument. That way the register rename
13619 ; optimization will not try to rename this register.
13620 ; Each pattern is repeated for each possible register number used in
13621 ; various ABIs (r11, r1, and for some functions r12)
13623 (define_insn "*restore_gpregs_<mode>_r11"
13624 [(match_parallel 0 "any_parallel_operand"
13625 [(clobber (match_operand:P 1 "register_operand" "=l"))
13626 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13627 (use (reg:P 11))
13628 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13629 (match_operand:P 4 "memory_operand" "m"))])]
13630 ""
13631 "bl %2"
13632 [(set_attr "type" "branch")
13633 (set_attr "length" "4")])
13635 (define_insn "*restore_gpregs_<mode>_r12"
13636 [(match_parallel 0 "any_parallel_operand"
13637 [(clobber (match_operand:P 1 "register_operand" "=l"))
13638 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13639 (use (reg:P 12))
13640 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13641 (match_operand:P 4 "memory_operand" "m"))])]
13642 ""
13643 "bl %2"
13644 [(set_attr "type" "branch")
13645 (set_attr "length" "4")])
13647 (define_insn "*restore_gpregs_<mode>_r1"
13648 [(match_parallel 0 "any_parallel_operand"
13649 [(clobber (match_operand:P 1 "register_operand" "=l"))
13650 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13651 (use (reg:P 1))
13652 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13653 (match_operand:P 4 "memory_operand" "m"))])]
13654 ""
13655 "bl %2"
13656 [(set_attr "type" "branch")
13657 (set_attr "length" "4")])
13659 (define_insn "*return_and_restore_gpregs_<mode>_r11"
13660 [(match_parallel 0 "any_parallel_operand"
13661 [(return)
13662 (clobber (match_operand:P 1 "register_operand" "=l"))
13663 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13664 (use (reg:P 11))
13665 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13666 (match_operand:P 4 "memory_operand" "m"))])]
13667 ""
13668 "b %2"
13669 [(set_attr "type" "branch")
13670 (set_attr "length" "4")])
13672 (define_insn "*return_and_restore_gpregs_<mode>_r12"
13673 [(match_parallel 0 "any_parallel_operand"
13674 [(return)
13675 (clobber (match_operand:P 1 "register_operand" "=l"))
13676 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13677 (use (reg:P 12))
13678 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13679 (match_operand:P 4 "memory_operand" "m"))])]
13680 ""
13681 "b %2"
13682 [(set_attr "type" "branch")
13683 (set_attr "length" "4")])
13685 (define_insn "*return_and_restore_gpregs_<mode>_r1"
13686 [(match_parallel 0 "any_parallel_operand"
13687 [(return)
13688 (clobber (match_operand:P 1 "register_operand" "=l"))
13689 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13690 (use (reg:P 1))
13691 (set (match_operand:P 3 "gpc_reg_operand" "=r")
13692 (match_operand:P 4 "memory_operand" "m"))])]
13693 ""
13694 "b %2"
13695 [(set_attr "type" "branch")
13696 (set_attr "length" "4")])
13698 (define_insn "*return_and_restore_fpregs_<mode>_r11"
13699 [(match_parallel 0 "any_parallel_operand"
13700 [(return)
13701 (clobber (match_operand:P 1 "register_operand" "=l"))
13702 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13703 (use (reg:P 11))
13704 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13705 (match_operand:DF 4 "memory_operand" "m"))])]
13706 ""
13707 "b %2"
13708 [(set_attr "type" "branch")
13709 (set_attr "length" "4")])
13711 (define_insn "*return_and_restore_fpregs_<mode>_r12"
13712 [(match_parallel 0 "any_parallel_operand"
13713 [(return)
13714 (clobber (match_operand:P 1 "register_operand" "=l"))
13715 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13716 (use (reg:P 12))
13717 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13718 (match_operand:DF 4 "memory_operand" "m"))])]
13719 ""
13720 "b %2"
13721 [(set_attr "type" "branch")
13722 (set_attr "length" "4")])
13724 (define_insn "*return_and_restore_fpregs_<mode>_r1"
13725 [(match_parallel 0 "any_parallel_operand"
13726 [(return)
13727 (clobber (match_operand:P 1 "register_operand" "=l"))
13728 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13729 (use (reg:P 1))
13730 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13731 (match_operand:DF 4 "memory_operand" "m"))])]
13732 ""
13733 "b %2"
13734 [(set_attr "type" "branch")
13735 (set_attr "length" "4")])
13737 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
13738 [(match_parallel 0 "any_parallel_operand"
13739 [(return)
13740 (use (match_operand:P 1 "register_operand" "l"))
13741 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13742 (use (reg:P 11))
13743 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13744 (match_operand:DF 4 "memory_operand" "m"))])]
13745 ""
13746 "b %2"
13747 [(set_attr "type" "branch")
13748 (set_attr "length" "4")])
13750 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
13751 [(match_parallel 0 "any_parallel_operand"
13752 [(return)
13753 (use (match_operand:P 1 "register_operand" "l"))
13754 (use (match_operand:P 2 "symbol_ref_operand" "s"))
13755 (use (reg:P 1))
13756 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
13757 (match_operand:DF 4 "memory_operand" "m"))])]
13758 ""
13759 "b %2"
13760 [(set_attr "type" "branch")
13761 (set_attr "length" "4")])
13763 ; This is used in compiling the unwind routines.
13764 (define_expand "eh_return"
13765 [(use (match_operand 0 "general_operand" ""))]
13766 ""
13767 "
13768 {
13769 if (TARGET_32BIT)
13770 emit_insn (gen_eh_set_lr_si (operands[0]));
13771 else
13772 emit_insn (gen_eh_set_lr_di (operands[0]));
13773 DONE;
13774 }")
13776 ; We can't expand this before we know where the link register is stored.
13777 (define_insn "eh_set_lr_<mode>"
13778 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
13779 UNSPECV_EH_RR)
13780 (clobber (match_scratch:P 1 "=&b"))]
13781 ""
13782 "#")
13784 (define_split
13785 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
13786 (clobber (match_scratch 1 ""))]
13787 "reload_completed"
13788 [(const_int 0)]
13789 "
13790 {
13791 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
13792 DONE;
13793 }")
13795 (define_insn "prefetch"
13796 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
13797 (match_operand:SI 1 "const_int_operand" "n")
13798 (match_operand:SI 2 "const_int_operand" "n"))]
13799 ""
13800 "*
13801 {
13802 if (GET_CODE (operands[0]) == REG)
13803 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
13804 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
13805 }"
13806 [(set_attr "type" "load")])
13807 \f
13808 (define_insn "bpermd_<mode>"
13809 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13810 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
13811 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
13812 "TARGET_POPCNTD"
13813 "bpermd %0,%1,%2"
13814 [(set_attr "type" "integer")])
13816 \f
13817 ;; Builtin fma support. Handle
13818 ;; Note that the conditions for expansion are in the FMA_F iterator.
13820 (define_expand "fma<mode>4"
13821 [(set (match_operand:FMA_F 0 "register_operand" "")
13822 (fma:FMA_F
13823 (match_operand:FMA_F 1 "register_operand" "")
13824 (match_operand:FMA_F 2 "register_operand" "")
13825 (match_operand:FMA_F 3 "register_operand" "")))]
13826 ""
13827 "")
13829 ; Altivec only has fma and nfms.
13830 (define_expand "fms<mode>4"
13831 [(set (match_operand:FMA_F 0 "register_operand" "")
13832 (fma:FMA_F
13833 (match_operand:FMA_F 1 "register_operand" "")
13834 (match_operand:FMA_F 2 "register_operand" "")
13835 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
13836 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13837 "")
13839 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
13840 (define_expand "fnma<mode>4"
13841 [(set (match_operand:FMA_F 0 "register_operand" "")
13842 (neg:FMA_F
13843 (fma:FMA_F
13844 (match_operand:FMA_F 1 "register_operand" "")
13845 (match_operand:FMA_F 2 "register_operand" "")
13846 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13847 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
13848 "")
13850 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
13851 (define_expand "fnms<mode>4"
13852 [(set (match_operand:FMA_F 0 "register_operand" "")
13853 (neg:FMA_F
13854 (fma:FMA_F
13855 (match_operand:FMA_F 1 "register_operand" "")
13856 (match_operand:FMA_F 2 "register_operand" "")
13857 (match_operand:FMA_F 3 "register_operand" ""))))]
13858 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13859 "")
13861 ; Not an official optab name, but used from builtins.
13862 (define_expand "nfma<mode>4"
13863 [(set (match_operand:FMA_F 0 "register_operand" "")
13864 (neg:FMA_F
13865 (fma:FMA_F
13866 (match_operand:FMA_F 1 "register_operand" "")
13867 (match_operand:FMA_F 2 "register_operand" "")
13868 (match_operand:FMA_F 3 "register_operand" ""))))]
13869 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
13870 "")
13872 ; Not an official optab name, but used from builtins.
13873 (define_expand "nfms<mode>4"
13874 [(set (match_operand:FMA_F 0 "register_operand" "")
13875 (neg:FMA_F
13876 (fma:FMA_F
13877 (match_operand:FMA_F 1 "register_operand" "")
13878 (match_operand:FMA_F 2 "register_operand" "")
13879 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13880 ""
13881 "")
13883 (define_expand "rs6000_get_timebase"
13884 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13885 ""
13886 {
13887 if (TARGET_POWERPC64)
13888 emit_insn (gen_rs6000_mftb_di (operands[0]));
13889 else
13890 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13891 DONE;
13892 })
13894 (define_insn "rs6000_get_timebase_ppc32"
13895 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13896 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13897 (clobber (match_scratch:SI 1 "=r"))
13898 (clobber (match_scratch:CC 2 "=y"))]
13899 "!TARGET_POWERPC64"
13900 {
13901 if (WORDS_BIG_ENDIAN)
13902 if (TARGET_MFCRF)
13903 {
13904 return "mfspr %0,269\;"
13905 "mfspr %L0,268\;"
13906 "mfspr %1,269\;"
13907 "cmpw %2,%0,%1\;"
13908 "bne- %2,$-16";
13909 }
13910 else
13911 {
13912 return "mftbu %0\;"
13913 "mftb %L0\;"
13914 "mftbu %1\;"
13915 "cmpw %2,%0,%1\;"
13916 "bne- %2,$-16";
13917 }
13918 else
13919 if (TARGET_MFCRF)
13920 {
13921 return "mfspr %L0,269\;"
13922 "mfspr %0,268\;"
13923 "mfspr %1,269\;"
13924 "cmpw %2,%L0,%1\;"
13925 "bne- %2,$-16";
13926 }
13927 else
13928 {
13929 return "mftbu %L0\;"
13930 "mftb %0\;"
13931 "mftbu %1\;"
13932 "cmpw %2,%L0,%1\;"
13933 "bne- %2,$-16";
13934 }
13935 })
13937 (define_insn "rs6000_mftb_<mode>"
13938 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13939 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
13940 ""
13941 {
13942 if (TARGET_MFCRF)
13943 return "mfspr %0,268";
13944 else
13945 return "mftb %0";
13946 })
13948 \f
13950 (include "sync.md")
13951 (include "vector.md")
13952 (include "vsx.md")
13953 (include "altivec.md")
13954 (include "spe.md")
13955 (include "dfp.md")
13956 (include "paired.md")