| blob | 5d212dd81808925c397e654cb8b6236c89a31b36 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2016 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 (FIRST_SPE_HIGH_REGNO 117)
60 (LAST_SPE_HIGH_REGNO 148)
61 ])
63 ;;
64 ;; UNSPEC usage
65 ;;
67 (define_c_enum "unspec"
68 [UNSPEC_FRSP ; frsp for POWER machines
69 UNSPEC_PROBE_STACK ; probe stack memory reference
70 UNSPEC_TOCPTR ; address of a word pointing to the TOC
71 UNSPEC_TOC ; address of the TOC (more-or-less)
72 UNSPEC_TOCSLOT ; offset from r1 of toc pointer save slot
73 UNSPEC_MOVSI_GOT
74 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
75 UNSPEC_FCTIWZ
76 UNSPEC_FRIM
77 UNSPEC_FRIN
78 UNSPEC_FRIP
79 UNSPEC_FRIZ
80 UNSPEC_XSRDPI
81 UNSPEC_LD_MPIC ; load_macho_picbase
82 UNSPEC_RELD_MPIC ; re-load_macho_picbase
83 UNSPEC_MPIC_CORRECT ; macho_correct_pic
84 UNSPEC_TLSGD
85 UNSPEC_TLSLD
86 UNSPEC_MOVESI_FROM_CR
87 UNSPEC_MOVESI_TO_CR
88 UNSPEC_TLSDTPREL
89 UNSPEC_TLSDTPRELHA
90 UNSPEC_TLSDTPRELLO
91 UNSPEC_TLSGOTDTPREL
92 UNSPEC_TLSTPREL
93 UNSPEC_TLSTPRELHA
94 UNSPEC_TLSTPRELLO
95 UNSPEC_TLSGOTTPREL
96 UNSPEC_TLSTLS
97 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
98 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
99 UNSPEC_STFIWX
100 UNSPEC_POPCNTB
101 UNSPEC_FRES
102 UNSPEC_SP_SET
103 UNSPEC_SP_TEST
104 UNSPEC_SYNC
105 UNSPEC_LWSYNC
106 UNSPEC_SYNC_OP
107 UNSPEC_ATOMIC
108 UNSPEC_CMPXCHG
109 UNSPEC_XCHG
110 UNSPEC_AND
111 UNSPEC_DLMZB
112 UNSPEC_DLMZB_CR
113 UNSPEC_DLMZB_STRLEN
114 UNSPEC_RSQRT
115 UNSPEC_TOCREL
116 UNSPEC_MACHOPIC_OFFSET
117 UNSPEC_BPERM
118 UNSPEC_COPYSIGN
119 UNSPEC_PARITY
120 UNSPEC_FCTIW
121 UNSPEC_FCTID
122 UNSPEC_LFIWAX
123 UNSPEC_LFIWZX
124 UNSPEC_FCTIWUZ
125 UNSPEC_NOP
126 UNSPEC_GRP_END_NOP
127 UNSPEC_P8V_FMRGOW
128 UNSPEC_P8V_MTVSRWZ
129 UNSPEC_P8V_RELOAD_FROM_GPR
130 UNSPEC_P8V_MTVSRD
131 UNSPEC_P8V_XXPERMDI
132 UNSPEC_P8V_RELOAD_FROM_VSX
133 UNSPEC_ADDG6S
134 UNSPEC_CDTBCD
135 UNSPEC_CBCDTD
136 UNSPEC_DIVE
137 UNSPEC_DIVEO
138 UNSPEC_DIVEU
139 UNSPEC_DIVEUO
140 UNSPEC_UNPACK_128BIT
141 UNSPEC_PACK_128BIT
142 UNSPEC_LSQ
143 UNSPEC_FUSION_GPR
144 UNSPEC_STACK_CHECK
145 UNSPEC_FUSION_P9
146 UNSPEC_FUSION_ADDIS
147 UNSPEC_ROUND_TO_ODD
148 UNSPEC_IEEE128_MOVE
149 UNSPEC_IEEE128_CONVERT
150 UNSPEC_SIGNBIT
151 UNSPEC_DOLOOP
152 ])
154 ;;
155 ;; UNSPEC_VOLATILE usage
156 ;;
158 (define_c_enum "unspecv"
159 [UNSPECV_BLOCK
160 UNSPECV_LL ; load-locked
161 UNSPECV_SC ; store-conditional
162 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
163 UNSPECV_EH_RR ; eh_reg_restore
164 UNSPECV_ISYNC ; isync instruction
165 UNSPECV_MFTB ; move from time base
166 UNSPECV_NLGR ; non-local goto receiver
167 UNSPECV_MFFS ; Move from FPSCR
168 UNSPECV_MTFSF ; Move to FPSCR Fields
169 UNSPECV_SPLIT_STACK_RETURN ; A camouflaged return
170 ])
172 \f
173 ;; Define an insn type attribute. This is used in function unit delay
174 ;; computations.
175 (define_attr "type"
176 "integer,two,three,
177 add,logical,shift,insert,
178 mul,halfmul,div,
179 exts,cntlz,popcnt,isel,
180 load,store,fpload,fpstore,vecload,vecstore,
181 cmp,
182 branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
183 cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
184 fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
185 brinc,
186 vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
187 vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto,
188 veclogical,veccmpfx,vecexts,vecmove,
189 htm,htmsimple,dfp"
190 (const_string "integer"))
192 ;; What data size does this instruction work on?
193 ;; This is used for insert, mul and others as necessary.
194 (define_attr "size" "8,16,32,64,128" (const_string "32"))
196 ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
197 ;; This is used for add, logical, shift, exts, mul.
198 (define_attr "dot" "no,yes" (const_string "no"))
200 ;; Does this instruction sign-extend its result?
201 ;; This is used for load insns.
202 (define_attr "sign_extend" "no,yes" (const_string "no"))
204 ;; Does this instruction use indexed (that is, reg+reg) addressing?
205 ;; This is used for load and store insns. If operand 0 or 1 is a MEM
206 ;; it is automatically set based on that. If a load or store instruction
207 ;; has fewer than two operands it needs to set this attribute manually
208 ;; or the compiler will crash.
209 (define_attr "indexed" "no,yes"
210 (if_then_else (ior (match_operand 0 "indexed_address_mem")
211 (match_operand 1 "indexed_address_mem"))
212 (const_string "yes")
213 (const_string "no")))
215 ;; Does this instruction use update addressing?
216 ;; This is used for load and store insns. See the comments for "indexed".
217 (define_attr "update" "no,yes"
218 (if_then_else (ior (match_operand 0 "update_address_mem")
219 (match_operand 1 "update_address_mem"))
220 (const_string "yes")
221 (const_string "no")))
223 ;; Is this instruction using operands[2] as shift amount, and can that be a
224 ;; register?
225 ;; This is used for shift insns.
226 (define_attr "maybe_var_shift" "no,yes" (const_string "no"))
228 ;; Is this instruction using a shift amount from a register?
229 ;; This is used for shift insns.
230 (define_attr "var_shift" "no,yes"
231 (if_then_else (and (eq_attr "type" "shift")
232 (eq_attr "maybe_var_shift" "yes"))
233 (if_then_else (match_operand 2 "gpc_reg_operand")
234 (const_string "yes")
235 (const_string "no"))
236 (const_string "no")))
238 ;; Is copying of this instruction disallowed?
239 (define_attr "cannot_copy" "no,yes" (const_string "no"))
241 ;; Define floating point instruction sub-types for use with Xfpu.md
242 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
244 ;; Length (in bytes).
245 ; '(pc)' in the following doesn't include the instruction itself; it is
246 ; calculated as if the instruction had zero size.
247 (define_attr "length" ""
248 (if_then_else (eq_attr "type" "branch")
249 (if_then_else (and (ge (minus (match_dup 0) (pc))
250 (const_int -32768))
251 (lt (minus (match_dup 0) (pc))
252 (const_int 32764)))
253 (const_int 4)
254 (const_int 8))
255 (const_int 4)))
257 ;; Processor type -- this attribute must exactly match the processor_type
258 ;; enumeration in rs6000-opts.h.
259 (define_attr "cpu"
260 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
261 ppc750,ppc7400,ppc7450,
262 ppc403,ppc405,ppc440,ppc476,
263 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
264 power4,power5,power6,power7,power8,power9,
265 rs64a,mpccore,cell,ppca2,titan"
266 (const (symbol_ref "rs6000_cpu_attr")))
269 ;; If this instruction is microcoded on the CELL processor
270 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
271 (define_attr "cell_micro" "not,conditional,always"
272 (if_then_else (ior (and (eq_attr "type" "shift,exts,mul")
273 (eq_attr "dot" "yes"))
274 (and (eq_attr "type" "load")
275 (eq_attr "sign_extend" "yes"))
276 (and (eq_attr "type" "shift")
277 (eq_attr "var_shift" "yes")))
278 (const_string "always")
279 (const_string "not")))
281 (automata_option "ndfa")
283 (include "rs64.md")
284 (include "mpc.md")
285 (include "40x.md")
286 (include "440.md")
287 (include "476.md")
288 (include "601.md")
289 (include "603.md")
290 (include "6xx.md")
291 (include "7xx.md")
292 (include "7450.md")
293 (include "8540.md")
294 (include "e300c2c3.md")
295 (include "e500mc.md")
296 (include "e500mc64.md")
297 (include "e5500.md")
298 (include "e6500.md")
299 (include "power4.md")
300 (include "power5.md")
301 (include "power6.md")
302 (include "power7.md")
303 (include "power8.md")
304 (include "power9.md")
305 (include "cell.md")
306 (include "xfpu.md")
307 (include "a2.md")
308 (include "titan.md")
310 (include "predicates.md")
311 (include "constraints.md")
313 (include "darwin.md")
315 \f
316 ;; Mode iterators
318 ; This mode iterator allows :GPR to be used to indicate the allowable size
319 ; of whole values in GPRs.
320 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
322 ; Any supported integer mode.
323 (define_mode_iterator INT [QI HI SI DI TI PTI])
325 ; Any supported integer mode that fits in one register.
326 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
328 ; Everything we can extend QImode to.
329 (define_mode_iterator EXTQI [SI (DI "TARGET_POWERPC64")])
331 ; Everything we can extend HImode to.
332 (define_mode_iterator EXTHI [SI (DI "TARGET_POWERPC64")])
334 ; Everything we can extend SImode to.
335 (define_mode_iterator EXTSI [(DI "TARGET_POWERPC64")])
337 ; QImode or HImode for small atomic ops
338 (define_mode_iterator QHI [QI HI])
340 ; QImode, HImode, SImode for fused ops only for GPR loads
341 (define_mode_iterator QHSI [QI HI SI])
343 ; HImode or SImode for sign extended fusion ops
344 (define_mode_iterator HSI [HI SI])
346 ; SImode or DImode, even if DImode doesn't fit in GPRs.
347 (define_mode_iterator SDI [SI DI])
349 ; Types that can be fused with an ADDIS instruction to load or store a GPR
350 ; register that has reg+offset addressing.
351 (define_mode_iterator GPR_FUSION [QI
352 HI
353 SI
354 (DI "TARGET_POWERPC64")
355 SF
356 (DF "TARGET_POWERPC64")])
358 ; Types that can be fused with an ADDIS instruction to load or store a FPR
359 ; register that has reg+offset addressing.
360 (define_mode_iterator FPR_FUSION [DI SF DF])
362 ; The size of a pointer. Also, the size of the value that a record-condition
363 ; (one with a '.') will compare; and the size used for arithmetic carries.
364 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
366 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
367 ; PTImode is GPR only)
368 (define_mode_iterator TI2 [TI PTI])
370 ; Any hardware-supported floating-point mode
371 (define_mode_iterator FP [
372 (SF "TARGET_HARD_FLOAT
373 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
374 (DF "TARGET_HARD_FLOAT
375 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
376 (TF "TARGET_HARD_FLOAT
377 && (TARGET_FPRS || TARGET_E500_DOUBLE)
378 && TARGET_LONG_DOUBLE_128")
379 (IF "TARGET_FLOAT128")
380 (KF "TARGET_FLOAT128")
381 (DD "TARGET_DFP")
382 (TD "TARGET_DFP")])
384 ; Any fma capable floating-point mode.
385 (define_mode_iterator FMA_F [
386 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
387 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
388 || VECTOR_UNIT_VSX_P (DFmode)")
389 (V2SF "TARGET_PAIRED_FLOAT")
390 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
391 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
392 (KF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (KFmode)")
393 (TF "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (TFmode)")
394 ])
396 ; Floating point move iterators to combine binary and decimal moves
397 (define_mode_iterator FMOVE32 [SF SD])
398 (define_mode_iterator FMOVE64 [DF DD])
399 (define_mode_iterator FMOVE64X [DI DF DD])
400 (define_mode_iterator FMOVE128 [(TF "TARGET_LONG_DOUBLE_128")
401 (IF "TARGET_LONG_DOUBLE_128")
402 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
404 (define_mode_iterator FMOVE128_FPR [(TF "FLOAT128_2REG_P (TFmode)")
405 (IF "FLOAT128_2REG_P (IFmode)")
406 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
408 ; Iterators for 128 bit types for direct move
409 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
410 (V16QI "")
411 (V8HI "")
412 (V4SI "")
413 (V4SF "")
414 (V2DI "")
415 (V2DF "")
416 (V1TI "")
417 (KF "FLOAT128_VECTOR_P (KFmode)")
418 (TF "FLOAT128_VECTOR_P (TFmode)")])
420 ; Iterator for 128-bit VSX types for pack/unpack
421 (define_mode_iterator FMOVE128_VSX [V1TI KF])
423 ; Whether a floating point move is ok, don't allow SD without hardware FP
424 (define_mode_attr fmove_ok [(SF "")
425 (DF "")
426 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
427 (DD "")])
429 ; Convert REAL_VALUE to the appropriate bits
430 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
431 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
432 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
433 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
435 ; Whether 0.0 has an all-zero bit pattern
436 (define_mode_attr zero_fp [(SF "j")
437 (DF "j")
438 (TF "j")
439 (IF "j")
440 (KF "j")
441 (SD "wn")
442 (DD "wn")
443 (TD "wn")])
445 ; Definitions for load to 32-bit fpr register
446 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
447 (define_mode_attr f32_lr2 [(SF "wb") (SD "wn")])
448 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
449 (define_mode_attr f32_lm2 [(SF "o") (SD "wn")])
450 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
451 (define_mode_attr f32_li2 [(SF "lxssp %0,%1") (SD "lfiwzx %0,%y1")])
452 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
454 ; Definitions for store from 32-bit fpr register
455 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
456 (define_mode_attr f32_sr2 [(SF "wb") (SD "wn")])
457 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
458 (define_mode_attr f32_sm2 [(SF "o") (SD "wn")])
459 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
460 (define_mode_attr f32_si2 [(SF "stxssp %1,%0") (SD "stfiwx %1,%y0")])
461 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
463 ; Definitions for 32-bit fpr direct move
464 ; At present, the decimal modes are not allowed in the traditional altivec
465 ; registers, so restrict the constraints to just the traditional FPRs.
466 (define_mode_attr f32_dm [(SF "wn") (SD "wh")])
468 ; Definitions for 32-bit VSX
469 (define_mode_attr f32_vsx [(SF "ww") (SD "wn")])
471 ; Definitions for 32-bit use of altivec registers
472 (define_mode_attr f32_av [(SF "wu") (SD "wn")])
474 ; Definitions for 64-bit VSX
475 (define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
477 ; Definitions for 64-bit direct move
478 (define_mode_attr f64_dm [(DF "wk") (DD "wh")])
480 ; Definitions for 64-bit use of altivec registers
481 (define_mode_attr f64_av [(DF "wv") (DD "wn")])
483 ; Definitions for 64-bit access to ISA 3.0 (power9) vector
484 (define_mode_attr f64_p9 [(DF "wb") (DD "wn")])
486 ; These modes do not fit in integer registers in 32-bit mode.
487 ; but on e500v2, the gpr are 64 bit registers
488 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
490 ; Iterator for reciprocal estimate instructions
491 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
493 ; Iterator for just SF/DF
494 (define_mode_iterator SFDF [SF DF])
496 ; Like SFDF, but a different name to match conditional move where the
497 ; comparison operands may be a different mode than the input operands.
498 (define_mode_iterator SFDF2 [SF DF])
500 ; Iterator for 128-bit floating point that uses the IBM double-double format
501 (define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)")
502 (TF "FLOAT128_IBM_P (TFmode)")])
504 ; Iterator for 128-bit floating point that uses IEEE 128-bit float
505 (define_mode_iterator IEEE128 [(KF "FLOAT128_IEEE_P (KFmode)")
506 (TF "FLOAT128_IEEE_P (TFmode)")])
508 ; Iterator for 128-bit floating point
509 (define_mode_iterator FLOAT128 [(KF "TARGET_FLOAT128")
510 (IF "TARGET_FLOAT128")
511 (TF "TARGET_LONG_DOUBLE_128")])
513 ; Iterator for signbit on 64-bit machines with direct move
514 (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)")
515 (TF "FLOAT128_VECTOR_P (TFmode)")])
517 (define_mode_attr Fsignbit [(KF "wa")
518 (TF "wa")])
520 ; Iterator for ISA 3.0 supported floating point types
521 (define_mode_iterator FP_ISA3 [SF
522 DF
523 (KF "FLOAT128_IEEE_P (KFmode)")
524 (TF "FLOAT128_IEEE_P (TFmode)")])
526 ; SF/DF suffix for traditional floating instructions
527 (define_mode_attr Ftrad [(SF "s") (DF "")])
529 ; SF/DF suffix for VSX instructions
530 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
532 ; SF/DF constraint for arithmetic on traditional floating point registers
533 (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
535 ; SF/DF constraint for arithmetic on VSX registers using instructions added in
536 ; ISA 2.06 (power7). This includes instructions that normally target DF mode,
537 ; but are used on SFmode, since internally SFmode values are kept in the DFmode
538 ; format.
539 (define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")])
541 ; SF/DF constraint for arithmetic on VSX registers. This is intended to be
542 ; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
543 ; instructions added in ISA 2.07 (power8)
544 (define_mode_attr Fv2 [(SF "wy") (DF "ws") (DI "wi")])
546 ; SF/DF constraint for arithmetic on altivec registers
547 (define_mode_attr Fa [(SF "wu") (DF "wv")])
549 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
550 (define_mode_attr Fs [(SF "s") (DF "d")])
552 ; FRE/FRES support
553 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
554 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
556 ; Conditional returns.
557 (define_code_iterator any_return [return simple_return])
558 (define_code_attr return_pred [(return "direct_return ()")
559 (simple_return "1")])
560 (define_code_attr return_str [(return "") (simple_return "simple_")])
562 ; Logical operators.
563 (define_code_iterator iorxor [ior xor])
565 ; Signed/unsigned variants of ops.
566 (define_code_iterator any_extend [sign_extend zero_extend])
567 (define_code_iterator any_fix [fix unsigned_fix])
568 (define_code_iterator any_float [float unsigned_float])
570 (define_code_attr u [(sign_extend "")
571 (zero_extend "u")])
573 (define_code_attr su [(sign_extend "s")
574 (zero_extend "u")
575 (fix "s")
576 (unsigned_fix "s")
577 (float "s")
578 (unsigned_float "u")])
580 (define_code_attr az [(sign_extend "a")
581 (zero_extend "z")
582 (fix "a")
583 (unsigned_fix "z")
584 (float "a")
585 (unsigned_float "z")])
587 (define_code_attr uns [(fix "")
588 (unsigned_fix "uns")
589 (float "")
590 (unsigned_float "uns")])
592 ; Various instructions that come in SI and DI forms.
593 ; A generic w/d attribute, for things like cmpw/cmpd.
594 (define_mode_attr wd [(QI "b")
595 (HI "h")
596 (SI "w")
597 (DI "d")
598 (V16QI "b")
599 (V8HI "h")
600 (V4SI "w")
601 (V2DI "d")
602 (V1TI "q")
603 (TI "q")])
605 ;; How many bits in this mode?
606 (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
608 ; DImode bits
609 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
611 ;; ISEL/ISEL64 target selection
612 (define_mode_attr sel [(SI "") (DI "64")])
614 ;; Bitmask for shift instructions
615 (define_mode_attr hH [(SI "h") (DI "H")])
617 ;; A mode twice the size of the given mode
618 (define_mode_attr dmode [(SI "di") (DI "ti")])
619 (define_mode_attr DMODE [(SI "DI") (DI "TI")])
621 ;; Suffix for reload patterns
622 (define_mode_attr ptrsize [(SI "32bit")
623 (DI "64bit")])
625 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
626 (DI "TARGET_64BIT")])
628 (define_mode_attr mptrsize [(SI "si")
629 (DI "di")])
631 (define_mode_attr ptrload [(SI "lwz")
632 (DI "ld")])
634 (define_mode_attr ptrm [(SI "m")
635 (DI "Y")])
637 (define_mode_attr rreg [(SF "f")
638 (DF "ws")
639 (TF "f")
640 (TD "f")
641 (V4SF "wf")
642 (V2DF "wd")])
644 (define_mode_attr rreg2 [(SF "f")
645 (DF "d")])
647 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
648 (DF "TARGET_FCFID")])
650 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
651 (DF "TARGET_E500_DOUBLE")])
653 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
654 (DF "TARGET_DOUBLE_FLOAT")])
656 ;; Mode iterator for logical operations on 128-bit types
657 (define_mode_iterator BOOL_128 [TI
658 PTI
659 (V16QI "TARGET_ALTIVEC")
660 (V8HI "TARGET_ALTIVEC")
661 (V4SI "TARGET_ALTIVEC")
662 (V4SF "TARGET_ALTIVEC")
663 (V2DI "TARGET_ALTIVEC")
664 (V2DF "TARGET_ALTIVEC")
665 (V1TI "TARGET_ALTIVEC")])
667 ;; For the GPRs we use 3 constraints for register outputs, two that are the
668 ;; same as the output register, and a third where the output register is an
669 ;; early clobber, so we don't have to deal with register overlaps. For the
670 ;; vector types, we prefer to use the vector registers. For TI mode, allow
671 ;; either.
673 ;; Mode attribute for boolean operation register constraints for output
674 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v")
675 (PTI "&r,r,r")
676 (V16QI "wa,v,&?r,?r,?r")
677 (V8HI "wa,v,&?r,?r,?r")
678 (V4SI "wa,v,&?r,?r,?r")
679 (V4SF "wa,v,&?r,?r,?r")
680 (V2DI "wa,v,&?r,?r,?r")
681 (V2DF "wa,v,&?r,?r,?r")
682 (V1TI "wa,v,&?r,?r,?r")])
684 ;; Mode attribute for boolean operation register constraints for operand1
685 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v")
686 (PTI "r,0,r")
687 (V16QI "wa,v,r,0,r")
688 (V8HI "wa,v,r,0,r")
689 (V4SI "wa,v,r,0,r")
690 (V4SF "wa,v,r,0,r")
691 (V2DI "wa,v,r,0,r")
692 (V2DF "wa,v,r,0,r")
693 (V1TI "wa,v,r,0,r")])
695 ;; Mode attribute for boolean operation register constraints for operand2
696 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v")
697 (PTI "r,r,0")
698 (V16QI "wa,v,r,r,0")
699 (V8HI "wa,v,r,r,0")
700 (V4SI "wa,v,r,r,0")
701 (V4SF "wa,v,r,r,0")
702 (V2DI "wa,v,r,r,0")
703 (V2DF "wa,v,r,r,0")
704 (V1TI "wa,v,r,r,0")])
706 ;; Mode attribute for boolean operation register constraints for operand1
707 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
708 ;; is used for operand1 or operand2
709 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v")
710 (PTI "r,0,0")
711 (V16QI "wa,v,r,0,0")
712 (V8HI "wa,v,r,0,0")
713 (V4SI "wa,v,r,0,0")
714 (V4SF "wa,v,r,0,0")
715 (V2DI "wa,v,r,0,0")
716 (V2DF "wa,v,r,0,0")
717 (V1TI "wa,v,r,0,0")])
719 ;; Reload iterator for creating the function to allocate a base register to
720 ;; supplement addressing modes.
721 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
722 SF SD SI DF DD DI TI PTI KF IF TF])
724 ;; Iterate over smin, smax
725 (define_code_iterator fp_minmax [smin smax])
727 (define_code_attr minmax [(smin "min")
728 (smax "max")])
730 (define_code_attr SMINMAX [(smin "SMIN")
731 (smax "SMAX")])
733 \f
734 ;; Start with fixed-point load and store insns. Here we put only the more
735 ;; complex forms. Basic data transfer is done later.
737 (define_insn "zero_extendqi<mode>2"
738 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
739 (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
740 ""
741 "@
742 lbz%U1%X1 %0,%1
743 rlwinm %0,%1,0,0xff"
744 [(set_attr "type" "load,shift")])
746 (define_insn_and_split "*zero_extendqi<mode>2_dot"
747 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
748 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
749 (const_int 0)))
750 (clobber (match_scratch:EXTQI 0 "=r,r"))]
751 "rs6000_gen_cell_microcode"
752 "@
753 andi. %0,%1,0xff
754 #"
755 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
756 [(set (match_dup 0)
757 (zero_extend:EXTQI (match_dup 1)))
758 (set (match_dup 2)
759 (compare:CC (match_dup 0)
760 (const_int 0)))]
761 ""
762 [(set_attr "type" "logical")
763 (set_attr "dot" "yes")
764 (set_attr "length" "4,8")])
766 (define_insn_and_split "*zero_extendqi<mode>2_dot2"
767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
769 (const_int 0)))
770 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
771 (zero_extend:EXTQI (match_dup 1)))]
772 "rs6000_gen_cell_microcode"
773 "@
774 andi. %0,%1,0xff
775 #"
776 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
777 [(set (match_dup 0)
778 (zero_extend:EXTQI (match_dup 1)))
779 (set (match_dup 2)
780 (compare:CC (match_dup 0)
781 (const_int 0)))]
782 ""
783 [(set_attr "type" "logical")
784 (set_attr "dot" "yes")
785 (set_attr "length" "4,8")])
788 (define_insn "zero_extendhi<mode>2"
789 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
790 (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
791 ""
792 "@
793 lhz%U1%X1 %0,%1
794 rlwinm %0,%1,0,0xffff"
795 [(set_attr "type" "load,shift")])
797 (define_insn_and_split "*zero_extendhi<mode>2_dot"
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
800 (const_int 0)))
801 (clobber (match_scratch:EXTHI 0 "=r,r"))]
802 "rs6000_gen_cell_microcode"
803 "@
804 andi. %0,%1,0xffff
805 #"
806 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
807 [(set (match_dup 0)
808 (zero_extend:EXTHI (match_dup 1)))
809 (set (match_dup 2)
810 (compare:CC (match_dup 0)
811 (const_int 0)))]
812 ""
813 [(set_attr "type" "logical")
814 (set_attr "dot" "yes")
815 (set_attr "length" "4,8")])
817 (define_insn_and_split "*zero_extendhi<mode>2_dot2"
818 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
819 (compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
820 (const_int 0)))
821 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
822 (zero_extend:EXTHI (match_dup 1)))]
823 "rs6000_gen_cell_microcode"
824 "@
825 andi. %0,%1,0xffff
826 #"
827 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
828 [(set (match_dup 0)
829 (zero_extend:EXTHI (match_dup 1)))
830 (set (match_dup 2)
831 (compare:CC (match_dup 0)
832 (const_int 0)))]
833 ""
834 [(set_attr "type" "logical")
835 (set_attr "dot" "yes")
836 (set_attr "length" "4,8")])
839 (define_insn "zero_extendsi<mode>2"
840 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu")
841 (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
842 ""
843 "@
844 lwz%U1%X1 %0,%1
845 rldicl %0,%1,0,32
846 mtvsrwz %x0,%1
847 lfiwzx %0,%y1
848 lxsiwzx %x0,%y1"
849 [(set_attr "type" "load,shift,mffgpr,fpload,fpload")])
851 (define_insn_and_split "*zero_extendsi<mode>2_dot"
852 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
853 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
854 (const_int 0)))
855 (clobber (match_scratch:EXTSI 0 "=r,r"))]
856 "rs6000_gen_cell_microcode"
857 "@
858 rldicl. %0,%1,0,32
859 #"
860 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
861 [(set (match_dup 0)
862 (zero_extend:DI (match_dup 1)))
863 (set (match_dup 2)
864 (compare:CC (match_dup 0)
865 (const_int 0)))]
866 ""
867 [(set_attr "type" "shift")
868 (set_attr "dot" "yes")
869 (set_attr "length" "4,8")])
871 (define_insn_and_split "*zero_extendsi<mode>2_dot2"
872 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
873 (compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
874 (const_int 0)))
875 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
876 (zero_extend:EXTSI (match_dup 1)))]
877 "rs6000_gen_cell_microcode"
878 "@
879 rldicl. %0,%1,0,32
880 #"
881 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
882 [(set (match_dup 0)
883 (zero_extend:EXTSI (match_dup 1)))
884 (set (match_dup 2)
885 (compare:CC (match_dup 0)
886 (const_int 0)))]
887 ""
888 [(set_attr "type" "shift")
889 (set_attr "dot" "yes")
890 (set_attr "length" "4,8")])
893 (define_insn "extendqi<mode>2"
894 [(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r")
895 (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r")))]
896 ""
897 "extsb %0,%1"
898 [(set_attr "type" "exts")])
900 (define_insn_and_split "*extendqi<mode>2_dot"
901 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
902 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
903 (const_int 0)))
904 (clobber (match_scratch:EXTQI 0 "=r,r"))]
905 "rs6000_gen_cell_microcode"
906 "@
907 extsb. %0,%1
908 #"
909 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
910 [(set (match_dup 0)
911 (sign_extend:EXTQI (match_dup 1)))
912 (set (match_dup 2)
913 (compare:CC (match_dup 0)
914 (const_int 0)))]
915 ""
916 [(set_attr "type" "exts")
917 (set_attr "dot" "yes")
918 (set_attr "length" "4,8")])
920 (define_insn_and_split "*extendqi<mode>2_dot2"
921 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
922 (compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
923 (const_int 0)))
924 (set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
925 (sign_extend:EXTQI (match_dup 1)))]
926 "rs6000_gen_cell_microcode"
927 "@
928 extsb. %0,%1
929 #"
930 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
931 [(set (match_dup 0)
932 (sign_extend:EXTQI (match_dup 1)))
933 (set (match_dup 2)
934 (compare:CC (match_dup 0)
935 (const_int 0)))]
936 ""
937 [(set_attr "type" "exts")
938 (set_attr "dot" "yes")
939 (set_attr "length" "4,8")])
942 (define_expand "extendhi<mode>2"
943 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "")
944 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "")))]
945 ""
946 "")
948 (define_insn "*extendhi<mode>2"
949 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
950 (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
951 "rs6000_gen_cell_microcode"
952 "@
953 lha%U1%X1 %0,%1
954 extsh %0,%1"
955 [(set_attr "type" "load,exts")
956 (set_attr "sign_extend" "yes")])
958 (define_insn "*extendhi<mode>2_noload"
959 [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
960 (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
961 "!rs6000_gen_cell_microcode"
962 "extsh %0,%1"
963 [(set_attr "type" "exts")])
965 (define_insn_and_split "*extendhi<mode>2_dot"
966 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
967 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
968 (const_int 0)))
969 (clobber (match_scratch:EXTHI 0 "=r,r"))]
970 "rs6000_gen_cell_microcode"
971 "@
972 extsh. %0,%1
973 #"
974 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
975 [(set (match_dup 0)
976 (sign_extend:EXTHI (match_dup 1)))
977 (set (match_dup 2)
978 (compare:CC (match_dup 0)
979 (const_int 0)))]
980 ""
981 [(set_attr "type" "exts")
982 (set_attr "dot" "yes")
983 (set_attr "length" "4,8")])
985 (define_insn_and_split "*extendhi<mode>2_dot2"
986 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
987 (compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
988 (const_int 0)))
989 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
990 (sign_extend:EXTHI (match_dup 1)))]
991 "rs6000_gen_cell_microcode"
992 "@
993 extsh. %0,%1
994 #"
995 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
996 [(set (match_dup 0)
997 (sign_extend:EXTHI (match_dup 1)))
998 (set (match_dup 2)
999 (compare:CC (match_dup 0)
1000 (const_int 0)))]
1001 ""
1002 [(set_attr "type" "exts")
1003 (set_attr "dot" "yes")
1004 (set_attr "length" "4,8")])
1007 (define_insn "extendsi<mode>2"
1008 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu")
1009 (sign_extend:EXTSI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))]
1010 ""
1011 "@
1012 lwa%U1%X1 %0,%1
1013 extsw %0,%1
1014 mtvsrwa %x0,%1
1015 lfiwax %0,%y1
1016 lxsiwax %x0,%y1"
1017 [(set_attr "type" "load,exts,mffgpr,fpload,fpload")
1018 (set_attr "sign_extend" "yes")])
1020 (define_insn_and_split "*extendsi<mode>2_dot"
1021 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1022 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1023 (const_int 0)))
1024 (clobber (match_scratch:EXTSI 0 "=r,r"))]
1025 "rs6000_gen_cell_microcode"
1026 "@
1027 extsw. %0,%1
1028 #"
1029 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1030 [(set (match_dup 0)
1031 (sign_extend:EXTSI (match_dup 1)))
1032 (set (match_dup 2)
1033 (compare:CC (match_dup 0)
1034 (const_int 0)))]
1035 ""
1036 [(set_attr "type" "exts")
1037 (set_attr "dot" "yes")
1038 (set_attr "length" "4,8")])
1040 (define_insn_and_split "*extendsi<mode>2_dot2"
1041 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1042 (compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1043 (const_int 0)))
1044 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
1045 (sign_extend:EXTSI (match_dup 1)))]
1046 "rs6000_gen_cell_microcode"
1047 "@
1048 extsw. %0,%1
1049 #"
1050 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1051 [(set (match_dup 0)
1052 (sign_extend:EXTSI (match_dup 1)))
1053 (set (match_dup 2)
1054 (compare:CC (match_dup 0)
1055 (const_int 0)))]
1056 ""
1057 [(set_attr "type" "exts")
1058 (set_attr "dot" "yes")
1059 (set_attr "length" "4,8")])
1060 \f
1061 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1063 (define_insn "*macchwc"
1064 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1065 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1066 (match_operand:SI 2 "gpc_reg_operand" "r")
1067 (const_int 16))
1068 (sign_extend:SI
1069 (match_operand:HI 1 "gpc_reg_operand" "r")))
1070 (match_operand:SI 4 "gpc_reg_operand" "0"))
1071 (const_int 0)))
1072 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1073 (plus:SI (mult:SI (ashiftrt:SI
1074 (match_dup 2)
1075 (const_int 16))
1076 (sign_extend:SI
1077 (match_dup 1)))
1078 (match_dup 4)))]
1079 "TARGET_MULHW"
1080 "macchw. %0,%1,%2"
1081 [(set_attr "type" "halfmul")])
1083 (define_insn "*macchw"
1084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1085 (plus:SI (mult:SI (ashiftrt:SI
1086 (match_operand:SI 2 "gpc_reg_operand" "r")
1087 (const_int 16))
1088 (sign_extend:SI
1089 (match_operand:HI 1 "gpc_reg_operand" "r")))
1090 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1091 "TARGET_MULHW"
1092 "macchw %0,%1,%2"
1093 [(set_attr "type" "halfmul")])
1095 (define_insn "*macchwuc"
1096 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1097 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1098 (match_operand:SI 2 "gpc_reg_operand" "r")
1099 (const_int 16))
1100 (zero_extend:SI
1101 (match_operand:HI 1 "gpc_reg_operand" "r")))
1102 (match_operand:SI 4 "gpc_reg_operand" "0"))
1103 (const_int 0)))
1104 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1105 (plus:SI (mult:SI (lshiftrt:SI
1106 (match_dup 2)
1107 (const_int 16))
1108 (zero_extend:SI
1109 (match_dup 1)))
1110 (match_dup 4)))]
1111 "TARGET_MULHW"
1112 "macchwu. %0,%1,%2"
1113 [(set_attr "type" "halfmul")])
1115 (define_insn "*macchwu"
1116 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1117 (plus:SI (mult:SI (lshiftrt:SI
1118 (match_operand:SI 2 "gpc_reg_operand" "r")
1119 (const_int 16))
1120 (zero_extend:SI
1121 (match_operand:HI 1 "gpc_reg_operand" "r")))
1122 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1123 "TARGET_MULHW"
1124 "macchwu %0,%1,%2"
1125 [(set_attr "type" "halfmul")])
1127 (define_insn "*machhwc"
1128 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1129 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1130 (match_operand:SI 1 "gpc_reg_operand" "%r")
1131 (const_int 16))
1132 (ashiftrt:SI
1133 (match_operand:SI 2 "gpc_reg_operand" "r")
1134 (const_int 16)))
1135 (match_operand:SI 4 "gpc_reg_operand" "0"))
1136 (const_int 0)))
1137 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1138 (plus:SI (mult:SI (ashiftrt:SI
1139 (match_dup 1)
1140 (const_int 16))
1141 (ashiftrt:SI
1142 (match_dup 2)
1143 (const_int 16)))
1144 (match_dup 4)))]
1145 "TARGET_MULHW"
1146 "machhw. %0,%1,%2"
1147 [(set_attr "type" "halfmul")])
1149 (define_insn "*machhw"
1150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1151 (plus:SI (mult:SI (ashiftrt:SI
1152 (match_operand:SI 1 "gpc_reg_operand" "%r")
1153 (const_int 16))
1154 (ashiftrt:SI
1155 (match_operand:SI 2 "gpc_reg_operand" "r")
1156 (const_int 16)))
1157 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1158 "TARGET_MULHW"
1159 "machhw %0,%1,%2"
1160 [(set_attr "type" "halfmul")])
1162 (define_insn "*machhwuc"
1163 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1164 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1165 (match_operand:SI 1 "gpc_reg_operand" "%r")
1166 (const_int 16))
1167 (lshiftrt:SI
1168 (match_operand:SI 2 "gpc_reg_operand" "r")
1169 (const_int 16)))
1170 (match_operand:SI 4 "gpc_reg_operand" "0"))
1171 (const_int 0)))
1172 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1173 (plus:SI (mult:SI (lshiftrt:SI
1174 (match_dup 1)
1175 (const_int 16))
1176 (lshiftrt:SI
1177 (match_dup 2)
1178 (const_int 16)))
1179 (match_dup 4)))]
1180 "TARGET_MULHW"
1181 "machhwu. %0,%1,%2"
1182 [(set_attr "type" "halfmul")])
1184 (define_insn "*machhwu"
1185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1186 (plus:SI (mult:SI (lshiftrt:SI
1187 (match_operand:SI 1 "gpc_reg_operand" "%r")
1188 (const_int 16))
1189 (lshiftrt:SI
1190 (match_operand:SI 2 "gpc_reg_operand" "r")
1191 (const_int 16)))
1192 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1193 "TARGET_MULHW"
1194 "machhwu %0,%1,%2"
1195 [(set_attr "type" "halfmul")])
1197 (define_insn "*maclhwc"
1198 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1199 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1200 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1201 (sign_extend:SI
1202 (match_operand:HI 2 "gpc_reg_operand" "r")))
1203 (match_operand:SI 4 "gpc_reg_operand" "0"))
1204 (const_int 0)))
1205 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1206 (plus:SI (mult:SI (sign_extend:SI
1207 (match_dup 1))
1208 (sign_extend:SI
1209 (match_dup 2)))
1210 (match_dup 4)))]
1211 "TARGET_MULHW"
1212 "maclhw. %0,%1,%2"
1213 [(set_attr "type" "halfmul")])
1215 (define_insn "*maclhw"
1216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1217 (plus:SI (mult:SI (sign_extend:SI
1218 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1219 (sign_extend:SI
1220 (match_operand:HI 2 "gpc_reg_operand" "r")))
1221 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1222 "TARGET_MULHW"
1223 "maclhw %0,%1,%2"
1224 [(set_attr "type" "halfmul")])
1226 (define_insn "*maclhwuc"
1227 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1228 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1229 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1230 (zero_extend:SI
1231 (match_operand:HI 2 "gpc_reg_operand" "r")))
1232 (match_operand:SI 4 "gpc_reg_operand" "0"))
1233 (const_int 0)))
1234 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 (plus:SI (mult:SI (zero_extend:SI
1236 (match_dup 1))
1237 (zero_extend:SI
1238 (match_dup 2)))
1239 (match_dup 4)))]
1240 "TARGET_MULHW"
1241 "maclhwu. %0,%1,%2"
1242 [(set_attr "type" "halfmul")])
1244 (define_insn "*maclhwu"
1245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1246 (plus:SI (mult:SI (zero_extend:SI
1247 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1248 (zero_extend:SI
1249 (match_operand:HI 2 "gpc_reg_operand" "r")))
1250 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1251 "TARGET_MULHW"
1252 "maclhwu %0,%1,%2"
1253 [(set_attr "type" "halfmul")])
1255 (define_insn "*nmacchwc"
1256 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1257 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1258 (mult:SI (ashiftrt:SI
1259 (match_operand:SI 2 "gpc_reg_operand" "r")
1260 (const_int 16))
1261 (sign_extend:SI
1262 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1263 (const_int 0)))
1264 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1265 (minus:SI (match_dup 4)
1266 (mult:SI (ashiftrt:SI
1267 (match_dup 2)
1268 (const_int 16))
1269 (sign_extend:SI
1270 (match_dup 1)))))]
1271 "TARGET_MULHW"
1272 "nmacchw. %0,%1,%2"
1273 [(set_attr "type" "halfmul")])
1275 (define_insn "*nmacchw"
1276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1277 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1278 (mult:SI (ashiftrt:SI
1279 (match_operand:SI 2 "gpc_reg_operand" "r")
1280 (const_int 16))
1281 (sign_extend:SI
1282 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1283 "TARGET_MULHW"
1284 "nmacchw %0,%1,%2"
1285 [(set_attr "type" "halfmul")])
1287 (define_insn "*nmachhwc"
1288 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1289 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1290 (mult:SI (ashiftrt:SI
1291 (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (const_int 16))
1293 (ashiftrt:SI
1294 (match_operand:SI 2 "gpc_reg_operand" "r")
1295 (const_int 16))))
1296 (const_int 0)))
1297 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1298 (minus:SI (match_dup 4)
1299 (mult:SI (ashiftrt:SI
1300 (match_dup 1)
1301 (const_int 16))
1302 (ashiftrt:SI
1303 (match_dup 2)
1304 (const_int 16)))))]
1305 "TARGET_MULHW"
1306 "nmachhw. %0,%1,%2"
1307 [(set_attr "type" "halfmul")])
1309 (define_insn "*nmachhw"
1310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1311 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1312 (mult:SI (ashiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (ashiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16)))))]
1318 "TARGET_MULHW"
1319 "nmachhw %0,%1,%2"
1320 [(set_attr "type" "halfmul")])
1322 (define_insn "*nmaclhwc"
1323 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1324 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1325 (mult:SI (sign_extend:SI
1326 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1327 (sign_extend:SI
1328 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1329 (const_int 0)))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (minus:SI (match_dup 4)
1332 (mult:SI (sign_extend:SI
1333 (match_dup 1))
1334 (sign_extend:SI
1335 (match_dup 2)))))]
1336 "TARGET_MULHW"
1337 "nmaclhw. %0,%1,%2"
1338 [(set_attr "type" "halfmul")])
1340 (define_insn "*nmaclhw"
1341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1343 (mult:SI (sign_extend:SI
1344 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1345 (sign_extend:SI
1346 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1347 "TARGET_MULHW"
1348 "nmaclhw %0,%1,%2"
1349 [(set_attr "type" "halfmul")])
1351 (define_insn "*mulchwc"
1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1353 (compare:CC (mult:SI (ashiftrt:SI
1354 (match_operand:SI 2 "gpc_reg_operand" "r")
1355 (const_int 16))
1356 (sign_extend:SI
1357 (match_operand:HI 1 "gpc_reg_operand" "r")))
1358 (const_int 0)))
1359 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1360 (mult:SI (ashiftrt:SI
1361 (match_dup 2)
1362 (const_int 16))
1363 (sign_extend:SI
1364 (match_dup 1))))]
1365 "TARGET_MULHW"
1366 "mulchw. %0,%1,%2"
1367 [(set_attr "type" "halfmul")])
1369 (define_insn "*mulchw"
1370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1371 (mult:SI (ashiftrt:SI
1372 (match_operand:SI 2 "gpc_reg_operand" "r")
1373 (const_int 16))
1374 (sign_extend:SI
1375 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1376 "TARGET_MULHW"
1377 "mulchw %0,%1,%2"
1378 [(set_attr "type" "halfmul")])
1380 (define_insn "*mulchwuc"
1381 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1382 (compare:CC (mult:SI (lshiftrt:SI
1383 (match_operand:SI 2 "gpc_reg_operand" "r")
1384 (const_int 16))
1385 (zero_extend:SI
1386 (match_operand:HI 1 "gpc_reg_operand" "r")))
1387 (const_int 0)))
1388 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1389 (mult:SI (lshiftrt:SI
1390 (match_dup 2)
1391 (const_int 16))
1392 (zero_extend:SI
1393 (match_dup 1))))]
1394 "TARGET_MULHW"
1395 "mulchwu. %0,%1,%2"
1396 [(set_attr "type" "halfmul")])
1398 (define_insn "*mulchwu"
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (mult:SI (lshiftrt:SI
1401 (match_operand:SI 2 "gpc_reg_operand" "r")
1402 (const_int 16))
1403 (zero_extend:SI
1404 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1405 "TARGET_MULHW"
1406 "mulchwu %0,%1,%2"
1407 [(set_attr "type" "halfmul")])
1409 (define_insn "*mulhhwc"
1410 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1411 (compare:CC (mult:SI (ashiftrt:SI
1412 (match_operand:SI 1 "gpc_reg_operand" "%r")
1413 (const_int 16))
1414 (ashiftrt:SI
1415 (match_operand:SI 2 "gpc_reg_operand" "r")
1416 (const_int 16)))
1417 (const_int 0)))
1418 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1419 (mult:SI (ashiftrt:SI
1420 (match_dup 1)
1421 (const_int 16))
1422 (ashiftrt:SI
1423 (match_dup 2)
1424 (const_int 16))))]
1425 "TARGET_MULHW"
1426 "mulhhw. %0,%1,%2"
1427 [(set_attr "type" "halfmul")])
1429 (define_insn "*mulhhw"
1430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1431 (mult:SI (ashiftrt:SI
1432 (match_operand:SI 1 "gpc_reg_operand" "%r")
1433 (const_int 16))
1434 (ashiftrt:SI
1435 (match_operand:SI 2 "gpc_reg_operand" "r")
1436 (const_int 16))))]
1437 "TARGET_MULHW"
1438 "mulhhw %0,%1,%2"
1439 [(set_attr "type" "halfmul")])
1441 (define_insn "*mulhhwuc"
1442 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1443 (compare:CC (mult:SI (lshiftrt:SI
1444 (match_operand:SI 1 "gpc_reg_operand" "%r")
1445 (const_int 16))
1446 (lshiftrt:SI
1447 (match_operand:SI 2 "gpc_reg_operand" "r")
1448 (const_int 16)))
1449 (const_int 0)))
1450 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1451 (mult:SI (lshiftrt:SI
1452 (match_dup 1)
1453 (const_int 16))
1454 (lshiftrt:SI
1455 (match_dup 2)
1456 (const_int 16))))]
1457 "TARGET_MULHW"
1458 "mulhhwu. %0,%1,%2"
1459 [(set_attr "type" "halfmul")])
1461 (define_insn "*mulhhwu"
1462 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1463 (mult:SI (lshiftrt:SI
1464 (match_operand:SI 1 "gpc_reg_operand" "%r")
1465 (const_int 16))
1466 (lshiftrt:SI
1467 (match_operand:SI 2 "gpc_reg_operand" "r")
1468 (const_int 16))))]
1469 "TARGET_MULHW"
1470 "mulhhwu %0,%1,%2"
1471 [(set_attr "type" "halfmul")])
1473 (define_insn "*mullhwc"
1474 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1475 (compare:CC (mult:SI (sign_extend:SI
1476 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1477 (sign_extend:SI
1478 (match_operand:HI 2 "gpc_reg_operand" "r")))
1479 (const_int 0)))
1480 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (mult:SI (sign_extend:SI
1482 (match_dup 1))
1483 (sign_extend:SI
1484 (match_dup 2))))]
1485 "TARGET_MULHW"
1486 "mullhw. %0,%1,%2"
1487 [(set_attr "type" "halfmul")])
1489 (define_insn "*mullhw"
1490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1491 (mult:SI (sign_extend:SI
1492 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1493 (sign_extend:SI
1494 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1495 "TARGET_MULHW"
1496 "mullhw %0,%1,%2"
1497 [(set_attr "type" "halfmul")])
1499 (define_insn "*mullhwuc"
1500 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1501 (compare:CC (mult:SI (zero_extend:SI
1502 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1503 (zero_extend:SI
1504 (match_operand:HI 2 "gpc_reg_operand" "r")))
1505 (const_int 0)))
1506 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1507 (mult:SI (zero_extend:SI
1508 (match_dup 1))
1509 (zero_extend:SI
1510 (match_dup 2))))]
1511 "TARGET_MULHW"
1512 "mullhwu. %0,%1,%2"
1513 [(set_attr "type" "halfmul")])
1515 (define_insn "*mullhwu"
1516 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1517 (mult:SI (zero_extend:SI
1518 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1519 (zero_extend:SI
1520 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1521 "TARGET_MULHW"
1522 "mullhwu %0,%1,%2"
1523 [(set_attr "type" "halfmul")])
1524 \f
1525 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1526 (define_insn "dlmzb"
1527 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1528 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1529 (match_operand:SI 2 "gpc_reg_operand" "r")]
1530 UNSPEC_DLMZB_CR))
1531 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1532 (unspec:SI [(match_dup 1)
1533 (match_dup 2)]
1534 UNSPEC_DLMZB))]
1535 "TARGET_DLMZB"
1536 "dlmzb. %0,%1,%2")
1538 (define_expand "strlensi"
1539 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1540 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1541 (match_operand:QI 2 "const_int_operand" "")
1542 (match_operand 3 "const_int_operand" "")]
1543 UNSPEC_DLMZB_STRLEN))
1544 (clobber (match_scratch:CC 4 "=x"))]
1545 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1546 {
1547 rtx result = operands[0];
1548 rtx src = operands[1];
1549 rtx search_char = operands[2];
1550 rtx align = operands[3];
1551 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1552 rtx loop_label, end_label, mem, cr0, cond;
1553 if (search_char != const0_rtx
1554 || GET_CODE (align) != CONST_INT
1555 || INTVAL (align) < 8)
1556 FAIL;
1557 word1 = gen_reg_rtx (SImode);
1558 word2 = gen_reg_rtx (SImode);
1559 scratch_dlmzb = gen_reg_rtx (SImode);
1560 scratch_string = gen_reg_rtx (Pmode);
1561 loop_label = gen_label_rtx ();
1562 end_label = gen_label_rtx ();
1563 addr = force_reg (Pmode, XEXP (src, 0));
1564 emit_move_insn (scratch_string, addr);
1565 emit_label (loop_label);
1566 mem = change_address (src, SImode, scratch_string);
1567 emit_move_insn (word1, mem);
1568 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1569 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1570 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1571 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1572 emit_jump_insn (gen_rtx_SET (pc_rtx,
1573 gen_rtx_IF_THEN_ELSE (VOIDmode,
1574 cond,
1575 gen_rtx_LABEL_REF
1576 (VOIDmode,
1577 end_label),
1578 pc_rtx)));
1579 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1580 emit_jump_insn (gen_rtx_SET (pc_rtx,
1581 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1582 emit_barrier ();
1583 emit_label (end_label);
1584 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1585 emit_insn (gen_subsi3 (result, scratch_string, addr));
1586 emit_insn (gen_addsi3 (result, result, constm1_rtx));
1587 DONE;
1588 })
1589 \f
1590 ;; Fixed-point arithmetic insns.
1592 (define_expand "add<mode>3"
1593 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1594 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1595 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1596 ""
1597 {
1598 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1599 {
1600 rtx lo0 = gen_lowpart (SImode, operands[0]);
1601 rtx lo1 = gen_lowpart (SImode, operands[1]);
1602 rtx lo2 = gen_lowpart (SImode, operands[2]);
1603 rtx hi0 = gen_highpart (SImode, operands[0]);
1604 rtx hi1 = gen_highpart (SImode, operands[1]);
1605 rtx hi2 = gen_highpart_mode (SImode, DImode, operands[2]);
1607 if (!reg_or_short_operand (lo2, SImode))
1608 lo2 = force_reg (SImode, lo2);
1609 if (!adde_operand (hi2, SImode))
1610 hi2 = force_reg (SImode, hi2);
1612 emit_insn (gen_addsi3_carry (lo0, lo1, lo2));
1613 emit_insn (gen_addsi3_carry_in (hi0, hi1, hi2));
1614 DONE;
1615 }
1617 if (CONST_INT_P (operands[2]) && !add_operand (operands[2], <MODE>mode))
1618 {
1619 rtx tmp = ((!can_create_pseudo_p ()
1620 || rtx_equal_p (operands[0], operands[1]))
1621 ? operands[0] : gen_reg_rtx (<MODE>mode));
1623 HOST_WIDE_INT val = INTVAL (operands[2]);
1624 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1625 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1627 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1628 FAIL;
1630 /* The ordering here is important for the prolog expander.
1631 When space is allocated from the stack, adding 'low' first may
1632 produce a temporary deallocation (which would be bad). */
1633 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1634 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1635 DONE;
1636 }
1637 })
1639 (define_insn "*add<mode>3"
1640 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r")
1641 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b")
1642 (match_operand:GPR 2 "add_operand" "r,I,L")))]
1643 ""
1644 "@
1645 add %0,%1,%2
1646 addi %0,%1,%2
1647 addis %0,%1,%v2"
1648 [(set_attr "type" "add")])
1650 (define_insn "addsi3_high"
1651 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1652 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1653 (high:SI (match_operand 2 "" ""))))]
1654 "TARGET_MACHO && !TARGET_64BIT"
1655 "addis %0,%1,ha16(%2)"
1656 [(set_attr "type" "add")])
1658 (define_insn_and_split "*add<mode>3_dot"
1659 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1660 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
1661 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
1662 (const_int 0)))
1663 (clobber (match_scratch:GPR 0 "=r,r"))]
1664 "<MODE>mode == Pmode"
1665 "@
1666 add. %0,%1,%2
1667 #"
1668 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1669 [(set (match_dup 0)
1670 (plus:GPR (match_dup 1)
1671 (match_dup 2)))
1672 (set (match_dup 3)
1673 (compare:CC (match_dup 0)
1674 (const_int 0)))]
1675 ""
1676 [(set_attr "type" "add")
1677 (set_attr "dot" "yes")
1678 (set_attr "length" "4,8")])
1680 (define_insn_and_split "*add<mode>3_dot2"
1681 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1682 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
1683 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
1684 (const_int 0)))
1685 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1686 (plus:GPR (match_dup 1)
1687 (match_dup 2)))]
1688 "<MODE>mode == Pmode"
1689 "@
1690 add. %0,%1,%2
1691 #"
1692 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1693 [(set (match_dup 0)
1694 (plus:GPR (match_dup 1)
1695 (match_dup 2)))
1696 (set (match_dup 3)
1697 (compare:CC (match_dup 0)
1698 (const_int 0)))]
1699 ""
1700 [(set_attr "type" "add")
1701 (set_attr "dot" "yes")
1702 (set_attr "length" "4,8")])
1704 (define_insn_and_split "*add<mode>3_imm_dot"
1705 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1706 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b")
1707 (match_operand:GPR 2 "short_cint_operand" "I,I"))
1708 (const_int 0)))
1709 (clobber (match_scratch:GPR 0 "=r,r"))
1710 (clobber (reg:GPR CA_REGNO))]
1711 "<MODE>mode == Pmode"
1712 "@
1713 addic. %0,%1,%2
1714 #"
1715 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1716 [(set (match_dup 0)
1717 (plus:GPR (match_dup 1)
1718 (match_dup 2)))
1719 (set (match_dup 3)
1720 (compare:CC (match_dup 0)
1721 (const_int 0)))]
1722 ""
1723 [(set_attr "type" "add")
1724 (set_attr "dot" "yes")
1725 (set_attr "length" "4,8")])
1727 (define_insn_and_split "*add<mode>3_imm_dot2"
1728 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1729 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b")
1730 (match_operand:GPR 2 "short_cint_operand" "I,I"))
1731 (const_int 0)))
1732 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1733 (plus:GPR (match_dup 1)
1734 (match_dup 2)))
1735 (clobber (reg:GPR CA_REGNO))]
1736 "<MODE>mode == Pmode"
1737 "@
1738 addic. %0,%1,%2
1739 #"
1740 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
1741 [(set (match_dup 0)
1742 (plus:GPR (match_dup 1)
1743 (match_dup 2)))
1744 (set (match_dup 3)
1745 (compare:CC (match_dup 0)
1746 (const_int 0)))]
1747 ""
1748 [(set_attr "type" "add")
1749 (set_attr "dot" "yes")
1750 (set_attr "length" "4,8")])
1752 ;; Split an add that we can't do in one insn into two insns, each of which
1753 ;; does one 16-bit part. This is used by combine. Note that the low-order
1754 ;; add should be last in case the result gets used in an address.
1756 (define_split
1757 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1758 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1759 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1760 ""
1761 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1762 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1763 {
1764 HOST_WIDE_INT val = INTVAL (operands[2]);
1765 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1766 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1768 operands[4] = GEN_INT (low);
1769 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1770 operands[3] = GEN_INT (rest);
1771 else if (can_create_pseudo_p ())
1772 {
1773 operands[3] = gen_reg_rtx (DImode);
1774 emit_move_insn (operands[3], operands[2]);
1775 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1776 DONE;
1777 }
1778 else
1779 FAIL;
1780 })
1783 (define_insn "add<mode>3_carry"
1784 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1785 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1786 (match_operand:P 2 "reg_or_short_operand" "rI")))
1787 (set (reg:P CA_REGNO)
1788 (ltu:P (plus:P (match_dup 1)
1789 (match_dup 2))
1790 (match_dup 1)))]
1791 ""
1792 "add%I2c %0,%1,%2"
1793 [(set_attr "type" "add")])
1795 (define_insn "*add<mode>3_imm_carry_pos"
1796 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1797 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1798 (match_operand:P 2 "short_cint_operand" "n")))
1799 (set (reg:P CA_REGNO)
1800 (geu:P (match_dup 1)
1801 (match_operand:P 3 "const_int_operand" "n")))]
1802 "INTVAL (operands[2]) > 0
1803 && INTVAL (operands[2]) + INTVAL (operands[3]) == 0"
1804 "addic %0,%1,%2"
1805 [(set_attr "type" "add")])
1807 (define_insn "*add<mode>3_imm_carry_0"
1808 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1809 (match_operand:P 1 "gpc_reg_operand" "r"))
1810 (set (reg:P CA_REGNO)
1811 (const_int 0))]
1812 ""
1813 "addic %0,%1,0"
1814 [(set_attr "type" "add")])
1816 (define_insn "*add<mode>3_imm_carry_m1"
1817 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1818 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1819 (const_int -1)))
1820 (set (reg:P CA_REGNO)
1821 (ne:P (match_dup 1)
1822 (const_int 0)))]
1823 ""
1824 "addic %0,%1,-1"
1825 [(set_attr "type" "add")])
1827 (define_insn "*add<mode>3_imm_carry_neg"
1828 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
1829 (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
1830 (match_operand:P 2 "short_cint_operand" "n")))
1831 (set (reg:P CA_REGNO)
1832 (gtu:P (match_dup 1)
1833 (match_operand:P 3 "const_int_operand" "n")))]
1834 "INTVAL (operands[2]) < 0
1835 && INTVAL (operands[2]) + INTVAL (operands[3]) == -1"
1836 "addic %0,%1,%2"
1837 [(set_attr "type" "add")])
1840 (define_expand "add<mode>3_carry_in"
1841 [(parallel [
1842 (set (match_operand:GPR 0 "gpc_reg_operand")
1843 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand")
1844 (match_operand:GPR 2 "adde_operand"))
1845 (reg:GPR CA_REGNO)))
1846 (clobber (reg:GPR CA_REGNO))])]
1847 ""
1848 {
1849 if (operands[2] == const0_rtx)
1850 {
1851 emit_insn (gen_add<mode>3_carry_in_0 (operands[0], operands[1]));
1852 DONE;
1853 }
1854 if (operands[2] == constm1_rtx)
1855 {
1856 emit_insn (gen_add<mode>3_carry_in_m1 (operands[0], operands[1]));
1857 DONE;
1858 }
1859 })
1861 (define_insn "*add<mode>3_carry_in_internal"
1862 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1863 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1864 (match_operand:GPR 2 "gpc_reg_operand" "r"))
1865 (reg:GPR CA_REGNO)))
1866 (clobber (reg:GPR CA_REGNO))]
1867 ""
1868 "adde %0,%1,%2"
1869 [(set_attr "type" "add")])
1871 (define_insn "add<mode>3_carry_in_0"
1872 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1873 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1874 (reg:GPR CA_REGNO)))
1875 (clobber (reg:GPR CA_REGNO))]
1876 ""
1877 "addze %0,%1"
1878 [(set_attr "type" "add")])
1880 (define_insn "add<mode>3_carry_in_m1"
1881 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1882 (plus:GPR (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
1883 (reg:GPR CA_REGNO))
1884 (const_int -1)))
1885 (clobber (reg:GPR CA_REGNO))]
1886 ""
1887 "addme %0,%1"
1888 [(set_attr "type" "add")])
1891 (define_expand "one_cmpl<mode>2"
1892 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1893 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1894 ""
1895 {
1896 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1897 {
1898 rs6000_split_logical (operands, NOT, false, false, false);
1899 DONE;
1900 }
1901 })
1903 (define_insn "*one_cmpl<mode>2"
1904 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1905 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1906 ""
1907 "not %0,%1")
1909 (define_insn_and_split "*one_cmpl<mode>2_dot"
1910 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1911 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1912 (const_int 0)))
1913 (clobber (match_scratch:GPR 0 "=r,r"))]
1914 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1915 "@
1916 not. %0,%1
1917 #"
1918 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1919 [(set (match_dup 0)
1920 (not:GPR (match_dup 1)))
1921 (set (match_dup 2)
1922 (compare:CC (match_dup 0)
1923 (const_int 0)))]
1924 ""
1925 [(set_attr "type" "logical")
1926 (set_attr "dot" "yes")
1927 (set_attr "length" "4,8")])
1929 (define_insn_and_split "*one_cmpl<mode>2_dot2"
1930 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1931 (compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1932 (const_int 0)))
1933 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1934 (not:GPR (match_dup 1)))]
1935 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
1936 "@
1937 not. %0,%1
1938 #"
1939 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
1940 [(set (match_dup 0)
1941 (not:GPR (match_dup 1)))
1942 (set (match_dup 2)
1943 (compare:CC (match_dup 0)
1944 (const_int 0)))]
1945 ""
1946 [(set_attr "type" "logical")
1947 (set_attr "dot" "yes")
1948 (set_attr "length" "4,8")])
1951 (define_expand "sub<mode>3"
1952 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1953 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1954 (match_operand:SDI 2 "gpc_reg_operand" "")))]
1955 ""
1956 {
1957 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1958 {
1959 rtx lo0 = gen_lowpart (SImode, operands[0]);
1960 rtx lo1 = gen_lowpart (SImode, operands[1]);
1961 rtx lo2 = gen_lowpart (SImode, operands[2]);
1962 rtx hi0 = gen_highpart (SImode, operands[0]);
1963 rtx hi1 = gen_highpart_mode (SImode, DImode, operands[1]);
1964 rtx hi2 = gen_highpart (SImode, operands[2]);
1966 if (!reg_or_short_operand (lo1, SImode))
1967 lo1 = force_reg (SImode, lo1);
1968 if (!adde_operand (hi1, SImode))
1969 hi1 = force_reg (SImode, hi1);
1971 emit_insn (gen_subfsi3_carry (lo0, lo2, lo1));
1972 emit_insn (gen_subfsi3_carry_in (hi0, hi2, hi1));
1973 DONE;
1974 }
1976 if (short_cint_operand (operands[1], <MODE>mode))
1977 {
1978 emit_insn (gen_subf<mode>3_imm (operands[0], operands[2], operands[1]));
1979 DONE;
1980 }
1981 })
1983 (define_insn "*subf<mode>3"
1984 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1985 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r")
1986 (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1987 ""
1988 "subf %0,%1,%2"
1989 [(set_attr "type" "add")])
1991 (define_insn_and_split "*subf<mode>3_dot"
1992 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1993 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
1994 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
1995 (const_int 0)))
1996 (clobber (match_scratch:GPR 0 "=r,r"))]
1997 "<MODE>mode == Pmode"
1998 "@
1999 subf. %0,%1,%2
2000 #"
2001 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2002 [(set (match_dup 0)
2003 (minus:GPR (match_dup 2)
2004 (match_dup 1)))
2005 (set (match_dup 3)
2006 (compare:CC (match_dup 0)
2007 (const_int 0)))]
2008 ""
2009 [(set_attr "type" "add")
2010 (set_attr "dot" "yes")
2011 (set_attr "length" "4,8")])
2013 (define_insn_and_split "*subf<mode>3_dot2"
2014 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2015 (compare:CC (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r")
2016 (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
2017 (const_int 0)))
2018 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2019 (minus:GPR (match_dup 2)
2020 (match_dup 1)))]
2021 "<MODE>mode == Pmode"
2022 "@
2023 subf. %0,%1,%2
2024 #"
2025 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2026 [(set (match_dup 0)
2027 (minus:GPR (match_dup 2)
2028 (match_dup 1)))
2029 (set (match_dup 3)
2030 (compare:CC (match_dup 0)
2031 (const_int 0)))]
2032 ""
2033 [(set_attr "type" "add")
2034 (set_attr "dot" "yes")
2035 (set_attr "length" "4,8")])
2037 (define_insn "subf<mode>3_imm"
2038 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2039 (minus:GPR (match_operand:GPR 2 "short_cint_operand" "I")
2040 (match_operand:GPR 1 "gpc_reg_operand" "r")))
2041 (clobber (reg:GPR CA_REGNO))]
2042 ""
2043 "subfic %0,%1,%2"
2044 [(set_attr "type" "add")])
2047 (define_insn "subf<mode>3_carry"
2048 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
2049 (minus:P (match_operand:P 2 "reg_or_short_operand" "rI")
2050 (match_operand:P 1 "gpc_reg_operand" "r")))
2051 (set (reg:P CA_REGNO)
2052 (leu:P (match_dup 1)
2053 (match_dup 2)))]
2054 ""
2055 "subf%I2c %0,%1,%2"
2056 [(set_attr "type" "add")])
2058 (define_insn "*subf<mode>3_imm_carry_0"
2059 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
2060 (neg:P (match_operand:P 1 "gpc_reg_operand" "r")))
2061 (set (reg:P CA_REGNO)
2062 (eq:P (match_dup 1)
2063 (const_int 0)))]
2064 ""
2065 "subfic %0,%1,0"
2066 [(set_attr "type" "add")])
2068 (define_insn "*subf<mode>3_imm_carry_m1"
2069 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
2070 (not:P (match_operand:P 1 "gpc_reg_operand" "r")))
2071 (set (reg:P CA_REGNO)
2072 (const_int 1))]
2073 ""
2074 "subfic %0,%1,-1"
2075 [(set_attr "type" "add")])
2078 (define_expand "subf<mode>3_carry_in"
2079 [(parallel [
2080 (set (match_operand:GPR 0 "gpc_reg_operand")
2081 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand"))
2082 (reg:GPR CA_REGNO))
2083 (match_operand:GPR 2 "adde_operand")))
2084 (clobber (reg:GPR CA_REGNO))])]
2085 ""
2086 {
2087 if (operands[2] == const0_rtx)
2088 {
2089 emit_insn (gen_subf<mode>3_carry_in_0 (operands[0], operands[1]));
2090 DONE;
2091 }
2092 if (operands[2] == constm1_rtx)
2093 {
2094 emit_insn (gen_subf<mode>3_carry_in_m1 (operands[0], operands[1]));
2095 DONE;
2096 }
2097 })
2099 (define_insn "*subf<mode>3_carry_in_internal"
2100 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2101 (plus:GPR (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
2102 (reg:GPR CA_REGNO))
2103 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2104 (clobber (reg:GPR CA_REGNO))]
2105 ""
2106 "subfe %0,%1,%2"
2107 [(set_attr "type" "add")])
2109 (define_insn "subf<mode>3_carry_in_0"
2110 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2111 (plus:GPR (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
2112 (reg:GPR CA_REGNO)))
2113 (clobber (reg:GPR CA_REGNO))]
2114 ""
2115 "subfze %0,%1"
2116 [(set_attr "type" "add")])
2118 (define_insn "subf<mode>3_carry_in_m1"
2119 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2120 (plus:GPR (minus:GPR (reg:GPR CA_REGNO)
2121 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2122 (const_int -2)))
2123 (clobber (reg:GPR CA_REGNO))]
2124 ""
2125 "subfme %0,%1"
2126 [(set_attr "type" "add")])
2128 (define_insn "subf<mode>3_carry_in_xx"
2129 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2130 (plus:GPR (reg:GPR CA_REGNO)
2131 (const_int -1)))
2132 (clobber (reg:GPR CA_REGNO))]
2133 ""
2134 "subfe %0,%0,%0"
2135 [(set_attr "type" "add")])
2138 (define_insn "neg<mode>2"
2139 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2140 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2141 ""
2142 "neg %0,%1"
2143 [(set_attr "type" "add")])
2145 (define_insn_and_split "*neg<mode>2_dot"
2146 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2147 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
2148 (const_int 0)))
2149 (clobber (match_scratch:GPR 0 "=r,r"))]
2150 "<MODE>mode == Pmode"
2151 "@
2152 neg. %0,%1
2153 #"
2154 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
2155 [(set (match_dup 0)
2156 (neg:GPR (match_dup 1)))
2157 (set (match_dup 2)
2158 (compare:CC (match_dup 0)
2159 (const_int 0)))]
2160 ""
2161 [(set_attr "type" "add")
2162 (set_attr "dot" "yes")
2163 (set_attr "length" "4,8")])
2165 (define_insn_and_split "*neg<mode>2_dot2"
2166 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2167 (compare:CC (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
2168 (const_int 0)))
2169 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2170 (neg:GPR (match_dup 1)))]
2171 "<MODE>mode == Pmode"
2172 "@
2173 neg. %0,%1
2174 #"
2175 "&& reload_completed && cc_reg_not_cr0_operand (operands[2], CCmode)"
2176 [(set (match_dup 0)
2177 (neg:GPR (match_dup 1)))
2178 (set (match_dup 2)
2179 (compare:CC (match_dup 0)
2180 (const_int 0)))]
2181 ""
2182 [(set_attr "type" "add")
2183 (set_attr "dot" "yes")
2184 (set_attr "length" "4,8")])
2187 (define_insn "clz<mode>2"
2188 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2189 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2190 ""
2191 "cntlz<wd> %0,%1"
2192 [(set_attr "type" "cntlz")])
2194 (define_expand "ctz<mode>2"
2195 [(set (match_dup 2)
2196 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2197 (set (match_dup 3)
2198 (and:GPR (match_dup 1)
2199 (match_dup 2)))
2200 (set (match_dup 4)
2201 (clz:GPR (match_dup 3)))
2202 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2203 (minus:GPR (match_dup 5)
2204 (match_dup 4)))
2205 (clobber (reg:GPR CA_REGNO))])]
2206 ""
2207 {
2208 if (TARGET_CTZ)
2209 {
2210 emit_insn (gen_ctz<mode>2_hw (operands[0], operands[1]));
2211 DONE;
2212 }
2214 operands[2] = gen_reg_rtx (<MODE>mode);
2215 operands[3] = gen_reg_rtx (<MODE>mode);
2216 operands[4] = gen_reg_rtx (<MODE>mode);
2217 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2218 })
2220 (define_insn "ctz<mode>2_hw"
2221 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2222 (ctz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2223 "TARGET_CTZ"
2224 "cnttz<wd> %0,%1"
2225 [(set_attr "type" "cntlz")])
2227 (define_expand "ffs<mode>2"
2228 [(set (match_dup 2)
2229 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2230 (set (match_dup 3)
2231 (and:GPR (match_dup 1)
2232 (match_dup 2)))
2233 (set (match_dup 4)
2234 (clz:GPR (match_dup 3)))
2235 (parallel [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2236 (minus:GPR (match_dup 5)
2237 (match_dup 4)))
2238 (clobber (reg:GPR CA_REGNO))])]
2239 ""
2240 {
2241 operands[2] = gen_reg_rtx (<MODE>mode);
2242 operands[3] = gen_reg_rtx (<MODE>mode);
2243 operands[4] = gen_reg_rtx (<MODE>mode);
2244 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2245 })
2248 (define_expand "popcount<mode>2"
2249 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2250 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2251 "TARGET_POPCNTB || TARGET_POPCNTD"
2252 {
2253 rs6000_emit_popcount (operands[0], operands[1]);
2254 DONE;
2255 })
2257 (define_insn "popcntb<mode>2"
2258 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2259 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2260 UNSPEC_POPCNTB))]
2261 "TARGET_POPCNTB"
2262 "popcntb %0,%1"
2263 [(set_attr "type" "popcnt")])
2265 (define_insn "popcntd<mode>2"
2266 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2267 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2268 "TARGET_POPCNTD"
2269 "popcnt<wd> %0,%1"
2270 [(set_attr "type" "popcnt")])
2273 (define_expand "parity<mode>2"
2274 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2275 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2276 "TARGET_POPCNTB"
2277 {
2278 rs6000_emit_parity (operands[0], operands[1]);
2279 DONE;
2280 })
2282 (define_insn "parity<mode>2_cmpb"
2283 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2284 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2285 "TARGET_CMPB && TARGET_POPCNTB"
2286 "prty<wd> %0,%1"
2287 [(set_attr "type" "popcnt")])
2290 ;; Since the hardware zeros the upper part of the register, save generating the
2291 ;; AND immediate if we are converting to unsigned
2292 (define_insn "*bswaphi2_extenddi"
2293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2294 (zero_extend:DI
2295 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2296 "TARGET_POWERPC64"
2297 "lhbrx %0,%y1"
2298 [(set_attr "length" "4")
2299 (set_attr "type" "load")])
2301 (define_insn "*bswaphi2_extendsi"
2302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2303 (zero_extend:SI
2304 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2305 ""
2306 "lhbrx %0,%y1"
2307 [(set_attr "length" "4")
2308 (set_attr "type" "load")])
2310 (define_expand "bswaphi2"
2311 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2312 (bswap:HI
2313 (match_operand:HI 1 "reg_or_mem_operand" "")))
2314 (clobber (match_scratch:SI 2 ""))])]
2315 ""
2316 {
2317 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2318 operands[1] = force_reg (HImode, operands[1]);
2319 })
2321 (define_insn "bswaphi2_internal"
2322 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2323 (bswap:HI
2324 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2325 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2326 ""
2327 "@
2328 lhbrx %0,%y1
2329 sthbrx %1,%y0
2330 #"
2331 [(set_attr "length" "4,4,12")
2332 (set_attr "type" "load,store,*")])
2334 (define_split
2335 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2336 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2337 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2338 "reload_completed"
2339 [(set (match_dup 3)
2340 (and:SI (lshiftrt:SI (match_dup 4)
2341 (const_int 8))
2342 (const_int 255)))
2343 (set (match_dup 2)
2344 (and:SI (ashift:SI (match_dup 4)
2345 (const_int 8))
2346 (const_int 65280))) ;; 0xff00
2347 (set (match_dup 3)
2348 (ior:SI (match_dup 3)
2349 (match_dup 2)))]
2350 "
2351 {
2352 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2353 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2354 }")
2356 (define_insn "*bswapsi2_extenddi"
2357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2358 (zero_extend:DI
2359 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2360 "TARGET_POWERPC64"
2361 "lwbrx %0,%y1"
2362 [(set_attr "length" "4")
2363 (set_attr "type" "load")])
2365 (define_expand "bswapsi2"
2366 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2367 (bswap:SI
2368 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2369 ""
2370 {
2371 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2372 operands[1] = force_reg (SImode, operands[1]);
2373 })
2375 (define_insn "*bswapsi2_internal"
2376 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2377 (bswap:SI
2378 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2379 ""
2380 "@
2381 lwbrx %0,%y1
2382 stwbrx %1,%y0
2383 #"
2384 [(set_attr "length" "4,4,12")
2385 (set_attr "type" "load,store,*")])
2387 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2388 ;; zero_extract insns do not change for -mlittle.
2389 (define_split
2390 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2391 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2392 "reload_completed"
2393 [(set (match_dup 0) ; DABC
2394 (rotate:SI (match_dup 1)
2395 (const_int 24)))
2396 (set (match_dup 0) ; DCBC
2397 (ior:SI (and:SI (ashift:SI (match_dup 1)
2398 (const_int 8))
2399 (const_int 16711680))
2400 (and:SI (match_dup 0)
2401 (const_int -16711681))))
2402 (set (match_dup 0) ; DCBA
2403 (ior:SI (and:SI (lshiftrt:SI (match_dup 1)
2404 (const_int 24))
2405 (const_int 255))
2406 (and:SI (match_dup 0)
2407 (const_int -256))))
2409 ]
2410 "")
2412 (define_expand "bswapdi2"
2413 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2414 (bswap:DI
2415 (match_operand:DI 1 "reg_or_mem_operand" "")))
2416 (clobber (match_scratch:DI 2 ""))
2417 (clobber (match_scratch:DI 3 ""))])]
2418 ""
2419 {
2420 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2421 operands[1] = force_reg (DImode, operands[1]);
2423 if (!TARGET_POWERPC64)
2424 {
2425 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2426 that uses 64-bit registers needs the same scratch registers as 64-bit
2427 mode. */
2428 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2429 DONE;
2430 }
2431 })
2433 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2434 (define_insn "*bswapdi2_ldbrx"
2435 [(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,&r")
2436 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2437 (clobber (match_scratch:DI 2 "=X,X,&r"))
2438 (clobber (match_scratch:DI 3 "=X,X,&r"))]
2439 "TARGET_POWERPC64 && TARGET_LDBRX
2440 && (REG_P (operands[0]) || REG_P (operands[1]))"
2441 "@
2442 ldbrx %0,%y1
2443 stdbrx %1,%y0
2444 #"
2445 [(set_attr "length" "4,4,36")
2446 (set_attr "type" "load,store,*")])
2448 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2449 (define_insn "*bswapdi2_64bit"
2450 [(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,&r")
2451 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2452 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2453 (clobber (match_scratch:DI 3 "=&r,&r,&r"))]
2454 "TARGET_POWERPC64 && !TARGET_LDBRX
2455 && (REG_P (operands[0]) || REG_P (operands[1]))
2456 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2457 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2458 "#"
2459 [(set_attr "length" "16,12,36")])
2461 (define_split
2462 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2463 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2464 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2465 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
2466 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2467 [(const_int 0)]
2468 "
2469 {
2470 rtx dest = operands[0];
2471 rtx src = operands[1];
2472 rtx op2 = operands[2];
2473 rtx op3 = operands[3];
2474 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2475 BYTES_BIG_ENDIAN ? 4 : 0);
2476 rtx dest_32 = simplify_gen_subreg (SImode, dest, DImode,
2477 BYTES_BIG_ENDIAN ? 4 : 0);
2478 rtx addr1;
2479 rtx addr2;
2480 rtx word1;
2481 rtx word2;
2483 addr1 = XEXP (src, 0);
2484 if (GET_CODE (addr1) == PLUS)
2485 {
2486 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2487 if (TARGET_AVOID_XFORM)
2488 {
2489 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2490 addr2 = op2;
2491 }
2492 else
2493 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2494 }
2495 else if (TARGET_AVOID_XFORM)
2496 {
2497 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2498 addr2 = op2;
2499 }
2500 else
2501 {
2502 emit_move_insn (op2, GEN_INT (4));
2503 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2504 }
2506 word1 = change_address (src, SImode, addr1);
2507 word2 = change_address (src, SImode, addr2);
2509 if (BYTES_BIG_ENDIAN)
2510 {
2511 emit_insn (gen_bswapsi2 (op3_32, word2));
2512 emit_insn (gen_bswapsi2 (dest_32, word1));
2513 }
2514 else
2515 {
2516 emit_insn (gen_bswapsi2 (op3_32, word1));
2517 emit_insn (gen_bswapsi2 (dest_32, word2));
2518 }
2520 emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32)));
2521 emit_insn (gen_iordi3 (dest, dest, op3));
2522 DONE;
2523 }")
2525 (define_split
2526 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2527 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2528 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2529 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
2530 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2531 [(const_int 0)]
2532 "
2533 {
2534 rtx dest = operands[0];
2535 rtx src = operands[1];
2536 rtx op2 = operands[2];
2537 rtx op3 = operands[3];
2538 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2539 BYTES_BIG_ENDIAN ? 4 : 0);
2540 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2541 BYTES_BIG_ENDIAN ? 4 : 0);
2542 rtx addr1;
2543 rtx addr2;
2544 rtx word1;
2545 rtx word2;
2547 addr1 = XEXP (dest, 0);
2548 if (GET_CODE (addr1) == PLUS)
2549 {
2550 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2551 if (TARGET_AVOID_XFORM)
2552 {
2553 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2554 addr2 = op2;
2555 }
2556 else
2557 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2558 }
2559 else if (TARGET_AVOID_XFORM)
2560 {
2561 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2562 addr2 = op2;
2563 }
2564 else
2565 {
2566 emit_move_insn (op2, GEN_INT (4));
2567 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2568 }
2570 word1 = change_address (dest, SImode, addr1);
2571 word2 = change_address (dest, SImode, addr2);
2573 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2575 if (BYTES_BIG_ENDIAN)
2576 {
2577 emit_insn (gen_bswapsi2 (word1, src_si));
2578 emit_insn (gen_bswapsi2 (word2, op3_si));
2579 }
2580 else
2581 {
2582 emit_insn (gen_bswapsi2 (word2, src_si));
2583 emit_insn (gen_bswapsi2 (word1, op3_si));
2584 }
2585 DONE;
2586 }")
2588 (define_split
2589 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2590 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2591 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2592 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
2593 "TARGET_POWERPC64 && reload_completed"
2594 [(const_int 0)]
2595 "
2596 {
2597 rtx dest = operands[0];
2598 rtx src = operands[1];
2599 rtx op2 = operands[2];
2600 rtx op3 = operands[3];
2601 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2602 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2603 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2604 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2605 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2607 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2608 emit_insn (gen_bswapsi2 (dest_si, src_si));
2609 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2610 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2611 emit_insn (gen_iordi3 (dest, dest, op3));
2612 DONE;
2613 }")
2615 (define_insn "bswapdi2_32bit"
2616 [(set (match_operand:DI 0 "reg_or_mem_operand" "=r,Z,?&r")
2617 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2618 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2619 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2620 "#"
2621 [(set_attr "length" "16,12,36")])
2623 (define_split
2624 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2625 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2626 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2627 "!TARGET_POWERPC64 && reload_completed"
2628 [(const_int 0)]
2629 "
2630 {
2631 rtx dest = operands[0];
2632 rtx src = operands[1];
2633 rtx op2 = operands[2];
2634 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2635 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2636 rtx addr1;
2637 rtx addr2;
2638 rtx word1;
2639 rtx word2;
2641 addr1 = XEXP (src, 0);
2642 if (GET_CODE (addr1) == PLUS)
2643 {
2644 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2645 if (TARGET_AVOID_XFORM
2646 || REGNO (XEXP (addr1, 1)) == REGNO (dest2))
2647 {
2648 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2649 addr2 = op2;
2650 }
2651 else
2652 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2653 }
2654 else if (TARGET_AVOID_XFORM
2655 || REGNO (addr1) == REGNO (dest2))
2656 {
2657 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2658 addr2 = op2;
2659 }
2660 else
2661 {
2662 emit_move_insn (op2, GEN_INT (4));
2663 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2664 }
2666 word1 = change_address (src, SImode, addr1);
2667 word2 = change_address (src, SImode, addr2);
2669 emit_insn (gen_bswapsi2 (dest2, word1));
2670 /* The REGNO (dest2) tests above ensure that addr2 has not been trashed,
2671 thus allowing us to omit an early clobber on the output. */
2672 emit_insn (gen_bswapsi2 (dest1, word2));
2673 DONE;
2674 }")
2676 (define_split
2677 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2678 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2679 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2680 "!TARGET_POWERPC64 && reload_completed"
2681 [(const_int 0)]
2682 "
2683 {
2684 rtx dest = operands[0];
2685 rtx src = operands[1];
2686 rtx op2 = operands[2];
2687 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2688 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2689 rtx addr1;
2690 rtx addr2;
2691 rtx word1;
2692 rtx word2;
2694 addr1 = XEXP (dest, 0);
2695 if (GET_CODE (addr1) == PLUS)
2696 {
2697 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2698 if (TARGET_AVOID_XFORM)
2699 {
2700 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2701 addr2 = op2;
2702 }
2703 else
2704 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2705 }
2706 else if (TARGET_AVOID_XFORM)
2707 {
2708 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2709 addr2 = op2;
2710 }
2711 else
2712 {
2713 emit_move_insn (op2, GEN_INT (4));
2714 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2715 }
2717 word1 = change_address (dest, SImode, addr1);
2718 word2 = change_address (dest, SImode, addr2);
2720 emit_insn (gen_bswapsi2 (word2, src1));
2721 emit_insn (gen_bswapsi2 (word1, src2));
2722 DONE;
2723 }")
2725 (define_split
2726 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2727 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2728 (clobber (match_operand:SI 2 "" ""))]
2729 "!TARGET_POWERPC64 && reload_completed"
2730 [(const_int 0)]
2731 "
2732 {
2733 rtx dest = operands[0];
2734 rtx src = operands[1];
2735 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2736 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2737 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2738 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2740 emit_insn (gen_bswapsi2 (dest1, src2));
2741 emit_insn (gen_bswapsi2 (dest2, src1));
2742 DONE;
2743 }")
2746 (define_insn "mul<mode>3"
2747 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2748 (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
2749 (match_operand:GPR 2 "reg_or_short_operand" "r,I")))]
2750 ""
2751 "@
2752 mull<wd> %0,%1,%2
2753 mulli %0,%1,%2"
2754 [(set_attr "type" "mul")
2755 (set (attr "size")
2756 (cond [(match_operand:GPR 2 "s8bit_cint_operand" "")
2757 (const_string "8")
2758 (match_operand:GPR 2 "short_cint_operand" "")
2759 (const_string "16")]
2760 (const_string "<bits>")))])
2762 (define_insn_and_split "*mul<mode>3_dot"
2763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2764 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2765 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2766 (const_int 0)))
2767 (clobber (match_scratch:GPR 0 "=r,r"))]
2768 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2769 "@
2770 mull<wd>. %0,%1,%2
2771 #"
2772 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2773 [(set (match_dup 0)
2774 (mult:GPR (match_dup 1)
2775 (match_dup 2)))
2776 (set (match_dup 3)
2777 (compare:CC (match_dup 0)
2778 (const_int 0)))]
2779 ""
2780 [(set_attr "type" "mul")
2781 (set_attr "size" "<bits>")
2782 (set_attr "dot" "yes")
2783 (set_attr "length" "4,8")])
2785 (define_insn_and_split "*mul<mode>3_dot2"
2786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2787 (compare:CC (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2788 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
2789 (const_int 0)))
2790 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2791 (mult:GPR (match_dup 1)
2792 (match_dup 2)))]
2793 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
2794 "@
2795 mull<wd>. %0,%1,%2
2796 #"
2797 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2798 [(set (match_dup 0)
2799 (mult:GPR (match_dup 1)
2800 (match_dup 2)))
2801 (set (match_dup 3)
2802 (compare:CC (match_dup 0)
2803 (const_int 0)))]
2804 ""
2805 [(set_attr "type" "mul")
2806 (set_attr "size" "<bits>")
2807 (set_attr "dot" "yes")
2808 (set_attr "length" "4,8")])
2811 (define_expand "<su>mul<mode>3_highpart"
2812 [(set (match_operand:GPR 0 "gpc_reg_operand")
2813 (subreg:GPR
2814 (mult:<DMODE> (any_extend:<DMODE>
2815 (match_operand:GPR 1 "gpc_reg_operand"))
2816 (any_extend:<DMODE>
2817 (match_operand:GPR 2 "gpc_reg_operand")))
2818 0))]
2819 ""
2820 {
2821 if (<MODE>mode == SImode && TARGET_POWERPC64)
2822 {
2823 emit_insn (gen_<su>mulsi3_highpart_64 (operands[0], operands[1],
2824 operands[2]));
2825 DONE;
2826 }
2828 if (!WORDS_BIG_ENDIAN)
2829 {
2830 emit_insn (gen_<su>mul<mode>3_highpart_le (operands[0], operands[1],
2831 operands[2]));
2832 DONE;
2833 }
2834 })
2836 (define_insn "*<su>mul<mode>3_highpart"
2837 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2838 (subreg:GPR
2839 (mult:<DMODE> (any_extend:<DMODE>
2840 (match_operand:GPR 1 "gpc_reg_operand" "r"))
2841 (any_extend:<DMODE>
2842 (match_operand:GPR 2 "gpc_reg_operand" "r")))
2843 0))]
2844 "WORDS_BIG_ENDIAN && !(<MODE>mode == SImode && TARGET_POWERPC64)"
2845 "mulh<wd><u> %0,%1,%2"
2846 [(set_attr "type" "mul")
2847 (set_attr "size" "<bits>")])
2849 (define_insn "<su>mulsi3_highpart_le"
2850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2851 (subreg:SI
2852 (mult:DI (any_extend:DI
2853 (match_operand:SI 1 "gpc_reg_operand" "r"))
2854 (any_extend:DI
2855 (match_operand:SI 2 "gpc_reg_operand" "r")))
2856 4))]
2857 "!WORDS_BIG_ENDIAN && !TARGET_POWERPC64"
2858 "mulhw<u> %0,%1,%2"
2859 [(set_attr "type" "mul")])
2861 (define_insn "<su>muldi3_highpart_le"
2862 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2863 (subreg:DI
2864 (mult:TI (any_extend:TI
2865 (match_operand:DI 1 "gpc_reg_operand" "r"))
2866 (any_extend:TI
2867 (match_operand:DI 2 "gpc_reg_operand" "r")))
2868 8))]
2869 "!WORDS_BIG_ENDIAN && TARGET_POWERPC64"
2870 "mulhd<u> %0,%1,%2"
2871 [(set_attr "type" "mul")
2872 (set_attr "size" "64")])
2874 (define_insn "<su>mulsi3_highpart_64"
2875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2876 (truncate:SI
2877 (lshiftrt:DI
2878 (mult:DI (any_extend:DI
2879 (match_operand:SI 1 "gpc_reg_operand" "r"))
2880 (any_extend:DI
2881 (match_operand:SI 2 "gpc_reg_operand" "r")))
2882 (const_int 32))))]
2883 "TARGET_POWERPC64"
2884 "mulhw<u> %0,%1,%2"
2885 [(set_attr "type" "mul")])
2887 (define_expand "<u>mul<mode><dmode>3"
2888 [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
2889 (mult:<DMODE> (any_extend:<DMODE>
2890 (match_operand:GPR 1 "gpc_reg_operand"))
2891 (any_extend:<DMODE>
2892 (match_operand:GPR 2 "gpc_reg_operand"))))]
2893 "!(<MODE>mode == SImode && TARGET_POWERPC64)"
2894 {
2895 rtx l = gen_reg_rtx (<MODE>mode);
2896 rtx h = gen_reg_rtx (<MODE>mode);
2897 emit_insn (gen_mul<mode>3 (l, operands[1], operands[2]));
2898 emit_insn (gen_<su>mul<mode>3_highpart (h, operands[1], operands[2]));
2899 emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
2900 emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
2901 DONE;
2902 })
2904 (define_insn "*maddld4"
2905 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2906 (plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2907 (match_operand:DI 2 "gpc_reg_operand" "r"))
2908 (match_operand:DI 3 "gpc_reg_operand" "r")))]
2909 "TARGET_MADDLD"
2910 "maddld %0,%1,%2,%3"
2911 [(set_attr "type" "mul")])
2913 (define_insn "udiv<mode>3"
2914 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2915 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2916 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2917 ""
2918 "div<wd>u %0,%1,%2"
2919 [(set_attr "type" "div")
2920 (set_attr "size" "<bits>")])
2923 ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for
2924 ;; modulus. If it isn't a power of two, force operands into register and do
2925 ;; a normal divide.
2926 (define_expand "div<mode>3"
2927 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2928 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2929 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2930 ""
2931 {
2932 if (CONST_INT_P (operands[2])
2933 && INTVAL (operands[2]) > 0
2934 && exact_log2 (INTVAL (operands[2])) >= 0)
2935 {
2936 emit_insn (gen_div<mode>3_sra (operands[0], operands[1], operands[2]));
2937 DONE;
2938 }
2940 operands[2] = force_reg (<MODE>mode, operands[2]);
2941 })
2943 (define_insn "*div<mode>3"
2944 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2945 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2946 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2947 ""
2948 "div<wd> %0,%1,%2"
2949 [(set_attr "type" "div")
2950 (set_attr "size" "<bits>")])
2952 (define_insn "div<mode>3_sra"
2953 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2954 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2955 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))
2956 (clobber (reg:GPR CA_REGNO))]
2957 ""
2958 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2959 [(set_attr "type" "two")
2960 (set_attr "length" "8")])
2962 (define_insn_and_split "*div<mode>3_sra_dot"
2963 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2964 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2965 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2966 (const_int 0)))
2967 (clobber (match_scratch:GPR 0 "=r,r"))
2968 (clobber (reg:GPR CA_REGNO))]
2969 "<MODE>mode == Pmode"
2970 "@
2971 sra<wd>i %0,%1,%p2\;addze. %0,%0
2972 #"
2973 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
2974 [(parallel [(set (match_dup 0)
2975 (div:GPR (match_dup 1)
2976 (match_dup 2)))
2977 (clobber (reg:GPR CA_REGNO))])
2978 (set (match_dup 3)
2979 (compare:CC (match_dup 0)
2980 (const_int 0)))]
2981 ""
2982 [(set_attr "type" "two")
2983 (set_attr "length" "8,12")
2984 (set_attr "cell_micro" "not")])
2986 (define_insn_and_split "*div<mode>3_sra_dot2"
2987 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2988 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
2989 (match_operand:GPR 2 "exact_log2_cint_operand" "N,N"))
2990 (const_int 0)))
2991 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
2992 (div:GPR (match_dup 1)
2993 (match_dup 2)))
2994 (clobber (reg:GPR CA_REGNO))]
2995 "<MODE>mode == Pmode"
2996 "@
2997 sra<wd>i %0,%1,%p2\;addze. %0,%0
2998 #"
2999 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3000 [(parallel [(set (match_dup 0)
3001 (div:GPR (match_dup 1)
3002 (match_dup 2)))
3003 (clobber (reg:GPR CA_REGNO))])
3004 (set (match_dup 3)
3005 (compare:CC (match_dup 0)
3006 (const_int 0)))]
3007 ""
3008 [(set_attr "type" "two")
3009 (set_attr "length" "8,12")
3010 (set_attr "cell_micro" "not")])
3012 (define_expand "mod<mode>3"
3013 [(set (match_operand:GPR 0 "gpc_reg_operand")
3014 (mod:GPR (match_operand:GPR 1 "gpc_reg_operand")
3015 (match_operand:GPR 2 "reg_or_cint_operand")))]
3016 ""
3017 {
3018 int i;
3019 rtx temp1;
3020 rtx temp2;
3022 if (GET_CODE (operands[2]) != CONST_INT
3023 || INTVAL (operands[2]) <= 0
3024 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3025 {
3026 if (!TARGET_MODULO)
3027 FAIL;
3029 operands[2] = force_reg (<MODE>mode, operands[2]);
3030 }
3031 else
3032 {
3033 temp1 = gen_reg_rtx (<MODE>mode);
3034 temp2 = gen_reg_rtx (<MODE>mode);
3036 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3037 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3038 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3039 DONE;
3040 }
3041 })
3043 ;; In order to enable using a peephole2 for combining div/mod to eliminate the
3044 ;; mod, prefer putting the result of mod into a different register
3045 (define_insn "*mod<mode>3"
3046 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
3047 (mod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3048 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3049 "TARGET_MODULO"
3050 "mods<wd> %0,%1,%2"
3051 [(set_attr "type" "div")
3052 (set_attr "size" "<bits>")])
3055 (define_insn "umod<mode>3"
3056 [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
3057 (umod:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3058 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
3059 "TARGET_MODULO"
3060 "modu<wd> %0,%1,%2"
3061 [(set_attr "type" "div")
3062 (set_attr "size" "<bits>")])
3064 ;; On machines with modulo support, do a combined div/mod the old fashioned
3065 ;; method, since the multiply/subtract is faster than doing the mod instruction
3066 ;; after a divide.
3068 (define_peephole2
3069 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3070 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3071 (match_operand:GPR 2 "gpc_reg_operand" "")))
3072 (set (match_operand:GPR 3 "gpc_reg_operand" "")
3073 (mod:GPR (match_dup 1)
3074 (match_dup 2)))]
3075 "TARGET_MODULO
3076 && ! reg_mentioned_p (operands[0], operands[1])
3077 && ! reg_mentioned_p (operands[0], operands[2])
3078 && ! reg_mentioned_p (operands[3], operands[1])
3079 && ! reg_mentioned_p (operands[3], operands[2])"
3080 [(set (match_dup 0)
3081 (div:GPR (match_dup 1)
3082 (match_dup 2)))
3083 (set (match_dup 3)
3084 (mult:GPR (match_dup 0)
3085 (match_dup 2)))
3086 (set (match_dup 3)
3087 (minus:GPR (match_dup 1)
3088 (match_dup 3)))])
3090 (define_peephole2
3091 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3092 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3093 (match_operand:GPR 2 "gpc_reg_operand" "")))
3094 (set (match_operand:GPR 3 "gpc_reg_operand" "")
3095 (umod:GPR (match_dup 1)
3096 (match_dup 2)))]
3097 "TARGET_MODULO
3098 && ! reg_mentioned_p (operands[0], operands[1])
3099 && ! reg_mentioned_p (operands[0], operands[2])
3100 && ! reg_mentioned_p (operands[3], operands[1])
3101 && ! reg_mentioned_p (operands[3], operands[2])"
3102 [(set (match_dup 0)
3103 (div:GPR (match_dup 1)
3104 (match_dup 2)))
3105 (set (match_dup 3)
3106 (mult:GPR (match_dup 0)
3107 (match_dup 2)))
3108 (set (match_dup 3)
3109 (minus:GPR (match_dup 1)
3110 (match_dup 3)))])
3112 \f
3113 ;; Logical instructions
3114 ;; The logical instructions are mostly combined by using match_operator,
3115 ;; but the plain AND insns are somewhat different because there is no
3116 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3117 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3119 (define_expand "and<mode>3"
3120 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
3121 (and:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
3122 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
3123 ""
3124 {
3125 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3126 {
3127 rs6000_split_logical (operands, AND, false, false, false);
3128 DONE;
3129 }
3131 if (CONST_INT_P (operands[2]))
3132 {
3133 if (rs6000_is_valid_and_mask (operands[2], <MODE>mode))
3134 {
3135 emit_insn (gen_and<mode>3_mask (operands[0], operands[1], operands[2]));
3136 DONE;
3137 }
3139 if (logical_const_operand (operands[2], <MODE>mode)
3140 && rs6000_gen_cell_microcode)
3141 {
3142 emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
3143 DONE;
3144 }
3146 if (rs6000_is_valid_2insn_and (operands[2], <MODE>mode))
3147 {
3148 rs6000_emit_2insn_and (<MODE>mode, operands, true, 0);
3149 DONE;
3150 }
3152 operands[2] = force_reg (<MODE>mode, operands[2]);
3153 }
3154 })
3157 (define_insn "and<mode>3_imm"
3158 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3159 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
3160 (match_operand:GPR 2 "logical_const_operand" "n")))
3161 (clobber (match_scratch:CC 3 "=x"))]
3162 "rs6000_gen_cell_microcode
3163 && !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3164 "andi%e2. %0,%1,%u2"
3165 [(set_attr "type" "logical")
3166 (set_attr "dot" "yes")])
3168 (define_insn_and_split "*and<mode>3_imm_dot"
3169 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3170 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3171 (match_operand:GPR 2 "logical_const_operand" "n,n"))
3172 (const_int 0)))
3173 (clobber (match_scratch:GPR 0 "=r,r"))
3174 (clobber (match_scratch:CC 4 "=X,x"))]
3175 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3176 && rs6000_gen_cell_microcode
3177 && !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3178 "@
3179 andi%e2. %0,%1,%u2
3180 #"
3181 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3182 [(parallel [(set (match_dup 0)
3183 (and:GPR (match_dup 1)
3184 (match_dup 2)))
3185 (clobber (match_dup 4))])
3186 (set (match_dup 3)
3187 (compare:CC (match_dup 0)
3188 (const_int 0)))]
3189 ""
3190 [(set_attr "type" "logical")
3191 (set_attr "dot" "yes")
3192 (set_attr "length" "4,8")])
3194 (define_insn_and_split "*and<mode>3_imm_dot2"
3195 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3196 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3197 (match_operand:GPR 2 "logical_const_operand" "n,n"))
3198 (const_int 0)))
3199 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3200 (and:GPR (match_dup 1)
3201 (match_dup 2)))
3202 (clobber (match_scratch:CC 4 "=X,x"))]
3203 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3204 && rs6000_gen_cell_microcode
3205 && !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3206 "@
3207 andi%e2. %0,%1,%u2
3208 #"
3209 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3210 [(parallel [(set (match_dup 0)
3211 (and:GPR (match_dup 1)
3212 (match_dup 2)))
3213 (clobber (match_dup 4))])
3214 (set (match_dup 3)
3215 (compare:CC (match_dup 0)
3216 (const_int 0)))]
3217 ""
3218 [(set_attr "type" "logical")
3219 (set_attr "dot" "yes")
3220 (set_attr "length" "4,8")])
3222 (define_insn_and_split "*and<mode>3_imm_mask_dot"
3223 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3224 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3225 (match_operand:GPR 2 "logical_const_operand" "n,n"))
3226 (const_int 0)))
3227 (clobber (match_scratch:GPR 0 "=r,r"))]
3228 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3229 && rs6000_gen_cell_microcode"
3230 "@
3231 andi%e2. %0,%1,%u2
3232 #"
3233 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3234 [(set (match_dup 0)
3235 (and:GPR (match_dup 1)
3236 (match_dup 2)))
3237 (set (match_dup 3)
3238 (compare:CC (match_dup 0)
3239 (const_int 0)))]
3240 ""
3241 [(set_attr "type" "logical")
3242 (set_attr "dot" "yes")
3243 (set_attr "length" "4,8")])
3245 (define_insn_and_split "*and<mode>3_imm_mask_dot2"
3246 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3247 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3248 (match_operand:GPR 2 "logical_const_operand" "n,n"))
3249 (const_int 0)))
3250 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3251 (and:GPR (match_dup 1)
3252 (match_dup 2)))]
3253 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3254 && rs6000_gen_cell_microcode"
3255 "@
3256 andi%e2. %0,%1,%u2
3257 #"
3258 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3259 [(set (match_dup 0)
3260 (and:GPR (match_dup 1)
3261 (match_dup 2)))
3262 (set (match_dup 3)
3263 (compare:CC (match_dup 0)
3264 (const_int 0)))]
3265 ""
3266 [(set_attr "type" "logical")
3267 (set_attr "dot" "yes")
3268 (set_attr "length" "4,8")])
3270 (define_insn "*and<mode>3_imm_dot_shifted"
3271 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3272 (compare:CC
3273 (and:GPR
3274 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
3275 (match_operand:SI 4 "const_int_operand" "n"))
3276 (match_operand:GPR 2 "const_int_operand" "n"))
3277 (const_int 0)))
3278 (clobber (match_scratch:GPR 0 "=r"))]
3279 "logical_const_operand (GEN_INT (UINTVAL (operands[2])
3280 << INTVAL (operands[4])),
3281 DImode)
3282 && (<MODE>mode == Pmode
3283 || (UINTVAL (operands[2]) << INTVAL (operands[4])) <= 0x7fffffff)
3284 && rs6000_gen_cell_microcode"
3285 {
3286 operands[2] = GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4]));
3287 return "andi%e2. %0,%1,%u2";
3288 }
3289 [(set_attr "type" "logical")
3290 (set_attr "dot" "yes")])
3293 (define_insn "and<mode>3_mask"
3294 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3295 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
3296 (match_operand:GPR 2 "const_int_operand" "n")))]
3297 "rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3298 {
3299 return rs6000_insn_for_and_mask (<MODE>mode, operands, false);
3300 }
3301 [(set_attr "type" "shift")])
3303 (define_insn_and_split "*and<mode>3_mask_dot"
3304 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3305 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3306 (match_operand:GPR 2 "const_int_operand" "n,n"))
3307 (const_int 0)))
3308 (clobber (match_scratch:GPR 0 "=r,r"))]
3309 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3310 && rs6000_gen_cell_microcode
3311 && !logical_const_operand (operands[2], <MODE>mode)
3312 && rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3313 {
3314 if (which_alternative == 0)
3315 return rs6000_insn_for_and_mask (<MODE>mode, operands, true);
3316 else
3317 return "#";
3318 }
3319 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3320 [(set (match_dup 0)
3321 (and:GPR (match_dup 1)
3322 (match_dup 2)))
3323 (set (match_dup 3)
3324 (compare:CC (match_dup 0)
3325 (const_int 0)))]
3326 ""
3327 [(set_attr "type" "shift")
3328 (set_attr "dot" "yes")
3329 (set_attr "length" "4,8")])
3331 (define_insn_and_split "*and<mode>3_mask_dot2"
3332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3333 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3334 (match_operand:GPR 2 "const_int_operand" "n,n"))
3335 (const_int 0)))
3336 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3337 (and:GPR (match_dup 1)
3338 (match_dup 2)))]
3339 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3340 && rs6000_gen_cell_microcode
3341 && !logical_const_operand (operands[2], <MODE>mode)
3342 && rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
3343 {
3344 if (which_alternative == 0)
3345 return rs6000_insn_for_and_mask (<MODE>mode, operands, true);
3346 else
3347 return "#";
3348 }
3349 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3350 [(set (match_dup 0)
3351 (and:GPR (match_dup 1)
3352 (match_dup 2)))
3353 (set (match_dup 3)
3354 (compare:CC (match_dup 0)
3355 (const_int 0)))]
3356 ""
3357 [(set_attr "type" "shift")
3358 (set_attr "dot" "yes")
3359 (set_attr "length" "4,8")])
3362 (define_insn_and_split "*and<mode>3_2insn"
3363 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3364 (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
3365 (match_operand:GPR 2 "const_int_operand" "n")))]
3366 "rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
3367 && !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
3368 || (logical_const_operand (operands[2], <MODE>mode)
3369 && rs6000_gen_cell_microcode))"
3370 "#"
3371 "&& 1"
3372 [(pc)]
3373 {
3374 rs6000_emit_2insn_and (<MODE>mode, operands, false, 0);
3375 DONE;
3376 }
3377 [(set_attr "type" "shift")
3378 (set_attr "length" "8")])
3380 (define_insn_and_split "*and<mode>3_2insn_dot"
3381 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3382 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3383 (match_operand:GPR 2 "const_int_operand" "n,n"))
3384 (const_int 0)))
3385 (clobber (match_scratch:GPR 0 "=r,r"))]
3386 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3387 && rs6000_gen_cell_microcode
3388 && rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
3389 && !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
3390 || (logical_const_operand (operands[2], <MODE>mode)
3391 && rs6000_gen_cell_microcode))"
3392 "#"
3393 "&& reload_completed"
3394 [(pc)]
3395 {
3396 rs6000_emit_2insn_and (<MODE>mode, operands, false, 1);
3397 DONE;
3398 }
3399 [(set_attr "type" "shift")
3400 (set_attr "dot" "yes")
3401 (set_attr "length" "8,12")])
3403 (define_insn_and_split "*and<mode>3_2insn_dot2"
3404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3405 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
3406 (match_operand:GPR 2 "const_int_operand" "n,n"))
3407 (const_int 0)))
3408 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3409 (and:GPR (match_dup 1)
3410 (match_dup 2)))]
3411 "(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
3412 && rs6000_gen_cell_microcode
3413 && rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
3414 && !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
3415 || (logical_const_operand (operands[2], <MODE>mode)
3416 && rs6000_gen_cell_microcode))"
3417 "#"
3418 "&& reload_completed"
3419 [(pc)]
3420 {
3421 rs6000_emit_2insn_and (<MODE>mode, operands, false, 2);
3422 DONE;
3423 }
3424 [(set_attr "type" "shift")
3425 (set_attr "dot" "yes")
3426 (set_attr "length" "8,12")])
3429 (define_expand "<code><mode>3"
3430 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
3431 (iorxor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
3432 (match_operand:SDI 2 "reg_or_cint_operand" "")))]
3433 ""
3434 {
3435 if (<MODE>mode == DImode && !TARGET_POWERPC64)
3436 {
3437 rs6000_split_logical (operands, <CODE>, false, false, false);
3438 DONE;
3439 }
3441 if (non_logical_cint_operand (operands[2], <MODE>mode))
3442 {
3443 rtx tmp = ((!can_create_pseudo_p ()
3444 || rtx_equal_p (operands[0], operands[1]))
3445 ? operands[0] : gen_reg_rtx (<MODE>mode));
3447 HOST_WIDE_INT value = INTVAL (operands[2]);
3448 HOST_WIDE_INT lo = value & 0xffff;
3449 HOST_WIDE_INT hi = value - lo;
3451 emit_insn (gen_<code><mode>3 (tmp, operands[1], GEN_INT (hi)));
3452 emit_insn (gen_<code><mode>3 (operands[0], tmp, GEN_INT (lo)));
3453 DONE;
3454 }
3456 if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
3457 operands[2] = force_reg (<MODE>mode, operands[2]);
3458 })
3460 (define_split
3461 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
3462 (iorxor:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3463 (match_operand:GPR 2 "non_logical_cint_operand" "")))]
3464 ""
3465 [(set (match_dup 3)
3466 (iorxor:GPR (match_dup 1)
3467 (match_dup 4)))
3468 (set (match_dup 0)
3469 (iorxor:GPR (match_dup 3)
3470 (match_dup 5)))]
3471 {
3472 operands[3] = ((!can_create_pseudo_p ()
3473 || rtx_equal_p (operands[0], operands[1]))
3474 ? operands[0] : gen_reg_rtx (<MODE>mode));
3476 HOST_WIDE_INT value = INTVAL (operands[2]);
3477 HOST_WIDE_INT lo = value & 0xffff;
3478 HOST_WIDE_INT hi = value - lo;
3480 operands[4] = GEN_INT (hi);
3481 operands[5] = GEN_INT (lo);
3482 })
3484 (define_insn "*bool<mode>3_imm"
3485 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3486 (match_operator:GPR 3 "boolean_or_operator"
3487 [(match_operand:GPR 1 "gpc_reg_operand" "%r")
3488 (match_operand:GPR 2 "logical_const_operand" "n")]))]
3489 ""
3490 "%q3i%e2 %0,%1,%u2"
3491 [(set_attr "type" "logical")])
3493 (define_insn "*bool<mode>3"
3494 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3495 (match_operator:GPR 3 "boolean_operator"
3496 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3497 (match_operand:GPR 2 "gpc_reg_operand" "r")]))]
3498 ""
3499 "%q3 %0,%1,%2"
3500 [(set_attr "type" "logical")])
3502 (define_insn_and_split "*bool<mode>3_dot"
3503 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3504 (compare:CC (match_operator:GPR 3 "boolean_operator"
3505 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3506 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3507 (const_int 0)))
3508 (clobber (match_scratch:GPR 0 "=r,r"))]
3509 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3510 "@
3511 %q3. %0,%1,%2
3512 #"
3513 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3514 [(set (match_dup 0)
3515 (match_dup 3))
3516 (set (match_dup 4)
3517 (compare:CC (match_dup 0)
3518 (const_int 0)))]
3519 ""
3520 [(set_attr "type" "logical")
3521 (set_attr "dot" "yes")
3522 (set_attr "length" "4,8")])
3524 (define_insn_and_split "*bool<mode>3_dot2"
3525 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3526 (compare:CC (match_operator:GPR 3 "boolean_operator"
3527 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3528 (match_operand:GPR 2 "gpc_reg_operand" "r,r")])
3529 (const_int 0)))
3530 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3531 (match_dup 3))]
3532 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3533 "@
3534 %q3. %0,%1,%2
3535 #"
3536 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3537 [(set (match_dup 0)
3538 (match_dup 3))
3539 (set (match_dup 4)
3540 (compare:CC (match_dup 0)
3541 (const_int 0)))]
3542 ""
3543 [(set_attr "type" "logical")
3544 (set_attr "dot" "yes")
3545 (set_attr "length" "4,8")])
3548 (define_insn "*boolc<mode>3"
3549 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3550 (match_operator:GPR 3 "boolean_operator"
3551 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))
3552 (match_operand:GPR 1 "gpc_reg_operand" "r")]))]
3553 ""
3554 "%q3 %0,%1,%2"
3555 [(set_attr "type" "logical")])
3557 (define_insn_and_split "*boolc<mode>3_dot"
3558 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3559 (compare:CC (match_operator:GPR 3 "boolean_operator"
3560 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3561 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3562 (const_int 0)))
3563 (clobber (match_scratch:GPR 0 "=r,r"))]
3564 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3565 "@
3566 %q3. %0,%1,%2
3567 #"
3568 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3569 [(set (match_dup 0)
3570 (match_dup 3))
3571 (set (match_dup 4)
3572 (compare:CC (match_dup 0)
3573 (const_int 0)))]
3574 ""
3575 [(set_attr "type" "logical")
3576 (set_attr "dot" "yes")
3577 (set_attr "length" "4,8")])
3579 (define_insn_and_split "*boolc<mode>3_dot2"
3580 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3581 (compare:CC (match_operator:GPR 3 "boolean_operator"
3582 [(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
3583 (match_operand:GPR 1 "gpc_reg_operand" "r,r")])
3584 (const_int 0)))
3585 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3586 (match_dup 3))]
3587 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3588 "@
3589 %q3. %0,%1,%2
3590 #"
3591 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3592 [(set (match_dup 0)
3593 (match_dup 3))
3594 (set (match_dup 4)
3595 (compare:CC (match_dup 0)
3596 (const_int 0)))]
3597 ""
3598 [(set_attr "type" "logical")
3599 (set_attr "dot" "yes")
3600 (set_attr "length" "4,8")])
3603 (define_insn "*boolcc<mode>3"
3604 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3605 (match_operator:GPR 3 "boolean_operator"
3606 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
3607 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
3608 ""
3609 "%q3 %0,%1,%2"
3610 [(set_attr "type" "logical")])
3612 (define_insn_and_split "*boolcc<mode>3_dot"
3613 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3614 (compare:CC (match_operator:GPR 3 "boolean_operator"
3615 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3616 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3617 (const_int 0)))
3618 (clobber (match_scratch:GPR 0 "=r,r"))]
3619 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3620 "@
3621 %q3. %0,%1,%2
3622 #"
3623 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3624 [(set (match_dup 0)
3625 (match_dup 3))
3626 (set (match_dup 4)
3627 (compare:CC (match_dup 0)
3628 (const_int 0)))]
3629 ""
3630 [(set_attr "type" "logical")
3631 (set_attr "dot" "yes")
3632 (set_attr "length" "4,8")])
3634 (define_insn_and_split "*boolcc<mode>3_dot2"
3635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3636 (compare:CC (match_operator:GPR 3 "boolean_operator"
3637 [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
3638 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
3639 (const_int 0)))
3640 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3641 (match_dup 3))]
3642 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3643 "@
3644 %q3. %0,%1,%2
3645 #"
3646 "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
3647 [(set (match_dup 0)
3648 (match_dup 3))
3649 (set (match_dup 4)
3650 (compare:CC (match_dup 0)
3651 (const_int 0)))]
3652 ""
3653 [(set_attr "type" "logical")
3654 (set_attr "dot" "yes")
3655 (set_attr "length" "4,8")])
3658 ;; TODO: Should have dots of this as well.
3659 (define_insn "*eqv<mode>3"
3660 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3661 (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3662 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
3663 ""
3664 "eqv %0,%1,%2"
3665 [(set_attr "type" "logical")])
3666 \f
3667 ;; Rotate-and-mask and insert.
3669 (define_insn "*rotl<mode>3_mask"
3670 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3671 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
3672 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3673 (match_operand:SI 2 "reg_or_cint_operand" "rn")])
3674 (match_operand:GPR 3 "const_int_operand" "n")))]
3675 "rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
3676 {
3677 return rs6000_insn_for_shift_mask (<MODE>mode, operands, false);
3678 }
3679 [(set_attr "type" "shift")
3680 (set_attr "maybe_var_shift" "yes")])
3682 (define_insn_and_split "*rotl<mode>3_mask_dot"
3683 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
3684 (compare:CC
3685 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
3686 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3687 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
3688 (match_operand:GPR 3 "const_int_operand" "n,n"))
3689 (const_int 0)))
3690 (clobber (match_scratch:GPR 0 "=r,r"))]
3691 "(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
3692 && rs6000_gen_cell_microcode
3693 && rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
3694 {
3695 if (which_alternative == 0)
3696 return rs6000_insn_for_shift_mask (<MODE>mode, operands, true);
3697 else
3698 return "#";
3699 }
3700 "&& reload_completed && cc_reg_not_cr0_operand (operands[5], CCmode)"
3701 [(set (match_dup 0)
3702 (and:GPR (match_dup 4)
3703 (match_dup 3)))
3704 (set (match_dup 5)
3705 (compare:CC (match_dup 0)
3706 (const_int 0)))]
3707 ""
3708 [(set_attr "type" "shift")
3709 (set_attr "maybe_var_shift" "yes")
3710 (set_attr "dot" "yes")
3711 (set_attr "length" "4,8")])
3713 (define_insn_and_split "*rotl<mode>3_mask_dot2"
3714 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
3715 (compare:CC
3716 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
3717 [(match_operand:GPR 1 "gpc_reg_operand" "r,r")
3718 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")])
3719 (match_operand:GPR 3 "const_int_operand" "n,n"))
3720 (const_int 0)))
3721 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3722 (and:GPR (match_dup 4)
3723 (match_dup 3)))]
3724 "(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
3725 && rs6000_gen_cell_microcode
3726 && rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
3727 {
3728 if (which_alternative == 0)
3729 return rs6000_insn_for_shift_mask (<MODE>mode, operands, true);
3730 else
3731 return "#";
3732 }
3733 "&& reload_completed && cc_reg_not_cr0_operand (operands[5], CCmode)"
3734 [(set (match_dup 0)
3735 (and:GPR (match_dup 4)
3736 (match_dup 3)))
3737 (set (match_dup 5)
3738 (compare:CC (match_dup 0)
3739 (const_int 0)))]
3740 ""
3741 [(set_attr "type" "shift")
3742 (set_attr "maybe_var_shift" "yes")
3743 (set_attr "dot" "yes")
3744 (set_attr "length" "4,8")])
3746 ; Special case for less-than-0. We can do it with just one machine
3747 ; instruction, but the generic optimizers do not realise it is cheap.
3748 (define_insn "*lt0_disi"
3749 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3750 (lt:DI (match_operand:SI 1 "gpc_reg_operand" "r")
3751 (const_int 0)))]
3752 "TARGET_POWERPC64"
3753 "rlwinm %0,%1,1,31,31"
3754 [(set_attr "type" "shift")])
3758 ; Two forms for insert (the two arms of the IOR are not canonicalized,
3759 ; both are an AND so are the same precedence).
3760 (define_insn "*rotl<mode>3_insert"
3761 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3762 (ior:GPR (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
3763 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3764 (match_operand:SI 2 "const_int_operand" "n")])
3765 (match_operand:GPR 3 "const_int_operand" "n"))
3766 (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0")
3767 (match_operand:GPR 6 "const_int_operand" "n"))))]
3768 "rs6000_is_valid_insert_mask (operands[3], operands[4], <MODE>mode)
3769 && UINTVAL (operands[3]) + UINTVAL (operands[6]) + 1 == 0"
3770 {
3771 return rs6000_insn_for_insert_mask (<MODE>mode, operands, false);
3772 }
3773 [(set_attr "type" "insert")])
3774 ; FIXME: this needs an attr "size", so that the scheduler can see the
3775 ; difference between rlwimi and rldimi. We also might want dot forms,
3776 ; but not for rlwimi on POWER4 and similar processors.
3778 (define_insn "*rotl<mode>3_insert_2"
3779 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3780 (ior:GPR (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0")
3781 (match_operand:GPR 6 "const_int_operand" "n"))
3782 (and:GPR (match_operator:GPR 4 "rotate_mask_operator"
3783 [(match_operand:GPR 1 "gpc_reg_operand" "r")
3784 (match_operand:SI 2 "const_int_operand" "n")])
3785 (match_operand:GPR 3 "const_int_operand" "n"))))]
3786 "rs6000_is_valid_insert_mask (operands[3], operands[4], <MODE>mode)
3787 && UINTVAL (operands[3]) + UINTVAL (operands[6]) + 1 == 0"
3788 {
3789 return rs6000_insn_for_insert_mask (<MODE>mode, operands, false);
3790 }
3791 [(set_attr "type" "insert")])
3793 ; There are also some forms without one of the ANDs.
3794 (define_insn "*rotl<mode>3_insert_3"
3795 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3796 (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
3797 (match_operand:GPR 4 "const_int_operand" "n"))
3798 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3799 (match_operand:SI 2 "const_int_operand" "n"))))]
3800 "INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)"
3801 {
3802 if (<MODE>mode == SImode)
3803 return "rlwimi %0,%1,%h2,0,31-%h2";
3804 else
3805 return "rldimi %0,%1,%H2,0";
3806 }
3807 [(set_attr "type" "insert")])
3809 (define_insn "*rotl<mode>3_insert_4"
3810 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3811 (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0")
3812 (match_operand:GPR 4 "const_int_operand" "n"))
3813 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3814 (match_operand:SI 2 "const_int_operand" "n"))))]
3815 "<MODE>mode == SImode &&
3816 GET_MODE_PRECISION (<MODE>mode)
3817 == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))"
3818 {
3819 operands[2] = GEN_INT (GET_MODE_PRECISION (<MODE>mode)
3820 - INTVAL (operands[2]));
3821 if (<MODE>mode == SImode)
3822 return "rlwimi %0,%1,%h2,32-%h2,31";
3823 else
3824 return "rldimi %0,%1,%H2,64-%H2";
3825 }
3826 [(set_attr "type" "insert")])
3829 ; This handles the important case of multiple-precision shifts. There is
3830 ; no canonicalization rule for ASHIFT vs. LSHIFTRT, so two patterns.
3831 (define_split
3832 [(set (match_operand:GPR 0 "gpc_reg_operand")
3833 (ior:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
3834 (match_operand:SI 3 "const_int_operand"))
3835 (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
3836 (match_operand:SI 4 "const_int_operand"))))]
3837 "can_create_pseudo_p ()
3838 && INTVAL (operands[3]) + INTVAL (operands[4])
3839 >= GET_MODE_PRECISION (<MODE>mode)"
3840 [(set (match_dup 5)
3841 (lshiftrt:GPR (match_dup 2)
3842 (match_dup 4)))
3843 (set (match_dup 0)
3844 (ior:GPR (and:GPR (match_dup 5)
3845 (match_dup 6))
3846 (ashift:GPR (match_dup 1)
3847 (match_dup 3))))]
3848 {
3849 unsigned HOST_WIDE_INT mask = 1;
3850 mask = (mask << INTVAL (operands[3])) - 1;
3851 operands[5] = gen_reg_rtx (<MODE>mode);
3852 operands[6] = GEN_INT (mask);
3853 })
3855 (define_split
3856 [(set (match_operand:GPR 0 "gpc_reg_operand")
3857 (ior:GPR (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand")
3858 (match_operand:SI 4 "const_int_operand"))
3859 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand")
3860 (match_operand:SI 3 "const_int_operand"))))]
3861 "can_create_pseudo_p ()
3862 && INTVAL (operands[3]) + INTVAL (operands[4])
3863 >= GET_MODE_PRECISION (<MODE>mode)"
3864 [(set (match_dup 5)
3865 (lshiftrt:GPR (match_dup 2)
3866 (match_dup 4)))
3867 (set (match_dup 0)
3868 (ior:GPR (and:GPR (match_dup 5)
3869 (match_dup 6))
3870 (ashift:GPR (match_dup 1)
3871 (match_dup 3))))]
3872 {
3873 unsigned HOST_WIDE_INT mask = 1;
3874 mask = (mask << INTVAL (operands[3])) - 1;
3875 operands[5] = gen_reg_rtx (<MODE>mode);
3876 operands[6] = GEN_INT (mask);
3877 })
3880 ; Another important case is setting some bits to 1; we can do that with
3881 ; an insert instruction, in many cases.
3882 (define_insn_and_split "*ior<mode>_mask"
3883 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3884 (ior:GPR (match_operand:GPR 1 "gpc_reg_operand" "0")
3885 (match_operand:GPR 2 "const_int_operand" "n")))
3886 (clobber (match_scratch:GPR 3 "=r"))]
3887 "!logical_const_operand (operands[2], <MODE>mode)
3888 && rs6000_is_valid_mask (operands[2], NULL, NULL, <MODE>mode)"
3889 "#"
3890 "&& 1"
3891 [(set (match_dup 3)
3892 (const_int -1))
3893 (set (match_dup 0)
3894 (ior:GPR (and:GPR (rotate:GPR (match_dup 3)
3895 (match_dup 4))
3896 (match_dup 2))
3897 (and:GPR (match_dup 1)
3898 (match_dup 5))))]
3899 {
3900 int nb, ne;
3901 rs6000_is_valid_mask (operands[2], &nb, &ne, <MODE>mode);
3902 if (GET_CODE (operands[3]) == SCRATCH)
3903 operands[3] = gen_reg_rtx (<MODE>mode);
3904 operands[4] = GEN_INT (ne);
3905 operands[5] = GEN_INT (~UINTVAL (operands[2]));
3906 }
3907 [(set_attr "type" "two")
3908 (set_attr "length" "8")])
3911 ;; Now the simple shifts.
3913 (define_insn "rotl<mode>3"
3914 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3915 (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3917 ""
3918 "rotl<wd>%I2 %0,%1,%<hH>2"
3919 [(set_attr "type" "shift")
3920 (set_attr "maybe_var_shift" "yes")])
3922 (define_insn "*rotlsi3_64"
3923 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3924 (zero_extend:DI
3925 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3926 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3927 "TARGET_POWERPC64"
3928 "rotlw%I2 %0,%1,%h2"
3929 [(set_attr "type" "shift")
3930 (set_attr "maybe_var_shift" "yes")])
3932 (define_insn_and_split "*rotl<mode>3_dot"
3933 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3934 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3935 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3936 (const_int 0)))
3937 (clobber (match_scratch:GPR 0 "=r,r"))]
3938 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3939 "@
3940 rotl<wd>%I2. %0,%1,%<hH>2
3941 #"
3942 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3943 [(set (match_dup 0)
3944 (rotate:GPR (match_dup 1)
3945 (match_dup 2)))
3946 (set (match_dup 3)
3947 (compare:CC (match_dup 0)
3948 (const_int 0)))]
3949 ""
3950 [(set_attr "type" "shift")
3951 (set_attr "maybe_var_shift" "yes")
3952 (set_attr "dot" "yes")
3953 (set_attr "length" "4,8")])
3955 (define_insn_and_split "*rotl<mode>3_dot2"
3956 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3957 (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
3959 (const_int 0)))
3960 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
3961 (rotate:GPR (match_dup 1)
3962 (match_dup 2)))]
3963 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
3964 "@
3965 rotl<wd>%I2. %0,%1,%<hH>2
3966 #"
3967 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
3968 [(set (match_dup 0)
3969 (rotate:GPR (match_dup 1)
3970 (match_dup 2)))
3971 (set (match_dup 3)
3972 (compare:CC (match_dup 0)
3973 (const_int 0)))]
3974 ""
3975 [(set_attr "type" "shift")
3976 (set_attr "maybe_var_shift" "yes")
3977 (set_attr "dot" "yes")
3978 (set_attr "length" "4,8")])
3981 (define_insn "ashl<mode>3"
3982 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3983 (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3984 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
3985 ""
3986 "sl<wd>%I2 %0,%1,%<hH>2"
3987 [(set_attr "type" "shift")
3988 (set_attr "maybe_var_shift" "yes")])
3990 (define_insn "*ashlsi3_64"
3991 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3992 (zero_extend:DI
3993 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3994 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
3995 "TARGET_POWERPC64"
3996 "slw%I2 %0,%1,%h2"
3997 [(set_attr "type" "shift")
3998 (set_attr "maybe_var_shift" "yes")])
4000 (define_insn_and_split "*ashl<mode>3_dot"
4001 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4002 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4003 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4004 (const_int 0)))
4005 (clobber (match_scratch:GPR 0 "=r,r"))]
4006 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4007 "@
4008 sl<wd>%I2. %0,%1,%<hH>2
4009 #"
4010 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4011 [(set (match_dup 0)
4012 (ashift:GPR (match_dup 1)
4013 (match_dup 2)))
4014 (set (match_dup 3)
4015 (compare:CC (match_dup 0)
4016 (const_int 0)))]
4017 ""
4018 [(set_attr "type" "shift")
4019 (set_attr "maybe_var_shift" "yes")
4020 (set_attr "dot" "yes")
4021 (set_attr "length" "4,8")])
4023 (define_insn_and_split "*ashl<mode>3_dot2"
4024 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4025 (compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4026 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4027 (const_int 0)))
4028 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4029 (ashift:GPR (match_dup 1)
4030 (match_dup 2)))]
4031 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4032 "@
4033 sl<wd>%I2. %0,%1,%<hH>2
4034 #"
4035 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4036 [(set (match_dup 0)
4037 (ashift:GPR (match_dup 1)
4038 (match_dup 2)))
4039 (set (match_dup 3)
4040 (compare:CC (match_dup 0)
4041 (const_int 0)))]
4042 ""
4043 [(set_attr "type" "shift")
4044 (set_attr "maybe_var_shift" "yes")
4045 (set_attr "dot" "yes")
4046 (set_attr "length" "4,8")])
4048 ;; Pretend we have a memory form of extswsli until register allocation is done
4049 ;; so that we use LWZ to load the value from memory, instead of LWA.
4050 (define_insn_and_split "ashdi3_extswsli"
4051 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4052 (ashift:DI
4053 (sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "r,m"))
4054 (match_operand:DI 2 "u6bit_cint_operand" "n,n")))]
4055 "TARGET_EXTSWSLI"
4056 "@
4057 extswsli %0,%1,%2
4058 #"
4059 "&& reload_completed && MEM_P (operands[1])"
4060 [(set (match_dup 3)
4061 (match_dup 1))
4062 (set (match_dup 0)
4063 (ashift:DI (sign_extend:DI (match_dup 3))
4064 (match_dup 2)))]
4065 {
4066 operands[3] = gen_lowpart (SImode, operands[0]);
4067 }
4068 [(set_attr "type" "shift")
4069 (set_attr "maybe_var_shift" "no")])
4072 (define_insn_and_split "ashdi3_extswsli_dot"
4073 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?x,??y")
4074 (compare:CC
4075 (ashift:DI
4076 (sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "r,r,m,m"))
4077 (match_operand:DI 2 "u6bit_cint_operand" "n,n,n,n"))
4078 (const_int 0)))
4079 (clobber (match_scratch:DI 0 "=r,r,r,r"))]
4080 "TARGET_EXTSWSLI"
4081 "@
4082 extswsli. %0,%1,%2
4083 #
4084 #
4085 #"
4086 "&& reload_completed
4087 && (cc_reg_not_cr0_operand (operands[3], CCmode)
4088 || memory_operand (operands[1], SImode))"
4089 [(pc)]
4090 {
4091 rtx dest = operands[0];
4092 rtx src = operands[1];
4093 rtx shift = operands[2];
4094 rtx cr = operands[3];
4095 rtx src2;
4097 if (!MEM_P (src))
4098 src2 = src;
4099 else
4100 {
4101 src2 = gen_lowpart (SImode, dest);
4102 emit_move_insn (src2, src);
4103 }
4105 if (REGNO (cr) == CR0_REGNO)
4106 {
4107 emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
4108 DONE;
4109 }
4111 emit_insn (gen_ashdi3_extswsli (dest, src2, shift));
4112 emit_insn (gen_rtx_SET (cr, gen_rtx_COMPARE (CCmode, dest, const0_rtx)));
4113 DONE;
4114 }
4115 [(set_attr "type" "shift")
4116 (set_attr "maybe_var_shift" "no")
4117 (set_attr "dot" "yes")
4118 (set_attr "length" "4,8,8,12")])
4120 (define_insn_and_split "ashdi3_extswsli_dot2"
4121 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y,?x,??y")
4122 (compare:CC
4123 (ashift:DI
4124 (sign_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "r,r,m,m"))
4125 (match_operand:DI 2 "u6bit_cint_operand" "n,n,n,n"))
4126 (const_int 0)))
4127 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
4128 (ashift:DI (sign_extend:DI (match_dup 1))
4129 (match_dup 2)))]
4130 "TARGET_EXTSWSLI"
4131 "@
4132 extswsli. %0,%1,%2
4133 #
4134 #
4135 #"
4136 "&& reload_completed
4137 && (cc_reg_not_cr0_operand (operands[3], CCmode)
4138 || memory_operand (operands[1], SImode))"
4139 [(pc)]
4140 {
4141 rtx dest = operands[0];
4142 rtx src = operands[1];
4143 rtx shift = operands[2];
4144 rtx cr = operands[3];
4145 rtx src2;
4147 if (!MEM_P (src))
4148 src2 = src;
4149 else
4150 {
4151 src2 = gen_lowpart (SImode, dest);
4152 emit_move_insn (src2, src);
4153 }
4155 if (REGNO (cr) == CR0_REGNO)
4156 {
4157 emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
4158 DONE;
4159 }
4161 emit_insn (gen_ashdi3_extswsli (dest, src2, shift));
4162 emit_insn (gen_rtx_SET (cr, gen_rtx_COMPARE (CCmode, dest, const0_rtx)));
4163 DONE;
4164 }
4165 [(set_attr "type" "shift")
4166 (set_attr "maybe_var_shift" "no")
4167 (set_attr "dot" "yes")
4168 (set_attr "length" "4,8,8,12")])
4170 (define_insn "lshr<mode>3"
4171 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4172 (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4173 (match_operand:SI 2 "reg_or_cint_operand" "rn")))]
4174 ""
4175 "sr<wd>%I2 %0,%1,%<hH>2"
4176 [(set_attr "type" "shift")
4177 (set_attr "maybe_var_shift" "yes")])
4179 (define_insn "*lshrsi3_64"
4180 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4181 (zero_extend:DI
4182 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4183 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))]
4184 "TARGET_POWERPC64"
4185 "srw%I2 %0,%1,%h2"
4186 [(set_attr "type" "shift")
4187 (set_attr "maybe_var_shift" "yes")])
4189 (define_insn_and_split "*lshr<mode>3_dot"
4190 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4191 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4192 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4193 (const_int 0)))
4194 (clobber (match_scratch:GPR 0 "=r,r"))]
4195 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4196 "@
4197 sr<wd>%I2. %0,%1,%<hH>2
4198 #"
4199 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4200 [(set (match_dup 0)
4201 (lshiftrt:GPR (match_dup 1)
4202 (match_dup 2)))
4203 (set (match_dup 3)
4204 (compare:CC (match_dup 0)
4205 (const_int 0)))]
4206 ""
4207 [(set_attr "type" "shift")
4208 (set_attr "maybe_var_shift" "yes")
4209 (set_attr "dot" "yes")
4210 (set_attr "length" "4,8")])
4212 (define_insn_and_split "*lshr<mode>3_dot2"
4213 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4214 (compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4215 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4216 (const_int 0)))
4217 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4218 (lshiftrt:GPR (match_dup 1)
4219 (match_dup 2)))]
4220 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4221 "@
4222 sr<wd>%I2. %0,%1,%<hH>2
4223 #"
4224 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4225 [(set (match_dup 0)
4226 (lshiftrt:GPR (match_dup 1)
4227 (match_dup 2)))
4228 (set (match_dup 3)
4229 (compare:CC (match_dup 0)
4230 (const_int 0)))]
4231 ""
4232 [(set_attr "type" "shift")
4233 (set_attr "maybe_var_shift" "yes")
4234 (set_attr "dot" "yes")
4235 (set_attr "length" "4,8")])
4238 (define_insn "ashr<mode>3"
4239 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4240 (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
4241 (match_operand:SI 2 "reg_or_cint_operand" "rn")))
4242 (clobber (reg:GPR CA_REGNO))]
4243 ""
4244 "sra<wd>%I2 %0,%1,%<hH>2"
4245 [(set_attr "type" "shift")
4246 (set_attr "maybe_var_shift" "yes")])
4248 (define_insn "*ashrsi3_64"
4249 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4250 (sign_extend:DI
4251 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4252 (match_operand:SI 2 "reg_or_cint_operand" "rn"))))
4253 (clobber (reg:SI CA_REGNO))]
4254 "TARGET_POWERPC64"
4255 "sraw%I2 %0,%1,%h2"
4256 [(set_attr "type" "shift")
4257 (set_attr "maybe_var_shift" "yes")])
4259 (define_insn_and_split "*ashr<mode>3_dot"
4260 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4261 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4262 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4263 (const_int 0)))
4264 (clobber (match_scratch:GPR 0 "=r,r"))
4265 (clobber (reg:GPR CA_REGNO))]
4266 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4267 "@
4268 sra<wd>%I2. %0,%1,%<hH>2
4269 #"
4270 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4271 [(parallel [(set (match_dup 0)
4272 (ashiftrt:GPR (match_dup 1)
4273 (match_dup 2)))
4274 (clobber (reg:GPR CA_REGNO))])
4275 (set (match_dup 3)
4276 (compare:CC (match_dup 0)
4277 (const_int 0)))]
4278 ""
4279 [(set_attr "type" "shift")
4280 (set_attr "maybe_var_shift" "yes")
4281 (set_attr "dot" "yes")
4282 (set_attr "length" "4,8")])
4284 (define_insn_and_split "*ashr<mode>3_dot2"
4285 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4286 (compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
4287 (match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
4288 (const_int 0)))
4289 (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4290 (ashiftrt:GPR (match_dup 1)
4291 (match_dup 2)))
4292 (clobber (reg:GPR CA_REGNO))]
4293 "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
4294 "@
4295 sra<wd>%I2. %0,%1,%<hH>2
4296 #"
4297 "&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
4298 [(parallel [(set (match_dup 0)
4299 (ashiftrt:GPR (match_dup 1)
4300 (match_dup 2)))
4301 (clobber (reg:GPR CA_REGNO))])
4302 (set (match_dup 3)
4303 (compare:CC (match_dup 0)
4304 (const_int 0)))]
4305 ""
4306 [(set_attr "type" "shift")
4307 (set_attr "maybe_var_shift" "yes")
4308 (set_attr "dot" "yes")
4309 (set_attr "length" "4,8")])
4310 \f
4311 ;; Builtins to replace a division to generate FRE reciprocal estimate
4312 ;; instructions and the necessary fixup instructions
4313 (define_expand "recip<mode>3"
4314 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4315 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4316 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4317 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4318 {
4319 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4320 DONE;
4321 })
4323 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4324 ;; hardware division. This is only done before register allocation and with
4325 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4326 (define_split
4327 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4328 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4329 (match_operand 2 "gpc_reg_operand" "")))]
4330 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4331 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4332 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4333 [(const_int 0)]
4334 {
4335 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4336 DONE;
4337 })
4339 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4340 ;; appropriate fixup.
4341 (define_expand "rsqrt<mode>2"
4342 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4343 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4344 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4345 {
4346 rs6000_emit_swsqrt (operands[0], operands[1], 1);
4347 DONE;
4348 })
4349 \f
4350 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
4351 ;; modes here, and also add in conditional vsx/power8-vector support to access
4352 ;; values in the traditional Altivec registers if the appropriate
4353 ;; -mupper-regs-{df,sf} option is enabled.
4355 (define_expand "abs<mode>2"
4356 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4357 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4358 "TARGET_<MODE>_INSN"
4359 "")
4361 (define_insn "*abs<mode>2_fpr"
4362 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4363 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4364 "TARGET_<MODE>_FPR"
4365 "@
4366 fabs %0,%1
4367 xsabsdp %x0,%x1"
4368 [(set_attr "type" "fpsimple")
4369 (set_attr "fp_type" "fp_addsub_<Fs>")])
4371 (define_insn "*nabs<mode>2_fpr"
4372 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4373 (neg:SFDF
4374 (abs:SFDF
4375 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
4376 "TARGET_<MODE>_FPR"
4377 "@
4378 fnabs %0,%1
4379 xsnabsdp %x0,%x1"
4380 [(set_attr "type" "fpsimple")
4381 (set_attr "fp_type" "fp_addsub_<Fs>")])
4383 (define_expand "neg<mode>2"
4384 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4385 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4386 "TARGET_<MODE>_INSN"
4387 "")
4389 (define_insn "*neg<mode>2_fpr"
4390 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4391 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
4392 "TARGET_<MODE>_FPR"
4393 "@
4394 fneg %0,%1
4395 xsnegdp %x0,%x1"
4396 [(set_attr "type" "fpsimple")
4397 (set_attr "fp_type" "fp_addsub_<Fs>")])
4399 (define_expand "add<mode>3"
4400 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4401 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4402 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4403 "TARGET_<MODE>_INSN"
4404 "")
4406 (define_insn "*add<mode>3_fpr"
4407 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4408 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
4409 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4410 "TARGET_<MODE>_FPR"
4411 "@
4412 fadd<Ftrad> %0,%1,%2
4413 xsadd<Fvsx> %x0,%x1,%x2"
4414 [(set_attr "type" "fp")
4415 (set_attr "fp_type" "fp_addsub_<Fs>")])
4417 (define_expand "sub<mode>3"
4418 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4419 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4420 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4421 "TARGET_<MODE>_INSN"
4422 "")
4424 (define_insn "*sub<mode>3_fpr"
4425 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4426 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
4427 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4428 "TARGET_<MODE>_FPR"
4429 "@
4430 fsub<Ftrad> %0,%1,%2
4431 xssub<Fvsx> %x0,%x1,%x2"
4432 [(set_attr "type" "fp")
4433 (set_attr "fp_type" "fp_addsub_<Fs>")])
4435 (define_expand "mul<mode>3"
4436 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4437 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4438 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4439 "TARGET_<MODE>_INSN"
4440 "")
4442 (define_insn "*mul<mode>3_fpr"
4443 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4444 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
4445 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4446 "TARGET_<MODE>_FPR"
4447 "@
4448 fmul<Ftrad> %0,%1,%2
4449 xsmul<Fvsx> %x0,%x1,%x2"
4450 [(set_attr "type" "dmul")
4451 (set_attr "fp_type" "fp_mul_<Fs>")])
4453 (define_expand "div<mode>3"
4454 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4455 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4456 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4457 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
4458 "")
4460 (define_insn "*div<mode>3_fpr"
4461 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4462 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
4463 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4464 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
4465 "@
4466 fdiv<Ftrad> %0,%1,%2
4467 xsdiv<Fvsx> %x0,%x1,%x2"
4468 [(set_attr "type" "<Fs>div")
4469 (set_attr "fp_type" "fp_div_<Fs>")])
4471 (define_insn "*sqrt<mode>2_internal"
4472 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4473 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4474 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4475 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4476 "@
4477 fsqrt<Ftrad> %0,%1
4478 xssqrt<Fvsx> %x0,%x1"
4479 [(set_attr "type" "<Fs>sqrt")
4480 (set_attr "fp_type" "fp_sqrt_<Fs>")])
4482 (define_expand "sqrt<mode>2"
4483 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4484 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
4485 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
4486 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
4487 {
4488 if (<MODE>mode == SFmode
4489 && TARGET_RECIP_PRECISION
4490 && RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)
4491 && !optimize_function_for_size_p (cfun)
4492 && flag_finite_math_only && !flag_trapping_math
4493 && flag_unsafe_math_optimizations)
4494 {
4495 rs6000_emit_swsqrt (operands[0], operands[1], 0);
4496 DONE;
4497 }
4498 })
4500 ;; Floating point reciprocal approximation
4501 (define_insn "fre<Fs>"
4502 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4503 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
4504 UNSPEC_FRES))]
4505 "TARGET_<FFRE>"
4506 "@
4507 fre<Ftrad> %0,%1
4508 xsre<Fvsx> %x0,%x1"
4509 [(set_attr "type" "fp")])
4511 (define_insn "*rsqrt<mode>2"
4512 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
4513 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
4514 UNSPEC_RSQRT))]
4515 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4516 "@
4517 frsqrte<Ftrad> %0,%1
4518 xsrsqrte<Fvsx> %x0,%x1"
4519 [(set_attr "type" "fp")])
4521 ;; Floating point comparisons
4522 (define_insn "*cmp<mode>_fpr"
4523 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
4524 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
4525 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
4526 "TARGET_<MODE>_FPR"
4527 "@
4528 fcmpu %0,%1,%2
4529 xscmpudp %0,%x1,%x2"
4530 [(set_attr "type" "fpcompare")])
4532 ;; Floating point conversions
4533 (define_expand "extendsfdf2"
4534 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4535 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4536 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4537 "")
4539 (define_insn_and_split "*extendsfdf2_fpr"
4540 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,wb")
4541 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,o")))]
4542 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4543 "@
4544 #
4545 fmr %0,%1
4546 lfs%U1%X1 %0,%1
4547 #
4548 xscpsgndp %x0,%x1,%x1
4549 lxsspx %x0,%y1
4550 lxssp %0,%1"
4551 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4552 [(const_int 0)]
4553 {
4554 emit_note (NOTE_INSN_DELETED);
4555 DONE;
4556 }
4557 [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")])
4559 (define_expand "truncdfsf2"
4560 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4561 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4562 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4563 "")
4565 (define_insn "*truncdfsf2_fpr"
4566 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
4567 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
4568 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4569 "@
4570 frsp %0,%1
4571 xsrsp %x0,%x1"
4572 [(set_attr "type" "fp")])
4574 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
4575 ;; builtins.c and optabs.c that are not correct for IBM long double
4576 ;; when little-endian.
4577 (define_expand "signbit<mode>2"
4578 [(set (match_dup 2)
4579 (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))
4580 (set (match_dup 3)
4581 (subreg:DI (match_dup 2) 0))
4582 (set (match_dup 4)
4583 (match_dup 5))
4584 (set (match_operand:SI 0 "gpc_reg_operand" "")
4585 (match_dup 6))]
4586 "TARGET_HARD_FLOAT
4587 && (TARGET_FPRS || TARGET_E500_DOUBLE)
4588 && (!FLOAT128_IEEE_P (<MODE>mode)
4589 || (TARGET_POWERPC64 && TARGET_DIRECT_MOVE))"
4590 {
4591 if (FLOAT128_IEEE_P (<MODE>mode))
4592 {
4593 if (<MODE>mode == KFmode)
4594 emit_insn (gen_signbitkf2_dm (operands[0], operands[1]));
4595 else if (<MODE>mode == TFmode)
4596 emit_insn (gen_signbittf2_dm (operands[0], operands[1]));
4597 else
4598 gcc_unreachable ();
4599 DONE;
4600 }
4601 operands[2] = gen_reg_rtx (DFmode);
4602 operands[3] = gen_reg_rtx (DImode);
4603 if (TARGET_POWERPC64)
4604 {
4605 operands[4] = gen_reg_rtx (DImode);
4606 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
4607 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
4608 WORDS_BIG_ENDIAN ? 4 : 0);
4609 }
4610 else
4611 {
4612 operands[4] = gen_reg_rtx (SImode);
4613 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
4614 WORDS_BIG_ENDIAN ? 0 : 4);
4615 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
4616 }
4617 })
4619 (define_expand "copysign<mode>3"
4620 [(set (match_dup 3)
4621 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
4622 (set (match_dup 4)
4623 (neg:SFDF (abs:SFDF (match_dup 1))))
4624 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
4625 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
4626 (match_dup 5))
4627 (match_dup 3)
4628 (match_dup 4)))]
4629 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
4630 && ((TARGET_PPC_GFXOPT
4631 && !HONOR_NANS (<MODE>mode)
4632 && !HONOR_SIGNED_ZEROS (<MODE>mode))
4633 || TARGET_CMPB
4634 || VECTOR_UNIT_VSX_P (<MODE>mode))"
4635 {
4636 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
4637 {
4638 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
4639 operands[2]));
4640 DONE;
4641 }
4643 operands[3] = gen_reg_rtx (<MODE>mode);
4644 operands[4] = gen_reg_rtx (<MODE>mode);
4645 operands[5] = CONST0_RTX (<MODE>mode);
4646 })
4648 ;; Optimize signbit on 64-bit systems with direct move to avoid doing the store
4649 ;; and load.
4650 (define_insn_and_split "signbit<mode>2_dm"
4651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4652 (unspec:SI
4653 [(match_operand:SIGNBIT 1 "input_operand" "<Fsignbit>,m,r")]
4654 UNSPEC_SIGNBIT))]
4655 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
4656 "#"
4657 "&& reload_completed"
4658 [(const_int 0)]
4659 {
4660 rs6000_split_signbit (operands[0], operands[1]);
4661 DONE;
4662 }
4663 [(set_attr "length" "8,8,12")
4664 (set_attr "type" "mftgpr,load,integer")])
4666 ;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating
4667 ;; point types, which makes normal SUBREG's problematical. Instead use a
4668 ;; special pattern to avoid using a normal movdi.
4669 (define_insn "signbit<mode>2_dm2"
4670 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4671 (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "<Fsignbit>")
4672 (const_int 0)]
4673 UNSPEC_SIGNBIT))]
4674 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
4675 "mfvsrd %0,%x1"
4676 [(set_attr "type" "mftgpr")])
4679 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
4680 ;; compiler from optimizing -0.0
4681 (define_insn "copysign<mode>3_fcpsgn"
4682 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
4683 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
4684 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
4685 UNSPEC_COPYSIGN))]
4686 "TARGET_<MODE>_FPR && TARGET_CMPB"
4687 "@
4688 fcpsgn %0,%2,%1
4689 xscpsgndp %x0,%x2,%x1"
4690 [(set_attr "type" "fpsimple")])
4692 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4693 ;; fsel instruction and some auxiliary computations. Then we just have a
4694 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4695 ;; combine.
4696 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
4697 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
4698 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
4699 ;; define_splits to make them if made by combine. On VSX machines we have the
4700 ;; min/max instructions.
4701 ;;
4702 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
4703 ;; to allow either DF/SF to use only traditional registers.
4705 (define_expand "s<minmax><mode>3"
4706 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4707 (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4708 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4709 "TARGET_MINMAX_<MODE>"
4710 {
4711 rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
4712 DONE;
4713 })
4715 (define_insn "*s<minmax><mode>3_vsx"
4716 [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
4717 (fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
4718 (match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
4719 "TARGET_VSX && TARGET_<MODE>_FPR"
4720 {
4721 return (TARGET_P9_MINMAX
4722 ? "xs<minmax>cdp %x0,%x1,%x2"
4723 : "xs<minmax>dp %x0,%x1,%x2");
4724 }
4725 [(set_attr "type" "fp")])
4727 ;; The conditional move instructions allow us to perform max and min operations
4728 ;; even when we don't have the appropriate max/min instruction using the FSEL
4729 ;; instruction.
4731 (define_insn_and_split "*s<minmax><mode>3_fpr"
4732 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4733 (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
4734 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
4735 "!TARGET_VSX && TARGET_MINMAX_<MODE>"
4736 "#"
4737 "&& 1"
4738 [(const_int 0)]
4739 {
4740 rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
4741 DONE;
4742 })
4744 (define_expand "mov<mode>cc"
4745 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
4746 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
4747 (match_operand:GPR 2 "gpc_reg_operand" "")
4748 (match_operand:GPR 3 "gpc_reg_operand" "")))]
4749 "TARGET_ISEL<sel>"
4750 "
4751 {
4752 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4753 DONE;
4754 else
4755 FAIL;
4756 }")
4758 ;; We use the BASE_REGS for the isel input operands because, if rA is
4759 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4760 ;; because we may switch the operands and rB may end up being rA.
4761 ;;
4762 ;; We need 2 patterns: an unsigned and a signed pattern. We could
4763 ;; leave out the mode in operand 4 and use one pattern, but reload can
4764 ;; change the mode underneath our feet and then gets confused trying
4765 ;; to reload the value.
4766 (define_insn "isel_signed_<mode>"
4767 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4768 (if_then_else:GPR
4769 (match_operator 1 "scc_comparison_operator"
4770 [(match_operand:CC 4 "cc_reg_operand" "y,y")
4771 (const_int 0)])
4772 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4773 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4774 "TARGET_ISEL<sel>"
4775 "*
4776 { return output_isel (operands); }"
4777 [(set_attr "type" "isel")
4778 (set_attr "length" "4")])
4780 (define_insn "isel_unsigned_<mode>"
4781 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
4782 (if_then_else:GPR
4783 (match_operator 1 "scc_comparison_operator"
4784 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
4785 (const_int 0)])
4786 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
4787 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
4788 "TARGET_ISEL<sel>"
4789 "*
4790 { return output_isel (operands); }"
4791 [(set_attr "type" "isel")
4792 (set_attr "length" "4")])
4794 ;; These patterns can be useful for combine; they let combine know that
4795 ;; isel can handle reversed comparisons so long as the operands are
4796 ;; registers.
4798 (define_insn "*isel_reversed_signed_<mode>"
4799 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4800 (if_then_else:GPR
4801 (match_operator 1 "scc_rev_comparison_operator"
4802 [(match_operand:CC 4 "cc_reg_operand" "y")
4803 (const_int 0)])
4804 (match_operand:GPR 2 "gpc_reg_operand" "b")
4805 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4806 "TARGET_ISEL<sel>"
4807 "*
4808 { return output_isel (operands); }"
4809 [(set_attr "type" "isel")
4810 (set_attr "length" "4")])
4812 (define_insn "*isel_reversed_unsigned_<mode>"
4813 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
4814 (if_then_else:GPR
4815 (match_operator 1 "scc_rev_comparison_operator"
4816 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4817 (const_int 0)])
4818 (match_operand:GPR 2 "gpc_reg_operand" "b")
4819 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
4820 "TARGET_ISEL<sel>"
4821 "*
4822 { return output_isel (operands); }"
4823 [(set_attr "type" "isel")
4824 (set_attr "length" "4")])
4826 ;; Floating point conditional move
4827 (define_expand "mov<mode>cc"
4828 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
4829 (if_then_else:SFDF (match_operand 1 "comparison_operator" "")
4830 (match_operand:SFDF 2 "gpc_reg_operand" "")
4831 (match_operand:SFDF 3 "gpc_reg_operand" "")))]
4832 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
4833 "
4834 {
4835 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4836 DONE;
4837 else
4838 FAIL;
4839 }")
4841 (define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
4842 [(set (match_operand:SFDF 0 "fpr_reg_operand" "=&<SFDF:rreg2>")
4843 (if_then_else:SFDF
4844 (ge (match_operand:SFDF2 1 "fpr_reg_operand" "<SFDF2:rreg2>")
4845 (match_operand:SFDF2 4 "zero_fp_constant" "F"))
4846 (match_operand:SFDF 2 "fpr_reg_operand" "<SFDF:rreg2>")
4847 (match_operand:SFDF 3 "fpr_reg_operand" "<SFDF:rreg2>")))]
4848 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
4849 "fsel %0,%1,%2,%3"
4850 [(set_attr "type" "fp")])
4852 (define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
4853 [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
4854 (if_then_else:SFDF
4855 (match_operator:CCFP 1 "fpmask_comparison_operator"
4856 [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
4857 (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
4858 (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
4859 (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
4860 (clobber (match_scratch:V2DI 6 "=0,&wa"))]
4861 "TARGET_P9_MINMAX"
4862 "#"
4863 ""
4864 [(set (match_dup 6)
4865 (if_then_else:V2DI (match_dup 1)
4866 (match_dup 7)
4867 (match_dup 8)))
4868 (set (match_dup 0)
4869 (if_then_else:SFDF (ne (match_dup 6)
4870 (match_dup 8))
4871 (match_dup 4)
4872 (match_dup 5)))]
4873 {
4874 if (GET_CODE (operands[6]) == SCRATCH)
4875 operands[6] = gen_reg_rtx (V2DImode);
4877 operands[7] = CONSTM1_RTX (V2DImode);
4878 operands[8] = CONST0_RTX (V2DImode);
4879 }
4880 [(set_attr "length" "8")
4881 (set_attr "type" "vecperm")])
4883 (define_insn "*fpmask<mode>"
4884 [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
4885 (if_then_else:V2DI
4886 (match_operator:CCFP 1 "fpmask_comparison_operator"
4887 [(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
4888 (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
4889 (match_operand:V2DI 4 "all_ones_constant" "")
4890 (match_operand:V2DI 5 "zero_constant" "")))]
4891 "TARGET_P9_MINMAX"
4892 "xscmp%V1dp %x0,%x2,%x3"
4893 [(set_attr "type" "fpcompare")])
4895 (define_insn "*xxsel<mode>"
4896 [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
4897 (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
4898 (match_operand:V2DI 2 "zero_constant" ""))
4899 (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
4900 (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
4901 "TARGET_P9_MINMAX"
4902 "xxsel %x0,%x1,%x3,%x4"
4903 [(set_attr "type" "vecmove")])
4905 \f
4906 ;; Conversions to and from floating-point.
4908 ; We don't define lfiwax/lfiwzx with the normal definition, because we
4909 ; don't want to support putting SImode in FPR registers.
4910 (define_insn "lfiwax"
4911 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
4912 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
4913 UNSPEC_LFIWAX))]
4914 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
4915 "@
4916 lfiwax %0,%y1
4917 lxsiwax %x0,%y1
4918 mtvsrwa %x0,%1"
4919 [(set_attr "type" "fpload,fpload,mffgpr")])
4921 ; This split must be run before register allocation because it allocates the
4922 ; memory slot that is needed to move values to/from the FPR. We don't allocate
4923 ; it earlier to allow for the combiner to merge insns together where it might
4924 ; not be needed and also in case the insns are deleted as dead code.
4926 (define_insn_and_split "floatsi<mode>2_lfiwax"
4927 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
4928 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
4929 (clobber (match_scratch:DI 2 "=wi"))]
4930 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
4931 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
4932 "#"
4933 ""
4934 [(pc)]
4935 "
4936 {
4937 rtx dest = operands[0];
4938 rtx src = operands[1];
4939 rtx tmp;
4941 if (!MEM_P (src) && TARGET_POWERPC64
4942 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
4943 tmp = convert_to_mode (DImode, src, false);
4944 else
4945 {
4946 tmp = operands[2];
4947 if (GET_CODE (tmp) == SCRATCH)
4948 tmp = gen_reg_rtx (DImode);
4949 if (MEM_P (src))
4950 {
4951 src = rs6000_address_for_fpconvert (src);
4952 emit_insn (gen_lfiwax (tmp, src));
4953 }
4954 else
4955 {
4956 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
4957 emit_move_insn (stack, src);
4958 emit_insn (gen_lfiwax (tmp, stack));
4959 }
4960 }
4961 emit_insn (gen_floatdi<mode>2 (dest, tmp));
4962 DONE;
4963 }"
4964 [(set_attr "length" "12")
4965 (set_attr "type" "fpload")])
4967 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
4968 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
4969 (float:SFDF
4970 (sign_extend:DI
4971 (match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
4972 (clobber (match_scratch:DI 2 "=wi"))]
4973 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
4974 && <SI_CONVERT_FP>"
4975 "#"
4976 ""
4977 [(pc)]
4978 "
4979 {
4980 operands[1] = rs6000_address_for_fpconvert (operands[1]);
4981 if (GET_CODE (operands[2]) == SCRATCH)
4982 operands[2] = gen_reg_rtx (DImode);
4983 emit_insn (gen_lfiwax (operands[2], operands[1]));
4984 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
4985 DONE;
4986 }"
4987 [(set_attr "length" "8")
4988 (set_attr "type" "fpload")])
4990 (define_insn "lfiwzx"
4991 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj")
4992 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
4993 UNSPEC_LFIWZX))]
4994 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
4995 "@
4996 lfiwzx %0,%y1
4997 lxsiwzx %x0,%y1
4998 mtvsrwz %x0,%1"
4999 [(set_attr "type" "fpload,fpload,mftgpr")])
5001 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5002 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5003 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5004 (clobber (match_scratch:DI 2 "=wi"))]
5005 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5006 && <SI_CONVERT_FP>"
5007 "#"
5008 ""
5009 [(pc)]
5010 "
5011 {
5012 rtx dest = operands[0];
5013 rtx src = operands[1];
5014 rtx tmp;
5016 if (!MEM_P (src) && TARGET_POWERPC64
5017 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5018 tmp = convert_to_mode (DImode, src, true);
5019 else
5020 {
5021 tmp = operands[2];
5022 if (GET_CODE (tmp) == SCRATCH)
5023 tmp = gen_reg_rtx (DImode);
5024 if (MEM_P (src))
5025 {
5026 src = rs6000_address_for_fpconvert (src);
5027 emit_insn (gen_lfiwzx (tmp, src));
5028 }
5029 else
5030 {
5031 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5032 emit_move_insn (stack, src);
5033 emit_insn (gen_lfiwzx (tmp, stack));
5034 }
5035 }
5036 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5037 DONE;
5038 }"
5039 [(set_attr "length" "12")
5040 (set_attr "type" "fpload")])
5042 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5043 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5044 (unsigned_float:SFDF
5045 (zero_extend:DI
5046 (match_operand:SI 1 "indexed_or_indirect_operand" "Z"))))
5047 (clobber (match_scratch:DI 2 "=wi"))]
5048 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5049 && <SI_CONVERT_FP>"
5050 "#"
5051 ""
5052 [(pc)]
5053 "
5054 {
5055 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5056 if (GET_CODE (operands[2]) == SCRATCH)
5057 operands[2] = gen_reg_rtx (DImode);
5058 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5059 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5060 DONE;
5061 }"
5062 [(set_attr "length" "8")
5063 (set_attr "type" "fpload")])
5065 ; For each of these conversions, there is a define_expand, a define_insn
5066 ; with a '#' template, and a define_split (with C code). The idea is
5067 ; to allow constant folding with the template of the define_insn,
5068 ; then to have the insns split later (between sched1 and final).
5070 (define_expand "floatsidf2"
5071 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5073 (use (match_dup 2))
5074 (use (match_dup 3))
5075 (clobber (match_dup 4))
5076 (clobber (match_dup 5))
5077 (clobber (match_dup 6))])]
5078 "TARGET_HARD_FLOAT
5079 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5080 "
5081 {
5082 if (TARGET_E500_DOUBLE)
5083 {
5084 if (!REG_P (operands[1]))
5085 operands[1] = force_reg (SImode, operands[1]);
5086 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5087 DONE;
5088 }
5089 else if (TARGET_LFIWAX && TARGET_FCFID)
5090 {
5091 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5092 DONE;
5093 }
5094 else if (TARGET_FCFID)
5095 {
5096 rtx dreg = operands[1];
5097 if (!REG_P (dreg))
5098 dreg = force_reg (SImode, dreg);
5099 dreg = convert_to_mode (DImode, dreg, false);
5100 emit_insn (gen_floatdidf2 (operands[0], dreg));
5101 DONE;
5102 }
5104 if (!REG_P (operands[1]))
5105 operands[1] = force_reg (SImode, operands[1]);
5106 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5107 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5108 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5109 operands[5] = gen_reg_rtx (DFmode);
5110 operands[6] = gen_reg_rtx (SImode);
5111 }")
5113 (define_insn_and_split "*floatsidf2_internal"
5114 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5115 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5116 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5117 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5118 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5119 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5120 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5121 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5122 "#"
5123 ""
5124 [(pc)]
5125 "
5126 {
5127 rtx lowword, highword;
5128 gcc_assert (MEM_P (operands[4]));
5129 highword = adjust_address (operands[4], SImode, 0);
5130 lowword = adjust_address (operands[4], SImode, 4);
5131 if (! WORDS_BIG_ENDIAN)
5132 std::swap (lowword, highword);
5134 emit_insn (gen_xorsi3 (operands[6], operands[1],
5135 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5136 emit_move_insn (lowword, operands[6]);
5137 emit_move_insn (highword, operands[2]);
5138 emit_move_insn (operands[5], operands[4]);
5139 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5140 DONE;
5141 }"
5142 [(set_attr "length" "24")
5143 (set_attr "type" "fp")])
5145 ;; If we don't have a direct conversion to single precision, don't enable this
5146 ;; conversion for 32-bit without fast math, because we don't have the insn to
5147 ;; generate the fixup swizzle to avoid double rounding problems.
5148 (define_expand "floatunssisf2"
5149 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5150 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5151 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5152 && (!TARGET_FPRS
5153 || (TARGET_FPRS
5154 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5155 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5156 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5157 "
5158 {
5159 if (!TARGET_FPRS)
5160 {
5161 if (!REG_P (operands[1]))
5162 operands[1] = force_reg (SImode, operands[1]);
5163 }
5164 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5165 {
5166 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5167 DONE;
5168 }
5169 else
5170 {
5171 rtx dreg = operands[1];
5172 if (!REG_P (dreg))
5173 dreg = force_reg (SImode, dreg);
5174 dreg = convert_to_mode (DImode, dreg, true);
5175 emit_insn (gen_floatdisf2 (operands[0], dreg));
5176 DONE;
5177 }
5178 }")
5180 (define_expand "floatunssidf2"
5181 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5182 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5183 (use (match_dup 2))
5184 (use (match_dup 3))
5185 (clobber (match_dup 4))
5186 (clobber (match_dup 5))])]
5187 "TARGET_HARD_FLOAT
5188 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5189 "
5190 {
5191 if (TARGET_E500_DOUBLE)
5192 {
5193 if (!REG_P (operands[1]))
5194 operands[1] = force_reg (SImode, operands[1]);
5195 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5196 DONE;
5197 }
5198 else if (TARGET_LFIWZX && TARGET_FCFID)
5199 {
5200 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5201 DONE;
5202 }
5203 else if (TARGET_FCFID)
5204 {
5205 rtx dreg = operands[1];
5206 if (!REG_P (dreg))
5207 dreg = force_reg (SImode, dreg);
5208 dreg = convert_to_mode (DImode, dreg, true);
5209 emit_insn (gen_floatdidf2 (operands[0], dreg));
5210 DONE;
5211 }
5213 if (!REG_P (operands[1]))
5214 operands[1] = force_reg (SImode, operands[1]);
5215 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5216 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5217 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5218 operands[5] = gen_reg_rtx (DFmode);
5219 }")
5221 (define_insn_and_split "*floatunssidf2_internal"
5222 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5223 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5224 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5225 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5226 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5227 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5228 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5229 && !(TARGET_FCFID && TARGET_POWERPC64)"
5230 "#"
5231 ""
5232 [(pc)]
5233 "
5234 {
5235 rtx lowword, highword;
5236 gcc_assert (MEM_P (operands[4]));
5237 highword = adjust_address (operands[4], SImode, 0);
5238 lowword = adjust_address (operands[4], SImode, 4);
5239 if (! WORDS_BIG_ENDIAN)
5240 std::swap (lowword, highword);
5242 emit_move_insn (lowword, operands[1]);
5243 emit_move_insn (highword, operands[2]);
5244 emit_move_insn (operands[5], operands[4]);
5245 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5246 DONE;
5247 }"
5248 [(set_attr "length" "20")
5249 (set_attr "type" "fp")])
5251 ;; ISA 3.0 adds instructions lxsi[bh]zx to directly load QImode and HImode to
5252 ;; vector registers. At the moment, QI/HImode are not allowed in floating
5253 ;; point or vector registers, so we use UNSPEC's to use the load byte and
5254 ;; half-word instructions.
5256 (define_expand "float<QHI:mode><FP_ISA3:mode>2"
5257 [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand")
5258 (float:FP_ISA3
5259 (match_operand:QHI 1 "input_operand")))
5260 (clobber (match_scratch:DI 2))
5261 (clobber (match_scratch:DI 3))])]
5262 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
5263 {
5264 if (MEM_P (operands[1]))
5265 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5266 })
5268 (define_insn_and_split "*float<QHI:mode><FP_ISA3:mode>2_internal"
5269 [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>")
5270 (float:FP_ISA3
5271 (match_operand:QHI 1 "reg_or_indexed_operand" "r,Z")))
5272 (clobber (match_scratch:DI 2 "=wi,v"))
5273 (clobber (match_scratch:DI 3 "=r,X"))]
5274 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
5275 && TARGET_UPPER_REGS_DI"
5276 "#"
5277 "&& reload_completed"
5278 [(const_int 0)]
5279 {
5280 rtx result = operands[0];
5281 rtx input = operands[1];
5282 rtx di = operands[2];
5284 if (!MEM_P (input))
5285 {
5286 rtx tmp = operands[3];
5287 emit_insn (gen_extend<QHI:mode>di2 (tmp, input));
5288 emit_move_insn (di, tmp);
5289 }
5290 else
5291 {
5292 machine_mode vmode;
5293 rtx di_vector;
5295 emit_insn (gen_p9_lxsi<QHI:wd>zx (di, input));
5297 if (<MODE>mode == QImode)
5298 vmode = V16QImode;
5299 else if (<MODE>mode == HImode)
5300 vmode = V8HImode;
5301 else
5302 gcc_unreachable ();
5304 di_vector = gen_rtx_REG (vmode, REGNO (di));
5305 emit_insn (gen_vsx_sign_extend_<QHI:mode>_di (di, di_vector));
5306 }
5308 emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
5309 DONE;
5310 })
5312 (define_expand "floatuns<QHI:mode><FP_ISA3:mode>2"
5313 [(parallel [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "")
5314 (unsigned_float:FP_ISA3
5315 (match_operand:QHI 1 "input_operand" "")))
5316 (clobber (match_scratch:DI 2 ""))
5317 (clobber (match_scratch:DI 3 ""))])]
5318 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
5319 {
5320 if (MEM_P (operands[1]))
5321 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5322 })
5324 (define_insn_and_split "*floatuns<QHI:mode><FP_ISA3:mode>2_internal"
5325 [(set (match_operand:FP_ISA3 0 "vsx_register_operand" "=<Fv>,<Fv>")
5326 (unsigned_float:FP_ISA3
5327 (match_operand:QHI 1 "reg_or_indexed_operand" "r,Z")))
5328 (clobber (match_scratch:DI 2 "=wi,wi"))
5329 (clobber (match_scratch:DI 3 "=r,X"))]
5330 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
5331 "#"
5332 "&& reload_completed"
5333 [(const_int 0)]
5334 {
5335 rtx result = operands[0];
5336 rtx input = operands[1];
5337 rtx di = operands[2];
5338 rtx tmp = operands[3];
5340 if (!MEM_P (input))
5341 {
5342 emit_insn (gen_zero_extend<QHI:mode>di2 (tmp, input));
5343 emit_move_insn (di, tmp);
5344 }
5345 else
5346 emit_insn (gen_p9_lxsi<QHI:wd>zx (di, input));
5348 emit_insn (gen_floatdi<FP_ISA3:mode>2 (result, di));
5349 DONE;
5350 })
5352 (define_expand "fix_trunc<mode>si2"
5353 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5354 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5355 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5356 "
5357 {
5358 if (!<E500_CONVERT>)
5359 {
5360 rtx tmp, stack;
5362 if (TARGET_STFIWX)
5363 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5364 else
5365 {
5366 tmp = gen_reg_rtx (DImode);
5367 stack = rs6000_allocate_stack_temp (DImode, true, false);
5368 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5369 tmp, stack));
5370 }
5371 DONE;
5372 }
5373 }")
5375 ; Like the convert to float patterns, this insn must be split before
5376 ; register allocation so that it can allocate the memory slot if it
5377 ; needed
5378 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5379 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5380 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5381 (clobber (match_scratch:DI 2 "=d"))]
5382 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5383 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5384 && TARGET_STFIWX && can_create_pseudo_p ()"
5385 "#"
5386 ""
5387 [(pc)]
5388 {
5389 rtx dest = operands[0];
5390 rtx src = operands[1];
5391 rtx tmp = operands[2];
5393 if (GET_CODE (tmp) == SCRATCH)
5394 tmp = gen_reg_rtx (DImode);
5396 emit_insn (gen_fctiwz_<mode> (tmp, src));
5397 if (MEM_P (dest))
5398 {
5399 dest = rs6000_address_for_fpconvert (dest);
5400 emit_insn (gen_stfiwx (dest, tmp));
5401 DONE;
5402 }
5403 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5404 {
5405 dest = gen_lowpart (DImode, dest);
5406 emit_move_insn (dest, tmp);
5407 DONE;
5408 }
5409 else
5410 {
5411 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5412 emit_insn (gen_stfiwx (stack, tmp));
5413 emit_move_insn (dest, stack);
5414 DONE;
5415 }
5416 }
5417 [(set_attr "length" "12")
5418 (set_attr "type" "fp")])
5420 (define_insn_and_split "fix_trunc<mode>si2_internal"
5421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5422 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5423 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5424 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5425 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5426 "#"
5427 ""
5428 [(pc)]
5429 "
5430 {
5431 rtx lowword;
5432 gcc_assert (MEM_P (operands[3]));
5433 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5435 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5436 emit_move_insn (operands[3], operands[2]);
5437 emit_move_insn (operands[0], lowword);
5438 DONE;
5439 }"
5440 [(set_attr "length" "16")
5441 (set_attr "type" "fp")])
5443 (define_expand "fix_trunc<mode>di2"
5444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5445 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5446 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5447 && TARGET_FCFID"
5448 "")
5450 (define_insn "*fix_trunc<mode>di2_fctidz"
5451 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5452 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5453 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5454 && TARGET_FCFID"
5455 "@
5456 fctidz %0,%1
5457 xscvdpsxds %x0,%x1"
5458 [(set_attr "type" "fp")])
5460 (define_expand "fix_trunc<SFDF:mode><QHI:mode>2"
5461 [(use (match_operand:QHI 0 "rs6000_nonimmediate_operand" ""))
5462 (use (match_operand:SFDF 1 "vsx_register_operand" ""))]
5463 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
5464 {
5465 rtx op0 = operands[0];
5466 rtx op1 = operands[1];
5467 rtx di_tmp = gen_reg_rtx (DImode);
5469 if (MEM_P (op0))
5470 op0 = rs6000_address_for_fpconvert (op0);
5472 emit_insn (gen_fctiwz_<SFDF:mode> (di_tmp, op1));
5473 emit_insn (gen_p9_stxsi<QHI:wd>x (op0, di_tmp));
5474 DONE;
5475 })
5477 (define_expand "fixuns_trunc<mode>si2"
5478 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5479 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5480 "TARGET_HARD_FLOAT
5481 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
5482 || <E500_CONVERT>)"
5483 "
5484 {
5485 if (!<E500_CONVERT>)
5486 {
5487 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5488 DONE;
5489 }
5490 }")
5492 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
5493 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5494 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5495 (clobber (match_scratch:DI 2 "=d"))]
5496 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
5497 && TARGET_STFIWX && can_create_pseudo_p ()"
5498 "#"
5499 ""
5500 [(pc)]
5501 {
5502 rtx dest = operands[0];
5503 rtx src = operands[1];
5504 rtx tmp = operands[2];
5506 if (GET_CODE (tmp) == SCRATCH)
5507 tmp = gen_reg_rtx (DImode);
5509 emit_insn (gen_fctiwuz_<mode> (tmp, src));
5510 if (MEM_P (dest))
5511 {
5512 dest = rs6000_address_for_fpconvert (dest);
5513 emit_insn (gen_stfiwx (dest, tmp));
5514 DONE;
5515 }
5516 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5517 {
5518 dest = gen_lowpart (DImode, dest);
5519 emit_move_insn (dest, tmp);
5520 DONE;
5521 }
5522 else
5523 {
5524 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5525 emit_insn (gen_stfiwx (stack, tmp));
5526 emit_move_insn (dest, stack);
5527 DONE;
5528 }
5529 }
5530 [(set_attr "length" "12")
5531 (set_attr "type" "fp")])
5533 (define_expand "fixuns_trunc<mode>di2"
5534 [(set (match_operand:DI 0 "register_operand" "")
5535 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
5536 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
5537 "")
5539 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
5540 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5541 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5542 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5543 && TARGET_FCTIDUZ"
5544 "@
5545 fctiduz %0,%1
5546 xscvdpuxds %x0,%x1"
5547 [(set_attr "type" "fp")])
5549 (define_expand "fixuns_trunc<SFDF:mode><QHI:mode>2"
5550 [(use (match_operand:QHI 0 "rs6000_nonimmediate_operand" ""))
5551 (use (match_operand:SFDF 1 "vsx_register_operand" ""))]
5552 "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
5553 {
5554 rtx op0 = operands[0];
5555 rtx op1 = operands[1];
5556 rtx di_tmp = gen_reg_rtx (DImode);
5558 if (MEM_P (op0))
5559 op0 = rs6000_address_for_fpconvert (op0);
5561 emit_insn (gen_fctiwuz_<SFDF:mode> (di_tmp, op1));
5562 emit_insn (gen_p9_stxsi<QHI:wd>x (op0, di_tmp));
5563 DONE;
5564 })
5566 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5567 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5568 ; because the first makes it clear that operand 0 is not live
5569 ; before the instruction.
5570 (define_insn "fctiwz_<mode>"
5571 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5572 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5573 UNSPEC_FCTIWZ))]
5574 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5575 "@
5576 fctiwz %0,%1
5577 xscvdpsxws %x0,%x1"
5578 [(set_attr "type" "fp")])
5580 (define_insn "fctiwuz_<mode>"
5581 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
5582 (unspec:DI [(unsigned_fix:SI
5583 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
5584 UNSPEC_FCTIWUZ))]
5585 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
5586 "@
5587 fctiwuz %0,%1
5588 xscvdpuxws %x0,%x1"
5589 [(set_attr "type" "fp")])
5591 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
5592 ;; since the friz instruction does not truncate the value if the floating
5593 ;; point value is < LONG_MIN or > LONG_MAX.
5594 (define_insn "*friz"
5595 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5596 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
5597 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
5598 && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
5599 "@
5600 friz %0,%1
5601 xsrdpiz %x0,%x1"
5602 [(set_attr "type" "fp")])
5604 ;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode. This
5605 ;; optimization prevents on ISA 2.06 systems and earlier having to store the
5606 ;; value from the FPR/vector unit to the stack, load the value into a GPR, sign
5607 ;; extend it, store it back on the stack from the GPR, load it back into the
5608 ;; FP/vector unit to do the rounding. If we have direct move (ISA 2.07),
5609 ;; disable using store and load to sign/zero extend the value.
5610 (define_insn_and_split "*round32<mode>2_fprs"
5611 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5612 (float:SFDF
5613 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5614 (clobber (match_scratch:DI 2 "=d"))
5615 (clobber (match_scratch:DI 3 "=d"))]
5616 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5617 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
5618 && !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
5619 "#"
5620 ""
5621 [(pc)]
5622 {
5623 rtx dest = operands[0];
5624 rtx src = operands[1];
5625 rtx tmp1 = operands[2];
5626 rtx tmp2 = operands[3];
5627 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5629 if (GET_CODE (tmp1) == SCRATCH)
5630 tmp1 = gen_reg_rtx (DImode);
5631 if (GET_CODE (tmp2) == SCRATCH)
5632 tmp2 = gen_reg_rtx (DImode);
5634 emit_insn (gen_fctiwz_<mode> (tmp1, src));
5635 emit_insn (gen_stfiwx (stack, tmp1));
5636 emit_insn (gen_lfiwax (tmp2, stack));
5637 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5638 DONE;
5639 }
5640 [(set_attr "type" "fpload")
5641 (set_attr "length" "16")])
5643 (define_insn_and_split "*roundu32<mode>2_fprs"
5644 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5645 (unsigned_float:SFDF
5646 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
5647 (clobber (match_scratch:DI 2 "=d"))
5648 (clobber (match_scratch:DI 3 "=d"))]
5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5650 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
5651 && can_create_pseudo_p ()"
5652 "#"
5653 ""
5654 [(pc)]
5655 {
5656 rtx dest = operands[0];
5657 rtx src = operands[1];
5658 rtx tmp1 = operands[2];
5659 rtx tmp2 = operands[3];
5660 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5662 if (GET_CODE (tmp1) == SCRATCH)
5663 tmp1 = gen_reg_rtx (DImode);
5664 if (GET_CODE (tmp2) == SCRATCH)
5665 tmp2 = gen_reg_rtx (DImode);
5667 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
5668 emit_insn (gen_stfiwx (stack, tmp1));
5669 emit_insn (gen_lfiwzx (tmp2, stack));
5670 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
5671 DONE;
5672 }
5673 [(set_attr "type" "fpload")
5674 (set_attr "length" "16")])
5676 ;; No VSX equivalent to fctid
5677 (define_insn "lrint<mode>di2"
5678 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5679 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5680 UNSPEC_FCTID))]
5681 "TARGET_<MODE>_FPR && TARGET_FPRND"
5682 "fctid %0,%1"
5683 [(set_attr "type" "fp")])
5685 (define_insn "btrunc<mode>2"
5686 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5687 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5688 UNSPEC_FRIZ))]
5689 "TARGET_<MODE>_FPR && TARGET_FPRND"
5690 "@
5691 friz %0,%1
5692 xsrdpiz %x0,%x1"
5693 [(set_attr "type" "fp")
5694 (set_attr "fp_type" "fp_addsub_<Fs>")])
5696 (define_insn "ceil<mode>2"
5697 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5698 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5699 UNSPEC_FRIP))]
5700 "TARGET_<MODE>_FPR && TARGET_FPRND"
5701 "@
5702 frip %0,%1
5703 xsrdpip %x0,%x1"
5704 [(set_attr "type" "fp")
5705 (set_attr "fp_type" "fp_addsub_<Fs>")])
5707 (define_insn "floor<mode>2"
5708 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5709 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5710 UNSPEC_FRIM))]
5711 "TARGET_<MODE>_FPR && TARGET_FPRND"
5712 "@
5713 frim %0,%1
5714 xsrdpim %x0,%x1"
5715 [(set_attr "type" "fp")
5716 (set_attr "fp_type" "fp_addsub_<Fs>")])
5718 ;; No VSX equivalent to frin
5719 (define_insn "round<mode>2"
5720 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5721 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
5722 UNSPEC_FRIN))]
5723 "TARGET_<MODE>_FPR && TARGET_FPRND"
5724 "frin %0,%1"
5725 [(set_attr "type" "fp")
5726 (set_attr "fp_type" "fp_addsub_<Fs>")])
5728 (define_insn "*xsrdpi<mode>2"
5729 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
5730 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv>")]
5731 UNSPEC_XSRDPI))]
5732 "TARGET_<MODE>_FPR && TARGET_VSX"
5733 "xsrdpi %x0,%x1"
5734 [(set_attr "type" "fp")
5735 (set_attr "fp_type" "fp_addsub_<Fs>")])
5737 (define_expand "lround<mode>di2"
5738 [(set (match_dup 2)
5739 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
5740 UNSPEC_XSRDPI))
5741 (set (match_operand:DI 0 "gpc_reg_operand" "")
5742 (unspec:DI [(match_dup 2)]
5743 UNSPEC_FCTID))]
5744 "TARGET_<MODE>_FPR && TARGET_VSX"
5745 {
5746 operands[2] = gen_reg_rtx (<MODE>mode);
5747 })
5749 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5750 (define_insn "stfiwx"
5751 [(set (match_operand:SI 0 "memory_operand" "=Z,Z")
5752 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d,wv")]
5753 UNSPEC_STFIWX))]
5754 "TARGET_PPC_GFXOPT"
5755 "@
5756 stfiwx %1,%y0
5757 stxsiwx %x1,%y0"
5758 [(set_attr "type" "fpstore")])
5760 ;; If we don't have a direct conversion to single precision, don't enable this
5761 ;; conversion for 32-bit without fast math, because we don't have the insn to
5762 ;; generate the fixup swizzle to avoid double rounding problems.
5763 (define_expand "floatsisf2"
5764 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5765 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5766 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5767 && (!TARGET_FPRS
5768 || (TARGET_FPRS
5769 && ((TARGET_FCFIDS && TARGET_LFIWAX)
5770 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5771 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5772 "
5773 {
5774 if (!TARGET_FPRS)
5775 {
5776 if (!REG_P (operands[1]))
5777 operands[1] = force_reg (SImode, operands[1]);
5778 }
5779 else if (TARGET_FCFIDS && TARGET_LFIWAX)
5780 {
5781 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
5782 DONE;
5783 }
5784 else if (TARGET_FCFID && TARGET_LFIWAX)
5785 {
5786 rtx dfreg = gen_reg_rtx (DFmode);
5787 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
5788 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
5789 DONE;
5790 }
5791 else
5792 {
5793 rtx dreg = operands[1];
5794 if (!REG_P (dreg))
5795 dreg = force_reg (SImode, dreg);
5796 dreg = convert_to_mode (DImode, dreg, false);
5797 emit_insn (gen_floatdisf2 (operands[0], dreg));
5798 DONE;
5799 }
5800 }")
5802 (define_expand "floatdidf2"
5803 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5804 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
5805 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5806 "")
5808 (define_insn "*floatdidf2_fpr"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5810 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
5811 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
5812 "@
5813 fcfid %0,%1
5814 xscvsxddp %x0,%x1"
5815 [(set_attr "type" "fp")])
5817 ; Allow the combiner to merge source memory operands to the conversion so that
5818 ; the optimizer/register allocator doesn't try to load the value too early in a
5819 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
5820 ; hit. We will split after reload to avoid the trip through the GPRs
5822 (define_insn_and_split "*floatdidf2_mem"
5823 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5824 (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
5825 (clobber (match_scratch:DI 2 "=d,wi"))]
5826 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
5827 "#"
5828 "&& reload_completed"
5829 [(set (match_dup 2) (match_dup 1))
5830 (set (match_dup 0) (float:DF (match_dup 2)))]
5831 ""
5832 [(set_attr "length" "8")
5833 (set_attr "type" "fpload")])
5835 (define_expand "floatunsdidf2"
5836 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5837 (unsigned_float:DF
5838 (match_operand:DI 1 "gpc_reg_operand" "")))]
5839 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
5840 "")
5842 (define_insn "*floatunsdidf2_fcfidu"
5843 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5844 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
5845 "TARGET_HARD_FLOAT && TARGET_FCFIDU"
5846 "@
5847 fcfidu %0,%1
5848 xscvuxddp %x0,%x1"
5849 [(set_attr "type" "fp")
5850 (set_attr "length" "4")])
5852 (define_insn_and_split "*floatunsdidf2_mem"
5853 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
5854 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
5855 (clobber (match_scratch:DI 2 "=d,wi"))]
5856 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
5857 "#"
5858 "&& reload_completed"
5859 [(set (match_dup 2) (match_dup 1))
5860 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
5861 ""
5862 [(set_attr "length" "8")
5863 (set_attr "type" "fpload")])
5865 (define_expand "floatdisf2"
5866 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5867 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5868 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5869 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
5870 "
5871 {
5872 if (!TARGET_FCFIDS)
5873 {
5874 rtx val = operands[1];
5875 if (!flag_unsafe_math_optimizations)
5876 {
5877 rtx label = gen_label_rtx ();
5878 val = gen_reg_rtx (DImode);
5879 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5880 emit_label (label);
5881 }
5882 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5883 DONE;
5884 }
5885 }")
5887 (define_insn "floatdisf2_fcfids"
5888 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
5889 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
5890 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5891 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5892 "@
5893 fcfids %0,%1
5894 xscvsxdsp %x0,%x1"
5895 [(set_attr "type" "fp")])
5897 (define_insn_and_split "*floatdisf2_mem"
5898 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
5899 (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
5900 (clobber (match_scratch:DI 2 "=d,d,wi"))]
5901 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5902 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
5903 "#"
5904 "&& reload_completed"
5905 [(pc)]
5906 "
5907 {
5908 emit_move_insn (operands[2], operands[1]);
5909 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
5910 DONE;
5911 }"
5912 [(set_attr "length" "8")])
5914 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5915 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5916 ;; from double rounding.
5917 ;; Instead of creating a new cpu type for two FP operations, just use fp
5918 (define_insn_and_split "floatdisf2_internal1"
5919 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5920 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
5921 (clobber (match_scratch:DF 2 "=d"))]
5922 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5923 && !TARGET_FCFIDS"
5924 "#"
5925 "&& reload_completed"
5926 [(set (match_dup 2)
5927 (float:DF (match_dup 1)))
5928 (set (match_dup 0)
5929 (float_truncate:SF (match_dup 2)))]
5930 ""
5931 [(set_attr "length" "8")
5932 (set_attr "type" "fp")])
5934 ;; Twiddles bits to avoid double rounding.
5935 ;; Bits that might be truncated when converting to DFmode are replaced
5936 ;; by a bit that won't be lost at that stage, but is below the SFmode
5937 ;; rounding position.
5938 (define_expand "floatdisf2_internal2"
5939 [(parallel [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
5940 (const_int 53)))
5941 (clobber (reg:DI CA_REGNO))])
5942 (set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
5943 (const_int 2047)))
5944 (set (match_dup 3) (plus:DI (match_dup 3)
5945 (const_int 1)))
5946 (set (match_dup 0) (plus:DI (match_dup 0)
5947 (const_int 2047)))
5948 (set (match_dup 4) (compare:CCUNS (match_dup 3)
5949 (const_int 2)))
5950 (set (match_dup 0) (ior:DI (match_dup 0)
5951 (match_dup 1)))
5952 (set (match_dup 0) (and:DI (match_dup 0)
5953 (const_int -2048)))
5954 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
5955 (label_ref (match_operand:DI 2 "" ""))
5956 (pc)))
5957 (set (match_dup 0) (match_dup 1))]
5958 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5959 && !TARGET_FCFIDS"
5960 "
5961 {
5962 operands[3] = gen_reg_rtx (DImode);
5963 operands[4] = gen_reg_rtx (CCUNSmode);
5964 }")
5966 (define_expand "floatunsdisf2"
5967 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5968 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5969 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5970 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
5971 "")
5973 (define_insn "floatunsdisf2_fcfidus"
5974 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wu")
5975 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d,wi")))]
5976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5977 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
5978 "@
5979 fcfidus %0,%1
5980 xscvuxdsp %x0,%x1"
5981 [(set_attr "type" "fp")])
5983 (define_insn_and_split "*floatunsdisf2_mem"
5984 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy,wy")
5985 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
5986 (clobber (match_scratch:DI 2 "=d,d,wi"))]
5987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5988 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
5989 "#"
5990 "&& reload_completed"
5991 [(pc)]
5992 "
5993 {
5994 emit_move_insn (operands[2], operands[1]);
5995 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
5996 DONE;
5997 }"
5998 [(set_attr "length" "8")
5999 (set_attr "type" "fpload")])
6000 \f
6001 ;; Define the TImode operations that can be done in a small number
6002 ;; of instructions. The & constraints are to prevent the register
6003 ;; allocator from allocating registers that overlap with the inputs
6004 ;; (for example, having an input in 7,8 and an output in 6,7). We
6005 ;; also allow for the output being the same as one of the inputs.
6007 (define_expand "addti3"
6008 [(set (match_operand:TI 0 "gpc_reg_operand" "")
6009 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "")
6010 (match_operand:TI 2 "reg_or_short_operand" "")))]
6011 "TARGET_64BIT"
6012 {
6013 rtx lo0 = gen_lowpart (DImode, operands[0]);
6014 rtx lo1 = gen_lowpart (DImode, operands[1]);
6015 rtx lo2 = gen_lowpart (DImode, operands[2]);
6016 rtx hi0 = gen_highpart (DImode, operands[0]);
6017 rtx hi1 = gen_highpart (DImode, operands[1]);
6018 rtx hi2 = gen_highpart_mode (DImode, TImode, operands[2]);
6020 if (!reg_or_short_operand (lo2, DImode))
6021 lo2 = force_reg (DImode, lo2);
6022 if (!adde_operand (hi2, DImode))
6023 hi2 = force_reg (DImode, hi2);
6025 emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
6026 emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
6027 DONE;
6028 })
6030 (define_expand "subti3"
6031 [(set (match_operand:TI 0 "gpc_reg_operand" "")
6032 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "")
6033 (match_operand:TI 2 "gpc_reg_operand" "")))]
6034 "TARGET_64BIT"
6035 {
6036 rtx lo0 = gen_lowpart (DImode, operands[0]);
6037 rtx lo1 = gen_lowpart (DImode, operands[1]);
6038 rtx lo2 = gen_lowpart (DImode, operands[2]);
6039 rtx hi0 = gen_highpart (DImode, operands[0]);
6040 rtx hi1 = gen_highpart_mode (DImode, TImode, operands[1]);
6041 rtx hi2 = gen_highpart (DImode, operands[2]);
6043 if (!reg_or_short_operand (lo1, DImode))
6044 lo1 = force_reg (DImode, lo1);
6045 if (!adde_operand (hi1, DImode))
6046 hi1 = force_reg (DImode, hi1);
6048 emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
6049 emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
6050 DONE;
6051 })
6052 \f
6053 ;; 128-bit logical operations expanders
6055 (define_expand "and<mode>3"
6056 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6057 (and:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
6058 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
6059 ""
6060 "")
6062 (define_expand "ior<mode>3"
6063 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6064 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
6065 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
6066 ""
6067 "")
6069 (define_expand "xor<mode>3"
6070 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6071 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
6072 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
6073 ""
6074 "")
6076 (define_expand "one_cmpl<mode>2"
6077 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6078 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
6079 ""
6080 "")
6082 (define_expand "nor<mode>3"
6083 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6084 (and:BOOL_128
6085 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
6086 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
6087 ""
6088 "")
6090 (define_expand "andc<mode>3"
6091 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6092 (and:BOOL_128
6093 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
6094 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
6095 ""
6096 "")
6098 ;; Power8 vector logical instructions.
6099 (define_expand "eqv<mode>3"
6100 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6101 (not:BOOL_128
6102 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
6103 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
6104 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
6105 "")
6107 ;; Rewrite nand into canonical form
6108 (define_expand "nand<mode>3"
6109 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6110 (ior:BOOL_128
6111 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
6112 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
6113 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
6114 "")
6116 ;; The canonical form is to have the negated element first, so we need to
6117 ;; reverse arguments.
6118 (define_expand "orc<mode>3"
6119 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
6120 (ior:BOOL_128
6121 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
6122 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
6123 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
6124 "")
6126 ;; 128-bit logical operations insns and split operations
6127 (define_insn_and_split "*and<mode>3_internal"
6128 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6129 (and:BOOL_128
6130 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
6131 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))]
6132 ""
6133 {
6134 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
6135 return "xxland %x0,%x1,%x2";
6137 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
6138 return "vand %0,%1,%2";
6140 return "#";
6141 }
6142 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
6143 [(const_int 0)]
6144 {
6145 rs6000_split_logical (operands, AND, false, false, false);
6146 DONE;
6147 }
6148 [(set (attr "type")
6149 (if_then_else
6150 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6151 (const_string "veclogical")
6152 (const_string "integer")))
6153 (set (attr "length")
6154 (if_then_else
6155 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6156 (const_string "4")
6157 (if_then_else
6158 (match_test "TARGET_POWERPC64")
6159 (const_string "8")
6160 (const_string "16"))))])
6162 ;; 128-bit IOR/XOR
6163 (define_insn_and_split "*bool<mode>3_internal"
6164 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6165 (match_operator:BOOL_128 3 "boolean_or_operator"
6166 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
6167 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
6168 ""
6169 {
6170 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
6171 return "xxl%q3 %x0,%x1,%x2";
6173 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
6174 return "v%q3 %0,%1,%2";
6176 return "#";
6177 }
6178 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
6179 [(const_int 0)]
6180 {
6181 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false);
6182 DONE;
6183 }
6184 [(set (attr "type")
6185 (if_then_else
6186 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6187 (const_string "veclogical")
6188 (const_string "integer")))
6189 (set (attr "length")
6190 (if_then_else
6191 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6192 (const_string "4")
6193 (if_then_else
6194 (match_test "TARGET_POWERPC64")
6195 (const_string "8")
6196 (const_string "16"))))])
6198 ;; 128-bit ANDC/ORC
6199 (define_insn_and_split "*boolc<mode>3_internal1"
6200 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6201 (match_operator:BOOL_128 3 "boolean_operator"
6202 [(not:BOOL_128
6203 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
6204 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
6205 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
6206 {
6207 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
6208 return "xxl%q3 %x0,%x1,%x2";
6210 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
6211 return "v%q3 %0,%1,%2";
6213 return "#";
6214 }
6215 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
6216 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
6217 [(const_int 0)]
6218 {
6219 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
6220 DONE;
6221 }
6222 [(set (attr "type")
6223 (if_then_else
6224 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6225 (const_string "veclogical")
6226 (const_string "integer")))
6227 (set (attr "length")
6228 (if_then_else
6229 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6230 (const_string "4")
6231 (if_then_else
6232 (match_test "TARGET_POWERPC64")
6233 (const_string "8")
6234 (const_string "16"))))])
6236 (define_insn_and_split "*boolc<mode>3_internal2"
6237 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
6238 (match_operator:TI2 3 "boolean_operator"
6239 [(not:TI2
6240 (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
6241 (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
6242 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
6243 "#"
6244 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
6245 [(const_int 0)]
6246 {
6247 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
6248 DONE;
6249 }
6250 [(set_attr "type" "integer")
6251 (set (attr "length")
6252 (if_then_else
6253 (match_test "TARGET_POWERPC64")
6254 (const_string "8")
6255 (const_string "16")))])
6257 ;; 128-bit NAND/NOR
6258 (define_insn_and_split "*boolcc<mode>3_internal1"
6259 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6260 (match_operator:BOOL_128 3 "boolean_operator"
6261 [(not:BOOL_128
6262 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
6263 (not:BOOL_128
6264 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
6265 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
6266 {
6267 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
6268 return "xxl%q3 %x0,%x1,%x2";
6270 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
6271 return "v%q3 %0,%1,%2";
6273 return "#";
6274 }
6275 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
6276 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
6277 [(const_int 0)]
6278 {
6279 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
6280 DONE;
6281 }
6282 [(set (attr "type")
6283 (if_then_else
6284 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6285 (const_string "veclogical")
6286 (const_string "integer")))
6287 (set (attr "length")
6288 (if_then_else
6289 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6290 (const_string "4")
6291 (if_then_else
6292 (match_test "TARGET_POWERPC64")
6293 (const_string "8")
6294 (const_string "16"))))])
6296 (define_insn_and_split "*boolcc<mode>3_internal2"
6297 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
6298 (match_operator:TI2 3 "boolean_operator"
6299 [(not:TI2
6300 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
6301 (not:TI2
6302 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
6303 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
6304 "#"
6305 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
6306 [(const_int 0)]
6307 {
6308 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true);
6309 DONE;
6310 }
6311 [(set_attr "type" "integer")
6312 (set (attr "length")
6313 (if_then_else
6314 (match_test "TARGET_POWERPC64")
6315 (const_string "8")
6316 (const_string "16")))])
6319 ;; 128-bit EQV
6320 (define_insn_and_split "*eqv<mode>3_internal1"
6321 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6322 (not:BOOL_128
6323 (xor:BOOL_128
6324 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
6325 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
6326 "TARGET_P8_VECTOR"
6327 {
6328 if (vsx_register_operand (operands[0], <MODE>mode))
6329 return "xxleqv %x0,%x1,%x2";
6331 return "#";
6332 }
6333 "TARGET_P8_VECTOR && reload_completed
6334 && int_reg_operand (operands[0], <MODE>mode)"
6335 [(const_int 0)]
6336 {
6337 rs6000_split_logical (operands, XOR, true, false, false);
6338 DONE;
6339 }
6340 [(set (attr "type")
6341 (if_then_else
6342 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6343 (const_string "veclogical")
6344 (const_string "integer")))
6345 (set (attr "length")
6346 (if_then_else
6347 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6348 (const_string "4")
6349 (if_then_else
6350 (match_test "TARGET_POWERPC64")
6351 (const_string "8")
6352 (const_string "16"))))])
6354 (define_insn_and_split "*eqv<mode>3_internal2"
6355 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
6356 (not:TI2
6357 (xor:TI2
6358 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
6359 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
6360 "!TARGET_P8_VECTOR"
6361 "#"
6362 "reload_completed && !TARGET_P8_VECTOR"
6363 [(const_int 0)]
6364 {
6365 rs6000_split_logical (operands, XOR, true, false, false);
6366 DONE;
6367 }
6368 [(set_attr "type" "integer")
6369 (set (attr "length")
6370 (if_then_else
6371 (match_test "TARGET_POWERPC64")
6372 (const_string "8")
6373 (const_string "16")))])
6375 ;; 128-bit one's complement
6376 (define_insn_and_split "*one_cmpl<mode>3_internal"
6377 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
6378 (not:BOOL_128
6379 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
6380 ""
6381 {
6382 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
6383 return "xxlnor %x0,%x1,%x1";
6385 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
6386 return "vnor %0,%1,%1";
6388 return "#";
6389 }
6390 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
6391 [(const_int 0)]
6392 {
6393 rs6000_split_logical (operands, NOT, false, false, false);
6394 DONE;
6395 }
6396 [(set (attr "type")
6397 (if_then_else
6398 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6399 (const_string "veclogical")
6400 (const_string "integer")))
6401 (set (attr "length")
6402 (if_then_else
6403 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
6404 (const_string "4")
6405 (if_then_else
6406 (match_test "TARGET_POWERPC64")
6407 (const_string "8")
6408 (const_string "16"))))])
6410 \f
6411 ;; Now define ways of moving data around.
6413 ;; Set up a register with a value from the GOT table
6415 (define_expand "movsi_got"
6416 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6417 (unspec:SI [(match_operand:SI 1 "got_operand" "")
6418 (match_dup 2)] UNSPEC_MOVSI_GOT))]
6419 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
6420 "
6421 {
6422 if (GET_CODE (operands[1]) == CONST)
6423 {
6424 rtx offset = const0_rtx;
6425 HOST_WIDE_INT value;
6427 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
6428 value = INTVAL (offset);
6429 if (value != 0)
6430 {
6431 rtx tmp = (!can_create_pseudo_p ()
6432 ? operands[0]
6433 : gen_reg_rtx (Pmode));
6434 emit_insn (gen_movsi_got (tmp, operands[1]));
6435 emit_insn (gen_addsi3 (operands[0], tmp, offset));
6436 DONE;
6437 }
6438 }
6440 operands[2] = rs6000_got_register (operands[1]);
6441 }")
6443 (define_insn "*movsi_got_internal"
6444 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6445 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
6446 (match_operand:SI 2 "gpc_reg_operand" "b")]
6447 UNSPEC_MOVSI_GOT))]
6448 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
6449 "lwz %0,%a1@got(%2)"
6450 [(set_attr "type" "load")])
6452 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
6453 ;; didn't get allocated to a hard register.
6454 (define_split
6455 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6456 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
6457 (match_operand:SI 2 "memory_operand" "")]
6458 UNSPEC_MOVSI_GOT))]
6459 "DEFAULT_ABI == ABI_V4
6460 && flag_pic == 1
6461 && (reload_in_progress || reload_completed)"
6462 [(set (match_dup 0) (match_dup 2))
6463 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
6464 UNSPEC_MOVSI_GOT))]
6465 "")
6467 ;; For SI, we special-case integers that can't be loaded in one insn. We
6468 ;; do the load 16-bits at a time. We could do this by loading from memory,
6469 ;; and this is even supposed to be faster, but it is simpler not to get
6470 ;; integers in the TOC.
6471 (define_insn "movsi_low"
6472 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6473 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
6474 (match_operand 2 "" ""))))]
6475 "TARGET_MACHO && ! TARGET_64BIT"
6476 "lwz %0,lo16(%2)(%1)"
6477 [(set_attr "type" "load")
6478 (set_attr "length" "4")])
6480 (define_insn "*movsi_internal1"
6481 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
6482 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
6483 "!TARGET_SINGLE_FPU &&
6484 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
6485 "@
6486 mr %0,%1
6487 la %0,%a1
6488 lwz%U1%X1 %0,%1
6489 stw%U0%X0 %1,%0
6490 li %0,%1
6491 lis %0,%v1
6492 #
6493 mf%1 %0
6494 mt%0 %1
6495 mt%0 %1
6496 nop"
6497 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*")
6498 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
6500 (define_insn "*movsi_internal1_single"
6501 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
6502 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
6503 "TARGET_SINGLE_FPU &&
6504 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
6505 "@
6506 mr %0,%1
6507 la %0,%a1
6508 lwz%U1%X1 %0,%1
6509 stw%U0%X0 %1,%0
6510 li %0,%1
6511 lis %0,%v1
6512 #
6513 mf%1 %0
6514 mt%0 %1
6515 mt%0 %1
6516 nop
6517 stfs%U0%X0 %1,%0
6518 lfs%U1%X1 %0,%1"
6519 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,fpstore,fpload")
6520 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
6522 ;; Split a load of a large constant into the appropriate two-insn
6523 ;; sequence.
6525 (define_split
6526 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6527 (match_operand:SI 1 "const_int_operand" ""))]
6528 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
6529 && (INTVAL (operands[1]) & 0xffff) != 0"
6530 [(set (match_dup 0)
6531 (match_dup 2))
6532 (set (match_dup 0)
6533 (ior:SI (match_dup 0)
6534 (match_dup 3)))]
6535 "
6536 {
6537 if (rs6000_emit_set_const (operands[0], operands[1]))
6538 DONE;
6539 else
6540 FAIL;
6541 }")
6543 (define_insn "*mov<mode>_internal2"
6544 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
6545 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
6546 (const_int 0)))
6547 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
6548 ""
6549 "@
6550 cmp<wd>i %2,%0,0
6551 mr. %0,%1
6552 #"
6553 [(set_attr "type" "cmp,logical,cmp")
6554 (set_attr "dot" "yes")
6555 (set_attr "length" "4,4,8")])
6557 (define_split
6558 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
6559 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
6560 (const_int 0)))
6561 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
6562 "reload_completed"
6563 [(set (match_dup 0) (match_dup 1))
6564 (set (match_dup 2)
6565 (compare:CC (match_dup 0)
6566 (const_int 0)))]
6567 "")
6568 \f
6569 (define_insn "*movhi_internal"
6570 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
6571 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
6572 "gpc_reg_operand (operands[0], HImode)
6573 || gpc_reg_operand (operands[1], HImode)"
6574 "@
6575 mr %0,%1
6576 lhz%U1%X1 %0,%1
6577 sth%U0%X0 %1,%0
6578 li %0,%w1
6579 mf%1 %0
6580 mt%0 %1
6581 nop"
6582 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
6584 (define_expand "mov<mode>"
6585 [(set (match_operand:INT 0 "general_operand" "")
6586 (match_operand:INT 1 "any_operand" ""))]
6587 ""
6588 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
6590 (define_insn "*movqi_internal"
6591 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
6592 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
6593 "gpc_reg_operand (operands[0], QImode)
6594 || gpc_reg_operand (operands[1], QImode)"
6595 "@
6596 mr %0,%1
6597 lbz%U1%X1 %0,%1
6598 stb%U0%X0 %1,%0
6599 li %0,%1
6600 mf%1 %0
6601 mt%0 %1
6602 nop"
6603 [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")])
6604 \f
6605 ;; Here is how to move condition codes around. When we store CC data in
6606 ;; an integer register or memory, we store just the high-order 4 bits.
6607 ;; This lets us not shift in the most common case of CR0.
6608 (define_expand "movcc"
6609 [(set (match_operand:CC 0 "nonimmediate_operand" "")
6610 (match_operand:CC 1 "nonimmediate_operand" ""))]
6611 ""
6612 "")
6614 (define_insn "*movcc_internal1"
6615 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
6616 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
6617 "register_operand (operands[0], CCmode)
6618 || register_operand (operands[1], CCmode)"
6619 "@
6620 mcrf %0,%1
6621 mtcrf 128,%1
6622 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
6623 crxor %0,%0,%0
6624 mfcr %0%Q1
6625 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
6626 mr %0,%1
6627 li %0,%1
6628 mf%1 %0
6629 mt%0 %1
6630 lwz%U1%X1 %0,%1
6631 stw%U0%X0 %1,%0"
6632 [(set (attr "type")
6633 (cond [(eq_attr "alternative" "0,3")
6634 (const_string "cr_logical")
6635 (eq_attr "alternative" "1,2")
6636 (const_string "mtcr")
6637 (eq_attr "alternative" "6,7")
6638 (const_string "integer")
6639 (eq_attr "alternative" "8")
6640 (const_string "mfjmpr")
6641 (eq_attr "alternative" "9")
6642 (const_string "mtjmpr")
6643 (eq_attr "alternative" "10")
6644 (const_string "load")
6645 (eq_attr "alternative" "11")
6646 (const_string "store")
6647 (match_test "TARGET_MFCRF")
6648 (const_string "mfcrf")
6649 ]
6650 (const_string "mfcr")))
6651 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
6652 \f
6653 ;; For floating-point, we normally deal with the floating-point registers
6654 ;; unless -msoft-float is used. The sole exception is that parameter passing
6655 ;; can produce floating-point values in fixed-point registers. Unless the
6656 ;; value is a simple constant or already in memory, we deal with this by
6657 ;; allocating memory and copying the value explicitly via that memory location.
6659 ;; Move 32-bit binary/decimal floating point
6660 (define_expand "mov<mode>"
6661 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
6662 (match_operand:FMOVE32 1 "any_operand" ""))]
6663 "<fmove_ok>"
6664 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
6666 (define_split
6667 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
6668 (match_operand:FMOVE32 1 "const_double_operand" ""))]
6669 "reload_completed
6670 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6671 || (GET_CODE (operands[0]) == SUBREG
6672 && GET_CODE (SUBREG_REG (operands[0])) == REG
6673 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6674 [(set (match_dup 2) (match_dup 3))]
6675 "
6676 {
6677 long l;
6679 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
6681 if (! TARGET_POWERPC64)
6682 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
6683 else
6684 operands[2] = gen_lowpart (SImode, operands[0]);
6686 operands[3] = gen_int_mode (l, SImode);
6687 }")
6689 (define_insn "mov<mode>_hardfloat"
6690 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,!r,<f32_lr>,<f32_lr2>,<f32_sm>,<f32_sm2>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h")
6691 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,<zero_fp>,<zero_fp>,<f32_lm>,<f32_lm2>,<f32_sr>,<f32_sr2>,Z,<f32_av>,r,<f32_dm>,r,h,0"))]
6692 "(gpc_reg_operand (operands[0], <MODE>mode)
6693 || gpc_reg_operand (operands[1], <MODE>mode))
6694 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
6695 "@
6696 mr %0,%1
6697 lwz%U1%X1 %0,%1
6698 stw%U0%X0 %1,%0
6699 fmr %0,%1
6700 xscpsgndp %x0,%x1,%x1
6701 xxlxor %x0,%x0,%x0
6702 li %0,0
6703 <f32_li>
6704 <f32_li2>
6705 <f32_si>
6706 <f32_si2>
6707 <f32_lv>
6708 <f32_sv>
6709 mtvsrwz %x0,%1
6710 mfvsrwz %0,%x1
6711 mt%0 %1
6712 mf%1 %0
6713 nop"
6714 [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*")
6715 (set_attr "length" "4")])
6717 (define_insn "*mov<mode>_softfloat"
6718 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
6719 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
6720 "(gpc_reg_operand (operands[0], <MODE>mode)
6721 || gpc_reg_operand (operands[1], <MODE>mode))
6722 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
6723 "@
6724 mr %0,%1
6725 mt%0 %1
6726 mf%1 %0
6727 lwz%U1%X1 %0,%1
6728 stw%U0%X0 %1,%0
6729 li %0,%1
6730 lis %0,%v1
6731 #
6732 #
6733 nop"
6734 [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
6735 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
6737 \f
6738 ;; Move 64-bit binary/decimal floating point
6739 (define_expand "mov<mode>"
6740 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
6741 (match_operand:FMOVE64 1 "any_operand" ""))]
6742 ""
6743 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
6745 (define_split
6746 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
6747 (match_operand:FMOVE64 1 "const_int_operand" ""))]
6748 "! TARGET_POWERPC64 && reload_completed
6749 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6750 || (GET_CODE (operands[0]) == SUBREG
6751 && GET_CODE (SUBREG_REG (operands[0])) == REG
6752 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6753 [(set (match_dup 2) (match_dup 4))
6754 (set (match_dup 3) (match_dup 1))]
6755 "
6756 {
6757 int endian = (WORDS_BIG_ENDIAN == 0);
6758 HOST_WIDE_INT value = INTVAL (operands[1]);
6760 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
6761 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
6762 operands[4] = GEN_INT (value >> 32);
6763 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
6764 }")
6766 (define_split
6767 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
6768 (match_operand:FMOVE64 1 "const_double_operand" ""))]
6769 "! TARGET_POWERPC64 && reload_completed
6770 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6771 || (GET_CODE (operands[0]) == SUBREG
6772 && GET_CODE (SUBREG_REG (operands[0])) == REG
6773 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6774 [(set (match_dup 2) (match_dup 4))
6775 (set (match_dup 3) (match_dup 5))]
6776 "
6777 {
6778 int endian = (WORDS_BIG_ENDIAN == 0);
6779 long l[2];
6781 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
6783 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
6784 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
6785 operands[4] = gen_int_mode (l[endian], SImode);
6786 operands[5] = gen_int_mode (l[1 - endian], SImode);
6787 }")
6789 (define_split
6790 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
6791 (match_operand:FMOVE64 1 "const_double_operand" ""))]
6792 "TARGET_POWERPC64 && reload_completed
6793 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
6794 || (GET_CODE (operands[0]) == SUBREG
6795 && GET_CODE (SUBREG_REG (operands[0])) == REG
6796 && REGNO (SUBREG_REG (operands[0])) <= 31))"
6797 [(set (match_dup 2) (match_dup 3))]
6798 "
6799 {
6800 int endian = (WORDS_BIG_ENDIAN == 0);
6801 long l[2];
6802 HOST_WIDE_INT val;
6804 <real_value_to_target> (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
6806 operands[2] = gen_lowpart (DImode, operands[0]);
6807 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
6808 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
6809 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
6811 operands[3] = gen_int_mode (val, DImode);
6812 }")
6814 ;; Don't have reload use general registers to load a constant. It is
6815 ;; less efficient than loading the constant into an FP register, since
6816 ;; it will probably be used there.
6818 ;; The move constraints are ordered to prefer floating point registers before
6819 ;; general purpose registers to avoid doing a store and a load to get the value
6820 ;; into a floating point register when it is needed for a floating point
6821 ;; operation. Prefer traditional floating point registers over VSX registers,
6822 ;; since the D-form version of the memory instructions does not need a GPR for
6823 ;; reloading. ISA 3.0 (power9) adds D-form addressing for scalars to Altivec
6824 ;; registers.
6826 ;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
6827 ;; except for 0.0 which can be created on VSX with an xor instruction.
6829 (define_insn "*mov<mode>_hardfloat32"
6830 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
6831 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
6832 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6833 && (gpc_reg_operand (operands[0], <MODE>mode)
6834 || gpc_reg_operand (operands[1], <MODE>mode))"
6835 "@
6836 stfd%U0%X0 %1,%0
6837 lfd%U1%X1 %0,%1
6838 fmr %0,%1
6839 lxsd%U1x %x0,%y1
6840 stxsd%U0x %x1,%y0
6841 lxsd %0,%1
6842 stxsd %1,%0
6843 xxlor %x0,%x1,%x1
6844 xxlxor %x0,%x0,%x0
6845 #
6846 #
6847 #
6848 #"
6849 [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
6850 (set_attr "size" "64")
6851 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
6853 (define_insn "*mov<mode>_softfloat32"
6854 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
6855 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
6856 "! TARGET_POWERPC64
6857 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
6858 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
6859 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE))
6860 && (gpc_reg_operand (operands[0], <MODE>mode)
6861 || gpc_reg_operand (operands[1], <MODE>mode))"
6862 "#"
6863 [(set_attr "type" "store,load,two,*,*,*")
6864 (set_attr "length" "8,8,8,8,12,16")])
6866 ; ld/std require word-aligned displacements -> 'Y' constraint.
6867 ; List Y->r and r->Y before r->r for reload.
6868 (define_insn "*mov<mode>_hardfloat64"
6869 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
6870 (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
6871 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6872 && (gpc_reg_operand (operands[0], <MODE>mode)
6873 || gpc_reg_operand (operands[1], <MODE>mode))"
6874 "@
6875 stfd%U0%X0 %1,%0
6876 lfd%U1%X1 %0,%1
6877 fmr %0,%1
6878 lxsd %0,%1
6879 stxsd %1,%0
6880 lxsd%U1x %x0,%y1
6881 stxsd%U0x %x1,%y0
6882 xxlor %x0,%x1,%x1
6883 xxlxor %x0,%x0,%x0
6884 li %0,0
6885 std%U0%X0 %1,%0
6886 ld%U1%X1 %0,%1
6887 mr %0,%1
6888 mt%0 %1
6889 mf%1 %0
6890 nop
6891 mftgpr %0,%1
6892 mffgpr %0,%1
6893 mfvsrd %0,%x1
6894 mtvsrd %x0,%1"
6895 [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
6896 (set_attr "size" "64")
6897 (set_attr "length" "4")])
6899 (define_insn "*mov<mode>_softfloat64"
6900 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
6901 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
6902 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6903 && (gpc_reg_operand (operands[0], <MODE>mode)
6904 || gpc_reg_operand (operands[1], <MODE>mode))"
6905 "@
6906 std%U0%X0 %1,%0
6907 ld%U1%X1 %0,%1
6908 mr %0,%1
6909 mt%0 %1
6910 mf%1 %0
6911 #
6912 #
6913 #
6914 nop"
6915 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
6916 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
6917 \f
6918 (define_expand "mov<mode>"
6919 [(set (match_operand:FMOVE128 0 "general_operand" "")
6920 (match_operand:FMOVE128 1 "any_operand" ""))]
6921 ""
6922 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
6924 ;; It's important to list Y->r and r->Y before r->r because otherwise
6925 ;; reload, given m->r, will try to pick r->r and reload it, which
6926 ;; doesn't make progress.
6928 ;; We can't split little endian direct moves of TDmode, because the words are
6929 ;; not swapped like they are for TImode or TFmode. Subregs therefore are
6930 ;; problematical. Don't allow direct move for this case.
6932 (define_insn_and_split "*mov<mode>_64bit_dm"
6933 [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r,r,wh")
6934 (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r,wh,r"))]
6935 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
6936 && FLOAT128_2REG_P (<MODE>mode)
6937 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN)
6938 && (gpc_reg_operand (operands[0], <MODE>mode)
6939 || gpc_reg_operand (operands[1], <MODE>mode))"
6940 "#"
6941 "&& reload_completed"
6942 [(pc)]
6943 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
6944 [(set_attr "length" "8,8,8,8,12,12,8,8,8")])
6946 (define_insn_and_split "*movtd_64bit_nodm"
6947 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
6948 (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
6949 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
6950 && (gpc_reg_operand (operands[0], TDmode)
6951 || gpc_reg_operand (operands[1], TDmode))"
6952 "#"
6953 "&& reload_completed"
6954 [(pc)]
6955 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
6956 [(set_attr "length" "8,8,8,12,12,8")])
6958 (define_insn_and_split "*mov<mode>_32bit"
6959 [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
6960 (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
6961 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
6962 && (FLOAT128_2REG_P (<MODE>mode)
6963 || int_reg_operand_not_pseudo (operands[0], <MODE>mode)
6964 || int_reg_operand_not_pseudo (operands[1], <MODE>mode))
6965 && (gpc_reg_operand (operands[0], <MODE>mode)
6966 || gpc_reg_operand (operands[1], <MODE>mode))"
6967 "#"
6968 "&& reload_completed"
6969 [(pc)]
6970 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
6971 [(set_attr "length" "8,8,8,8,20,20,16")])
6973 (define_insn_and_split "*mov<mode>_softfloat"
6974 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
6975 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
6976 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
6977 && (gpc_reg_operand (operands[0], <MODE>mode)
6978 || gpc_reg_operand (operands[1], <MODE>mode))"
6979 "#"
6980 "&& reload_completed"
6981 [(pc)]
6982 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
6983 [(set_attr "length" "20,20,16")])
6985 (define_expand "extenddf<mode>2"
6986 [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
6987 (float_extend:FLOAT128 (match_operand:DF 1 "gpc_reg_operand" "")))]
6988 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)
6989 && TARGET_LONG_DOUBLE_128"
6990 {
6991 if (FLOAT128_IEEE_P (<MODE>mode))
6992 rs6000_expand_float128_convert (operands[0], operands[1], false);
6993 else if (TARGET_E500_DOUBLE)
6994 {
6995 gcc_assert (<MODE>mode == TFmode);
6996 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
6997 }
6998 else if (TARGET_VSX)
6999 {
7000 if (<MODE>mode == TFmode)
7001 emit_insn (gen_extenddftf2_vsx (operands[0], operands[1]));
7002 else if (<MODE>mode == IFmode)
7003 emit_insn (gen_extenddfif2_vsx (operands[0], operands[1]));
7004 else
7005 gcc_unreachable ();
7006 }
7007 else
7008 {
7009 rtx zero = gen_reg_rtx (DFmode);
7010 rs6000_emit_move (zero, CONST0_RTX (DFmode), DFmode);
7012 if (<MODE>mode == TFmode)
7013 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1], zero));
7014 else if (<MODE>mode == IFmode)
7015 emit_insn (gen_extenddfif2_fprs (operands[0], operands[1], zero));
7016 else
7017 gcc_unreachable ();
7018 }
7019 DONE;
7020 })
7022 ;; Allow memory operands for the source to be created by the combiner.
7023 (define_insn_and_split "extenddf<mode>2_fprs"
7024 [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d,&d")
7025 (float_extend:IBM128
7026 (match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
7027 (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
7028 "!TARGET_VSX && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7029 && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
7030 "#"
7031 "&& reload_completed"
7032 [(set (match_dup 3) (match_dup 1))
7033 (set (match_dup 4) (match_dup 2))]
7034 {
7035 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
7036 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
7038 operands[3] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
7039 operands[4] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
7040 })
7042 (define_insn_and_split "extenddf<mode>2_vsx"
7043 [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
7044 (float_extend:IBM128
7045 (match_operand:DF 1 "nonimmediate_operand" "ws,m")))]
7046 "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
7047 "#"
7048 "&& reload_completed"
7049 [(set (match_dup 2) (match_dup 1))
7050 (set (match_dup 3) (match_dup 4))]
7051 {
7052 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
7053 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
7055 operands[2] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
7056 operands[3] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
7057 operands[4] = CONST0_RTX (DFmode);
7058 })
7060 (define_expand "extendsf<mode>2"
7061 [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
7062 (float_extend:FLOAT128 (match_operand:SF 1 "gpc_reg_operand" "")))]
7063 "TARGET_HARD_FLOAT
7064 && (TARGET_FPRS || TARGET_E500_DOUBLE)
7065 && TARGET_LONG_DOUBLE_128"
7066 {
7067 if (FLOAT128_IEEE_P (<MODE>mode))
7068 rs6000_expand_float128_convert (operands[0], operands[1], false);
7069 else
7070 {
7071 rtx tmp = gen_reg_rtx (DFmode);
7072 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
7073 emit_insn (gen_extenddf<mode>2 (operands[0], tmp));
7074 }
7075 DONE;
7076 })
7078 (define_expand "trunc<mode>df2"
7079 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7080 (float_truncate:DF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
7081 "TARGET_HARD_FLOAT
7082 && (TARGET_FPRS || TARGET_E500_DOUBLE)
7083 && TARGET_LONG_DOUBLE_128"
7084 {
7085 if (FLOAT128_IEEE_P (<MODE>mode))
7086 {
7087 rs6000_expand_float128_convert (operands[0], operands[1], false);
7088 DONE;
7089 }
7090 })
7092 (define_insn_and_split "trunc<mode>df2_internal1"
7093 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
7094 (float_truncate:DF
7095 (match_operand:IBM128 1 "gpc_reg_operand" "0,d")))]
7096 "FLOAT128_IBM_P (<MODE>mode) && !TARGET_XL_COMPAT
7097 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7098 "@
7099 #
7100 fmr %0,%1"
7101 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
7102 [(const_int 0)]
7103 {
7104 emit_note (NOTE_INSN_DELETED);
7105 DONE;
7106 }
7107 [(set_attr "type" "fpsimple")])
7109 (define_insn "trunc<mode>df2_internal2"
7110 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7111 (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
7112 "FLOAT128_IBM_P (<MODE>mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT
7113 && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
7114 "fadd %0,%1,%L1"
7115 [(set_attr "type" "fp")
7116 (set_attr "fp_type" "fp_addsub_d")])
7118 (define_expand "trunc<mode>sf2"
7119 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7120 (float_truncate:SF (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
7121 "TARGET_HARD_FLOAT
7122 && (TARGET_FPRS || TARGET_E500_DOUBLE)
7123 && TARGET_LONG_DOUBLE_128"
7124 {
7125 if (FLOAT128_IEEE_P (<MODE>mode))
7126 rs6000_expand_float128_convert (operands[0], operands[1], false);
7127 else if (TARGET_E500_DOUBLE)
7128 {
7129 gcc_assert (<MODE>mode == TFmode);
7130 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
7131 }
7132 else if (<MODE>mode == TFmode)
7133 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
7134 else if (<MODE>mode == IFmode)
7135 emit_insn (gen_truncifsf2_fprs (operands[0], operands[1]));
7136 else
7137 gcc_unreachable ();
7138 DONE;
7139 })
7141 (define_insn_and_split "trunc<mode>sf2_fprs"
7142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
7143 (float_truncate:SF (match_operand:IBM128 1 "gpc_reg_operand" "d")))
7144 (clobber (match_scratch:DF 2 "=d"))]
7145 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
7146 && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
7147 "#"
7148 "&& reload_completed"
7149 [(set (match_dup 2)
7150 (float_truncate:DF (match_dup 1)))
7151 (set (match_dup 0)
7152 (float_truncate:SF (match_dup 2)))]
7153 "")
7155 (define_expand "floatsi<mode>2"
7156 [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
7157 (float:FLOAT128 (match_operand:SI 1 "gpc_reg_operand" "")))]
7158 "TARGET_HARD_FLOAT
7159 && (TARGET_FPRS || TARGET_E500_DOUBLE)
7160 && TARGET_LONG_DOUBLE_128"
7161 {
7162 if (FLOAT128_IEEE_P (<MODE>mode))
7163 rs6000_expand_float128_convert (operands[0], operands[1], false);
7164 else
7165 {
7166 rtx tmp = gen_reg_rtx (DFmode);
7167 expand_float (tmp, operands[1], false);
7168 if (<MODE>mode == TFmode)
7169 emit_insn (gen_extenddftf2 (operands[0], tmp));
7170 else if (<MODE>mode == IFmode)
7171 emit_insn (gen_extenddfif2 (operands[0], tmp));
7172 else
7173 gcc_unreachable ();
7174 }
7175 DONE;
7176 })
7178 ; fadd, but rounding towards zero.
7179 ; This is probably not the optimal code sequence.
7180 (define_insn "fix_trunc_helper<mode>"
7181 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
7182 (unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")]
7183 UNSPEC_FIX_TRUNC_TF))
7184 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
7185 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7186 && FLOAT128_IBM_P (<MODE>mode)"
7187 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
7188 [(set_attr "type" "fp")
7189 (set_attr "length" "20")])
7191 (define_expand "fix_trunc<mode>si2"
7192 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7193 (fix:SI (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
7194 "TARGET_HARD_FLOAT
7195 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
7196 {
7197 if (FLOAT128_IEEE_P (<MODE>mode))
7198 rs6000_expand_float128_convert (operands[0], operands[1], false);
7199 else if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
7200 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
7201 else if (<MODE>mode == TFmode)
7202 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
7203 else if (<MODE>mode == IFmode)
7204 emit_insn (gen_fix_truncifsi2_fprs (operands[0], operands[1]));
7205 else
7206 gcc_unreachable ();
7207 DONE;
7208 })
7210 (define_expand "fix_trunc<mode>si2_fprs"
7211 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
7212 (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" "")))
7213 (clobber (match_dup 2))
7214 (clobber (match_dup 3))
7215 (clobber (match_dup 4))
7216 (clobber (match_dup 5))])]
7217 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7218 {
7219 operands[2] = gen_reg_rtx (DFmode);
7220 operands[3] = gen_reg_rtx (DFmode);
7221 operands[4] = gen_reg_rtx (DImode);
7222 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
7223 })
7225 (define_insn_and_split "*fix_trunc<mode>si2_internal"
7226 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7227 (fix:SI (match_operand:IBM128 1 "gpc_reg_operand" "d")))
7228 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
7229 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
7230 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
7231 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
7232 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
7233 "#"
7234 ""
7235 [(pc)]
7236 {
7237 rtx lowword;
7238 emit_insn (gen_fix_trunc_helper<mode> (operands[2], operands[1],
7239 operands[3]));
7241 gcc_assert (MEM_P (operands[5]));
7242 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
7244 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
7245 emit_move_insn (operands[5], operands[4]);
7246 emit_move_insn (operands[0], lowword);
7247 DONE;
7248 })
7250 (define_expand "fix_trunc<mode>di2"
7251 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7252 (fix:DI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
7253 "TARGET_FLOAT128"
7254 {
7255 rs6000_expand_float128_convert (operands[0], operands[1], false);
7256 DONE;
7257 })
7259 (define_expand "fixuns_trunc<IEEE128:mode><SDI:mode>2"
7260 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
7261 (unsigned_fix:SDI (match_operand:IEEE128 1 "gpc_reg_operand" "")))]
7262 "TARGET_FLOAT128"
7263 {
7264 rs6000_expand_float128_convert (operands[0], operands[1], true);
7265 DONE;
7266 })
7268 (define_expand "floatdi<mode>2"
7269 [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
7270 (float:IEEE128 (match_operand:DI 1 "gpc_reg_operand" "")))]
7271 "TARGET_FLOAT128"
7272 {
7273 rs6000_expand_float128_convert (operands[0], operands[1], false);
7274 DONE;
7275 })
7277 (define_expand "floatuns<SDI:mode><IEEE128:mode>2"
7278 [(set (match_operand:IEEE128 0 "gpc_reg_operand" "")
7279 (unsigned_float:IEEE128 (match_operand:SDI 1 "gpc_reg_operand" "")))]
7280 "TARGET_FLOAT128"
7281 {
7282 rs6000_expand_float128_convert (operands[0], operands[1], true);
7283 DONE;
7284 })
7286 (define_expand "neg<mode>2"
7287 [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
7288 (neg:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
7289 "FLOAT128_IEEE_P (<MODE>mode)
7290 || (FLOAT128_IBM_P (<MODE>mode)
7291 && TARGET_HARD_FLOAT
7292 && (TARGET_FPRS || TARGET_E500_DOUBLE))"
7293 "
7294 {
7295 if (FLOAT128_IEEE_P (<MODE>mode))
7296 {
7297 if (TARGET_FLOAT128_HW)
7298 {
7299 if (<MODE>mode == TFmode)
7300 emit_insn (gen_negtf2_hw (operands[0], operands[1]));
7301 else if (<MODE>mode == KFmode)
7302 emit_insn (gen_negkf2_hw (operands[0], operands[1]));
7303 else
7304 gcc_unreachable ();
7305 }
7306 else if (TARGET_FLOAT128)
7307 {
7308 if (<MODE>mode == TFmode)
7309 emit_insn (gen_ieee_128bit_vsx_negtf2 (operands[0], operands[1]));
7310 else if (<MODE>mode == KFmode)
7311 emit_insn (gen_ieee_128bit_vsx_negkf2 (operands[0], operands[1]));
7312 else
7313 gcc_unreachable ();
7314 }
7315 else
7316 {
7317 rtx libfunc = optab_libfunc (neg_optab, <MODE>mode);
7318 rtx target = emit_library_call_value (libfunc, operands[0], LCT_CONST,
7319 <MODE>mode, 1,
7320 operands[1], <MODE>mode);
7322 if (target && !rtx_equal_p (target, operands[0]))
7323 emit_move_insn (operands[0], target);
7324 }
7325 DONE;
7326 }
7327 }")
7329 (define_insn "neg<mode>2_internal"
7330 [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d")
7331 (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))]
7332 "TARGET_HARD_FLOAT && TARGET_FPRS && FLOAT128_IBM_P (TFmode)"
7333 "*
7334 {
7335 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7336 return \"fneg %L0,%L1\;fneg %0,%1\";
7337 else
7338 return \"fneg %0,%1\;fneg %L0,%L1\";
7339 }"
7340 [(set_attr "type" "fpsimple")
7341 (set_attr "length" "8")])
7343 (define_expand "abs<mode>2"
7344 [(set (match_operand:FLOAT128 0 "gpc_reg_operand" "")
7345 (abs:FLOAT128 (match_operand:FLOAT128 1 "gpc_reg_operand" "")))]
7346 "FLOAT128_IEEE_P (<MODE>mode)
7347 || (FLOAT128_IBM_P (<MODE>mode)
7348 && TARGET_HARD_FLOAT
7349 && (TARGET_FPRS || TARGET_E500_DOUBLE))"
7350 "
7351 {
7352 rtx label;
7354 if (FLOAT128_IEEE_P (<MODE>mode))
7355 {
7356 if (TARGET_FLOAT128_HW)
7357 {
7358 if (<MODE>mode == TFmode)
7359 emit_insn (gen_abstf2_hw (operands[0], operands[1]));
7360 else if (<MODE>mode == KFmode)
7361 emit_insn (gen_abskf2_hw (operands[0], operands[1]));
7362 else
7363 FAIL;
7364 DONE;
7365 }
7366 else if (TARGET_FLOAT128)
7367 {
7368 if (<MODE>mode == TFmode)
7369 emit_insn (gen_ieee_128bit_vsx_abstf2 (operands[0], operands[1]));
7370 else if (<MODE>mode == KFmode)
7371 emit_insn (gen_ieee_128bit_vsx_abskf2 (operands[0], operands[1]));
7372 else
7373 FAIL;
7374 DONE;
7375 }
7376 else
7377 FAIL;
7378 }
7380 label = gen_label_rtx ();
7381 if (TARGET_E500_DOUBLE && <MODE>mode == TFmode)
7382 {
7383 if (flag_finite_math_only && !flag_trapping_math)
7384 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
7385 else
7386 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
7387 }
7388 else if (<MODE>mode == TFmode)
7389 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
7390 else if (<MODE>mode == TFmode)
7391 emit_insn (gen_absif2_internal (operands[0], operands[1], label));
7392 else
7393 FAIL;
7394 emit_label (label);
7395 DONE;
7396 }")
7398 (define_expand "abs<mode>2_internal"
7399 [(set (match_operand:IBM128 0 "gpc_reg_operand" "")
7400 (match_operand:IBM128 1 "gpc_reg_operand" ""))
7401 (set (match_dup 3) (match_dup 5))
7402 (set (match_dup 5) (abs:DF (match_dup 5)))
7403 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
7404 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
7405 (label_ref (match_operand 2 "" ""))
7406 (pc)))
7407 (set (match_dup 6) (neg:DF (match_dup 6)))]
7408 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
7409 && TARGET_LONG_DOUBLE_128"
7410 "
7411 {
7412 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
7413 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
7414 operands[3] = gen_reg_rtx (DFmode);
7415 operands[4] = gen_reg_rtx (CCFPmode);
7416 operands[5] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, hi_word);
7417 operands[6] = simplify_gen_subreg (DFmode, operands[0], <MODE>mode, lo_word);
7418 }")
7420 \f
7421 ;; Generate IEEE 128-bit -0.0 (0x80000000000000000000000000000000) in a vector
7422 ;; register
7424 (define_expand "ieee_128bit_negative_zero"
7425 [(set (match_operand:V16QI 0 "register_operand" "") (match_dup 1))]
7426 "TARGET_FLOAT128"
7427 {
7428 rtvec v = rtvec_alloc (16);
7429 int i, high;
7431 for (i = 0; i < 16; i++)
7432 RTVEC_ELT (v, i) = const0_rtx;
7434 high = (BYTES_BIG_ENDIAN) ? 0 : 15;
7435 RTVEC_ELT (v, high) = GEN_INT (0x80);
7437 rs6000_expand_vector_init (operands[0], gen_rtx_PARALLEL (V16QImode, v));
7438 DONE;
7439 })
7441 ;; IEEE 128-bit negate
7443 ;; We have 2 insns here for negate and absolute value. The first uses
7444 ;; match_scratch so that phases like combine can recognize neg/abs as generic
7445 ;; insns, and second insn after the first split pass loads up the bit to
7446 ;; twiddle the sign bit. Later GCSE passes can then combine multiple uses of
7447 ;; neg/abs to create the constant just once.
7449 (define_insn_and_split "ieee_128bit_vsx_neg<mode>2"
7450 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7451 (neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
7452 (clobber (match_scratch:V16QI 2 "=v"))]
7453 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
7454 "#"
7455 "&& 1"
7456 [(parallel [(set (match_dup 0)
7457 (neg:IEEE128 (match_dup 1)))
7458 (use (match_dup 2))])]
7459 {
7460 if (GET_CODE (operands[2]) == SCRATCH)
7461 operands[2] = gen_reg_rtx (V16QImode);
7463 operands[3] = gen_reg_rtx (V16QImode);
7464 emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
7465 }
7466 [(set_attr "length" "8")
7467 (set_attr "type" "vecsimple")])
7469 (define_insn "*ieee_128bit_vsx_neg<mode>2_internal"
7470 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7471 (neg:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
7472 (use (match_operand:V16QI 2 "register_operand" "v"))]
7473 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
7474 "xxlxor %x0,%x1,%x2"
7475 [(set_attr "type" "veclogical")])
7477 ;; IEEE 128-bit absolute value
7478 (define_insn_and_split "ieee_128bit_vsx_abs<mode>2"
7479 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7480 (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
7481 (clobber (match_scratch:V16QI 2 "=v"))]
7482 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
7483 "#"
7484 "&& 1"
7485 [(parallel [(set (match_dup 0)
7486 (abs:IEEE128 (match_dup 1)))
7487 (use (match_dup 2))])]
7488 {
7489 if (GET_CODE (operands[2]) == SCRATCH)
7490 operands[2] = gen_reg_rtx (V16QImode);
7492 operands[3] = gen_reg_rtx (V16QImode);
7493 emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
7494 }
7495 [(set_attr "length" "8")
7496 (set_attr "type" "vecsimple")])
7498 (define_insn "*ieee_128bit_vsx_abs<mode>2_internal"
7499 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7500 (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))
7501 (use (match_operand:V16QI 2 "register_operand" "v"))]
7502 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
7503 "xxlandc %x0,%x1,%x2"
7504 [(set_attr "type" "veclogical")])
7506 ;; IEEE 128-bit negative absolute value
7507 (define_insn_and_split "*ieee_128bit_vsx_nabs<mode>2"
7508 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7509 (neg:IEEE128
7510 (abs:IEEE128
7511 (match_operand:IEEE128 1 "register_operand" "wa"))))
7512 (clobber (match_scratch:V16QI 2 "=v"))]
7513 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
7514 "#"
7515 "&& 1"
7516 [(parallel [(set (match_dup 0)
7517 (neg:IEEE128 (abs:IEEE128 (match_dup 1))))
7518 (use (match_dup 2))])]
7519 {
7520 if (GET_CODE (operands[2]) == SCRATCH)
7521 operands[2] = gen_reg_rtx (V16QImode);
7523 operands[3] = gen_reg_rtx (V16QImode);
7524 emit_insn (gen_ieee_128bit_negative_zero (operands[2]));
7525 }
7526 [(set_attr "length" "8")
7527 (set_attr "type" "vecsimple")])
7529 (define_insn "*ieee_128bit_vsx_nabs<mode>2_internal"
7530 [(set (match_operand:IEEE128 0 "register_operand" "=wa")
7531 (neg:IEEE128
7532 (abs:IEEE128
7533 (match_operand:IEEE128 1 "register_operand" "wa"))))
7534 (use (match_operand:V16QI 2 "register_operand" "v"))]
7535 "TARGET_FLOAT128 && !TARGET_FLOAT128_HW"
7536 "xxlor %x0,%x1,%x2"
7537 [(set_attr "type" "veclogical")])
7539 ;; Float128 conversion functions. These expand to library function calls.
7540 ;; We use expand to convert from IBM double double to IEEE 128-bit
7541 ;; and trunc for the opposite.
7542 (define_expand "extendiftf2"
7543 [(set (match_operand:TF 0 "gpc_reg_operand" "")
7544 (float_extend:TF (match_operand:IF 1 "gpc_reg_operand" "")))]
7545 "TARGET_FLOAT128"
7546 {
7547 rs6000_expand_float128_convert (operands[0], operands[1], false);
7548 DONE;
7549 })
7551 (define_expand "extendifkf2"
7552 [(set (match_operand:KF 0 "gpc_reg_operand" "")
7553 (float_extend:KF (match_operand:IF 1 "gpc_reg_operand" "")))]
7554 "TARGET_FLOAT128"
7555 {
7556 rs6000_expand_float128_convert (operands[0], operands[1], false);
7557 DONE;
7558 })
7560 (define_expand "extendtfkf2"
7561 [(set (match_operand:KF 0 "gpc_reg_operand" "")
7562 (float_extend:KF (match_operand:TF 1 "gpc_reg_operand" "")))]
7563 "TARGET_FLOAT128"
7564 {
7565 rs6000_expand_float128_convert (operands[0], operands[1], false);
7566 DONE;
7567 })
7569 (define_expand "trunciftf2"
7570 [(set (match_operand:IF 0 "gpc_reg_operand" "")
7571 (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
7572 "TARGET_FLOAT128"
7573 {
7574 rs6000_expand_float128_convert (operands[0], operands[1], false);
7575 DONE;
7576 })
7578 (define_expand "truncifkf2"
7579 [(set (match_operand:IF 0 "gpc_reg_operand" "")
7580 (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand" "")))]
7581 "TARGET_FLOAT128"
7582 {
7583 rs6000_expand_float128_convert (operands[0], operands[1], false);
7584 DONE;
7585 })
7587 (define_expand "trunckftf2"
7588 [(set (match_operand:TF 0 "gpc_reg_operand" "")
7589 (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand" "")))]
7590 "TARGET_FLOAT128"
7591 {
7592 rs6000_expand_float128_convert (operands[0], operands[1], false);
7593 DONE;
7594 })
7596 (define_expand "trunctfif2"
7597 [(set (match_operand:IF 0 "gpc_reg_operand" "")
7598 (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand" "")))]
7599 "TARGET_FLOAT128"
7600 {
7601 rs6000_expand_float128_convert (operands[0], operands[1], false);
7602 DONE;
7603 })
7605 \f
7606 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
7607 ;; must have 3 arguments, and scratch register constraint must be a single
7608 ;; constraint.
7610 ;; Reload patterns to support gpr load/store with misaligned mem.
7611 ;; and multiple gpr load/store at offset >= 0xfffc
7612 (define_expand "reload_<mode>_store"
7613 [(parallel [(match_operand 0 "memory_operand" "=m")
7614 (match_operand 1 "gpc_reg_operand" "r")
7615 (match_operand:GPR 2 "register_operand" "=&b")])]
7616 ""
7617 {
7618 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
7619 DONE;
7620 })
7622 (define_expand "reload_<mode>_load"
7623 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
7624 (match_operand 1 "memory_operand" "m")
7625 (match_operand:GPR 2 "register_operand" "=b")])]
7626 ""
7627 {
7628 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
7629 DONE;
7630 })
7632 \f
7633 ;; Reload patterns for various types using the vector registers. We may need
7634 ;; an additional base register to convert the reg+offset addressing to reg+reg
7635 ;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
7636 ;; index register for gpr registers.
7637 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
7638 [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
7639 (match_operand:RELOAD 1 "gpc_reg_operand" "wa")
7640 (match_operand:P 2 "register_operand" "=b")])]
7641 "<P:tptrsize>"
7642 {
7643 rs6000_secondary_reload_inner (operands[1], operands[0], operands[2], true);
7644 DONE;
7645 })
7647 (define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
7648 [(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
7649 (match_operand:RELOAD 1 "memory_operand" "m")
7650 (match_operand:P 2 "register_operand" "=b")])]
7651 "<P:tptrsize>"
7652 {
7653 rs6000_secondary_reload_inner (operands[0], operands[1], operands[2], false);
7654 DONE;
7655 })
7658 ;; Reload sometimes tries to move the address to a GPR, and can generate
7659 ;; invalid RTL for addresses involving AND -16. Allow addresses involving
7660 ;; reg+reg, reg+small constant, or just reg, all wrapped in an AND -16.
7662 (define_insn_and_split "*vec_reload_and_plus_<mptrsize>"
7663 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
7664 (and:P (plus:P (match_operand:P 1 "gpc_reg_operand" "r")
7665 (match_operand:P 2 "reg_or_cint_operand" "rI"))
7666 (const_int -16)))]
7667 "TARGET_ALTIVEC && (reload_in_progress || reload_completed)"
7668 "#"
7669 "&& reload_completed"
7670 [(set (match_dup 0)
7671 (plus:P (match_dup 1)
7672 (match_dup 2)))
7673 (set (match_dup 0)
7674 (and:P (match_dup 0)
7675 (const_int -16)))])
7676 \f
7677 ;; Power8 merge instructions to allow direct move to/from floating point
7678 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
7679 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
7680 ;; value, since it is allocated in reload and not all of the flow information
7681 ;; is setup for it. We have two patterns to do the two moves between gprs and
7682 ;; fprs. There isn't a dependancy between the two, but we could potentially
7683 ;; schedule other instructions between the two instructions.
7685 (define_insn "p8_fmrgow_<mode>"
7686 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
7687 (unspec:FMOVE64X [
7688 (match_operand:DF 1 "register_operand" "d")
7689 (match_operand:DF 2 "register_operand" "d")]
7690 UNSPEC_P8V_FMRGOW))]
7691 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7692 "fmrgow %0,%1,%2"
7693 [(set_attr "type" "fpsimple")])
7695 (define_insn "p8_mtvsrwz"
7696 [(set (match_operand:DF 0 "register_operand" "=d")
7697 (unspec:DF [(match_operand:SI 1 "register_operand" "r")]
7698 UNSPEC_P8V_MTVSRWZ))]
7699 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7700 "mtvsrwz %x0,%1"
7701 [(set_attr "type" "mftgpr")])
7703 (define_insn_and_split "reload_fpr_from_gpr<mode>"
7704 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
7705 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
7706 UNSPEC_P8V_RELOAD_FROM_GPR))
7707 (clobber (match_operand:IF 2 "register_operand" "=d"))]
7708 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7709 "#"
7710 "&& reload_completed"
7711 [(const_int 0)]
7712 {
7713 rtx dest = operands[0];
7714 rtx src = operands[1];
7715 rtx tmp_hi = simplify_gen_subreg (DFmode, operands[2], IFmode, 0);
7716 rtx tmp_lo = simplify_gen_subreg (DFmode, operands[2], IFmode, 8);
7717 rtx gpr_hi_reg = gen_highpart (SImode, src);
7718 rtx gpr_lo_reg = gen_lowpart (SImode, src);
7720 emit_insn (gen_p8_mtvsrwz (tmp_hi, gpr_hi_reg));
7721 emit_insn (gen_p8_mtvsrwz (tmp_lo, gpr_lo_reg));
7722 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp_hi, tmp_lo));
7723 DONE;
7724 }
7725 [(set_attr "length" "12")
7726 (set_attr "type" "three")])
7728 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
7729 (define_insn "p8_mtvsrd_df"
7730 [(set (match_operand:DF 0 "register_operand" "=wa")
7731 (unspec:DF [(match_operand:DI 1 "register_operand" "r")]
7732 UNSPEC_P8V_MTVSRD))]
7733 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7734 "mtvsrd %x0,%1"
7735 [(set_attr "type" "mftgpr")])
7737 (define_insn "p8_xxpermdi_<mode>"
7738 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
7739 (unspec:FMOVE128_GPR [
7740 (match_operand:DF 1 "register_operand" "wa")
7741 (match_operand:DF 2 "register_operand" "wa")]
7742 UNSPEC_P8V_XXPERMDI))]
7743 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7744 "xxpermdi %x0,%x1,%x2,0"
7745 [(set_attr "type" "vecperm")])
7747 (define_insn_and_split "reload_vsx_from_gpr<mode>"
7748 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
7749 (unspec:FMOVE128_GPR
7750 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
7751 UNSPEC_P8V_RELOAD_FROM_GPR))
7752 (clobber (match_operand:IF 2 "register_operand" "=wa"))]
7753 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7754 "#"
7755 "&& reload_completed"
7756 [(const_int 0)]
7757 {
7758 rtx dest = operands[0];
7759 rtx src = operands[1];
7760 /* You might think that we could use op0 as one temp and a DF clobber
7761 as op2, but you'd be wrong. Secondary reload move patterns don't
7762 check for overlap of the clobber and the destination. */
7763 rtx tmp_hi = simplify_gen_subreg (DFmode, operands[2], IFmode, 0);
7764 rtx tmp_lo = simplify_gen_subreg (DFmode, operands[2], IFmode, 8);
7765 rtx gpr_hi_reg = gen_highpart (DImode, src);
7766 rtx gpr_lo_reg = gen_lowpart (DImode, src);
7768 emit_insn (gen_p8_mtvsrd_df (tmp_hi, gpr_hi_reg));
7769 emit_insn (gen_p8_mtvsrd_df (tmp_lo, gpr_lo_reg));
7770 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp_hi, tmp_lo));
7771 DONE;
7772 }
7773 [(set_attr "length" "12")
7774 (set_attr "type" "three")])
7776 (define_split
7777 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
7778 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
7779 "reload_completed
7780 && (int_reg_operand (operands[0], <MODE>mode)
7781 || int_reg_operand (operands[1], <MODE>mode))
7782 && (!TARGET_DIRECT_MOVE_128
7783 || (!vsx_register_operand (operands[0], <MODE>mode)
7784 && !vsx_register_operand (operands[1], <MODE>mode)))"
7785 [(pc)]
7786 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
7788 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
7789 ;; type is stored internally as double precision in the VSX registers, we have
7790 ;; to convert it from the vector format.
7791 (define_insn "p8_mtvsrd_sf"
7792 [(set (match_operand:SF 0 "register_operand" "=wa")
7793 (unspec:SF [(match_operand:DI 1 "register_operand" "r")]
7794 UNSPEC_P8V_MTVSRD))]
7795 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7796 "mtvsrd %x0,%1"
7797 [(set_attr "type" "mftgpr")])
7799 (define_insn_and_split "reload_vsx_from_gprsf"
7800 [(set (match_operand:SF 0 "register_operand" "=wa")
7801 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
7802 UNSPEC_P8V_RELOAD_FROM_GPR))
7803 (clobber (match_operand:DI 2 "register_operand" "=r"))]
7804 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7805 "#"
7806 "&& reload_completed"
7807 [(const_int 0)]
7808 {
7809 rtx op0 = operands[0];
7810 rtx op1 = operands[1];
7811 rtx op2 = operands[2];
7812 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
7814 /* Move SF value to upper 32-bits for xscvspdpn. */
7815 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
7816 emit_insn (gen_p8_mtvsrd_sf (op0, op2));
7817 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
7818 DONE;
7819 }
7820 [(set_attr "length" "8")
7821 (set_attr "type" "two")])
7823 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
7824 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
7825 ;; and then doing a move of that.
7826 (define_insn "p8_mfvsrd_3_<mode>"
7827 [(set (match_operand:DF 0 "register_operand" "=r")
7828 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
7829 UNSPEC_P8V_RELOAD_FROM_VSX))]
7830 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7831 "mfvsrd %0,%x1"
7832 [(set_attr "type" "mftgpr")])
7834 (define_insn_and_split "reload_gpr_from_vsx<mode>"
7835 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
7836 (unspec:FMOVE128_GPR
7837 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
7838 UNSPEC_P8V_RELOAD_FROM_VSX))
7839 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
7840 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7841 "#"
7842 "&& reload_completed"
7843 [(const_int 0)]
7844 {
7845 rtx dest = operands[0];
7846 rtx src = operands[1];
7847 rtx tmp = operands[2];
7848 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
7849 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
7851 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
7852 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
7853 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
7854 DONE;
7855 }
7856 [(set_attr "length" "12")
7857 (set_attr "type" "three")])
7859 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
7860 ;; type is stored internally as double precision, we have to convert it to the
7861 ;; vector format.
7863 (define_insn_and_split "reload_gpr_from_vsxsf"
7864 [(set (match_operand:SF 0 "register_operand" "=r")
7865 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
7866 UNSPEC_P8V_RELOAD_FROM_VSX))
7867 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
7868 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7869 "#"
7870 "&& reload_completed"
7871 [(const_int 0)]
7872 {
7873 rtx op0 = operands[0];
7874 rtx op1 = operands[1];
7875 rtx op2 = operands[2];
7876 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
7878 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
7879 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
7880 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
7881 DONE;
7882 }
7883 [(set_attr "length" "12")
7884 (set_attr "type" "three")])
7886 (define_insn "p8_mfvsrd_4_disf"
7887 [(set (match_operand:DI 0 "register_operand" "=r")
7888 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
7889 UNSPEC_P8V_RELOAD_FROM_VSX))]
7890 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
7891 "mfvsrd %0,%x1"
7892 [(set_attr "type" "mftgpr")])
7894 \f
7895 ;; Next come the multi-word integer load and store and the load and store
7896 ;; multiple insns.
7898 ;; List r->r after r->Y, otherwise reload will try to reload a
7899 ;; non-offsettable address by using r->r which won't make progress.
7900 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
7901 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
7903 ;; GPR store GPR load GPR move FPR store FPR load FPR move
7904 ;; GPR const AVX store AVX store AVX load AVX load VSX move
7905 ;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
7906 ;; AVX const
7908 (define_insn "*movdi_internal32"
7909 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
7910 "=Y, r, r, ?m, ?*d, ?*d,
7911 r, ?wY, ?Z, ?*wb, ?*wv, ?wi,
7912 ?wo, ?wo, ?wv, ?wi, ?wi, ?wv,
7913 ?wv")
7915 (match_operand:DI 1 "input_operand"
7916 "r, Y, r, d, m, d,
7917 IJKnGHF, wb, wv, wY, Z, wi,
7918 Oj, wM, OjwM, Oj, wM, wS,
7919 wB"))]
7921 "! TARGET_POWERPC64
7922 && (gpc_reg_operand (operands[0], DImode)
7923 || gpc_reg_operand (operands[1], DImode))"
7924 "@
7925 #
7926 #
7927 #
7928 stfd%U0%X0 %1,%0
7929 lfd%U1%X1 %0,%1
7930 fmr %0,%1
7931 #
7932 stxsd %1,%0
7933 stxsdx %x1,%y0
7934 lxsd %0,%1
7935 lxsdx %x0,%y1
7936 xxlor %x0,%x1,%x1
7937 xxspltib %x0,0
7938 xxspltib %x0,255
7939 vspltisw %0,%1
7940 xxlxor %x0,%x0,%x0
7941 xxlorc %x0,%x0,%x0
7942 #
7943 #"
7944 [(set_attr "type"
7945 "store, load, *, fpstore, fpload, fpsimple,
7946 *, fpstore, fpstore, fpload, fpload, veclogical,
7947 vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple,
7948 vecsimple")
7949 (set_attr "size" "64")])
7951 (define_split
7952 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7953 (match_operand:DI 1 "const_int_operand" ""))]
7954 "! TARGET_POWERPC64 && reload_completed
7955 && gpr_or_gpr_p (operands[0], operands[1])
7956 && !direct_move_p (operands[0], operands[1])"
7957 [(set (match_dup 2) (match_dup 4))
7958 (set (match_dup 3) (match_dup 1))]
7959 "
7960 {
7961 HOST_WIDE_INT value = INTVAL (operands[1]);
7962 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7963 DImode);
7964 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7965 DImode);
7966 operands[4] = GEN_INT (value >> 32);
7967 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
7968 }")
7970 (define_split
7971 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
7972 (match_operand:DIFD 1 "input_operand" ""))]
7973 "reload_completed && !TARGET_POWERPC64
7974 && gpr_or_gpr_p (operands[0], operands[1])
7975 && !direct_move_p (operands[0], operands[1])"
7976 [(pc)]
7977 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
7979 ;; GPR store GPR load GPR move GPR li GPR lis GPR #
7980 ;; FPR store FPR load FPR move AVX store AVX store AVX load
7981 ;; AVX load VSX move P9 0 P9 -1 AVX 0/-1 VSX 0
7982 ;; VSX -1 P9 const AVX const From SPR To SPR SPR<->SPR
7983 ;; FPR->GPR GPR->FPR VSX->GPR GPR->VSX
7984 (define_insn "*movdi_internal64"
7985 [(set (match_operand:DI 0 "nonimmediate_operand"
7986 "=Y, r, r, r, r, r,
7987 ?m, ?*d, ?*d, ?wY, ?Z, ?*wb,
7988 ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi,
7989 ?wi, ?wv, ?wv, r, *h, *h,
7990 ?*r, ?*wg, ?*r, ?*wj")
7992 (match_operand:DI 1 "input_operand"
7993 "r, Y, r, I, L, nF,
7994 d, m, d, wb, wv, wY,
7995 Z, wi, Oj, wM, OjwM, Oj,
7996 wM, wS, wB, *h, r, 0,
7997 wg, r, wj, r"))]
7999 "TARGET_POWERPC64
8000 && (gpc_reg_operand (operands[0], DImode)
8001 || gpc_reg_operand (operands[1], DImode))"
8002 "@
8003 std%U0%X0 %1,%0
8004 ld%U1%X1 %0,%1
8005 mr %0,%1
8006 li %0,%1
8007 lis %0,%v1
8008 #
8009 stfd%U0%X0 %1,%0
8010 lfd%U1%X1 %0,%1
8011 fmr %0,%1
8012 stxsd %1,%0
8013 stxsdx %x1,%y0
8014 lxsd %0,%1
8015 lxsdx %x0,%y1
8016 xxlor %x0,%x1,%x1
8017 xxspltib %x0,0
8018 xxspltib %x0,255
8019 vspltisw %0,%1
8020 xxlxor %x0,%x0,%x0
8021 xxlorc %x0,%x0,%x0
8022 #
8023 #
8024 mf%1 %0
8025 mt%0 %1
8026 nop
8027 mftgpr %0,%1
8028 mffgpr %0,%1
8029 mfvsrd %0,%x1
8030 mtvsrd %x0,%1"
8031 [(set_attr "type"
8032 "store, load, *, *, *, *,
8033 fpstore, fpload, fpsimple, fpstore, fpstore, fpload,
8034 fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,
8035 veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
8036 mftgpr, mffgpr, mftgpr, mffgpr")
8038 (set_attr "size" "64")
8039 (set_attr "length"
8040 "4, 4, 4, 4, 4, 20,
8041 4, 4, 4, 4, 4, 4,
8042 4, 4, 4, 4, 4, 8,
8043 8, 4, 4, 4, 4, 4,
8044 4, 4, 4, 4")])
8046 ; Some DImode loads are best done as a load of -1 followed by a mask
8047 ; instruction.
8048 (define_split
8049 [(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
8050 (match_operand:DI 1 "const_int_operand"))]
8051 "TARGET_POWERPC64
8052 && num_insns_constant (operands[1], DImode) > 1
8053 && rs6000_is_valid_and_mask (operands[1], DImode)"
8054 [(set (match_dup 0)
8055 (const_int -1))
8056 (set (match_dup 0)
8057 (and:DI (match_dup 0)
8058 (match_dup 1)))]
8059 "")
8061 ;; Split a load of a large constant into the appropriate five-instruction
8062 ;; sequence. Handle anything in a constant number of insns.
8063 ;; When non-easy constants can go in the TOC, this should use
8064 ;; easy_fp_constant predicate.
8065 (define_split
8066 [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
8067 (match_operand:DI 1 "const_int_operand" ""))]
8068 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8069 [(set (match_dup 0) (match_dup 2))
8070 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8071 "
8072 {
8073 if (rs6000_emit_set_const (operands[0], operands[1]))
8074 DONE;
8075 else
8076 FAIL;
8077 }")
8079 (define_split
8080 [(set (match_operand:DI 0 "int_reg_operand_not_pseudo" "")
8081 (match_operand:DI 1 "const_scalar_int_operand" ""))]
8082 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8083 [(set (match_dup 0) (match_dup 2))
8084 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8085 "
8086 {
8087 if (rs6000_emit_set_const (operands[0], operands[1]))
8088 DONE;
8089 else
8090 FAIL;
8091 }")
8093 (define_split
8094 [(set (match_operand:DI 0 "altivec_register_operand" "")
8095 (match_operand:DI 1 "s5bit_cint_operand" ""))]
8096 "TARGET_UPPER_REGS_DI && TARGET_VSX && reload_completed"
8097 [(const_int 0)]
8098 {
8099 rtx op0 = operands[0];
8100 rtx op1 = operands[1];
8101 int r = REGNO (op0);
8102 rtx op0_v4si = gen_rtx_REG (V4SImode, r);
8104 emit_insn (gen_altivec_vspltisw (op0_v4si, op1));
8105 if (op1 != const0_rtx && op1 != constm1_rtx)
8106 {
8107 rtx op0_v2di = gen_rtx_REG (V2DImode, r);
8108 emit_insn (gen_altivec_vupkhsw (op0_v2di, op0_v4si));
8109 }
8110 DONE;
8111 })
8113 (define_split
8114 [(set (match_operand:DI 0 "altivec_register_operand" "")
8115 (match_operand:DI 1 "xxspltib_constant_split" ""))]
8116 "TARGET_UPPER_REGS_DI && TARGET_P9_VECTOR && reload_completed"
8117 [(const_int 0)]
8118 {
8119 rtx op0 = operands[0];
8120 rtx op1 = operands[1];
8121 int r = REGNO (op0);
8122 rtx op0_v16qi = gen_rtx_REG (V16QImode, r);
8124 emit_insn (gen_xxspltib_v16qi (op0_v16qi, op1));
8125 emit_insn (gen_vsx_sign_extend_qi_di (operands[0], op0_v16qi));
8126 DONE;
8127 })
8129 \f
8130 ;; TImode/PTImode is similar, except that we usually want to compute the
8131 ;; address into a register and use lsi/stsi (the exception is during reload).
8133 (define_insn "*mov<mode>_string"
8134 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
8135 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
8136 "! TARGET_POWERPC64
8137 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
8138 && (gpc_reg_operand (operands[0], <MODE>mode)
8139 || gpc_reg_operand (operands[1], <MODE>mode))"
8140 "*
8141 {
8142 switch (which_alternative)
8143 {
8144 default:
8145 gcc_unreachable ();
8146 case 0:
8147 if (TARGET_STRING)
8148 return \"stswi %1,%P0,16\";
8149 case 1:
8150 return \"#\";
8151 case 2:
8152 /* If the address is not used in the output, we can use lsi. Otherwise,
8153 fall through to generating four loads. */
8154 if (TARGET_STRING
8155 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8156 return \"lswi %0,%P1,16\";
8157 /* ... fall through ... */
8158 case 3:
8159 case 4:
8160 case 5:
8161 return \"#\";
8162 }
8163 }"
8164 [(set_attr "type" "store,store,load,load,*,*")
8165 (set_attr "update" "yes")
8166 (set_attr "indexed" "yes")
8167 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
8168 (const_string "always")
8169 (const_string "conditional")))])
8171 (define_insn "*mov<mode>_ppc64"
8172 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
8173 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
8174 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
8175 && (gpc_reg_operand (operands[0], <MODE>mode)
8176 || gpc_reg_operand (operands[1], <MODE>mode)))"
8177 {
8178 return rs6000_output_move_128bit (operands);
8179 }
8180 [(set_attr "type" "store,store,load,load,*,*")
8181 (set_attr "length" "8")])
8183 (define_split
8184 [(set (match_operand:TI2 0 "int_reg_operand" "")
8185 (match_operand:TI2 1 "const_scalar_int_operand" ""))]
8186 "TARGET_POWERPC64
8187 && (VECTOR_MEM_NONE_P (<MODE>mode)
8188 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
8189 [(set (match_dup 2) (match_dup 4))
8190 (set (match_dup 3) (match_dup 5))]
8191 "
8192 {
8193 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8194 <MODE>mode);
8195 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8196 <MODE>mode);
8197 if (CONST_WIDE_INT_P (operands[1]))
8198 {
8199 operands[4] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 1));
8200 operands[5] = GEN_INT (CONST_WIDE_INT_ELT (operands[1], 0));
8201 }
8202 else if (CONST_INT_P (operands[1]))
8203 {
8204 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8205 operands[5] = operands[1];
8206 }
8207 else
8208 FAIL;
8209 }")
8211 (define_split
8212 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
8213 (match_operand:TI2 1 "input_operand" ""))]
8214 "reload_completed
8215 && gpr_or_gpr_p (operands[0], operands[1])
8216 && !direct_move_p (operands[0], operands[1])
8217 && !quad_load_store_p (operands[0], operands[1])"
8218 [(pc)]
8219 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8220 \f
8221 (define_expand "load_multiple"
8222 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8223 (match_operand:SI 1 "" ""))
8224 (use (match_operand:SI 2 "" ""))])]
8225 "TARGET_STRING && !TARGET_POWERPC64"
8226 "
8227 {
8228 int regno;
8229 int count;
8230 rtx op1;
8231 int i;
8233 /* Support only loading a constant number of fixed-point registers from
8234 memory and only bother with this if more than two; the machine
8235 doesn't support more than eight. */
8236 if (GET_CODE (operands[2]) != CONST_INT
8237 || INTVAL (operands[2]) <= 2
8238 || INTVAL (operands[2]) > 8
8239 || GET_CODE (operands[1]) != MEM
8240 || GET_CODE (operands[0]) != REG
8241 || REGNO (operands[0]) >= 32)
8242 FAIL;
8244 count = INTVAL (operands[2]);
8245 regno = REGNO (operands[0]);
8247 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8248 op1 = replace_equiv_address (operands[1],
8249 force_reg (SImode, XEXP (operands[1], 0)));
8251 for (i = 0; i < count; i++)
8252 XVECEXP (operands[3], 0, i)
8253 = gen_rtx_SET (gen_rtx_REG (SImode, regno + i),
8254 adjust_address_nv (op1, SImode, i * 4));
8255 }")
8257 (define_insn "*ldmsi8"
8258 [(match_parallel 0 "load_multiple_operation"
8259 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8260 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8261 (set (match_operand:SI 3 "gpc_reg_operand" "")
8262 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8263 (set (match_operand:SI 4 "gpc_reg_operand" "")
8264 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8265 (set (match_operand:SI 5 "gpc_reg_operand" "")
8266 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8267 (set (match_operand:SI 6 "gpc_reg_operand" "")
8268 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8269 (set (match_operand:SI 7 "gpc_reg_operand" "")
8270 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8271 (set (match_operand:SI 8 "gpc_reg_operand" "")
8272 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8273 (set (match_operand:SI 9 "gpc_reg_operand" "")
8274 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8275 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8276 "*
8277 { return rs6000_output_load_multiple (operands); }"
8278 [(set_attr "type" "load")
8279 (set_attr "update" "yes")
8280 (set_attr "indexed" "yes")
8281 (set_attr "length" "32")])
8283 (define_insn "*ldmsi7"
8284 [(match_parallel 0 "load_multiple_operation"
8285 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8286 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8287 (set (match_operand:SI 3 "gpc_reg_operand" "")
8288 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8289 (set (match_operand:SI 4 "gpc_reg_operand" "")
8290 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8291 (set (match_operand:SI 5 "gpc_reg_operand" "")
8292 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8293 (set (match_operand:SI 6 "gpc_reg_operand" "")
8294 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8295 (set (match_operand:SI 7 "gpc_reg_operand" "")
8296 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8297 (set (match_operand:SI 8 "gpc_reg_operand" "")
8298 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8299 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8300 "*
8301 { return rs6000_output_load_multiple (operands); }"
8302 [(set_attr "type" "load")
8303 (set_attr "update" "yes")
8304 (set_attr "indexed" "yes")
8305 (set_attr "length" "32")])
8307 (define_insn "*ldmsi6"
8308 [(match_parallel 0 "load_multiple_operation"
8309 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8310 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8311 (set (match_operand:SI 3 "gpc_reg_operand" "")
8312 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8313 (set (match_operand:SI 4 "gpc_reg_operand" "")
8314 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8315 (set (match_operand:SI 5 "gpc_reg_operand" "")
8316 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8317 (set (match_operand:SI 6 "gpc_reg_operand" "")
8318 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8319 (set (match_operand:SI 7 "gpc_reg_operand" "")
8320 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8321 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8322 "*
8323 { return rs6000_output_load_multiple (operands); }"
8324 [(set_attr "type" "load")
8325 (set_attr "update" "yes")
8326 (set_attr "indexed" "yes")
8327 (set_attr "length" "32")])
8329 (define_insn "*ldmsi5"
8330 [(match_parallel 0 "load_multiple_operation"
8331 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8332 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8333 (set (match_operand:SI 3 "gpc_reg_operand" "")
8334 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8335 (set (match_operand:SI 4 "gpc_reg_operand" "")
8336 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8337 (set (match_operand:SI 5 "gpc_reg_operand" "")
8338 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8339 (set (match_operand:SI 6 "gpc_reg_operand" "")
8340 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8341 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8342 "*
8343 { return rs6000_output_load_multiple (operands); }"
8344 [(set_attr "type" "load")
8345 (set_attr "update" "yes")
8346 (set_attr "indexed" "yes")
8347 (set_attr "length" "32")])
8349 (define_insn "*ldmsi4"
8350 [(match_parallel 0 "load_multiple_operation"
8351 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8352 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8353 (set (match_operand:SI 3 "gpc_reg_operand" "")
8354 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8355 (set (match_operand:SI 4 "gpc_reg_operand" "")
8356 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8357 (set (match_operand:SI 5 "gpc_reg_operand" "")
8358 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8359 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8360 "*
8361 { return rs6000_output_load_multiple (operands); }"
8362 [(set_attr "type" "load")
8363 (set_attr "update" "yes")
8364 (set_attr "indexed" "yes")
8365 (set_attr "length" "32")])
8367 (define_insn "*ldmsi3"
8368 [(match_parallel 0 "load_multiple_operation"
8369 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8370 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8371 (set (match_operand:SI 3 "gpc_reg_operand" "")
8372 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8373 (set (match_operand:SI 4 "gpc_reg_operand" "")
8374 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8375 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8376 "*
8377 { return rs6000_output_load_multiple (operands); }"
8378 [(set_attr "type" "load")
8379 (set_attr "update" "yes")
8380 (set_attr "indexed" "yes")
8381 (set_attr "length" "32")])
8383 (define_expand "store_multiple"
8384 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8385 (match_operand:SI 1 "" ""))
8386 (clobber (scratch:SI))
8387 (use (match_operand:SI 2 "" ""))])]
8388 "TARGET_STRING && !TARGET_POWERPC64"
8389 "
8390 {
8391 int regno;
8392 int count;
8393 rtx to;
8394 rtx op0;
8395 int i;
8397 /* Support only storing a constant number of fixed-point registers to
8398 memory and only bother with this if more than two; the machine
8399 doesn't support more than eight. */
8400 if (GET_CODE (operands[2]) != CONST_INT
8401 || INTVAL (operands[2]) <= 2
8402 || INTVAL (operands[2]) > 8
8403 || GET_CODE (operands[0]) != MEM
8404 || GET_CODE (operands[1]) != REG
8405 || REGNO (operands[1]) >= 32)
8406 FAIL;
8408 count = INTVAL (operands[2]);
8409 regno = REGNO (operands[1]);
8411 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8412 to = force_reg (SImode, XEXP (operands[0], 0));
8413 op0 = replace_equiv_address (operands[0], to);
8415 XVECEXP (operands[3], 0, 0)
8416 = gen_rtx_SET (adjust_address_nv (op0, SImode, 0), operands[1]);
8417 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8418 gen_rtx_SCRATCH (SImode));
8420 for (i = 1; i < count; i++)
8421 XVECEXP (operands[3], 0, i + 1)
8422 = gen_rtx_SET (adjust_address_nv (op0, SImode, i * 4),
8423 gen_rtx_REG (SImode, regno + i));
8424 }")
8426 (define_insn "*stmsi8"
8427 [(match_parallel 0 "store_multiple_operation"
8428 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8429 (match_operand:SI 2 "gpc_reg_operand" "r"))
8430 (clobber (match_scratch:SI 3 "=X"))
8431 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8432 (match_operand:SI 4 "gpc_reg_operand" "r"))
8433 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8434 (match_operand:SI 5 "gpc_reg_operand" "r"))
8435 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8436 (match_operand:SI 6 "gpc_reg_operand" "r"))
8437 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8438 (match_operand:SI 7 "gpc_reg_operand" "r"))
8439 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8440 (match_operand:SI 8 "gpc_reg_operand" "r"))
8441 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8442 (match_operand:SI 9 "gpc_reg_operand" "r"))
8443 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8444 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8445 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
8446 "stswi %2,%1,%O0"
8447 [(set_attr "type" "store")
8448 (set_attr "update" "yes")
8449 (set_attr "indexed" "yes")
8450 (set_attr "cell_micro" "always")])
8452 (define_insn "*stmsi7"
8453 [(match_parallel 0 "store_multiple_operation"
8454 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8455 (match_operand:SI 2 "gpc_reg_operand" "r"))
8456 (clobber (match_scratch:SI 3 "=X"))
8457 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8458 (match_operand:SI 4 "gpc_reg_operand" "r"))
8459 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8460 (match_operand:SI 5 "gpc_reg_operand" "r"))
8461 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8462 (match_operand:SI 6 "gpc_reg_operand" "r"))
8463 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8464 (match_operand:SI 7 "gpc_reg_operand" "r"))
8465 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8466 (match_operand:SI 8 "gpc_reg_operand" "r"))
8467 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8468 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8469 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8470 "stswi %2,%1,%O0"
8471 [(set_attr "type" "store")
8472 (set_attr "update" "yes")
8473 (set_attr "indexed" "yes")
8474 (set_attr "cell_micro" "always")])
8476 (define_insn "*stmsi6"
8477 [(match_parallel 0 "store_multiple_operation"
8478 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8479 (match_operand:SI 2 "gpc_reg_operand" "r"))
8480 (clobber (match_scratch:SI 3 "=X"))
8481 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8482 (match_operand:SI 4 "gpc_reg_operand" "r"))
8483 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8484 (match_operand:SI 5 "gpc_reg_operand" "r"))
8485 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8486 (match_operand:SI 6 "gpc_reg_operand" "r"))
8487 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8488 (match_operand:SI 7 "gpc_reg_operand" "r"))
8489 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8490 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8491 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8492 "stswi %2,%1,%O0"
8493 [(set_attr "type" "store")
8494 (set_attr "update" "yes")
8495 (set_attr "indexed" "yes")
8496 (set_attr "cell_micro" "always")])
8498 (define_insn "*stmsi5"
8499 [(match_parallel 0 "store_multiple_operation"
8500 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8501 (match_operand:SI 2 "gpc_reg_operand" "r"))
8502 (clobber (match_scratch:SI 3 "=X"))
8503 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8504 (match_operand:SI 4 "gpc_reg_operand" "r"))
8505 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8506 (match_operand:SI 5 "gpc_reg_operand" "r"))
8507 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8508 (match_operand:SI 6 "gpc_reg_operand" "r"))
8509 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8510 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8511 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8512 "stswi %2,%1,%O0"
8513 [(set_attr "type" "store")
8514 (set_attr "update" "yes")
8515 (set_attr "indexed" "yes")
8516 (set_attr "cell_micro" "always")])
8518 (define_insn "*stmsi4"
8519 [(match_parallel 0 "store_multiple_operation"
8520 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8521 (match_operand:SI 2 "gpc_reg_operand" "r"))
8522 (clobber (match_scratch:SI 3 "=X"))
8523 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8524 (match_operand:SI 4 "gpc_reg_operand" "r"))
8525 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8526 (match_operand:SI 5 "gpc_reg_operand" "r"))
8527 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8528 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
8529 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8530 "stswi %2,%1,%O0"
8531 [(set_attr "type" "store")
8532 (set_attr "update" "yes")
8533 (set_attr "indexed" "yes")
8534 (set_attr "cell_micro" "always")])
8536 (define_insn "*stmsi3"
8537 [(match_parallel 0 "store_multiple_operation"
8538 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8539 (match_operand:SI 2 "gpc_reg_operand" "r"))
8540 (clobber (match_scratch:SI 3 "=X"))
8541 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8542 (match_operand:SI 4 "gpc_reg_operand" "r"))
8543 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8544 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
8545 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8546 "stswi %2,%1,%O0"
8547 [(set_attr "type" "store")
8548 (set_attr "update" "yes")
8549 (set_attr "indexed" "yes")
8550 (set_attr "cell_micro" "always")])
8551 \f
8552 (define_expand "setmemsi"
8553 [(parallel [(set (match_operand:BLK 0 "" "")
8554 (match_operand 2 "const_int_operand" ""))
8555 (use (match_operand:SI 1 "" ""))
8556 (use (match_operand:SI 3 "" ""))])]
8557 ""
8558 "
8559 {
8560 /* If value to set is not zero, use the library routine. */
8561 if (operands[2] != const0_rtx)
8562 FAIL;
8564 if (expand_block_clear (operands))
8565 DONE;
8566 else
8567 FAIL;
8568 }")
8570 ;; String/block move insn.
8571 ;; Argument 0 is the destination
8572 ;; Argument 1 is the source
8573 ;; Argument 2 is the length
8574 ;; Argument 3 is the alignment
8576 (define_expand "movmemsi"
8577 [(parallel [(set (match_operand:BLK 0 "" "")
8578 (match_operand:BLK 1 "" ""))
8579 (use (match_operand:SI 2 "" ""))
8580 (use (match_operand:SI 3 "" ""))])]
8581 ""
8582 "
8583 {
8584 if (expand_block_move (operands))
8585 DONE;
8586 else
8587 FAIL;
8588 }")
8590 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8591 ;; register allocator doesn't have a clue about allocating 8 word registers.
8592 ;; rD/rS = r5 is preferred, efficient form.
8593 (define_expand "movmemsi_8reg"
8594 [(parallel [(set (match_operand 0 "" "")
8595 (match_operand 1 "" ""))
8596 (use (match_operand 2 "" ""))
8597 (use (match_operand 3 "" ""))
8598 (clobber (reg:SI 5))
8599 (clobber (reg:SI 6))
8600 (clobber (reg:SI 7))
8601 (clobber (reg:SI 8))
8602 (clobber (reg:SI 9))
8603 (clobber (reg:SI 10))
8604 (clobber (reg:SI 11))
8605 (clobber (reg:SI 12))
8606 (clobber (match_scratch:SI 4 ""))])]
8607 "TARGET_STRING"
8608 "")
8610 (define_insn ""
8611 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8612 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8613 (use (match_operand:SI 2 "immediate_operand" "i"))
8614 (use (match_operand:SI 3 "immediate_operand" "i"))
8615 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
8616 (clobber (reg:SI 6))
8617 (clobber (reg:SI 7))
8618 (clobber (reg:SI 8))
8619 (clobber (reg:SI 9))
8620 (clobber (reg:SI 10))
8621 (clobber (reg:SI 11))
8622 (clobber (reg:SI 12))
8623 (clobber (match_scratch:SI 5 "=X"))]
8624 "TARGET_STRING
8625 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8626 || INTVAL (operands[2]) == 0)
8627 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8628 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8629 && REGNO (operands[4]) == 5"
8630 "lswi %4,%1,%2\;stswi %4,%0,%2"
8631 [(set_attr "type" "store")
8632 (set_attr "update" "yes")
8633 (set_attr "indexed" "yes")
8634 (set_attr "cell_micro" "always")
8635 (set_attr "length" "8")])
8637 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8638 ;; register allocator doesn't have a clue about allocating 6 word registers.
8639 ;; rD/rS = r5 is preferred, efficient form.
8640 (define_expand "movmemsi_6reg"
8641 [(parallel [(set (match_operand 0 "" "")
8642 (match_operand 1 "" ""))
8643 (use (match_operand 2 "" ""))
8644 (use (match_operand 3 "" ""))
8645 (clobber (reg:SI 5))
8646 (clobber (reg:SI 6))
8647 (clobber (reg:SI 7))
8648 (clobber (reg:SI 8))
8649 (clobber (reg:SI 9))
8650 (clobber (reg:SI 10))
8651 (clobber (match_scratch:SI 4 ""))])]
8652 "TARGET_STRING"
8653 "")
8655 (define_insn ""
8656 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8657 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8658 (use (match_operand:SI 2 "immediate_operand" "i"))
8659 (use (match_operand:SI 3 "immediate_operand" "i"))
8660 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
8661 (clobber (reg:SI 6))
8662 (clobber (reg:SI 7))
8663 (clobber (reg:SI 8))
8664 (clobber (reg:SI 9))
8665 (clobber (reg:SI 10))
8666 (clobber (match_scratch:SI 5 "=X"))]
8667 "TARGET_STRING
8668 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8669 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8670 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8671 && REGNO (operands[4]) == 5"
8672 "lswi %4,%1,%2\;stswi %4,%0,%2"
8673 [(set_attr "type" "store")
8674 (set_attr "update" "yes")
8675 (set_attr "indexed" "yes")
8676 (set_attr "cell_micro" "always")
8677 (set_attr "length" "8")])
8679 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8680 ;; problems with TImode.
8681 ;; rD/rS = r5 is preferred, efficient form.
8682 (define_expand "movmemsi_4reg"
8683 [(parallel [(set (match_operand 0 "" "")
8684 (match_operand 1 "" ""))
8685 (use (match_operand 2 "" ""))
8686 (use (match_operand 3 "" ""))
8687 (clobber (reg:SI 5))
8688 (clobber (reg:SI 6))
8689 (clobber (reg:SI 7))
8690 (clobber (reg:SI 8))
8691 (clobber (match_scratch:SI 4 ""))])]
8692 "TARGET_STRING"
8693 "")
8695 (define_insn ""
8696 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8697 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8698 (use (match_operand:SI 2 "immediate_operand" "i"))
8699 (use (match_operand:SI 3 "immediate_operand" "i"))
8700 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
8701 (clobber (reg:SI 6))
8702 (clobber (reg:SI 7))
8703 (clobber (reg:SI 8))
8704 (clobber (match_scratch:SI 5 "=X"))]
8705 "TARGET_STRING
8706 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8707 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8708 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8709 && REGNO (operands[4]) == 5"
8710 "lswi %4,%1,%2\;stswi %4,%0,%2"
8711 [(set_attr "type" "store")
8712 (set_attr "update" "yes")
8713 (set_attr "indexed" "yes")
8714 (set_attr "cell_micro" "always")
8715 (set_attr "length" "8")])
8717 ;; Move up to 8 bytes at a time.
8718 (define_expand "movmemsi_2reg"
8719 [(parallel [(set (match_operand 0 "" "")
8720 (match_operand 1 "" ""))
8721 (use (match_operand 2 "" ""))
8722 (use (match_operand 3 "" ""))
8723 (clobber (match_scratch:DI 4 ""))
8724 (clobber (match_scratch:SI 5 ""))])]
8725 "TARGET_STRING && ! TARGET_POWERPC64"
8726 "")
8728 (define_insn ""
8729 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8730 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8731 (use (match_operand:SI 2 "immediate_operand" "i"))
8732 (use (match_operand:SI 3 "immediate_operand" "i"))
8733 (clobber (match_scratch:DI 4 "=&r"))
8734 (clobber (match_scratch:SI 5 "=X"))]
8735 "TARGET_STRING && ! TARGET_POWERPC64
8736 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8737 "lswi %4,%1,%2\;stswi %4,%0,%2"
8738 [(set_attr "type" "store")
8739 (set_attr "update" "yes")
8740 (set_attr "indexed" "yes")
8741 (set_attr "cell_micro" "always")
8742 (set_attr "length" "8")])
8744 ;; Move up to 4 bytes at a time.
8745 (define_expand "movmemsi_1reg"
8746 [(parallel [(set (match_operand 0 "" "")
8747 (match_operand 1 "" ""))
8748 (use (match_operand 2 "" ""))
8749 (use (match_operand 3 "" ""))
8750 (clobber (match_scratch:SI 4 ""))
8751 (clobber (match_scratch:SI 5 ""))])]
8752 "TARGET_STRING"
8753 "")
8755 (define_insn ""
8756 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
8757 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
8758 (use (match_operand:SI 2 "immediate_operand" "i"))
8759 (use (match_operand:SI 3 "immediate_operand" "i"))
8760 (clobber (match_scratch:SI 4 "=&r"))
8761 (clobber (match_scratch:SI 5 "=X"))]
8762 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8763 "lswi %4,%1,%2\;stswi %4,%0,%2"
8764 [(set_attr "type" "store")
8765 (set_attr "update" "yes")
8766 (set_attr "indexed" "yes")
8767 (set_attr "cell_micro" "always")
8768 (set_attr "length" "8")])
8769 \f
8770 ;; Define insns that do load or store with update. Some of these we can
8771 ;; get by using pre-decrement or pre-increment, but the hardware can also
8772 ;; do cases where the increment is not the size of the object.
8773 ;;
8774 ;; In all these cases, we use operands 0 and 1 for the register being
8775 ;; incremented because those are the operands that local-alloc will
8776 ;; tie and these are the pair most likely to be tieable (and the ones
8777 ;; that will benefit the most).
8779 (define_insn "*movdi_update1"
8780 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8781 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8782 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
8783 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8784 (plus:DI (match_dup 1) (match_dup 2)))]
8785 "TARGET_POWERPC64 && TARGET_UPDATE
8786 && (!avoiding_indexed_address_p (DImode)
8787 || !gpc_reg_operand (operands[2], DImode))"
8788 "@
8789 ldux %3,%0,%2
8790 ldu %3,%2(%0)"
8791 [(set_attr "type" "load")
8792 (set_attr "update" "yes")
8793 (set_attr "indexed" "yes,no")])
8795 (define_insn "movdi_<mode>_update"
8796 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8797 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8798 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8799 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8800 (plus:P (match_dup 1) (match_dup 2)))]
8801 "TARGET_POWERPC64 && TARGET_UPDATE
8802 && (!avoiding_indexed_address_p (Pmode)
8803 || !gpc_reg_operand (operands[2], Pmode)
8804 || (REG_P (operands[0])
8805 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
8806 "@
8807 stdux %3,%0,%2
8808 stdu %3,%2(%0)"
8809 [(set_attr "type" "store")
8810 (set_attr "update" "yes")
8811 (set_attr "indexed" "yes,no")])
8813 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
8814 ;; needed for stack allocation, even if the user passes -mno-update.
8815 (define_insn "movdi_<mode>_update_stack"
8816 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
8817 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
8818 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8819 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
8820 (plus:P (match_dup 1) (match_dup 2)))]
8821 "TARGET_POWERPC64"
8822 "@
8823 stdux %3,%0,%2
8824 stdu %3,%2(%0)"
8825 [(set_attr "type" "store")
8826 (set_attr "update" "yes")
8827 (set_attr "indexed" "yes,no")])
8829 (define_insn "*movsi_update1"
8830 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8831 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8832 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8833 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8834 (plus:SI (match_dup 1) (match_dup 2)))]
8835 "TARGET_UPDATE
8836 && (!avoiding_indexed_address_p (SImode)
8837 || !gpc_reg_operand (operands[2], SImode))"
8838 "@
8839 lwzux %3,%0,%2
8840 lwzu %3,%2(%0)"
8841 [(set_attr "type" "load")
8842 (set_attr "update" "yes")
8843 (set_attr "indexed" "yes,no")])
8845 (define_insn "*movsi_update2"
8846 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8847 (sign_extend:DI
8848 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8849 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8850 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8851 (plus:DI (match_dup 1) (match_dup 2)))]
8852 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
8853 && !avoiding_indexed_address_p (DImode)"
8854 "lwaux %3,%0,%2"
8855 [(set_attr "type" "load")
8856 (set_attr "sign_extend" "yes")
8857 (set_attr "update" "yes")
8858 (set_attr "indexed" "yes")])
8860 (define_insn "movsi_update"
8861 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8862 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8863 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8864 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8865 (plus:SI (match_dup 1) (match_dup 2)))]
8866 "TARGET_UPDATE
8867 && (!avoiding_indexed_address_p (SImode)
8868 || !gpc_reg_operand (operands[2], SImode)
8869 || (REG_P (operands[0])
8870 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
8871 "@
8872 stwux %3,%0,%2
8873 stwu %3,%2(%0)"
8874 [(set_attr "type" "store")
8875 (set_attr "update" "yes")
8876 (set_attr "indexed" "yes,no")])
8878 ;; This is an unconditional pattern; needed for stack allocation, even
8879 ;; if the user passes -mno-update.
8880 (define_insn "movsi_update_stack"
8881 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8882 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8883 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8884 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8885 (plus:SI (match_dup 1) (match_dup 2)))]
8886 ""
8887 "@
8888 stwux %3,%0,%2
8889 stwu %3,%2(%0)"
8890 [(set_attr "type" "store")
8891 (set_attr "update" "yes")
8892 (set_attr "indexed" "yes,no")])
8894 (define_insn "*movhi_update1"
8895 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8896 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8897 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8898 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8899 (plus:SI (match_dup 1) (match_dup 2)))]
8900 "TARGET_UPDATE
8901 && (!avoiding_indexed_address_p (SImode)
8902 || !gpc_reg_operand (operands[2], SImode))"
8903 "@
8904 lhzux %3,%0,%2
8905 lhzu %3,%2(%0)"
8906 [(set_attr "type" "load")
8907 (set_attr "update" "yes")
8908 (set_attr "indexed" "yes,no")])
8910 (define_insn "*movhi_update2"
8911 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8912 (zero_extend:SI
8913 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8914 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8915 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8916 (plus:SI (match_dup 1) (match_dup 2)))]
8917 "TARGET_UPDATE
8918 && (!avoiding_indexed_address_p (SImode)
8919 || !gpc_reg_operand (operands[2], SImode))"
8920 "@
8921 lhzux %3,%0,%2
8922 lhzu %3,%2(%0)"
8923 [(set_attr "type" "load")
8924 (set_attr "update" "yes")
8925 (set_attr "indexed" "yes,no")])
8927 (define_insn "*movhi_update3"
8928 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8929 (sign_extend:SI
8930 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8931 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8932 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8933 (plus:SI (match_dup 1) (match_dup 2)))]
8934 "TARGET_UPDATE && rs6000_gen_cell_microcode
8935 && (!avoiding_indexed_address_p (SImode)
8936 || !gpc_reg_operand (operands[2], SImode))"
8937 "@
8938 lhaux %3,%0,%2
8939 lhau %3,%2(%0)"
8940 [(set_attr "type" "load")
8941 (set_attr "sign_extend" "yes")
8942 (set_attr "update" "yes")
8943 (set_attr "indexed" "yes,no")])
8945 (define_insn "*movhi_update4"
8946 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8947 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8948 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8949 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8950 (plus:SI (match_dup 1) (match_dup 2)))]
8951 "TARGET_UPDATE
8952 && (!avoiding_indexed_address_p (SImode)
8953 || !gpc_reg_operand (operands[2], SImode))"
8954 "@
8955 sthux %3,%0,%2
8956 sthu %3,%2(%0)"
8957 [(set_attr "type" "store")
8958 (set_attr "update" "yes")
8959 (set_attr "indexed" "yes,no")])
8961 (define_insn "*movqi_update1"
8962 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8963 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8964 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8965 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8966 (plus:SI (match_dup 1) (match_dup 2)))]
8967 "TARGET_UPDATE
8968 && (!avoiding_indexed_address_p (SImode)
8969 || !gpc_reg_operand (operands[2], SImode))"
8970 "@
8971 lbzux %3,%0,%2
8972 lbzu %3,%2(%0)"
8973 [(set_attr "type" "load")
8974 (set_attr "update" "yes")
8975 (set_attr "indexed" "yes,no")])
8977 (define_insn "*movqi_update2"
8978 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8979 (zero_extend:SI
8980 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8981 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8982 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8983 (plus:SI (match_dup 1) (match_dup 2)))]
8984 "TARGET_UPDATE
8985 && (!avoiding_indexed_address_p (SImode)
8986 || !gpc_reg_operand (operands[2], SImode))"
8987 "@
8988 lbzux %3,%0,%2
8989 lbzu %3,%2(%0)"
8990 [(set_attr "type" "load")
8991 (set_attr "update" "yes")
8992 (set_attr "indexed" "yes,no")])
8994 (define_insn "*movqi_update3"
8995 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8996 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8997 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8998 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8999 (plus:SI (match_dup 1) (match_dup 2)))]
9000 "TARGET_UPDATE
9001 && (!avoiding_indexed_address_p (SImode)
9002 || !gpc_reg_operand (operands[2], SImode))"
9003 "@
9004 stbux %3,%0,%2
9005 stbu %3,%2(%0)"
9006 [(set_attr "type" "store")
9007 (set_attr "update" "yes")
9008 (set_attr "indexed" "yes,no")])
9010 (define_insn "*movsf_update1"
9011 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9012 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9013 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9014 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9015 (plus:SI (match_dup 1) (match_dup 2)))]
9016 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9017 && (!avoiding_indexed_address_p (SImode)
9018 || !gpc_reg_operand (operands[2], SImode))"
9019 "@
9020 lfsux %3,%0,%2
9021 lfsu %3,%2(%0)"
9022 [(set_attr "type" "fpload")
9023 (set_attr "update" "yes")
9024 (set_attr "indexed" "yes,no")])
9026 (define_insn "*movsf_update2"
9027 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9028 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9029 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9030 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9031 (plus:SI (match_dup 1) (match_dup 2)))]
9032 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
9033 && (!avoiding_indexed_address_p (SImode)
9034 || !gpc_reg_operand (operands[2], SImode))"
9035 "@
9036 stfsux %3,%0,%2
9037 stfsu %3,%2(%0)"
9038 [(set_attr "type" "fpstore")
9039 (set_attr "update" "yes")
9040 (set_attr "indexed" "yes,no")])
9042 (define_insn "*movsf_update3"
9043 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9044 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9045 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9046 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9047 (plus:SI (match_dup 1) (match_dup 2)))]
9048 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9049 && (!avoiding_indexed_address_p (SImode)
9050 || !gpc_reg_operand (operands[2], SImode))"
9051 "@
9052 lwzux %3,%0,%2
9053 lwzu %3,%2(%0)"
9054 [(set_attr "type" "load")
9055 (set_attr "update" "yes")
9056 (set_attr "indexed" "yes,no")])
9058 (define_insn "*movsf_update4"
9059 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9060 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9061 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9062 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9063 (plus:SI (match_dup 1) (match_dup 2)))]
9064 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
9065 && (!avoiding_indexed_address_p (SImode)
9066 || !gpc_reg_operand (operands[2], SImode))"
9067 "@
9068 stwux %3,%0,%2
9069 stwu %3,%2(%0)"
9070 [(set_attr "type" "store")
9071 (set_attr "update" "yes")
9072 (set_attr "indexed" "yes,no")])
9074 (define_insn "*movdf_update1"
9075 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
9076 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9077 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9078 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9079 (plus:SI (match_dup 1) (match_dup 2)))]
9080 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9081 && (!avoiding_indexed_address_p (SImode)
9082 || !gpc_reg_operand (operands[2], SImode))"
9083 "@
9084 lfdux %3,%0,%2
9085 lfdu %3,%2(%0)"
9086 [(set_attr "type" "fpload")
9087 (set_attr "update" "yes")
9088 (set_attr "indexed" "yes,no")
9089 (set_attr "size" "64")])
9091 (define_insn "*movdf_update2"
9092 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9093 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9094 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
9095 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9096 (plus:SI (match_dup 1) (match_dup 2)))]
9097 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
9098 && (!avoiding_indexed_address_p (SImode)
9099 || !gpc_reg_operand (operands[2], SImode))"
9100 "@
9101 stfdux %3,%0,%2
9102 stfdu %3,%2(%0)"
9103 [(set_attr "type" "fpstore")
9104 (set_attr "update" "yes")
9105 (set_attr "indexed" "yes,no")])
9108 ;; After inserting conditional returns we can sometimes have
9109 ;; unnecessary register moves. Unfortunately we cannot have a
9110 ;; modeless peephole here, because some single SImode sets have early
9111 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9112 ;; sequences, using get_attr_length here will smash the operands
9113 ;; array. Neither is there an early_cobbler_p predicate.
9114 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9115 ;; Also this optimization interferes with scalars going into
9116 ;; altivec registers (the code does reloading through the FPRs).
9117 (define_peephole2
9118 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9119 (match_operand:DF 1 "any_operand" ""))
9120 (set (match_operand:DF 2 "gpc_reg_operand" "")
9121 (match_dup 0))]
9122 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9123 && !TARGET_UPPER_REGS_DF
9124 && peep2_reg_dead_p (2, operands[0])"
9125 [(set (match_dup 2) (match_dup 1))])
9127 (define_peephole2
9128 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9129 (match_operand:SF 1 "any_operand" ""))
9130 (set (match_operand:SF 2 "gpc_reg_operand" "")
9131 (match_dup 0))]
9132 "!TARGET_UPPER_REGS_SF
9133 && peep2_reg_dead_p (2, operands[0])"
9134 [(set (match_dup 2) (match_dup 1))])
9136 \f
9137 ;; TLS support.
9139 ;; Mode attributes for different ABIs.
9140 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
9141 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
9142 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
9143 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
9145 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
9146 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9147 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9148 (match_operand 4 "" "g")))
9149 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9150 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9151 UNSPEC_TLSGD)
9152 (clobber (reg:SI LR_REGNO))]
9153 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9154 {
9155 if (TARGET_CMODEL != CMODEL_SMALL)
9156 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
9157 "bl %z3\;nop";
9158 else
9159 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
9160 }
9161 "&& TARGET_TLS_MARKERS"
9162 [(set (match_dup 0)
9163 (unspec:TLSmode [(match_dup 1)
9164 (match_dup 2)]
9165 UNSPEC_TLSGD))
9166 (parallel [(set (match_dup 0)
9167 (call (mem:TLSmode (match_dup 3))
9168 (match_dup 4)))
9169 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9170 (clobber (reg:SI LR_REGNO))])]
9171 ""
9172 [(set_attr "type" "two")
9173 (set (attr "length")
9174 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9175 (const_int 16)
9176 (const_int 12)))])
9178 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
9179 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9180 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
9181 (match_operand 4 "" "g")))
9182 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9183 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9184 UNSPEC_TLSGD)
9185 (clobber (reg:SI LR_REGNO))]
9186 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9187 {
9188 if (flag_pic)
9189 {
9190 if (TARGET_SECURE_PLT && flag_pic == 2)
9191 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
9192 else
9193 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
9194 }
9195 else
9196 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
9197 }
9198 "&& TARGET_TLS_MARKERS"
9199 [(set (match_dup 0)
9200 (unspec:TLSmode [(match_dup 1)
9201 (match_dup 2)]
9202 UNSPEC_TLSGD))
9203 (parallel [(set (match_dup 0)
9204 (call (mem:TLSmode (match_dup 3))
9205 (match_dup 4)))
9206 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
9207 (clobber (reg:SI LR_REGNO))])]
9208 ""
9209 [(set_attr "type" "two")
9210 (set_attr "length" "8")])
9212 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
9213 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9214 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9215 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9216 UNSPEC_TLSGD))]
9217 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9218 "addi %0,%1,%2@got@tlsgd"
9219 "&& TARGET_CMODEL != CMODEL_SMALL"
9220 [(set (match_dup 3)
9221 (high:TLSmode
9222 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
9223 (set (match_dup 0)
9224 (lo_sum:TLSmode (match_dup 3)
9225 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
9226 "
9227 {
9228 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9229 }"
9230 [(set (attr "length")
9231 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9232 (const_int 8)
9233 (const_int 4)))])
9235 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
9236 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9237 (high:TLSmode
9238 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9239 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9240 UNSPEC_TLSGD)))]
9241 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9242 "addis %0,%1,%2@got@tlsgd@ha"
9243 [(set_attr "length" "4")])
9245 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
9246 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9247 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9248 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9249 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9250 UNSPEC_TLSGD)))]
9251 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9252 "addi %0,%1,%2@got@tlsgd@l"
9253 [(set_attr "length" "4")])
9255 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
9256 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9257 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9258 (match_operand 2 "" "g")))
9259 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9260 UNSPEC_TLSGD)
9261 (clobber (reg:SI LR_REGNO))]
9262 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9263 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9264 "bl %z1(%3@tlsgd)\;nop"
9265 [(set_attr "type" "branch")
9266 (set_attr "length" "8")])
9268 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
9269 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9270 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9271 (match_operand 2 "" "g")))
9272 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
9273 UNSPEC_TLSGD)
9274 (clobber (reg:SI LR_REGNO))]
9275 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9276 {
9277 if (flag_pic)
9278 {
9279 if (TARGET_SECURE_PLT && flag_pic == 2)
9280 return "bl %z1+32768(%3@tlsgd)@plt";
9281 return "bl %z1(%3@tlsgd)@plt";
9282 }
9283 return "bl %z1(%3@tlsgd)";
9284 }
9285 [(set_attr "type" "branch")
9286 (set_attr "length" "4")])
9288 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
9289 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9290 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9291 (match_operand 3 "" "g")))
9292 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9293 UNSPEC_TLSLD)
9294 (clobber (reg:SI LR_REGNO))]
9295 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9296 {
9297 if (TARGET_CMODEL != CMODEL_SMALL)
9298 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
9299 "bl %z2\;nop";
9300 else
9301 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
9302 }
9303 "&& TARGET_TLS_MARKERS"
9304 [(set (match_dup 0)
9305 (unspec:TLSmode [(match_dup 1)]
9306 UNSPEC_TLSLD))
9307 (parallel [(set (match_dup 0)
9308 (call (mem:TLSmode (match_dup 2))
9309 (match_dup 3)))
9310 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9311 (clobber (reg:SI LR_REGNO))])]
9312 ""
9313 [(set_attr "type" "two")
9314 (set (attr "length")
9315 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9316 (const_int 16)
9317 (const_int 12)))])
9319 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
9320 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9321 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
9322 (match_operand 3 "" "g")))
9323 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9324 UNSPEC_TLSLD)
9325 (clobber (reg:SI LR_REGNO))]
9326 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
9327 {
9328 if (flag_pic)
9329 {
9330 if (TARGET_SECURE_PLT && flag_pic == 2)
9331 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
9332 else
9333 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
9334 }
9335 else
9336 return "addi %0,%1,%&@got@tlsld\;bl %z2";
9337 }
9338 "&& TARGET_TLS_MARKERS"
9339 [(set (match_dup 0)
9340 (unspec:TLSmode [(match_dup 1)]
9341 UNSPEC_TLSLD))
9342 (parallel [(set (match_dup 0)
9343 (call (mem:TLSmode (match_dup 2))
9344 (match_dup 3)))
9345 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9346 (clobber (reg:SI LR_REGNO))])]
9347 ""
9348 [(set_attr "length" "8")])
9350 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
9351 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9352 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9353 UNSPEC_TLSLD))]
9354 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
9355 "addi %0,%1,%&@got@tlsld"
9356 "&& TARGET_CMODEL != CMODEL_SMALL"
9357 [(set (match_dup 2)
9358 (high:TLSmode
9359 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
9360 (set (match_dup 0)
9361 (lo_sum:TLSmode (match_dup 2)
9362 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
9363 "
9364 {
9365 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9366 }"
9367 [(set (attr "length")
9368 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9369 (const_int 8)
9370 (const_int 4)))])
9372 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
9373 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9374 (high:TLSmode
9375 (unspec:TLSmode [(const_int 0)
9376 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
9377 UNSPEC_TLSLD)))]
9378 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9379 "addis %0,%1,%&@got@tlsld@ha"
9380 [(set_attr "length" "4")])
9382 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
9383 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9384 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9385 (unspec:TLSmode [(const_int 0)
9386 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
9387 UNSPEC_TLSLD)))]
9388 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
9389 "addi %0,%1,%&@got@tlsld@l"
9390 [(set_attr "length" "4")])
9392 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
9393 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9394 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9395 (match_operand 2 "" "g")))
9396 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9397 (clobber (reg:SI LR_REGNO))]
9398 "HAVE_AS_TLS && TARGET_TLS_MARKERS
9399 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
9400 "bl %z1(%&@tlsld)\;nop"
9401 [(set_attr "type" "branch")
9402 (set_attr "length" "8")])
9404 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
9405 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9406 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
9407 (match_operand 2 "" "g")))
9408 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
9409 (clobber (reg:SI LR_REGNO))]
9410 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
9411 {
9412 if (flag_pic)
9413 {
9414 if (TARGET_SECURE_PLT && flag_pic == 2)
9415 return "bl %z1+32768(%&@tlsld)@plt";
9416 return "bl %z1(%&@tlsld)@plt";
9417 }
9418 return "bl %z1(%&@tlsld)";
9419 }
9420 [(set_attr "type" "branch")
9421 (set_attr "length" "4")])
9423 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
9424 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9425 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9426 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9427 UNSPEC_TLSDTPREL))]
9428 "HAVE_AS_TLS"
9429 "addi %0,%1,%2@dtprel")
9431 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
9432 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9433 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9434 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9435 UNSPEC_TLSDTPRELHA))]
9436 "HAVE_AS_TLS"
9437 "addis %0,%1,%2@dtprel@ha")
9439 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
9440 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9441 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9442 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9443 UNSPEC_TLSDTPRELLO))]
9444 "HAVE_AS_TLS"
9445 "addi %0,%1,%2@dtprel@l")
9447 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
9448 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9449 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9450 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9451 UNSPEC_TLSGOTDTPREL))]
9452 "HAVE_AS_TLS"
9453 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
9454 "&& TARGET_CMODEL != CMODEL_SMALL"
9455 [(set (match_dup 3)
9456 (high:TLSmode
9457 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
9458 (set (match_dup 0)
9459 (lo_sum:TLSmode (match_dup 3)
9460 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
9461 "
9462 {
9463 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9464 }"
9465 [(set (attr "length")
9466 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9467 (const_int 8)
9468 (const_int 4)))])
9470 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
9471 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9472 (high:TLSmode
9473 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9474 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9475 UNSPEC_TLSGOTDTPREL)))]
9476 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9477 "addis %0,%1,%2@got@dtprel@ha"
9478 [(set_attr "length" "4")])
9480 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
9481 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9482 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9483 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9484 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9485 UNSPEC_TLSGOTDTPREL)))]
9486 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9487 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
9488 [(set_attr "length" "4")])
9490 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
9491 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9492 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9493 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9494 UNSPEC_TLSTPREL))]
9495 "HAVE_AS_TLS"
9496 "addi %0,%1,%2@tprel")
9498 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
9499 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9500 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9501 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9502 UNSPEC_TLSTPRELHA))]
9503 "HAVE_AS_TLS"
9504 "addis %0,%1,%2@tprel@ha")
9506 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
9507 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9508 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9509 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9510 UNSPEC_TLSTPRELLO))]
9511 "HAVE_AS_TLS"
9512 "addi %0,%1,%2@tprel@l")
9514 ;; "b" output constraint here and on tls_tls input to support linker tls
9515 ;; optimization. The linker may edit the instructions emitted by a
9516 ;; tls_got_tprel/tls_tls pair to addis,addi.
9517 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
9518 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9519 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9520 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9521 UNSPEC_TLSGOTTPREL))]
9522 "HAVE_AS_TLS"
9523 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
9524 "&& TARGET_CMODEL != CMODEL_SMALL"
9525 [(set (match_dup 3)
9526 (high:TLSmode
9527 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
9528 (set (match_dup 0)
9529 (lo_sum:TLSmode (match_dup 3)
9530 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
9531 "
9532 {
9533 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
9534 }"
9535 [(set (attr "length")
9536 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
9537 (const_int 8)
9538 (const_int 4)))])
9540 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
9541 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
9542 (high:TLSmode
9543 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9544 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9545 UNSPEC_TLSGOTTPREL)))]
9546 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9547 "addis %0,%1,%2@got@tprel@ha"
9548 [(set_attr "length" "4")])
9550 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
9551 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9552 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
9553 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
9554 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9555 UNSPEC_TLSGOTTPREL)))]
9556 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
9557 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
9558 [(set_attr "length" "4")])
9560 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
9561 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
9562 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
9563 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
9564 UNSPEC_TLSTLS))]
9565 "TARGET_ELF && HAVE_AS_TLS"
9566 "add %0,%1,%2@tls")
9568 (define_expand "tls_get_tpointer"
9569 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9570 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
9571 "TARGET_XCOFF && HAVE_AS_TLS"
9572 "
9573 {
9574 emit_insn (gen_tls_get_tpointer_internal ());
9575 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
9576 DONE;
9577 }")
9579 (define_insn "tls_get_tpointer_internal"
9580 [(set (reg:SI 3)
9581 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
9582 (clobber (reg:SI LR_REGNO))]
9583 "TARGET_XCOFF && HAVE_AS_TLS"
9584 "bla __get_tpointer")
9586 (define_expand "tls_get_addr<mode>"
9587 [(set (match_operand:P 0 "gpc_reg_operand" "")
9588 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
9589 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
9590 "TARGET_XCOFF && HAVE_AS_TLS"
9591 "
9592 {
9593 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
9594 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
9595 emit_insn (gen_tls_get_addr_internal<mode> ());
9596 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
9597 DONE;
9598 }")
9600 (define_insn "tls_get_addr_internal<mode>"
9601 [(set (reg:P 3)
9602 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
9603 (clobber (reg:P 0))
9604 (clobber (reg:P 4))
9605 (clobber (reg:P 5))
9606 (clobber (reg:P 11))
9607 (clobber (reg:CC CR0_REGNO))
9608 (clobber (reg:P LR_REGNO))]
9609 "TARGET_XCOFF && HAVE_AS_TLS"
9610 "bla __tls_get_addr")
9611 \f
9612 ;; Next come insns related to the calling sequence.
9613 ;;
9614 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9615 ;; We move the back-chain and decrement the stack pointer.
9617 (define_expand "allocate_stack"
9618 [(set (match_operand 0 "gpc_reg_operand" "")
9619 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9620 (set (reg 1)
9621 (minus (reg 1) (match_dup 1)))]
9622 ""
9623 "
9624 { rtx chain = gen_reg_rtx (Pmode);
9625 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9626 rtx neg_op0;
9627 rtx insn, par, set, mem;
9629 emit_move_insn (chain, stack_bot);
9631 /* Check stack bounds if necessary. */
9632 if (crtl->limit_stack)
9633 {
9634 rtx available;
9635 available = expand_binop (Pmode, sub_optab,
9636 stack_pointer_rtx, stack_limit_rtx,
9637 NULL_RTX, 1, OPTAB_WIDEN);
9638 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9639 }
9641 if (GET_CODE (operands[1]) != CONST_INT
9642 || INTVAL (operands[1]) < -32767
9643 || INTVAL (operands[1]) > 32768)
9644 {
9645 neg_op0 = gen_reg_rtx (Pmode);
9646 if (TARGET_32BIT)
9647 emit_insn (gen_negsi2 (neg_op0, operands[1]));
9648 else
9649 emit_insn (gen_negdi2 (neg_op0, operands[1]));
9650 }
9651 else
9652 neg_op0 = GEN_INT (- INTVAL (operands[1]));
9654 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
9655 : gen_movdi_di_update_stack))
9656 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
9657 chain));
9658 /* Since we didn't use gen_frame_mem to generate the MEM, grab
9659 it now and set the alias set/attributes. The above gen_*_update
9660 calls will generate a PARALLEL with the MEM set being the first
9661 operation. */
9662 par = PATTERN (insn);
9663 gcc_assert (GET_CODE (par) == PARALLEL);
9664 set = XVECEXP (par, 0, 0);
9665 gcc_assert (GET_CODE (set) == SET);
9666 mem = SET_DEST (set);
9667 gcc_assert (MEM_P (mem));
9668 MEM_NOTRAP_P (mem) = 1;
9669 set_mem_alias_set (mem, get_frame_alias_set ());
9671 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9672 DONE;
9673 }")
9675 ;; These patterns say how to save and restore the stack pointer. We need not
9676 ;; save the stack pointer at function level since we are careful to
9677 ;; preserve the backchain. At block level, we have to restore the backchain
9678 ;; when we restore the stack pointer.
9679 ;;
9680 ;; For nonlocal gotos, we must save both the stack pointer and its
9681 ;; backchain and restore both. Note that in the nonlocal case, the
9682 ;; save area is a memory location.
9684 (define_expand "save_stack_function"
9685 [(match_operand 0 "any_operand" "")
9686 (match_operand 1 "any_operand" "")]
9687 ""
9688 "DONE;")
9690 (define_expand "restore_stack_function"
9691 [(match_operand 0 "any_operand" "")
9692 (match_operand 1 "any_operand" "")]
9693 ""
9694 "DONE;")
9696 ;; Adjust stack pointer (op0) to a new value (op1).
9697 ;; First copy old stack backchain to new location, and ensure that the
9698 ;; scheduler won't reorder the sp assignment before the backchain write.
9699 (define_expand "restore_stack_block"
9700 [(set (match_dup 2) (match_dup 3))
9701 (set (match_dup 4) (match_dup 2))
9702 (match_dup 5)
9703 (set (match_operand 0 "register_operand" "")
9704 (match_operand 1 "register_operand" ""))]
9705 ""
9706 "
9707 {
9708 rtvec p;
9710 operands[1] = force_reg (Pmode, operands[1]);
9711 operands[2] = gen_reg_rtx (Pmode);
9712 operands[3] = gen_frame_mem (Pmode, operands[0]);
9713 operands[4] = gen_frame_mem (Pmode, operands[1]);
9714 p = rtvec_alloc (1);
9715 RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
9716 const0_rtx);
9717 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
9718 }")
9720 (define_expand "save_stack_nonlocal"
9721 [(set (match_dup 3) (match_dup 4))
9722 (set (match_operand 0 "memory_operand" "") (match_dup 3))
9723 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
9724 ""
9725 "
9726 {
9727 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9729 /* Copy the backchain to the first word, sp to the second. */
9730 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
9731 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
9732 operands[3] = gen_reg_rtx (Pmode);
9733 operands[4] = gen_frame_mem (Pmode, operands[1]);
9734 }")
9736 (define_expand "restore_stack_nonlocal"
9737 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
9738 (set (match_dup 3) (match_dup 4))
9739 (set (match_dup 5) (match_dup 2))
9740 (match_dup 6)
9741 (set (match_operand 0 "register_operand" "") (match_dup 3))]
9742 ""
9743 "
9744 {
9745 int units_per_word = (TARGET_32BIT) ? 4 : 8;
9746 rtvec p;
9748 /* Restore the backchain from the first word, sp from the second. */
9749 operands[2] = gen_reg_rtx (Pmode);
9750 operands[3] = gen_reg_rtx (Pmode);
9751 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
9752 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
9753 operands[5] = gen_frame_mem (Pmode, operands[3]);
9754 p = rtvec_alloc (1);
9755 RTVEC_ELT (p, 0) = gen_rtx_SET (gen_frame_mem (BLKmode, operands[0]),
9756 const0_rtx);
9757 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
9758 }")
9759 \f
9760 ;; TOC register handling.
9762 ;; Code to initialize the TOC register...
9764 (define_insn "load_toc_aix_si"
9765 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9766 (unspec:SI [(const_int 0)] UNSPEC_TOC))
9767 (use (reg:SI 2))])]
9768 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
9769 "*
9770 {
9771 char buf[30];
9772 extern int need_toc_init;
9773 need_toc_init = 1;
9774 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9775 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9776 operands[2] = gen_rtx_REG (Pmode, 2);
9777 return \"lwz %0,%1(%2)\";
9778 }"
9779 [(set_attr "type" "load")
9780 (set_attr "update" "no")
9781 (set_attr "indexed" "no")])
9783 (define_insn "load_toc_aix_di"
9784 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9785 (unspec:DI [(const_int 0)] UNSPEC_TOC))
9786 (use (reg:DI 2))])]
9787 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
9788 "*
9789 {
9790 char buf[30];
9791 extern int need_toc_init;
9792 need_toc_init = 1;
9793 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9794 !TARGET_ELF || !TARGET_MINIMAL_TOC);
9795 if (TARGET_ELF)
9796 strcat (buf, \"@toc\");
9797 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9798 operands[2] = gen_rtx_REG (Pmode, 2);
9799 return \"ld %0,%1(%2)\";
9800 }"
9801 [(set_attr "type" "load")
9802 (set_attr "update" "no")
9803 (set_attr "indexed" "no")])
9805 (define_insn "load_toc_v4_pic_si"
9806 [(set (reg:SI LR_REGNO)
9807 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
9808 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9809 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9810 [(set_attr "type" "branch")
9811 (set_attr "length" "4")])
9813 (define_expand "load_toc_v4_PIC_1"
9814 [(parallel [(set (reg:SI LR_REGNO)
9815 (match_operand:SI 0 "immediate_operand" "s"))
9816 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
9817 "TARGET_ELF && DEFAULT_ABI == ABI_V4
9818 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9819 "")
9821 (define_insn "load_toc_v4_PIC_1_normal"
9822 [(set (reg:SI LR_REGNO)
9823 (match_operand:SI 0 "immediate_operand" "s"))
9824 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
9825 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
9826 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9827 "bcl 20,31,%0\\n%0:"
9828 [(set_attr "type" "branch")
9829 (set_attr "length" "4")
9830 (set_attr "cannot_copy" "yes")])
9832 (define_insn "load_toc_v4_PIC_1_476"
9833 [(set (reg:SI LR_REGNO)
9834 (match_operand:SI 0 "immediate_operand" "s"))
9835 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
9836 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
9837 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
9838 "*
9839 {
9840 char name[32];
9841 static char templ[32];
9843 get_ppc476_thunk_name (name);
9844 sprintf (templ, \"bl %s\\n%%0:\", name);
9845 return templ;
9846 }"
9847 [(set_attr "type" "branch")
9848 (set_attr "length" "4")
9849 (set_attr "cannot_copy" "yes")])
9851 (define_expand "load_toc_v4_PIC_1b"
9852 [(parallel [(set (reg:SI LR_REGNO)
9853 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
9854 (label_ref (match_operand 1 "" ""))]
9855 UNSPEC_TOCPTR))
9856 (match_dup 1)])]
9857 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
9858 "")
9860 (define_insn "load_toc_v4_PIC_1b_normal"
9861 [(set (reg:SI LR_REGNO)
9862 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
9863 (label_ref (match_operand 1 "" ""))]
9864 UNSPEC_TOCPTR))
9865 (match_dup 1)]
9866 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
9867 "bcl 20,31,$+8\;.long %0-$"
9868 [(set_attr "type" "branch")
9869 (set_attr "length" "8")])
9871 (define_insn "load_toc_v4_PIC_1b_476"
9872 [(set (reg:SI LR_REGNO)
9873 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
9874 (label_ref (match_operand 1 "" ""))]
9875 UNSPEC_TOCPTR))
9876 (match_dup 1)]
9877 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
9878 "*
9879 {
9880 char name[32];
9881 static char templ[32];
9883 get_ppc476_thunk_name (name);
9884 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
9885 return templ;
9886 }"
9887 [(set_attr "type" "branch")
9888 (set_attr "length" "16")])
9890 (define_insn "load_toc_v4_PIC_2"
9891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9892 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9893 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9894 (match_operand:SI 3 "immediate_operand" "s")))))]
9895 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
9896 "lwz %0,%2-%3(%1)"
9897 [(set_attr "type" "load")])
9899 (define_insn "load_toc_v4_PIC_3b"
9900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9901 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9902 (high:SI
9903 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9904 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
9905 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
9906 "addis %0,%1,%2-%3@ha")
9908 (define_insn "load_toc_v4_PIC_3c"
9909 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9910 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9911 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
9912 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
9913 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
9914 "addi %0,%1,%2-%3@l")
9916 ;; If the TOC is shared over a translation unit, as happens with all
9917 ;; the kinds of PIC that we support, we need to restore the TOC
9918 ;; pointer only when jumping over units of translation.
9919 ;; On Darwin, we need to reload the picbase.
9921 (define_expand "builtin_setjmp_receiver"
9922 [(use (label_ref (match_operand 0 "" "")))]
9923 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9924 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9925 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9926 "
9927 {
9928 #if TARGET_MACHO
9929 if (DEFAULT_ABI == ABI_DARWIN)
9930 {
9931 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
9932 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9933 rtx tmplabrtx;
9934 char tmplab[20];
9936 crtl->uses_pic_offset_table = 1;
9937 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9938 CODE_LABEL_NUMBER (operands[0]));
9939 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
9941 emit_insn (gen_load_macho_picbase (tmplabrtx));
9942 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
9943 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9944 }
9945 else
9946 #endif
9947 rs6000_emit_load_toc_table (FALSE);
9948 DONE;
9949 }")
9951 ;; Largetoc support
9952 (define_insn "*largetoc_high"
9953 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
9954 (high:DI
9955 (unspec [(match_operand:DI 1 "" "")
9956 (match_operand:DI 2 "gpc_reg_operand" "b")]
9957 UNSPEC_TOCREL)))]
9958 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
9959 "addis %0,%2,%1@toc@ha")
9961 (define_insn "*largetoc_high_aix<mode>"
9962 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
9963 (high:P
9964 (unspec [(match_operand:P 1 "" "")
9965 (match_operand:P 2 "gpc_reg_operand" "b")]
9966 UNSPEC_TOCREL)))]
9967 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
9968 "addis %0,%1@u(%2)")
9970 (define_insn "*largetoc_high_plus"
9971 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
9972 (high:DI
9973 (plus:DI
9974 (unspec [(match_operand:DI 1 "" "")
9975 (match_operand:DI 2 "gpc_reg_operand" "b")]
9976 UNSPEC_TOCREL)
9977 (match_operand:DI 3 "add_cint_operand" "n"))))]
9978 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
9979 "addis %0,%2,%1+%3@toc@ha")
9981 (define_insn "*largetoc_high_plus_aix<mode>"
9982 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
9983 (high:P
9984 (plus:P
9985 (unspec [(match_operand:P 1 "" "")
9986 (match_operand:P 2 "gpc_reg_operand" "b")]
9987 UNSPEC_TOCREL)
9988 (match_operand:P 3 "add_cint_operand" "n"))))]
9989 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
9990 "addis %0,%1+%3@u(%2)")
9992 (define_insn "*largetoc_low"
9993 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9994 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
9995 (match_operand:DI 2 "" "")))]
9996 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
9997 "addi %0,%1,%2@l")
9999 (define_insn "*largetoc_low_aix<mode>"
10000 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
10001 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
10002 (match_operand:P 2 "" "")))]
10003 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
10004 "la %0,%2@l(%1)")
10006 (define_insn_and_split "*tocref<mode>"
10007 [(set (match_operand:P 0 "gpc_reg_operand" "=b")
10008 (match_operand:P 1 "small_toc_ref" "R"))]
10009 "TARGET_TOC"
10010 "la %0,%a1"
10011 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10012 [(set (match_dup 0) (high:P (match_dup 1)))
10013 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10015 ;; Elf specific ways of loading addresses for non-PIC code.
10016 ;; The output of this could be r0, but we make a very strong
10017 ;; preference for a base register because it will usually
10018 ;; be needed there.
10019 (define_insn "elf_high"
10020 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10021 (high:SI (match_operand 1 "" "")))]
10022 "TARGET_ELF && ! TARGET_64BIT"
10023 "lis %0,%1@ha")
10025 (define_insn "elf_low"
10026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10027 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10028 (match_operand 2 "" "")))]
10029 "TARGET_ELF && ! TARGET_64BIT"
10030 "la %0,%2@l(%1)")
10031 \f
10032 ;; Call and call_value insns
10033 (define_expand "call"
10034 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10035 (match_operand 1 "" ""))
10036 (use (match_operand 2 "" ""))
10037 (clobber (reg:SI LR_REGNO))])]
10038 ""
10039 "
10040 {
10041 #if TARGET_MACHO
10042 if (MACHOPIC_INDIRECT)
10043 operands[0] = machopic_indirect_call_target (operands[0]);
10044 #endif
10046 gcc_assert (GET_CODE (operands[0]) == MEM);
10047 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10049 operands[0] = XEXP (operands[0], 0);
10051 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10052 {
10053 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10054 DONE;
10055 }
10057 if (GET_CODE (operands[0]) != SYMBOL_REF
10058 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10059 {
10060 if (INTVAL (operands[2]) & CALL_LONG)
10061 operands[0] = rs6000_longcall_ref (operands[0]);
10063 switch (DEFAULT_ABI)
10064 {
10065 case ABI_V4:
10066 case ABI_DARWIN:
10067 operands[0] = force_reg (Pmode, operands[0]);
10068 break;
10070 default:
10071 gcc_unreachable ();
10072 }
10073 }
10074 }")
10076 (define_expand "call_value"
10077 [(parallel [(set (match_operand 0 "" "")
10078 (call (mem:SI (match_operand 1 "address_operand" ""))
10079 (match_operand 2 "" "")))
10080 (use (match_operand 3 "" ""))
10081 (clobber (reg:SI LR_REGNO))])]
10082 ""
10083 "
10084 {
10085 #if TARGET_MACHO
10086 if (MACHOPIC_INDIRECT)
10087 operands[1] = machopic_indirect_call_target (operands[1]);
10088 #endif
10090 gcc_assert (GET_CODE (operands[1]) == MEM);
10091 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10093 operands[1] = XEXP (operands[1], 0);
10095 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10096 {
10097 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
10098 DONE;
10099 }
10101 if (GET_CODE (operands[1]) != SYMBOL_REF
10102 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10103 {
10104 if (INTVAL (operands[3]) & CALL_LONG)
10105 operands[1] = rs6000_longcall_ref (operands[1]);
10107 switch (DEFAULT_ABI)
10108 {
10109 case ABI_V4:
10110 case ABI_DARWIN:
10111 operands[1] = force_reg (Pmode, operands[1]);
10112 break;
10114 default:
10115 gcc_unreachable ();
10116 }
10117 }
10118 }")
10120 ;; Call to function in current module. No TOC pointer reload needed.
10121 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10122 ;; either the function was not prototyped, or it was prototyped as a
10123 ;; variable argument function. It is > 0 if FP registers were passed
10124 ;; and < 0 if they were not.
10126 (define_insn "*call_local32"
10127 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10128 (match_operand 1 "" "g,g"))
10129 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10130 (clobber (reg:SI LR_REGNO))]
10131 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10132 "*
10133 {
10134 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10135 output_asm_insn (\"crxor 6,6,6\", operands);
10137 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10138 output_asm_insn (\"creqv 6,6,6\", operands);
10140 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10141 }"
10142 [(set_attr "type" "branch")
10143 (set_attr "length" "4,8")])
10145 (define_insn "*call_local64"
10146 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10147 (match_operand 1 "" "g,g"))
10148 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10149 (clobber (reg:SI LR_REGNO))]
10150 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10151 "*
10152 {
10153 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10154 output_asm_insn (\"crxor 6,6,6\", operands);
10156 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10157 output_asm_insn (\"creqv 6,6,6\", operands);
10159 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10160 }"
10161 [(set_attr "type" "branch")
10162 (set_attr "length" "4,8")])
10164 (define_insn "*call_value_local32"
10165 [(set (match_operand 0 "" "")
10166 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10167 (match_operand 2 "" "g,g")))
10168 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10169 (clobber (reg:SI LR_REGNO))]
10170 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10171 "*
10172 {
10173 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10174 output_asm_insn (\"crxor 6,6,6\", operands);
10176 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10177 output_asm_insn (\"creqv 6,6,6\", operands);
10179 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10180 }"
10181 [(set_attr "type" "branch")
10182 (set_attr "length" "4,8")])
10185 (define_insn "*call_value_local64"
10186 [(set (match_operand 0 "" "")
10187 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10188 (match_operand 2 "" "g,g")))
10189 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10190 (clobber (reg:SI LR_REGNO))]
10191 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10192 "*
10193 {
10194 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10195 output_asm_insn (\"crxor 6,6,6\", operands);
10197 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10198 output_asm_insn (\"creqv 6,6,6\", operands);
10200 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10201 }"
10202 [(set_attr "type" "branch")
10203 (set_attr "length" "4,8")])
10206 ;; A function pointer under System V is just a normal pointer
10207 ;; operands[0] is the function pointer
10208 ;; operands[1] is the stack size to clean up
10209 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10210 ;; which indicates how to set cr1
10212 (define_insn "*call_indirect_nonlocal_sysv<mode>"
10213 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
10214 (match_operand 1 "" "g,g,g,g"))
10215 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10216 (clobber (reg:SI LR_REGNO))]
10217 "DEFAULT_ABI == ABI_V4
10218 || DEFAULT_ABI == ABI_DARWIN"
10219 {
10220 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10221 output_asm_insn ("crxor 6,6,6", operands);
10223 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10224 output_asm_insn ("creqv 6,6,6", operands);
10226 return "b%T0l";
10227 }
10228 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10229 (set_attr "length" "4,4,8,8")])
10231 (define_insn_and_split "*call_nonlocal_sysv<mode>"
10232 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10233 (match_operand 1 "" "g,g"))
10234 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10235 (clobber (reg:SI LR_REGNO))]
10236 "(DEFAULT_ABI == ABI_DARWIN
10237 || (DEFAULT_ABI == ABI_V4
10238 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10239 {
10240 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10241 output_asm_insn ("crxor 6,6,6", operands);
10243 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10244 output_asm_insn ("creqv 6,6,6", operands);
10246 #if TARGET_MACHO
10247 return output_call(insn, operands, 0, 2);
10248 #else
10249 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10250 {
10251 gcc_assert (!TARGET_SECURE_PLT);
10252 return "bl %z0@plt";
10253 }
10254 else
10255 return "bl %z0";
10256 #endif
10257 }
10258 "DEFAULT_ABI == ABI_V4
10259 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10260 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10261 [(parallel [(call (mem:SI (match_dup 0))
10262 (match_dup 1))
10263 (use (match_dup 2))
10264 (use (match_dup 3))
10265 (clobber (reg:SI LR_REGNO))])]
10266 {
10267 operands[3] = pic_offset_table_rtx;
10268 }
10269 [(set_attr "type" "branch,branch")
10270 (set_attr "length" "4,8")])
10272 (define_insn "*call_nonlocal_sysv_secure<mode>"
10273 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
10274 (match_operand 1 "" "g,g"))
10275 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10276 (use (match_operand:SI 3 "register_operand" "r,r"))
10277 (clobber (reg:SI LR_REGNO))]
10278 "(DEFAULT_ABI == ABI_V4
10279 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
10280 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
10281 {
10282 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10283 output_asm_insn ("crxor 6,6,6", operands);
10285 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10286 output_asm_insn ("creqv 6,6,6", operands);
10288 if (flag_pic == 2)
10289 /* The magic 32768 offset here and in the other sysv call insns
10290 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10291 See sysv4.h:toc_section. */
10292 return "bl %z0+32768@plt";
10293 else
10294 return "bl %z0@plt";
10295 }
10296 [(set_attr "type" "branch,branch")
10297 (set_attr "length" "4,8")])
10299 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
10300 [(set (match_operand 0 "" "")
10301 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
10302 (match_operand 2 "" "g,g,g,g")))
10303 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10304 (clobber (reg:SI LR_REGNO))]
10305 "DEFAULT_ABI == ABI_V4
10306 || DEFAULT_ABI == ABI_DARWIN"
10307 {
10308 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10309 output_asm_insn ("crxor 6,6,6", operands);
10311 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10312 output_asm_insn ("creqv 6,6,6", operands);
10314 return "b%T1l";
10315 }
10316 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10317 (set_attr "length" "4,4,8,8")])
10319 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
10320 [(set (match_operand 0 "" "")
10321 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10322 (match_operand 2 "" "g,g")))
10323 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10324 (clobber (reg:SI LR_REGNO))]
10325 "(DEFAULT_ABI == ABI_DARWIN
10326 || (DEFAULT_ABI == ABI_V4
10327 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10328 {
10329 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10330 output_asm_insn ("crxor 6,6,6", operands);
10332 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10333 output_asm_insn ("creqv 6,6,6", operands);
10335 #if TARGET_MACHO
10336 return output_call(insn, operands, 1, 3);
10337 #else
10338 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10339 {
10340 gcc_assert (!TARGET_SECURE_PLT);
10341 return "bl %z1@plt";
10342 }
10343 else
10344 return "bl %z1";
10345 #endif
10346 }
10347 "DEFAULT_ABI == ABI_V4
10348 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10349 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10350 [(parallel [(set (match_dup 0)
10351 (call (mem:SI (match_dup 1))
10352 (match_dup 2)))
10353 (use (match_dup 3))
10354 (use (match_dup 4))
10355 (clobber (reg:SI LR_REGNO))])]
10356 {
10357 operands[4] = pic_offset_table_rtx;
10358 }
10359 [(set_attr "type" "branch,branch")
10360 (set_attr "length" "4,8")])
10362 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
10363 [(set (match_operand 0 "" "")
10364 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
10365 (match_operand 2 "" "g,g")))
10366 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10367 (use (match_operand:SI 4 "register_operand" "r,r"))
10368 (clobber (reg:SI LR_REGNO))]
10369 "(DEFAULT_ABI == ABI_V4
10370 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
10371 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
10372 {
10373 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10374 output_asm_insn ("crxor 6,6,6", operands);
10376 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10377 output_asm_insn ("creqv 6,6,6", operands);
10379 if (flag_pic == 2)
10380 return "bl %z1+32768@plt";
10381 else
10382 return "bl %z1@plt";
10383 }
10384 [(set_attr "type" "branch,branch")
10385 (set_attr "length" "4,8")])
10388 ;; Call to AIX abi function in the same module.
10390 (define_insn "*call_local_aix<mode>"
10391 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
10392 (match_operand 1 "" "g"))
10393 (clobber (reg:P LR_REGNO))]
10394 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10395 "bl %z0"
10396 [(set_attr "type" "branch")
10397 (set_attr "length" "4")])
10399 (define_insn "*call_value_local_aix<mode>"
10400 [(set (match_operand 0 "" "")
10401 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
10402 (match_operand 2 "" "g")))
10403 (clobber (reg:P LR_REGNO))]
10404 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10405 "bl %z1"
10406 [(set_attr "type" "branch")
10407 (set_attr "length" "4")])
10409 ;; Call to AIX abi function which may be in another module.
10410 ;; Restore the TOC pointer (r2) after the call.
10412 (define_insn "*call_nonlocal_aix<mode>"
10413 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
10414 (match_operand 1 "" "g"))
10415 (clobber (reg:P LR_REGNO))]
10416 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10417 "bl %z0\;nop"
10418 [(set_attr "type" "branch")
10419 (set_attr "length" "8")])
10421 (define_insn "*call_value_nonlocal_aix<mode>"
10422 [(set (match_operand 0 "" "")
10423 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
10424 (match_operand 2 "" "g")))
10425 (clobber (reg:P LR_REGNO))]
10426 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10427 "bl %z1\;nop"
10428 [(set_attr "type" "branch")
10429 (set_attr "length" "8")])
10431 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
10432 ;; Operand0 is the addresss of the function to call
10433 ;; Operand2 is the location in the function descriptor to load r2 from
10434 ;; Operand3 is the offset of the stack location holding the current TOC pointer
10436 (define_insn "*call_indirect_aix<mode>"
10437 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10438 (match_operand 1 "" "g,g"))
10439 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
10440 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 3 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
10441 (clobber (reg:P LR_REGNO))]
10442 "DEFAULT_ABI == ABI_AIX"
10443 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3(1)"
10444 [(set_attr "type" "jmpreg")
10445 (set_attr "length" "12")])
10447 (define_insn "*call_value_indirect_aix<mode>"
10448 [(set (match_operand 0 "" "")
10449 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10450 (match_operand 2 "" "g,g")))
10451 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
10452 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 4 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
10453 (clobber (reg:P LR_REGNO))]
10454 "DEFAULT_ABI == ABI_AIX"
10455 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4(1)"
10456 [(set_attr "type" "jmpreg")
10457 (set_attr "length" "12")])
10459 ;; Call to indirect functions with the ELFv2 ABI.
10460 ;; Operand0 is the addresss of the function to call
10461 ;; Operand2 is the offset of the stack location holding the current TOC pointer
10463 (define_insn "*call_indirect_elfv2<mode>"
10464 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
10465 (match_operand 1 "" "g,g"))
10466 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 2 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
10467 (clobber (reg:P LR_REGNO))]
10468 "DEFAULT_ABI == ABI_ELFv2"
10469 "b%T0l\;<ptrload> 2,%2(1)"
10470 [(set_attr "type" "jmpreg")
10471 (set_attr "length" "8")])
10473 (define_insn "*call_value_indirect_elfv2<mode>"
10474 [(set (match_operand 0 "" "")
10475 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
10476 (match_operand 2 "" "g,g")))
10477 (set (reg:P TOC_REGNUM) (unspec [(match_operand:P 3 "const_int_operand" "n,n")] UNSPEC_TOCSLOT))
10478 (clobber (reg:P LR_REGNO))]
10479 "DEFAULT_ABI == ABI_ELFv2"
10480 "b%T1l\;<ptrload> 2,%3(1)"
10481 [(set_attr "type" "jmpreg")
10482 (set_attr "length" "8")])
10485 ;; Call subroutine returning any type.
10486 (define_expand "untyped_call"
10487 [(parallel [(call (match_operand 0 "" "")
10488 (const_int 0))
10489 (match_operand 1 "" "")
10490 (match_operand 2 "" "")])]
10491 ""
10492 "
10493 {
10494 int i;
10496 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
10498 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10499 {
10500 rtx set = XVECEXP (operands[2], 0, i);
10501 emit_move_insn (SET_DEST (set), SET_SRC (set));
10502 }
10504 /* The optimizer does not know that the call sets the function value
10505 registers we stored in the result block. We avoid problems by
10506 claiming that all hard registers are used and clobbered at this
10507 point. */
10508 emit_insn (gen_blockage ());
10510 DONE;
10511 }")
10513 ;; sibling call patterns
10514 (define_expand "sibcall"
10515 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10516 (match_operand 1 "" ""))
10517 (use (match_operand 2 "" ""))
10518 (use (reg:SI LR_REGNO))
10519 (simple_return)])]
10520 ""
10521 "
10522 {
10523 #if TARGET_MACHO
10524 if (MACHOPIC_INDIRECT)
10525 operands[0] = machopic_indirect_call_target (operands[0]);
10526 #endif
10528 gcc_assert (GET_CODE (operands[0]) == MEM);
10529 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10531 operands[0] = XEXP (operands[0], 0);
10533 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10534 {
10535 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
10536 DONE;
10537 }
10538 }")
10540 (define_expand "sibcall_value"
10541 [(parallel [(set (match_operand 0 "register_operand" "")
10542 (call (mem:SI (match_operand 1 "address_operand" ""))
10543 (match_operand 2 "" "")))
10544 (use (match_operand 3 "" ""))
10545 (use (reg:SI LR_REGNO))
10546 (simple_return)])]
10547 ""
10548 "
10549 {
10550 #if TARGET_MACHO
10551 if (MACHOPIC_INDIRECT)
10552 operands[1] = machopic_indirect_call_target (operands[1]);
10553 #endif
10555 gcc_assert (GET_CODE (operands[1]) == MEM);
10556 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10558 operands[1] = XEXP (operands[1], 0);
10560 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10561 {
10562 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
10563 DONE;
10564 }
10565 }")
10567 ;; this and similar patterns must be marked as using LR, otherwise
10568 ;; dataflow will try to delete the store into it. This is true
10569 ;; even when the actual reg to jump to is in CTR, when LR was
10570 ;; saved and restored around the PIC-setting BCL.
10571 (define_insn "*sibcall_local32"
10572 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10573 (match_operand 1 "" "g,g"))
10574 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10575 (use (reg:SI LR_REGNO))
10576 (simple_return)]
10577 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10578 "*
10579 {
10580 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10581 output_asm_insn (\"crxor 6,6,6\", operands);
10583 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10584 output_asm_insn (\"creqv 6,6,6\", operands);
10586 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10587 }"
10588 [(set_attr "type" "branch")
10589 (set_attr "length" "4,8")])
10591 (define_insn "*sibcall_local64"
10592 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10593 (match_operand 1 "" "g,g"))
10594 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10595 (use (reg:SI LR_REGNO))
10596 (simple_return)]
10597 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10598 "*
10599 {
10600 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10601 output_asm_insn (\"crxor 6,6,6\", operands);
10603 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10604 output_asm_insn (\"creqv 6,6,6\", operands);
10606 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10607 }"
10608 [(set_attr "type" "branch")
10609 (set_attr "length" "4,8")])
10611 (define_insn "*sibcall_value_local32"
10612 [(set (match_operand 0 "" "")
10613 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10614 (match_operand 2 "" "g,g")))
10615 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10616 (use (reg:SI LR_REGNO))
10617 (simple_return)]
10618 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10619 "*
10620 {
10621 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10622 output_asm_insn (\"crxor 6,6,6\", operands);
10624 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10625 output_asm_insn (\"creqv 6,6,6\", operands);
10627 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10628 }"
10629 [(set_attr "type" "branch")
10630 (set_attr "length" "4,8")])
10632 (define_insn "*sibcall_value_local64"
10633 [(set (match_operand 0 "" "")
10634 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10635 (match_operand 2 "" "g,g")))
10636 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10637 (use (reg:SI LR_REGNO))
10638 (simple_return)]
10639 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10640 "*
10641 {
10642 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10643 output_asm_insn (\"crxor 6,6,6\", operands);
10645 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10646 output_asm_insn (\"creqv 6,6,6\", operands);
10648 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10649 }"
10650 [(set_attr "type" "branch")
10651 (set_attr "length" "4,8")])
10653 (define_insn "*sibcall_nonlocal_sysv<mode>"
10654 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
10655 (match_operand 1 "" ""))
10656 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
10657 (use (reg:SI LR_REGNO))
10658 (simple_return)]
10659 "(DEFAULT_ABI == ABI_DARWIN
10660 || DEFAULT_ABI == ABI_V4)
10661 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10662 "*
10663 {
10664 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10665 output_asm_insn (\"crxor 6,6,6\", operands);
10667 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10668 output_asm_insn (\"creqv 6,6,6\", operands);
10670 if (which_alternative >= 2)
10671 return \"b%T0\";
10672 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
10673 {
10674 gcc_assert (!TARGET_SECURE_PLT);
10675 return \"b %z0@plt\";
10676 }
10677 else
10678 return \"b %z0\";
10679 }"
10680 [(set_attr "type" "branch")
10681 (set_attr "length" "4,8,4,8")])
10683 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
10684 [(set (match_operand 0 "" "")
10685 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
10686 (match_operand 2 "" "")))
10687 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
10688 (use (reg:SI LR_REGNO))
10689 (simple_return)]
10690 "(DEFAULT_ABI == ABI_DARWIN
10691 || DEFAULT_ABI == ABI_V4)
10692 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10693 "*
10694 {
10695 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10696 output_asm_insn (\"crxor 6,6,6\", operands);
10698 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10699 output_asm_insn (\"creqv 6,6,6\", operands);
10701 if (which_alternative >= 2)
10702 return \"b%T1\";
10703 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
10704 {
10705 gcc_assert (!TARGET_SECURE_PLT);
10706 return \"b %z1@plt\";
10707 }
10708 else
10709 return \"b %z1\";
10710 }"
10711 [(set_attr "type" "branch")
10712 (set_attr "length" "4,8,4,8")])
10714 ;; AIX ABI sibling call patterns.
10716 (define_insn "*sibcall_aix<mode>"
10717 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
10718 (match_operand 1 "" "g,g"))
10719 (simple_return)]
10720 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10721 "@
10722 b %z0
10723 b%T0"
10724 [(set_attr "type" "branch")
10725 (set_attr "length" "4")])
10727 (define_insn "*sibcall_value_aix<mode>"
10728 [(set (match_operand 0 "" "")
10729 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
10730 (match_operand 2 "" "g,g")))
10731 (simple_return)]
10732 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
10733 "@
10734 b %z1
10735 b%T1"
10736 [(set_attr "type" "branch")
10737 (set_attr "length" "4")])
10739 (define_expand "sibcall_epilogue"
10740 [(use (const_int 0))]
10741 ""
10742 {
10743 if (!TARGET_SCHED_PROLOG)
10744 emit_insn (gen_blockage ());
10745 rs6000_emit_epilogue (TRUE);
10746 DONE;
10747 })
10749 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10750 ;; all of memory. This blocks insns from being moved across this point.
10752 (define_insn "blockage"
10753 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
10754 ""
10755 "")
10757 (define_expand "probe_stack_address"
10758 [(use (match_operand 0 "address_operand"))]
10759 ""
10760 {
10761 operands[0] = gen_rtx_MEM (Pmode, operands[0]);
10762 MEM_VOLATILE_P (operands[0]) = 1;
10764 if (TARGET_64BIT)
10765 emit_insn (gen_probe_stack_di (operands[0]));
10766 else
10767 emit_insn (gen_probe_stack_si (operands[0]));
10768 DONE;
10769 })
10771 (define_insn "probe_stack_<mode>"
10772 [(set (match_operand:P 0 "memory_operand" "=m")
10773 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
10774 ""
10775 {
10776 operands[1] = gen_rtx_REG (Pmode, 0);
10777 return "st<wd>%U0%X0 %1,%0";
10778 }
10779 [(set_attr "type" "store")
10780 (set (attr "update")
10781 (if_then_else (match_operand 0 "update_address_mem")
10782 (const_string "yes")
10783 (const_string "no")))
10784 (set (attr "indexed")
10785 (if_then_else (match_operand 0 "indexed_address_mem")
10786 (const_string "yes")
10787 (const_string "no")))
10788 (set_attr "length" "4")])
10790 (define_insn "probe_stack_range<P:mode>"
10791 [(set (match_operand:P 0 "register_operand" "=r")
10792 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
10793 (match_operand:P 2 "register_operand" "r")]
10794 UNSPECV_PROBE_STACK_RANGE))]
10795 ""
10796 "* return output_probe_stack_range (operands[0], operands[2]);"
10797 [(set_attr "type" "three")])
10798 \f
10799 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10800 ;; signed & unsigned, and one type of branch.
10801 ;;
10802 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10803 ;; insns, and branches.
10805 (define_expand "cbranch<mode>4"
10806 [(use (match_operator 0 "rs6000_cbranch_operator"
10807 [(match_operand:GPR 1 "gpc_reg_operand" "")
10808 (match_operand:GPR 2 "reg_or_short_operand" "")]))
10809 (use (match_operand 3 ""))]
10810 ""
10811 "
10812 {
10813 /* Take care of the possibility that operands[2] might be negative but
10814 this might be a logical operation. That insn doesn't exist. */
10815 if (GET_CODE (operands[2]) == CONST_INT
10816 && INTVAL (operands[2]) < 0)
10817 {
10818 operands[2] = force_reg (<MODE>mode, operands[2]);
10819 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
10820 GET_MODE (operands[0]),
10821 operands[1], operands[2]);
10822 }
10824 rs6000_emit_cbranch (<MODE>mode, operands);
10825 DONE;
10826 }")
10828 (define_expand "cbranch<mode>4"
10829 [(use (match_operator 0 "rs6000_cbranch_operator"
10830 [(match_operand:FP 1 "gpc_reg_operand" "")
10831 (match_operand:FP 2 "gpc_reg_operand" "")]))
10832 (use (match_operand 3 ""))]
10833 ""
10834 "
10835 {
10836 rs6000_emit_cbranch (<MODE>mode, operands);
10837 DONE;
10838 }")
10840 (define_expand "cstore<mode>4_signed"
10841 [(use (match_operator 1 "signed_comparison_operator"
10842 [(match_operand:P 2 "gpc_reg_operand")
10843 (match_operand:P 3 "gpc_reg_operand")]))
10844 (clobber (match_operand:P 0 "gpc_reg_operand"))]
10845 ""
10846 {
10847 enum rtx_code cond_code = GET_CODE (operands[1]);
10849 rtx op0 = operands[0];
10850 rtx op1 = operands[2];
10851 rtx op2 = operands[3];
10853 if (cond_code == GE || cond_code == LT)
10854 {
10855 cond_code = swap_condition (cond_code);
10856 std::swap (op1, op2);
10857 }
10859 rtx tmp1 = gen_reg_rtx (<MODE>mode);
10860 rtx tmp2 = gen_reg_rtx (<MODE>mode);
10861 rtx tmp3 = gen_reg_rtx (<MODE>mode);
10863 int sh = GET_MODE_BITSIZE (<MODE>mode) - 1;
10864 emit_insn (gen_lshr<mode>3 (tmp1, op1, GEN_INT (sh)));
10865 emit_insn (gen_ashr<mode>3 (tmp2, op2, GEN_INT (sh)));
10867 emit_insn (gen_subf<mode>3_carry (tmp3, op1, op2));
10869 if (cond_code == LE)
10870 emit_insn (gen_add<mode>3_carry_in (op0, tmp1, tmp2));
10871 else
10872 {
10873 rtx tmp4 = gen_reg_rtx (<MODE>mode);
10874 emit_insn (gen_add<mode>3_carry_in (tmp4, tmp1, tmp2));
10875 emit_insn (gen_xor<mode>3 (op0, tmp4, const1_rtx));
10876 }
10878 DONE;
10879 })
10881 (define_expand "cstore<mode>4_unsigned"
10882 [(use (match_operator 1 "unsigned_comparison_operator"
10883 [(match_operand:P 2 "gpc_reg_operand")
10884 (match_operand:P 3 "reg_or_short_operand")]))
10885 (clobber (match_operand:P 0 "gpc_reg_operand"))]
10886 ""
10887 {
10888 enum rtx_code cond_code = GET_CODE (operands[1]);
10890 rtx op0 = operands[0];
10891 rtx op1 = operands[2];
10892 rtx op2 = operands[3];
10894 if (cond_code == GEU || cond_code == LTU)
10895 {
10896 cond_code = swap_condition (cond_code);
10897 std::swap (op1, op2);
10898 }
10900 if (!gpc_reg_operand (op1, <MODE>mode))
10901 op1 = force_reg (<MODE>mode, op1);
10902 if (!reg_or_short_operand (op2, <MODE>mode))
10903 op2 = force_reg (<MODE>mode, op2);
10905 rtx tmp = gen_reg_rtx (<MODE>mode);
10906 rtx tmp2 = gen_reg_rtx (<MODE>mode);
10908 emit_insn (gen_subf<mode>3_carry (tmp, op1, op2));
10909 emit_insn (gen_subf<mode>3_carry_in_xx (tmp2));
10911 if (cond_code == LEU)
10912 emit_insn (gen_add<mode>3 (op0, tmp2, const1_rtx));
10913 else
10914 emit_insn (gen_neg<mode>2 (op0, tmp2));
10916 DONE;
10917 })
10919 (define_expand "cstore_si_as_di"
10920 [(use (match_operator 1 "unsigned_comparison_operator"
10921 [(match_operand:SI 2 "gpc_reg_operand")
10922 (match_operand:SI 3 "reg_or_short_operand")]))
10923 (clobber (match_operand:SI 0 "gpc_reg_operand"))]
10924 ""
10925 {
10926 int uns_flag = unsigned_comparison_operator (operands[1], VOIDmode) ? 1 : 0;
10927 enum rtx_code cond_code = signed_condition (GET_CODE (operands[1]));
10929 operands[2] = force_reg (SImode, operands[2]);
10930 operands[3] = force_reg (SImode, operands[3]);
10931 rtx op1 = gen_reg_rtx (DImode);
10932 rtx op2 = gen_reg_rtx (DImode);
10933 convert_move (op1, operands[2], uns_flag);
10934 convert_move (op2, operands[3], uns_flag);
10936 if (cond_code == GT || cond_code == LE)
10937 {
10938 cond_code = swap_condition (cond_code);
10939 std::swap (op1, op2);
10940 }
10942 rtx tmp = gen_reg_rtx (DImode);
10943 rtx tmp2 = gen_reg_rtx (DImode);
10944 emit_insn (gen_subdi3 (tmp, op1, op2));
10945 emit_insn (gen_lshrdi3 (tmp2, tmp, GEN_INT (63)));
10947 rtx tmp3;
10948 switch (cond_code)
10949 {
10950 default:
10951 gcc_unreachable ();
10952 case LT:
10953 tmp3 = tmp2;
10954 break;
10955 case GE:
10956 tmp3 = gen_reg_rtx (DImode);
10957 emit_insn (gen_xordi3 (tmp3, tmp2, const1_rtx));
10958 break;
10959 }
10961 convert_move (operands[0], tmp3, 1);
10963 DONE;
10964 })
10966 (define_expand "cstore<mode>4_signed_imm"
10967 [(use (match_operator 1 "signed_comparison_operator"
10968 [(match_operand:GPR 2 "gpc_reg_operand")
10969 (match_operand:GPR 3 "immediate_operand")]))
10970 (clobber (match_operand:GPR 0 "gpc_reg_operand"))]
10971 ""
10972 {
10973 bool invert = false;
10975 enum rtx_code cond_code = GET_CODE (operands[1]);
10977 rtx op0 = operands[0];
10978 rtx op1 = operands[2];
10979 HOST_WIDE_INT val = INTVAL (operands[3]);
10981 if (cond_code == GE || cond_code == GT)
10982 {
10983 cond_code = reverse_condition (cond_code);
10984 invert = true;
10985 }
10987 if (cond_code == LE)
10988 val++;
10990 rtx tmp = gen_reg_rtx (<MODE>mode);
10991 emit_insn (gen_add<mode>3 (tmp, op1, GEN_INT (-val)));
10992 rtx x = gen_reg_rtx (<MODE>mode);
10993 if (val < 0)
10994 emit_insn (gen_and<mode>3 (x, op1, tmp));
10995 else
10996 emit_insn (gen_ior<mode>3 (x, op1, tmp));
10998 if (invert)
10999 {
11000 rtx tmp = gen_reg_rtx (<MODE>mode);
11001 emit_insn (gen_one_cmpl<mode>2 (tmp, x));
11002 x = tmp;
11003 }
11005 int sh = GET_MODE_BITSIZE (<MODE>mode) - 1;
11006 emit_insn (gen_lshr<mode>3 (op0, x, GEN_INT (sh)));
11008 DONE;
11009 })
11011 (define_expand "cstore<mode>4_unsigned_imm"
11012 [(use (match_operator 1 "unsigned_comparison_operator"
11013 [(match_operand:GPR 2 "gpc_reg_operand")
11014 (match_operand:GPR 3 "immediate_operand")]))
11015 (clobber (match_operand:GPR 0 "gpc_reg_operand"))]
11016 ""
11017 {
11018 bool invert = false;
11020 enum rtx_code cond_code = GET_CODE (operands[1]);
11022 rtx op0 = operands[0];
11023 rtx op1 = operands[2];
11024 HOST_WIDE_INT val = INTVAL (operands[3]);
11026 if (cond_code == GEU || cond_code == GTU)
11027 {
11028 cond_code = reverse_condition (cond_code);
11029 invert = true;
11030 }
11032 if (cond_code == LEU)
11033 val++;
11035 rtx tmp = gen_reg_rtx (<MODE>mode);
11036 rtx tmp2 = gen_reg_rtx (<MODE>mode);
11037 emit_insn (gen_add<mode>3 (tmp, op1, GEN_INT (-val)));
11038 emit_insn (gen_one_cmpl<mode>2 (tmp2, op1));
11039 rtx x = gen_reg_rtx (<MODE>mode);
11040 if (val < 0)
11041 emit_insn (gen_ior<mode>3 (x, tmp, tmp2));
11042 else
11043 emit_insn (gen_and<mode>3 (x, tmp, tmp2));
11045 if (invert)
11046 {
11047 rtx tmp = gen_reg_rtx (<MODE>mode);
11048 emit_insn (gen_one_cmpl<mode>2 (tmp, x));
11049 x = tmp;
11050 }
11052 int sh = GET_MODE_BITSIZE (<MODE>mode) - 1;
11053 emit_insn (gen_lshr<mode>3 (op0, x, GEN_INT (sh)));
11055 DONE;
11056 })
11058 (define_expand "cstore<mode>4"
11059 [(use (match_operator 1 "rs6000_cbranch_operator"
11060 [(match_operand:GPR 2 "gpc_reg_operand")
11061 (match_operand:GPR 3 "reg_or_short_operand")]))
11062 (clobber (match_operand:GPR 0 "gpc_reg_operand"))]
11063 ""
11064 {
11065 /* Use ISEL if the user asked for it. */
11066 if (TARGET_ISEL)
11067 rs6000_emit_sISEL (<MODE>mode, operands);
11069 /* Expanding EQ and NE directly to some machine instructions does not help
11070 but does hurt combine. So don't. */
11071 else if (GET_CODE (operands[1]) == EQ)
11072 emit_insn (gen_eq<mode>3 (operands[0], operands[2], operands[3]));
11073 else if (<MODE>mode == Pmode
11074 && GET_CODE (operands[1]) == NE)
11075 emit_insn (gen_ne<mode>3 (operands[0], operands[2], operands[3]));
11076 else if (GET_CODE (operands[1]) == NE)
11077 {
11078 rtx tmp = gen_reg_rtx (<MODE>mode);
11079 emit_insn (gen_eq<mode>3 (tmp, operands[2], operands[3]));
11080 emit_insn (gen_xor<mode>3 (operands[0], tmp, const1_rtx));
11081 }
11083 /* Expanding the unsigned comparisons however helps a lot: all the neg_ltu
11084 etc. combinations magically work out just right. */
11085 else if (<MODE>mode == Pmode
11086 && unsigned_comparison_operator (operands[1], VOIDmode))
11087 emit_insn (gen_cstore<mode>4_unsigned (operands[0], operands[1],
11088 operands[2], operands[3]));
11090 /* For comparisons smaller than Pmode we can cheaply do things in Pmode. */
11091 else if (<MODE>mode == SImode && Pmode == DImode)
11092 emit_insn (gen_cstore_si_as_di (operands[0], operands[1],
11093 operands[2], operands[3]));
11095 /* For signed comparisons against a constant, we can do some simple
11096 bit-twiddling. */
11097 else if (signed_comparison_operator (operands[1], VOIDmode)
11098 && CONST_INT_P (operands[3]))
11099 emit_insn (gen_cstore<mode>4_signed_imm (operands[0], operands[1],
11100 operands[2], operands[3]));
11102 /* And similarly for unsigned comparisons. */
11103 else if (unsigned_comparison_operator (operands[1], VOIDmode)
11104 && CONST_INT_P (operands[3]))
11105 emit_insn (gen_cstore<mode>4_unsigned_imm (operands[0], operands[1],
11106 operands[2], operands[3]));
11108 /* We also do not want to use mfcr for signed comparisons. */
11109 else if (<MODE>mode == Pmode
11110 && signed_comparison_operator (operands[1], VOIDmode))
11111 emit_insn (gen_cstore<mode>4_signed (operands[0], operands[1],
11112 operands[2], operands[3]));
11114 /* Everything else, use the mfcr brute force. */
11115 else
11116 rs6000_emit_sCOND (<MODE>mode, operands);
11118 DONE;
11119 })
11121 (define_expand "cstore<mode>4"
11122 [(use (match_operator 1 "rs6000_cbranch_operator"
11123 [(match_operand:FP 2 "gpc_reg_operand")
11124 (match_operand:FP 3 "gpc_reg_operand")]))
11125 (clobber (match_operand:SI 0 "gpc_reg_operand"))]
11126 ""
11127 {
11128 rs6000_emit_sCOND (<MODE>mode, operands);
11129 DONE;
11130 })
11133 (define_expand "stack_protect_set"
11134 [(match_operand 0 "memory_operand" "")
11135 (match_operand 1 "memory_operand" "")]
11136 ""
11137 {
11138 #ifdef TARGET_THREAD_SSP_OFFSET
11139 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11140 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11141 operands[1] = gen_rtx_MEM (Pmode, addr);
11142 #endif
11143 if (TARGET_64BIT)
11144 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11145 else
11146 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11147 DONE;
11148 })
11150 (define_insn "stack_protect_setsi"
11151 [(set (match_operand:SI 0 "memory_operand" "=m")
11152 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11153 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11154 "TARGET_32BIT"
11155 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
11156 [(set_attr "type" "three")
11157 (set_attr "length" "12")])
11159 (define_insn "stack_protect_setdi"
11160 [(set (match_operand:DI 0 "memory_operand" "=Y")
11161 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11162 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11163 "TARGET_64BIT"
11164 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
11165 [(set_attr "type" "three")
11166 (set_attr "length" "12")])
11168 (define_expand "stack_protect_test"
11169 [(match_operand 0 "memory_operand" "")
11170 (match_operand 1 "memory_operand" "")
11171 (match_operand 2 "" "")]
11172 ""
11173 {
11174 rtx test, op0, op1;
11175 #ifdef TARGET_THREAD_SSP_OFFSET
11176 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11177 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11178 operands[1] = gen_rtx_MEM (Pmode, addr);
11179 #endif
11180 op0 = operands[0];
11181 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11182 test = gen_rtx_EQ (VOIDmode, op0, op1);
11183 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11184 DONE;
11185 })
11187 (define_insn "stack_protect_testsi"
11188 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11189 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11190 (match_operand:SI 2 "memory_operand" "m,m")]
11191 UNSPEC_SP_TEST))
11192 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11193 (clobber (match_scratch:SI 3 "=&r,&r"))]
11194 "TARGET_32BIT"
11195 "@
11196 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11197 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
11198 [(set_attr "length" "16,20")])
11200 (define_insn "stack_protect_testdi"
11201 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11202 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11203 (match_operand:DI 2 "memory_operand" "Y,Y")]
11204 UNSPEC_SP_TEST))
11205 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11206 (clobber (match_scratch:DI 3 "=&r,&r"))]
11207 "TARGET_64BIT"
11208 "@
11209 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
11210 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
11211 [(set_attr "length" "16,20")])
11213 \f
11214 ;; Here are the actual compare insns.
11215 (define_insn "*cmp<mode>_signed"
11216 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11217 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11218 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11219 ""
11220 "cmp<wd>%I2 %0,%1,%2"
11221 [(set_attr "type" "cmp")])
11223 (define_insn "*cmp<mode>_unsigned"
11224 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11225 (compare:CCUNS (match_operand:GPR 1 "gpc_reg_operand" "r")
11226 (match_operand:GPR 2 "reg_or_u_short_operand" "rK")))]
11227 ""
11228 "cmpl<wd>%I2 %0,%1,%2"
11229 [(set_attr "type" "cmp")])
11231 ;; If we are comparing a register for equality with a large constant,
11232 ;; we can do this with an XOR followed by a compare. But this is profitable
11233 ;; only if the large constant is only used for the comparison (and in this
11234 ;; case we already have a register to reuse as scratch).
11235 ;;
11236 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11237 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11239 (define_peephole2
11240 [(set (match_operand:SI 0 "register_operand")
11241 (match_operand:SI 1 "logical_const_operand" ""))
11242 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11243 [(match_dup 0)
11244 (match_operand:SI 2 "logical_const_operand" "")]))
11245 (set (match_operand:CC 4 "cc_reg_operand" "")
11246 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11247 (match_dup 0)))
11248 (set (pc)
11249 (if_then_else (match_operator 6 "equality_operator"
11250 [(match_dup 4) (const_int 0)])
11251 (match_operand 7 "" "")
11252 (match_operand 8 "" "")))]
11253 "peep2_reg_dead_p (3, operands[0])
11254 && peep2_reg_dead_p (4, operands[4])
11255 && REGNO (operands[0]) != REGNO (operands[5])"
11256 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11257 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11258 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11260 {
11261 /* Get the constant we are comparing against, and see what it looks like
11262 when sign-extended from 16 to 32 bits. Then see what constant we could
11263 XOR with SEXTC to get the sign-extended value. */
11264 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11265 SImode,
11266 operands[1], operands[2]);
11267 HOST_WIDE_INT c = INTVAL (cnst);
11268 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11269 HOST_WIDE_INT xorv = c ^ sextc;
11271 operands[9] = GEN_INT (xorv);
11272 operands[10] = GEN_INT (sextc);
11273 })
11275 ;; The following two insns don't exist as single insns, but if we provide
11276 ;; them, we can swap an add and compare, which will enable us to overlap more
11277 ;; of the required delay between a compare and branch. We generate code for
11278 ;; them by splitting.
11280 (define_insn ""
11281 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11282 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11283 (match_operand:SI 2 "short_cint_operand" "i")))
11284 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11285 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11286 ""
11287 "#"
11288 [(set_attr "length" "8")])
11290 (define_insn ""
11291 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11292 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11293 (match_operand:SI 2 "u_short_cint_operand" "i")))
11294 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11295 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11296 ""
11297 "#"
11298 [(set_attr "length" "8")])
11300 (define_split
11301 [(set (match_operand:CC 3 "cc_reg_operand" "")
11302 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11303 (match_operand:SI 2 "short_cint_operand" "")))
11304 (set (match_operand:SI 0 "gpc_reg_operand" "")
11305 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11306 ""
11307 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11308 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11310 (define_split
11311 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11312 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11313 (match_operand:SI 2 "u_short_cint_operand" "")))
11314 (set (match_operand:SI 0 "gpc_reg_operand" "")
11315 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11316 ""
11317 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11318 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11320 ;; Only need to compare second words if first words equal
11321 (define_insn "*cmp<mode>_internal1"
11322 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11323 (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
11324 (match_operand:IBM128 2 "gpc_reg_operand" "d")))]
11325 "!TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
11326 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11327 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11328 [(set_attr "type" "fpcompare")
11329 (set_attr "length" "12")])
11331 (define_insn_and_split "*cmp<mode>_internal2"
11332 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11333 (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d")
11334 (match_operand:IBM128 2 "gpc_reg_operand" "d")))
11335 (clobber (match_scratch:DF 3 "=d"))
11336 (clobber (match_scratch:DF 4 "=d"))
11337 (clobber (match_scratch:DF 5 "=d"))
11338 (clobber (match_scratch:DF 6 "=d"))
11339 (clobber (match_scratch:DF 7 "=d"))
11340 (clobber (match_scratch:DF 8 "=d"))
11341 (clobber (match_scratch:DF 9 "=d"))
11342 (clobber (match_scratch:DF 10 "=d"))
11343 (clobber (match_scratch:GPR 11 "=b"))]
11344 "TARGET_XL_COMPAT && FLOAT128_IBM_P (<MODE>mode)
11345 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
11346 "#"
11347 "&& reload_completed"
11348 [(set (match_dup 3) (match_dup 14))
11349 (set (match_dup 4) (match_dup 15))
11350 (set (match_dup 9) (abs:DF (match_dup 5)))
11351 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11352 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11353 (label_ref (match_dup 12))
11354 (pc)))
11355 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11356 (set (pc) (label_ref (match_dup 13)))
11357 (match_dup 12)
11358 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11359 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11360 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11361 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
11362 (match_dup 13)]
11363 {
11364 REAL_VALUE_TYPE rv;
11365 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
11366 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
11368 operands[5] = simplify_gen_subreg (DFmode, operands[1], <MODE>mode, hi_word);
11369 operands[6] = simplify_gen_subreg (DFmode, operands[1], <MODE>mode, lo_word);
11370 operands[7] = simplify_gen_subreg (DFmode, operands[2], <MODE>mode, hi_word);
11371 operands[8] = simplify_gen_subreg (DFmode, operands[2], <MODE>mode, lo_word);
11372 operands[12] = gen_label_rtx ();
11373 operands[13] = gen_label_rtx ();
11374 real_inf (&rv);
11375 operands[14] = force_const_mem (DFmode,
11376 const_double_from_real_value (rv, DFmode));
11377 operands[15] = force_const_mem (DFmode,
11378 const_double_from_real_value (dconst0,
11379 DFmode));
11380 if (TARGET_TOC)
11381 {
11382 rtx tocref;
11383 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
11384 operands[14] = gen_const_mem (DFmode, tocref);
11385 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
11386 operands[15] = gen_const_mem (DFmode, tocref);
11387 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11388 set_mem_alias_set (operands[15], get_TOC_alias_set ());
11389 }
11390 })
11391 \f
11392 ;; Now we have the scc insns. We can do some combinations because of the
11393 ;; way the machine works.
11394 ;;
11395 ;; Note that this is probably faster if we can put an insn between the
11396 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11397 ;; cases the insns below which don't use an intermediate CR field will
11398 ;; be used instead.
11399 (define_insn ""
11400 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11401 (match_operator:SI 1 "scc_comparison_operator"
11402 [(match_operand 2 "cc_reg_operand" "y")
11403 (const_int 0)]))]
11404 ""
11405 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11406 [(set (attr "type")
11407 (cond [(match_test "TARGET_MFCRF")
11408 (const_string "mfcrf")
11409 ]
11410 (const_string "mfcr")))
11411 (set_attr "length" "8")])
11413 ;; Same as above, but get the GT bit.
11414 (define_insn "move_from_CR_gt_bit"
11415 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11416 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11417 "TARGET_HARD_FLOAT && !TARGET_FPRS"
11418 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
11419 [(set_attr "type" "mfcr")
11420 (set_attr "length" "8")])
11422 ;; Same as above, but get the OV/ORDERED bit.
11423 (define_insn "move_from_CR_ov_bit"
11424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11425 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
11426 UNSPEC_MV_CR_OV))]
11427 "TARGET_ISEL"
11428 "mfcr %0\;rlwinm %0,%0,%t1,1"
11429 [(set_attr "type" "mfcr")
11430 (set_attr "length" "8")])
11432 (define_insn ""
11433 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11434 (match_operator:DI 1 "scc_comparison_operator"
11435 [(match_operand 2 "cc_reg_operand" "y")
11436 (const_int 0)]))]
11437 "TARGET_POWERPC64"
11438 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
11439 [(set (attr "type")
11440 (cond [(match_test "TARGET_MFCRF")
11441 (const_string "mfcrf")
11442 ]
11443 (const_string "mfcr")))
11444 (set_attr "length" "8")])
11446 (define_insn ""
11447 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11448 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11449 [(match_operand 2 "cc_reg_operand" "y,y")
11450 (const_int 0)])
11451 (const_int 0)))
11452 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11453 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11454 "TARGET_32BIT"
11455 "@
11456 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
11457 #"
11458 [(set_attr "type" "shift")
11459 (set_attr "dot" "yes")
11460 (set_attr "length" "8,16")])
11462 (define_split
11463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11464 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11465 [(match_operand 2 "cc_reg_operand" "")
11466 (const_int 0)])
11467 (const_int 0)))
11468 (set (match_operand:SI 3 "gpc_reg_operand" "")
11469 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11470 "TARGET_32BIT && reload_completed"
11471 [(set (match_dup 3)
11472 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11473 (set (match_dup 0)
11474 (compare:CC (match_dup 3)
11475 (const_int 0)))]
11476 "")
11478 (define_insn ""
11479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11480 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11481 [(match_operand 2 "cc_reg_operand" "y")
11482 (const_int 0)])
11483 (match_operand:SI 3 "const_int_operand" "n")))]
11484 ""
11485 "*
11486 {
11487 int is_bit = ccr_bit (operands[1], 1);
11488 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11489 int count;
11491 if (is_bit >= put_bit)
11492 count = is_bit - put_bit;
11493 else
11494 count = 32 - (put_bit - is_bit);
11496 operands[4] = GEN_INT (count);
11497 operands[5] = GEN_INT (put_bit);
11499 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
11500 }"
11501 [(set (attr "type")
11502 (cond [(match_test "TARGET_MFCRF")
11503 (const_string "mfcrf")
11504 ]
11505 (const_string "mfcr")))
11506 (set_attr "length" "8")])
11508 (define_insn ""
11509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11510 (compare:CC
11511 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11512 [(match_operand 2 "cc_reg_operand" "y,y")
11513 (const_int 0)])
11514 (match_operand:SI 3 "const_int_operand" "n,n"))
11515 (const_int 0)))
11516 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11517 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11518 (match_dup 3)))]
11519 ""
11520 "*
11521 {
11522 int is_bit = ccr_bit (operands[1], 1);
11523 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11524 int count;
11526 /* Force split for non-cc0 compare. */
11527 if (which_alternative == 1)
11528 return \"#\";
11530 if (is_bit >= put_bit)
11531 count = is_bit - put_bit;
11532 else
11533 count = 32 - (put_bit - is_bit);
11535 operands[5] = GEN_INT (count);
11536 operands[6] = GEN_INT (put_bit);
11538 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
11539 }"
11540 [(set_attr "type" "shift")
11541 (set_attr "dot" "yes")
11542 (set_attr "length" "8,16")])
11544 (define_split
11545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
11546 (compare:CC
11547 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11548 [(match_operand 2 "cc_reg_operand" "")
11549 (const_int 0)])
11550 (match_operand:SI 3 "const_int_operand" ""))
11551 (const_int 0)))
11552 (set (match_operand:SI 4 "gpc_reg_operand" "")
11553 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11554 (match_dup 3)))]
11555 "reload_completed"
11556 [(set (match_dup 4)
11557 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11558 (match_dup 3)))
11559 (set (match_dup 0)
11560 (compare:CC (match_dup 4)
11561 (const_int 0)))]
11562 "")
11565 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11566 (DI "rKJI")])
11568 (define_insn_and_split "eq<mode>3"
11569 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11570 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11571 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))
11572 (clobber (match_scratch:GPR 3 "=r"))
11573 (clobber (match_scratch:GPR 4 "=r"))]
11574 ""
11575 "#"
11576 ""
11577 [(set (match_dup 4)
11578 (clz:GPR (match_dup 3)))
11579 (set (match_dup 0)
11580 (lshiftrt:GPR (match_dup 4)
11581 (match_dup 5)))]
11582 {
11583 operands[3] = rs6000_emit_eqne (<MODE>mode,
11584 operands[1], operands[2], operands[3]);
11586 if (GET_CODE (operands[4]) == SCRATCH)
11587 operands[4] = gen_reg_rtx (<MODE>mode);
11589 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11590 }
11591 [(set (attr "length")
11592 (if_then_else (match_test "operands[2] == const0_rtx")
11593 (const_string "8")
11594 (const_string "12")))])
11596 (define_insn_and_split "ne<mode>3"
11597 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11598 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11599 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")))
11600 (clobber (match_scratch:P 3 "=r"))
11601 (clobber (match_scratch:P 4 "=r"))
11602 (clobber (reg:P CA_REGNO))]
11603 "!TARGET_ISEL"
11604 "#"
11605 ""
11606 [(parallel [(set (match_dup 4)
11607 (plus:P (match_dup 3)
11608 (const_int -1)))
11609 (set (reg:P CA_REGNO)
11610 (ne:P (match_dup 3)
11611 (const_int 0)))])
11612 (parallel [(set (match_dup 0)
11613 (plus:P (plus:P (not:P (match_dup 4))
11614 (reg:P CA_REGNO))
11615 (match_dup 3)))
11616 (clobber (reg:P CA_REGNO))])]
11617 {
11618 operands[3] = rs6000_emit_eqne (<MODE>mode,
11619 operands[1], operands[2], operands[3]);
11621 if (GET_CODE (operands[4]) == SCRATCH)
11622 operands[4] = gen_reg_rtx (<MODE>mode);
11623 }
11624 [(set (attr "length")
11625 (if_then_else (match_test "operands[2] == const0_rtx")
11626 (const_string "8")
11627 (const_string "12")))])
11629 (define_insn_and_split "*neg_eq_<mode>"
11630 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11631 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11632 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
11633 (clobber (match_scratch:P 3 "=r"))
11634 (clobber (match_scratch:P 4 "=r"))
11635 (clobber (reg:P CA_REGNO))]
11636 ""
11637 "#"
11638 ""
11639 [(parallel [(set (match_dup 4)
11640 (plus:P (match_dup 3)
11641 (const_int -1)))
11642 (set (reg:P CA_REGNO)
11643 (ne:P (match_dup 3)
11644 (const_int 0)))])
11645 (parallel [(set (match_dup 0)
11646 (plus:P (reg:P CA_REGNO)
11647 (const_int -1)))
11648 (clobber (reg:P CA_REGNO))])]
11649 {
11650 operands[3] = rs6000_emit_eqne (<MODE>mode,
11651 operands[1], operands[2], operands[3]);
11653 if (GET_CODE (operands[4]) == SCRATCH)
11654 operands[4] = gen_reg_rtx (<MODE>mode);
11655 }
11656 [(set (attr "length")
11657 (if_then_else (match_test "operands[2] == const0_rtx")
11658 (const_string "8")
11659 (const_string "12")))])
11661 (define_insn_and_split "*neg_ne_<mode>"
11662 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11663 (neg:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11664 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
11665 (clobber (match_scratch:P 3 "=r"))
11666 (clobber (match_scratch:P 4 "=r"))
11667 (clobber (reg:P CA_REGNO))]
11668 ""
11669 "#"
11670 ""
11671 [(parallel [(set (match_dup 4)
11672 (neg:P (match_dup 3)))
11673 (set (reg:P CA_REGNO)
11674 (eq:P (match_dup 3)
11675 (const_int 0)))])
11676 (parallel [(set (match_dup 0)
11677 (plus:P (reg:P CA_REGNO)
11678 (const_int -1)))
11679 (clobber (reg:P CA_REGNO))])]
11680 {
11681 operands[3] = rs6000_emit_eqne (<MODE>mode,
11682 operands[1], operands[2], operands[3]);
11684 if (GET_CODE (operands[4]) == SCRATCH)
11685 operands[4] = gen_reg_rtx (<MODE>mode);
11686 }
11687 [(set (attr "length")
11688 (if_then_else (match_test "operands[2] == const0_rtx")
11689 (const_string "8")
11690 (const_string "12")))])
11692 (define_insn_and_split "*plus_eq_<mode>"
11693 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11694 (plus:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11695 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11696 (match_operand:P 3 "gpc_reg_operand" "r")))
11697 (clobber (match_scratch:P 4 "=r"))
11698 (clobber (match_scratch:P 5 "=r"))
11699 (clobber (reg:P CA_REGNO))]
11700 ""
11701 "#"
11702 ""
11703 [(parallel [(set (match_dup 5)
11704 (neg:P (match_dup 4)))
11705 (set (reg:P CA_REGNO)
11706 (eq:P (match_dup 4)
11707 (const_int 0)))])
11708 (parallel [(set (match_dup 0)
11709 (plus:P (match_dup 3)
11710 (reg:P CA_REGNO)))
11711 (clobber (reg:P CA_REGNO))])]
11712 {
11713 operands[4] = rs6000_emit_eqne (<MODE>mode,
11714 operands[1], operands[2], operands[4]);
11716 if (GET_CODE (operands[5]) == SCRATCH)
11717 operands[5] = gen_reg_rtx (<MODE>mode);
11718 }
11719 [(set (attr "length")
11720 (if_then_else (match_test "operands[2] == const0_rtx")
11721 (const_string "8")
11722 (const_string "12")))])
11724 (define_insn_and_split "*plus_ne_<mode>"
11725 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11726 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11727 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11728 (match_operand:P 3 "gpc_reg_operand" "r")))
11729 (clobber (match_scratch:P 4 "=r"))
11730 (clobber (match_scratch:P 5 "=r"))
11731 (clobber (reg:P CA_REGNO))]
11732 ""
11733 "#"
11734 ""
11735 [(parallel [(set (match_dup 5)
11736 (plus:P (match_dup 4)
11737 (const_int -1)))
11738 (set (reg:P CA_REGNO)
11739 (ne:P (match_dup 4)
11740 (const_int 0)))])
11741 (parallel [(set (match_dup 0)
11742 (plus:P (match_dup 3)
11743 (reg:P CA_REGNO)))
11744 (clobber (reg:P CA_REGNO))])]
11745 {
11746 operands[4] = rs6000_emit_eqne (<MODE>mode,
11747 operands[1], operands[2], operands[4]);
11749 if (GET_CODE (operands[5]) == SCRATCH)
11750 operands[5] = gen_reg_rtx (<MODE>mode);
11751 }
11752 [(set (attr "length")
11753 (if_then_else (match_test "operands[2] == const0_rtx")
11754 (const_string "8")
11755 (const_string "12")))])
11757 (define_insn_and_split "*minus_eq_<mode>"
11758 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11759 (minus:P (match_operand:P 3 "gpc_reg_operand" "r")
11760 (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
11761 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
11762 (clobber (match_scratch:P 4 "=r"))
11763 (clobber (match_scratch:P 5 "=r"))
11764 (clobber (reg:P CA_REGNO))]
11765 ""
11766 "#"
11767 ""
11768 [(parallel [(set (match_dup 5)
11769 (plus:P (match_dup 4)
11770 (const_int -1)))
11771 (set (reg:P CA_REGNO)
11772 (ne:P (match_dup 4)
11773 (const_int 0)))])
11774 (parallel [(set (match_dup 0)
11775 (plus:P (plus:P (match_dup 3)
11776 (reg:P CA_REGNO))
11777 (const_int -1)))
11778 (clobber (reg:P CA_REGNO))])]
11779 {
11780 operands[4] = rs6000_emit_eqne (<MODE>mode,
11781 operands[1], operands[2], operands[4]);
11783 if (GET_CODE (operands[5]) == SCRATCH)
11784 operands[5] = gen_reg_rtx (<MODE>mode);
11785 }
11786 [(set (attr "length")
11787 (if_then_else (match_test "operands[2] == const0_rtx")
11788 (const_string "8")
11789 (const_string "12")))])
11791 (define_insn_and_split "*minus_ne_<mode>"
11792 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
11793 (minus:P (match_operand:P 3 "gpc_reg_operand" "r")
11794 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
11795 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))
11796 (clobber (match_scratch:P 4 "=r"))
11797 (clobber (match_scratch:P 5 "=r"))
11798 (clobber (reg:P CA_REGNO))]
11799 ""
11800 "#"
11801 ""
11802 [(parallel [(set (match_dup 5)
11803 (neg:P (match_dup 4)))
11804 (set (reg:P CA_REGNO)
11805 (eq:P (match_dup 4)
11806 (const_int 0)))])
11807 (parallel [(set (match_dup 0)
11808 (plus:P (plus:P (match_dup 3)
11809 (reg:P CA_REGNO))
11810 (const_int -1)))
11811 (clobber (reg:P CA_REGNO))])]
11812 {
11813 operands[4] = rs6000_emit_eqne (<MODE>mode,
11814 operands[1], operands[2], operands[4]);
11816 if (GET_CODE (operands[5]) == SCRATCH)
11817 operands[5] = gen_reg_rtx (<MODE>mode);
11818 }
11819 [(set (attr "length")
11820 (if_then_else (match_test "operands[2] == const0_rtx")
11821 (const_string "8")
11822 (const_string "12")))])
11824 (define_insn_and_split "*eqsi3_ext<mode>"
11825 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r")
11826 (eq:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r")
11827 (match_operand:SI 2 "scc_eq_operand" "rKLI")))
11828 (clobber (match_scratch:SI 3 "=r"))
11829 (clobber (match_scratch:SI 4 "=r"))]
11830 ""
11831 "#"
11832 ""
11833 [(set (match_dup 4)
11834 (clz:SI (match_dup 3)))
11835 (set (match_dup 0)
11836 (zero_extend:EXTSI
11837 (lshiftrt:SI (match_dup 4)
11838 (const_int 5))))]
11839 {
11840 operands[3] = rs6000_emit_eqne (SImode,
11841 operands[1], operands[2], operands[3]);
11843 if (GET_CODE (operands[4]) == SCRATCH)
11844 operands[4] = gen_reg_rtx (SImode);
11845 }
11846 [(set (attr "length")
11847 (if_then_else (match_test "operands[2] == const0_rtx")
11848 (const_string "8")
11849 (const_string "12")))])
11851 (define_insn_and_split "*nesi3_ext<mode>"
11852 [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r")
11853 (ne:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r")
11854 (match_operand:SI 2 "scc_eq_operand" "rKLI")))
11855 (clobber (match_scratch:SI 3 "=r"))
11856 (clobber (match_scratch:SI 4 "=r"))
11857 (clobber (match_scratch:EXTSI 5 "=r"))]
11858 ""
11859 "#"
11860 ""
11861 [(set (match_dup 4)
11862 (clz:SI (match_dup 3)))
11863 (set (match_dup 5)
11864 (zero_extend:EXTSI
11865 (lshiftrt:SI (match_dup 4)
11866 (const_int 5))))
11867 (set (match_dup 0)
11868 (xor:EXTSI (match_dup 5)
11869 (const_int 1)))]
11870 {
11871 operands[3] = rs6000_emit_eqne (SImode,
11872 operands[1], operands[2], operands[3]);
11874 if (GET_CODE (operands[4]) == SCRATCH)
11875 operands[4] = gen_reg_rtx (SImode);
11876 if (GET_CODE (operands[5]) == SCRATCH)
11877 operands[5] = gen_reg_rtx (<MODE>mode);
11878 }
11879 [(set (attr "length")
11880 (if_then_else (match_test "operands[2] == const0_rtx")
11881 (const_string "12")
11882 (const_string "16")))])
11883 \f
11884 ;; Define both directions of branch and return. If we need a reload
11885 ;; register, we'd rather use CR0 since it is much easier to copy a
11886 ;; register CC value to there.
11888 (define_insn ""
11889 [(set (pc)
11890 (if_then_else (match_operator 1 "branch_comparison_operator"
11891 [(match_operand 2
11892 "cc_reg_operand" "y")
11893 (const_int 0)])
11894 (label_ref (match_operand 0 "" ""))
11895 (pc)))]
11896 ""
11897 "*
11898 {
11899 return output_cbranch (operands[1], \"%l0\", 0, insn);
11900 }"
11901 [(set_attr "type" "branch")])
11903 (define_insn ""
11904 [(set (pc)
11905 (if_then_else (match_operator 0 "branch_comparison_operator"
11906 [(match_operand 1
11907 "cc_reg_operand" "y")
11908 (const_int 0)])
11909 (any_return)
11910 (pc)))]
11911 "<return_pred>"
11912 "*
11913 {
11914 return output_cbranch (operands[0], NULL, 0, insn);
11915 }"
11916 [(set_attr "type" "jmpreg")
11917 (set_attr "length" "4")])
11919 (define_insn ""
11920 [(set (pc)
11921 (if_then_else (match_operator 1 "branch_comparison_operator"
11922 [(match_operand 2
11923 "cc_reg_operand" "y")
11924 (const_int 0)])
11925 (pc)
11926 (label_ref (match_operand 0 "" ""))))]
11927 ""
11928 "*
11929 {
11930 return output_cbranch (operands[1], \"%l0\", 1, insn);
11931 }"
11932 [(set_attr "type" "branch")])
11934 (define_insn ""
11935 [(set (pc)
11936 (if_then_else (match_operator 0 "branch_comparison_operator"
11937 [(match_operand 1
11938 "cc_reg_operand" "y")
11939 (const_int 0)])
11940 (pc)
11941 (any_return)))]
11942 "<return_pred>"
11943 "*
11944 {
11945 return output_cbranch (operands[0], NULL, 1, insn);
11946 }"
11947 [(set_attr "type" "jmpreg")
11948 (set_attr "length" "4")])
11950 ;; Logic on condition register values.
11952 ; This pattern matches things like
11953 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
11954 ; (eq:SI (reg:CCFP 68) (const_int 0)))
11955 ; (const_int 1)))
11956 ; which are generated by the branch logic.
11957 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
11959 (define_insn "*cceq_ior_compare"
11960 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
11961 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
11962 [(match_operator:SI 2
11963 "branch_positive_comparison_operator"
11964 [(match_operand 3
11965 "cc_reg_operand" "y,y")
11966 (const_int 0)])
11967 (match_operator:SI 4
11968 "branch_positive_comparison_operator"
11969 [(match_operand 5
11970 "cc_reg_operand" "0,y")
11971 (const_int 0)])])
11972 (const_int 1)))]
11973 ""
11974 "cr%q1 %E0,%j2,%j4"
11975 [(set_attr "type" "cr_logical,delayed_cr")])
11977 ; Why is the constant -1 here, but 1 in the previous pattern?
11978 ; Because ~1 has all but the low bit set.
11979 (define_insn ""
11980 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
11981 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
11982 [(not:SI (match_operator:SI 2
11983 "branch_positive_comparison_operator"
11984 [(match_operand 3
11985 "cc_reg_operand" "y,y")
11986 (const_int 0)]))
11987 (match_operator:SI 4
11988 "branch_positive_comparison_operator"
11989 [(match_operand 5
11990 "cc_reg_operand" "0,y")
11991 (const_int 0)])])
11992 (const_int -1)))]
11993 ""
11994 "cr%q1 %E0,%j2,%j4"
11995 [(set_attr "type" "cr_logical,delayed_cr")])
11997 (define_insn "*cceq_rev_compare"
11998 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
11999 (compare:CCEQ (match_operator:SI 1
12000 "branch_positive_comparison_operator"
12001 [(match_operand 2
12002 "cc_reg_operand" "0,y")
12003 (const_int 0)])
12004 (const_int 0)))]
12005 ""
12006 "crnot %E0,%j1"
12007 [(set_attr "type" "cr_logical,delayed_cr")])
12009 ;; If we are comparing the result of two comparisons, this can be done
12010 ;; using creqv or crxor.
12012 (define_insn_and_split ""
12013 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12014 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12015 [(match_operand 2 "cc_reg_operand" "y")
12016 (const_int 0)])
12017 (match_operator 3 "branch_comparison_operator"
12018 [(match_operand 4 "cc_reg_operand" "y")
12019 (const_int 0)])))]
12020 ""
12021 "#"
12022 ""
12023 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12024 (match_dup 5)))]
12025 "
12026 {
12027 int positive_1, positive_2;
12029 positive_1 = branch_positive_comparison_operator (operands[1],
12030 GET_MODE (operands[1]));
12031 positive_2 = branch_positive_comparison_operator (operands[3],
12032 GET_MODE (operands[3]));
12034 if (! positive_1)
12035 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
12036 GET_CODE (operands[1])),
12037 SImode,
12038 operands[2], const0_rtx);
12039 else if (GET_MODE (operands[1]) != SImode)
12040 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
12041 operands[2], const0_rtx);
12043 if (! positive_2)
12044 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
12045 GET_CODE (operands[3])),
12046 SImode,
12047 operands[4], const0_rtx);
12048 else if (GET_MODE (operands[3]) != SImode)
12049 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
12050 operands[4], const0_rtx);
12052 if (positive_1 == positive_2)
12053 {
12054 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12055 operands[5] = constm1_rtx;
12056 }
12057 else
12058 {
12059 operands[5] = const1_rtx;
12060 }
12061 }")
12063 ;; Unconditional branch and return.
12065 (define_insn "jump"
12066 [(set (pc)
12067 (label_ref (match_operand 0 "" "")))]
12068 ""
12069 "b %l0"
12070 [(set_attr "type" "branch")])
12072 (define_insn "<return_str>return"
12073 [(any_return)]
12074 "<return_pred>"
12075 "blr"
12076 [(set_attr "type" "jmpreg")])
12078 (define_expand "indirect_jump"
12079 [(set (pc) (match_operand 0 "register_operand" ""))])
12081 (define_insn "*indirect_jump<mode>"
12082 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
12083 ""
12084 "@
12085 bctr
12086 blr"
12087 [(set_attr "type" "jmpreg")])
12089 ;; Table jump for switch statements:
12090 (define_expand "tablejump"
12091 [(use (match_operand 0 "" ""))
12092 (use (label_ref (match_operand 1 "" "")))]
12093 ""
12094 "
12095 {
12096 if (TARGET_32BIT)
12097 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12098 else
12099 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12100 DONE;
12101 }")
12103 (define_expand "tablejumpsi"
12104 [(set (match_dup 3)
12105 (plus:SI (match_operand:SI 0 "" "")
12106 (match_dup 2)))
12107 (parallel [(set (pc) (match_dup 3))
12108 (use (label_ref (match_operand 1 "" "")))])]
12109 "TARGET_32BIT"
12110 "
12111 { operands[0] = force_reg (SImode, operands[0]);
12112 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12113 operands[3] = gen_reg_rtx (SImode);
12114 }")
12116 (define_expand "tablejumpdi"
12117 [(set (match_dup 4)
12118 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
12119 (set (match_dup 3)
12120 (plus:DI (match_dup 4)
12121 (match_dup 2)))
12122 (parallel [(set (pc) (match_dup 3))
12123 (use (label_ref (match_operand 1 "" "")))])]
12124 "TARGET_64BIT"
12125 "
12126 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
12127 operands[3] = gen_reg_rtx (DImode);
12128 operands[4] = gen_reg_rtx (DImode);
12129 }")
12131 (define_insn "*tablejump<mode>_internal1"
12132 [(set (pc)
12133 (match_operand:P 0 "register_operand" "c,*l"))
12134 (use (label_ref (match_operand 1 "" "")))]
12135 ""
12136 "@
12137 bctr
12138 blr"
12139 [(set_attr "type" "jmpreg")])
12141 (define_insn "nop"
12142 [(unspec [(const_int 0)] UNSPEC_NOP)]
12143 ""
12144 "nop")
12146 (define_insn "group_ending_nop"
12147 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
12148 ""
12149 "*
12150 {
12151 if (rs6000_cpu_attr == CPU_POWER6)
12152 return \"ori 1,1,0\";
12153 return \"ori 2,2,0\";
12154 }")
12155 \f
12156 ;; Define the subtract-one-and-jump insns, starting with the template
12157 ;; so loop.c knows what to generate.
12159 (define_expand "doloop_end"
12160 [(use (match_operand 0 "" "")) ; loop pseudo
12161 (use (match_operand 1 "" ""))] ; label
12162 ""
12163 "
12164 {
12165 if (TARGET_64BIT)
12166 {
12167 if (GET_MODE (operands[0]) != DImode)
12168 FAIL;
12169 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
12170 }
12171 else
12172 {
12173 if (GET_MODE (operands[0]) != SImode)
12174 FAIL;
12175 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
12176 }
12177 DONE;
12178 }")
12180 (define_expand "ctr<mode>"
12181 [(parallel [(set (pc)
12182 (if_then_else (ne (match_operand:P 0 "register_operand" "")
12183 (const_int 1))
12184 (label_ref (match_operand 1 "" ""))
12185 (pc)))
12186 (set (match_dup 0)
12187 (plus:P (match_dup 0)
12188 (const_int -1)))
12189 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12190 (clobber (match_scratch:CC 2 ""))
12191 (clobber (match_scratch:P 3 ""))])]
12192 ""
12193 "")
12195 ;; We need to be able to do this for any operand, including MEM, or we
12196 ;; will cause reload to blow up since we don't allow output reloads on
12197 ;; JUMP_INSNs.
12198 ;; For the length attribute to be calculated correctly, the
12199 ;; label MUST be operand 0.
12200 ;; The UNSPEC is present to prevent combine creating this pattern.
12202 (define_insn "*ctr<mode>_internal1"
12203 [(set (pc)
12204 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12205 (const_int 1))
12206 (label_ref (match_operand 0 "" ""))
12207 (pc)))
12208 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
12209 (plus:P (match_dup 1)
12210 (const_int -1)))
12211 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12212 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12213 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12214 ""
12215 "*
12216 {
12217 if (which_alternative != 0)
12218 return \"#\";
12219 else if (get_attr_length (insn) == 4)
12220 return \"bdnz %l0\";
12221 else
12222 return \"bdz $+8\;b %l0\";
12223 }"
12224 [(set_attr "type" "branch")
12225 (set_attr "length" "*,16,20,20")])
12227 (define_insn "*ctr<mode>_internal2"
12228 [(set (pc)
12229 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12230 (const_int 1))
12231 (pc)
12232 (label_ref (match_operand 0 "" ""))))
12233 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
12234 (plus:P (match_dup 1)
12235 (const_int -1)))
12236 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12237 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12238 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12239 ""
12240 "*
12241 {
12242 if (which_alternative != 0)
12243 return \"#\";
12244 else if (get_attr_length (insn) == 4)
12245 return \"bdz %l0\";
12246 else
12247 return \"bdnz $+8\;b %l0\";
12248 }"
12249 [(set_attr "type" "branch")
12250 (set_attr "length" "*,16,20,20")])
12252 ;; Similar but use EQ
12254 (define_insn "*ctr<mode>_internal5"
12255 [(set (pc)
12256 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12257 (const_int 1))
12258 (label_ref (match_operand 0 "" ""))
12259 (pc)))
12260 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
12261 (plus:P (match_dup 1)
12262 (const_int -1)))
12263 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12264 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12265 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12266 ""
12267 "*
12268 {
12269 if (which_alternative != 0)
12270 return \"#\";
12271 else if (get_attr_length (insn) == 4)
12272 return \"bdz %l0\";
12273 else
12274 return \"bdnz $+8\;b %l0\";
12275 }"
12276 [(set_attr "type" "branch")
12277 (set_attr "length" "*,16,20,20")])
12279 (define_insn "*ctr<mode>_internal6"
12280 [(set (pc)
12281 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*b,*b,*b")
12282 (const_int 1))
12283 (pc)
12284 (label_ref (match_operand 0 "" ""))))
12285 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*d*wi*c*l")
12286 (plus:P (match_dup 1)
12287 (const_int -1)))
12288 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12289 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
12290 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
12291 ""
12292 "*
12293 {
12294 if (which_alternative != 0)
12295 return \"#\";
12296 else if (get_attr_length (insn) == 4)
12297 return \"bdnz %l0\";
12298 else
12299 return \"bdz $+8\;b %l0\";
12300 }"
12301 [(set_attr "type" "branch")
12302 (set_attr "length" "*,16,20,20")])
12304 ;; Now the splitters if we could not allocate the CTR register
12306 (define_split
12307 [(set (pc)
12308 (if_then_else (match_operator 2 "comparison_operator"
12309 [(match_operand:P 1 "gpc_reg_operand" "")
12310 (const_int 1)])
12311 (match_operand 5 "" "")
12312 (match_operand 6 "" "")))
12313 (set (match_operand:P 0 "int_reg_operand" "")
12314 (plus:P (match_dup 1) (const_int -1)))
12315 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12316 (clobber (match_scratch:CC 3 ""))
12317 (clobber (match_scratch:P 4 ""))]
12318 "reload_completed"
12319 [(set (match_dup 3)
12320 (compare:CC (match_dup 1)
12321 (const_int 1)))
12322 (set (match_dup 0)
12323 (plus:P (match_dup 1)
12324 (const_int -1)))
12325 (set (pc) (if_then_else (match_dup 7)
12326 (match_dup 5)
12327 (match_dup 6)))]
12328 "
12329 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
12330 operands[3], const0_rtx); }")
12332 (define_split
12333 [(set (pc)
12334 (if_then_else (match_operator 2 "comparison_operator"
12335 [(match_operand:P 1 "gpc_reg_operand" "")
12336 (const_int 1)])
12337 (match_operand 5 "" "")
12338 (match_operand 6 "" "")))
12339 (set (match_operand:P 0 "nonimmediate_operand" "")
12340 (plus:P (match_dup 1) (const_int -1)))
12341 (unspec [(const_int 0)] UNSPEC_DOLOOP)
12342 (clobber (match_scratch:CC 3 ""))
12343 (clobber (match_scratch:P 4 ""))]
12344 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
12345 [(set (match_dup 3)
12346 (compare:CC (match_dup 1)
12347 (const_int 1)))
12348 (set (match_dup 4)
12349 (plus:P (match_dup 1)
12350 (const_int -1)))
12351 (set (match_dup 0)
12352 (match_dup 4))
12353 (set (pc) (if_then_else (match_dup 7)
12354 (match_dup 5)
12355 (match_dup 6)))]
12356 "
12357 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
12358 operands[3], const0_rtx); }")
12359 \f
12360 (define_insn "trap"
12361 [(trap_if (const_int 1) (const_int 0))]
12362 ""
12363 "trap"
12364 [(set_attr "type" "trap")])
12366 (define_expand "ctrap<mode>4"
12367 [(trap_if (match_operator 0 "ordered_comparison_operator"
12368 [(match_operand:GPR 1 "register_operand")
12369 (match_operand:GPR 2 "reg_or_short_operand")])
12370 (match_operand 3 "zero_constant" ""))]
12371 ""
12372 "")
12374 (define_insn ""
12375 [(trap_if (match_operator 0 "ordered_comparison_operator"
12376 [(match_operand:GPR 1 "register_operand" "r")
12377 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
12378 (const_int 0))]
12379 ""
12380 "t<wd>%V0%I2 %1,%2"
12381 [(set_attr "type" "trap")])
12382 \f
12383 ;; Insns related to generating the function prologue and epilogue.
12385 (define_expand "prologue"
12386 [(use (const_int 0))]
12387 ""
12388 {
12389 rs6000_emit_prologue ();
12390 if (!TARGET_SCHED_PROLOG)
12391 emit_insn (gen_blockage ());
12392 DONE;
12393 })
12395 (define_insn "*movesi_from_cr_one"
12396 [(match_parallel 0 "mfcr_operation"
12397 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
12398 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
12399 (match_operand 3 "immediate_operand" "n")]
12400 UNSPEC_MOVESI_FROM_CR))])]
12401 "TARGET_MFCRF"
12402 "*
12403 {
12404 int mask = 0;
12405 int i;
12406 for (i = 0; i < XVECLEN (operands[0], 0); i++)
12407 {
12408 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
12409 operands[4] = GEN_INT (mask);
12410 output_asm_insn (\"mfcr %1,%4\", operands);
12411 }
12412 return \"\";
12413 }"
12414 [(set_attr "type" "mfcrf")])
12416 (define_insn "movesi_from_cr"
12417 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12418 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
12419 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
12420 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
12421 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
12422 UNSPEC_MOVESI_FROM_CR))]
12423 ""
12424 "mfcr %0"
12425 [(set_attr "type" "mfcr")])
12427 (define_insn "*crsave"
12428 [(match_parallel 0 "crsave_operation"
12429 [(set (match_operand:SI 1 "memory_operand" "=m")
12430 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
12431 ""
12432 "stw %2,%1"
12433 [(set_attr "type" "store")])
12435 (define_insn "*stmw"
12436 [(match_parallel 0 "stmw_operation"
12437 [(set (match_operand:SI 1 "memory_operand" "=m")
12438 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
12439 "TARGET_MULTIPLE"
12440 "stmw %2,%1"
12441 [(set_attr "type" "store")
12442 (set_attr "update" "yes")
12443 (set_attr "indexed" "yes")])
12445 ; The following comment applies to:
12446 ; save_gpregs_*
12447 ; save_fpregs_*
12448 ; restore_gpregs*
12449 ; return_and_restore_gpregs*
12450 ; return_and_restore_fpregs*
12451 ; return_and_restore_fpregs_aix*
12452 ;
12453 ; The out-of-line save / restore functions expects one input argument.
12454 ; Since those are not standard call_insn's, we must avoid using
12455 ; MATCH_OPERAND for that argument. That way the register rename
12456 ; optimization will not try to rename this register.
12457 ; Each pattern is repeated for each possible register number used in
12458 ; various ABIs (r11, r1, and for some functions r12)
12460 (define_insn "*save_gpregs_<mode>_r11"
12461 [(match_parallel 0 "any_parallel_operand"
12462 [(clobber (reg:P 65))
12463 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12464 (use (reg:P 11))
12465 (set (match_operand:P 2 "memory_operand" "=m")
12466 (match_operand:P 3 "gpc_reg_operand" "r"))])]
12467 ""
12468 "bl %1"
12469 [(set_attr "type" "branch")
12470 (set_attr "length" "4")])
12472 (define_insn "*save_gpregs_<mode>_r12"
12473 [(match_parallel 0 "any_parallel_operand"
12474 [(clobber (reg:P 65))
12475 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12476 (use (reg:P 12))
12477 (set (match_operand:P 2 "memory_operand" "=m")
12478 (match_operand:P 3 "gpc_reg_operand" "r"))])]
12479 ""
12480 "bl %1"
12481 [(set_attr "type" "branch")
12482 (set_attr "length" "4")])
12484 (define_insn "*save_gpregs_<mode>_r1"
12485 [(match_parallel 0 "any_parallel_operand"
12486 [(clobber (reg:P 65))
12487 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12488 (use (reg:P 1))
12489 (set (match_operand:P 2 "memory_operand" "=m")
12490 (match_operand:P 3 "gpc_reg_operand" "r"))])]
12491 ""
12492 "bl %1"
12493 [(set_attr "type" "branch")
12494 (set_attr "length" "4")])
12496 (define_insn "*save_fpregs_<mode>_r11"
12497 [(match_parallel 0 "any_parallel_operand"
12498 [(clobber (reg:P 65))
12499 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12500 (use (reg:P 11))
12501 (set (match_operand:DF 2 "memory_operand" "=m")
12502 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
12503 ""
12504 "bl %1"
12505 [(set_attr "type" "branch")
12506 (set_attr "length" "4")])
12508 (define_insn "*save_fpregs_<mode>_r12"
12509 [(match_parallel 0 "any_parallel_operand"
12510 [(clobber (reg:P 65))
12511 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12512 (use (reg:P 12))
12513 (set (match_operand:DF 2 "memory_operand" "=m")
12514 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
12515 ""
12516 "bl %1"
12517 [(set_attr "type" "branch")
12518 (set_attr "length" "4")])
12520 (define_insn "*save_fpregs_<mode>_r1"
12521 [(match_parallel 0 "any_parallel_operand"
12522 [(clobber (reg:P 65))
12523 (use (match_operand:P 1 "symbol_ref_operand" "s"))
12524 (use (reg:P 1))
12525 (set (match_operand:DF 2 "memory_operand" "=m")
12526 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
12527 ""
12528 "bl %1"
12529 [(set_attr "type" "branch")
12530 (set_attr "length" "4")])
12532 ; This is to explain that changes to the stack pointer should
12533 ; not be moved over loads from or stores to stack memory.
12534 (define_insn "stack_tie"
12535 [(match_parallel 0 "tie_operand"
12536 [(set (mem:BLK (reg 1)) (const_int 0))])]
12537 ""
12538 ""
12539 [(set_attr "length" "0")])
12541 (define_expand "epilogue"
12542 [(use (const_int 0))]
12543 ""
12544 {
12545 if (!TARGET_SCHED_PROLOG)
12546 emit_insn (gen_blockage ());
12547 rs6000_emit_epilogue (FALSE);
12548 DONE;
12549 })
12551 ; On some processors, doing the mtcrf one CC register at a time is
12552 ; faster (like on the 604e). On others, doing them all at once is
12553 ; faster; for instance, on the 601 and 750.
12555 (define_expand "movsi_to_cr_one"
12556 [(set (match_operand:CC 0 "cc_reg_operand" "")
12557 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
12558 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
12559 ""
12560 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
12562 (define_insn "*movsi_to_cr"
12563 [(match_parallel 0 "mtcrf_operation"
12564 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
12565 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
12566 (match_operand 3 "immediate_operand" "n")]
12567 UNSPEC_MOVESI_TO_CR))])]
12568 ""
12569 "*
12570 {
12571 int mask = 0;
12572 int i;
12573 for (i = 0; i < XVECLEN (operands[0], 0); i++)
12574 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
12575 operands[4] = GEN_INT (mask);
12576 return \"mtcrf %4,%2\";
12577 }"
12578 [(set_attr "type" "mtcr")])
12580 (define_insn "*mtcrfsi"
12581 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12582 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
12583 (match_operand 2 "immediate_operand" "n")]
12584 UNSPEC_MOVESI_TO_CR))]
12585 "GET_CODE (operands[0]) == REG
12586 && CR_REGNO_P (REGNO (operands[0]))
12587 && GET_CODE (operands[2]) == CONST_INT
12588 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
12589 "mtcrf %R0,%1"
12590 [(set_attr "type" "mtcr")])
12592 ; The load-multiple instructions have similar properties.
12593 ; Note that "load_multiple" is a name known to the machine-independent
12594 ; code that actually corresponds to the PowerPC load-string.
12596 (define_insn "*lmw"
12597 [(match_parallel 0 "lmw_operation"
12598 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
12599 (match_operand:SI 2 "memory_operand" "m"))])]
12600 "TARGET_MULTIPLE"
12601 "lmw %1,%2"
12602 [(set_attr "type" "load")
12603 (set_attr "update" "yes")
12604 (set_attr "indexed" "yes")
12605 (set_attr "cell_micro" "always")])
12607 (define_insn "*return_internal_<mode>"
12608 [(simple_return)
12609 (use (match_operand:P 0 "register_operand" "lc"))]
12610 ""
12611 "b%T0"
12612 [(set_attr "type" "jmpreg")])
12614 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
12615 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
12617 ; The following comment applies to:
12618 ; save_gpregs_*
12619 ; save_fpregs_*
12620 ; restore_gpregs*
12621 ; return_and_restore_gpregs*
12622 ; return_and_restore_fpregs*
12623 ; return_and_restore_fpregs_aix*
12624 ;
12625 ; The out-of-line save / restore functions expects one input argument.
12626 ; Since those are not standard call_insn's, we must avoid using
12627 ; MATCH_OPERAND for that argument. That way the register rename
12628 ; optimization will not try to rename this register.
12629 ; Each pattern is repeated for each possible register number used in
12630 ; various ABIs (r11, r1, and for some functions r12)
12632 (define_insn "*restore_gpregs_<mode>_r11"
12633 [(match_parallel 0 "any_parallel_operand"
12634 [(clobber (match_operand:P 1 "register_operand" "=l"))
12635 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12636 (use (reg:P 11))
12637 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12638 (match_operand:P 4 "memory_operand" "m"))])]
12639 ""
12640 "bl %2"
12641 [(set_attr "type" "branch")
12642 (set_attr "length" "4")])
12644 (define_insn "*restore_gpregs_<mode>_r12"
12645 [(match_parallel 0 "any_parallel_operand"
12646 [(clobber (match_operand:P 1 "register_operand" "=l"))
12647 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12648 (use (reg:P 12))
12649 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12650 (match_operand:P 4 "memory_operand" "m"))])]
12651 ""
12652 "bl %2"
12653 [(set_attr "type" "branch")
12654 (set_attr "length" "4")])
12656 (define_insn "*restore_gpregs_<mode>_r1"
12657 [(match_parallel 0 "any_parallel_operand"
12658 [(clobber (match_operand:P 1 "register_operand" "=l"))
12659 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12660 (use (reg:P 1))
12661 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12662 (match_operand:P 4 "memory_operand" "m"))])]
12663 ""
12664 "bl %2"
12665 [(set_attr "type" "branch")
12666 (set_attr "length" "4")])
12668 (define_insn "*return_and_restore_gpregs_<mode>_r11"
12669 [(match_parallel 0 "any_parallel_operand"
12670 [(return)
12671 (clobber (match_operand:P 1 "register_operand" "=l"))
12672 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12673 (use (reg:P 11))
12674 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12675 (match_operand:P 4 "memory_operand" "m"))])]
12676 ""
12677 "b %2"
12678 [(set_attr "type" "branch")
12679 (set_attr "length" "4")])
12681 (define_insn "*return_and_restore_gpregs_<mode>_r12"
12682 [(match_parallel 0 "any_parallel_operand"
12683 [(return)
12684 (clobber (match_operand:P 1 "register_operand" "=l"))
12685 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12686 (use (reg:P 12))
12687 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12688 (match_operand:P 4 "memory_operand" "m"))])]
12689 ""
12690 "b %2"
12691 [(set_attr "type" "branch")
12692 (set_attr "length" "4")])
12694 (define_insn "*return_and_restore_gpregs_<mode>_r1"
12695 [(match_parallel 0 "any_parallel_operand"
12696 [(return)
12697 (clobber (match_operand:P 1 "register_operand" "=l"))
12698 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12699 (use (reg:P 1))
12700 (set (match_operand:P 3 "gpc_reg_operand" "=r")
12701 (match_operand:P 4 "memory_operand" "m"))])]
12702 ""
12703 "b %2"
12704 [(set_attr "type" "branch")
12705 (set_attr "length" "4")])
12707 (define_insn "*return_and_restore_fpregs_<mode>_r11"
12708 [(match_parallel 0 "any_parallel_operand"
12709 [(return)
12710 (clobber (match_operand:P 1 "register_operand" "=l"))
12711 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12712 (use (reg:P 11))
12713 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
12714 (match_operand:DF 4 "memory_operand" "m"))])]
12715 ""
12716 "b %2"
12717 [(set_attr "type" "branch")
12718 (set_attr "length" "4")])
12720 (define_insn "*return_and_restore_fpregs_<mode>_r12"
12721 [(match_parallel 0 "any_parallel_operand"
12722 [(return)
12723 (clobber (match_operand:P 1 "register_operand" "=l"))
12724 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12725 (use (reg:P 12))
12726 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
12727 (match_operand:DF 4 "memory_operand" "m"))])]
12728 ""
12729 "b %2"
12730 [(set_attr "type" "branch")
12731 (set_attr "length" "4")])
12733 (define_insn "*return_and_restore_fpregs_<mode>_r1"
12734 [(match_parallel 0 "any_parallel_operand"
12735 [(return)
12736 (clobber (match_operand:P 1 "register_operand" "=l"))
12737 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12738 (use (reg:P 1))
12739 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
12740 (match_operand:DF 4 "memory_operand" "m"))])]
12741 ""
12742 "b %2"
12743 [(set_attr "type" "branch")
12744 (set_attr "length" "4")])
12746 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
12747 [(match_parallel 0 "any_parallel_operand"
12748 [(return)
12749 (use (match_operand:P 1 "register_operand" "l"))
12750 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12751 (use (reg:P 11))
12752 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
12753 (match_operand:DF 4 "memory_operand" "m"))])]
12754 ""
12755 "b %2"
12756 [(set_attr "type" "branch")
12757 (set_attr "length" "4")])
12759 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
12760 [(match_parallel 0 "any_parallel_operand"
12761 [(return)
12762 (use (match_operand:P 1 "register_operand" "l"))
12763 (use (match_operand:P 2 "symbol_ref_operand" "s"))
12764 (use (reg:P 1))
12765 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
12766 (match_operand:DF 4 "memory_operand" "m"))])]
12767 ""
12768 "b %2"
12769 [(set_attr "type" "branch")
12770 (set_attr "length" "4")])
12772 ; This is used in compiling the unwind routines.
12773 (define_expand "eh_return"
12774 [(use (match_operand 0 "general_operand" ""))]
12775 ""
12776 "
12777 {
12778 if (TARGET_32BIT)
12779 emit_insn (gen_eh_set_lr_si (operands[0]));
12780 else
12781 emit_insn (gen_eh_set_lr_di (operands[0]));
12782 DONE;
12783 }")
12785 ; We can't expand this before we know where the link register is stored.
12786 (define_insn "eh_set_lr_<mode>"
12787 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
12788 UNSPECV_EH_RR)
12789 (clobber (match_scratch:P 1 "=&b"))]
12790 ""
12791 "#")
12793 (define_split
12794 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
12795 (clobber (match_scratch 1 ""))]
12796 "reload_completed"
12797 [(const_int 0)]
12798 "
12799 {
12800 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
12801 DONE;
12802 }")
12804 (define_insn "prefetch"
12805 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
12806 (match_operand:SI 1 "const_int_operand" "n")
12807 (match_operand:SI 2 "const_int_operand" "n"))]
12808 ""
12809 "*
12810 {
12811 if (GET_CODE (operands[0]) == REG)
12812 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
12813 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
12814 }"
12815 [(set_attr "type" "load")])
12816 \f
12817 ;; Handle -fsplit-stack.
12819 (define_expand "split_stack_prologue"
12820 [(const_int 0)]
12821 ""
12822 {
12823 rs6000_expand_split_stack_prologue ();
12824 DONE;
12825 })
12827 (define_expand "load_split_stack_limit"
12828 [(set (match_operand 0)
12829 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))]
12830 ""
12831 {
12832 emit_insn (gen_rtx_SET (operands[0],
12833 gen_rtx_UNSPEC (Pmode,
12834 gen_rtvec (1, const0_rtx),
12835 UNSPEC_STACK_CHECK)));
12836 DONE;
12837 })
12839 (define_insn "load_split_stack_limit_di"
12840 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12841 (unspec:DI [(const_int 0)] UNSPEC_STACK_CHECK))]
12842 "TARGET_64BIT"
12843 "ld %0,-0x7040(13)"
12844 [(set_attr "type" "load")
12845 (set_attr "update" "no")
12846 (set_attr "indexed" "no")])
12848 (define_insn "load_split_stack_limit_si"
12849 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12850 (unspec:SI [(const_int 0)] UNSPEC_STACK_CHECK))]
12851 "!TARGET_64BIT"
12852 "lwz %0,-0x7020(2)"
12853 [(set_attr "type" "load")
12854 (set_attr "update" "no")
12855 (set_attr "indexed" "no")])
12857 ;; A return instruction which the middle-end doesn't see.
12858 ;; Use r0 to stop regrename twiddling with lr restore insns emitted
12859 ;; after the call to __morestack.
12860 (define_insn "split_stack_return"
12861 [(unspec_volatile [(use (reg:SI 0))] UNSPECV_SPLIT_STACK_RETURN)]
12862 ""
12863 "blr"
12864 [(set_attr "type" "jmpreg")])
12866 ;; If there are operand 0 bytes available on the stack, jump to
12867 ;; operand 1.
12868 (define_expand "split_stack_space_check"
12869 [(set (match_dup 2)
12870 (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
12871 (set (match_dup 3)
12872 (minus (reg STACK_POINTER_REGNUM)
12873 (match_operand 0)))
12874 (set (match_dup 4) (compare:CCUNS (match_dup 3) (match_dup 2)))
12875 (set (pc) (if_then_else
12876 (geu (match_dup 4) (const_int 0))
12877 (label_ref (match_operand 1))
12878 (pc)))]
12879 ""
12880 {
12881 rs6000_split_stack_space_check (operands[0], operands[1]);
12882 DONE;
12883 })
12884 \f
12885 (define_insn "bpermd_<mode>"
12886 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12887 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
12888 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
12889 "TARGET_POPCNTD"
12890 "bpermd %0,%1,%2"
12891 [(set_attr "type" "popcnt")])
12893 \f
12894 ;; Builtin fma support. Handle
12895 ;; Note that the conditions for expansion are in the FMA_F iterator.
12897 (define_expand "fma<mode>4"
12898 [(set (match_operand:FMA_F 0 "register_operand" "")
12899 (fma:FMA_F
12900 (match_operand:FMA_F 1 "register_operand" "")
12901 (match_operand:FMA_F 2 "register_operand" "")
12902 (match_operand:FMA_F 3 "register_operand" "")))]
12903 ""
12904 "")
12906 (define_insn "*fma<mode>4_fpr"
12907 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
12908 (fma:SFDF
12909 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>")
12910 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
12911 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))]
12912 "TARGET_<MODE>_FPR"
12913 "@
12914 fmadd<Ftrad> %0,%1,%2,%3
12915 xsmadda<Fvsx> %x0,%x1,%x2
12916 xsmaddm<Fvsx> %x0,%x1,%x3"
12917 [(set_attr "type" "fp")
12918 (set_attr "fp_type" "fp_maddsub_<Fs>")])
12920 ; Altivec only has fma and nfms.
12921 (define_expand "fms<mode>4"
12922 [(set (match_operand:FMA_F 0 "register_operand" "")
12923 (fma:FMA_F
12924 (match_operand:FMA_F 1 "register_operand" "")
12925 (match_operand:FMA_F 2 "register_operand" "")
12926 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
12927 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
12928 "")
12930 (define_insn "*fms<mode>4_fpr"
12931 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
12932 (fma:SFDF
12933 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
12934 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
12935 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
12936 "TARGET_<MODE>_FPR"
12937 "@
12938 fmsub<Ftrad> %0,%1,%2,%3
12939 xsmsuba<Fvsx> %x0,%x1,%x2
12940 xsmsubm<Fvsx> %x0,%x1,%x3"
12941 [(set_attr "type" "fp")
12942 (set_attr "fp_type" "fp_maddsub_<Fs>")])
12944 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
12945 (define_expand "fnma<mode>4"
12946 [(set (match_operand:FMA_F 0 "register_operand" "")
12947 (neg:FMA_F
12948 (fma:FMA_F
12949 (match_operand:FMA_F 1 "register_operand" "")
12950 (match_operand:FMA_F 2 "register_operand" "")
12951 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
12952 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
12953 "")
12955 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
12956 (define_expand "fnms<mode>4"
12957 [(set (match_operand:FMA_F 0 "register_operand" "")
12958 (neg:FMA_F
12959 (fma:FMA_F
12960 (match_operand:FMA_F 1 "register_operand" "")
12961 (match_operand:FMA_F 2 "register_operand" "")
12962 (match_operand:FMA_F 3 "register_operand" ""))))]
12963 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
12964 "")
12966 ; Not an official optab name, but used from builtins.
12967 (define_expand "nfma<mode>4"
12968 [(set (match_operand:FMA_F 0 "register_operand" "")
12969 (neg:FMA_F
12970 (fma:FMA_F
12971 (match_operand:FMA_F 1 "register_operand" "")
12972 (match_operand:FMA_F 2 "register_operand" "")
12973 (match_operand:FMA_F 3 "register_operand" ""))))]
12974 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
12975 "")
12977 (define_insn "*nfma<mode>4_fpr"
12978 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
12979 (neg:SFDF
12980 (fma:SFDF
12981 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
12982 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
12983 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
12984 "TARGET_<MODE>_FPR"
12985 "@
12986 fnmadd<Ftrad> %0,%1,%2,%3
12987 xsnmadda<Fvsx> %x0,%x1,%x2
12988 xsnmaddm<Fvsx> %x0,%x1,%x3"
12989 [(set_attr "type" "fp")
12990 (set_attr "fp_type" "fp_maddsub_<Fs>")])
12992 ; Not an official optab name, but used from builtins.
12993 (define_expand "nfms<mode>4"
12994 [(set (match_operand:FMA_F 0 "register_operand" "")
12995 (neg:FMA_F
12996 (fma:FMA_F
12997 (match_operand:FMA_F 1 "register_operand" "")
12998 (match_operand:FMA_F 2 "register_operand" "")
12999 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
13000 ""
13001 "")
13003 (define_insn "*nfmssf4_fpr"
13004 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
13005 (neg:SFDF
13006 (fma:SFDF
13007 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
13008 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
13009 (neg:SFDF
13010 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))]
13011 "TARGET_<MODE>_FPR"
13012 "@
13013 fnmsub<Ftrad> %0,%1,%2,%3
13014 xsnmsuba<Fvsx> %x0,%x1,%x2
13015 xsnmsubm<Fvsx> %x0,%x1,%x3"
13016 [(set_attr "type" "fp")
13017 (set_attr "fp_type" "fp_maddsub_<Fs>")])
13019 \f
13020 (define_expand "rs6000_get_timebase"
13021 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
13022 ""
13023 {
13024 if (TARGET_POWERPC64)
13025 emit_insn (gen_rs6000_mftb_di (operands[0]));
13026 else
13027 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
13028 DONE;
13029 })
13031 (define_insn "rs6000_get_timebase_ppc32"
13032 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13033 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
13034 (clobber (match_scratch:SI 1 "=r"))
13035 (clobber (match_scratch:CC 2 "=y"))]
13036 "!TARGET_POWERPC64"
13037 {
13038 if (WORDS_BIG_ENDIAN)
13039 if (TARGET_MFCRF)
13040 {
13041 return "mfspr %0,269\;"
13042 "mfspr %L0,268\;"
13043 "mfspr %1,269\;"
13044 "cmpw %2,%0,%1\;"
13045 "bne- %2,$-16";
13046 }
13047 else
13048 {
13049 return "mftbu %0\;"
13050 "mftb %L0\;"
13051 "mftbu %1\;"
13052 "cmpw %2,%0,%1\;"
13053 "bne- %2,$-16";
13054 }
13055 else
13056 if (TARGET_MFCRF)
13057 {
13058 return "mfspr %L0,269\;"
13059 "mfspr %0,268\;"
13060 "mfspr %1,269\;"
13061 "cmpw %2,%L0,%1\;"
13062 "bne- %2,$-16";
13063 }
13064 else
13065 {
13066 return "mftbu %L0\;"
13067 "mftb %0\;"
13068 "mftbu %1\;"
13069 "cmpw %2,%L0,%1\;"
13070 "bne- %2,$-16";
13071 }
13072 }
13073 [(set_attr "length" "20")])
13075 (define_insn "rs6000_mftb_<mode>"
13076 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13077 (unspec_volatile:GPR [(const_int 0)] UNSPECV_MFTB))]
13078 ""
13079 {
13080 if (TARGET_MFCRF)
13081 return "mfspr %0,268";
13082 else
13083 return "mftb %0";
13084 })
13086 \f
13087 (define_insn "rs6000_mffs"
13088 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
13089 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
13090 "TARGET_HARD_FLOAT && TARGET_FPRS"
13091 "mffs %0")
13093 (define_insn "rs6000_mtfsf"
13094 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
13095 (match_operand:DF 1 "gpc_reg_operand" "d")]
13096 UNSPECV_MTFSF)]
13097 "TARGET_HARD_FLOAT && TARGET_FPRS"
13098 "mtfsf %0,%1")
13100 \f
13101 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
13102 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
13103 ;; register that is being loaded. The fused ops must be physically adjacent.
13105 ;; There are two parts to addis fusion. The support for fused TOCs occur
13106 ;; before register allocation, and is meant to reduce the lifetime for the
13107 ;; tempoary register that holds the ADDIS result. On Power8 GPR loads, we try
13108 ;; to use the register that is being load. The peephole2 then gathers any
13109 ;; other fused possibilities that it can find after register allocation. If
13110 ;; power9 fusion is selected, we also fuse floating point loads/stores.
13112 ;; Fused TOC support: Replace simple GPR loads with a fused form. This is done
13113 ;; before register allocation, so that we can avoid allocating a temporary base
13114 ;; register that won't be used, and that we try to load into base registers,
13115 ;; and not register 0. If we can't get a fused GPR load, generate a P9 fusion
13116 ;; (addis followed by load) even on power8.
13118 (define_split
13119 [(set (match_operand:INT1 0 "toc_fusion_or_p9_reg_operand" "")
13120 (match_operand:INT1 1 "toc_fusion_mem_raw" ""))]
13121 "TARGET_TOC_FUSION_INT && can_create_pseudo_p ()"
13122 [(parallel [(set (match_dup 0) (match_dup 2))
13123 (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
13124 (use (match_dup 3))
13125 (clobber (scratch:DI))])]
13126 {
13127 operands[2] = fusion_wrap_memory_address (operands[1]);
13128 operands[3] = gen_rtx_REG (Pmode, TOC_REGISTER);
13129 })
13131 (define_insn "*toc_fusionload_<mode>"
13132 [(set (match_operand:QHSI 0 "int_reg_operand" "=&b,??r")
13133 (match_operand:QHSI 1 "toc_fusion_mem_wrapped" "wG,wG"))
13134 (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
13135 (use (match_operand:DI 2 "base_reg_operand" "r,r"))
13136 (clobber (match_scratch:DI 3 "=X,&b"))]
13137 "TARGET_TOC_FUSION_INT"
13138 {
13139 if (base_reg_operand (operands[0], <MODE>mode))
13140 return emit_fusion_gpr_load (operands[0], operands[1]);
13142 return emit_fusion_p9_load (operands[0], operands[1], operands[3]);
13143 }
13144 [(set_attr "type" "load")
13145 (set_attr "length" "8")])
13147 (define_insn "*toc_fusionload_di"
13148 [(set (match_operand:DI 0 "int_reg_operand" "=&b,??r,?d")
13149 (match_operand:DI 1 "toc_fusion_mem_wrapped" "wG,wG,wG"))
13150 (unspec [(const_int 0)] UNSPEC_FUSION_ADDIS)
13151 (use (match_operand:DI 2 "base_reg_operand" "r,r,r"))
13152 (clobber (match_scratch:DI 3 "=X,&b,&b"))]
13153 "TARGET_TOC_FUSION_INT && TARGET_POWERPC64
13154 && (MEM_P (operands[1]) || int_reg_operand (operands[0], DImode))"
13155 {
13156 if (base_reg_operand (operands[0], DImode))
13157 return emit_fusion_gpr_load (operands[0], operands[1]);
13159 return emit_fusion_p9_load (operands[0], operands[1], operands[3]);
13160 }
13161 [(set_attr "type" "load")
13162 (set_attr "length" "8")])
13164 \f
13165 ;; Find cases where the addis that feeds into a load instruction is either used
13166 ;; once or is the same as the target register, and replace it with the fusion
13167 ;; insn
13169 (define_peephole2
13170 [(set (match_operand:P 0 "base_reg_operand" "")
13171 (match_operand:P 1 "fusion_gpr_addis" ""))
13172 (set (match_operand:INT1 2 "base_reg_operand" "")
13173 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
13174 "TARGET_P8_FUSION
13175 && fusion_gpr_load_p (operands[0], operands[1], operands[2],
13176 operands[3])"
13177 [(const_int 0)]
13178 {
13179 expand_fusion_gpr_load (operands);
13180 DONE;
13181 })
13183 ;; Fusion insn, created by the define_peephole2 above (and eventually by
13184 ;; reload)
13186 (define_insn "fusion_gpr_load_<mode>"
13187 [(set (match_operand:INT1 0 "base_reg_operand" "=b")
13188 (unspec:INT1 [(match_operand:INT1 1 "fusion_addis_mem_combo_load" "wF")]
13189 UNSPEC_FUSION_GPR))]
13190 "TARGET_P8_FUSION"
13191 {
13192 return emit_fusion_gpr_load (operands[0], operands[1]);
13193 }
13194 [(set_attr "type" "load")
13195 (set_attr "length" "8")])
13197 \f
13198 ;; ISA 3.0 (power9) fusion support
13199 ;; Merge addis with floating load/store to FPRs (or GPRs).
13200 (define_peephole2
13201 [(set (match_operand:P 0 "base_reg_operand" "")
13202 (match_operand:P 1 "fusion_gpr_addis" ""))
13203 (set (match_operand:SFDF 2 "toc_fusion_or_p9_reg_operand" "")
13204 (match_operand:SFDF 3 "fusion_offsettable_mem_operand" ""))]
13205 "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
13206 && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])"
13207 [(const_int 0)]
13208 {
13209 expand_fusion_p9_load (operands);
13210 DONE;
13211 })
13213 (define_peephole2
13214 [(set (match_operand:P 0 "base_reg_operand" "")
13215 (match_operand:P 1 "fusion_gpr_addis" ""))
13216 (set (match_operand:SFDF 2 "offsettable_mem_operand" "")
13217 (match_operand:SFDF 3 "toc_fusion_or_p9_reg_operand" ""))]
13218 "TARGET_P9_FUSION && peep2_reg_dead_p (2, operands[0])
13219 && fusion_p9_p (operands[0], operands[1], operands[2], operands[3])"
13220 [(const_int 0)]
13221 {
13222 expand_fusion_p9_store (operands);
13223 DONE;
13224 })
13226 (define_peephole2
13227 [(set (match_operand:SDI 0 "int_reg_operand" "")
13228 (match_operand:SDI 1 "upper16_cint_operand" ""))
13229 (set (match_dup 0)
13230 (ior:SDI (match_dup 0)
13231 (match_operand:SDI 2 "u_short_cint_operand" "")))]
13232 "TARGET_P9_FUSION"
13233 [(set (match_dup 0)
13234 (unspec:SDI [(match_dup 1)
13235 (match_dup 2)] UNSPEC_FUSION_P9))])
13237 (define_peephole2
13238 [(set (match_operand:SDI 0 "int_reg_operand" "")
13239 (match_operand:SDI 1 "upper16_cint_operand" ""))
13240 (set (match_operand:SDI 2 "int_reg_operand" "")
13241 (ior:SDI (match_dup 0)
13242 (match_operand:SDI 3 "u_short_cint_operand" "")))]
13243 "TARGET_P9_FUSION
13244 && !rtx_equal_p (operands[0], operands[2])
13245 && peep2_reg_dead_p (2, operands[0])"
13246 [(set (match_dup 2)
13247 (unspec:SDI [(match_dup 1)
13248 (match_dup 3)] UNSPEC_FUSION_P9))])
13250 ;; Fusion insns, created by the define_peephole2 above (and eventually by
13251 ;; reload). Because we want to eventually have secondary_reload generate
13252 ;; these, they have to have a single alternative that gives the register
13253 ;; classes. This means we need to have separate gpr/fpr/altivec versions.
13254 (define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load"
13255 [(set (match_operand:GPR_FUSION 0 "int_reg_operand" "=r")
13256 (unspec:GPR_FUSION
13257 [(match_operand:GPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
13258 UNSPEC_FUSION_P9))
13259 (clobber (match_operand:P 2 "base_reg_operand" "=b"))]
13260 "TARGET_P9_FUSION"
13261 {
13262 /* This insn is a secondary reload insn, which cannot have alternatives.
13263 If we are not loading up register 0, use the power8 fusion instead. */
13264 if (base_reg_operand (operands[0], <GPR_FUSION:MODE>mode))
13265 return emit_fusion_gpr_load (operands[0], operands[1]);
13267 return emit_fusion_p9_load (operands[0], operands[1], operands[2]);
13268 }
13269 [(set_attr "type" "load")
13270 (set_attr "length" "8")])
13272 (define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store"
13273 [(set (match_operand:GPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
13274 (unspec:GPR_FUSION
13275 [(match_operand:GPR_FUSION 1 "int_reg_operand" "r")]
13276 UNSPEC_FUSION_P9))
13277 (clobber (match_operand:P 2 "base_reg_operand" "=&b"))]
13278 "TARGET_P9_FUSION"
13279 {
13280 return emit_fusion_p9_store (operands[0], operands[1], operands[2]);
13281 }
13282 [(set_attr "type" "store")
13283 (set_attr "length" "8")])
13285 (define_insn "fusion_fpr_<P:mode>_<FPR_FUSION:mode>_load"
13286 [(set (match_operand:FPR_FUSION 0 "fpr_reg_operand" "=d")
13287 (unspec:FPR_FUSION
13288 [(match_operand:FPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
13289 UNSPEC_FUSION_P9))
13290 (clobber (match_operand:P 2 "base_reg_operand" "=b"))]
13291 "TARGET_P9_FUSION"
13292 {
13293 return emit_fusion_p9_load (operands[0], operands[1], operands[2]);
13294 }
13295 [(set_attr "type" "fpload")
13296 (set_attr "length" "8")])
13298 (define_insn "fusion_fpr_<P:mode>_<FPR_FUSION:mode>_store"
13299 [(set (match_operand:FPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
13300 (unspec:FPR_FUSION
13301 [(match_operand:FPR_FUSION 1 "fpr_reg_operand" "d")]
13302 UNSPEC_FUSION_P9))
13303 (clobber (match_operand:P 2 "base_reg_operand" "=b"))]
13304 "TARGET_P9_FUSION"
13305 {
13306 return emit_fusion_p9_store (operands[0], operands[1], operands[2]);
13307 }
13308 [(set_attr "type" "fpstore")
13309 (set_attr "length" "8")])
13311 (define_insn "*fusion_p9_<mode>_constant"
13312 [(set (match_operand:SDI 0 "int_reg_operand" "=r")
13313 (unspec:SDI [(match_operand:SDI 1 "upper16_cint_operand" "L")
13314 (match_operand:SDI 2 "u_short_cint_operand" "K")]
13315 UNSPEC_FUSION_P9))]
13316 "TARGET_P9_FUSION"
13317 {
13318 emit_fusion_addis (operands[0], operands[1], "constant", "<MODE>");
13319 return "ori %0,%0,%2";
13320 }
13321 [(set_attr "type" "two")
13322 (set_attr "length" "8")])
13324 \f
13325 ;; Miscellaneous ISA 2.06 (power7) instructions
13326 (define_insn "addg6s"
13327 [(set (match_operand:SI 0 "register_operand" "=r")
13328 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
13329 (match_operand:SI 2 "register_operand" "r")]
13330 UNSPEC_ADDG6S))]
13331 "TARGET_POPCNTD"
13332 "addg6s %0,%1,%2"
13333 [(set_attr "type" "integer")
13334 (set_attr "length" "4")])
13336 (define_insn "cdtbcd"
13337 [(set (match_operand:SI 0 "register_operand" "=r")
13338 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
13339 UNSPEC_CDTBCD))]
13340 "TARGET_POPCNTD"
13341 "cdtbcd %0,%1"
13342 [(set_attr "type" "integer")
13343 (set_attr "length" "4")])
13345 (define_insn "cbcdtd"
13346 [(set (match_operand:SI 0 "register_operand" "=r")
13347 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
13348 UNSPEC_CBCDTD))]
13349 "TARGET_POPCNTD"
13350 "cbcdtd %0,%1"
13351 [(set_attr "type" "integer")
13352 (set_attr "length" "4")])
13354 (define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE
13355 UNSPEC_DIVEO
13356 UNSPEC_DIVEU
13357 UNSPEC_DIVEUO])
13359 (define_int_attr div_extend [(UNSPEC_DIVE "e")
13360 (UNSPEC_DIVEO "eo")
13361 (UNSPEC_DIVEU "eu")
13362 (UNSPEC_DIVEUO "euo")])
13364 (define_insn "div<div_extend>_<mode>"
13365 [(set (match_operand:GPR 0 "register_operand" "=r")
13366 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r")
13367 (match_operand:GPR 2 "register_operand" "r")]
13368 UNSPEC_DIV_EXTEND))]
13369 "TARGET_POPCNTD"
13370 "div<wd><div_extend> %0,%1,%2"
13371 [(set_attr "type" "div")
13372 (set_attr "size" "<bits>")])
13374 \f
13375 ;; Pack/unpack 128-bit floating point types that take 2 scalar registers
13377 ; Type of the 64-bit part when packing/unpacking 128-bit floating point types
13378 (define_mode_attr FP128_64 [(TF "DF")
13379 (IF "DF")
13380 (TD "DI")
13381 (KF "DI")])
13383 (define_expand "unpack<mode>"
13384 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "")
13385 (unspec:<FP128_64>
13386 [(match_operand:FMOVE128 1 "register_operand" "")
13387 (match_operand:QI 2 "const_0_to_1_operand" "")]
13388 UNSPEC_UNPACK_128BIT))]
13389 "FLOAT128_2REG_P (<MODE>mode)"
13390 "")
13392 (define_insn_and_split "unpack<mode>_dm"
13393 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m")
13394 (unspec:<FP128_64>
13395 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r")
13396 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")]
13397 UNSPEC_UNPACK_128BIT))]
13398 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE && FLOAT128_2REG_P (<MODE>mode)"
13399 "#"
13400 "&& reload_completed"
13401 [(set (match_dup 0) (match_dup 3))]
13402 {
13403 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
13405 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
13406 {
13407 emit_note (NOTE_INSN_DELETED);
13408 DONE;
13409 }
13411 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
13412 }
13413 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store")
13414 (set_attr "length" "4")])
13416 (define_insn_and_split "unpack<mode>_nodm"
13417 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m")
13418 (unspec:<FP128_64>
13419 [(match_operand:FMOVE128 1 "register_operand" "d,d")
13420 (match_operand:QI 2 "const_0_to_1_operand" "i,i")]
13421 UNSPEC_UNPACK_128BIT))]
13422 "(!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE) && FLOAT128_2REG_P (<MODE>mode)"
13423 "#"
13424 "&& reload_completed"
13425 [(set (match_dup 0) (match_dup 3))]
13426 {
13427 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]);
13429 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno)
13430 {
13431 emit_note (NOTE_INSN_DELETED);
13432 DONE;
13433 }
13435 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno);
13436 }
13437 [(set_attr "type" "fp,fpstore")
13438 (set_attr "length" "4")])
13440 (define_insn_and_split "pack<mode>"
13441 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d")
13442 (unspec:FMOVE128
13443 [(match_operand:<FP128_64> 1 "register_operand" "0,d")
13444 (match_operand:<FP128_64> 2 "register_operand" "d,d")]
13445 UNSPEC_PACK_128BIT))]
13446 "FLOAT128_2REG_P (<MODE>mode)"
13447 "@
13448 fmr %L0,%2
13449 #"
13450 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])"
13451 [(set (match_dup 3) (match_dup 1))
13452 (set (match_dup 4) (match_dup 2))]
13453 {
13454 unsigned dest_hi = REGNO (operands[0]);
13455 unsigned dest_lo = dest_hi + 1;
13457 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo));
13458 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo));
13460 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi);
13461 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo);
13462 }
13463 [(set_attr "type" "fpsimple,fp")
13464 (set_attr "length" "4,8")])
13466 (define_insn "unpack<mode>"
13467 [(set (match_operand:DI 0 "register_operand" "=d,d")
13468 (unspec:DI [(match_operand:FMOVE128_VSX 1 "register_operand" "0,wa")
13469 (match_operand:QI 2 "const_0_to_1_operand" "O,i")]
13470 UNSPEC_UNPACK_128BIT))]
13471 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
13472 {
13473 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0)
13474 return ASM_COMMENT_START " xxpermdi to same register";
13476 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3);
13477 return "xxpermdi %x0,%x1,%x1,%3";
13478 }
13479 [(set_attr "type" "vecperm")])
13481 (define_insn "pack<mode>"
13482 [(set (match_operand:FMOVE128_VSX 0 "register_operand" "=wa")
13483 (unspec:FMOVE128_VSX
13484 [(match_operand:DI 1 "register_operand" "d")
13485 (match_operand:DI 2 "register_operand" "d")]
13486 UNSPEC_PACK_128BIT))]
13487 "TARGET_VSX"
13488 "xxpermdi %x0,%x1,%x2,0"
13489 [(set_attr "type" "vecperm")])
13492 \f
13493 ;; ISA 2.08 IEEE 128-bit floating point support.
13495 (define_insn "add<mode>3"
13496 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13497 (plus:IEEE128
13498 (match_operand:IEEE128 1 "altivec_register_operand" "v")
13499 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
13500 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13501 "xsaddqp %0,%1,%2"
13502 [(set_attr "type" "vecfloat")
13503 (set_attr "size" "128")])
13505 (define_insn "sub<mode>3"
13506 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13507 (minus:IEEE128
13508 (match_operand:IEEE128 1 "altivec_register_operand" "v")
13509 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
13510 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13511 "xssubqp %0,%1,%2"
13512 [(set_attr "type" "vecfloat")
13513 (set_attr "size" "128")])
13515 (define_insn "mul<mode>3"
13516 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13517 (mult:IEEE128
13518 (match_operand:IEEE128 1 "altivec_register_operand" "v")
13519 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
13520 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13521 "xsmulqp %0,%1,%2"
13522 [(set_attr "type" "vecfloat")
13523 (set_attr "size" "128")])
13525 (define_insn "div<mode>3"
13526 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13527 (div:IEEE128
13528 (match_operand:IEEE128 1 "altivec_register_operand" "v")
13529 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
13530 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13531 "xsdivqp %0,%1,%2"
13532 [(set_attr "type" "vecdiv")
13533 (set_attr "size" "128")])
13535 (define_insn "sqrt<mode>2"
13536 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13537 (sqrt:IEEE128
13538 (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
13539 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13540 "xssqrtqp %0,%1"
13541 [(set_attr "type" "vecdiv")
13542 (set_attr "size" "128")])
13544 (define_expand "copysign<mode>3"
13545 [(use (match_operand:IEEE128 0 "altivec_register_operand"))
13546 (use (match_operand:IEEE128 1 "altivec_register_operand"))
13547 (use (match_operand:IEEE128 2 "altivec_register_operand"))]
13548 "FLOAT128_IEEE_P (<MODE>mode)"
13549 {
13550 if (TARGET_FLOAT128_HW)
13551 emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
13552 operands[2]));
13553 else
13554 {
13555 rtx tmp = gen_reg_rtx (<MODE>mode);
13556 emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
13557 operands[2], tmp));
13558 }
13559 DONE;
13560 })
13562 (define_insn "copysign<mode>3_hard"
13563 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13564 (unspec:IEEE128
13565 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
13566 (match_operand:IEEE128 2 "altivec_register_operand" "v")]
13567 UNSPEC_COPYSIGN))]
13568 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13569 "xscpsgnqp %0,%2,%1"
13570 [(set_attr "type" "vecmove")
13571 (set_attr "size" "128")])
13573 (define_insn "copysign<mode>3_soft"
13574 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13575 (unspec:IEEE128
13576 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
13577 (match_operand:IEEE128 2 "altivec_register_operand" "v")
13578 (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
13579 UNSPEC_COPYSIGN))]
13580 "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13581 "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
13582 [(set_attr "type" "veccomplex")
13583 (set_attr "length" "8")])
13585 (define_insn "neg<mode>2_hw"
13586 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13587 (neg:IEEE128
13588 (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
13589 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13590 "xsnegqp %0,%1"
13591 [(set_attr "type" "vecmove")
13592 (set_attr "size" "128")])
13595 (define_insn "abs<mode>2_hw"
13596 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13597 (abs:IEEE128
13598 (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
13599 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13600 "xsabsqp %0,%1"
13601 [(set_attr "type" "vecmove")
13602 (set_attr "size" "128")])
13605 (define_insn "*nabs<mode>2_hw"
13606 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13607 (neg:IEEE128
13608 (abs:IEEE128
13609 (match_operand:IEEE128 1 "altivec_register_operand" "v"))))]
13610 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13611 "xsnabsqp %0,%1"
13612 [(set_attr "type" "vecmove")
13613 (set_attr "size" "128")])
13615 ;; Initially don't worry about doing fusion
13616 (define_insn "*fma<mode>4_hw"
13617 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13618 (fma:IEEE128
13619 (match_operand:IEEE128 1 "altivec_register_operand" "%v")
13620 (match_operand:IEEE128 2 "altivec_register_operand" "v")
13621 (match_operand:IEEE128 3 "altivec_register_operand" "0")))]
13622 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13623 "xsmaddqp %0,%1,%2"
13624 [(set_attr "type" "vecfloat")
13625 (set_attr "size" "128")])
13627 (define_insn "*fms<mode>4_hw"
13628 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13629 (fma:IEEE128
13630 (match_operand:IEEE128 1 "altivec_register_operand" "%v")
13631 (match_operand:IEEE128 2 "altivec_register_operand" "v")
13632 (neg:IEEE128
13633 (match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
13634 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13635 "xsmsubqp %0,%1,%2"
13636 [(set_attr "type" "vecfloat")
13637 (set_attr "size" "128")])
13639 (define_insn "*nfma<mode>4_hw"
13640 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13641 (neg:IEEE128
13642 (fma:IEEE128
13643 (match_operand:IEEE128 1 "altivec_register_operand" "%v")
13644 (match_operand:IEEE128 2 "altivec_register_operand" "v")
13645 (match_operand:IEEE128 3 "altivec_register_operand" "0"))))]
13646 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13647 "xsnmaddqp %0,%1,%2"
13648 [(set_attr "type" "vecfloat")
13649 (set_attr "size" "128")])
13651 (define_insn "*nfms<mode>4_hw"
13652 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13653 (neg:IEEE128
13654 (fma:IEEE128
13655 (match_operand:IEEE128 1 "altivec_register_operand" "%v")
13656 (match_operand:IEEE128 2 "altivec_register_operand" "v")
13657 (neg:IEEE128
13658 (match_operand:IEEE128 3 "altivec_register_operand" "0")))))]
13659 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13660 "xsnmsubqp %0,%1,%2"
13661 [(set_attr "type" "vecfloat")
13662 (set_attr "size" "128")])
13664 (define_insn "extend<SFDF:mode><IEEE128:mode>2_hw"
13665 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13666 (float_extend:IEEE128
13667 (match_operand:SFDF 1 "altivec_register_operand" "v")))]
13668 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<IEEE128:MODE>mode)"
13669 "xscvdpqp %0,%1"
13670 [(set_attr "type" "vecfloat")
13671 (set_attr "size" "128")])
13673 ;; Conversion between KFmode and TFmode if TFmode is ieee 128-bit floating
13674 ;; point is a simple copy.
13675 (define_insn_and_split "extendkftf2"
13676 [(set (match_operand:TF 0 "vsx_register_operand" "=wa,?wa")
13677 (float_extend:TF (match_operand:KF 1 "vsx_register_operand" "0,wa")))]
13678 "TARGET_FLOAT128 && TARGET_IEEEQUAD"
13679 "@
13680 #
13681 xxlor %x0,%x1,%x1"
13682 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
13683 [(const_int 0)]
13684 {
13685 emit_note (NOTE_INSN_DELETED);
13686 DONE;
13687 }
13688 [(set_attr "type" "*,veclogical")
13689 (set_attr "length" "0,4")])
13691 (define_insn_and_split "trunctfkf2"
13692 [(set (match_operand:KF 0 "vsx_register_operand" "=wa,?wa")
13693 (float_extend:KF (match_operand:TF 1 "vsx_register_operand" "0,wa")))]
13694 "TARGET_FLOAT128 && TARGET_IEEEQUAD"
13695 "@
13696 #
13697 xxlor %x0,%x1,%x1"
13698 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
13699 [(const_int 0)]
13700 {
13701 emit_note (NOTE_INSN_DELETED);
13702 DONE;
13703 }
13704 [(set_attr "type" "*,veclogical")
13705 (set_attr "length" "0,4")])
13707 (define_insn "trunc<mode>df2_hw"
13708 [(set (match_operand:DF 0 "altivec_register_operand" "=v")
13709 (float_truncate:DF
13710 (match_operand:IEEE128 1 "altivec_register_operand" "v")))]
13711 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13712 "xscvqpdp %0,%1"
13713 [(set_attr "type" "vecfloat")
13714 (set_attr "size" "128")])
13716 ;; There is no KFmode -> SFmode instruction. Preserve the accuracy by doing
13717 ;; the KFmode -> DFmode conversion using round to odd rather than the normal
13718 ;; conversion
13719 (define_insn_and_split "trunc<mode>sf2_hw"
13720 [(set (match_operand:SF 0 "vsx_register_operand" "=wy")
13721 (float_truncate:SF
13722 (match_operand:IEEE128 1 "altivec_register_operand" "v")))
13723 (clobber (match_scratch:DF 2 "=v"))]
13724 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13725 "#"
13726 "&& 1"
13727 [(set (match_dup 2)
13728 (unspec:DF [(match_dup 1)] UNSPEC_ROUND_TO_ODD))
13729 (set (match_dup 0)
13730 (float_truncate:SF (match_dup 2)))]
13731 {
13732 if (GET_CODE (operands[2]) == SCRATCH)
13733 operands[2] = gen_reg_rtx (DFmode);
13734 }
13735 [(set_attr "type" "vecfloat")
13736 (set_attr "length" "8")])
13738 ;; At present SImode is not allowed in VSX registers at all, and DImode is only
13739 ;; allowed in the traditional floating point registers. Use V2DImode so that
13740 ;; we can get a value in an Altivec register.
13742 (define_insn_and_split "fix<uns>_<mode>si2_hw"
13743 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,Z")
13744 (any_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v,v")))
13745 (clobber (match_scratch:V2DI 2 "=v,v"))]
13746 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13747 "#"
13748 "&& 1"
13749 [(pc)]
13750 {
13751 convert_float128_to_int (operands, <CODE>);
13752 DONE;
13753 }
13754 [(set_attr "length" "8")
13755 (set_attr "type" "mftgpr,fpstore")])
13757 (define_insn_and_split "fix<uns>_<mode>di2_hw"
13758 [(set (match_operand:DI 0 "nonimmediate_operand" "=wr,wi,Z")
13759 (any_fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v,v,v")))
13760 (clobber (match_scratch:V2DI 2 "=v,v,v"))]
13761 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13762 "#"
13763 "&& 1"
13764 [(pc)]
13765 {
13766 convert_float128_to_int (operands, <CODE>);
13767 DONE;
13768 }
13769 [(set_attr "length" "8")
13770 (set_attr "type" "mftgpr,vecsimple,fpstore")])
13772 (define_insn_and_split "float<uns>_<mode>si2_hw"
13773 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v")
13774 (any_float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "r,Z")))
13775 (clobber (match_scratch:V2DI 2 "=v,v"))]
13776 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13777 "#"
13778 "&& 1"
13779 [(pc)]
13780 {
13781 convert_int_to_float128 (operands, <CODE>);
13782 DONE;
13783 }
13784 [(set_attr "length" "8")
13785 (set_attr "type" "vecfloat")])
13787 (define_insn_and_split "float<uns>_<mode>di2_hw"
13788 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v")
13789 (any_float:IEEE128 (match_operand:DI 1 "nonimmediate_operand" "wi,wr,Z")))
13790 (clobber (match_scratch:V2DI 2 "=v,v,v"))]
13791 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13792 "#"
13793 "&& 1"
13794 [(pc)]
13795 {
13796 convert_int_to_float128 (operands, <CODE>);
13797 DONE;
13798 }
13799 [(set_attr "length" "8")
13800 (set_attr "type" "vecfloat")])
13802 ;; Integer conversion instructions, using V2DImode to get an Altivec register
13803 (define_insn "*xscvqp<su>wz_<mode>"
13804 [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
13805 (unspec:V2DI
13806 [(any_fix:SI
13807 (match_operand:IEEE128 1 "altivec_register_operand" "v"))]
13808 UNSPEC_IEEE128_CONVERT))]
13809 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13810 "xscvqp<su>wz %0,%1"
13811 [(set_attr "type" "vecfloat")
13812 (set_attr "size" "128")])
13814 (define_insn "*xscvqp<su>dz_<mode>"
13815 [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
13816 (unspec:V2DI
13817 [(any_fix:DI
13818 (match_operand:IEEE128 1 "altivec_register_operand" "v"))]
13819 UNSPEC_IEEE128_CONVERT))]
13820 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13821 "xscvqp<su>dz %0,%1"
13822 [(set_attr "type" "vecfloat")
13823 (set_attr "size" "128")])
13825 (define_insn "*xscv<su>dqp_<mode>"
13826 [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
13827 (any_float:IEEE128
13828 (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v")]
13829 UNSPEC_IEEE128_CONVERT)))]
13830 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13831 "xscv<su>dqp %0,%1"
13832 [(set_attr "type" "vecfloat")
13833 (set_attr "size" "128")])
13835 (define_insn "*ieee128_mfvsrd_64bit"
13836 [(set (match_operand:DI 0 "reg_or_indexed_operand" "=wr,Z,wi")
13837 (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v,v,v")]
13838 UNSPEC_IEEE128_MOVE))]
13839 "TARGET_FLOAT128_HW && TARGET_POWERPC64"
13840 "@
13841 mfvsrd %0,%x1
13842 stxsdx %x1,%y0
13843 xxlor %x0,%x1,%x1"
13844 [(set_attr "type" "mftgpr,fpstore,veclogical")])
13847 (define_insn "*ieee128_mfvsrd_32bit"
13848 [(set (match_operand:DI 0 "reg_or_indexed_operand" "=Z,wi")
13849 (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v,v")]
13850 UNSPEC_IEEE128_MOVE))]
13851 "TARGET_FLOAT128_HW && !TARGET_POWERPC64"
13852 "@
13853 stxsdx %x1,%y0
13854 xxlor %x0,%x1,%x1"
13855 [(set_attr "type" "fpstore,veclogical")])
13857 (define_insn "*ieee128_mfvsrwz"
13858 [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z")
13859 (unspec:SI [(match_operand:V2DI 1 "altivec_register_operand" "v,v")]
13860 UNSPEC_IEEE128_MOVE))]
13861 "TARGET_FLOAT128_HW"
13862 "@
13863 mfvsrwz %0,%x1
13864 stxsiwx %x1,%y0"
13865 [(set_attr "type" "mftgpr,fpstore")])
13867 ;; 0 says do sign-extension, 1 says zero-extension
13868 (define_insn "*ieee128_mtvsrw"
13869 [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v,v,v")
13870 (unspec:V2DI [(match_operand:SI 1 "nonimmediate_operand" "r,Z,r,Z")
13871 (match_operand:SI 2 "const_0_to_1_operand" "O,O,n,n")]
13872 UNSPEC_IEEE128_MOVE))]
13873 "TARGET_FLOAT128_HW"
13874 "@
13875 mtvsrwa %x0,%1
13876 lxsiwax %x0,%y1
13877 mtvsrwz %x0,%1
13878 lxsiwzx %x0,%y1"
13879 [(set_attr "type" "mffgpr,fpload,mffgpr,fpload")])
13882 (define_insn "*ieee128_mtvsrd_64bit"
13883 [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v,v")
13884 (unspec:V2DI [(match_operand:DI 1 "nonimmediate_operand" "wr,Z,wi")]
13885 UNSPEC_IEEE128_MOVE))]
13886 "TARGET_FLOAT128_HW && TARGET_POWERPC64"
13887 "@
13888 mtvsrd %x0,%1
13889 lxsdx %x0,%y1
13890 xxlor %x0,%x1,%x1"
13891 [(set_attr "type" "mffgpr,fpload,veclogical")])
13893 (define_insn "*ieee128_mtvsrd_32bit"
13894 [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v")
13895 (unspec:V2DI [(match_operand:DI 1 "nonimmediate_operand" "Z,wi")]
13896 UNSPEC_IEEE128_MOVE))]
13897 "TARGET_FLOAT128_HW && !TARGET_POWERPC64"
13898 "@
13899 lxsdx %x0,%y1
13900 xxlor %x0,%x1,%x1"
13901 [(set_attr "type" "fpload,veclogical")])
13903 ;; IEEE 128-bit instructions with round to odd semantics
13904 (define_insn "*trunc<mode>df2_odd"
13905 [(set (match_operand:DF 0 "vsx_register_operand" "=v")
13906 (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
13907 UNSPEC_ROUND_TO_ODD))]
13908 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13909 "xscvqpdpo %0,%1"
13910 [(set_attr "type" "vecfloat")
13911 (set_attr "size" "128")])
13913 ;; IEEE 128-bit comparisons
13914 (define_insn "*cmp<mode>_hw"
13915 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13916 (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
13917 (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
13918 "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
13919 "xscmpuqp %0,%1,%2"
13920 [(set_attr "type" "veccmp")
13921 (set_attr "size" "128")])
13923 \f
13925 (include "sync.md")
13926 (include "vector.md")
13927 (include "vsx.md")
13928 (include "altivec.md")
13929 (include "spe.md")
13930 (include "dfp.md")
13931 (include "paired.md")
13932 (include "crypto.md")
13933 (include "htm.md")