| blob | 9870967ea7109972bf4192f6469097b76ab0751e |
1 /* Instruction scheduling pass.
2 Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction scheduling pass.
24 This pass implements list scheduling within basic blocks. It is
25 run after flow analysis, but before register allocation. The
26 scheduler works as follows:
28 We compute insn priorities based on data dependencies. Flow
29 analysis only creates a fraction of the data-dependencies we must
30 observe: namely, only those dependencies which the combiner can be
31 expected to use. For this pass, we must therefore create the
32 remaining dependencies we need to observe: register dependencies,
33 memory dependencies, dependencies to keep function calls in order,
34 and the dependence between a conditional branch and the setting of
35 condition codes are all dealt with here.
37 The scheduler first traverses the data flow graph, starting with
38 the last instruction, and proceeding to the first, assigning
39 values to insn_priority as it goes. This sorts the instructions
40 topologically by data dependence.
42 Once priorities have been established, we order the insns using
43 list scheduling. This works as follows: starting with a list of
44 all the ready insns, and sorted according to priority number, we
45 schedule the insn from the end of the list by placing its
46 predecessors in the list according to their priority order. We
47 consider this insn scheduled by setting the pointer to the "end" of
48 the list to point to the previous insn. When an insn has no
49 predecessors, we either queue it until sufficient time has elapsed
50 or add it to the ready list. As the instructions are scheduled or
51 when stalls are introduced, the queue advances and dumps insns into
52 the ready list. When all insns down to the lowest priority have
53 been scheduled, the critical path of the basic block has been made
54 as short as possible. The remaining insns are then scheduled in
55 remaining slots.
57 Function unit conflicts are resolved during reverse list scheduling
58 by tracking the time when each insn is committed to the schedule
59 and from that, the time the function units it uses must be free.
60 As insns on the ready list are considered for scheduling, those
61 that would result in a blockage of the already committed insns are
62 queued until no blockage will result. Among the remaining insns on
63 the ready list to be considered, the first one with the largest
64 potential for causing a subsequent blockage is chosen.
66 The following list shows the order in which we want to break ties
67 among insns in the ready list:
69 1. choose insn with lowest conflict cost, ties broken by
70 2. choose insn with the longest path to end of bb, ties broken by
71 3. choose insn that kills the most registers, ties broken by
72 4. choose insn that conflicts with the most ready insns, or finally
73 5. choose insn with lowest UID.
75 Memory references complicate matters. Only if we can be certain
76 that memory references are not part of the data dependency graph
77 (via true, anti, or output dependence), can we move operations past
78 memory references. To first approximation, reads can be done
79 independently, while writes introduce dependencies. Better
80 approximations will yield fewer dependencies.
82 Dependencies set up by memory references are treated in exactly the
83 same way as other dependencies, by using LOG_LINKS.
85 Having optimized the critical path, we may have also unduly
86 extended the lifetimes of some registers. If an operation requires
87 that constants be loaded into registers, it is certainly desirable
88 to load those constants as early as necessary, but no earlier.
89 I.e., it will not do to load up a bunch of registers at the
90 beginning of a basic block only to use them at the end, if they
91 could be loaded later, since this may result in excessive register
92 utilization.
94 Note that since branches are never in basic blocks, but only end
95 basic blocks, this pass will not do any branch scheduling. But
96 that is ok, since we can use GNU's delayed branch scheduling
97 pass to take care of this case.
99 Also note that no further optimizations based on algebraic identities
100 are performed, so this pass would be a good one to perform instruction
101 splitting, such as breaking up a multiply instruction into shifts
102 and adds where that is profitable.
104 Given the memory aliasing analysis that this pass should perform,
105 it should be possible to remove redundant stores to memory, and to
106 load values from registers instead of hitting memory.
108 This pass must update information that subsequent passes expect to be
109 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
110 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
111 basic_block_end.
113 The information in the line number notes is carefully retained by this
114 pass. All other NOTE insns are grouped in their same relative order at
115 the beginning of basic blocks that have been scheduled. */
116 \f
117 #include <stdio.h>
127 #ifdef INSN_SCHEDULING
128 /* Arrays set up by scheduling for the same respective purposes as
129 similar-named arrays set up by flow analysis. We work with these
130 arrays during the scheduling pass so we can compare values against
131 unscheduled code.
133 Values of these arrays are copied at the end of this pass into the
134 arrays set up by flow analysis. */
139 /* Element N is the next insn that sets (hard or pseudo) register
140 N within the current basic block; or zero, if there is no
141 such insn. Needed for new registers which may be introduced
142 by splitting insns. */
148 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
150 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
152 /* Vector indexed by INSN_UID giving each instruction a priority. */
154 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
157 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
159 /* Vector indexed by INSN_UID giving an encoding of the function units
160 used. */
162 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
164 /* Vector indexed by INSN_UID giving an encoding of the blockage range
165 function. The unit and the range are encoded. */
167 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
168 #define UNIT_BITS 5
169 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
170 #define ENCODE_BLOCKAGE(U,R) \
171 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
172 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
173 | MAX_BLOCKAGE_COST (R))
174 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
175 #define BLOCKAGE_RANGE(B) \
176 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
177 | (B) & BLOCKAGE_MASK)
179 /* Encodings of the `<name>_unit_blockage_range' function. */
180 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
181 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
183 #define DONE_PRIORITY -1
184 #define MAX_PRIORITY 0x7fffffff
185 #define TAIL_PRIORITY 0x7ffffffe
186 #define LAUNCH_PRIORITY 0x7f000001
187 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
188 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
190 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
192 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
194 /* Vector indexed by INSN_UID giving line-number note in effect for each
195 insn. For line-number notes, this indicates whether the note may be
196 reused. */
198 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
200 /* Vector indexed by basic block number giving the starting line-number
201 for each basic block. */
204 /* List of important notes we must keep around. This is a pointer to the
205 last element in the list. */
208 /* Regsets telling whether a given register is live or dead before the last
209 scheduled insn. Must scan the instructions once before scheduling to
210 determine what registers are live or dead at the end of the block. */
214 /* Regset telling whether a given register is live after the insn currently
215 being scheduled. Before processing an insn, this is equal to bb_live_regs
216 above. This is used so that we can find registers that are newly born/dead
217 after processing an insn. */
220 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
221 during the initial scan and reused later. If there are not exactly as
222 many REG_DEAD notes in the post scheduled code as there were in the
223 prescheduled code then we trigger an abort because this indicates a bug. */
226 /* Queues, etc. */
228 /* An instruction is ready to be scheduled when all insns following it
229 have already been scheduled. It is important to ensure that all
230 insns which use its result will not be executed until its result
231 has been computed. An insn is maintained in one of four structures:
233 (P) the "Pending" set of insns which cannot be scheduled until
234 their dependencies have been satisfied.
235 (Q) the "Queued" set of insns that can be scheduled when sufficient
236 time has passed.
237 (R) the "Ready" list of unscheduled, uncommitted insns.
238 (S) the "Scheduled" list of insns.
240 Initially, all insns are either "Pending" or "Ready" depending on
241 whether their dependencies are satisfied.
243 Insns move from the "Ready" list to the "Scheduled" list as they
244 are committed to the schedule. As this occurs, the insns in the
245 "Pending" list have their dependencies satisfied and move to either
246 the "Ready" list or the "Queued" set depending on whether
247 sufficient time has passed to make them ready. As time passes,
248 insns move from the "Queued" set to the "Ready" list. Insns may
249 move from the "Ready" list to the "Queued" set if they are blocked
250 due to a function unit conflict.
252 The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled
253 insns, i.e., those that are ready, queued, and pending.
254 The "Queued" set (Q) is implemented by the variable `insn_queue'.
255 The "Ready" list (R) is implemented by the variables `ready' and
256 `n_ready'.
257 The "Scheduled" list (S) is the new insn chain built by this pass.
259 The transition (R->S) is implemented in the scheduling loop in
260 `schedule_block' when the best insn to schedule is chosen.
261 The transition (R->Q) is implemented in `schedule_select' when an
262 insn is found to to have a function unit conflict with the already
263 committed insns.
264 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
265 insns move from the ready list to the scheduled list.
266 The transition (Q->R) is implemented at the top of the scheduling
267 loop in `schedule_block' as time passes or stalls are introduced. */
269 /* Implement a circular buffer to delay instructions until sufficient
270 time has passed. INSN_QUEUE_SIZE is a power of two larger than
271 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
272 longest time an isnsn may be queued. */
276 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
277 #define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1))
279 /* Vector indexed by INSN_UID giving the minimum clock tick at which
280 the insn becomes ready. This is used to note timing constraints for
281 insns in the pending list. */
283 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
285 /* Data structure for keeping track of register information
286 during that register's life. */
288 struct sometimes
289 {
292 };
294 /* Forward declarations. */
299 HOST_WIDE_INT));
342 /* Main entry point of this file. */
346 \f
347 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
349 /* Vector indexed by N giving the initial (unchanging) value known
350 for pseudo-register N. */
353 /* Vector recording for each reg_known_value whether it is due to a
354 REG_EQUIV note. Future passes (viz., reload) may replace the
355 pseudo with the equivalent expression and so we account for the
356 dependences that would be introduced if that happens. */
357 /* ??? This is a problem only on the Convex. The REG_EQUIV notes created in
358 assign_parms mention the arg pointer, and there are explicit insns in the
359 RTL that modify the arg pointer. Thus we must ensure that such insns don't
360 get scheduled across each other because that would invalidate the REG_EQUIV
361 notes. One could argue that the REG_EQUIV notes are wrong, but solving
362 the problem in the scheduler will likely give better code, so we do it
363 here. */
366 /* Indicates number of valid entries in reg_known_value. */
369 static rtx
371 rtx x;
372 {
377 {
382 {
383 /* We can tolerate LO_SUMs being offset here; these
384 rtl are used for nothing other than comparisons. */
390 }
391 }
393 }
395 /* Set up all info needed to perform alias analysis on memory references. */
397 void
399 {
401 rtx insn;
402 rtx note;
403 rtx set;
407 reg_known_value
413 reg_known_equiv_p
419 /* Fill in the entries with known constant values. */
428 {
432 }
434 /* Fill in the remaining entries. */
438 }
440 /* Return 1 if X and Y are identical-looking rtx's.
442 We use the data in reg_known_value above to see if two registers with
443 different numbers are, in fact, equivalent. */
445 static int
448 {
465 /* Rtx's of different codes cannot be equal. */
469 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
470 (REG:SI x) and (REG:HI x) are NOT equivalent. */
475 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
484 /* For commutative operations, the RTX match if the operand match in any
485 order. Also handle the simple binary and unary cases without a loop. */
497 /* Compare the elements. If any pair of corresponding elements
498 fail to match, return 0 for the whole things. */
502 {
504 {
518 /* Two vectors must have the same length. */
522 /* And the corresponding elements must match. */
540 /* These are just backpointers, so they don't matter. */
546 /* It is believed that rtx's at this level will never
547 contain anything but integers and other rtx's,
548 except for within LABEL_REFs and SYMBOL_REFs. */
551 }
552 }
554 }
556 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
557 X and return it, or return 0 if none found. */
559 static rtx
561 rtx x;
562 {
575 {
576 rtx t;
579 {
583 }
586 }
588 }
590 /* Return nonzero if X and Y (memory addresses) could reference the
591 same location in memory. C is an offset accumulator. When
592 C is nonzero, we are testing aliases between X and Y + C.
593 XSIZE is the size in bytes of the X reference,
594 similarly YSIZE is the size in bytes for Y.
596 If XSIZE or YSIZE is zero, we do not know the amount of memory being
597 referenced (the reference was BLKmode), so make the most pessimistic
598 assumptions.
600 We recognize the following cases of non-conflicting memory:
602 (1) addresses involving the frame pointer cannot conflict
603 with addresses involving static variables.
604 (2) static variables with different addresses cannot conflict.
606 Nice to notice that varying addresses cannot conflict with fp if no
607 local variables had their addresses taken, but that's too hard now. */
609 /* ??? In Fortran, references to a array parameter can never conflict with
610 another array parameter. */
612 static int
616 HOST_WIDE_INT c;
617 {
622 else
628 else
637 {
642 }
646 {
647 rtx y1;
656 {
660 }
668 }
671 {
672 /* The fact that X is canonicalized means that this
673 PLUS rtx is canonicalized. */
678 {
679 /* The fact that Y is canonicalized means that this
680 PLUS rtx is canonicalized. */
692 else
697 /* Handle case where we cannot understand iteration operators,
698 but we notice that the base addresses are distinct objects. */
706 }
709 }
711 {
712 /* The fact that Y is canonicalized means that this
713 PLUS rtx is canonicalized. */
719 else
721 }
725 {
727 {
728 /* Handle cases where we expect the second operands to be the
729 same, and check only whether the first operand would conflict
730 or not. */
742 /* Can't properly adjust our sizes. */
749 }
750 }
753 {
755 {
759 }
762 {
766 else
769 }
780 }
782 }
784 /* Functions to compute memory dependencies.
786 Since we process the insns in execution order, we can build tables
787 to keep track of what registers are fixed (and not aliased), what registers
788 are varying in known ways, and what registers are varying in unknown
789 ways.
791 If both memory references are volatile, then there must always be a
792 dependence between the two references, since their order can not be
793 changed. A volatile and non-volatile reference can be interchanged
794 though.
796 A MEM_IN_STRUCT reference at a non-QImode varying address can never
797 conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must
798 allow QImode aliasing because the ANSI C standard allows character
799 pointers to alias anything. We are assuming that characters are
800 always QImode here. */
802 /* Read dependence: X is read after read in MEM takes place. There can
803 only be a dependence here if both reads are volatile. */
805 int
807 rtx mem;
808 rtx x;
809 {
811 }
813 /* True dependence: X is read after store in MEM takes place. */
815 int
817 rtx mem;
818 rtx x;
819 {
820 /* If X is an unchanging read, then it can't possibly conflict with any
821 non-unchanging store. It may conflict with an unchanging write though,
822 because there may be a single store to this address to initialize it.
823 Just fall through to the code below to resolve the case where we have
824 both an unchanging read and an unchanging write. This won't handle all
825 cases optimally, but the possible performance loss should be
826 negligible. */
839 }
841 /* Anti dependence: X is written after read in MEM takes place. */
843 int
845 rtx mem;
846 rtx x;
847 {
848 /* If MEM is an unchanging read, then it can't possibly conflict with
849 the store to X, because there is at most one store to MEM, and it must
850 have occured somewhere before MEM. */
863 }
865 /* Output dependence: X is written after store in MEM takes place. */
867 int
869 rtx mem;
870 rtx x;
871 {
881 }
882 \f
883 /* Helper functions for instruction scheduling. */
885 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
886 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
887 of dependence that this link represents. */
889 static void
891 rtx insn;
892 rtx elem;
894 {
897 /* Don't depend an insn on itself. */
901 /* If elem is part of a sequence that must be scheduled together, then
902 make the dependence point to the last insn of the sequence.
903 When HAVE_cc0, it is possible for NOTEs to exist between users and
904 setters of the condition codes, so we must skip past notes here.
905 Otherwise, NOTEs are impossible here. */
909 #ifdef HAVE_cc0
912 #endif
915 {
916 /* Notes will never intervene here though, so don't bother checking
917 for them. */
918 /* We must reject CODE_LABELs, so that we don't get confused by one
919 that has LABEL_PRESERVE_P set, which is represented by the same
920 bit in the rtl as SCHED_GROUP_P. A CODE_LABEL can never be
921 SCHED_GROUP_P. */
926 /* Again, don't depend an insn on itself. */
930 /* Make the dependence to NEXT, the last insn of the group, instead
931 of the original ELEM. */
933 }
935 /* Check that we don't already have this dependence. */
938 {
939 /* If this is a more restrictive type of dependence than the existing
940 one, then change the existing dependence to this type. */
944 }
945 /* Might want to check one level of transitivity to save conses. */
948 /* Insn dependency, not data dependency. */
953 }
955 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
956 of INSN. Abort if not found. */
958 static void
960 rtx insn;
961 rtx elem;
962 {
968 {
970 {
973 else
976 }
977 }
982 }
983 \f
984 #ifndef INSN_SCHEDULING
985 void
988 {
989 }
990 #else
991 #ifndef __GNUC__
992 #define __inline
993 #endif
995 /* Computation of memory dependencies. */
997 /* The *_insns and *_mems are paired lists. Each pending memory operation
998 will have a pointer to the MEM rtx on one list and a pointer to the
999 containing insn on the other list in the same place in the list. */
1001 /* We can't use add_dependence like the old code did, because a single insn
1002 may have multiple memory accesses, and hence needs to be on the list
1003 once for each memory access. Add_dependence won't let you add an insn
1004 to a list more than once. */
1006 /* An INSN_LIST containing all insns with pending read operations. */
1009 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
1012 /* An INSN_LIST containing all insns with pending write operations. */
1015 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
1018 /* Indicates the combined length of the two pending lists. We must prevent
1019 these lists from ever growing too large since the number of dependencies
1020 produced is at least O(N*N), and execution time is at least O(4*N*N), as
1021 a function of the length of these pending lists. */
1025 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
1029 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
1033 /* The last insn upon which all memory references must depend.
1034 This is an insn which flushed the pending lists, creating a dependency
1035 between it and all previously pending memory references. This creates
1036 a barrier (or a checkpoint) which no memory reference is allowed to cross.
1038 This includes all non constant CALL_INSNs. When we do interprocedural
1039 alias analysis, this restriction can be relaxed.
1040 This may also be an INSN that writes memory if the pending lists grow
1041 too large. */
1045 /* The last function call we have seen. All hard regs, and, of course,
1046 the last function call, must depend on this. */
1050 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
1051 that does not already cross a call. We create dependencies between each
1052 of those insn and the next call insn, to ensure that they won't cross a call
1053 after scheduling is done. */
1057 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
1058 so that insns independent of the last scheduled insn will be preferred
1059 over dependent instructions. */
1063 /* Process an insn's memory dependencies. There are four kinds of
1064 dependencies:
1066 (0) read dependence: read follows read
1067 (1) true dependence: read follows write
1068 (2) anti dependence: write follows read
1069 (3) output dependence: write follows write
1071 We are careful to build only dependencies which actually exist, and
1072 use transitivity to avoid building too many links. */
1073 \f
1074 /* Return the INSN_LIST containing INSN in LIST, or NULL
1075 if LIST does not contain INSN. */
1077 __inline static rtx
1079 rtx insn;
1080 rtx list;
1081 {
1083 {
1087 }
1089 }
1091 /* Compute the function units used by INSN. This caches the value
1092 returned by function_units_used. A function unit is encoded as the
1093 unit number if the value is non-negative and the compliment of a
1094 mask if the value is negative. A function unit index is the
1095 non-negative encoding. */
1097 __inline static int
1099 rtx insn;
1100 {
1104 {
1107 /* A USE insn, or something else we don't need to understand.
1108 We can't pass these directly to function_units_used because it will
1109 trigger a fatal error for unrecognizable insns. */
1112 else
1113 {
1115 /* Increment non-negative values so we can cache zero. */
1117 }
1118 /* We only cache 16 bits of the result, so if the value is out of
1119 range, don't cache it. */
1124 }
1126 }
1128 /* Compute the blockage range for executing INSN on UNIT. This caches
1129 the value returned by the blockage_range_function for the unit.
1130 These values are encoded in an int where the upper half gives the
1131 minimum value and the lower half gives the maximum value. */
1133 __inline static unsigned int
1136 rtx insn;
1137 {
1142 {
1144 /* We only cache the blockage range for one unit and then only if
1145 the values fit. */
1148 }
1149 else
1153 }
1155 /* A vector indexed by function unit instance giving the last insn to use
1156 the unit. The value of the function unit instance index for unit U
1157 instance I is (U + I * FUNCTION_UNITS_SIZE). */
1160 /* A vector indexed by function unit instance giving the minimum time when
1161 the unit will unblock based on the maximum blockage cost. */
1164 /* A vector indexed by function unit number giving the number of insns
1165 that remain to use the unit. */
1168 /* Reset the function unit state to the null state. */
1170 static void
1172 {
1176 }
1178 /* Record an insn as one that will use the units encoded by UNIT. */
1180 __inline static void
1183 {
1188 else
1192 }
1194 /* Return the actual hazard cost of executing INSN on the unit UNIT,
1195 instance INSTANCE at time CLOCK if the previous actual hazard cost
1196 was COST. */
1198 __inline static int
1201 rtx insn;
1202 {
1206 {
1207 /* The scheduler is operating in reverse, so INSN is the executing
1208 insn and the unit's last insn is the candidate insn. We want a
1209 more exact measure of the blockage if we execute INSN at CLOCK
1210 given when we committed the execution of the unit's last insn.
1212 The blockage value is given by either the unit's max blockage
1213 constant, blockage range function, or blockage function. Use
1214 the most exact form for the given unit. */
1217 {
1222 else
1225 }
1228 }
1230 }
1232 /* Record INSN as having begun execution on the units encoded by UNIT at
1233 time CLOCK. */
1235 __inline static void
1238 rtx insn;
1239 {
1243 {
1245 #if MAX_MULTIPLICITY > 1
1246 /* Find the first free instance of the function unit and use that
1247 one. We assume that one is free. */
1249 {
1253 }
1254 #endif
1257 }
1258 else
1262 }
1264 /* Return the actual hazard cost of executing INSN on the units encoded by
1265 UNIT at time CLOCK if the previous actual hazard cost was COST. */
1267 __inline static int
1270 rtx insn;
1271 {
1275 {
1276 /* Find the instance of the function unit with the minimum hazard. */
1282 #if MAX_MULTIPLICITY > 1
1284 {
1286 {
1291 {
1295 }
1296 }
1297 }
1298 #endif
1300 }
1301 else
1307 }
1309 /* Return the potential hazard cost of executing an instruction on the
1310 units encoded by UNIT if the previous potential hazard cost was COST.
1311 An insn with a large blockage time is chosen in preference to one
1312 with a smaller time; an insn that uses a unit that is more likely
1313 to be used is chosen in preference to one with a unit that is less
1314 used. We are trying to minimize a subsequent actual hazard. */
1316 __inline static int
1319 rtx insn;
1320 {
1325 {
1328 {
1330 {
1334 }
1337 {
1338 /* Make the number of instructions left dominate. Make the
1339 minimum delay dominate the maximum delay. If all these
1340 are the same, use the unit number to add an arbitrary
1341 ordering. Other terms can be added. */
1346 }
1347 }
1348 }
1349 else
1355 }
1357 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
1358 This is the number of virtual cycles taken between instruction issue and
1359 instruction results. */
1361 __inline static int
1364 {
1368 {
1371 /* A USE insn, or something else we don't need to understand.
1372 We can't pass these directly to result_ready_cost because it will
1373 trigger a fatal error for unrecognizable insns. */
1375 {
1378 }
1379 else
1380 {
1387 }
1388 }
1390 /* A USE insn should never require the value used to be computed. This
1391 allows the computation of a function's result and parameter values to
1392 overlap the return and call. */
1397 /* If some dependencies vary the cost, compute the adjustment. Most
1398 commonly, the adjustment is complete: either the cost is ignored
1399 (in the case of an output- or anti-dependence), or the cost is
1400 unchanged. These values are cached in the link as LINK_COST_FREE
1401 and LINK_COST_ZERO. */
1405 #ifdef ADJUST_COST
1407 {
1416 }
1417 #endif
1419 }
1421 /* Compute the priority number for INSN. */
1423 static int
1425 rtx insn;
1426 {
1428 {
1432 rtx prev;
1439 /* Nonzero if these insns must be scheduled together. */
1441 {
1444 {
1447 }
1448 }
1451 {
1454 /* A dependence pointing to a note or deleted insn is always
1455 obsolete, because sched_analyze_insn will have created any
1456 necessary new dependences which replace it. Notes and deleted
1457 insns can be created when instructions are deleted by insn
1458 splitting, or by register allocation. */
1460 {
1463 }
1465 /* Clear the link cost adjustment bits. */
1467 #ifdef ADJUST_COST
1469 #endif
1471 /* This priority calculation was chosen because it results in the
1472 least instruction movement, and does not hurt the performance
1473 of the resulting code compared to the old algorithm.
1474 This makes the sched algorithm more stable, which results
1475 in better code, because there is less register pressure,
1476 cross jumping is more likely to work, and debugging is easier.
1478 When all instructions have a latency of 1, there is no need to
1479 move any instructions. Subtracting one here ensures that in such
1480 cases all instructions will end up with a priority of one, and
1481 hence no scheduling will be done.
1483 The original code did not subtract the one, and added the
1484 insn_cost of the current instruction to its priority (e.g.
1485 move the insn_cost call down to the end). */
1492 }
1497 }
1499 }
1500 \f
1501 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
1502 them to the unused_*_list variables, so that they can be reused. */
1504 static void
1506 {
1510 {
1515 {
1518 }
1523 }
1526 {
1531 {
1534 }
1539 }
1542 {
1547 {
1550 }
1555 }
1558 {
1563 {
1566 }
1571 }
1572 }
1574 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
1575 The MEM is a memory reference contained within INSN, which we are saving
1576 so that we can do memory aliasing on it. */
1578 static void
1581 {
1585 {
1588 }
1589 else
1596 {
1599 }
1600 else
1606 pending_lists_length++;
1607 }
1608 \f
1609 /* Make a dependency between every memory reference on the pending lists
1610 and INSN, thus flushing the pending lists. */
1612 static void
1614 rtx insn;
1615 {
1616 rtx link;
1619 {
1631 }
1633 {
1645 }
1652 }
1654 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1655 by the write to the destination of X, and reads of everything mentioned. */
1657 static void
1659 rtx x;
1660 rtx insn;
1661 {
1670 {
1672 {
1673 /* The second and third arguments are values read by this insn. */
1676 }
1678 }
1681 {
1686 /* A hard reg in a wide mode may really be multiple registers.
1687 If so, mark all of them just like the first. */
1689 {
1692 {
1693 rtx u;
1700 REG_DEP_OUTPUT);
1705 /* Function calls clobber all call_used regs. */
1707 }
1708 }
1709 else
1710 {
1711 rtx u;
1721 /* Pseudos that are REG_EQUIV to something may be replaced
1722 by that during reloading. We need only add dependencies for
1723 the address in the REG_EQUIV note. */
1729 /* Don't let it cross a call after scheduling if it doesn't
1730 already cross one. */
1733 }
1734 }
1736 {
1737 /* Writing memory. */
1740 {
1741 /* Flush all pending reads and writes to prevent the pending lists
1742 from getting any larger. Insn scheduling runs too slowly when
1743 these lists get long. The number 32 was chosen because it
1744 seems like a reasonable number. When compiling GCC with itself,
1745 this flush occurs 8 times for sparc, and 10 times for m88k using
1746 the number 32. */
1748 }
1749 else
1750 {
1756 {
1757 /* If a dependency already exists, don't create a new one. */
1764 }
1769 {
1770 /* If a dependency already exists, don't create a new one. */
1777 }
1784 }
1786 }
1788 /* Analyze reads. */
1791 }
1793 /* Analyze the uses of memory and registers in rtx X in INSN. */
1795 static void
1797 rtx x;
1798 rtx insn;
1799 {
1811 {
1817 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1818 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1819 this does not mean that this insn is using cc0. */
1822 #ifdef HAVE_cc0
1824 {
1827 /* There may be a note before this insn now, but all notes will
1828 be removed before we actually try to schedule the insns, so
1829 it won't cause a problem later. We must avoid it here though. */
1831 /* User of CC0 depends on immediately preceding insn. */
1834 /* Make a copy of all dependencies on the immediately previous insn,
1835 and add to this insn. This is so that all the dependencies will
1836 apply to the group. Remove an explicit dependence on this insn
1837 as SCHED_GROUP_P now represents it. */
1850 }
1851 #endif
1854 {
1857 {
1862 {
1870 /* Function calls clobber all call_used regs. */
1872 }
1873 }
1874 else
1875 {
1881 /* Pseudos that are REG_EQUIV to something may be replaced
1882 by that during reloading. We need only add dependencies for
1883 the address in the REG_EQUIV note. */
1889 /* If the register does not already cross any calls, then add this
1890 insn to the sched_before_next_call list so that it will still
1891 not cross calls after scheduling. */
1894 }
1896 }
1899 {
1900 /* Reading memory. */
1907 {
1908 /* If a dependency already exists, don't create a new one. */
1915 }
1920 {
1921 /* If a dependency already exists, don't create a new one. */
1928 }
1932 /* Always add these dependencies to pending_reads, since
1933 this insn may be followed by a write. */
1937 /* Take advantage of tail recursion here. */
1940 }
1946 {
1947 rtx u;
1949 /* Traditional and volatile asm instructions must be considered to use
1950 and clobber all hard registers, all pseudo-registers and all of
1951 memory. So must TRAP_IF and UNSPEC_VOLATILE operations.
1953 Consider for instance a volatile asm that changes the fpu rounding
1954 mode. An insn should not be moved across this even if it only uses
1955 pseudo-regs because it might give an incorrectly rounded result. */
1957 {
1960 {
1966 }
1970 }
1972 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
1973 We can not just fall through here since then we would be confused
1974 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
1975 traditional asms unlike their normal usage. */
1978 {
1982 }
1984 }
1990 /* These both read and modify the result. We must handle them as writes
1991 to get proper dependencies for following instructions. We must handle
1992 them as reads to get proper dependencies from this to previous
1993 instructions. Thus we need to pass them to both sched_analyze_1
1994 and sched_analyze_2. We must call sched_analyze_2 first in order
1995 to get the proper antecedent for the read. */
1999 }
2001 /* Other cases: walk the insn. */
2004 {
2010 }
2011 }
2013 /* Analyze an INSN with pattern X to find all dependencies. */
2015 static void
2018 {
2020 rtx link;
2027 {
2030 {
2034 else
2036 }
2037 }
2038 else
2041 /* Mark registers CLOBBERED or used by called function. */
2044 {
2047 else
2049 }
2051 /* After reload, it is possible for an instruction to have a REG_DEAD note
2052 for a register that actually dies a few instructions earlier. For
2053 example, this can happen with SECONDARY_MEMORY_NEEDED reloads.
2054 In this case, we must consider the insn to use the register mentioned
2055 in the REG_DEAD note. Otherwise, we may accidentally move this insn
2056 after another insn that sets the register, thus getting obviously invalid
2057 rtl. This confuses reorg which believes that REG_DEAD notes are still
2058 meaningful.
2060 ??? We would get better code if we fixed reload to put the REG_DEAD
2061 notes in the right places, but that may not be worth the effort. */
2064 {
2065 rtx note;
2070 }
2073 {
2076 {
2082 }
2083 }
2085 {
2089 }
2091 /* Handle function calls and function returns created by the epilogue
2092 threading code. */
2094 {
2095 rtx dep_insn;
2096 rtx prev_dep_insn;
2098 /* When scheduling instructions, we make sure calls don't lose their
2099 accompanying USE insns by depending them one on another in order.
2101 Also, we must do the same thing for returns created by the epilogue
2102 threading code. Note this code works only in this special case,
2103 because other passes make no guarantee that they will never emit
2104 an instruction between a USE and a RETURN. There is such a guarantee
2105 for USE instructions immediately before a call. */
2111 {
2114 /* Make a copy of all dependencies on dep_insn, and add to insn.
2115 This is so that all of the dependencies will apply to the
2116 group. */
2123 }
2124 }
2125 }
2127 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
2128 for every dependency. */
2130 static int
2133 {
2140 {
2144 {
2147 }
2149 {
2150 rtx x;
2153 /* Any instruction using a hard register which may get clobbered
2154 by a call needs to be marked as dependent on this call.
2155 This prevents a use of a hard return reg from being moved
2156 past a void call (i.e. it does not explicitly set the hard
2157 return reg). */
2159 /* If this call is followed by a NOTE_INSN_SETJMP, then assume that
2160 all registers, not just hard registers, may be clobbered by this
2161 call. */
2163 /* Insn, being a CALL_INSN, magically depends on
2164 `last_function_call' already. */
2168 {
2171 {
2177 }
2180 /* Add a fake REG_NOTE which we will later convert
2181 back into a NOTE_INSN_SETJMP note. */
2184 }
2185 else
2186 {
2189 {
2197 }
2198 }
2200 /* For each insn which shouldn't cross a call, add a dependence
2201 between that insn and this call insn. */
2204 {
2207 }
2212 /* We don't need to flush memory for a function call which does
2213 not involve memory. */
2215 {
2216 /* In the absence of interprocedural alias analysis,
2217 we must flush all pending reads and writes, and
2218 start new dependencies starting from here. */
2220 }
2222 /* Depend this function call (actually, the user of this
2223 function call) on all hard register clobberage. */
2226 }
2230 }
2231 }
2232 \f
2233 /* Called when we see a set of a register. If death is true, then we are
2234 scanning backwards. Mark that register as unborn. If nobody says
2235 otherwise, that is how things will remain. If death is false, then we
2236 are scanning forwards. Mark that register as being born. */
2238 static void
2241 rtx x;
2243 {
2253 {
2254 /* Must treat modification of just one hardware register of a multi-reg
2255 value or just a byte field of a register exactly the same way that
2256 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
2257 does not kill the entire register. */
2263 }
2268 /* Global registers are always live, so the code below does not apply
2269 to them. */
2273 {
2275 register REGSET_ELT_TYPE bit
2279 {
2280 /* If we only set part of the register, then this set does not
2281 kill it. */
2285 /* Try killing this register. */
2287 {
2290 {
2296 }
2297 }
2298 else
2299 {
2302 }
2303 }
2304 else
2305 {
2306 /* Make the register live again. */
2308 {
2311 {
2317 }
2318 }
2319 else
2320 {
2323 }
2324 }
2325 }
2326 }
2327 \f
2328 /* Macros and functions for keeping the priority queue sorted, and
2329 dealing with queueing and unqueueing of instructions. */
2331 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
2332 do { if ((NEW_READY) - (OLD_READY) == 1) \
2333 swap_sort (READY, NEW_READY); \
2334 else if ((NEW_READY) - (OLD_READY) > 1) \
2335 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
2336 while (0)
2338 /* Returns a positive value if y is preferred; returns a negative value if
2339 x is preferred. Should never return 0, since that will make the sort
2340 unstable. */
2342 static int
2345 {
2348 rtx link;
2352 /* Choose the instruction with the highest priority, if different. */
2357 {
2358 /* Classify the instructions into three classes:
2359 1) Data dependent on last schedule insn.
2360 2) Anti/Output dependent on last scheduled insn.
2361 3) Independent of last scheduled insn, or has latency of one.
2362 Choose the insn from the highest numbered class if different. */
2368 else
2376 else
2381 }
2383 /* If insns are equally good, sort by INSN_LUID (original insn order),
2384 so that we make the sort stable. This minimizes instruction movement,
2385 thus minimizing sched's effect on debugging and cross-jumping. */
2387 }
2389 /* Resort the array A in which only element at index N may be out of order. */
2391 __inline static void
2395 {
2400 {
2403 }
2405 }
2409 /* Add INSN to the insn queue so that it fires at least N_CYCLES
2410 before the currently executing insn. */
2412 __inline static void
2414 rtx insn;
2416 {
2421 }
2423 /* Return nonzero if PAT is the pattern of an insn which makes a
2424 register live. */
2426 __inline static int
2428 rtx pat;
2429 {
2437 {
2443 /* It would be more accurate to use refers_to_regno_p or
2444 reg_mentioned_p to determine when the dest is not live before this
2445 insn. */
2451 }
2453 {
2457 }
2459 }
2461 /* PREV is an insn that is ready to execute. Adjust its priority if that
2462 will help shorten register lifetimes. */
2464 __inline static void
2466 rtx prev;
2467 {
2468 /* Trying to shorten register lives after reload has completed
2469 is useless and wrong. It gives inaccurate schedules. */
2471 {
2472 rtx note;
2475 /* ??? This code has no effect, because REG_DEAD notes are removed
2476 before we ever get here. */
2481 /* Defer scheduling insns which kill registers, since that
2482 shortens register lives. Prefer scheduling insns which
2483 make registers live for the same reason. */
2485 {
2498 {
2503 }
2505 }
2506 }
2507 }
2509 /* INSN is the "currently executing insn". Launch each insn which was
2510 waiting on INSN (in the backwards dataflow sense). READY is a
2511 vector of insns which are ready to fire. N_READY is the number of
2512 elements in READY. CLOCK is the current virtual cycle. */
2514 static int
2516 rtx insn;
2520 {
2521 rtx link;
2530 /* This is used by the function adjust_priority above. */
2533 else
2537 {
2542 {
2543 /* We satisfied one requirement to fire PREV. Record the earliest
2544 time when PREV can fire. No need to do this if the cost is 1,
2545 because PREV can fire no sooner than the next cycle. */
2548 }
2549 else
2550 {
2551 /* We satisfied the last requirement to fire PREV. Ensure that all
2552 timing requirements are satisfied. */
2556 /* Adjust the priority of PREV and either put it on the ready
2557 list or queue it. */
2561 else
2563 }
2564 }
2567 }
2569 /* Given N_READY insns in the ready list READY at time CLOCK, queue
2570 those that are blocked due to function unit hazards and rearrange
2571 the remaining ones to minimize subsequent function unit hazards. */
2573 static int
2578 {
2581 rtx insn;
2583 /* Work down the ready list in groups of instructions with the same
2584 priority value. Queue insns in the group that are blocked and
2585 select among those that remain for the one with the largest
2586 potential hazard. */
2588 {
2594 /* Queue insns in the group that are blocked. */
2596 {
2599 {
2600 q++;
2606 }
2607 }
2610 /* Check the next group if all insns were queued. */
2614 /* If more than one remains, select the first one with the largest
2615 potential hazard. */
2617 {
2620 {
2625 {
2628 }
2629 }
2630 }
2631 /* We have found a suitable insn to schedule. */
2633 }
2635 /* Move the best insn to be front of the ready list. */
2637 {
2639 {
2646 }
2648 {
2652 }
2653 }
2655 /* Compact the ready list. */
2662 }
2664 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
2665 dead_notes list. */
2667 static void
2670 {
2671 rtx link;
2673 /* The number of registers killed after scheduling must be the same as the
2674 number of registers killed before scheduling. The number of REG_DEAD
2675 notes may not be conserved, i.e. two SImode hard register REG_DEAD notes
2676 might become one DImode hard register REG_DEAD note, but the number of
2677 registers killed will be conserved.
2679 We carefully remove REG_DEAD notes from the dead_notes list, so that
2680 there will be none left at the end. If we run out early, then there
2681 is a bug somewhere in flow, combine and/or sched. */
2684 {
2685 #if 1
2687 #else
2690 #endif
2691 }
2692 else
2693 {
2694 /* Number of regs killed by REG. */
2697 /* Number of regs killed by REG_DEAD notes taken off the list. */
2705 {
2710 }
2713 /* If we took too many regs kills off, put the extra ones back. */
2715 {
2724 reg_note_regs--;
2725 }
2726 }
2731 }
2733 /* Subroutine on attach_deaths_insn--handles the recursive search
2734 through INSN. If SET_P is true, then x is being modified by the insn. */
2736 static void
2738 rtx x;
2739 rtx insn;
2741 {
2753 {
2762 /* Get rid of the easy cases first. */
2766 {
2767 /* If the register dies in this insn, queue that note, and mark
2768 this register as needing to die. */
2769 /* This code is very similar to mark_used_1 (if set_p is false)
2770 and mark_set_1 (if set_p is true) in flow.c. */
2774 register REGSET_ELT_TYPE bit
2783 {
2788 {
2795 }
2796 }
2798 /* If it wasn't live before we started, then add a REG_DEAD note.
2799 We must check the previous lifetime info not the current info,
2800 because we may have to execute this code several times, e.g.
2801 once for a clobber (which doesn't add a note) and later
2802 for a use (which does add a note).
2804 Always make the register live. We must do this even if it was
2805 live before, because this may be an insn which sets and uses
2806 the same register, in which case the register has already been
2807 killed, so we must make it live again.
2809 Global registers are always live, and should never have a REG_DEAD
2810 note added for them, so none of the code below applies to them. */
2813 {
2814 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2815 STACK_POINTER_REGNUM, since these are always considered to be
2816 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2818 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2820 #endif
2821 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2823 #endif
2825 {
2827 {
2828 /* If none of the words in X is needed, make a REG_DEAD
2829 note. Otherwise, we must make partial REG_DEAD
2830 notes. */
2833 else
2834 {
2837 /* Don't make a REG_DEAD note for a part of a
2838 register that is set in the insn. */
2848 insn);
2849 }
2850 }
2851 }
2854 {
2857 {
2859 bit
2864 }
2865 }
2866 else
2867 {
2870 }
2871 }
2873 }
2876 /* Handle tail-recursive case. */
2882 /* These two cases preserve the value of SET_P, so handle them
2883 separately. */
2889 /* This case preserves the value of SET_P for the first operand, but
2890 clears it for the other two. */
2897 /* Other cases: walk the insn. */
2900 {
2906 }
2907 }
2908 }
2910 /* After INSN has executed, add register death notes for each register
2911 that is dead after INSN. */
2913 static void
2915 rtx insn;
2916 {
2919 rtx link;
2922 {
2925 /* A register might die here even if it is the destination, e.g.
2926 it is the target of a volatile read and is otherwise unused.
2927 Hence we must always call attach_deaths for the SET_DEST. */
2929 }
2931 {
2934 {
2937 {
2941 }
2942 /* Flow does not add REG_DEAD notes to registers that die in
2943 clobbers, so we can't either. */
2946 }
2947 }
2948 /* If this is a CLOBBER, only add REG_DEAD notes to registers inside a
2949 MEM being clobbered, just like flow. */
2952 /* Otherwise don't add a death note to things being clobbered. */
2956 /* Make death notes for things used in the called function. */
2961 }
2963 /* Delete notes beginning with INSN and maybe put them in the chain
2964 of notes ended by NOTE_LIST.
2965 Returns the insn following the notes. */
2967 static rtx
2970 {
2974 {
2976 /* Delete the note from its current position. */
2983 /* Record line-number notes so they can be reused. */
2986 /* Don't save away NOTE_INSN_SETJMPs, because they must remain
2987 immediately after the call they follow. We use a fake
2988 (REG_DEAD (const_int -1)) note to remember them. */
2990 {
2991 /* Insert the note at the end of the notes list. */
2996 }
2999 }
3001 }
3003 /* Constructor for `sometimes' data structure. */
3005 static int
3010 {
3014 /* There should never be a register greater than max_regno here. If there
3015 is, it means that a define_split has created a new pseudo reg. This
3016 is not allowed, since there will not be flow info available for any
3017 new register, so catch the error here. */
3026 sometimes_max++;
3028 }
3030 /* Count lengths of all regs we are currently tracking,
3031 and find new registers no longer live. */
3033 static void
3037 {
3041 {
3049 }
3050 }
3052 /* Use modified list scheduling to rearrange insns in basic block
3053 B. FILE, if nonzero, is where we dump interesting output about
3054 this pass. */
3056 static void
3060 {
3066 #define NEED_NOTHING 0
3067 #define NEED_HEAD 1
3068 #define NEED_TAIL 2
3071 /* HEAD and TAIL delimit the region being scheduled. */
3074 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
3075 being scheduled. When the insns have been ordered,
3076 these insns delimit where the new insns are to be
3077 spliced back into the insn chain. */
3078 rtx next_tail;
3079 rtx prev_head;
3081 /* Keep life information accurate. */
3099 /* Remove certain insns at the beginning from scheduling,
3100 by advancing HEAD. */
3102 /* At the start of a function, before reload has run, don't delay getting
3103 parameters from hard registers into pseudo registers. */
3105 {
3113 {
3124 /* Keep this insn from ever being scheduled. */
3127 }
3128 }
3130 /* Don't include any notes or labels at the beginning of the
3131 basic block, or notes at the ends of basic blocks. */
3133 {
3141 }
3142 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
3143 to schedule this block. */
3148 #if 0
3149 /* This short-cut doesn't work. It does not count call insns crossed by
3150 registers in reg_sometimes_live. It does not mark these registers as
3151 dead if they die in this block. It does not mark these registers live
3152 (or create new reg_sometimes_live entries if necessary) if they are born
3153 in this block.
3155 The easy solution is to just always schedule a block. This block only
3156 has one insn, so this won't slow down this pass by much. */
3160 #endif
3162 /* Now HEAD through TAIL are the insns actually to be rearranged;
3163 Let PREV_HEAD and NEXT_TAIL enclose them. */
3167 /* Initialize basic block data structures. */
3182 {
3185 }
3187 /* Allocate vector to hold insns to be rearranged (except those
3188 insns which are controlled by an insn with SCHED_GROUP_P set).
3189 All these insns are included between ORIG_HEAD and ORIG_TAIL,
3190 as those variables ultimately are set up. */
3193 /* TAIL is now the last of the insns to be rearranged.
3194 Put those insns into the READY vector. */
3197 /* For all branches, calls, uses, and cc0 setters, force them to remain
3198 in order at the end of the block by adding dependencies and giving
3199 the last a high priority. There may be notes present, and prev_head
3200 may also be a note.
3202 Branches must obviously remain at the end. Calls should remain at the
3203 end since moving them results in worse register allocation. Uses remain
3204 at the end to ensure proper register allocation. cc0 setters remaim
3205 at the end because they can't be moved away from their cc0 user. */
3210 #ifdef HAVE_cc0
3212 #endif
3213 ))
3215 {
3217 {
3220 {
3224 }
3226 {
3229 }
3232 /* Skip over insns that are part of a group. */
3234 {
3237 }
3238 }
3241 /* Don't overrun the bounds of the basic block. */
3244 }
3246 /* Assign priorities to instructions. Also check whether they
3247 are in priority order already. If so then I will be nonnegative.
3248 We use this shortcut only before reloading. */
3249 #if 0
3251 #endif
3254 {
3256 {
3259 {
3262 else
3263 {
3264 /* Make this dependent on the last of the instructions
3265 that must remain in order at the end of the block. */
3268 }
3269 }
3271 {
3273 {
3278 }
3280 }
3281 #if 0
3288 #endif
3289 }
3290 }
3292 #if 0
3293 /* This short-cut doesn't work. It does not count call insns crossed by
3294 registers in reg_sometimes_live. It does not mark these registers as
3295 dead if they die in this block. It does not mark these registers live
3296 (or create new reg_sometimes_live entries if necessary) if they are born
3297 in this block.
3299 The easy solution is to just always schedule a block. These blocks tend
3300 to be very short, so this doesn't slow down this pass by much. */
3302 /* If existing order is good, don't bother to reorder. */
3304 {
3309 {
3314 }
3317 }
3318 #endif
3320 /* Scan all the insns to be scheduled, removing NOTE insns
3321 and register death notes.
3322 Line number NOTE insns end up in NOTE_LIST.
3323 Register death notes end up in DEAD_NOTES.
3325 Recreate the register life information for the end of this basic
3326 block. */
3329 {
3331 regset_bytes);
3335 {
3336 /* This is the first block in the function. There may be insns
3337 before head that we can't schedule. We still need to examine
3338 them though for accurate register lifetime analysis. */
3340 /* We don't want to remove any REG_DEAD notes as the code below
3341 does. */
3346 {
3347 /* See if the register gets born here. */
3348 /* We must check for registers being born before we check for
3349 registers dying. It is possible for a register to be born
3350 and die in the same insn, e.g. reading from a volatile
3351 memory location into an otherwise unused register. Such
3352 a register must be marked as dead after this insn. */
3357 {
3364 /* ??? This code is obsolete and should be deleted. It
3365 is harmless though, so we will leave it in for now. */
3369 }
3372 {
3375 /* Verify that the REG_NOTE has a legal value. */
3377 {
3380 register REGSET_ELT_TYPE bit
3384 {
3388 {
3395 }
3396 }
3397 else
3398 {
3401 }
3402 }
3403 }
3404 }
3405 }
3406 }
3408 /* If debugging information is being produced, keep track of the line
3409 number notes for each insn. */
3411 {
3412 /* We must use the true line number for the first insn in the block
3413 that was computed and saved at the start of this pass. We can't
3414 use the current line number, because scheduling of the previous
3415 block may have changed the current line number. */
3423 else
3425 }
3428 {
3431 /* Farm out notes. This is needed to keep the debugger from
3432 getting completely deranged. */
3434 {
3443 }
3447 {
3448 /* See if the register gets born here. */
3449 /* We must check for registers being born before we check for
3450 registers dying. It is possible for a register to be born and
3451 die in the same insn, e.g. reading from a volatile memory
3452 location into an otherwise unused register. Such a register
3453 must be marked as dead after this insn. */
3458 {
3465 /* ??? This code is obsolete and should be deleted. It
3466 is harmless though, so we will leave it in for now. */
3470 }
3472 /* Need to know what registers this insn kills. */
3474 {
3478 /* Verify that the REG_NOTE has a legal value. */
3480 {
3483 register REGSET_ELT_TYPE bit
3486 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
3487 alone. */
3489 {
3492 else
3496 }
3497 else
3501 {
3505 {
3512 }
3513 }
3514 else
3515 {
3518 }
3519 }
3520 else
3522 }
3523 }
3524 }
3527 {
3528 /* Keep track of register lives. */
3530 regs_sometimes_live
3534 /* Start with registers live at end. */
3536 {
3540 {
3546 }
3547 }
3548 }
3553 {
3564 }
3566 /* Now HEAD and TAIL are going to become disconnected
3567 entirely from the insn chain. */
3570 /* Q_SIZE will always be zero here. */
3574 /* Now, perform list scheduling. */
3576 /* Where we start inserting insns is after TAIL. */
3586 {
3589 /* Add all pending insns that can be scheduled without stalls to the
3590 ready list. */
3592 {
3598 }
3601 /* If there are no ready insns, stall until one is ready and add all
3602 of the pending insns at that point to the ready list. */
3604 {
3609 {
3611 {
3617 }
3620 }
3623 }
3625 /* There should be some instructions waiting to fire. */
3630 {
3635 }
3637 /* Sort the ready list and choose the best insn to schedule. Select
3638 which insn should issue in this cycle and queue those that are
3639 blocked by function unit hazards.
3641 N_READY holds the number of items that were scheduled the last time,
3642 minus the one instruction scheduled on the last loop iteration; it
3643 is not modified for any other reason in this loop. */
3647 {
3650 {
3653 /* We must set n_ready here, to ensure that sorting always
3654 occurs when we come back to the SCHED_SORT line above. */
3657 }
3658 }
3662 /* The first insn scheduled becomes the new tail. */
3667 {
3672 }
3678 {
3679 /* Process this insn, and each insn linked to this one which must
3680 be immediately output after this insn. */
3681 do
3682 {
3683 /* First we kill registers set by this insn, and then we
3684 make registers used by this insn live. This is the opposite
3685 order used above because we are traversing the instructions
3686 backwards. */
3688 /* Strictly speaking, we should scan REG_UNUSED notes and make
3689 every register mentioned there live, however, we will just
3690 kill them again immediately below, so there doesn't seem to
3691 be any reason why we bother to do this. */
3693 /* See if this is the last notice we must take of a register. */
3698 {
3704 }
3706 /* This code keeps life analysis information up to date. */
3708 {
3711 /* A call kills all call used and global registers, except
3712 for those mentioned in the call pattern which will be
3713 made live again later. */
3716 {
3718 register REGSET_ELT_TYPE bit
3723 }
3725 /* Regs live at the time of a call instruction must not
3726 go in a register clobbered by calls. Record this for
3727 all regs now live. Note that insns which are born or
3728 die in a call do not cross a call, so this must be done
3729 after the killings (above) and before the births
3730 (below). */
3736 }
3738 /* Make every register used live, and add REG_DEAD notes for
3739 registers which were not live before we started. */
3742 /* Find registers now made live by that instruction. */
3744 {
3747 {
3752 sometimes_max
3754 sometimes_max);
3755 }
3756 }
3758 /* Count lengths of all regs we are worrying about now,
3759 and handle registers no longer live. */
3762 {
3770 {
3771 /* This is the end of one of this register's lifetime
3772 segments. Save the lifetime info collected so far,
3773 and clear its bit in the old_live_regs entry. */
3779 /* Delete the reg_sometimes_live entry for this reg by
3780 copying the last entry over top of it. */
3782 /* ...and decrement i so that this newly copied entry
3783 will be processed. */
3784 i--;
3785 }
3786 }
3790 }
3793 /* Set INSN back to the insn we are scheduling now. */
3795 }
3797 /* Schedule INSN. Remove it from the ready list. */
3806 /* Check to see if we need to re-emit a NOTE_INSN_SETJMP here. */
3808 {
3812 {
3815 }
3816 }
3818 /* Everything that precedes INSN now either becomes "ready", if
3819 it can execute immediately before INSN, or "pending", if
3820 there must be a delay. Give INSN high enough priority that
3821 at least one (maybe more) reg-killing insns can be launched
3822 ahead of all others. Mark INSN as scheduled by changing its
3823 priority to -1. */
3828 /* Schedule all prior insns that must not be moved. */
3830 {
3831 /* Disable these insns from being launched. */
3834 {
3835 /* Disable these insns from being launched by anybody. */
3838 }
3840 /* None of these insns can move forward into delay slots. */
3842 {
3851 }
3852 }
3853 }
3860 /* HEAD is now the first insn in the chain of insns that
3861 been scheduled by the loop above.
3862 TAIL is the last of those insns. */
3865 /* NOTE_LIST is the end of a chain of notes previously found
3866 among the insns. Insert them at the beginning of the insns. */
3868 {
3876 }
3878 /* There should be no REG_DEAD notes leftover at the end.
3879 In practice, this can occur as the result of bugs in flow, combine.c,
3880 and/or sched.c. The values of the REG_DEAD notes remaining are
3881 meaningless, because dead_notes is just used as a free list. */
3882 #if 1
3885 #endif
3897 /* Restore the line-number notes of each insn. */
3899 {
3906 /* Determine the current line-number. We want to know the current
3907 line number of the first insn of the block here, in case it is
3908 different from the true line number that was saved earlier. If
3909 different, then we need a line number note before the first insn
3910 of this block. If it happens to be the same, then we don't want to
3911 emit another line number note here. */
3916 /* Walk the insns keeping track of the current line-number and inserting
3917 the line-number notes as needed. */
3921 /* This used to emit line number notes before every non-deleted note.
3922 However, this confuses a debugger, because line notes not separated
3923 by real instructions all end up at the same address. I can find no
3924 use for line number notes before other notes, so none are emitted. */
3931 {
3935 {
3936 /* Re-use the original line-number note. */
3942 }
3943 else
3944 {
3945 notes++;
3948 }
3949 }
3952 }
3955 {
3956 fprintf (file, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n",
3958 }
3960 /* Yow! We're done! */
3964 }
3965 \f
3966 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
3967 REGNO, returning the rtx of the reference found if any. Otherwise,
3968 returns 0. */
3970 static rtx
3973 rtx x;
3974 {
3977 rtx tem;
3984 {
3986 {
3989 }
3994 }
3997 }
3999 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
4000 needed for the hard register mentioned in the note. This can happen
4001 if the reference to the hard register in the original insn was split into
4002 several smaller hard register references in the split insns. */
4004 static void
4007 {
4010 rtx insn;
4012 /* Assume that this is a REG_DEAD note. */
4021 {
4024 /* Check for references to new_reg in the split insns. */
4026 {
4029 {
4030 /* Create a new reg dead note here. */
4037 /* If killed multiple registers here, then add in the excess. */
4041 }
4042 /* It isn't mentioned anywhere, so no new reg note is needed for
4043 this register. */
4046 }
4047 }
4048 }
4050 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
4051 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
4053 static void
4056 {
4059 /* PAT is either a CLOBBER or a SET here. */
4068 {
4070 {
4074 {
4084 {
4085 /* Use the same scheme as combine.c, don't put both REG_DEAD
4086 and REG_UNUSED notes on the same insn. */
4089 {
4095 }
4096 /* The reg only dies in one insn, the last one that uses
4097 it. */
4099 }
4101 /* We found an instruction that both uses the register,
4102 and sets it, so no new REG_NOTE is needed for this set. */
4104 }
4105 }
4106 /* If this is a set, it must die somewhere, unless it is the dest of
4107 the original insn, and hence is live after the original insn. Abort
4108 if it isn't supposed to be live after the original insn.
4110 If this is a clobber, then just add a REG_UNUSED note. */
4112 {
4118 {
4125 }
4127 /* The original insn could have multiple sets, so search the
4128 insn for all sets. */
4130 {
4133 }
4135 {
4142 }
4146 }
4147 }
4148 }
4150 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
4151 registers modified by X. INC is -1 if the containing insn is being deleted,
4152 and is 1 if the containing insn is a newly generated insn. */
4154 static void
4156 rtx x;
4158 {
4166 {
4170 {
4176 }
4177 else
4179 }
4180 }
4182 /* Updates all flow-analysis related quantities (including REG_NOTES) for
4183 the insns from FIRST to LAST inclusive that were created by splitting
4184 ORIG_INSN. NOTES are the original REG_NOTES. */
4186 static void
4188 rtx notes;
4190 rtx orig_insn;
4191 {
4193 rtx next;
4195 rtx set;
4197 /* Get and save the destination set by the original insn. */
4203 /* Move REG_NOTES from the original insn to where they now belong. */
4206 {
4209 {
4212 /* Move these notes from the original insn to the last new insn where
4213 the register is now set. */
4216 {
4219 {
4220 /* If this note refers to a multiple word hard register, it
4221 may have been split into several smaller hard register
4222 references, so handle it specially. */
4229 else
4230 {
4233 }
4235 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
4236 notes. */
4237 /* ??? This won't handle multiple word registers correctly,
4238 but should be good enough for now. */
4243 /* The reg only dies in one insn, the last one that uses
4244 it. */
4246 }
4247 /* It must die somewhere, fail it we couldn't find where it died.
4249 If this is a REG_UNUSED note, then it must be a temporary
4250 register that was not needed by this instantiation of the
4251 pattern, so we can safely ignore it. */
4253 {
4258 }
4259 }
4263 /* This note applies to the dest of the original insn. Find the
4264 first new insn that now has the same dest, and move the note
4265 there. */
4271 {
4275 {
4278 /* The reg is only zero before one insn, the first that
4279 uses it. */
4281 }
4282 /* It must be set somewhere, fail if we couldn't find where it
4283 was set. */
4286 }
4291 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
4292 set is meaningless. Just drop the note. */
4297 /* These notes apply to the dest of the original insn. Find the last
4298 new insn that now has the same dest, and move the note there. */
4304 {
4308 {
4311 /* Only put this note on one of the new insns. */
4313 }
4315 /* The original dest must still be set someplace. Abort if we
4316 couldn't find it. */
4319 }
4323 /* Move a REG_LIBCALL note to the first insn created, and update
4324 the corresponding REG_RETVAL note. */
4335 /* Move a REG_RETVAL note to the last insn created, and update
4336 the corresponding REG_LIBCALL note. */
4347 /* This should be moved to whichever instruction is a JUMP_INSN. */
4350 {
4352 {
4355 /* Only put this note on one of the new insns. */
4357 }
4358 /* Fail if we couldn't find a JUMP_INSN. */
4361 }
4365 /* This should be moved to whichever instruction now has the
4366 increment operation. */
4370 /* Should be moved to the new insn(s) which use the label. */
4380 /* These two notes will never appear until after reorg, so we don't
4381 have to handle them here. */
4384 }
4385 }
4387 /* Each new insn created, except the last, has a new set. If the destination
4388 is a register, then this reg is now live across several insns, whereas
4389 previously the dest reg was born and died within the same insn. To
4390 reflect this, we now need a REG_DEAD note on the insn where this
4391 dest reg dies.
4393 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
4396 {
4397 rtx pat;
4404 {
4409 }
4410 }
4412 /* If any insn, except the last, uses the register set by the last insn,
4413 then we need a new REG_DEAD note on that insn. In this case, there
4414 would not have been a REG_DEAD note for this register in the original
4415 insn because it was used and set within one insn.
4417 There is no new REG_DEAD note needed if the last insn uses the register
4418 that it is setting. */
4422 {
4432 {
4434 {
4438 {
4448 {
4454 /* The reg only dies in one insn, the last one
4455 that uses it. */
4457 }
4458 }
4461 }
4462 }
4463 }
4465 /* If the original dest is modifying a multiple register target, and the
4466 original instruction was split such that the original dest is now set
4467 by two or more SUBREG sets, then the split insns no longer kill the
4468 destination of the original insn.
4470 In this case, if there exists an instruction in the same basic block,
4471 before the split insn, which uses the original dest, and this use is
4472 killed by the original insn, then we must remove the REG_DEAD note on
4473 this insn, because it is now superfluous.
4475 This does not apply when a hard register gets split, because the code
4476 knows how to handle overlapping hard registers properly. */
4478 {
4483 {
4486 {
4489 {
4492 }
4495 {
4498 }
4499 }
4503 }
4506 {
4507 /* Search backwards from FIRST, looking for the first insn that uses
4508 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
4509 If we find an insn, and it has a REG_DEAD note, then delete the
4510 note. */
4513 {
4519 {
4523 }
4524 }
4525 }
4527 {
4528 /* This should never happen. */
4530 }
4531 }
4533 /* Update reg_n_sets. This is necessary to prevent local alloc from
4534 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
4535 a reg from set once to set multiple times. */
4537 {
4544 {
4547 {
4551 }
4552 }
4555 {
4562 {
4565 {
4569 }
4570 }
4574 }
4575 }
4576 }
4578 /* The one entry point in this file. DUMP_FILE is the dump file for
4579 this pass. */
4581 void
4584 {
4587 rtx insn;
4589 /* Taking care of this degenerate case makes the rest of
4590 this code simpler. */
4594 /* Create an insn here so that we can hang dependencies off of it later. */
4595 sched_before_next_call
4599 /* Initialize the unused_*_lists. We can't use the ones left over from
4600 the previous function, because gcc has freed that memory. We can use
4601 the ones left over from the first sched pass in the second pass however,
4602 so only clear them on the first sched pass. The first pass is before
4603 reload if flag_schedule_insns is set, otherwise it is afterwards. */
4606 {
4609 }
4611 /* We create no insns here, only reorder them, so we
4612 remember how far we can cut back the stack on exit. */
4614 /* Allocate data for this pass. See comments, above,
4615 for what these vectors do. */
4625 {
4636 }
4637 else
4638 {
4646 }
4649 {
4650 rtx line;
4657 /* Determine the line-number at the start of each basic block.
4658 This must be computed and saved now, because after a basic block's
4659 predecessor has been scheduled, it is impossible to accurately
4660 determine the correct line number for the first insn of the block. */
4665 {
4668 }
4669 }
4679 /* Schedule each basic block, block by block. */
4681 /* ??? Add a NOTE after the last insn of the last basic block. It is not
4682 known why this is done. */
4688 /* Don't emit a NOTE if it would end up between an unconditional
4689 jump and a BARRIER. */
4695 {
4701 {
4702 rtx prev;
4703 rtx set;
4705 /* Can't use `next_real_insn' because that
4706 might go across CODE_LABELS and short-out basic blocks. */
4709 {
4714 }
4716 /* Don't split no-op move insns. These should silently disappear
4717 later in final. Splitting such insns would break the code
4718 that handles REG_NO_CONFLICT blocks. */
4721 {
4725 /* Nops get in the way while scheduling, so delete them now if
4726 register allocation has already been done. It is too risky
4727 to try to do this before register allocation, and there are
4728 unlikely to be very many nops then anyways. */
4730 {
4734 }
4737 }
4739 /* Split insns here to get max fine-grain parallelism. */
4742 {
4748 {
4749 /* try_split returns the NOTE that INSN became. */
4759 {
4762 }
4763 }
4764 }
4768 }
4772 #ifdef USE_C_ALLOCA
4774 #endif
4775 }
4777 /* Reposition the prologue and epilogue notes in case we moved the
4778 prologue/epilogue insns. */
4783 {
4789 /* Walk the insns deleting redundant line-number notes. Many of these
4790 are already present. The remainder tend to occur at basic
4791 block boundaries. */
4794 {
4795 /* If there are no active insns following, INSN is redundant. */
4797 {
4798 notes++;
4801 }
4802 /* If the line number is unchanged, LINE is redundant. */
4806 {
4807 notes++;
4811 }
4812 else
4815 }
4821 active_insn++;
4825 }
4828 {
4832 {
4834 {
4840 /* Negative values are special; don't overwrite the current
4841 reg_live_length value if it is negative. */
4859 }
4860 /* Negative values are special; don't overwrite the current
4861 reg_live_length value if it is negative. */
4865 /* We can't change the value of reg_n_calls_crossed to zero for
4866 pseudos which are live in more than one block.
4868 This is because combine might have made an optimization which
4869 invalidated basic_block_live_at_start and reg_n_calls_crossed,
4870 but it does not update them. If we update reg_n_calls_crossed
4871 here, the two variables are now inconsistent, and this might
4872 confuse the caller-save code into saving a register that doesn't
4873 need to be saved. This is only a problem when we zero calls
4874 crossed for a pseudo live in multiple basic blocks.
4876 Alternatively, we could try to correctly update basic block live
4877 at start here in sched, but that seems complicated. */
4881 }
4882 }
4883 }