gcc/config/s390/s390-modes.def

   1 /* Definitions of target machine for GNU compiler, for IBM S/390
   2    Copyright (C) 2002-2018 Free Software Foundation, Inc.
   3    Contributed by Hartmut Penner (hpenner@de.ibm.com) and
   4                   Ulrich Weigand (uweigand@de.ibm.com).
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE.  */
  23 INT_MODE (OI, 32);
  24
  25 /* Define TFmode to work around reload problem PR 20927.  */
  26 FLOAT_MODE (TF, 16, ieee_quad_format);
  27
  28 /* Add any extra modes needed to represent the condition code.  */
  29
  30 /*
  31
  32 Condition Codes
  33
  34 Check for zero
  35
  36 CCZ:  EQ          NE           NE          NE
  37 CCZ1: EQ          NE                                  (CS)
  38
  39 Unsigned compares
  40
  41 CCU:  EQ          LTU          GTU         NE         (CLG/R, CL/R/Y, CLM/Y, CLI/Y)
  42 CCUR: EQ          GTU          LTU         NE         (CLGF/R)
  43
  44 Signed compares
  45
  46 CCS:  EQ          LT           GT          UNORDERED  (LTGFR, LTGR, LTR, ICM/Y,
  47                                                        LTDBR, LTDR, LTEBR, LTER,
  48                                                        CG/R, C/R/Y, CGHI, CHI,
  49                                                        CDB/R, CD/R, CEB/R, CE/R,
  50                                                        ADB/R, AEB/R, SDB/R, SEB/R,
  51                                                        SRAG, SRA, SRDA)
  52 CCSR: EQ          GT           LT          UNORDERED  (CGF/R, CH/Y)
  53
  54 Condition codes resulting from add with overflow
  55
  56 CCA:  EQ          LT           GT          Overflow
  57 CCAP: EQ          LT           GT          LT         (AGHI, AHI)
  58 CCAN: EQ          LT           GT          GT         (AGHI, AHI)
  59
  60 Condition codes of unsigned adds and subs
  61
  62 CCL:  EQ          NE           EQ          NE         (ALGF/R, ALG/R, AL/R/Y,
  63                                                        ALCG/R, ALC/R,
  64                                                        SLGF/R, SLG/R, SL/R/Y,
  65                                                        SLBG/R, SLB/R)
  66 CCL1: GEU         GEU          LTU         LTU        (ALG/R, AL/R/Y)
  67 CCL2: GTU         GTU          LEU         LEU        (SLG/R, SL/R/Y)
  68 CCL3: EQ          LTU          EQ          GTU        (SLG/R, SL/R/Y)
  69
  70 Test under mask checks
  71
  72 CCT:  EQ          NE           NE          NE         (ICM/Y, TML, CG/R, CGHI,
  73                                                        C/R/Y, CHI, NG/R, N/R/Y,
  74                                                        OG/R, O/R/Y, XG/R, X/R/Y)
  75 CCT1: NE          EQ           NE          NE         (TMH, TML)
  76 CCT2: NE          NE           EQ          NE         (TMH, TML)
  77 CCT3: NE          NE           NE          EQ         (TMH, TML)
  78
  79 CCA and CCT modes are request only modes. These modes are never returned by
  80 s390_select_cc_mode. They are only intended to match other modes.
  81
  82 Requested mode            -> Destination CC register mode
  83
  84 CCS, CCU, CCT, CCSR, CCUR -> CCZ
  85 CCA                       -> CCAP, CCAN
  86
  87
  88
  89 *** Comments ***
  90
  91 CCAP, CCAN
  92
  93 The CC obtained from add instruction usually can't be used for comparisons
  94 because its coupling with overflow flag. In case of an overflow the
  95 less than/greater than data are lost. Nevertheless a comparison can be done
  96 whenever immediate values are involved because they are known at compile time.
  97 If you know whether the used constant is positive or negative you can predict
  98 the sign of the result even in case of an overflow.
  99
 100
 101 CCT, CCT1, CCT2, CCT3
 102
 103 If bits of an integer masked with an AND instruction are checked, the test under
 104 mask instructions turn out to be very handy for a set of special cases.
 105 The simple cases are checks whether all masked bits are zero or ones:
 106
 107   int a;
 108   if ((a & (16 + 128)) == 0)          -> CCT/CCZ
 109   if ((a & (16 + 128)) == 16 + 128)   -> CCT3
 110
 111 Using two extra modes makes it possible to do complete checks on two bits of an
 112 integer (This is possible on register operands only. TM does not provide the
 113 information necessary for CCT1 and CCT2 modes.):
 114
 115   int a;
 116   if ((a & (16 + 128)) == 16)         -> CCT1
 117   if ((a & (16 + 128)) == 128)        -> CCT2
 118
 119
 120 CCSR, CCUR
 121
 122 There are several instructions comparing 32 bit with 64-bit unsigned/signed
 123 values. Such instructions can be considered to have a builtin zero/sign_extend.
 124 The problem is that in the RTL (to be canonical) the zero/sign extended operand
 125 has to be the first one but the machine instructions like it the other way
 126 around. The following both modes can be considered as CCS and CCU modes with
 127 exchanged operands.
 128
 129
 130 CCL1, CCL2
 131
 132 These modes represent the result of overflow checks.
 133
 134 if (a + b < a) -> CCL1 state of the carry bit   (CC2 | CC3)
 135 if (a - b > a) -> CCL2 state of the borrow bit  (CC0 | CC1)
 136
 137 They are used when multi word numbers are computed dealing one SImode part after
 138 another or whenever manual overflow checks like the examples above are
 139 compiled.
 140
 141
 142 CCL3
 143
 144 A logical subtract instruction sets the borrow bit in case of an overflow.
 145 The resulting condition code of those instructions is represented by the
 146 CCL3 mode. Together with the CCU mode this mode is used for jumpless
 147 implementations of several if-constructs - see s390_expand_addcc for more
 148 details.
 149
 150 CCZ1
 151
 152 The compare and swap instructions sets the condition code to 0/1 if the
 153 operands were equal/unequal. The CCZ1 mode ensures the result can be
 154 effectively placed into a register.
 155
 156 CCVIH, CCVIHU, CCVFH, CCVFHE
 157
 158 These are condition code modes used in instructions setting the
 159 condition code.  The mode determines which comparison to perform (H -
 160 high, HU - high unsigned, HE - high or equal) and whether it is a
 161 floating point comparison or not (I - int, F - float).
 162
 163 The comparison operation to be performed needs to be encoded into the
 164 condition code mode since the comparison operator is not available in
 165 compare style patterns (set cc (compare (op0) (op1))).  So the
 166 condition code mode is the only information to determine the
 167 instruction to be used.
 168
 169 CCVIALL, CCVIANY, CCVFALL, CCVFANY
 170
 171 These modes are used in instructions reading the condition code.
 172 Opposed to the CC producer patterns the comparison operator is
 173 available.  Hence the comparison operation does not need to be part of
 174 the CC mode.  However, we still need to know whether CC has been
 175 generated by a float or an integer comparison in order to be able to
 176 invert the condition correctly (int: GT -> LE, float: GT -> UNLE).
 177
 178 The ALL and ANY variants differ only in the usage of CC1 which
 179 indicates a mixed result across the vector elements.  Be aware that
 180 depending on the comparison code the ALL and ANY variants might
 181 actually refer to their opposite meaning.  I.e. while inverting the
 182 comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE
 183 (reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison
 184 (inverting "all equal" should be "any not equal") However, the
 185 middle-end does invert only the comparison operator without touching
 186 the mode.
 187 Hence, the ALL/ANY in the mode names refer to the meaning in the
 188 context of EQ, GT, GE while for the inverted codes it actually means
 189 ANY/ALL.
 190
 191 CCRAW
 192
 193 The cc mode generated by a non-compare instruction.  The condition
 194 code mask for the CC consumer is determined by the comparison operator
 195 (only EQ and NE allowed) and the immediate value given as second
 196 operand to the operator.  For the other CC modes this value used to be
 197 0.
 198
 199 */
 200
 201
 202 CC_MODE (CCZ);
 203 CC_MODE (CCZ1);
 204 CC_MODE (CCA);
 205 CC_MODE (CCAP);
 206 CC_MODE (CCAN);
 207 CC_MODE (CCL);
 208 CC_MODE (CCL1);
 209 CC_MODE (CCL2);
 210 CC_MODE (CCL3);
 211 CC_MODE (CCU);
 212 CC_MODE (CCUR);
 213 CC_MODE (CCS);
 214 CC_MODE (CCSR);
 215 CC_MODE (CCT);
 216 CC_MODE (CCT1);
 217 CC_MODE (CCT2);
 218 CC_MODE (CCT3);
 219 CC_MODE (CCRAW);
 220
 221 CC_MODE (CCVEQ);
 222
 223 CC_MODE (CCVIH);
 224 CC_MODE (CCVIHU);
 225
 226 CC_MODE (CCVFH);
 227 CC_MODE (CCVFHE);
 228
 229 CC_MODE (CCVIALL);
 230 CC_MODE (CCVIANY);
 231
 232 CC_MODE (CCVFALL);
 233 CC_MODE (CCVFANY);
 234
 235 /* Vector modes.  */
 236
 237 VECTOR_MODES (INT, 2);        /*                 V2QI */
 238 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
 239 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
 240 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
 241
 242 VECTOR_MODE (FLOAT, SF, 2);   /* V2SF */
 243 VECTOR_MODE (FLOAT, SF, 4);   /* V4SF */
 244 VECTOR_MODE (FLOAT, DF, 2);   /* V2DF */
 245
 246 VECTOR_MODE (INT, QI, 1);     /* V1QI */
 247 VECTOR_MODE (INT, HI, 1);     /* V1HI */
 248 VECTOR_MODE (INT, SI, 1);     /* V1SI */
 249 VECTOR_MODE (INT, DI, 1);     /* V1DI */
 250 VECTOR_MODE (INT, TI, 1);     /* V1TI */
 251
 252 VECTOR_MODE (FLOAT, SF, 1);   /* V1SF */
 253 VECTOR_MODE (FLOAT, DF, 1);   /* V1DF */
 254 VECTOR_MODE (FLOAT, TF, 1);   /* V1TF */