gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify it under
   8 the terms of the GNU General Public License as published by the Free
   9 Software Foundation; either version 2, or (at your option) any later
  10 version.
  11
  12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  15 for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING.  If not, write to the Free
  19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
  20 02110-1301, USA.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information created by
  53    flow.c aren't completely updated:
  54
  55    - reg_live_length is not updated
  56    - reg_n_refs is not adjusted in the rare case when a register is
  57      no longer required in a computation
  58    - there are extremely rare cases (see distribute_notes) when a
  59      REG_DEAD note is lost
  60    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  61      removed because there is no way to know which register it was
  62      linking
  63
  64    To simplify substitution, we combine only when the earlier insn(s)
  65    consist of only a single assignment.  To simplify updating afterward,
  66    we never combine when a subroutine call appears in the middle.
  67
  68    Since we do not represent assignments to CC0 explicitly except when that
  69    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  70    the condition code for the insn that set the condition code.
  71    Fortunately, these two insns must be consecutive.
  72    Therefore, every JUMP_INSN is taken to have an implicit logical link
  73    to the preceding insn.  This is not quite right, since non-jumps can
  74    also use the condition code; but in practice such insns would not
  75    combine anyway.  */
  76
  77 #include "config.h"
  78 #include "system.h"
  79 #include "coretypes.h"
  80 #include "tm.h"
  81 #include "rtl.h"
  82 #include "tree.h"
  83 #include "tm_p.h"
  84 #include "flags.h"
  85 #include "regs.h"
  86 #include "hard-reg-set.h"
  87 #include "basic-block.h"
  88 #include "insn-config.h"
  89 #include "function.h"
  90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  91 #include "expr.h"
  92 #include "insn-attr.h"
  93 #include "recog.h"
  94 #include "real.h"
  95 #include "toplev.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105
 106 /* Number of attempts to combine instructions in this function.  */
 107
 108 static int combine_attempts;
 109
 110 /* Number of attempts that got as far as substitution in this function.  */
 111
 112 static int combine_merges;
 113
 114 /* Number of instructions combined with added SETs in this function.  */
 115
 116 static int combine_extras;
 117
 118 /* Number of instructions combined in this function.  */
 119
 120 static int combine_successes;
 121
 122 /* Totals over entire compilation.  */
 123
 124 static int total_attempts, total_merges, total_extras, total_successes;
 125
 126 \f
 127 /* Vector mapping INSN_UIDs to cuids.
 128    The cuids are like uids but increase monotonically always.
 129    Combine always uses cuids so that it can compare them.
 130    But actually renumbering the uids, which we used to do,
 131    proves to be a bad idea because it makes it hard to compare
 132    the dumps produced by earlier passes with those from later passes.  */
 133
 134 static int *uid_cuid;
 135 static int max_uid_cuid;
 136
 137 /* Get the cuid of an insn.  */
 138
 139 #define INSN_CUID(INSN) \
 140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
 141
 142 /* Maximum register number, which is the size of the tables below.  */
 143
 144 static unsigned int combine_max_regno;
 145
 146 struct reg_stat {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 };
 254
 255 static struct reg_stat *reg_stat;
 256
 257 /* Record the cuid of the last insn that invalidated memory
 258    (anything that writes memory, and subroutine calls, but not pushes).  */
 259
 260 static int mem_last_set;
 261
 262 /* Record the cuid of the last CALL_INSN
 263    so we can tell whether a potential combination crosses any calls.  */
 264
 265 static int last_call_cuid;
 266
 267 /* When `subst' is called, this is the insn that is being modified
 268    (by combining in a previous insn).  The PATTERN of this insn
 269    is still the old pattern partially modified and it should not be
 270    looked at, but this may be used to examine the successors of the insn
 271    to judge whether a simplification is valid.  */
 272
 273 static rtx subst_insn;
 274
 275 /* This is the lowest CUID that `subst' is currently dealing with.
 276    get_last_value will not return a value if the register was set at or
 277    after this CUID.  If not for this mechanism, we could get confused if
 278    I2 or I1 in try_combine were an insn that used the old value of a register
 279    to obtain a new value.  In that case, we might erroneously get the
 280    new value of the register when we wanted the old one.  */
 281
 282 static int subst_low_cuid;
 283
 284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 285    must consider all these registers to be always live.  */
 286
 287 static HARD_REG_SET newpat_used_regs;
 288
 289 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 290    insn is the earlier than I2 or I3, combine should rescan starting at
 291    that location.  */
 292
 293 static rtx added_links_insn;
 294
 295 /* Basic block in which we are performing combines.  */
 296 static basic_block this_basic_block;
 297
 298 /* A bitmap indicating which blocks had registers go dead at entry.
 299    After combine, we'll need to re-do global life analysis with
 300    those blocks as starting points.  */
 301 static sbitmap refresh_blocks;
 302 \f
 303 /* The following array records the insn_rtx_cost for every insn
 304    in the instruction stream.  */
 305
 306 static int *uid_insn_cost;
 307
 308 /* Length of the currently allocated uid_insn_cost array.  */
 309
 310 static int last_insn_cost;
 311
 312 /* Incremented for each label.  */
 313
 314 static int label_tick;
 315
 316 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 317    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 318
 319 static enum machine_mode nonzero_bits_mode;
 320
 321 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 322    be safely used.  It is zero while computing them and after combine has
 323    completed.  This former test prevents propagating values based on
 324    previously set values, which can be incorrect if a variable is modified
 325    in a loop.  */
 326
 327 static int nonzero_sign_valid;
 328
 329 \f
 330 /* Record one modification to rtl structure
 331    to be undone by storing old_contents into *where.  */
 332
 333 struct undo
 334 {
 335   struct undo *next;
 336   enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
 337   union { rtx r; int i; enum machine_mode m; } old_contents;
 338   union { rtx *r; int *i; } where;
 339 };
 340
 341 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 342    num_undo says how many are currently recorded.
 343
 344    other_insn is nonzero if we have modified some other insn in the process
 345    of working on subst_insn.  It must be verified too.  */
 346
 347 struct undobuf
 348 {
 349   struct undo *undos;
 350   struct undo *frees;
 351   rtx other_insn;
 352 };
 353
 354 static struct undobuf undobuf;
 355
 356 /* Number of times the pseudo being substituted for
 357    was found and replaced.  */
 358
 359 static int n_occurrences;
 360
 361 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
 362                                          enum machine_mode,
 363                                          unsigned HOST_WIDE_INT,
 364                                          unsigned HOST_WIDE_INT *);
 365 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
 366                                                 enum machine_mode,
 367                                                 unsigned int, unsigned int *);
 368 static void do_SUBST (rtx *, rtx);
 369 static void do_SUBST_INT (int *, int);
 370 static void init_reg_last (void);
 371 static void setup_incoming_promotions (void);
 372 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
 373 static int cant_combine_insn_p (rtx);
 374 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
 375 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
 376 static int contains_muldiv (rtx);
 377 static rtx try_combine (rtx, rtx, rtx, int *);
 378 static void undo_all (void);
 379 static void undo_commit (void);
 380 static rtx *find_split_point (rtx *, rtx);
 381 static rtx subst (rtx, rtx, rtx, int, int);
 382 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
 383 static rtx simplify_if_then_else (rtx);
 384 static rtx simplify_set (rtx);
 385 static rtx simplify_logical (rtx);
 386 static rtx expand_compound_operation (rtx);
 387 static rtx expand_field_assignment (rtx);
 388 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 389                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 390 static rtx extract_left_shift (rtx, int);
 391 static rtx make_compound_operation (rtx, enum rtx_code);
 392 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 393                               unsigned HOST_WIDE_INT *);
 394 static rtx canon_reg_for_combine (rtx, rtx);
 395 static rtx force_to_mode (rtx, enum machine_mode,
 396                           unsigned HOST_WIDE_INT, int);
 397 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 398 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 399 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 400 static rtx make_field_assignment (rtx);
 401 static rtx apply_distributive_law (rtx);
 402 static rtx distribute_and_simplify_rtx (rtx, int);
 403 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 404                                      unsigned HOST_WIDE_INT);
 405 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 406                                    unsigned HOST_WIDE_INT);
 407 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 408                             HOST_WIDE_INT, enum machine_mode, int *);
 409 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 410 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 411                                  int);
 412 static int recog_for_combine (rtx *, rtx, rtx *);
 413 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 414 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 415 static void update_table_tick (rtx);
 416 static void record_value_for_reg (rtx, rtx, rtx);
 417 static void check_conversions (rtx, rtx);
 418 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
 419 static void record_dead_and_set_regs (rtx);
 420 static int get_last_value_validate (rtx *, rtx, int, int);
 421 static rtx get_last_value (rtx);
 422 static int use_crosses_set_p (rtx, int);
 423 static void reg_dead_at_p_1 (rtx, rtx, void *);
 424 static int reg_dead_at_p (rtx, rtx);
 425 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 426 static int reg_bitfield_target_p (rtx, rtx);
 427 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
 428 static void distribute_links (rtx);
 429 static void mark_used_regs_combine (rtx);
 430 static int insn_cuid (rtx);
 431 static void record_promoted_value (rtx, rtx);
 432 static int unmentioned_reg_p_1 (rtx *, void *);
 433 static bool unmentioned_reg_p (rtx, rtx);
 434 static void record_truncated_value (rtx);
 435 static bool reg_truncated_to_mode (enum machine_mode, rtx);
 436 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 437 \f
 438
 439 /* It is not safe to use ordinary gen_lowpart in combine.
 440    See comments in gen_lowpart_for_combine.  */
 441 #undef RTL_HOOKS_GEN_LOWPART
 442 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 443
 444 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 445 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 446 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 447
 448 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 449 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 450
 451 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 452 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 453
 454 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 455 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 456
 457 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 458
 459 \f
 460 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 461    insn.  The substitution can be undone by undo_all.  If INTO is already
 462    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 463    also call SUBST, we have to compute it before we put anything into
 464    the undo table.  */
 465
 466 static void
 467 do_SUBST (rtx *into, rtx newval)
 468 {
 469   struct undo *buf;
 470   rtx oldval = *into;
 471
 472   if (oldval == newval)
 473     return;
 474
 475   /* We'd like to catch as many invalid transformations here as
 476      possible.  Unfortunately, there are way too many mode changes
 477      that are perfectly valid, so we'd waste too much effort for
 478      little gain doing the checks here.  Focus on catching invalid
 479      transformations involving integer constants.  */
 480   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 481       && GET_CODE (newval) == CONST_INT)
 482     {
 483       /* Sanity check that we're replacing oldval with a CONST_INT
 484          that is a valid sign-extension for the original mode.  */
 485       gcc_assert (INTVAL (newval)
 486                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 487
 488       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 489          CONST_INT is not valid, because after the replacement, the
 490          original mode would be gone.  Unfortunately, we can't tell
 491          when do_SUBST is called to replace the operand thereof, so we
 492          perform this test on oldval instead, checking whether an
 493          invalid replacement took place before we got here.  */
 494       gcc_assert (!(GET_CODE (oldval) == SUBREG
 495                     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
 496       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 497                     && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
 498     }
 499
 500   if (undobuf.frees)
 501     buf = undobuf.frees, undobuf.frees = buf->next;
 502   else
 503     buf = XNEW (struct undo);
 504
 505   buf->kind = UNDO_RTX;
 506   buf->where.r = into;
 507   buf->old_contents.r = oldval;
 508   *into = newval;
 509
 510   buf->next = undobuf.undos, undobuf.undos = buf;
 511 }
 512
 513 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 514
 515 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 516    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 517    not safe.  */
 518
 519 static void
 520 do_SUBST_INT (int *into, int newval)
 521 {
 522   struct undo *buf;
 523   int oldval = *into;
 524
 525   if (oldval == newval)
 526     return;
 527
 528   if (undobuf.frees)
 529     buf = undobuf.frees, undobuf.frees = buf->next;
 530   else
 531     buf = XNEW (struct undo);
 532
 533   buf->kind = UNDO_INT;
 534   buf->where.i = into;
 535   buf->old_contents.i = oldval;
 536   *into = newval;
 537
 538   buf->next = undobuf.undos, undobuf.undos = buf;
 539 }
 540
 541 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 542
 543 /* Similar to SUBST, but just substitute the mode.  This is used when
 544    changing the mode of a pseudo-register, so that any other
 545    references to the entry in the regno_reg_rtx array will change as
 546    well.  */
 547
 548 static void
 549 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 550 {
 551   struct undo *buf;
 552   enum machine_mode oldval = GET_MODE (*into);
 553
 554   if (oldval == newval)
 555     return;
 556
 557   if (undobuf.frees)
 558     buf = undobuf.frees, undobuf.frees = buf->next;
 559   else
 560     buf = XNEW (struct undo);
 561
 562   buf->kind = UNDO_MODE;
 563   buf->where.r = into;
 564   buf->old_contents.m = oldval;
 565   PUT_MODE (*into, newval);
 566
 567   buf->next = undobuf.undos, undobuf.undos = buf;
 568 }
 569
 570 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 571 \f
 572 /* Subroutine of try_combine.  Determine whether the combine replacement
 573    patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
 574    that the original instruction sequence I1, I2 and I3.  Note that I1
 575    and/or NEWI2PAT may be NULL_RTX.  This function returns false, if the
 576    costs of all instructions can be estimated, and the replacements are
 577    more expensive than the original sequence.  */
 578
 579 static bool
 580 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
 581 {
 582   int i1_cost, i2_cost, i3_cost;
 583   int new_i2_cost, new_i3_cost;
 584   int old_cost, new_cost;
 585
 586   /* Lookup the original insn_rtx_costs.  */
 587   i2_cost = INSN_UID (i2) <= last_insn_cost
 588             ? uid_insn_cost[INSN_UID (i2)] : 0;
 589   i3_cost = INSN_UID (i3) <= last_insn_cost
 590             ? uid_insn_cost[INSN_UID (i3)] : 0;
 591
 592   if (i1)
 593     {
 594       i1_cost = INSN_UID (i1) <= last_insn_cost
 595                 ? uid_insn_cost[INSN_UID (i1)] : 0;
 596       old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
 597                  ? i1_cost + i2_cost + i3_cost : 0;
 598     }
 599   else
 600     {
 601       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 602       i1_cost = 0;
 603     }
 604
 605   /* Calculate the replacement insn_rtx_costs.  */
 606   new_i3_cost = insn_rtx_cost (newpat);
 607   if (newi2pat)
 608     {
 609       new_i2_cost = insn_rtx_cost (newi2pat);
 610       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 611                  ? new_i2_cost + new_i3_cost : 0;
 612     }
 613   else
 614     {
 615       new_cost = new_i3_cost;
 616       new_i2_cost = 0;
 617     }
 618
 619   if (undobuf.other_insn)
 620     {
 621       int old_other_cost, new_other_cost;
 622
 623       old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
 624                         ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
 625       new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
 626       if (old_other_cost > 0 && new_other_cost > 0)
 627         {
 628           old_cost += old_other_cost;
 629           new_cost += new_other_cost;
 630         }
 631       else
 632         old_cost = 0;
 633     }
 634
 635   /* Disallow this recombination if both new_cost and old_cost are
 636      greater than zero, and new_cost is greater than old cost.  */
 637   if (old_cost > 0
 638       && new_cost > old_cost)
 639     {
 640       if (dump_file)
 641         {
 642           if (i1)
 643             {
 644               fprintf (dump_file,
 645                        "rejecting combination of insns %d, %d and %d\n",
 646                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 647               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 648                        i1_cost, i2_cost, i3_cost, old_cost);
 649             }
 650           else
 651             {
 652               fprintf (dump_file,
 653                        "rejecting combination of insns %d and %d\n",
 654                        INSN_UID (i2), INSN_UID (i3));
 655               fprintf (dump_file, "original costs %d + %d = %d\n",
 656                        i2_cost, i3_cost, old_cost);
 657             }
 658
 659           if (newi2pat)
 660             {
 661               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 662                        new_i2_cost, new_i3_cost, new_cost);
 663             }
 664           else
 665             fprintf (dump_file, "replacement cost %d\n", new_cost);
 666         }
 667
 668       return false;
 669     }
 670
 671   /* Update the uid_insn_cost array with the replacement costs.  */
 672   uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
 673   uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
 674   if (i1)
 675     uid_insn_cost[INSN_UID (i1)] = 0;
 676
 677   return true;
 678 }
 679 \f
 680 /* Main entry point for combiner.  F is the first insn of the function.
 681    NREGS is the first unused pseudo-reg number.
 682
 683    Return nonzero if the combiner has turned an indirect jump
 684    instruction into a direct jump.  */
 685 static int
 686 combine_instructions (rtx f, unsigned int nregs)
 687 {
 688   rtx insn, next;
 689 #ifdef HAVE_cc0
 690   rtx prev;
 691 #endif
 692   int i;
 693   unsigned int j = 0;
 694   rtx links, nextlinks;
 695   sbitmap_iterator sbi;
 696
 697   int new_direct_jump_p = 0;
 698
 699   combine_attempts = 0;
 700   combine_merges = 0;
 701   combine_extras = 0;
 702   combine_successes = 0;
 703
 704   combine_max_regno = nregs;
 705
 706   rtl_hooks = combine_rtl_hooks;
 707
 708   reg_stat = XCNEWVEC (struct reg_stat, nregs);
 709
 710   init_recog_no_volatile ();
 711
 712   /* Compute maximum uid value so uid_cuid can be allocated.  */
 713
 714   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 715     if (INSN_UID (insn) > i)
 716       i = INSN_UID (insn);
 717
 718   uid_cuid = XNEWVEC (int, i + 1);
 719   max_uid_cuid = i;
 720
 721   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
 722
 723   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
 724      problems when, for example, we have j <<= 1 in a loop.  */
 725
 726   nonzero_sign_valid = 0;
 727
 728   /* Compute the mapping from uids to cuids.
 729      Cuids are numbers assigned to insns, like uids,
 730      except that cuids increase monotonically through the code.
 731
 732      Scan all SETs and see if we can deduce anything about what
 733      bits are known to be zero for some registers and how many copies
 734      of the sign bit are known to exist for those registers.
 735
 736      Also set any known values so that we can use it while searching
 737      for what bits are known to be set.  */
 738
 739   label_tick = 1;
 740
 741   setup_incoming_promotions ();
 742
 743   refresh_blocks = sbitmap_alloc (last_basic_block);
 744   sbitmap_zero (refresh_blocks);
 745
 746   /* Allocate array of current insn_rtx_costs.  */
 747   uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
 748   last_insn_cost = max_uid_cuid;
 749
 750   for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
 751     {
 752       uid_cuid[INSN_UID (insn)] = ++i;
 753       subst_low_cuid = i;
 754       subst_insn = insn;
 755
 756       if (INSN_P (insn))
 757         {
 758           note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
 759                        NULL);
 760           record_dead_and_set_regs (insn);
 761
 762 #ifdef AUTO_INC_DEC
 763           for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 764             if (REG_NOTE_KIND (links) == REG_INC)
 765               set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 766                                                 NULL);
 767 #endif
 768
 769           /* Record the current insn_rtx_cost of this instruction.  */
 770           if (NONJUMP_INSN_P (insn))
 771             uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
 772           if (dump_file)
 773             fprintf(dump_file, "insn_cost %d: %d\n",
 774                     INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
 775         }
 776
 777       if (LABEL_P (insn))
 778         label_tick++;
 779     }
 780
 781   nonzero_sign_valid = 1;
 782
 783   /* Now scan all the insns in forward order.  */
 784
 785   label_tick = 1;
 786   last_call_cuid = 0;
 787   mem_last_set = 0;
 788   init_reg_last ();
 789   setup_incoming_promotions ();
 790
 791   FOR_EACH_BB (this_basic_block)
 792     {
 793       for (insn = BB_HEAD (this_basic_block);
 794            insn != NEXT_INSN (BB_END (this_basic_block));
 795            insn = next ? next : NEXT_INSN (insn))
 796         {
 797           next = 0;
 798
 799           if (LABEL_P (insn))
 800             label_tick++;
 801
 802           else if (INSN_P (insn))
 803             {
 804               /* See if we know about function return values before this
 805                  insn based upon SUBREG flags.  */
 806               check_conversions (insn, PATTERN (insn));
 807
 808               /* Try this insn with each insn it links back to.  */
 809
 810               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 811                 if ((next = try_combine (insn, XEXP (links, 0),
 812                                          NULL_RTX, &new_direct_jump_p)) != 0)
 813                   goto retry;
 814
 815               /* Try each sequence of three linked insns ending with this one.  */
 816
 817               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 818                 {
 819                   rtx link = XEXP (links, 0);
 820
 821                   /* If the linked insn has been replaced by a note, then there
 822                      is no point in pursuing this chain any further.  */
 823                   if (NOTE_P (link))
 824                     continue;
 825
 826                   for (nextlinks = LOG_LINKS (link);
 827                        nextlinks;
 828                        nextlinks = XEXP (nextlinks, 1))
 829                     if ((next = try_combine (insn, link,
 830                                              XEXP (nextlinks, 0),
 831                                              &new_direct_jump_p)) != 0)
 832                       goto retry;
 833                 }
 834
 835 #ifdef HAVE_cc0
 836               /* Try to combine a jump insn that uses CC0
 837                  with a preceding insn that sets CC0, and maybe with its
 838                  logical predecessor as well.
 839                  This is how we make decrement-and-branch insns.
 840                  We need this special code because data flow connections
 841                  via CC0 do not get entered in LOG_LINKS.  */
 842
 843               if (JUMP_P (insn)
 844                   && (prev = prev_nonnote_insn (insn)) != 0
 845                   && NONJUMP_INSN_P (prev)
 846                   && sets_cc0_p (PATTERN (prev)))
 847                 {
 848                   if ((next = try_combine (insn, prev,
 849                                            NULL_RTX, &new_direct_jump_p)) != 0)
 850                     goto retry;
 851
 852                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 853                        nextlinks = XEXP (nextlinks, 1))
 854                     if ((next = try_combine (insn, prev,
 855                                              XEXP (nextlinks, 0),
 856                                              &new_direct_jump_p)) != 0)
 857                       goto retry;
 858                 }
 859
 860               /* Do the same for an insn that explicitly references CC0.  */
 861               if (NONJUMP_INSN_P (insn)
 862                   && (prev = prev_nonnote_insn (insn)) != 0
 863                   && NONJUMP_INSN_P (prev)
 864                   && sets_cc0_p (PATTERN (prev))
 865                   && GET_CODE (PATTERN (insn)) == SET
 866                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
 867                 {
 868                   if ((next = try_combine (insn, prev,
 869                                            NULL_RTX, &new_direct_jump_p)) != 0)
 870                     goto retry;
 871
 872                   for (nextlinks = LOG_LINKS (prev); nextlinks;
 873                        nextlinks = XEXP (nextlinks, 1))
 874                     if ((next = try_combine (insn, prev,
 875                                              XEXP (nextlinks, 0),
 876                                              &new_direct_jump_p)) != 0)
 877                       goto retry;
 878                 }
 879
 880               /* Finally, see if any of the insns that this insn links to
 881                  explicitly references CC0.  If so, try this insn, that insn,
 882                  and its predecessor if it sets CC0.  */
 883               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 884                 if (NONJUMP_INSN_P (XEXP (links, 0))
 885                     && GET_CODE (PATTERN (XEXP (links, 0))) == SET
 886                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
 887                     && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
 888                     && NONJUMP_INSN_P (prev)
 889                     && sets_cc0_p (PATTERN (prev))
 890                     && (next = try_combine (insn, XEXP (links, 0),
 891                                             prev, &new_direct_jump_p)) != 0)
 892                   goto retry;
 893 #endif
 894
 895               /* Try combining an insn with two different insns whose results it
 896                  uses.  */
 897               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 898                 for (nextlinks = XEXP (links, 1); nextlinks;
 899                      nextlinks = XEXP (nextlinks, 1))
 900                   if ((next = try_combine (insn, XEXP (links, 0),
 901                                            XEXP (nextlinks, 0),
 902                                            &new_direct_jump_p)) != 0)
 903                     goto retry;
 904
 905               /* Try this insn with each REG_EQUAL note it links back to.  */
 906               for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
 907                 {
 908                   rtx set, note;
 909                   rtx temp = XEXP (links, 0);
 910                   if ((set = single_set (temp)) != 0
 911                       && (note = find_reg_equal_equiv_note (temp)) != 0
 912                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
 913                       /* Avoid using a register that may already been marked
 914                          dead by an earlier instruction.  */
 915                       && ! unmentioned_reg_p (note, SET_SRC (set))
 916                       && (GET_MODE (note) == VOIDmode
 917                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
 918                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
 919                     {
 920                       /* Temporarily replace the set's source with the
 921                          contents of the REG_EQUAL note.  The insn will
 922                          be deleted or recognized by try_combine.  */
 923                       rtx orig = SET_SRC (set);
 924                       SET_SRC (set) = note;
 925                       next = try_combine (insn, temp, NULL_RTX,
 926                                           &new_direct_jump_p);
 927                       if (next)
 928                         goto retry;
 929                       SET_SRC (set) = orig;
 930                     }
 931                 }
 932
 933               if (!NOTE_P (insn))
 934                 record_dead_and_set_regs (insn);
 935
 936             retry:
 937               ;
 938             }
 939         }
 940     }
 941   clear_bb_flags ();
 942
 943   EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
 944     BASIC_BLOCK (j)->flags |= BB_DIRTY;
 945   new_direct_jump_p |= purge_all_dead_edges ();
 946   delete_noop_moves ();
 947
 948   update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
 949                                     PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
 950                                     | PROP_KILL_DEAD_CODE);
 951
 952   /* Clean up.  */
 953   sbitmap_free (refresh_blocks);
 954   free (uid_insn_cost);
 955   free (reg_stat);
 956   free (uid_cuid);
 957
 958   {
 959     struct undo *undo, *next;
 960     for (undo = undobuf.frees; undo; undo = next)
 961       {
 962         next = undo->next;
 963         free (undo);
 964       }
 965     undobuf.frees = 0;
 966   }
 967
 968   total_attempts += combine_attempts;
 969   total_merges += combine_merges;
 970   total_extras += combine_extras;
 971   total_successes += combine_successes;
 972
 973   nonzero_sign_valid = 0;
 974   rtl_hooks = general_rtl_hooks;
 975
 976   /* Make recognizer allow volatile MEMs again.  */
 977   init_recog ();
 978
 979   return new_direct_jump_p;
 980 }
 981
 982 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
 983
 984 static void
 985 init_reg_last (void)
 986 {
 987   unsigned int i;
 988   for (i = 0; i < combine_max_regno; i++)
 989     memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
 990 }
 991 \f
 992 /* Set up any promoted values for incoming argument registers.  */
 993
 994 static void
 995 setup_incoming_promotions (void)
 996 {
 997   unsigned int regno;
 998   rtx reg;
 999   enum machine_mode mode;
1000   int unsignedp;
1001   rtx first = get_insns ();
1002
1003   if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1004     {
1005       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1006         /* Check whether this register can hold an incoming pointer
1007            argument.  FUNCTION_ARG_REGNO_P tests outgoing register
1008            numbers, so translate if necessary due to register windows.  */
1009         if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1010             && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1011           {
1012             record_value_for_reg
1013               (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1014                                            : SIGN_EXTEND),
1015                                           GET_MODE (reg),
1016                                           gen_rtx_CLOBBER (mode, const0_rtx)));
1017           }
1018     }
1019 }
1020 \f
1021 /* Called via note_stores.  If X is a pseudo that is narrower than
1022    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1023
1024    If we are setting only a portion of X and we can't figure out what
1025    portion, assume all bits will be used since we don't know what will
1026    be happening.
1027
1028    Similarly, set how many bits of X are known to be copies of the sign bit
1029    at all locations in the function.  This is the smallest number implied
1030    by any set of X.  */
1031
1032 static void
1033 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1034                                   void *data ATTRIBUTE_UNUSED)
1035 {
1036   unsigned int num;
1037
1038   if (REG_P (x)
1039       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1040       /* If this register is undefined at the start of the file, we can't
1041          say what its contents were.  */
1042       && ! REGNO_REG_SET_P
1043          (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1044       && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1045     {
1046       if (set == 0 || GET_CODE (set) == CLOBBER)
1047         {
1048           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1049           reg_stat[REGNO (x)].sign_bit_copies = 1;
1050           return;
1051         }
1052
1053       /* If this is a complex assignment, see if we can convert it into a
1054          simple assignment.  */
1055       set = expand_field_assignment (set);
1056
1057       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1058          set what we know about X.  */
1059
1060       if (SET_DEST (set) == x
1061           || (GET_CODE (SET_DEST (set)) == SUBREG
1062               && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1063                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1064               && SUBREG_REG (SET_DEST (set)) == x))
1065         {
1066           rtx src = SET_SRC (set);
1067
1068 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1069           /* If X is narrower than a word and SRC is a non-negative
1070              constant that would appear negative in the mode of X,
1071              sign-extend it for use in reg_stat[].nonzero_bits because some
1072              machines (maybe most) will actually do the sign-extension
1073              and this is the conservative approach.
1074
1075              ??? For 2.5, try to tighten up the MD files in this regard
1076              instead of this kludge.  */
1077
1078           if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1079               && GET_CODE (src) == CONST_INT
1080               && INTVAL (src) > 0
1081               && 0 != (INTVAL (src)
1082                        & ((HOST_WIDE_INT) 1
1083                           << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1084             src = GEN_INT (INTVAL (src)
1085                            | ((HOST_WIDE_INT) (-1)
1086                               << GET_MODE_BITSIZE (GET_MODE (x))));
1087 #endif
1088
1089           /* Don't call nonzero_bits if it cannot change anything.  */
1090           if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1091             reg_stat[REGNO (x)].nonzero_bits
1092               |= nonzero_bits (src, nonzero_bits_mode);
1093           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1094           if (reg_stat[REGNO (x)].sign_bit_copies == 0
1095               || reg_stat[REGNO (x)].sign_bit_copies > num)
1096             reg_stat[REGNO (x)].sign_bit_copies = num;
1097         }
1098       else
1099         {
1100           reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1101           reg_stat[REGNO (x)].sign_bit_copies = 1;
1102         }
1103     }
1104 }
1105 \f
1106 /* See if INSN can be combined into I3.  PRED and SUCC are optionally
1107    insns that were previously combined into I3 or that will be combined
1108    into the merger of INSN and I3.
1109
1110    Return 0 if the combination is not allowed for any reason.
1111
1112    If the combination is allowed, *PDEST will be set to the single
1113    destination of INSN and *PSRC to the single source, and this function
1114    will return 1.  */
1115
1116 static int
1117 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1118                rtx *pdest, rtx *psrc)
1119 {
1120   int i;
1121   rtx set = 0, src, dest;
1122   rtx p;
1123 #ifdef AUTO_INC_DEC
1124   rtx link;
1125 #endif
1126   int all_adjacent = (succ ? (next_active_insn (insn) == succ
1127                               && next_active_insn (succ) == i3)
1128                       : next_active_insn (insn) == i3);
1129
1130   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1131      or a PARALLEL consisting of such a SET and CLOBBERs.
1132
1133      If INSN has CLOBBER parallel parts, ignore them for our processing.
1134      By definition, these happen during the execution of the insn.  When it
1135      is merged with another insn, all bets are off.  If they are, in fact,
1136      needed and aren't also supplied in I3, they may be added by
1137      recog_for_combine.  Otherwise, it won't match.
1138
1139      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1140      note.
1141
1142      Get the source and destination of INSN.  If more than one, can't
1143      combine.  */
1144
1145   if (GET_CODE (PATTERN (insn)) == SET)
1146     set = PATTERN (insn);
1147   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1148            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1149     {
1150       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1151         {
1152           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1153           rtx note;
1154
1155           switch (GET_CODE (elt))
1156             {
1157             /* This is important to combine floating point insns
1158                for the SH4 port.  */
1159             case USE:
1160               /* Combining an isolated USE doesn't make sense.
1161                  We depend here on combinable_i3pat to reject them.  */
1162               /* The code below this loop only verifies that the inputs of
1163                  the SET in INSN do not change.  We call reg_set_between_p
1164                  to verify that the REG in the USE does not change between
1165                  I3 and INSN.
1166                  If the USE in INSN was for a pseudo register, the matching
1167                  insn pattern will likely match any register; combining this
1168                  with any other USE would only be safe if we knew that the
1169                  used registers have identical values, or if there was
1170                  something to tell them apart, e.g. different modes.  For
1171                  now, we forgo such complicated tests and simply disallow
1172                  combining of USES of pseudo registers with any other USE.  */
1173               if (REG_P (XEXP (elt, 0))
1174                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1175                 {
1176                   rtx i3pat = PATTERN (i3);
1177                   int i = XVECLEN (i3pat, 0) - 1;
1178                   unsigned int regno = REGNO (XEXP (elt, 0));
1179
1180                   do
1181                     {
1182                       rtx i3elt = XVECEXP (i3pat, 0, i);
1183
1184                       if (GET_CODE (i3elt) == USE
1185                           && REG_P (XEXP (i3elt, 0))
1186                           && (REGNO (XEXP (i3elt, 0)) == regno
1187                               ? reg_set_between_p (XEXP (elt, 0),
1188                                                    PREV_INSN (insn), i3)
1189                               : regno >= FIRST_PSEUDO_REGISTER))
1190                         return 0;
1191                     }
1192                   while (--i >= 0);
1193                 }
1194               break;
1195
1196               /* We can ignore CLOBBERs.  */
1197             case CLOBBER:
1198               break;
1199
1200             case SET:
1201               /* Ignore SETs whose result isn't used but not those that
1202                  have side-effects.  */
1203               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1204                   && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1205                       || INTVAL (XEXP (note, 0)) <= 0)
1206                   && ! side_effects_p (elt))
1207                 break;
1208
1209               /* If we have already found a SET, this is a second one and
1210                  so we cannot combine with this insn.  */
1211               if (set)
1212                 return 0;
1213
1214               set = elt;
1215               break;
1216
1217             default:
1218               /* Anything else means we can't combine.  */
1219               return 0;
1220             }
1221         }
1222
1223       if (set == 0
1224           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1225              so don't do anything with it.  */
1226           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1227         return 0;
1228     }
1229   else
1230     return 0;
1231
1232   if (set == 0)
1233     return 0;
1234
1235   set = expand_field_assignment (set);
1236   src = SET_SRC (set), dest = SET_DEST (set);
1237
1238   /* Don't eliminate a store in the stack pointer.  */
1239   if (dest == stack_pointer_rtx
1240       /* Don't combine with an insn that sets a register to itself if it has
1241          a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
1242       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1243       /* Can't merge an ASM_OPERANDS.  */
1244       || GET_CODE (src) == ASM_OPERANDS
1245       /* Can't merge a function call.  */
1246       || GET_CODE (src) == CALL
1247       /* Don't eliminate a function call argument.  */
1248       || (CALL_P (i3)
1249           && (find_reg_fusage (i3, USE, dest)
1250               || (REG_P (dest)
1251                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1252                   && global_regs[REGNO (dest)])))
1253       /* Don't substitute into an incremented register.  */
1254       || FIND_REG_INC_NOTE (i3, dest)
1255       || (succ && FIND_REG_INC_NOTE (succ, dest))
1256       /* Don't substitute into a non-local goto, this confuses CFG.  */
1257       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1258 #if 0
1259       /* Don't combine the end of a libcall into anything.  */
1260       /* ??? This gives worse code, and appears to be unnecessary, since no
1261          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
1262          use REG_RETVAL notes for noconflict blocks, but other code here
1263          makes sure that those insns don't disappear.  */
1264       || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1265 #endif
1266       /* Make sure that DEST is not used after SUCC but before I3.  */
1267       || (succ && ! all_adjacent
1268           && reg_used_between_p (dest, succ, i3))
1269       /* Make sure that the value that is to be substituted for the register
1270          does not use any registers whose values alter in between.  However,
1271          If the insns are adjacent, a use can't cross a set even though we
1272          think it might (this can happen for a sequence of insns each setting
1273          the same destination; last_set of that register might point to
1274          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1275          equivalent to the memory so the substitution is valid even if there
1276          are intervening stores.  Also, don't move a volatile asm or
1277          UNSPEC_VOLATILE across any other insns.  */
1278       || (! all_adjacent
1279           && (((!MEM_P (src)
1280                 || ! find_reg_note (insn, REG_EQUIV, src))
1281                && use_crosses_set_p (src, INSN_CUID (insn)))
1282               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1283               || GET_CODE (src) == UNSPEC_VOLATILE))
1284       /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1285          better register allocation by not doing the combine.  */
1286       || find_reg_note (i3, REG_NO_CONFLICT, dest)
1287       || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1288       /* Don't combine across a CALL_INSN, because that would possibly
1289          change whether the life span of some REGs crosses calls or not,
1290          and it is a pain to update that information.
1291          Exception: if source is a constant, moving it later can't hurt.
1292          Accept that special case, because it helps -fforce-addr a lot.  */
1293       || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1294     return 0;
1295
1296   /* DEST must either be a REG or CC0.  */
1297   if (REG_P (dest))
1298     {
1299       /* If register alignment is being enforced for multi-word items in all
1300          cases except for parameters, it is possible to have a register copy
1301          insn referencing a hard register that is not allowed to contain the
1302          mode being copied and which would not be valid as an operand of most
1303          insns.  Eliminate this problem by not combining with such an insn.
1304
1305          Also, on some machines we don't want to extend the life of a hard
1306          register.  */
1307
1308       if (REG_P (src)
1309           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1310                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1311               /* Don't extend the life of a hard register unless it is
1312                  user variable (if we have few registers) or it can't
1313                  fit into the desired register (meaning something special
1314                  is going on).
1315                  Also avoid substituting a return register into I3, because
1316                  reload can't handle a conflict with constraints of other
1317                  inputs.  */
1318               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1319                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1320         return 0;
1321     }
1322   else if (GET_CODE (dest) != CC0)
1323     return 0;
1324
1325
1326   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1327     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1328       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1329         {
1330           /* Don't substitute for a register intended as a clobberable
1331              operand.  */
1332           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1333           if (rtx_equal_p (reg, dest))
1334             return 0;
1335
1336           /* If the clobber represents an earlyclobber operand, we must not
1337              substitute an expression containing the clobbered register.
1338              As we do not analyze the constraint strings here, we have to
1339              make the conservative assumption.  However, if the register is
1340              a fixed hard reg, the clobber cannot represent any operand;
1341              we leave it up to the machine description to either accept or
1342              reject use-and-clobber patterns.  */
1343           if (!REG_P (reg)
1344               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1345               || !fixed_regs[REGNO (reg)])
1346             if (reg_overlap_mentioned_p (reg, src))
1347               return 0;
1348         }
1349
1350   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1351      or not), reject, unless nothing volatile comes between it and I3 */
1352
1353   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1354     {
1355       /* Make sure succ doesn't contain a volatile reference.  */
1356       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1357         return 0;
1358
1359       for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1360         if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1361           return 0;
1362     }
1363
1364   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1365      to be an explicit register variable, and was chosen for a reason.  */
1366
1367   if (GET_CODE (src) == ASM_OPERANDS
1368       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1369     return 0;
1370
1371   /* If there are any volatile insns between INSN and I3, reject, because
1372      they might affect machine state.  */
1373
1374   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1375     if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1376       return 0;
1377
1378   /* If INSN contains an autoincrement or autodecrement, make sure that
1379      register is not used between there and I3, and not already used in
1380      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1381      Also insist that I3 not be a jump; if it were one
1382      and the incremented register were spilled, we would lose.  */
1383
1384 #ifdef AUTO_INC_DEC
1385   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1386     if (REG_NOTE_KIND (link) == REG_INC
1387         && (JUMP_P (i3)
1388             || reg_used_between_p (XEXP (link, 0), insn, i3)
1389             || (pred != NULL_RTX
1390                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1391             || (succ != NULL_RTX
1392                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1393             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1394       return 0;
1395 #endif
1396
1397 #ifdef HAVE_cc0
1398   /* Don't combine an insn that follows a CC0-setting insn.
1399      An insn that uses CC0 must not be separated from the one that sets it.
1400      We do, however, allow I2 to follow a CC0-setting insn if that insn
1401      is passed as I1; in that case it will be deleted also.
1402      We also allow combining in this case if all the insns are adjacent
1403      because that would leave the two CC0 insns adjacent as well.
1404      It would be more logical to test whether CC0 occurs inside I1 or I2,
1405      but that would be much slower, and this ought to be equivalent.  */
1406
1407   p = prev_nonnote_insn (insn);
1408   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1409       && ! all_adjacent)
1410     return 0;
1411 #endif
1412
1413   /* If we get here, we have passed all the tests and the combination is
1414      to be allowed.  */
1415
1416   *pdest = dest;
1417   *psrc = src;
1418
1419   return 1;
1420 }
1421 \f
1422 /* LOC is the location within I3 that contains its pattern or the component
1423    of a PARALLEL of the pattern.  We validate that it is valid for combining.
1424
1425    One problem is if I3 modifies its output, as opposed to replacing it
1426    entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1427    so would produce an insn that is not equivalent to the original insns.
1428
1429    Consider:
1430
1431          (set (reg:DI 101) (reg:DI 100))
1432          (set (subreg:SI (reg:DI 101) 0) <foo>)
1433
1434    This is NOT equivalent to:
1435
1436          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1437                     (set (reg:DI 101) (reg:DI 100))])
1438
1439    Not only does this modify 100 (in which case it might still be valid
1440    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1441
1442    We can also run into a problem if I2 sets a register that I1
1443    uses and I1 gets directly substituted into I3 (not via I2).  In that
1444    case, we would be getting the wrong value of I2DEST into I3, so we
1445    must reject the combination.  This case occurs when I2 and I1 both
1446    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1447    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1448    of a SET must prevent combination from occurring.
1449
1450    Before doing the above check, we first try to expand a field assignment
1451    into a set of logical operations.
1452
1453    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1454    we place a register that is both set and used within I3.  If more than one
1455    such register is detected, we fail.
1456
1457    Return 1 if the combination is valid, zero otherwise.  */
1458
1459 static int
1460 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1461                   int i1_not_in_src, rtx *pi3dest_killed)
1462 {
1463   rtx x = *loc;
1464
1465   if (GET_CODE (x) == SET)
1466     {
1467       rtx set = x ;
1468       rtx dest = SET_DEST (set);
1469       rtx src = SET_SRC (set);
1470       rtx inner_dest = dest;
1471       rtx subdest;
1472
1473       while (GET_CODE (inner_dest) == STRICT_LOW_PART
1474              || GET_CODE (inner_dest) == SUBREG
1475              || GET_CODE (inner_dest) == ZERO_EXTRACT)
1476         inner_dest = XEXP (inner_dest, 0);
1477
1478       /* Check for the case where I3 modifies its output, as discussed
1479          above.  We don't want to prevent pseudos from being combined
1480          into the address of a MEM, so only prevent the combination if
1481          i1 or i2 set the same MEM.  */
1482       if ((inner_dest != dest &&
1483            (!MEM_P (inner_dest)
1484             || rtx_equal_p (i2dest, inner_dest)
1485             || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1486            && (reg_overlap_mentioned_p (i2dest, inner_dest)
1487                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1488
1489           /* This is the same test done in can_combine_p except we can't test
1490              all_adjacent; we don't have to, since this instruction will stay
1491              in place, thus we are not considering increasing the lifetime of
1492              INNER_DEST.
1493
1494              Also, if this insn sets a function argument, combining it with
1495              something that might need a spill could clobber a previous
1496              function argument; the all_adjacent test in can_combine_p also
1497              checks this; here, we do a more specific test for this case.  */
1498
1499           || (REG_P (inner_dest)
1500               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1501               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1502                                         GET_MODE (inner_dest))))
1503           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1504         return 0;
1505
1506       /* If DEST is used in I3, it is being killed in this insn, so
1507          record that for later.  We have to consider paradoxical
1508          subregs here, since they kill the whole register, but we
1509          ignore partial subregs, STRICT_LOW_PART, etc.
1510          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1511          STACK_POINTER_REGNUM, since these are always considered to be
1512          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
1513       subdest = dest;
1514       if (GET_CODE (subdest) == SUBREG
1515           && (GET_MODE_SIZE (GET_MODE (subdest))
1516               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1517         subdest = SUBREG_REG (subdest);
1518       if (pi3dest_killed
1519           && REG_P (subdest)
1520           && reg_referenced_p (subdest, PATTERN (i3))
1521           && REGNO (subdest) != FRAME_POINTER_REGNUM
1522 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1523           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1524 #endif
1525 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526           && (REGNO (subdest) != ARG_POINTER_REGNUM
1527               || ! fixed_regs [REGNO (subdest)])
1528 #endif
1529           && REGNO (subdest) != STACK_POINTER_REGNUM)
1530         {
1531           if (*pi3dest_killed)
1532             return 0;
1533
1534           *pi3dest_killed = subdest;
1535         }
1536     }
1537
1538   else if (GET_CODE (x) == PARALLEL)
1539     {
1540       int i;
1541
1542       for (i = 0; i < XVECLEN (x, 0); i++)
1543         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1544                                 i1_not_in_src, pi3dest_killed))
1545           return 0;
1546     }
1547
1548   return 1;
1549 }
1550 \f
1551 /* Return 1 if X is an arithmetic expression that contains a multiplication
1552    and division.  We don't count multiplications by powers of two here.  */
1553
1554 static int
1555 contains_muldiv (rtx x)
1556 {
1557   switch (GET_CODE (x))
1558     {
1559     case MOD:  case DIV:  case UMOD:  case UDIV:
1560       return 1;
1561
1562     case MULT:
1563       return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1564                 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1565     default:
1566       if (BINARY_P (x))
1567         return contains_muldiv (XEXP (x, 0))
1568             || contains_muldiv (XEXP (x, 1));
1569
1570       if (UNARY_P (x))
1571         return contains_muldiv (XEXP (x, 0));
1572
1573       return 0;
1574     }
1575 }
1576 \f
1577 /* Determine whether INSN can be used in a combination.  Return nonzero if
1578    not.  This is used in try_combine to detect early some cases where we
1579    can't perform combinations.  */
1580
1581 static int
1582 cant_combine_insn_p (rtx insn)
1583 {
1584   rtx set;
1585   rtx src, dest;
1586
1587   /* If this isn't really an insn, we can't do anything.
1588      This can occur when flow deletes an insn that it has merged into an
1589      auto-increment address.  */
1590   if (! INSN_P (insn))
1591     return 1;
1592
1593   /* Never combine loads and stores involving hard regs that are likely
1594      to be spilled.  The register allocator can usually handle such
1595      reg-reg moves by tying.  If we allow the combiner to make
1596      substitutions of likely-spilled regs, reload might die.
1597      As an exception, we allow combinations involving fixed regs; these are
1598      not available to the register allocator so there's no risk involved.  */
1599
1600   set = single_set (insn);
1601   if (! set)
1602     return 0;
1603   src = SET_SRC (set);
1604   dest = SET_DEST (set);
1605   if (GET_CODE (src) == SUBREG)
1606     src = SUBREG_REG (src);
1607   if (GET_CODE (dest) == SUBREG)
1608     dest = SUBREG_REG (dest);
1609   if (REG_P (src) && REG_P (dest)
1610       && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1611            && ! fixed_regs[REGNO (src)]
1612            && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1613           || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1614               && ! fixed_regs[REGNO (dest)]
1615               && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1616     return 1;
1617
1618   return 0;
1619 }
1620
1621 struct likely_spilled_retval_info
1622 {
1623   unsigned regno, nregs;
1624   unsigned mask;
1625 };
1626
1627 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
1628    hard registers that are known to be written to / clobbered in full.  */
1629 static void
1630 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1631 {
1632   struct likely_spilled_retval_info *info = data;
1633   unsigned regno, nregs;
1634   unsigned new_mask;
1635
1636   if (!REG_P (XEXP (set, 0)))
1637     return;
1638   regno = REGNO (x);
1639   if (regno >= info->regno + info->nregs)
1640     return;
1641   nregs = hard_regno_nregs[regno][GET_MODE (x)];
1642   if (regno + nregs <= info->regno)
1643     return;
1644   new_mask = (2U << (nregs - 1)) - 1;
1645   if (regno < info->regno)
1646     new_mask >>= info->regno - regno;
1647   else
1648     new_mask <<= regno - info->regno;
1649   info->mask &= new_mask;
1650 }
1651
1652 /* Return nonzero iff part of the return value is live during INSN, and
1653    it is likely spilled.  This can happen when more than one insn is needed
1654    to copy the return value, e.g. when we consider to combine into the
1655    second copy insn for a complex value.  */
1656
1657 static int
1658 likely_spilled_retval_p (rtx insn)
1659 {
1660   rtx use = BB_END (this_basic_block);
1661   rtx reg, p;
1662   unsigned regno, nregs;
1663   /* We assume here that no machine mode needs more than
1664      32 hard registers when the value overlaps with a register
1665      for which FUNCTION_VALUE_REGNO_P is true.  */
1666   unsigned mask;
1667   struct likely_spilled_retval_info info;
1668
1669   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1670     return 0;
1671   reg = XEXP (PATTERN (use), 0);
1672   if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1673     return 0;
1674   regno = REGNO (reg);
1675   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1676   if (nregs == 1)
1677     return 0;
1678   mask = (2U << (nregs - 1)) - 1;
1679
1680   /* Disregard parts of the return value that are set later.  */
1681   info.regno = regno;
1682   info.nregs = nregs;
1683   info.mask = mask;
1684   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1685     note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1686   mask = info.mask;
1687
1688   /* Check if any of the (probably) live return value registers is
1689      likely spilled.  */
1690   nregs --;
1691   do
1692     {
1693       if ((mask & 1 << nregs)
1694           && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1695         return 1;
1696     } while (nregs--);
1697   return 0;
1698 }
1699
1700 /* Adjust INSN after we made a change to its destination.
1701
1702    Changing the destination can invalidate notes that say something about
1703    the results of the insn and a LOG_LINK pointing to the insn.  */
1704
1705 static void
1706 adjust_for_new_dest (rtx insn)
1707 {
1708   rtx *loc;
1709
1710   /* For notes, be conservative and simply remove them.  */
1711   loc = &REG_NOTES (insn);
1712   while (*loc)
1713     {
1714       enum reg_note kind = REG_NOTE_KIND (*loc);
1715       if (kind == REG_EQUAL || kind == REG_EQUIV)
1716         *loc = XEXP (*loc, 1);
1717       else
1718         loc = &XEXP (*loc, 1);
1719     }
1720
1721   /* The new insn will have a destination that was previously the destination
1722      of an insn just above it.  Call distribute_links to make a LOG_LINK from
1723      the next use of that destination.  */
1724   distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1725 }
1726
1727 /* Return TRUE if combine can reuse reg X in mode MODE.
1728    ADDED_SETS is nonzero if the original set is still required.  */
1729 static bool
1730 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1731 {
1732   unsigned int regno;
1733
1734   if (!REG_P(x))
1735     return false;
1736
1737   regno = REGNO (x);
1738   /* Allow hard registers if the new mode is legal, and occupies no more
1739      registers than the old mode.  */
1740   if (regno < FIRST_PSEUDO_REGISTER)
1741     return (HARD_REGNO_MODE_OK (regno, mode)
1742             && (hard_regno_nregs[regno][GET_MODE (x)]
1743                 >= hard_regno_nregs[regno][mode]));
1744
1745   /* Or a pseudo that is only used once.  */
1746   return (REG_N_SETS (regno) == 1 && !added_sets
1747           && !REG_USERVAR_P (x));
1748 }
1749
1750
1751 /* Check whether X, the destination of a set, refers to part of
1752    the register specified by REG.  */
1753
1754 static bool
1755 reg_subword_p (rtx x, rtx reg)
1756 {
1757   /* Check that reg is an integer mode register.  */
1758   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1759     return false;
1760
1761   if (GET_CODE (x) == STRICT_LOW_PART
1762       || GET_CODE (x) == ZERO_EXTRACT)
1763     x = XEXP (x, 0);
1764
1765   return GET_CODE (x) == SUBREG
1766          && SUBREG_REG (x) == reg
1767          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1768 }
1769
1770
1771 /* Try to combine the insns I1 and I2 into I3.
1772    Here I1 and I2 appear earlier than I3.
1773    I1 can be zero; then we combine just I2 into I3.
1774
1775    If we are combining three insns and the resulting insn is not recognized,
1776    try splitting it into two insns.  If that happens, I2 and I3 are retained
1777    and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
1778    are pseudo-deleted.
1779
1780    Return 0 if the combination does not work.  Then nothing is changed.
1781    If we did the combination, return the insn at which combine should
1782    resume scanning.
1783
1784    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1785    new direct jump instruction.  */
1786
1787 static rtx
1788 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1789 {
1790   /* New patterns for I3 and I2, respectively.  */
1791   rtx newpat, newi2pat = 0;
1792   rtvec newpat_vec_with_clobbers = 0;
1793   int substed_i2 = 0, substed_i1 = 0;
1794   /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
1795   int added_sets_1, added_sets_2;
1796   /* Total number of SETs to put into I3.  */
1797   int total_sets;
1798   /* Nonzero if I2's body now appears in I3.  */
1799   int i2_is_used;
1800   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
1801   int insn_code_number, i2_code_number = 0, other_code_number = 0;
1802   /* Contains I3 if the destination of I3 is used in its source, which means
1803      that the old life of I3 is being killed.  If that usage is placed into
1804      I2 and not in I3, a REG_DEAD note must be made.  */
1805   rtx i3dest_killed = 0;
1806   /* SET_DEST and SET_SRC of I2 and I1.  */
1807   rtx i2dest, i2src, i1dest = 0, i1src = 0;
1808   /* PATTERN (I2), or a copy of it in certain cases.  */
1809   rtx i2pat;
1810   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
1811   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1812   int i2dest_killed = 0, i1dest_killed = 0;
1813   int i1_feeds_i3 = 0;
1814   /* Notes that must be added to REG_NOTES in I3 and I2.  */
1815   rtx new_i3_notes, new_i2_notes;
1816   /* Notes that we substituted I3 into I2 instead of the normal case.  */
1817   int i3_subst_into_i2 = 0;
1818   /* Notes that I1, I2 or I3 is a MULT operation.  */
1819   int have_mult = 0;
1820   int swap_i2i3 = 0;
1821
1822   int maxreg;
1823   rtx temp;
1824   rtx link;
1825   int i;
1826
1827   /* Exit early if one of the insns involved can't be used for
1828      combinations.  */
1829   if (cant_combine_insn_p (i3)
1830       || cant_combine_insn_p (i2)
1831       || (i1 && cant_combine_insn_p (i1))
1832       || likely_spilled_retval_p (i3)
1833       /* We also can't do anything if I3 has a
1834          REG_LIBCALL note since we don't want to disrupt the contiguity of a
1835          libcall.  */
1836 #if 0
1837       /* ??? This gives worse code, and appears to be unnecessary, since no
1838          pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
1839       || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1840 #endif
1841       )
1842     return 0;
1843
1844   combine_attempts++;
1845   undobuf.other_insn = 0;
1846
1847   /* Reset the hard register usage information.  */
1848   CLEAR_HARD_REG_SET (newpat_used_regs);
1849
1850   /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
1851      code below, set I1 to be the earlier of the two insns.  */
1852   if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1853     temp = i1, i1 = i2, i2 = temp;
1854
1855   added_links_insn = 0;
1856
1857   /* First check for one important special-case that the code below will
1858      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
1859      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
1860      we may be able to replace that destination with the destination of I3.
1861      This occurs in the common code where we compute both a quotient and
1862      remainder into a structure, in which case we want to do the computation
1863      directly into the structure to avoid register-register copies.
1864
1865      Note that this case handles both multiple sets in I2 and also
1866      cases where I2 has a number of CLOBBER or PARALLELs.
1867
1868      We make very conservative checks below and only try to handle the
1869      most common cases of this.  For example, we only handle the case
1870      where I2 and I3 are adjacent to avoid making difficult register
1871      usage tests.  */
1872
1873   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1874       && REG_P (SET_SRC (PATTERN (i3)))
1875       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1876       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1877       && GET_CODE (PATTERN (i2)) == PARALLEL
1878       && ! side_effects_p (SET_DEST (PATTERN (i3)))
1879       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1880          below would need to check what is inside (and reg_overlap_mentioned_p
1881          doesn't support those codes anyway).  Don't allow those destinations;
1882          the resulting insn isn't likely to be recognized anyway.  */
1883       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1884       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1885       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1886                                     SET_DEST (PATTERN (i3)))
1887       && next_real_insn (i2) == i3)
1888     {
1889       rtx p2 = PATTERN (i2);
1890
1891       /* Make sure that the destination of I3,
1892          which we are going to substitute into one output of I2,
1893          is not used within another output of I2.  We must avoid making this:
1894          (parallel [(set (mem (reg 69)) ...)
1895                     (set (reg 69) ...)])
1896          which is not well-defined as to order of actions.
1897          (Besides, reload can't handle output reloads for this.)
1898
1899          The problem can also happen if the dest of I3 is a memory ref,
1900          if another dest in I2 is an indirect memory ref.  */
1901       for (i = 0; i < XVECLEN (p2, 0); i++)
1902         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1903              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1904             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1905                                         SET_DEST (XVECEXP (p2, 0, i))))
1906           break;
1907
1908       if (i == XVECLEN (p2, 0))
1909         for (i = 0; i < XVECLEN (p2, 0); i++)
1910           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1911                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1912               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1913             {
1914               combine_merges++;
1915
1916               subst_insn = i3;
1917               subst_low_cuid = INSN_CUID (i2);
1918
1919               added_sets_2 = added_sets_1 = 0;
1920               i2dest = SET_SRC (PATTERN (i3));
1921               i2dest_killed = dead_or_set_p (i2, i2dest);
1922
1923               /* Replace the dest in I2 with our dest and make the resulting
1924                  insn the new pattern for I3.  Then skip to where we
1925                  validate the pattern.  Everything was set up above.  */
1926               SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1927                      SET_DEST (PATTERN (i3)));
1928
1929               newpat = p2;
1930               i3_subst_into_i2 = 1;
1931               goto validate_replacement;
1932             }
1933     }
1934
1935   /* If I2 is setting a pseudo to a constant and I3 is setting some
1936      sub-part of it to another constant, merge them by making a new
1937      constant.  */
1938   if (i1 == 0
1939       && (temp = single_set (i2)) != 0
1940       && (GET_CODE (SET_SRC (temp)) == CONST_INT
1941           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1942       && GET_CODE (PATTERN (i3)) == SET
1943       && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1944           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1945       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1946     {
1947       rtx dest = SET_DEST (PATTERN (i3));
1948       int offset = -1;
1949       int width = 0;
1950
1951       if (GET_CODE (dest) == ZERO_EXTRACT)
1952         {
1953           if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1954               && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1955             {
1956               width = INTVAL (XEXP (dest, 1));
1957               offset = INTVAL (XEXP (dest, 2));
1958               dest = XEXP (dest, 0);
1959               if (BITS_BIG_ENDIAN)
1960                 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1961             }
1962         }
1963       else
1964         {
1965           if (GET_CODE (dest) == STRICT_LOW_PART)
1966             dest = XEXP (dest, 0);
1967           width = GET_MODE_BITSIZE (GET_MODE (dest));
1968           offset = 0;
1969         }
1970
1971       if (offset >= 0)
1972         {
1973           /* If this is the low part, we're done.  */
1974           if (subreg_lowpart_p (dest))
1975             ;
1976           /* Handle the case where inner is twice the size of outer.  */
1977           else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1978                    == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1979             offset += GET_MODE_BITSIZE (GET_MODE (dest));
1980           /* Otherwise give up for now.  */
1981           else
1982             offset = -1;
1983         }
1984
1985       if (offset >= 0)
1986         {
1987           HOST_WIDE_INT mhi, ohi, ihi;
1988           HOST_WIDE_INT mlo, olo, ilo;
1989           rtx inner = SET_SRC (PATTERN (i3));
1990           rtx outer = SET_SRC (temp);
1991
1992           if (GET_CODE (outer) == CONST_INT)
1993             {
1994               olo = INTVAL (outer);
1995               ohi = olo < 0 ? -1 : 0;
1996             }
1997           else
1998             {
1999               olo = CONST_DOUBLE_LOW (outer);
2000               ohi = CONST_DOUBLE_HIGH (outer);
2001             }
2002
2003           if (GET_CODE (inner) == CONST_INT)
2004             {
2005               ilo = INTVAL (inner);
2006               ihi = ilo < 0 ? -1 : 0;
2007             }
2008           else
2009             {
2010               ilo = CONST_DOUBLE_LOW (inner);
2011               ihi = CONST_DOUBLE_HIGH (inner);
2012             }
2013
2014           if (width < HOST_BITS_PER_WIDE_INT)
2015             {
2016               mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2017               mhi = 0;
2018             }
2019           else if (width < HOST_BITS_PER_WIDE_INT * 2)
2020             {
2021               mhi = ((unsigned HOST_WIDE_INT) 1
2022                      << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2023               mlo = -1;
2024             }
2025           else
2026             {
2027               mlo = -1;
2028               mhi = -1;
2029             }
2030
2031           ilo &= mlo;
2032           ihi &= mhi;
2033
2034           if (offset >= HOST_BITS_PER_WIDE_INT)
2035             {
2036               mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2037               mlo = 0;
2038               ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2039               ilo = 0;
2040             }
2041           else if (offset > 0)
2042             {
2043               mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2044                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2045               mlo = mlo << offset;
2046               ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2047                                        >> (HOST_BITS_PER_WIDE_INT - offset));
2048               ilo = ilo << offset;
2049             }
2050
2051           olo = (olo & ~mlo) | ilo;
2052           ohi = (ohi & ~mhi) | ihi;
2053
2054           combine_merges++;
2055           subst_insn = i3;
2056           subst_low_cuid = INSN_CUID (i2);
2057           added_sets_2 = added_sets_1 = 0;
2058           i2dest = SET_DEST (temp);
2059           i2dest_killed = dead_or_set_p (i2, i2dest);
2060
2061           SUBST (SET_SRC (temp),
2062                  immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2063
2064           newpat = PATTERN (i2);
2065           goto validate_replacement;
2066         }
2067     }
2068
2069 #ifndef HAVE_cc0
2070   /* If we have no I1 and I2 looks like:
2071         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2072                    (set Y OP)])
2073      make up a dummy I1 that is
2074         (set Y OP)
2075      and change I2 to be
2076         (set (reg:CC X) (compare:CC Y (const_int 0)))
2077
2078      (We can ignore any trailing CLOBBERs.)
2079
2080      This undoes a previous combination and allows us to match a branch-and-
2081      decrement insn.  */
2082
2083   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2084       && XVECLEN (PATTERN (i2), 0) >= 2
2085       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2086       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2087           == MODE_CC)
2088       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2089       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2090       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2091       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2092       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2093                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2094     {
2095       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2096         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2097           break;
2098
2099       if (i == 1)
2100         {
2101           /* We make I1 with the same INSN_UID as I2.  This gives it
2102              the same INSN_CUID for value tracking.  Our fake I1 will
2103              never appear in the insn stream so giving it the same INSN_UID
2104              as I2 will not cause a problem.  */
2105
2106           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2107                              BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2108                              XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2109                              NULL_RTX);
2110
2111           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2112           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2113                  SET_DEST (PATTERN (i1)));
2114         }
2115     }
2116 #endif
2117
2118   /* Verify that I2 and I1 are valid for combining.  */
2119   if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2120       || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2121     {
2122       undo_all ();
2123       return 0;
2124     }
2125
2126   /* Record whether I2DEST is used in I2SRC and similarly for the other
2127      cases.  Knowing this will help in register status updating below.  */
2128   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2129   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2130   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2131   i2dest_killed = dead_or_set_p (i2, i2dest);
2132   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2133
2134   /* See if I1 directly feeds into I3.  It does if I1DEST is not used
2135      in I2SRC.  */
2136   i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2137
2138   /* Ensure that I3's pattern can be the destination of combines.  */
2139   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2140                           i1 && i2dest_in_i1src && i1_feeds_i3,
2141                           &i3dest_killed))
2142     {
2143       undo_all ();
2144       return 0;
2145     }
2146
2147   /* See if any of the insns is a MULT operation.  Unless one is, we will
2148      reject a combination that is, since it must be slower.  Be conservative
2149      here.  */
2150   if (GET_CODE (i2src) == MULT
2151       || (i1 != 0 && GET_CODE (i1src) == MULT)
2152       || (GET_CODE (PATTERN (i3)) == SET
2153           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2154     have_mult = 1;
2155
2156   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2157      We used to do this EXCEPT in one case: I3 has a post-inc in an
2158      output operand.  However, that exception can give rise to insns like
2159         mov r3,(r3)+
2160      which is a famous insn on the PDP-11 where the value of r3 used as the
2161      source was model-dependent.  Avoid this sort of thing.  */
2162
2163 #if 0
2164   if (!(GET_CODE (PATTERN (i3)) == SET
2165         && REG_P (SET_SRC (PATTERN (i3)))
2166         && MEM_P (SET_DEST (PATTERN (i3)))
2167         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2168             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2169     /* It's not the exception.  */
2170 #endif
2171 #ifdef AUTO_INC_DEC
2172     for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2173       if (REG_NOTE_KIND (link) == REG_INC
2174           && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2175               || (i1 != 0
2176                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2177         {
2178           undo_all ();
2179           return 0;
2180         }
2181 #endif
2182
2183   /* See if the SETs in I1 or I2 need to be kept around in the merged
2184      instruction: whenever the value set there is still needed past I3.
2185      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2186
2187      For the SET in I1, we have two cases:  If I1 and I2 independently
2188      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2189      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2190      in I1 needs to be kept around unless I1DEST dies or is set in either
2191      I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
2192      I1DEST.  If so, we know I1 feeds into I2.  */
2193
2194   added_sets_2 = ! dead_or_set_p (i3, i2dest);
2195
2196   added_sets_1
2197     = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2198                : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2199
2200   /* If the set in I2 needs to be kept around, we must make a copy of
2201      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2202      PATTERN (I2), we are only substituting for the original I1DEST, not into
2203      an already-substituted copy.  This also prevents making self-referential
2204      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2205      I2DEST.  */
2206
2207   i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2208            ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2209            : PATTERN (i2));
2210
2211   if (added_sets_2)
2212     i2pat = copy_rtx (i2pat);
2213
2214   combine_merges++;
2215
2216   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2217
2218   maxreg = max_reg_num ();
2219
2220   subst_insn = i3;
2221
2222 #ifndef HAVE_cc0
2223   /* Many machines that don't use CC0 have insns that can both perform an
2224      arithmetic operation and set the condition code.  These operations will
2225      be represented as a PARALLEL with the first element of the vector
2226      being a COMPARE of an arithmetic operation with the constant zero.
2227      The second element of the vector will set some pseudo to the result
2228      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2229      match such a pattern and so will generate an extra insn.   Here we test
2230      for this case, where both the comparison and the operation result are
2231      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2232      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2233
2234   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2235       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2236       && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2237       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2238     {
2239 #ifdef SELECT_CC_MODE
2240       rtx *cc_use;
2241       enum machine_mode compare_mode;
2242 #endif
2243
2244       newpat = PATTERN (i3);
2245       SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2246
2247       i2_is_used = 1;
2248
2249 #ifdef SELECT_CC_MODE
2250       /* See if a COMPARE with the operand we substituted in should be done
2251          with the mode that is currently being used.  If not, do the same
2252          processing we do in `subst' for a SET; namely, if the destination
2253          is used only once, try to replace it with a register of the proper
2254          mode and also replace the COMPARE.  */
2255       if (undobuf.other_insn == 0
2256           && (cc_use = find_single_use (SET_DEST (newpat), i3,
2257                                         &undobuf.other_insn))
2258           && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2259                                               i2src, const0_rtx))
2260               != GET_MODE (SET_DEST (newpat))))
2261         {
2262           if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2263                                    compare_mode))
2264             {
2265               unsigned int regno = REGNO (SET_DEST (newpat));
2266               rtx new_dest;
2267
2268               if (regno < FIRST_PSEUDO_REGISTER)
2269                 new_dest = gen_rtx_REG (compare_mode, regno);
2270               else
2271                 {
2272                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2273                   new_dest = regno_reg_rtx[regno];
2274                 }
2275
2276               SUBST (SET_DEST (newpat), new_dest);
2277               SUBST (XEXP (*cc_use, 0), new_dest);
2278               SUBST (SET_SRC (newpat),
2279                      gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2280             }
2281           else
2282             undobuf.other_insn = 0;
2283         }
2284 #endif
2285     }
2286   else
2287 #endif
2288     {
2289       /* It is possible that the source of I2 or I1 may be performing
2290          an unneeded operation, such as a ZERO_EXTEND of something
2291          that is known to have the high part zero.  Handle that case
2292          by letting subst look at the innermost one of them.
2293
2294          Another way to do this would be to have a function that tries
2295          to simplify a single insn instead of merging two or more
2296          insns.  We don't do this because of the potential of infinite
2297          loops and because of the potential extra memory required.
2298          However, doing it the way we are is a bit of a kludge and
2299          doesn't catch all cases.
2300
2301          But only do this if -fexpensive-optimizations since it slows
2302          things down and doesn't usually win.
2303
2304          This is not done in the COMPARE case above because the
2305          unmodified I2PAT is used in the PARALLEL and so a pattern
2306          with a modified I2SRC would not match.  */
2307
2308       if (flag_expensive_optimizations)
2309         {
2310           /* Pass pc_rtx so no substitutions are done, just
2311              simplifications.  */
2312           if (i1)
2313             {
2314               subst_low_cuid = INSN_CUID (i1);
2315               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2316             }
2317           else
2318             {
2319               subst_low_cuid = INSN_CUID (i2);
2320               i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2321             }
2322         }
2323
2324       n_occurrences = 0;                /* `subst' counts here */
2325
2326       /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2327          need to make a unique copy of I2SRC each time we substitute it
2328          to avoid self-referential rtl.  */
2329
2330       subst_low_cuid = INSN_CUID (i2);
2331       newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2332                       ! i1_feeds_i3 && i1dest_in_i1src);
2333       substed_i2 = 1;
2334
2335       /* Record whether i2's body now appears within i3's body.  */
2336       i2_is_used = n_occurrences;
2337     }
2338
2339   /* If we already got a failure, don't try to do more.  Otherwise,
2340      try to substitute in I1 if we have it.  */
2341
2342   if (i1 && GET_CODE (newpat) != CLOBBER)
2343     {
2344       /* Before we can do this substitution, we must redo the test done
2345          above (see detailed comments there) that ensures  that I1DEST
2346          isn't mentioned in any SETs in NEWPAT that are field assignments.  */
2347
2348       if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2349                               0, (rtx*) 0))
2350         {
2351           undo_all ();
2352           return 0;
2353         }
2354
2355       n_occurrences = 0;
2356       subst_low_cuid = INSN_CUID (i1);
2357       newpat = subst (newpat, i1dest, i1src, 0, 0);
2358       substed_i1 = 1;
2359     }
2360
2361   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
2362      to count all the ways that I2SRC and I1SRC can be used.  */
2363   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2364        && i2_is_used + added_sets_2 > 1)
2365       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2366           && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2367               > 1))
2368       /* Fail if we tried to make a new register.  */
2369       || max_reg_num () != maxreg
2370       /* Fail if we couldn't do something and have a CLOBBER.  */
2371       || GET_CODE (newpat) == CLOBBER
2372       /* Fail if this new pattern is a MULT and we didn't have one before
2373          at the outer level.  */
2374       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2375           && ! have_mult))
2376     {
2377       undo_all ();
2378       return 0;
2379     }
2380
2381   /* If the actions of the earlier insns must be kept
2382      in addition to substituting them into the latest one,
2383      we must make a new PARALLEL for the latest insn
2384      to hold additional the SETs.  */
2385
2386   if (added_sets_1 || added_sets_2)
2387     {
2388       combine_extras++;
2389
2390       if (GET_CODE (newpat) == PARALLEL)
2391         {
2392           rtvec old = XVEC (newpat, 0);
2393           total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2394           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2395           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2396                   sizeof (old->elem[0]) * old->num_elem);
2397         }
2398       else
2399         {
2400           rtx old = newpat;
2401           total_sets = 1 + added_sets_1 + added_sets_2;
2402           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2403           XVECEXP (newpat, 0, 0) = old;
2404         }
2405
2406       if (added_sets_1)
2407         XVECEXP (newpat, 0, --total_sets)
2408           = (GET_CODE (PATTERN (i1)) == PARALLEL
2409              ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2410
2411       if (added_sets_2)
2412         {
2413           /* If there is no I1, use I2's body as is.  We used to also not do
2414              the subst call below if I2 was substituted into I3,
2415              but that could lose a simplification.  */
2416           if (i1 == 0)
2417             XVECEXP (newpat, 0, --total_sets) = i2pat;
2418           else
2419             /* See comment where i2pat is assigned.  */
2420             XVECEXP (newpat, 0, --total_sets)
2421               = subst (i2pat, i1dest, i1src, 0, 0);
2422         }
2423     }
2424
2425   /* We come here when we are replacing a destination in I2 with the
2426      destination of I3.  */
2427  validate_replacement:
2428
2429   /* Note which hard regs this insn has as inputs.  */
2430   mark_used_regs_combine (newpat);
2431
2432   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
2433      consider splitting this pattern, we might need these clobbers.  */
2434   if (i1 && GET_CODE (newpat) == PARALLEL
2435       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2436     {
2437       int len = XVECLEN (newpat, 0);
2438
2439       newpat_vec_with_clobbers = rtvec_alloc (len);
2440       for (i = 0; i < len; i++)
2441         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2442     }
2443
2444   /* Is the result of combination a valid instruction?  */
2445   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2446
2447   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2448      the second SET's destination is a register that is unused and isn't
2449      marked as an instruction that might trap in an EH region.  In that case,
2450      we just need the first SET.   This can occur when simplifying a divmod
2451      insn.  We *must* test for this case here because the code below that
2452      splits two independent SETs doesn't handle this case correctly when it
2453      updates the register status.
2454
2455      It's pointless doing this if we originally had two sets, one from
2456      i3, and one from i2.  Combining then splitting the parallel results
2457      in the original i2 again plus an invalid insn (which we delete).
2458      The net effect is only to move instructions around, which makes
2459      debug info less accurate.
2460
2461      Also check the case where the first SET's destination is unused.
2462      That would not cause incorrect code, but does cause an unneeded
2463      insn to remain.  */
2464
2465   if (insn_code_number < 0
2466       && !(added_sets_2 && i1 == 0)
2467       && GET_CODE (newpat) == PARALLEL
2468       && XVECLEN (newpat, 0) == 2
2469       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2470       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2471       && asm_noperands (newpat) < 0)
2472     {
2473       rtx set0 = XVECEXP (newpat, 0, 0);
2474       rtx set1 = XVECEXP (newpat, 0, 1);
2475       rtx note;
2476
2477       if (((REG_P (SET_DEST (set1))
2478             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2479            || (GET_CODE (SET_DEST (set1)) == SUBREG
2480                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2481           && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2482               || INTVAL (XEXP (note, 0)) <= 0)
2483           && ! side_effects_p (SET_SRC (set1)))
2484         {
2485           newpat = set0;
2486           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2487         }
2488
2489       else if (((REG_P (SET_DEST (set0))
2490                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2491                 || (GET_CODE (SET_DEST (set0)) == SUBREG
2492                     && find_reg_note (i3, REG_UNUSED,
2493                                       SUBREG_REG (SET_DEST (set0)))))
2494                && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2495                    || INTVAL (XEXP (note, 0)) <= 0)
2496                && ! side_effects_p (SET_SRC (set0)))
2497         {
2498           newpat = set1;
2499           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2500
2501           if (insn_code_number >= 0)
2502             {
2503               /* If we will be able to accept this, we have made a
2504                  change to the destination of I3.  This requires us to
2505                  do a few adjustments.  */
2506
2507               PATTERN (i3) = newpat;
2508               adjust_for_new_dest (i3);
2509             }
2510         }
2511     }
2512
2513   /* If we were combining three insns and the result is a simple SET
2514      with no ASM_OPERANDS that wasn't recognized, try to split it into two
2515      insns.  There are two ways to do this.  It can be split using a
2516      machine-specific method (like when you have an addition of a large
2517      constant) or by combine in the function find_split_point.  */
2518
2519   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2520       && asm_noperands (newpat) < 0)
2521     {
2522       rtx m_split, *split;
2523
2524       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
2525          use I2DEST as a scratch register will help.  In the latter case,
2526          convert I2DEST to the mode of the source of NEWPAT if we can.  */
2527
2528       m_split = split_insns (newpat, i3);
2529
2530       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2531          inputs of NEWPAT.  */
2532
2533       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2534          possible to try that as a scratch reg.  This would require adding
2535          more code to make it work though.  */
2536
2537       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2538         {
2539           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2540
2541           /* First try to split using the original register as a
2542              scratch register.  */
2543           m_split = split_insns (gen_rtx_PARALLEL
2544                                  (VOIDmode,
2545                                   gen_rtvec (2, newpat,
2546                                              gen_rtx_CLOBBER (VOIDmode,
2547                                                               i2dest))),
2548                                  i3);
2549
2550           /* If that didn't work, try changing the mode of I2DEST if
2551              we can.  */
2552           if (m_split == 0
2553               && new_mode != GET_MODE (i2dest)
2554               && new_mode != VOIDmode
2555               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2556             {
2557               enum machine_mode old_mode = GET_MODE (i2dest);
2558               rtx ni2dest;
2559
2560               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2561                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2562               else
2563                 {
2564                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2565                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
2566                 }
2567
2568               m_split = split_insns (gen_rtx_PARALLEL
2569                                      (VOIDmode,
2570                                       gen_rtvec (2, newpat,
2571                                                  gen_rtx_CLOBBER (VOIDmode,
2572                                                                   ni2dest))),
2573                                      i3);
2574
2575               if (m_split == 0
2576                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2577                 {
2578                   struct undo *buf;
2579
2580                   PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2581                   buf = undobuf.undos;
2582                   undobuf.undos = buf->next;
2583                   buf->next = undobuf.frees;
2584                   undobuf.frees = buf;
2585                 }
2586             }
2587         }
2588
2589       /* If recog_for_combine has discarded clobbers, try to use them
2590          again for the split.  */
2591       if (m_split == 0 && newpat_vec_with_clobbers)
2592         m_split
2593           = split_insns (gen_rtx_PARALLEL (VOIDmode,
2594                                            newpat_vec_with_clobbers), i3);
2595
2596       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2597         {
2598           m_split = PATTERN (m_split);
2599           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2600           if (insn_code_number >= 0)
2601             newpat = m_split;
2602         }
2603       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2604                && (next_real_insn (i2) == i3
2605                    || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2606         {
2607           rtx i2set, i3set;
2608           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2609           newi2pat = PATTERN (m_split);
2610
2611           i3set = single_set (NEXT_INSN (m_split));
2612           i2set = single_set (m_split);
2613
2614           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2615
2616           /* If I2 or I3 has multiple SETs, we won't know how to track
2617              register status, so don't use these insns.  If I2's destination
2618              is used between I2 and I3, we also can't use these insns.  */
2619
2620           if (i2_code_number >= 0 && i2set && i3set
2621               && (next_real_insn (i2) == i3
2622                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2623             insn_code_number = recog_for_combine (&newi3pat, i3,
2624                                                   &new_i3_notes);
2625           if (insn_code_number >= 0)
2626             newpat = newi3pat;
2627
2628           /* It is possible that both insns now set the destination of I3.
2629              If so, we must show an extra use of it.  */
2630
2631           if (insn_code_number >= 0)
2632             {
2633               rtx new_i3_dest = SET_DEST (i3set);
2634               rtx new_i2_dest = SET_DEST (i2set);
2635
2636               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2637                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2638                      || GET_CODE (new_i3_dest) == SUBREG)
2639                 new_i3_dest = XEXP (new_i3_dest, 0);
2640
2641               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2642                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2643                      || GET_CODE (new_i2_dest) == SUBREG)
2644                 new_i2_dest = XEXP (new_i2_dest, 0);
2645
2646               if (REG_P (new_i3_dest)
2647                   && REG_P (new_i2_dest)
2648                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2649                 REG_N_SETS (REGNO (new_i2_dest))++;
2650             }
2651         }
2652
2653       /* If we can split it and use I2DEST, go ahead and see if that
2654          helps things be recognized.  Verify that none of the registers
2655          are set between I2 and I3.  */
2656       if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2657 #ifdef HAVE_cc0
2658           && REG_P (i2dest)
2659 #endif
2660           /* We need I2DEST in the proper mode.  If it is a hard register
2661              or the only use of a pseudo, we can change its mode.
2662              Make sure we don't change a hard register to have a mode that
2663              isn't valid for it, or change the number of registers.  */
2664           && (GET_MODE (*split) == GET_MODE (i2dest)
2665               || GET_MODE (*split) == VOIDmode
2666               || can_change_dest_mode (i2dest, added_sets_2,
2667                                        GET_MODE (*split)))
2668           && (next_real_insn (i2) == i3
2669               || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2670           /* We can't overwrite I2DEST if its value is still used by
2671              NEWPAT.  */
2672           && ! reg_referenced_p (i2dest, newpat))
2673         {
2674           rtx newdest = i2dest;
2675           enum rtx_code split_code = GET_CODE (*split);
2676           enum machine_mode split_mode = GET_MODE (*split);
2677           bool subst_done = false;
2678           newi2pat = NULL_RTX;
2679
2680           /* Get NEWDEST as a register in the proper mode.  We have already
2681              validated that we can do this.  */
2682           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2683             {
2684               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2685                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2686               else
2687                 {
2688                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2689                   newdest = regno_reg_rtx[REGNO (i2dest)];
2690                 }
2691             }
2692
2693           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2694              an ASHIFT.  This can occur if it was inside a PLUS and hence
2695              appeared to be a memory address.  This is a kludge.  */
2696           if (split_code == MULT
2697               && GET_CODE (XEXP (*split, 1)) == CONST_INT
2698               && INTVAL (XEXP (*split, 1)) > 0
2699               && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2700             {
2701               SUBST (*split, gen_rtx_ASHIFT (split_mode,
2702                                              XEXP (*split, 0), GEN_INT (i)));
2703               /* Update split_code because we may not have a multiply
2704                  anymore.  */
2705               split_code = GET_CODE (*split);
2706             }
2707
2708 #ifdef INSN_SCHEDULING
2709           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2710              be written as a ZERO_EXTEND.  */
2711           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2712             {
2713 #ifdef LOAD_EXTEND_OP
2714               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2715                  what it really is.  */
2716               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2717                   == SIGN_EXTEND)
2718                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2719                                                     SUBREG_REG (*split)));
2720               else
2721 #endif
2722                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2723                                                     SUBREG_REG (*split)));
2724             }
2725 #endif
2726
2727           /* Attempt to split binary operators using arithmetic identities.  */
2728           if (BINARY_P (SET_SRC (newpat))
2729               && split_mode == GET_MODE (SET_SRC (newpat))
2730               && ! side_effects_p (SET_SRC (newpat)))
2731             {
2732               rtx setsrc = SET_SRC (newpat);
2733               enum machine_mode mode = GET_MODE (setsrc);
2734               enum rtx_code code = GET_CODE (setsrc);
2735               rtx src_op0 = XEXP (setsrc, 0);
2736               rtx src_op1 = XEXP (setsrc, 1);
2737
2738               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
2739               if (rtx_equal_p (src_op0, src_op1))
2740                 {
2741                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2742                   SUBST (XEXP (setsrc, 0), newdest);
2743                   SUBST (XEXP (setsrc, 1), newdest);
2744                   subst_done = true;
2745                 }
2746               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
2747               else if ((code == PLUS || code == MULT)
2748                        && GET_CODE (src_op0) == code
2749                        && GET_CODE (XEXP (src_op0, 0)) == code
2750                        && (INTEGRAL_MODE_P (mode)
2751                            || (FLOAT_MODE_P (mode)
2752                                && flag_unsafe_math_optimizations)))
2753                 {
2754                   rtx p = XEXP (XEXP (src_op0, 0), 0);
2755                   rtx q = XEXP (XEXP (src_op0, 0), 1);
2756                   rtx r = XEXP (src_op0, 1);
2757                   rtx s = src_op1;
2758
2759                   /* Split both "((X op Y) op X) op Y" and
2760                      "((X op Y) op Y) op X" as "T op T" where T is
2761                      "X op Y".  */
2762                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2763                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2764                     {
2765                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
2766                                               XEXP (src_op0, 0));
2767                       SUBST (XEXP (setsrc, 0), newdest);
2768                       SUBST (XEXP (setsrc, 1), newdest);
2769                       subst_done = true;
2770                     }
2771                   /* Split "((X op X) op Y) op Y)" as "T op T" where
2772                      T is "X op Y".  */
2773                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2774                     {
2775                       rtx tmp = simplify_gen_binary (code, mode, p, r);
2776                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2777                       SUBST (XEXP (setsrc, 0), newdest);
2778                       SUBST (XEXP (setsrc, 1), newdest);
2779                       subst_done = true;
2780                     }
2781                 }
2782             }
2783
2784           if (!subst_done)
2785             {
2786               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2787               SUBST (*split, newdest);
2788             }
2789
2790           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2791
2792           /* recog_for_combine might have added CLOBBERs to newi2pat.
2793              Make sure NEWPAT does not depend on the clobbered regs.  */
2794           if (GET_CODE (newi2pat) == PARALLEL)
2795             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2796               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2797                 {
2798                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2799                   if (reg_overlap_mentioned_p (reg, newpat))
2800                     {
2801                       undo_all ();
2802                       return 0;
2803                     }
2804                 }
2805
2806           /* If the split point was a MULT and we didn't have one before,
2807              don't use one now.  */
2808           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2809             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2810         }
2811     }
2812
2813   /* Check for a case where we loaded from memory in a narrow mode and
2814      then sign extended it, but we need both registers.  In that case,
2815      we have a PARALLEL with both loads from the same memory location.
2816      We can split this into a load from memory followed by a register-register
2817      copy.  This saves at least one insn, more if register allocation can
2818      eliminate the copy.
2819
2820      We cannot do this if the destination of the first assignment is a
2821      condition code register or cc0.  We eliminate this case by making sure
2822      the SET_DEST and SET_SRC have the same mode.
2823
2824      We cannot do this if the destination of the second assignment is
2825      a register that we have already assumed is zero-extended.  Similarly
2826      for a SUBREG of such a register.  */
2827
2828   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2829            && GET_CODE (newpat) == PARALLEL
2830            && XVECLEN (newpat, 0) == 2
2831            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2832            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2833            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2834                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2835            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2836            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2837                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2838            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2839                                    INSN_CUID (i2))
2840            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2841            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2842            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2843                  (REG_P (temp)
2844                   && reg_stat[REGNO (temp)].nonzero_bits != 0
2845                   && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2846                   && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2847                   && (reg_stat[REGNO (temp)].nonzero_bits
2848                       != GET_MODE_MASK (word_mode))))
2849            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2850                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2851                      (REG_P (temp)
2852                       && reg_stat[REGNO (temp)].nonzero_bits != 0
2853                       && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2854                       && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2855                       && (reg_stat[REGNO (temp)].nonzero_bits
2856                           != GET_MODE_MASK (word_mode)))))
2857            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2858                                          SET_SRC (XVECEXP (newpat, 0, 1)))
2859            && ! find_reg_note (i3, REG_UNUSED,
2860                                SET_DEST (XVECEXP (newpat, 0, 0))))
2861     {
2862       rtx ni2dest;
2863
2864       newi2pat = XVECEXP (newpat, 0, 0);
2865       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2866       newpat = XVECEXP (newpat, 0, 1);
2867       SUBST (SET_SRC (newpat),
2868              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2869       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2870
2871       if (i2_code_number >= 0)
2872         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2873
2874       if (insn_code_number >= 0)
2875         swap_i2i3 = 1;
2876     }
2877
2878   /* Similarly, check for a case where we have a PARALLEL of two independent
2879      SETs but we started with three insns.  In this case, we can do the sets
2880      as two separate insns.  This case occurs when some SET allows two
2881      other insns to combine, but the destination of that SET is still live.  */
2882
2883   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2884            && GET_CODE (newpat) == PARALLEL
2885            && XVECLEN (newpat, 0) == 2
2886            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2887            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2888            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2889            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2890            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2891            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2892            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2893                                    INSN_CUID (i2))
2894            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2895                                   XVECEXP (newpat, 0, 0))
2896            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2897                                   XVECEXP (newpat, 0, 1))
2898            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2899                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2900     {
2901       /* Normally, it doesn't matter which of the two is done first,
2902          but it does if one references cc0.  In that case, it has to
2903          be first.  */
2904 #ifdef HAVE_cc0
2905       if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2906         {
2907           newi2pat = XVECEXP (newpat, 0, 0);
2908           newpat = XVECEXP (newpat, 0, 1);
2909         }
2910       else
2911 #endif
2912         {
2913           newi2pat = XVECEXP (newpat, 0, 1);
2914           newpat = XVECEXP (newpat, 0, 0);
2915         }
2916
2917       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2918
2919       if (i2_code_number >= 0)
2920         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2921     }
2922
2923   /* If it still isn't recognized, fail and change things back the way they
2924      were.  */
2925   if ((insn_code_number < 0
2926        /* Is the result a reasonable ASM_OPERANDS?  */
2927        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2928     {
2929       undo_all ();
2930       return 0;
2931     }
2932
2933   /* If we had to change another insn, make sure it is valid also.  */
2934   if (undobuf.other_insn)
2935     {
2936       rtx other_pat = PATTERN (undobuf.other_insn);
2937       rtx new_other_notes;
2938       rtx note, next;
2939
2940       CLEAR_HARD_REG_SET (newpat_used_regs);
2941
2942       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2943                                              &new_other_notes);
2944
2945       if (other_code_number < 0 && ! check_asm_operands (other_pat))
2946         {
2947           undo_all ();
2948           return 0;
2949         }
2950
2951       PATTERN (undobuf.other_insn) = other_pat;
2952
2953       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2954          are still valid.  Then add any non-duplicate notes added by
2955          recog_for_combine.  */
2956       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2957         {
2958           next = XEXP (note, 1);
2959
2960           if (REG_NOTE_KIND (note) == REG_UNUSED
2961               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2962             {
2963               if (REG_P (XEXP (note, 0)))
2964                 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2965
2966               remove_note (undobuf.other_insn, note);
2967             }
2968         }
2969
2970       for (note = new_other_notes; note; note = XEXP (note, 1))
2971         if (REG_P (XEXP (note, 0)))
2972           REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2973
2974       distribute_notes (new_other_notes, undobuf.other_insn,
2975                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2976     }
2977 #ifdef HAVE_cc0
2978   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2979      they are adjacent to each other or not.  */
2980   {
2981     rtx p = prev_nonnote_insn (i3);
2982     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2983         && sets_cc0_p (newi2pat))
2984       {
2985         undo_all ();
2986         return 0;
2987       }
2988   }
2989 #endif
2990
2991   /* Only allow this combination if insn_rtx_costs reports that the
2992      replacement instructions are cheaper than the originals.  */
2993   if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2994     {
2995       undo_all ();
2996       return 0;
2997     }
2998
2999   /* We now know that we can do this combination.  Merge the insns and
3000      update the status of registers and LOG_LINKS.  */
3001
3002   if (swap_i2i3)
3003     {
3004       rtx insn;
3005       rtx link;
3006       rtx ni2dest;
3007
3008       /* I3 now uses what used to be its destination and which is now
3009          I2's destination.  This requires us to do a few adjustments.  */
3010       PATTERN (i3) = newpat;
3011       adjust_for_new_dest (i3);
3012
3013       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3014          so we still will.
3015
3016          However, some later insn might be using I2's dest and have
3017          a LOG_LINK pointing at I3.  We must remove this link.
3018          The simplest way to remove the link is to point it at I1,
3019          which we know will be a NOTE.  */
3020
3021       /* newi2pat is usually a SET here; however, recog_for_combine might
3022          have added some clobbers.  */
3023       if (GET_CODE (newi2pat) == PARALLEL)
3024         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3025       else
3026         ni2dest = SET_DEST (newi2pat);
3027
3028       for (insn = NEXT_INSN (i3);
3029            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3030                     || insn != BB_HEAD (this_basic_block->next_bb));
3031            insn = NEXT_INSN (insn))
3032         {
3033           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3034             {
3035               for (link = LOG_LINKS (insn); link;
3036                    link = XEXP (link, 1))
3037                 if (XEXP (link, 0) == i3)
3038                   XEXP (link, 0) = i1;
3039
3040               break;
3041             }
3042         }
3043     }
3044
3045   {
3046     rtx i3notes, i2notes, i1notes = 0;
3047     rtx i3links, i2links, i1links = 0;
3048     rtx midnotes = 0;
3049     unsigned int regno;
3050     /* Compute which registers we expect to eliminate.  newi2pat may be setting
3051        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
3052        same as i3dest, in which case newi2pat may be setting i1dest.  */
3053     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3054                    || i2dest_in_i2src || i2dest_in_i1src
3055                    || !i2dest_killed
3056                    ? 0 : i2dest);
3057     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3058                    || (newi2pat && reg_set_p (i1dest, newi2pat))
3059                    || !i1dest_killed
3060                    ? 0 : i1dest);
3061
3062     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3063        clear them.  */
3064     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3065     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3066     if (i1)
3067       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3068
3069     /* Ensure that we do not have something that should not be shared but
3070        occurs multiple times in the new insns.  Check this by first
3071        resetting all the `used' flags and then copying anything is shared.  */
3072
3073     reset_used_flags (i3notes);
3074     reset_used_flags (i2notes);
3075     reset_used_flags (i1notes);
3076     reset_used_flags (newpat);
3077     reset_used_flags (newi2pat);
3078     if (undobuf.other_insn)
3079       reset_used_flags (PATTERN (undobuf.other_insn));
3080
3081     i3notes = copy_rtx_if_shared (i3notes);
3082     i2notes = copy_rtx_if_shared (i2notes);
3083     i1notes = copy_rtx_if_shared (i1notes);
3084     newpat = copy_rtx_if_shared (newpat);
3085     newi2pat = copy_rtx_if_shared (newi2pat);
3086     if (undobuf.other_insn)
3087       reset_used_flags (PATTERN (undobuf.other_insn));
3088
3089     INSN_CODE (i3) = insn_code_number;
3090     PATTERN (i3) = newpat;
3091
3092     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3093       {
3094         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3095
3096         reset_used_flags (call_usage);
3097         call_usage = copy_rtx (call_usage);
3098
3099         if (substed_i2)
3100           replace_rtx (call_usage, i2dest, i2src);
3101
3102         if (substed_i1)
3103           replace_rtx (call_usage, i1dest, i1src);
3104
3105         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3106       }
3107
3108     if (undobuf.other_insn)
3109       INSN_CODE (undobuf.other_insn) = other_code_number;
3110
3111     /* We had one special case above where I2 had more than one set and
3112        we replaced a destination of one of those sets with the destination
3113        of I3.  In that case, we have to update LOG_LINKS of insns later
3114        in this basic block.  Note that this (expensive) case is rare.
3115
3116        Also, in this case, we must pretend that all REG_NOTEs for I2
3117        actually came from I3, so that REG_UNUSED notes from I2 will be
3118        properly handled.  */
3119
3120     if (i3_subst_into_i2)
3121       {
3122         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3123           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3124                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3125               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3126               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3127               && ! find_reg_note (i2, REG_UNUSED,
3128                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3129             for (temp = NEXT_INSN (i2);
3130                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3131                           || BB_HEAD (this_basic_block) != temp);
3132                  temp = NEXT_INSN (temp))
3133               if (temp != i3 && INSN_P (temp))
3134                 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3135                   if (XEXP (link, 0) == i2)
3136                     XEXP (link, 0) = i3;
3137
3138         if (i3notes)
3139           {
3140             rtx link = i3notes;
3141             while (XEXP (link, 1))
3142               link = XEXP (link, 1);
3143             XEXP (link, 1) = i2notes;
3144           }
3145         else
3146           i3notes = i2notes;
3147         i2notes = 0;
3148       }
3149
3150     LOG_LINKS (i3) = 0;
3151     REG_NOTES (i3) = 0;
3152     LOG_LINKS (i2) = 0;
3153     REG_NOTES (i2) = 0;
3154
3155     if (newi2pat)
3156       {
3157         INSN_CODE (i2) = i2_code_number;
3158         PATTERN (i2) = newi2pat;
3159       }
3160     else
3161       SET_INSN_DELETED (i2);
3162
3163     if (i1)
3164       {
3165         LOG_LINKS (i1) = 0;
3166         REG_NOTES (i1) = 0;
3167         SET_INSN_DELETED (i1);
3168       }
3169
3170     /* Get death notes for everything that is now used in either I3 or
3171        I2 and used to die in a previous insn.  If we built two new
3172        patterns, move from I1 to I2 then I2 to I3 so that we get the
3173        proper movement on registers that I2 modifies.  */
3174
3175     if (newi2pat)
3176       {
3177         move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3178         move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3179       }
3180     else
3181       move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3182                    i3, &midnotes);
3183
3184     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
3185     if (i3notes)
3186       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3187                         elim_i2, elim_i1);
3188     if (i2notes)
3189       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3190                         elim_i2, elim_i1);
3191     if (i1notes)
3192       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3193                         elim_i2, elim_i1);
3194     if (midnotes)
3195       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3196                         elim_i2, elim_i1);
3197
3198     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
3199        know these are REG_UNUSED and want them to go to the desired insn,
3200        so we always pass it as i3.  We have not counted the notes in
3201        reg_n_deaths yet, so we need to do so now.  */
3202
3203     if (newi2pat && new_i2_notes)
3204       {
3205         for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3206           if (REG_P (XEXP (temp, 0)))
3207             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3208
3209         distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3210       }
3211
3212     if (new_i3_notes)
3213       {
3214         for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3215           if (REG_P (XEXP (temp, 0)))
3216             REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3217
3218         distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3219       }
3220
3221     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
3222        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
3223        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
3224        in that case, it might delete I2.  Similarly for I2 and I1.
3225        Show an additional death due to the REG_DEAD note we make here.  If
3226        we discard it in distribute_notes, we will decrement it again.  */
3227
3228     if (i3dest_killed)
3229       {
3230         if (REG_P (i3dest_killed))
3231           REG_N_DEATHS (REGNO (i3dest_killed))++;
3232
3233         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3234           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3235                                                NULL_RTX),
3236                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3237         else
3238           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3239                                                NULL_RTX),
3240                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3241                             elim_i2, elim_i1);
3242       }
3243
3244     if (i2dest_in_i2src)
3245       {
3246         if (REG_P (i2dest))
3247           REG_N_DEATHS (REGNO (i2dest))++;
3248
3249         if (newi2pat && reg_set_p (i2dest, newi2pat))
3250           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3251                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3252         else
3253           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3254                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3255                             NULL_RTX, NULL_RTX);
3256       }
3257
3258     if (i1dest_in_i1src)
3259       {
3260         if (REG_P (i1dest))
3261           REG_N_DEATHS (REGNO (i1dest))++;
3262
3263         if (newi2pat && reg_set_p (i1dest, newi2pat))
3264           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3265                             NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3266         else
3267           distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3268                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3269                             NULL_RTX, NULL_RTX);
3270       }
3271
3272     distribute_links (i3links);
3273     distribute_links (i2links);
3274     distribute_links (i1links);
3275
3276     if (REG_P (i2dest))
3277       {
3278         rtx link;
3279         rtx i2_insn = 0, i2_val = 0, set;
3280
3281         /* The insn that used to set this register doesn't exist, and
3282            this life of the register may not exist either.  See if one of
3283            I3's links points to an insn that sets I2DEST.  If it does,
3284            that is now the last known value for I2DEST. If we don't update
3285            this and I2 set the register to a value that depended on its old
3286            contents, we will get confused.  If this insn is used, thing
3287            will be set correctly in combine_instructions.  */
3288
3289         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3290           if ((set = single_set (XEXP (link, 0))) != 0
3291               && rtx_equal_p (i2dest, SET_DEST (set)))
3292             i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3293
3294         record_value_for_reg (i2dest, i2_insn, i2_val);
3295
3296         /* If the reg formerly set in I2 died only once and that was in I3,
3297            zero its use count so it won't make `reload' do any work.  */
3298         if (! added_sets_2
3299             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3300             && ! i2dest_in_i2src)
3301           {
3302             regno = REGNO (i2dest);
3303             REG_N_SETS (regno)--;
3304           }
3305       }
3306
3307     if (i1 && REG_P (i1dest))
3308       {
3309         rtx link;
3310         rtx i1_insn = 0, i1_val = 0, set;
3311
3312         for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3313           if ((set = single_set (XEXP (link, 0))) != 0
3314               && rtx_equal_p (i1dest, SET_DEST (set)))
3315             i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3316
3317         record_value_for_reg (i1dest, i1_insn, i1_val);
3318
3319         regno = REGNO (i1dest);
3320         if (! added_sets_1 && ! i1dest_in_i1src)
3321           REG_N_SETS (regno)--;
3322       }
3323
3324     /* Update reg_stat[].nonzero_bits et al for any changes that may have
3325        been made to this insn.  The order of
3326        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
3327        can affect nonzero_bits of newpat */
3328     if (newi2pat)
3329       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3330     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3331
3332     /* Set new_direct_jump_p if a new return or simple jump instruction
3333        has been created.
3334
3335        If I3 is now an unconditional jump, ensure that it has a
3336        BARRIER following it since it may have initially been a
3337        conditional jump.  It may also be the last nonnote insn.  */
3338
3339     if (returnjump_p (i3) || any_uncondjump_p (i3))
3340       {
3341         *new_direct_jump_p = 1;
3342         mark_jump_label (PATTERN (i3), i3, 0);
3343
3344         if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3345             || !BARRIER_P (temp))
3346           emit_barrier_after (i3);
3347       }
3348
3349     if (undobuf.other_insn != NULL_RTX
3350         && (returnjump_p (undobuf.other_insn)
3351             || any_uncondjump_p (undobuf.other_insn)))
3352       {
3353         *new_direct_jump_p = 1;
3354
3355         if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3356             || !BARRIER_P (temp))
3357           emit_barrier_after (undobuf.other_insn);
3358       }
3359
3360     /* An NOOP jump does not need barrier, but it does need cleaning up
3361        of CFG.  */
3362     if (GET_CODE (newpat) == SET
3363         && SET_SRC (newpat) == pc_rtx
3364         && SET_DEST (newpat) == pc_rtx)
3365       *new_direct_jump_p = 1;
3366   }
3367
3368   combine_successes++;
3369   undo_commit ();
3370
3371   if (added_links_insn
3372       && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3373       && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3374     return added_links_insn;
3375   else
3376     return newi2pat ? i2 : i3;
3377 }
3378 \f
3379 /* Undo all the modifications recorded in undobuf.  */
3380
3381 static void
3382 undo_all (void)
3383 {
3384   struct undo *undo, *next;
3385
3386   for (undo = undobuf.undos; undo; undo = next)
3387     {
3388       next = undo->next;
3389       switch (undo->kind)
3390         {
3391         case UNDO_RTX:
3392           *undo->where.r = undo->old_contents.r;
3393           break;
3394         case UNDO_INT:
3395           *undo->where.i = undo->old_contents.i;
3396           break;
3397         case UNDO_MODE:
3398           PUT_MODE (*undo->where.r, undo->old_contents.m);
3399           break;
3400         default:
3401           gcc_unreachable ();
3402         }
3403
3404       undo->next = undobuf.frees;
3405       undobuf.frees = undo;
3406     }
3407
3408   undobuf.undos = 0;
3409 }
3410
3411 /* We've committed to accepting the changes we made.  Move all
3412    of the undos to the free list.  */
3413
3414 static void
3415 undo_commit (void)
3416 {
3417   struct undo *undo, *next;
3418
3419   for (undo = undobuf.undos; undo; undo = next)
3420     {
3421       next = undo->next;
3422       undo->next = undobuf.frees;
3423       undobuf.frees = undo;
3424     }
3425   undobuf.undos = 0;
3426 }
3427
3428 \f
3429 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3430    where we have an arithmetic expression and return that point.  LOC will
3431    be inside INSN.
3432
3433    try_combine will call this function to see if an insn can be split into
3434    two insns.  */
3435
3436 static rtx *
3437 find_split_point (rtx *loc, rtx insn)
3438 {
3439   rtx x = *loc;
3440   enum rtx_code code = GET_CODE (x);
3441   rtx *split;
3442   unsigned HOST_WIDE_INT len = 0;
3443   HOST_WIDE_INT pos = 0;
3444   int unsignedp = 0;
3445   rtx inner = NULL_RTX;
3446
3447   /* First special-case some codes.  */
3448   switch (code)
3449     {
3450     case SUBREG:
3451 #ifdef INSN_SCHEDULING
3452       /* If we are making a paradoxical SUBREG invalid, it becomes a split
3453          point.  */
3454       if (MEM_P (SUBREG_REG (x)))
3455         return loc;
3456 #endif
3457       return find_split_point (&SUBREG_REG (x), insn);
3458
3459     case MEM:
3460 #ifdef HAVE_lo_sum
3461       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3462          using LO_SUM and HIGH.  */
3463       if (GET_CODE (XEXP (x, 0)) == CONST
3464           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3465         {
3466           SUBST (XEXP (x, 0),
3467                  gen_rtx_LO_SUM (Pmode,
3468                                  gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3469                                  XEXP (x, 0)));
3470           return &XEXP (XEXP (x, 0), 0);
3471         }
3472 #endif
3473
3474       /* If we have a PLUS whose second operand is a constant and the
3475          address is not valid, perhaps will can split it up using
3476          the machine-specific way to split large constants.  We use
3477          the first pseudo-reg (one of the virtual regs) as a placeholder;
3478          it will not remain in the result.  */
3479       if (GET_CODE (XEXP (x, 0)) == PLUS
3480           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3481           && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3482         {
3483           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3484           rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3485                                  subst_insn);
3486
3487           /* This should have produced two insns, each of which sets our
3488              placeholder.  If the source of the second is a valid address,
3489              we can make put both sources together and make a split point
3490              in the middle.  */
3491
3492           if (seq
3493               && NEXT_INSN (seq) != NULL_RTX
3494               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3495               && NONJUMP_INSN_P (seq)
3496               && GET_CODE (PATTERN (seq)) == SET
3497               && SET_DEST (PATTERN (seq)) == reg
3498               && ! reg_mentioned_p (reg,
3499                                     SET_SRC (PATTERN (seq)))
3500               && NONJUMP_INSN_P (NEXT_INSN (seq))
3501               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3502               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3503               && memory_address_p (GET_MODE (x),
3504                                    SET_SRC (PATTERN (NEXT_INSN (seq)))))
3505             {
3506               rtx src1 = SET_SRC (PATTERN (seq));
3507               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3508
3509               /* Replace the placeholder in SRC2 with SRC1.  If we can
3510                  find where in SRC2 it was placed, that can become our
3511                  split point and we can replace this address with SRC2.
3512                  Just try two obvious places.  */
3513
3514               src2 = replace_rtx (src2, reg, src1);
3515               split = 0;
3516               if (XEXP (src2, 0) == src1)
3517                 split = &XEXP (src2, 0);
3518               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3519                        && XEXP (XEXP (src2, 0), 0) == src1)
3520                 split = &XEXP (XEXP (src2, 0), 0);
3521
3522               if (split)
3523                 {
3524                   SUBST (XEXP (x, 0), src2);
3525                   return split;
3526                 }
3527             }
3528
3529           /* If that didn't work, perhaps the first operand is complex and
3530              needs to be computed separately, so make a split point there.
3531              This will occur on machines that just support REG + CONST
3532              and have a constant moved through some previous computation.  */
3533
3534           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3535                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3536                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3537             return &XEXP (XEXP (x, 0), 0);
3538         }
3539       break;
3540
3541     case SET:
3542 #ifdef HAVE_cc0
3543       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3544          ZERO_EXTRACT, the most likely reason why this doesn't match is that
3545          we need to put the operand into a register.  So split at that
3546          point.  */
3547
3548       if (SET_DEST (x) == cc0_rtx
3549           && GET_CODE (SET_SRC (x)) != COMPARE
3550           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3551           && !OBJECT_P (SET_SRC (x))
3552           && ! (GET_CODE (SET_SRC (x)) == SUBREG
3553                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3554         return &SET_SRC (x);
3555 #endif
3556
3557       /* See if we can split SET_SRC as it stands.  */
3558       split = find_split_point (&SET_SRC (x), insn);
3559       if (split && split != &SET_SRC (x))
3560         return split;
3561
3562       /* See if we can split SET_DEST as it stands.  */
3563       split = find_split_point (&SET_DEST (x), insn);
3564       if (split && split != &SET_DEST (x))
3565         return split;
3566
3567       /* See if this is a bitfield assignment with everything constant.  If
3568          so, this is an IOR of an AND, so split it into that.  */
3569       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3570           && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3571               <= HOST_BITS_PER_WIDE_INT)
3572           && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3573           && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3574           && GET_CODE (SET_SRC (x)) == CONST_INT
3575           && ((INTVAL (XEXP (SET_DEST (x), 1))
3576                + INTVAL (XEXP (SET_DEST (x), 2)))
3577               <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3578           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3579         {
3580           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3581           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3582           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3583           rtx dest = XEXP (SET_DEST (x), 0);
3584           enum machine_mode mode = GET_MODE (dest);
3585           unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3586           rtx or_mask;
3587
3588           if (BITS_BIG_ENDIAN)
3589             pos = GET_MODE_BITSIZE (mode) - len - pos;
3590
3591           or_mask = gen_int_mode (src << pos, mode);
3592           if (src == mask)
3593             SUBST (SET_SRC (x),
3594                    simplify_gen_binary (IOR, mode, dest, or_mask));
3595           else
3596             {
3597               rtx negmask = gen_int_mode (~(mask << pos), mode);
3598               SUBST (SET_SRC (x),
3599                      simplify_gen_binary (IOR, mode,
3600                                           simplify_gen_binary (AND, mode,
3601                                                                dest, negmask),
3602                                           or_mask));
3603             }
3604
3605           SUBST (SET_DEST (x), dest);
3606
3607           split = find_split_point (&SET_SRC (x), insn);
3608           if (split && split != &SET_SRC (x))
3609             return split;
3610         }
3611
3612       /* Otherwise, see if this is an operation that we can split into two.
3613          If so, try to split that.  */
3614       code = GET_CODE (SET_SRC (x));
3615
3616       switch (code)
3617         {
3618         case AND:
3619           /* If we are AND'ing with a large constant that is only a single
3620              bit and the result is only being used in a context where we
3621              need to know if it is zero or nonzero, replace it with a bit
3622              extraction.  This will avoid the large constant, which might
3623              have taken more than one insn to make.  If the constant were
3624              not a valid argument to the AND but took only one insn to make,
3625              this is no worse, but if it took more than one insn, it will
3626              be better.  */
3627
3628           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3629               && REG_P (XEXP (SET_SRC (x), 0))
3630               && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3631               && REG_P (SET_DEST (x))
3632               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3633               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3634               && XEXP (*split, 0) == SET_DEST (x)
3635               && XEXP (*split, 1) == const0_rtx)
3636             {
3637               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3638                                                 XEXP (SET_SRC (x), 0),
3639                                                 pos, NULL_RTX, 1, 1, 0, 0);
3640               if (extraction != 0)
3641                 {
3642                   SUBST (SET_SRC (x), extraction);
3643                   return find_split_point (loc, insn);
3644                 }
3645             }
3646           break;
3647
3648         case NE:
3649           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3650              is known to be on, this can be converted into a NEG of a shift.  */
3651           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3652               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3653               && 1 <= (pos = exact_log2
3654                        (nonzero_bits (XEXP (SET_SRC (x), 0),
3655                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
3656             {
3657               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3658
3659               SUBST (SET_SRC (x),
3660                      gen_rtx_NEG (mode,
3661                                   gen_rtx_LSHIFTRT (mode,
3662                                                     XEXP (SET_SRC (x), 0),
3663                                                     GEN_INT (pos))));
3664
3665               split = find_split_point (&SET_SRC (x), insn);
3666               if (split && split != &SET_SRC (x))
3667                 return split;
3668             }
3669           break;
3670
3671         case SIGN_EXTEND:
3672           inner = XEXP (SET_SRC (x), 0);
3673
3674           /* We can't optimize if either mode is a partial integer
3675              mode as we don't know how many bits are significant
3676              in those modes.  */
3677           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3678               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3679             break;
3680
3681           pos = 0;
3682           len = GET_MODE_BITSIZE (GET_MODE (inner));
3683           unsignedp = 0;
3684           break;
3685
3686         case SIGN_EXTRACT:
3687         case ZERO_EXTRACT:
3688           if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3689               && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3690             {
3691               inner = XEXP (SET_SRC (x), 0);
3692               len = INTVAL (XEXP (SET_SRC (x), 1));
3693               pos = INTVAL (XEXP (SET_SRC (x), 2));
3694
3695               if (BITS_BIG_ENDIAN)
3696                 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3697               unsignedp = (code == ZERO_EXTRACT);
3698             }
3699           break;
3700
3701         default:
3702           break;
3703         }
3704
3705       if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3706         {
3707           enum machine_mode mode = GET_MODE (SET_SRC (x));
3708
3709           /* For unsigned, we have a choice of a shift followed by an
3710              AND or two shifts.  Use two shifts for field sizes where the
3711              constant might be too large.  We assume here that we can
3712              always at least get 8-bit constants in an AND insn, which is
3713              true for every current RISC.  */
3714
3715           if (unsignedp && len <= 8)
3716             {
3717               SUBST (SET_SRC (x),
3718                      gen_rtx_AND (mode,
3719                                   gen_rtx_LSHIFTRT
3720                                   (mode, gen_lowpart (mode, inner),
3721                                    GEN_INT (pos)),
3722                                   GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3723
3724               split = find_split_point (&SET_SRC (x), insn);
3725               if (split && split != &SET_SRC (x))
3726                 return split;
3727             }
3728           else
3729             {
3730               SUBST (SET_SRC (x),
3731                      gen_rtx_fmt_ee
3732                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3733                       gen_rtx_ASHIFT (mode,
3734                                       gen_lowpart (mode, inner),
3735                                       GEN_INT (GET_MODE_BITSIZE (mode)
3736                                                - len - pos)),
3737                       GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3738
3739               split = find_split_point (&SET_SRC (x), insn);
3740               if (split && split != &SET_SRC (x))
3741                 return split;
3742             }
3743         }
3744
3745       /* See if this is a simple operation with a constant as the second
3746          operand.  It might be that this constant is out of range and hence
3747          could be used as a split point.  */
3748       if (BINARY_P (SET_SRC (x))
3749           && CONSTANT_P (XEXP (SET_SRC (x), 1))
3750           && (OBJECT_P (XEXP (SET_SRC (x), 0))
3751               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3752                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3753         return &XEXP (SET_SRC (x), 1);
3754
3755       /* Finally, see if this is a simple operation with its first operand
3756          not in a register.  The operation might require this operand in a
3757          register, so return it as a split point.  We can always do this
3758          because if the first operand were another operation, we would have
3759          already found it as a split point.  */
3760       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3761           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3762         return &XEXP (SET_SRC (x), 0);
3763
3764       return 0;
3765
3766     case AND:
3767     case IOR:
3768       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3769          it is better to write this as (not (ior A B)) so we can split it.
3770          Similarly for IOR.  */
3771       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3772         {
3773           SUBST (*loc,
3774                  gen_rtx_NOT (GET_MODE (x),
3775                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3776                                               GET_MODE (x),
3777                                               XEXP (XEXP (x, 0), 0),
3778                                               XEXP (XEXP (x, 1), 0))));
3779           return find_split_point (loc, insn);
3780         }
3781
3782       /* Many RISC machines have a large set of logical insns.  If the
3783          second operand is a NOT, put it first so we will try to split the
3784          other operand first.  */
3785       if (GET_CODE (XEXP (x, 1)) == NOT)
3786         {
3787           rtx tem = XEXP (x, 0);
3788           SUBST (XEXP (x, 0), XEXP (x, 1));
3789           SUBST (XEXP (x, 1), tem);
3790         }
3791       break;
3792
3793     default:
3794       break;
3795     }
3796
3797   /* Otherwise, select our actions depending on our rtx class.  */
3798   switch (GET_RTX_CLASS (code))
3799     {
3800     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
3801     case RTX_TERNARY:
3802       split = find_split_point (&XEXP (x, 2), insn);
3803       if (split)
3804         return split;
3805       /* ... fall through ...  */
3806     case RTX_BIN_ARITH:
3807     case RTX_COMM_ARITH:
3808     case RTX_COMPARE:
3809     case RTX_COMM_COMPARE:
3810       split = find_split_point (&XEXP (x, 1), insn);
3811       if (split)
3812         return split;
3813       /* ... fall through ...  */
3814     case RTX_UNARY:
3815       /* Some machines have (and (shift ...) ...) insns.  If X is not
3816          an AND, but XEXP (X, 0) is, use it as our split point.  */
3817       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3818         return &XEXP (x, 0);
3819
3820       split = find_split_point (&XEXP (x, 0), insn);
3821       if (split)
3822         return split;
3823       return loc;
3824
3825     default:
3826       /* Otherwise, we don't have a split point.  */
3827       return 0;
3828     }
3829 }
3830 \f
3831 /* Throughout X, replace FROM with TO, and return the result.
3832    The result is TO if X is FROM;
3833    otherwise the result is X, but its contents may have been modified.
3834    If they were modified, a record was made in undobuf so that
3835    undo_all will (among other things) return X to its original state.
3836
3837    If the number of changes necessary is too much to record to undo,
3838    the excess changes are not made, so the result is invalid.
3839    The changes already made can still be undone.
3840    undobuf.num_undo is incremented for such changes, so by testing that
3841    the caller can tell whether the result is valid.
3842
3843    `n_occurrences' is incremented each time FROM is replaced.
3844
3845    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3846
3847    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
3848    by copying if `n_occurrences' is nonzero.  */
3849
3850 static rtx
3851 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3852 {
3853   enum rtx_code code = GET_CODE (x);
3854   enum machine_mode op0_mode = VOIDmode;
3855   const char *fmt;
3856   int len, i;
3857   rtx new;
3858
3859 /* Two expressions are equal if they are identical copies of a shared
3860    RTX or if they are both registers with the same register number
3861    and mode.  */
3862
3863 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
3864   ((X) == (Y)                                           \
3865    || (REG_P (X) && REG_P (Y)   \
3866        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3867
3868   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3869     {
3870       n_occurrences++;
3871       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3872     }
3873
3874   /* If X and FROM are the same register but different modes, they will
3875      not have been seen as equal above.  However, flow.c will make a
3876      LOG_LINKS entry for that case.  If we do nothing, we will try to
3877      rerecognize our original insn and, when it succeeds, we will
3878      delete the feeding insn, which is incorrect.
3879
3880      So force this insn not to match in this (rare) case.  */
3881   if (! in_dest && code == REG && REG_P (from)
3882       && REGNO (x) == REGNO (from))
3883     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3884
3885   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3886      of which may contain things that can be combined.  */
3887   if (code != MEM && code != LO_SUM && OBJECT_P (x))
3888     return x;
3889
3890   /* It is possible to have a subexpression appear twice in the insn.
3891      Suppose that FROM is a register that appears within TO.
3892      Then, after that subexpression has been scanned once by `subst',
3893      the second time it is scanned, TO may be found.  If we were
3894      to scan TO here, we would find FROM within it and create a
3895      self-referent rtl structure which is completely wrong.  */
3896   if (COMBINE_RTX_EQUAL_P (x, to))
3897     return to;
3898
3899   /* Parallel asm_operands need special attention because all of the
3900      inputs are shared across the arms.  Furthermore, unsharing the
3901      rtl results in recognition failures.  Failure to handle this case
3902      specially can result in circular rtl.
3903
3904      Solve this by doing a normal pass across the first entry of the
3905      parallel, and only processing the SET_DESTs of the subsequent
3906      entries.  Ug.  */
3907
3908   if (code == PARALLEL
3909       && GET_CODE (XVECEXP (x, 0, 0)) == SET
3910       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3911     {
3912       new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3913
3914       /* If this substitution failed, this whole thing fails.  */
3915       if (GET_CODE (new) == CLOBBER
3916           && XEXP (new, 0) == const0_rtx)
3917         return new;
3918
3919       SUBST (XVECEXP (x, 0, 0), new);
3920
3921       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3922         {
3923           rtx dest = SET_DEST (XVECEXP (x, 0, i));
3924
3925           if (!REG_P (dest)
3926               && GET_CODE (dest) != CC0
3927               && GET_CODE (dest) != PC)
3928             {
3929               new = subst (dest, from, to, 0, unique_copy);
3930
3931               /* If this substitution failed, this whole thing fails.  */
3932               if (GET_CODE (new) == CLOBBER
3933                   && XEXP (new, 0) == const0_rtx)
3934                 return new;
3935
3936               SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3937             }
3938         }
3939     }
3940   else
3941     {
3942       len = GET_RTX_LENGTH (code);
3943       fmt = GET_RTX_FORMAT (code);
3944
3945       /* We don't need to process a SET_DEST that is a register, CC0,
3946          or PC, so set up to skip this common case.  All other cases
3947          where we want to suppress replacing something inside a
3948          SET_SRC are handled via the IN_DEST operand.  */
3949       if (code == SET
3950           && (REG_P (SET_DEST (x))
3951               || GET_CODE (SET_DEST (x)) == CC0
3952               || GET_CODE (SET_DEST (x)) == PC))
3953         fmt = "ie";
3954
3955       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3956          constant.  */
3957       if (fmt[0] == 'e')
3958         op0_mode = GET_MODE (XEXP (x, 0));
3959
3960       for (i = 0; i < len; i++)
3961         {
3962           if (fmt[i] == 'E')
3963             {
3964               int j;
3965               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3966                 {
3967                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3968                     {
3969                       new = (unique_copy && n_occurrences
3970                              ? copy_rtx (to) : to);
3971                       n_occurrences++;
3972                     }
3973                   else
3974                     {
3975                       new = subst (XVECEXP (x, i, j), from, to, 0,
3976                                    unique_copy);
3977
3978                       /* If this substitution failed, this whole thing
3979                          fails.  */
3980                       if (GET_CODE (new) == CLOBBER
3981                           && XEXP (new, 0) == const0_rtx)
3982                         return new;
3983                     }
3984
3985                   SUBST (XVECEXP (x, i, j), new);
3986                 }
3987             }
3988           else if (fmt[i] == 'e')
3989             {
3990               /* If this is a register being set, ignore it.  */
3991               new = XEXP (x, i);
3992               if (in_dest
3993                   && i == 0
3994                   && (((code == SUBREG || code == ZERO_EXTRACT)
3995                        && REG_P (new))
3996                       || code == STRICT_LOW_PART))
3997                 ;
3998
3999               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4000                 {
4001                   /* In general, don't install a subreg involving two
4002                      modes not tieable.  It can worsen register
4003                      allocation, and can even make invalid reload
4004                      insns, since the reg inside may need to be copied
4005                      from in the outside mode, and that may be invalid
4006                      if it is an fp reg copied in integer mode.
4007
4008                      We allow two exceptions to this: It is valid if
4009                      it is inside another SUBREG and the mode of that
4010                      SUBREG and the mode of the inside of TO is
4011                      tieable and it is valid if X is a SET that copies
4012                      FROM to CC0.  */
4013
4014                   if (GET_CODE (to) == SUBREG
4015                       && ! MODES_TIEABLE_P (GET_MODE (to),
4016                                             GET_MODE (SUBREG_REG (to)))
4017                       && ! (code == SUBREG
4018                             && MODES_TIEABLE_P (GET_MODE (x),
4019                                                 GET_MODE (SUBREG_REG (to))))
4020 #ifdef HAVE_cc0
4021                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4022 #endif
4023                       )
4024                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4025
4026 #ifdef CANNOT_CHANGE_MODE_CLASS
4027                   if (code == SUBREG
4028                       && REG_P (to)
4029                       && REGNO (to) < FIRST_PSEUDO_REGISTER
4030                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4031                                                    GET_MODE (to),
4032                                                    GET_MODE (x)))
4033                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4034 #endif
4035
4036                   new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4037                   n_occurrences++;
4038                 }
4039               else
4040                 /* If we are in a SET_DEST, suppress most cases unless we
4041                    have gone inside a MEM, in which case we want to
4042                    simplify the address.  We assume here that things that
4043                    are actually part of the destination have their inner
4044                    parts in the first expression.  This is true for SUBREG,
4045                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4046                    things aside from REG and MEM that should appear in a
4047                    SET_DEST.  */
4048                 new = subst (XEXP (x, i), from, to,
4049                              (((in_dest
4050                                 && (code == SUBREG || code == STRICT_LOW_PART
4051                                     || code == ZERO_EXTRACT))
4052                                || code == SET)
4053                               && i == 0), unique_copy);
4054
4055               /* If we found that we will have to reject this combination,
4056                  indicate that by returning the CLOBBER ourselves, rather than
4057                  an expression containing it.  This will speed things up as
4058                  well as prevent accidents where two CLOBBERs are considered
4059                  to be equal, thus producing an incorrect simplification.  */
4060
4061               if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4062                 return new;
4063
4064               if (GET_CODE (x) == SUBREG
4065                   && (GET_CODE (new) == CONST_INT
4066                       || GET_CODE (new) == CONST_DOUBLE))
4067                 {
4068                   enum machine_mode mode = GET_MODE (x);
4069
4070                   x = simplify_subreg (GET_MODE (x), new,
4071                                        GET_MODE (SUBREG_REG (x)),
4072                                        SUBREG_BYTE (x));
4073                   if (! x)
4074                     x = gen_rtx_CLOBBER (mode, const0_rtx);
4075                 }
4076               else if (GET_CODE (new) == CONST_INT
4077                        && GET_CODE (x) == ZERO_EXTEND)
4078                 {
4079                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4080                                                 new, GET_MODE (XEXP (x, 0)));
4081                   gcc_assert (x);
4082                 }
4083               else
4084                 SUBST (XEXP (x, i), new);
4085             }
4086         }
4087     }
4088
4089   /* Try to simplify X.  If the simplification changed the code, it is likely
4090      that further simplification will help, so loop, but limit the number
4091      of repetitions that will be performed.  */
4092
4093   for (i = 0; i < 4; i++)
4094     {
4095       /* If X is sufficiently simple, don't bother trying to do anything
4096          with it.  */
4097       if (code != CONST_INT && code != REG && code != CLOBBER)
4098         x = combine_simplify_rtx (x, op0_mode, in_dest);
4099
4100       if (GET_CODE (x) == code)
4101         break;
4102
4103       code = GET_CODE (x);
4104
4105       /* We no longer know the original mode of operand 0 since we
4106          have changed the form of X)  */
4107       op0_mode = VOIDmode;
4108     }
4109
4110   return x;
4111 }
4112 \f
4113 /* Simplify X, a piece of RTL.  We just operate on the expression at the
4114    outer level; call `subst' to simplify recursively.  Return the new
4115    expression.
4116
4117    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
4118    if we are inside a SET_DEST.  */
4119
4120 static rtx
4121 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4122 {
4123   enum rtx_code code = GET_CODE (x);
4124   enum machine_mode mode = GET_MODE (x);
4125   rtx temp;
4126   int i;
4127
4128   /* If this is a commutative operation, put a constant last and a complex
4129      expression first.  We don't need to do this for comparisons here.  */
4130   if (COMMUTATIVE_ARITH_P (x)
4131       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4132     {
4133       temp = XEXP (x, 0);
4134       SUBST (XEXP (x, 0), XEXP (x, 1));
4135       SUBST (XEXP (x, 1), temp);
4136     }
4137
4138   /* If this is a simple operation applied to an IF_THEN_ELSE, try
4139      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
4140      things.  Check for cases where both arms are testing the same
4141      condition.
4142
4143      Don't do anything if all operands are very simple.  */
4144
4145   if ((BINARY_P (x)
4146        && ((!OBJECT_P (XEXP (x, 0))
4147             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4148                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4149            || (!OBJECT_P (XEXP (x, 1))
4150                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4151                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4152       || (UNARY_P (x)
4153           && (!OBJECT_P (XEXP (x, 0))
4154                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4155                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4156     {
4157       rtx cond, true_rtx, false_rtx;
4158
4159       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4160       if (cond != 0
4161           /* If everything is a comparison, what we have is highly unlikely
4162              to be simpler, so don't use it.  */
4163           && ! (COMPARISON_P (x)
4164                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4165         {
4166           rtx cop1 = const0_rtx;
4167           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4168
4169           if (cond_code == NE && COMPARISON_P (cond))
4170             return x;
4171
4172           /* Simplify the alternative arms; this may collapse the true and
4173              false arms to store-flag values.  Be careful to use copy_rtx
4174              here since true_rtx or false_rtx might share RTL with x as a
4175              result of the if_then_else_cond call above.  */
4176           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4177           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4178
4179           /* If true_rtx and false_rtx are not general_operands, an if_then_else
4180              is unlikely to be simpler.  */
4181           if (general_operand (true_rtx, VOIDmode)
4182               && general_operand (false_rtx, VOIDmode))
4183             {
4184               enum rtx_code reversed;
4185
4186               /* Restarting if we generate a store-flag expression will cause
4187                  us to loop.  Just drop through in this case.  */
4188
4189               /* If the result values are STORE_FLAG_VALUE and zero, we can
4190                  just make the comparison operation.  */
4191               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4192                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4193                                              cond, cop1);
4194               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4195                        && ((reversed = reversed_comparison_code_parts
4196                                         (cond_code, cond, cop1, NULL))
4197                            != UNKNOWN))
4198                 x = simplify_gen_relational (reversed, mode, VOIDmode,
4199                                              cond, cop1);
4200
4201               /* Likewise, we can make the negate of a comparison operation
4202                  if the result values are - STORE_FLAG_VALUE and zero.  */
4203               else if (GET_CODE (true_rtx) == CONST_INT
4204                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4205                        && false_rtx == const0_rtx)
4206                 x = simplify_gen_unary (NEG, mode,
4207                                         simplify_gen_relational (cond_code,
4208                                                                  mode, VOIDmode,
4209                                                                  cond, cop1),
4210                                         mode);
4211               else if (GET_CODE (false_rtx) == CONST_INT
4212                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4213                        && true_rtx == const0_rtx
4214                        && ((reversed = reversed_comparison_code_parts
4215                                         (cond_code, cond, cop1, NULL))
4216                            != UNKNOWN))
4217                 x = simplify_gen_unary (NEG, mode,
4218                                         simplify_gen_relational (reversed,
4219                                                                  mode, VOIDmode,
4220                                                                  cond, cop1),
4221                                         mode);
4222               else
4223                 return gen_rtx_IF_THEN_ELSE (mode,
4224                                              simplify_gen_relational (cond_code,
4225                                                                       mode,
4226                                                                       VOIDmode,
4227                                                                       cond,
4228                                                                       cop1),
4229                                              true_rtx, false_rtx);
4230
4231               code = GET_CODE (x);
4232               op0_mode = VOIDmode;
4233             }
4234         }
4235     }
4236
4237   /* Try to fold this expression in case we have constants that weren't
4238      present before.  */
4239   temp = 0;
4240   switch (GET_RTX_CLASS (code))
4241     {
4242     case RTX_UNARY:
4243       if (op0_mode == VOIDmode)
4244         op0_mode = GET_MODE (XEXP (x, 0));
4245       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4246       break;
4247     case RTX_COMPARE:
4248     case RTX_COMM_COMPARE:
4249       {
4250         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4251         if (cmp_mode == VOIDmode)
4252           {
4253             cmp_mode = GET_MODE (XEXP (x, 1));
4254             if (cmp_mode == VOIDmode)
4255               cmp_mode = op0_mode;
4256           }
4257         temp = simplify_relational_operation (code, mode, cmp_mode,
4258                                               XEXP (x, 0), XEXP (x, 1));
4259       }
4260       break;
4261     case RTX_COMM_ARITH:
4262     case RTX_BIN_ARITH:
4263       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4264       break;
4265     case RTX_BITFIELD_OPS:
4266     case RTX_TERNARY:
4267       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4268                                          XEXP (x, 1), XEXP (x, 2));
4269       break;
4270     default:
4271       break;
4272     }
4273
4274   if (temp)
4275     {
4276       x = temp;
4277       code = GET_CODE (temp);
4278       op0_mode = VOIDmode;
4279       mode = GET_MODE (temp);
4280     }
4281
4282   /* First see if we can apply the inverse distributive law.  */
4283   if (code == PLUS || code == MINUS
4284       || code == AND || code == IOR || code == XOR)
4285     {
4286       x = apply_distributive_law (x);
4287       code = GET_CODE (x);
4288       op0_mode = VOIDmode;
4289     }
4290
4291   /* If CODE is an associative operation not otherwise handled, see if we
4292      can associate some operands.  This can win if they are constants or
4293      if they are logically related (i.e. (a & b) & a).  */
4294   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4295        || code == AND || code == IOR || code == XOR
4296        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4297       && ((INTEGRAL_MODE_P (mode) && code != DIV)
4298           || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4299     {
4300       if (GET_CODE (XEXP (x, 0)) == code)
4301         {
4302           rtx other = XEXP (XEXP (x, 0), 0);
4303           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4304           rtx inner_op1 = XEXP (x, 1);
4305           rtx inner;
4306
4307           /* Make sure we pass the constant operand if any as the second
4308              one if this is a commutative operation.  */
4309           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4310             {
4311               rtx tem = inner_op0;
4312               inner_op0 = inner_op1;
4313               inner_op1 = tem;
4314             }
4315           inner = simplify_binary_operation (code == MINUS ? PLUS
4316                                              : code == DIV ? MULT
4317                                              : code,
4318                                              mode, inner_op0, inner_op1);
4319
4320           /* For commutative operations, try the other pair if that one
4321              didn't simplify.  */
4322           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4323             {
4324               other = XEXP (XEXP (x, 0), 1);
4325               inner = simplify_binary_operation (code, mode,
4326                                                  XEXP (XEXP (x, 0), 0),
4327                                                  XEXP (x, 1));
4328             }
4329
4330           if (inner)
4331             return simplify_gen_binary (code, mode, other, inner);
4332         }
4333     }
4334
4335   /* A little bit of algebraic simplification here.  */
4336   switch (code)
4337     {
4338     case MEM:
4339       /* Ensure that our address has any ASHIFTs converted to MULT in case
4340          address-recognizing predicates are called later.  */
4341       temp = make_compound_operation (XEXP (x, 0), MEM);
4342       SUBST (XEXP (x, 0), temp);
4343       break;
4344
4345     case SUBREG:
4346       if (op0_mode == VOIDmode)
4347         op0_mode = GET_MODE (SUBREG_REG (x));
4348
4349       /* See if this can be moved to simplify_subreg.  */
4350       if (CONSTANT_P (SUBREG_REG (x))
4351           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4352              /* Don't call gen_lowpart if the inner mode
4353                 is VOIDmode and we cannot simplify it, as SUBREG without
4354                 inner mode is invalid.  */
4355           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4356               || gen_lowpart_common (mode, SUBREG_REG (x))))
4357         return gen_lowpart (mode, SUBREG_REG (x));
4358
4359       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4360         break;
4361       {
4362         rtx temp;
4363         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4364                                 SUBREG_BYTE (x));
4365         if (temp)
4366           return temp;
4367       }
4368
4369       /* Don't change the mode of the MEM if that would change the meaning
4370          of the address.  */
4371       if (MEM_P (SUBREG_REG (x))
4372           && (MEM_VOLATILE_P (SUBREG_REG (x))
4373               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4374         return gen_rtx_CLOBBER (mode, const0_rtx);
4375
4376       /* Note that we cannot do any narrowing for non-constants since
4377          we might have been counting on using the fact that some bits were
4378          zero.  We now do this in the SET.  */
4379
4380       break;
4381
4382     case NEG:
4383       temp = expand_compound_operation (XEXP (x, 0));
4384
4385       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4386          replaced by (lshiftrt X C).  This will convert
4387          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
4388
4389       if (GET_CODE (temp) == ASHIFTRT
4390           && GET_CODE (XEXP (temp, 1)) == CONST_INT
4391           && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4392         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4393                                      INTVAL (XEXP (temp, 1)));
4394
4395       /* If X has only a single bit that might be nonzero, say, bit I, convert
4396          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4397          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
4398          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
4399          or a SUBREG of one since we'd be making the expression more
4400          complex if it was just a register.  */
4401
4402       if (!REG_P (temp)
4403           && ! (GET_CODE (temp) == SUBREG
4404                 && REG_P (SUBREG_REG (temp)))
4405           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4406         {
4407           rtx temp1 = simplify_shift_const
4408             (NULL_RTX, ASHIFTRT, mode,
4409              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4410                                    GET_MODE_BITSIZE (mode) - 1 - i),
4411              GET_MODE_BITSIZE (mode) - 1 - i);
4412
4413           /* If all we did was surround TEMP with the two shifts, we
4414              haven't improved anything, so don't use it.  Otherwise,
4415              we are better off with TEMP1.  */
4416           if (GET_CODE (temp1) != ASHIFTRT
4417               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4418               || XEXP (XEXP (temp1, 0), 0) != temp)
4419             return temp1;
4420         }
4421       break;
4422
4423     case TRUNCATE:
4424       /* We can't handle truncation to a partial integer mode here
4425          because we don't know the real bitsize of the partial
4426          integer mode.  */
4427       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4428         break;
4429
4430       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4431           && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4432                                     GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4433         SUBST (XEXP (x, 0),
4434                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4435                               GET_MODE_MASK (mode), 0));
4436
4437       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4438          whose value is a comparison can be replaced with a subreg if
4439          STORE_FLAG_VALUE permits.  */
4440       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4441           && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4442           && (temp = get_last_value (XEXP (x, 0)))
4443           && COMPARISON_P (temp))
4444         return gen_lowpart (mode, XEXP (x, 0));
4445       break;
4446
4447 #ifdef HAVE_cc0
4448     case COMPARE:
4449       /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4450          using cc0, in which case we want to leave it as a COMPARE
4451          so we can distinguish it from a register-register-copy.  */
4452       if (XEXP (x, 1) == const0_rtx)
4453         return XEXP (x, 0);
4454
4455       /* x - 0 is the same as x unless x's mode has signed zeros and
4456          allows rounding towards -infinity.  Under those conditions,
4457          0 - 0 is -0.  */
4458       if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4459             && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4460           && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4461         return XEXP (x, 0);
4462       break;
4463 #endif
4464
4465     case CONST:
4466       /* (const (const X)) can become (const X).  Do it this way rather than
4467          returning the inner CONST since CONST can be shared with a
4468          REG_EQUAL note.  */
4469       if (GET_CODE (XEXP (x, 0)) == CONST)
4470         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4471       break;
4472
4473 #ifdef HAVE_lo_sum
4474     case LO_SUM:
4475       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
4476          can add in an offset.  find_split_point will split this address up
4477          again if it doesn't match.  */
4478       if (GET_CODE (XEXP (x, 0)) == HIGH
4479           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4480         return XEXP (x, 1);
4481       break;
4482 #endif
4483
4484     case PLUS:
4485       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4486          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4487          bit-field and can be replaced by either a sign_extend or a
4488          sign_extract.  The `and' may be a zero_extend and the two
4489          <c>, -<c> constants may be reversed.  */
4490       if (GET_CODE (XEXP (x, 0)) == XOR
4491           && GET_CODE (XEXP (x, 1)) == CONST_INT
4492           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4493           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4494           && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4495               || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4496           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4497           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4498                && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4499                && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4500                    == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4501               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4502                   && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4503                       == (unsigned int) i + 1))))
4504         return simplify_shift_const
4505           (NULL_RTX, ASHIFTRT, mode,
4506            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4507                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
4508                                  GET_MODE_BITSIZE (mode) - (i + 1)),
4509            GET_MODE_BITSIZE (mode) - (i + 1));
4510
4511       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4512          can become (ashiftrt (ashift (xor x 1) C) C) where C is
4513          the bitsize of the mode - 1.  This allows simplification of
4514          "a = (b & 8) == 0;"  */
4515       if (XEXP (x, 1) == constm1_rtx
4516           && !REG_P (XEXP (x, 0))
4517           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4518                 && REG_P (SUBREG_REG (XEXP (x, 0))))
4519           && nonzero_bits (XEXP (x, 0), mode) == 1)
4520         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4521            simplify_shift_const (NULL_RTX, ASHIFT, mode,
4522                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4523                                  GET_MODE_BITSIZE (mode) - 1),
4524            GET_MODE_BITSIZE (mode) - 1);
4525
4526       /* If we are adding two things that have no bits in common, convert
4527          the addition into an IOR.  This will often be further simplified,
4528          for example in cases like ((a & 1) + (a & 2)), which can
4529          become a & 3.  */
4530
4531       if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4532           && (nonzero_bits (XEXP (x, 0), mode)
4533               & nonzero_bits (XEXP (x, 1), mode)) == 0)
4534         {
4535           /* Try to simplify the expression further.  */
4536           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4537           temp = combine_simplify_rtx (tor, mode, in_dest);
4538
4539           /* If we could, great.  If not, do not go ahead with the IOR
4540              replacement, since PLUS appears in many special purpose
4541              address arithmetic instructions.  */
4542           if (GET_CODE (temp) != CLOBBER && temp != tor)
4543             return temp;
4544         }
4545       break;
4546
4547     case MINUS:
4548       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4549          (and <foo> (const_int pow2-1))  */
4550       if (GET_CODE (XEXP (x, 1)) == AND
4551           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4552           && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4553           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4554         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4555                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4556       break;
4557
4558     case MULT:
4559       /* If we have (mult (plus A B) C), apply the distributive law and then
4560          the inverse distributive law to see if things simplify.  This
4561          occurs mostly in addresses, often when unrolling loops.  */
4562
4563       if (GET_CODE (XEXP (x, 0)) == PLUS)
4564         {
4565           rtx result = distribute_and_simplify_rtx (x, 0);
4566           if (result)
4567             return result;
4568         }
4569
4570       /* Try simplify a*(b/c) as (a*b)/c.  */
4571       if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4572           && GET_CODE (XEXP (x, 0)) == DIV)
4573         {
4574           rtx tem = simplify_binary_operation (MULT, mode,
4575                                                XEXP (XEXP (x, 0), 0),
4576                                                XEXP (x, 1));
4577           if (tem)
4578             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4579         }
4580       break;
4581
4582     case UDIV:
4583       /* If this is a divide by a power of two, treat it as a shift if
4584          its first operand is a shift.  */
4585       if (GET_CODE (XEXP (x, 1)) == CONST_INT
4586           && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4587           && (GET_CODE (XEXP (x, 0)) == ASHIFT
4588               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4589               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4590               || GET_CODE (XEXP (x, 0)) == ROTATE
4591               || GET_CODE (XEXP (x, 0)) == ROTATERT))
4592         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4593       break;
4594
4595     case EQ:  case NE:
4596     case GT:  case GTU:  case GE:  case GEU:
4597     case LT:  case LTU:  case LE:  case LEU:
4598     case UNEQ:  case LTGT:
4599     case UNGT:  case UNGE:
4600     case UNLT:  case UNLE:
4601     case UNORDERED: case ORDERED:
4602       /* If the first operand is a condition code, we can't do anything
4603          with it.  */
4604       if (GET_CODE (XEXP (x, 0)) == COMPARE
4605           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4606               && ! CC0_P (XEXP (x, 0))))
4607         {
4608           rtx op0 = XEXP (x, 0);
4609           rtx op1 = XEXP (x, 1);
4610           enum rtx_code new_code;
4611
4612           if (GET_CODE (op0) == COMPARE)
4613             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4614
4615           /* Simplify our comparison, if possible.  */
4616           new_code = simplify_comparison (code, &op0, &op1);
4617
4618           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4619              if only the low-order bit is possibly nonzero in X (such as when
4620              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
4621              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
4622              known to be either 0 or -1, NE becomes a NEG and EQ becomes
4623              (plus X 1).
4624
4625              Remove any ZERO_EXTRACT we made when thinking this was a
4626              comparison.  It may now be simpler to use, e.g., an AND.  If a
4627              ZERO_EXTRACT is indeed appropriate, it will be placed back by
4628              the call to make_compound_operation in the SET case.  */
4629
4630           if (STORE_FLAG_VALUE == 1
4631               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4632               && op1 == const0_rtx
4633               && mode == GET_MODE (op0)
4634               && nonzero_bits (op0, mode) == 1)
4635             return gen_lowpart (mode,
4636                                 expand_compound_operation (op0));
4637
4638           else if (STORE_FLAG_VALUE == 1
4639                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4640                    && op1 == const0_rtx
4641                    && mode == GET_MODE (op0)
4642                    && (num_sign_bit_copies (op0, mode)
4643                        == GET_MODE_BITSIZE (mode)))
4644             {
4645               op0 = expand_compound_operation (op0);
4646               return simplify_gen_unary (NEG, mode,
4647                                          gen_lowpart (mode, op0),
4648                                          mode);
4649             }
4650
4651           else if (STORE_FLAG_VALUE == 1
4652                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4653                    && op1 == const0_rtx
4654                    && mode == GET_MODE (op0)
4655                    && nonzero_bits (op0, mode) == 1)
4656             {
4657               op0 = expand_compound_operation (op0);
4658               return simplify_gen_binary (XOR, mode,
4659                                           gen_lowpart (mode, op0),
4660                                           const1_rtx);
4661             }
4662
4663           else if (STORE_FLAG_VALUE == 1
4664                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4665                    && op1 == const0_rtx
4666                    && mode == GET_MODE (op0)
4667                    && (num_sign_bit_copies (op0, mode)
4668                        == GET_MODE_BITSIZE (mode)))
4669             {
4670               op0 = expand_compound_operation (op0);
4671               return plus_constant (gen_lowpart (mode, op0), 1);
4672             }
4673
4674           /* If STORE_FLAG_VALUE is -1, we have cases similar to
4675              those above.  */
4676           if (STORE_FLAG_VALUE == -1
4677               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4678               && op1 == const0_rtx
4679               && (num_sign_bit_copies (op0, mode)
4680                   == GET_MODE_BITSIZE (mode)))
4681             return gen_lowpart (mode,
4682                                 expand_compound_operation (op0));
4683
4684           else if (STORE_FLAG_VALUE == -1
4685                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4686                    && op1 == const0_rtx
4687                    && mode == GET_MODE (op0)
4688                    && nonzero_bits (op0, mode) == 1)
4689             {
4690               op0 = expand_compound_operation (op0);
4691               return simplify_gen_unary (NEG, mode,
4692                                          gen_lowpart (mode, op0),
4693                                          mode);
4694             }
4695
4696           else if (STORE_FLAG_VALUE == -1
4697                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4698                    && op1 == const0_rtx
4699                    && mode == GET_MODE (op0)
4700                    && (num_sign_bit_copies (op0, mode)
4701                        == GET_MODE_BITSIZE (mode)))
4702             {
4703               op0 = expand_compound_operation (op0);
4704               return simplify_gen_unary (NOT, mode,
4705                                          gen_lowpart (mode, op0),
4706                                          mode);
4707             }
4708
4709           /* If X is 0/1, (eq X 0) is X-1.  */
4710           else if (STORE_FLAG_VALUE == -1
4711                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4712                    && op1 == const0_rtx
4713                    && mode == GET_MODE (op0)
4714                    && nonzero_bits (op0, mode) == 1)
4715             {
4716               op0 = expand_compound_operation (op0);
4717               return plus_constant (gen_lowpart (mode, op0), -1);
4718             }
4719
4720           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4721              one bit that might be nonzero, we can convert (ne x 0) to
4722              (ashift x c) where C puts the bit in the sign bit.  Remove any
4723              AND with STORE_FLAG_VALUE when we are done, since we are only
4724              going to test the sign bit.  */
4725           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4726               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4727               && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4728                   == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4729               && op1 == const0_rtx
4730               && mode == GET_MODE (op0)
4731               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4732             {
4733               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4734                                         expand_compound_operation (op0),
4735                                         GET_MODE_BITSIZE (mode) - 1 - i);
4736               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4737                 return XEXP (x, 0);
4738               else
4739                 return x;
4740             }
4741
4742           /* If the code changed, return a whole new comparison.  */
4743           if (new_code != code)
4744             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4745
4746           /* Otherwise, keep this operation, but maybe change its operands.
4747              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
4748           SUBST (XEXP (x, 0), op0);
4749           SUBST (XEXP (x, 1), op1);
4750         }
4751       break;
4752
4753     case IF_THEN_ELSE:
4754       return simplify_if_then_else (x);
4755
4756     case ZERO_EXTRACT:
4757     case SIGN_EXTRACT:
4758     case ZERO_EXTEND:
4759     case SIGN_EXTEND:
4760       /* If we are processing SET_DEST, we are done.  */
4761       if (in_dest)
4762         return x;
4763
4764       return expand_compound_operation (x);
4765
4766     case SET:
4767       return simplify_set (x);
4768
4769     case AND:
4770     case IOR:
4771       return simplify_logical (x);
4772
4773     case ASHIFT:
4774     case LSHIFTRT:
4775     case ASHIFTRT:
4776     case ROTATE:
4777     case ROTATERT:
4778       /* If this is a shift by a constant amount, simplify it.  */
4779       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4780         return simplify_shift_const (x, code, mode, XEXP (x, 0),
4781                                      INTVAL (XEXP (x, 1)));
4782
4783       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4784         SUBST (XEXP (x, 1),
4785                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4786                               ((HOST_WIDE_INT) 1
4787                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4788                               - 1,
4789                               0));
4790       break;
4791
4792     default:
4793       break;
4794     }
4795
4796   return x;
4797 }
4798 \f
4799 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
4800
4801 static rtx
4802 simplify_if_then_else (rtx x)
4803 {
4804   enum machine_mode mode = GET_MODE (x);
4805   rtx cond = XEXP (x, 0);
4806   rtx true_rtx = XEXP (x, 1);
4807   rtx false_rtx = XEXP (x, 2);
4808   enum rtx_code true_code = GET_CODE (cond);
4809   int comparison_p = COMPARISON_P (cond);
4810   rtx temp;
4811   int i;
4812   enum rtx_code false_code;
4813   rtx reversed;
4814
4815   /* Simplify storing of the truth value.  */
4816   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4817     return simplify_gen_relational (true_code, mode, VOIDmode,
4818                                     XEXP (cond, 0), XEXP (cond, 1));
4819
4820   /* Also when the truth value has to be reversed.  */
4821   if (comparison_p
4822       && true_rtx == const0_rtx && false_rtx == const_true_rtx
4823       && (reversed = reversed_comparison (cond, mode)))
4824     return reversed;
4825
4826   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4827      in it is being compared against certain values.  Get the true and false
4828      comparisons and see if that says anything about the value of each arm.  */
4829
4830   if (comparison_p
4831       && ((false_code = reversed_comparison_code (cond, NULL))
4832           != UNKNOWN)
4833       && REG_P (XEXP (cond, 0)))
4834     {
4835       HOST_WIDE_INT nzb;
4836       rtx from = XEXP (cond, 0);
4837       rtx true_val = XEXP (cond, 1);
4838       rtx false_val = true_val;
4839       int swapped = 0;
4840
4841       /* If FALSE_CODE is EQ, swap the codes and arms.  */
4842
4843       if (false_code == EQ)
4844         {
4845           swapped = 1, true_code = EQ, false_code = NE;
4846           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4847         }
4848
4849       /* If we are comparing against zero and the expression being tested has
4850          only a single bit that might be nonzero, that is its value when it is
4851          not equal to zero.  Similarly if it is known to be -1 or 0.  */
4852
4853       if (true_code == EQ && true_val == const0_rtx
4854           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4855         false_code = EQ, false_val = GEN_INT (nzb);
4856       else if (true_code == EQ && true_val == const0_rtx
4857                && (num_sign_bit_copies (from, GET_MODE (from))
4858                    == GET_MODE_BITSIZE (GET_MODE (from))))
4859         false_code = EQ, false_val = constm1_rtx;
4860
4861       /* Now simplify an arm if we know the value of the register in the
4862          branch and it is used in the arm.  Be careful due to the potential
4863          of locally-shared RTL.  */
4864
4865       if (reg_mentioned_p (from, true_rtx))
4866         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4867                                       from, true_val),
4868                       pc_rtx, pc_rtx, 0, 0);
4869       if (reg_mentioned_p (from, false_rtx))
4870         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4871                                    from, false_val),
4872                        pc_rtx, pc_rtx, 0, 0);
4873
4874       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4875       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4876
4877       true_rtx = XEXP (x, 1);
4878       false_rtx = XEXP (x, 2);
4879       true_code = GET_CODE (cond);
4880     }
4881
4882   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4883      reversed, do so to avoid needing two sets of patterns for
4884      subtract-and-branch insns.  Similarly if we have a constant in the true
4885      arm, the false arm is the same as the first operand of the comparison, or
4886      the false arm is more complicated than the true arm.  */
4887
4888   if (comparison_p
4889       && reversed_comparison_code (cond, NULL) != UNKNOWN
4890       && (true_rtx == pc_rtx
4891           || (CONSTANT_P (true_rtx)
4892               && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4893           || true_rtx == const0_rtx
4894           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4895           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4896               && !OBJECT_P (false_rtx))
4897           || reg_mentioned_p (true_rtx, false_rtx)
4898           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4899     {
4900       true_code = reversed_comparison_code (cond, NULL);
4901       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4902       SUBST (XEXP (x, 1), false_rtx);
4903       SUBST (XEXP (x, 2), true_rtx);
4904
4905       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4906       cond = XEXP (x, 0);
4907
4908       /* It is possible that the conditional has been simplified out.  */
4909       true_code = GET_CODE (cond);
4910       comparison_p = COMPARISON_P (cond);
4911     }
4912
4913   /* If the two arms are identical, we don't need the comparison.  */
4914
4915   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4916     return true_rtx;
4917
4918   /* Convert a == b ? b : a to "a".  */
4919   if (true_code == EQ && ! side_effects_p (cond)
4920       && !HONOR_NANS (mode)
4921       && rtx_equal_p (XEXP (cond, 0), false_rtx)
4922       && rtx_equal_p (XEXP (cond, 1), true_rtx))
4923     return false_rtx;
4924   else if (true_code == NE && ! side_effects_p (cond)
4925            && !HONOR_NANS (mode)
4926            && rtx_equal_p (XEXP (cond, 0), true_rtx)
4927            && rtx_equal_p (XEXP (cond, 1), false_rtx))
4928     return true_rtx;
4929
4930   /* Look for cases where we have (abs x) or (neg (abs X)).  */
4931
4932   if (GET_MODE_CLASS (mode) == MODE_INT
4933       && GET_CODE (false_rtx) == NEG
4934       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4935       && comparison_p
4936       && rtx_equal_p (true_rtx, XEXP (cond, 0))
4937       && ! side_effects_p (true_rtx))
4938     switch (true_code)
4939       {
4940       case GT:
4941       case GE:
4942         return simplify_gen_unary (ABS, mode, true_rtx, mode);
4943       case LT:
4944       case LE:
4945         return
4946           simplify_gen_unary (NEG, mode,
4947                               simplify_gen_unary (ABS, mode, true_rtx, mode),
4948                               mode);
4949       default:
4950         break;
4951       }
4952
4953   /* Look for MIN or MAX.  */
4954
4955   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4956       && comparison_p
4957       && rtx_equal_p (XEXP (cond, 0), true_rtx)
4958       && rtx_equal_p (XEXP (cond, 1), false_rtx)
4959       && ! side_effects_p (cond))
4960     switch (true_code)
4961       {
4962       case GE:
4963       case GT:
4964         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4965       case LE:
4966       case LT:
4967         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4968       case GEU:
4969       case GTU:
4970         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4971       case LEU:
4972       case LTU:
4973         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4974       default:
4975         break;
4976       }
4977
4978   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4979      second operand is zero, this can be done as (OP Z (mult COND C2)) where
4980      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4981      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4982      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4983      neither 1 or -1, but it isn't worth checking for.  */
4984
4985   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4986       && comparison_p
4987       && GET_MODE_CLASS (mode) == MODE_INT
4988       && ! side_effects_p (x))
4989     {
4990       rtx t = make_compound_operation (true_rtx, SET);
4991       rtx f = make_compound_operation (false_rtx, SET);
4992       rtx cond_op0 = XEXP (cond, 0);
4993       rtx cond_op1 = XEXP (cond, 1);
4994       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4995       enum machine_mode m = mode;
4996       rtx z = 0, c1 = NULL_RTX;
4997
4998       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4999            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5000            || GET_CODE (t) == ASHIFT
5001            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5002           && rtx_equal_p (XEXP (t, 0), f))
5003         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5004
5005       /* If an identity-zero op is commutative, check whether there
5006          would be a match if we swapped the operands.  */
5007       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5008                 || GET_CODE (t) == XOR)
5009                && rtx_equal_p (XEXP (t, 1), f))
5010         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5011       else if (GET_CODE (t) == SIGN_EXTEND
5012                && (GET_CODE (XEXP (t, 0)) == PLUS
5013                    || GET_CODE (XEXP (t, 0)) == MINUS
5014                    || GET_CODE (XEXP (t, 0)) == IOR
5015                    || GET_CODE (XEXP (t, 0)) == XOR
5016                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5017                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5018                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5019                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5020                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5021                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5022                && (num_sign_bit_copies (f, GET_MODE (f))
5023                    > (unsigned int)
5024                      (GET_MODE_BITSIZE (mode)
5025                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5026         {
5027           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5028           extend_op = SIGN_EXTEND;
5029           m = GET_MODE (XEXP (t, 0));
5030         }
5031       else if (GET_CODE (t) == SIGN_EXTEND
5032                && (GET_CODE (XEXP (t, 0)) == PLUS
5033                    || GET_CODE (XEXP (t, 0)) == IOR
5034                    || GET_CODE (XEXP (t, 0)) == XOR)
5035                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5036                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5037                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5038                && (num_sign_bit_copies (f, GET_MODE (f))
5039                    > (unsigned int)
5040                      (GET_MODE_BITSIZE (mode)
5041                       - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5042         {
5043           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5044           extend_op = SIGN_EXTEND;
5045           m = GET_MODE (XEXP (t, 0));
5046         }
5047       else if (GET_CODE (t) == ZERO_EXTEND
5048                && (GET_CODE (XEXP (t, 0)) == PLUS
5049                    || GET_CODE (XEXP (t, 0)) == MINUS
5050                    || GET_CODE (XEXP (t, 0)) == IOR
5051                    || GET_CODE (XEXP (t, 0)) == XOR
5052                    || GET_CODE (XEXP (t, 0)) == ASHIFT
5053                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5054                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5055                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5056                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5057                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5058                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5059                && ((nonzero_bits (f, GET_MODE (f))
5060                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5061                    == 0))
5062         {
5063           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5064           extend_op = ZERO_EXTEND;
5065           m = GET_MODE (XEXP (t, 0));
5066         }
5067       else if (GET_CODE (t) == ZERO_EXTEND
5068                && (GET_CODE (XEXP (t, 0)) == PLUS
5069                    || GET_CODE (XEXP (t, 0)) == IOR
5070                    || GET_CODE (XEXP (t, 0)) == XOR)
5071                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5072                && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5073                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5074                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5075                && ((nonzero_bits (f, GET_MODE (f))
5076                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5077                    == 0))
5078         {
5079           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5080           extend_op = ZERO_EXTEND;
5081           m = GET_MODE (XEXP (t, 0));
5082         }
5083
5084       if (z)
5085         {
5086           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5087                                                  cond_op0, cond_op1),
5088                         pc_rtx, pc_rtx, 0, 0);
5089           temp = simplify_gen_binary (MULT, m, temp,
5090                                       simplify_gen_binary (MULT, m, c1,
5091                                                            const_true_rtx));
5092           temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5093           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5094
5095           if (extend_op != UNKNOWN)
5096             temp = simplify_gen_unary (extend_op, mode, temp, m);
5097
5098           return temp;
5099         }
5100     }
5101
5102   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5103      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5104      negation of a single bit, we can convert this operation to a shift.  We
5105      can actually do this more generally, but it doesn't seem worth it.  */
5106
5107   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5108       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5109       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5110            && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5111           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5112                == GET_MODE_BITSIZE (mode))
5113               && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5114     return
5115       simplify_shift_const (NULL_RTX, ASHIFT, mode,
5116                             gen_lowpart (mode, XEXP (cond, 0)), i);
5117
5118   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
5119   if (true_code == NE && XEXP (cond, 1) == const0_rtx
5120       && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5121       && GET_MODE (XEXP (cond, 0)) == mode
5122       && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5123           == nonzero_bits (XEXP (cond, 0), mode)
5124       && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5125     return XEXP (cond, 0);
5126
5127   return x;
5128 }
5129 \f
5130 /* Simplify X, a SET expression.  Return the new expression.  */
5131
5132 static rtx
5133 simplify_set (rtx x)
5134 {
5135   rtx src = SET_SRC (x);
5136   rtx dest = SET_DEST (x);
5137   enum machine_mode mode
5138     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5139   rtx other_insn;
5140   rtx *cc_use;
5141
5142   /* (set (pc) (return)) gets written as (return).  */
5143   if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5144     return src;
5145
5146   /* Now that we know for sure which bits of SRC we are using, see if we can
5147      simplify the expression for the object knowing that we only need the
5148      low-order bits.  */
5149
5150   if (GET_MODE_CLASS (mode) == MODE_INT
5151       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5152     {
5153       src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5154       SUBST (SET_SRC (x), src);
5155     }
5156
5157   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5158      the comparison result and try to simplify it unless we already have used
5159      undobuf.other_insn.  */
5160   if ((GET_MODE_CLASS (mode) == MODE_CC
5161        || GET_CODE (src) == COMPARE
5162        || CC0_P (dest))
5163       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5164       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5165       && COMPARISON_P (*cc_use)
5166       && rtx_equal_p (XEXP (*cc_use, 0), dest))
5167     {
5168       enum rtx_code old_code = GET_CODE (*cc_use);
5169       enum rtx_code new_code;
5170       rtx op0, op1, tmp;
5171       int other_changed = 0;
5172       enum machine_mode compare_mode = GET_MODE (dest);
5173
5174       if (GET_CODE (src) == COMPARE)
5175         op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5176       else
5177         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5178
5179       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5180                                            op0, op1);
5181       if (!tmp)
5182         new_code = old_code;
5183       else if (!CONSTANT_P (tmp))
5184         {
5185           new_code = GET_CODE (tmp);
5186           op0 = XEXP (tmp, 0);
5187           op1 = XEXP (tmp, 1);
5188         }
5189       else
5190         {
5191           rtx pat = PATTERN (other_insn);
5192           undobuf.other_insn = other_insn;
5193           SUBST (*cc_use, tmp);
5194
5195           /* Attempt to simplify CC user.  */
5196           if (GET_CODE (pat) == SET)
5197             {
5198               rtx new = simplify_rtx (SET_SRC (pat));
5199               if (new != NULL_RTX)
5200                 SUBST (SET_SRC (pat), new);
5201             }
5202
5203           /* Convert X into a no-op move.  */
5204           SUBST (SET_DEST (x), pc_rtx);
5205           SUBST (SET_SRC (x), pc_rtx);
5206           return x;
5207         }
5208
5209       /* Simplify our comparison, if possible.  */
5210       new_code = simplify_comparison (new_code, &op0, &op1);
5211
5212 #ifdef SELECT_CC_MODE
5213       /* If this machine has CC modes other than CCmode, check to see if we
5214          need to use a different CC mode here.  */
5215       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5216         compare_mode = GET_MODE (op0);
5217       else
5218         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5219
5220 #ifndef HAVE_cc0
5221       /* If the mode changed, we have to change SET_DEST, the mode in the
5222          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
5223          a hard register, just build new versions with the proper mode.  If it
5224          is a pseudo, we lose unless it is only time we set the pseudo, in
5225          which case we can safely change its mode.  */
5226       if (compare_mode != GET_MODE (dest))
5227         {
5228           if (can_change_dest_mode (dest, 0, compare_mode))
5229             {
5230               unsigned int regno = REGNO (dest);
5231               rtx new_dest;
5232
5233               if (regno < FIRST_PSEUDO_REGISTER)
5234                 new_dest = gen_rtx_REG (compare_mode, regno);
5235               else
5236                 {
5237                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5238                   new_dest = regno_reg_rtx[regno];
5239                 }
5240
5241               SUBST (SET_DEST (x), new_dest);
5242               SUBST (XEXP (*cc_use, 0), new_dest);
5243               other_changed = 1;
5244
5245               dest = new_dest;
5246             }
5247         }
5248 #endif  /* cc0 */
5249 #endif  /* SELECT_CC_MODE */
5250
5251       /* If the code changed, we have to build a new comparison in
5252          undobuf.other_insn.  */
5253       if (new_code != old_code)
5254         {
5255           int other_changed_previously = other_changed;
5256           unsigned HOST_WIDE_INT mask;
5257
5258           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5259                                           dest, const0_rtx));
5260           other_changed = 1;
5261
5262           /* If the only change we made was to change an EQ into an NE or
5263              vice versa, OP0 has only one bit that might be nonzero, and OP1
5264              is zero, check if changing the user of the condition code will
5265              produce a valid insn.  If it won't, we can keep the original code
5266              in that insn by surrounding our operation with an XOR.  */
5267
5268           if (((old_code == NE && new_code == EQ)
5269                || (old_code == EQ && new_code == NE))
5270               && ! other_changed_previously && op1 == const0_rtx
5271               && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5272               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5273             {
5274               rtx pat = PATTERN (other_insn), note = 0;
5275
5276               if ((recog_for_combine (&pat, other_insn, &note) < 0
5277                    && ! check_asm_operands (pat)))
5278                 {
5279                   PUT_CODE (*cc_use, old_code);
5280                   other_changed = 0;
5281
5282                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5283                                              op0, GEN_INT (mask));
5284                 }
5285             }
5286         }
5287
5288       if (other_changed)
5289         undobuf.other_insn = other_insn;
5290
5291 #ifdef HAVE_cc0
5292       /* If we are now comparing against zero, change our source if
5293          needed.  If we do not use cc0, we always have a COMPARE.  */
5294       if (op1 == const0_rtx && dest == cc0_rtx)
5295         {
5296           SUBST (SET_SRC (x), op0);
5297           src = op0;
5298         }
5299       else
5300 #endif
5301
5302       /* Otherwise, if we didn't previously have a COMPARE in the
5303          correct mode, we need one.  */
5304       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5305         {
5306           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5307           src = SET_SRC (x);
5308         }
5309       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5310         {
5311           SUBST(SET_SRC (x), op0);
5312           src = SET_SRC (x);
5313         }
5314       else
5315         {
5316           /* Otherwise, update the COMPARE if needed.  */
5317           SUBST (XEXP (src, 0), op0);
5318           SUBST (XEXP (src, 1), op1);
5319         }
5320     }
5321   else
5322     {
5323       /* Get SET_SRC in a form where we have placed back any
5324          compound expressions.  Then do the checks below.  */
5325       src = make_compound_operation (src, SET);
5326       SUBST (SET_SRC (x), src);
5327     }
5328
5329   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5330      and X being a REG or (subreg (reg)), we may be able to convert this to
5331      (set (subreg:m2 x) (op)).
5332
5333      We can always do this if M1 is narrower than M2 because that means that
5334      we only care about the low bits of the result.
5335
5336      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5337      perform a narrower operation than requested since the high-order bits will
5338      be undefined.  On machine where it is defined, this transformation is safe
5339      as long as M1 and M2 have the same number of words.  */
5340
5341   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5342       && !OBJECT_P (SUBREG_REG (src))
5343       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5344            / UNITS_PER_WORD)
5345           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5346                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5347 #ifndef WORD_REGISTER_OPERATIONS
5348       && (GET_MODE_SIZE (GET_MODE (src))
5349         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5350 #endif
5351 #ifdef CANNOT_CHANGE_MODE_CLASS
5352       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5353             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5354                                          GET_MODE (SUBREG_REG (src)),
5355                                          GET_MODE (src)))
5356 #endif
5357       && (REG_P (dest)
5358           || (GET_CODE (dest) == SUBREG
5359               && REG_P (SUBREG_REG (dest)))))
5360     {
5361       SUBST (SET_DEST (x),
5362              gen_lowpart (GET_MODE (SUBREG_REG (src)),
5363                                       dest));
5364       SUBST (SET_SRC (x), SUBREG_REG (src));
5365
5366       src = SET_SRC (x), dest = SET_DEST (x);
5367     }
5368
5369 #ifdef HAVE_cc0
5370   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5371      in SRC.  */
5372   if (dest == cc0_rtx
5373       && GET_CODE (src) == SUBREG
5374       && subreg_lowpart_p (src)
5375       && (GET_MODE_BITSIZE (GET_MODE (src))
5376           < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5377     {
5378       rtx inner = SUBREG_REG (src);
5379       enum machine_mode inner_mode = GET_MODE (inner);
5380
5381       /* Here we make sure that we don't have a sign bit on.  */
5382       if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5383           && (nonzero_bits (inner, inner_mode)
5384               < ((unsigned HOST_WIDE_INT) 1
5385                  << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5386         {
5387           SUBST (SET_SRC (x), inner);
5388           src = SET_SRC (x);
5389         }
5390     }
5391 #endif
5392
5393 #ifdef LOAD_EXTEND_OP
5394   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5395      would require a paradoxical subreg.  Replace the subreg with a
5396      zero_extend to avoid the reload that would otherwise be required.  */
5397
5398   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5399       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5400       && SUBREG_BYTE (src) == 0
5401       && (GET_MODE_SIZE (GET_MODE (src))
5402           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5403       && MEM_P (SUBREG_REG (src)))
5404     {
5405       SUBST (SET_SRC (x),
5406              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5407                             GET_MODE (src), SUBREG_REG (src)));
5408
5409       src = SET_SRC (x);
5410     }
5411 #endif
5412
5413   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5414      are comparing an item known to be 0 or -1 against 0, use a logical
5415      operation instead. Check for one of the arms being an IOR of the other
5416      arm with some value.  We compute three terms to be IOR'ed together.  In
5417      practice, at most two will be nonzero.  Then we do the IOR's.  */
5418
5419   if (GET_CODE (dest) != PC
5420       && GET_CODE (src) == IF_THEN_ELSE
5421       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5422       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5423       && XEXP (XEXP (src, 0), 1) == const0_rtx
5424       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5425 #ifdef HAVE_conditional_move
5426       && ! can_conditionally_move_p (GET_MODE (src))
5427 #endif
5428       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5429                                GET_MODE (XEXP (XEXP (src, 0), 0)))
5430           == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5431       && ! side_effects_p (src))
5432     {
5433       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5434                       ? XEXP (src, 1) : XEXP (src, 2));
5435       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5436                    ? XEXP (src, 2) : XEXP (src, 1));
5437       rtx term1 = const0_rtx, term2, term3;
5438
5439       if (GET_CODE (true_rtx) == IOR
5440           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5441         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5442       else if (GET_CODE (true_rtx) == IOR
5443                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5444         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5445       else if (GET_CODE (false_rtx) == IOR
5446                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5447         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5448       else if (GET_CODE (false_rtx) == IOR
5449                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5450         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5451
5452       term2 = simplify_gen_binary (AND, GET_MODE (src),
5453                                    XEXP (XEXP (src, 0), 0), true_rtx);
5454       term3 = simplify_gen_binary (AND, GET_MODE (src),
5455                                    simplify_gen_unary (NOT, GET_MODE (src),
5456                                                        XEXP (XEXP (src, 0), 0),
5457                                                        GET_MODE (src)),
5458                                    false_rtx);
5459
5460       SUBST (SET_SRC (x),
5461              simplify_gen_binary (IOR, GET_MODE (src),
5462                                   simplify_gen_binary (IOR, GET_MODE (src),
5463                                                        term1, term2),
5464                                   term3));
5465
5466       src = SET_SRC (x);
5467     }
5468
5469   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5470      whole thing fail.  */
5471   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5472     return src;
5473   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5474     return dest;
5475   else
5476     /* Convert this into a field assignment operation, if possible.  */
5477     return make_field_assignment (x);
5478 }
5479 \f
5480 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5481    result.  */
5482
5483 static rtx
5484 simplify_logical (rtx x)
5485 {
5486   enum machine_mode mode = GET_MODE (x);
5487   rtx op0 = XEXP (x, 0);
5488   rtx op1 = XEXP (x, 1);
5489
5490   switch (GET_CODE (x))
5491     {
5492     case AND:
5493       /* We can call simplify_and_const_int only if we don't lose
5494          any (sign) bits when converting INTVAL (op1) to
5495          "unsigned HOST_WIDE_INT".  */
5496       if (GET_CODE (op1) == CONST_INT
5497           && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5498               || INTVAL (op1) > 0))
5499         {
5500           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5501           if (GET_CODE (x) != AND)
5502             return x;
5503
5504           op0 = XEXP (x, 0);
5505           op1 = XEXP (x, 1);
5506         }
5507
5508       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5509          apply the distributive law and then the inverse distributive
5510          law to see if things simplify.  */
5511       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5512         {
5513           rtx result = distribute_and_simplify_rtx (x, 0);
5514           if (result)
5515             return result;
5516         }
5517       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5518         {
5519           rtx result = distribute_and_simplify_rtx (x, 1);
5520           if (result)
5521             return result;
5522         }
5523       break;
5524
5525     case IOR:
5526       /* If we have (ior (and A B) C), apply the distributive law and then
5527          the inverse distributive law to see if things simplify.  */
5528
5529       if (GET_CODE (op0) == AND)
5530         {
5531           rtx result = distribute_and_simplify_rtx (x, 0);
5532           if (result)
5533             return result;
5534         }
5535
5536       if (GET_CODE (op1) == AND)
5537         {
5538           rtx result = distribute_and_simplify_rtx (x, 1);
5539           if (result)
5540             return result;
5541         }
5542       break;
5543
5544     default:
5545       gcc_unreachable ();
5546     }
5547
5548   return x;
5549 }
5550 \f
5551 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5552    operations" because they can be replaced with two more basic operations.
5553    ZERO_EXTEND is also considered "compound" because it can be replaced with
5554    an AND operation, which is simpler, though only one operation.
5555
5556    The function expand_compound_operation is called with an rtx expression
5557    and will convert it to the appropriate shifts and AND operations,
5558    simplifying at each stage.
5559
5560    The function make_compound_operation is called to convert an expression
5561    consisting of shifts and ANDs into the equivalent compound expression.
5562    It is the inverse of this function, loosely speaking.  */
5563
5564 static rtx
5565 expand_compound_operation (rtx x)
5566 {
5567   unsigned HOST_WIDE_INT pos = 0, len;
5568   int unsignedp = 0;
5569   unsigned int modewidth;
5570   rtx tem;
5571
5572   switch (GET_CODE (x))
5573     {
5574     case ZERO_EXTEND:
5575       unsignedp = 1;
5576     case SIGN_EXTEND:
5577       /* We can't necessarily use a const_int for a multiword mode;
5578          it depends on implicitly extending the value.
5579          Since we don't know the right way to extend it,
5580          we can't tell whether the implicit way is right.
5581
5582          Even for a mode that is no wider than a const_int,
5583          we can't win, because we need to sign extend one of its bits through
5584          the rest of it, and we don't know which bit.  */
5585       if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5586         return x;
5587
5588       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5589          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
5590          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5591          reloaded. If not for that, MEM's would very rarely be safe.
5592
5593          Reject MODEs bigger than a word, because we might not be able
5594          to reference a two-register group starting with an arbitrary register
5595          (and currently gen_lowpart might crash for a SUBREG).  */
5596
5597       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5598         return x;
5599
5600       /* Reject MODEs that aren't scalar integers because turning vector
5601          or complex modes into shifts causes problems.  */
5602
5603       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5604         return x;
5605
5606       len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5607       /* If the inner object has VOIDmode (the only way this can happen
5608          is if it is an ASM_OPERANDS), we can't do anything since we don't
5609          know how much masking to do.  */
5610       if (len == 0)
5611         return x;
5612
5613       break;
5614
5615     case ZERO_EXTRACT:
5616       unsignedp = 1;
5617
5618       /* ... fall through ...  */
5619
5620     case SIGN_EXTRACT:
5621       /* If the operand is a CLOBBER, just return it.  */
5622       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5623         return XEXP (x, 0);
5624
5625       if (GET_CODE (XEXP (x, 1)) != CONST_INT
5626           || GET_CODE (XEXP (x, 2)) != CONST_INT
5627           || GET_MODE (XEXP (x, 0)) == VOIDmode)
5628         return x;
5629
5630       /* Reject MODEs that aren't scalar integers because turning vector
5631          or complex modes into shifts causes problems.  */
5632
5633       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5634         return x;
5635
5636       len = INTVAL (XEXP (x, 1));
5637       pos = INTVAL (XEXP (x, 2));
5638
5639       /* This should stay within the object being extracted, fail otherwise.  */
5640       if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5641         return x;
5642
5643       if (BITS_BIG_ENDIAN)
5644         pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5645
5646       break;
5647
5648     default:
5649       return x;
5650     }
5651   /* Convert sign extension to zero extension, if we know that the high
5652      bit is not set, as this is easier to optimize.  It will be converted
5653      back to cheaper alternative in make_extraction.  */
5654   if (GET_CODE (x) == SIGN_EXTEND
5655       && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5656           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5657                 & ~(((unsigned HOST_WIDE_INT)
5658                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5659                      >> 1))
5660                == 0)))
5661     {
5662       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5663       rtx temp2 = expand_compound_operation (temp);
5664
5665       /* Make sure this is a profitable operation.  */
5666       if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5667        return temp2;
5668       else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5669        return temp;
5670       else
5671        return x;
5672     }
5673
5674   /* We can optimize some special cases of ZERO_EXTEND.  */
5675   if (GET_CODE (x) == ZERO_EXTEND)
5676     {
5677       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5678          know that the last value didn't have any inappropriate bits
5679          set.  */
5680       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5681           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5682           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5683           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5684               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5685         return XEXP (XEXP (x, 0), 0);
5686
5687       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5688       if (GET_CODE (XEXP (x, 0)) == SUBREG
5689           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5690           && subreg_lowpart_p (XEXP (x, 0))
5691           && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5692           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5693               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5694         return SUBREG_REG (XEXP (x, 0));
5695
5696       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5697          is a comparison and STORE_FLAG_VALUE permits.  This is like
5698          the first case, but it works even when GET_MODE (x) is larger
5699          than HOST_WIDE_INT.  */
5700       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5701           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5702           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5703           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5704               <= HOST_BITS_PER_WIDE_INT)
5705           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5706               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5707         return XEXP (XEXP (x, 0), 0);
5708
5709       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
5710       if (GET_CODE (XEXP (x, 0)) == SUBREG
5711           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5712           && subreg_lowpart_p (XEXP (x, 0))
5713           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5714           && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5715               <= HOST_BITS_PER_WIDE_INT)
5716           && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5717               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5718         return SUBREG_REG (XEXP (x, 0));
5719
5720     }
5721
5722   /* If we reach here, we want to return a pair of shifts.  The inner
5723      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
5724      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
5725      logical depending on the value of UNSIGNEDP.
5726
5727      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5728      converted into an AND of a shift.
5729
5730      We must check for the case where the left shift would have a negative
5731      count.  This can happen in a case like (x >> 31) & 255 on machines
5732      that can't shift by a constant.  On those machines, we would first
5733      combine the shift with the AND to produce a variable-position
5734      extraction.  Then the constant of 31 would be substituted in to produce
5735      a such a position.  */
5736
5737   modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5738   if (modewidth + len >= pos)
5739     tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5740                                 GET_MODE (x),
5741                                 simplify_shift_const (NULL_RTX, ASHIFT,
5742                                                       GET_MODE (x),
5743                                                       XEXP (x, 0),
5744                                                       modewidth - pos - len),
5745                                 modewidth - len);
5746
5747   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5748     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5749                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
5750                                                         GET_MODE (x),
5751                                                         XEXP (x, 0), pos),
5752                                   ((HOST_WIDE_INT) 1 << len) - 1);
5753   else
5754     /* Any other cases we can't handle.  */
5755     return x;
5756
5757   /* If we couldn't do this for some reason, return the original
5758      expression.  */
5759   if (GET_CODE (tem) == CLOBBER)
5760     return x;
5761
5762   return tem;
5763 }
5764 \f
5765 /* X is a SET which contains an assignment of one object into
5766    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5767    or certain SUBREGS). If possible, convert it into a series of
5768    logical operations.
5769
5770    We half-heartedly support variable positions, but do not at all
5771    support variable lengths.  */
5772
5773 static rtx
5774 expand_field_assignment (rtx x)
5775 {
5776   rtx inner;
5777   rtx pos;                      /* Always counts from low bit.  */
5778   int len;
5779   rtx mask, cleared, masked;
5780   enum machine_mode compute_mode;
5781
5782   /* Loop until we find something we can't simplify.  */
5783   while (1)
5784     {
5785       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5786           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5787         {
5788           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5789           len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5790           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5791         }
5792       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5793                && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5794         {
5795           inner = XEXP (SET_DEST (x), 0);
5796           len = INTVAL (XEXP (SET_DEST (x), 1));
5797           pos = XEXP (SET_DEST (x), 2);
5798
5799           /* A constant position should stay within the width of INNER.  */
5800           if (GET_CODE (pos) == CONST_INT
5801               && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5802             break;
5803
5804           if (BITS_BIG_ENDIAN)
5805             {
5806               if (GET_CODE (pos) == CONST_INT)
5807                 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5808                                - INTVAL (pos));
5809               else if (GET_CODE (pos) == MINUS
5810                        && GET_CODE (XEXP (pos, 1)) == CONST_INT
5811                        && (INTVAL (XEXP (pos, 1))
5812                            == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5813                 /* If position is ADJUST - X, new position is X.  */
5814                 pos = XEXP (pos, 0);
5815               else
5816                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5817                                            GEN_INT (GET_MODE_BITSIZE (
5818                                                     GET_MODE (inner))
5819                                                     - len),
5820                                            pos);
5821             }
5822         }
5823
5824       /* A SUBREG between two modes that occupy the same numbers of words
5825          can be done by moving the SUBREG to the source.  */
5826       else if (GET_CODE (SET_DEST (x)) == SUBREG
5827                /* We need SUBREGs to compute nonzero_bits properly.  */
5828                && nonzero_sign_valid
5829                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5830                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5831                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5832                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5833         {
5834           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5835                            gen_lowpart
5836                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
5837                             SET_SRC (x)));
5838           continue;
5839         }
5840       else
5841         break;
5842
5843       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5844         inner = SUBREG_REG (inner);
5845
5846       compute_mode = GET_MODE (inner);
5847
5848       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
5849       if (! SCALAR_INT_MODE_P (compute_mode))
5850         {
5851           enum machine_mode imode;
5852
5853           /* Don't do anything for vector or complex integral types.  */
5854           if (! FLOAT_MODE_P (compute_mode))
5855             break;
5856
5857           /* Try to find an integral mode to pun with.  */
5858           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5859           if (imode == BLKmode)
5860             break;
5861
5862           compute_mode = imode;
5863           inner = gen_lowpart (imode, inner);
5864         }
5865
5866       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
5867       if (len >= HOST_BITS_PER_WIDE_INT)
5868         break;
5869
5870       /* Now compute the equivalent expression.  Make a copy of INNER
5871          for the SET_DEST in case it is a MEM into which we will substitute;
5872          we don't want shared RTL in that case.  */
5873       mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5874       cleared = simplify_gen_binary (AND, compute_mode,
5875                                      simplify_gen_unary (NOT, compute_mode,
5876                                        simplify_gen_binary (ASHIFT,
5877                                                             compute_mode,
5878                                                             mask, pos),
5879                                        compute_mode),
5880                                      inner);
5881       masked = simplify_gen_binary (ASHIFT, compute_mode,
5882                                     simplify_gen_binary (
5883                                       AND, compute_mode,
5884                                       gen_lowpart (compute_mode, SET_SRC (x)),
5885                                       mask),
5886                                     pos);
5887
5888       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5889                        simplify_gen_binary (IOR, compute_mode,
5890                                             cleared, masked));
5891     }
5892
5893   return x;
5894 }
5895 \f
5896 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
5897    it is an RTX that represents a variable starting position; otherwise,
5898    POS is the (constant) starting bit position (counted from the LSB).
5899
5900    UNSIGNEDP is nonzero for an unsigned reference and zero for a
5901    signed reference.
5902
5903    IN_DEST is nonzero if this is a reference in the destination of a
5904    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
5905    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5906    be used.
5907
5908    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
5909    ZERO_EXTRACT should be built even for bits starting at bit 0.
5910
5911    MODE is the desired mode of the result (if IN_DEST == 0).
5912
5913    The result is an RTX for the extraction or NULL_RTX if the target
5914    can't handle it.  */
5915
5916 static rtx
5917 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5918                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5919                  int in_dest, int in_compare)
5920 {
5921   /* This mode describes the size of the storage area
5922      to fetch the overall value from.  Within that, we
5923      ignore the POS lowest bits, etc.  */
5924   enum machine_mode is_mode = GET_MODE (inner);
5925   enum machine_mode inner_mode;
5926   enum machine_mode wanted_inner_mode;
5927   enum machine_mode wanted_inner_reg_mode = word_mode;
5928   enum machine_mode pos_mode = word_mode;
5929   enum machine_mode extraction_mode = word_mode;
5930   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5931   rtx new = 0;
5932   rtx orig_pos_rtx = pos_rtx;
5933   HOST_WIDE_INT orig_pos;
5934
5935   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5936     {
5937       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5938          consider just the QI as the memory to extract from.
5939          The subreg adds or removes high bits; its mode is
5940          irrelevant to the meaning of this extraction,
5941          since POS and LEN count from the lsb.  */
5942       if (MEM_P (SUBREG_REG (inner)))
5943         is_mode = GET_MODE (SUBREG_REG (inner));
5944       inner = SUBREG_REG (inner);
5945     }
5946   else if (GET_CODE (inner) == ASHIFT
5947            && GET_CODE (XEXP (inner, 1)) == CONST_INT
5948            && pos_rtx == 0 && pos == 0
5949            && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5950     {
5951       /* We're extracting the least significant bits of an rtx
5952          (ashift X (const_int C)), where LEN > C.  Extract the
5953          least significant (LEN - C) bits of X, giving an rtx
5954          whose mode is MODE, then shift it left C times.  */
5955       new = make_extraction (mode, XEXP (inner, 0),
5956                              0, 0, len - INTVAL (XEXP (inner, 1)),
5957                              unsignedp, in_dest, in_compare);
5958       if (new != 0)
5959         return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5960     }
5961
5962   inner_mode = GET_MODE (inner);
5963
5964   if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5965     pos = INTVAL (pos_rtx), pos_rtx = 0;
5966
5967   /* See if this can be done without an extraction.  We never can if the
5968      width of the field is not the same as that of some integer mode. For
5969      registers, we can only avoid the extraction if the position is at the
5970      low-order bit and this is either not in the destination or we have the
5971      appropriate STRICT_LOW_PART operation available.
5972
5973      For MEM, we can avoid an extract if the field starts on an appropriate
5974      boundary and we can change the mode of the memory reference.  */
5975
5976   if (tmode != BLKmode
5977       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5978            && !MEM_P (inner)
5979            && (inner_mode == tmode
5980                || !REG_P (inner)
5981                || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5982                                          GET_MODE_BITSIZE (inner_mode))
5983                || reg_truncated_to_mode (tmode, inner))
5984            && (! in_dest
5985                || (REG_P (inner)
5986                    && have_insn_for (STRICT_LOW_PART, tmode))))
5987           || (MEM_P (inner) && pos_rtx == 0
5988               && (pos
5989                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5990                      : BITS_PER_UNIT)) == 0
5991               /* We can't do this if we are widening INNER_MODE (it
5992                  may not be aligned, for one thing).  */
5993               && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5994               && (inner_mode == tmode
5995                   || (! mode_dependent_address_p (XEXP (inner, 0))
5996                       && ! MEM_VOLATILE_P (inner))))))
5997     {
5998       /* If INNER is a MEM, make a new MEM that encompasses just the desired
5999          field.  If the original and current mode are the same, we need not
6000          adjust the offset.  Otherwise, we do if bytes big endian.
6001
6002          If INNER is not a MEM, get a piece consisting of just the field
6003          of interest (in this case POS % BITS_PER_WORD must be 0).  */
6004
6005       if (MEM_P (inner))
6006         {
6007           HOST_WIDE_INT offset;
6008
6009           /* POS counts from lsb, but make OFFSET count in memory order.  */
6010           if (BYTES_BIG_ENDIAN)
6011             offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6012           else
6013             offset = pos / BITS_PER_UNIT;
6014
6015           new = adjust_address_nv (inner, tmode, offset);
6016         }
6017       else if (REG_P (inner))
6018         {
6019           if (tmode != inner_mode)
6020             {
6021               /* We can't call gen_lowpart in a DEST since we
6022                  always want a SUBREG (see below) and it would sometimes
6023                  return a new hard register.  */
6024               if (pos || in_dest)
6025                 {
6026                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6027
6028                   if (WORDS_BIG_ENDIAN
6029                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6030                     final_word = ((GET_MODE_SIZE (inner_mode)
6031                                    - GET_MODE_SIZE (tmode))
6032                                   / UNITS_PER_WORD) - final_word;
6033
6034                   final_word *= UNITS_PER_WORD;
6035                   if (BYTES_BIG_ENDIAN &&
6036                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6037                     final_word += (GET_MODE_SIZE (inner_mode)
6038                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6039
6040                   /* Avoid creating invalid subregs, for example when
6041                      simplifying (x>>32)&255.  */
6042                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
6043                     return NULL_RTX;
6044
6045                   new = gen_rtx_SUBREG (tmode, inner, final_word);
6046                 }
6047               else
6048                 new = gen_lowpart (tmode, inner);
6049             }
6050           else
6051             new = inner;
6052         }
6053       else
6054         new = force_to_mode (inner, tmode,
6055                              len >= HOST_BITS_PER_WIDE_INT
6056                              ? ~(unsigned HOST_WIDE_INT) 0
6057                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6058                              0);
6059
6060       /* If this extraction is going into the destination of a SET,
6061          make a STRICT_LOW_PART unless we made a MEM.  */
6062
6063       if (in_dest)
6064         return (MEM_P (new) ? new
6065                 : (GET_CODE (new) != SUBREG
6066                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
6067                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6068
6069       if (mode == tmode)
6070         return new;
6071
6072       if (GET_CODE (new) == CONST_INT)
6073         return gen_int_mode (INTVAL (new), mode);
6074
6075       /* If we know that no extraneous bits are set, and that the high
6076          bit is not set, convert the extraction to the cheaper of
6077          sign and zero extension, that are equivalent in these cases.  */
6078       if (flag_expensive_optimizations
6079           && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6080               && ((nonzero_bits (new, tmode)
6081                    & ~(((unsigned HOST_WIDE_INT)
6082                         GET_MODE_MASK (tmode))
6083                        >> 1))
6084                   == 0)))
6085         {
6086           rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6087           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6088
6089           /* Prefer ZERO_EXTENSION, since it gives more information to
6090              backends.  */
6091           if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6092             return temp;
6093           return temp1;
6094         }
6095
6096       /* Otherwise, sign- or zero-extend unless we already are in the
6097          proper mode.  */
6098
6099       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6100                              mode, new));
6101     }
6102
6103   /* Unless this is a COMPARE or we have a funny memory reference,
6104      don't do anything with zero-extending field extracts starting at
6105      the low-order bit since they are simple AND operations.  */
6106   if (pos_rtx == 0 && pos == 0 && ! in_dest
6107       && ! in_compare && unsignedp)
6108     return 0;
6109
6110   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6111      if the position is not a constant and the length is not 1.  In all
6112      other cases, we would only be going outside our object in cases when
6113      an original shift would have been undefined.  */
6114   if (MEM_P (inner)
6115       && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6116           || (pos_rtx != 0 && len != 1)))
6117     return 0;
6118
6119   /* Get the mode to use should INNER not be a MEM, the mode for the position,
6120      and the mode for the result.  */
6121   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6122     {
6123       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6124       pos_mode = mode_for_extraction (EP_insv, 2);
6125       extraction_mode = mode_for_extraction (EP_insv, 3);
6126     }
6127
6128   if (! in_dest && unsignedp
6129       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6130     {
6131       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6132       pos_mode = mode_for_extraction (EP_extzv, 3);
6133       extraction_mode = mode_for_extraction (EP_extzv, 0);
6134     }
6135
6136   if (! in_dest && ! unsignedp
6137       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6138     {
6139       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6140       pos_mode = mode_for_extraction (EP_extv, 3);
6141       extraction_mode = mode_for_extraction (EP_extv, 0);
6142     }
6143
6144   /* Never narrow an object, since that might not be safe.  */
6145
6146   if (mode != VOIDmode
6147       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6148     extraction_mode = mode;
6149
6150   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6151       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6152     pos_mode = GET_MODE (pos_rtx);
6153
6154   /* If this is not from memory, the desired mode is the preferred mode
6155      for an extraction pattern's first input operand, or word_mode if there
6156      is none.  */
6157   if (!MEM_P (inner))
6158     wanted_inner_mode = wanted_inner_reg_mode;
6159   else
6160     {
6161       /* Be careful not to go beyond the extracted object and maintain the
6162          natural alignment of the memory.  */
6163       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6164       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6165              > GET_MODE_BITSIZE (wanted_inner_mode))
6166         {
6167           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6168           gcc_assert (wanted_inner_mode != VOIDmode);
6169         }
6170
6171       /* If we have to change the mode of memory and cannot, the desired mode
6172          is EXTRACTION_MODE.  */
6173       if (inner_mode != wanted_inner_mode
6174           && (mode_dependent_address_p (XEXP (inner, 0))
6175               || MEM_VOLATILE_P (inner)
6176               || pos_rtx))
6177         wanted_inner_mode = extraction_mode;
6178     }
6179
6180   orig_pos = pos;
6181
6182   if (BITS_BIG_ENDIAN)
6183     {
6184       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6185          BITS_BIG_ENDIAN style.  If position is constant, compute new
6186          position.  Otherwise, build subtraction.
6187          Note that POS is relative to the mode of the original argument.
6188          If it's a MEM we need to recompute POS relative to that.
6189          However, if we're extracting from (or inserting into) a register,
6190          we want to recompute POS relative to wanted_inner_mode.  */
6191       int width = (MEM_P (inner)
6192                    ? GET_MODE_BITSIZE (is_mode)
6193                    : GET_MODE_BITSIZE (wanted_inner_mode));
6194
6195       if (pos_rtx == 0)
6196         pos = width - len - pos;
6197       else
6198         pos_rtx
6199           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6200       /* POS may be less than 0 now, but we check for that below.
6201          Note that it can only be less than 0 if !MEM_P (inner).  */
6202     }
6203
6204   /* If INNER has a wider mode, and this is a constant extraction, try to
6205      make it smaller and adjust the byte to point to the byte containing
6206      the value.  */
6207   if (wanted_inner_mode != VOIDmode
6208       && inner_mode != wanted_inner_mode
6209       && ! pos_rtx
6210       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6211       && MEM_P (inner)
6212       && ! mode_dependent_address_p (XEXP (inner, 0))
6213       && ! MEM_VOLATILE_P (inner))
6214     {
6215       int offset = 0;
6216
6217       /* The computations below will be correct if the machine is big
6218          endian in both bits and bytes or little endian in bits and bytes.
6219          If it is mixed, we must adjust.  */
6220
6221       /* If bytes are big endian and we had a paradoxical SUBREG, we must
6222          adjust OFFSET to compensate.  */
6223       if (BYTES_BIG_ENDIAN
6224           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6225         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6226
6227       /* We can now move to the desired byte.  */
6228       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6229                 * GET_MODE_SIZE (wanted_inner_mode);
6230       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6231
6232       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6233           && is_mode != wanted_inner_mode)
6234         offset = (GET_MODE_SIZE (is_mode)
6235                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
6236
6237       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6238     }
6239
6240   /* If INNER is not memory, we can always get it into the proper mode.  If we
6241      are changing its mode, POS must be a constant and smaller than the size
6242      of the new mode.  */
6243   else if (!MEM_P (inner))
6244     {
6245       if (GET_MODE (inner) != wanted_inner_mode
6246           && (pos_rtx != 0
6247               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6248         return 0;
6249
6250       if (orig_pos < 0)
6251         return 0;
6252
6253       inner = force_to_mode (inner, wanted_inner_mode,
6254                              pos_rtx
6255                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6256                              ? ~(unsigned HOST_WIDE_INT) 0
6257                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6258                                 << orig_pos),
6259                              0);
6260     }
6261
6262   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
6263      have to zero extend.  Otherwise, we can just use a SUBREG.  */
6264   if (pos_rtx != 0
6265       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6266     {
6267       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6268
6269       /* If we know that no extraneous bits are set, and that the high
6270          bit is not set, convert extraction to cheaper one - either
6271          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6272          cases.  */
6273       if (flag_expensive_optimizations
6274           && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6275               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6276                    & ~(((unsigned HOST_WIDE_INT)
6277                         GET_MODE_MASK (GET_MODE (pos_rtx)))
6278                        >> 1))
6279                   == 0)))
6280         {
6281           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6282
6283           /* Prefer ZERO_EXTENSION, since it gives more information to
6284              backends.  */
6285           if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6286             temp = temp1;
6287         }
6288       pos_rtx = temp;
6289     }
6290   else if (pos_rtx != 0
6291            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6292     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6293
6294   /* Make POS_RTX unless we already have it and it is correct.  If we don't
6295      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6296      be a CONST_INT.  */
6297   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6298     pos_rtx = orig_pos_rtx;
6299
6300   else if (pos_rtx == 0)
6301     pos_rtx = GEN_INT (pos);
6302
6303   /* Make the required operation.  See if we can use existing rtx.  */
6304   new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6305                          extraction_mode, inner, GEN_INT (len), pos_rtx);
6306   if (! in_dest)
6307     new = gen_lowpart (mode, new);
6308
6309   return new;
6310 }
6311 \f
6312 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6313    with any other operations in X.  Return X without that shift if so.  */
6314
6315 static rtx
6316 extract_left_shift (rtx x, int count)
6317 {
6318   enum rtx_code code = GET_CODE (x);
6319   enum machine_mode mode = GET_MODE (x);
6320   rtx tem;
6321
6322   switch (code)
6323     {
6324     case ASHIFT:
6325       /* This is the shift itself.  If it is wide enough, we will return
6326          either the value being shifted if the shift count is equal to
6327          COUNT or a shift for the difference.  */
6328       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6329           && INTVAL (XEXP (x, 1)) >= count)
6330         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6331                                      INTVAL (XEXP (x, 1)) - count);
6332       break;
6333
6334     case NEG:  case NOT:
6335       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6336         return simplify_gen_unary (code, mode, tem, mode);
6337
6338       break;
6339
6340     case PLUS:  case IOR:  case XOR:  case AND:
6341       /* If we can safely shift this constant and we find the inner shift,
6342          make a new operation.  */
6343       if (GET_CODE (XEXP (x, 1)) == CONST_INT
6344           && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6345           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6346         return simplify_gen_binary (code, mode, tem,
6347                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6348
6349       break;
6350
6351     default:
6352       break;
6353     }
6354
6355   return 0;
6356 }
6357 \f
6358 /* Look at the expression rooted at X.  Look for expressions
6359    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6360    Form these expressions.
6361
6362    Return the new rtx, usually just X.
6363
6364    Also, for machines like the VAX that don't have logical shift insns,
6365    try to convert logical to arithmetic shift operations in cases where
6366    they are equivalent.  This undoes the canonicalizations to logical
6367    shifts done elsewhere.
6368
6369    We try, as much as possible, to re-use rtl expressions to save memory.
6370
6371    IN_CODE says what kind of expression we are processing.  Normally, it is
6372    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
6373    being kludges), it is MEM.  When processing the arguments of a comparison
6374    or a COMPARE against zero, it is COMPARE.  */
6375
6376 static rtx
6377 make_compound_operation (rtx x, enum rtx_code in_code)
6378 {
6379   enum rtx_code code = GET_CODE (x);
6380   enum machine_mode mode = GET_MODE (x);
6381   int mode_width = GET_MODE_BITSIZE (mode);
6382   rtx rhs, lhs;
6383   enum rtx_code next_code;
6384   int i;
6385   rtx new = 0;
6386   rtx tem;
6387   const char *fmt;
6388
6389   /* Select the code to be used in recursive calls.  Once we are inside an
6390      address, we stay there.  If we have a comparison, set to COMPARE,
6391      but once inside, go back to our default of SET.  */
6392
6393   next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6394                : ((code == COMPARE || COMPARISON_P (x))
6395                   && XEXP (x, 1) == const0_rtx) ? COMPARE
6396                : in_code == COMPARE ? SET : in_code);
6397
6398   /* Process depending on the code of this operation.  If NEW is set
6399      nonzero, it will be returned.  */
6400
6401   switch (code)
6402     {
6403     case ASHIFT:
6404       /* Convert shifts by constants into multiplications if inside
6405          an address.  */
6406       if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6407           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6408           && INTVAL (XEXP (x, 1)) >= 0)
6409         {
6410           new = make_compound_operation (XEXP (x, 0), next_code);
6411           new = gen_rtx_MULT (mode, new,
6412                               GEN_INT ((HOST_WIDE_INT) 1
6413                                        << INTVAL (XEXP (x, 1))));
6414         }
6415       break;
6416
6417     case AND:
6418       /* If the second operand is not a constant, we can't do anything
6419          with it.  */
6420       if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6421         break;
6422
6423       /* If the constant is a power of two minus one and the first operand
6424          is a logical right shift, make an extraction.  */
6425       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6426           && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6427         {
6428           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6429           new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6430                                  0, in_code == COMPARE);
6431         }
6432
6433       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
6434       else if (GET_CODE (XEXP (x, 0)) == SUBREG
6435                && subreg_lowpart_p (XEXP (x, 0))
6436                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6437                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6438         {
6439           new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6440                                          next_code);
6441           new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6442                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6443                                  0, in_code == COMPARE);
6444         }
6445       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
6446       else if ((GET_CODE (XEXP (x, 0)) == XOR
6447                 || GET_CODE (XEXP (x, 0)) == IOR)
6448                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6449                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6450                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6451         {
6452           /* Apply the distributive law, and then try to make extractions.  */
6453           new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6454                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6455                                              XEXP (x, 1)),
6456                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6457                                              XEXP (x, 1)));
6458           new = make_compound_operation (new, in_code);
6459         }
6460
6461       /* If we are have (and (rotate X C) M) and C is larger than the number
6462          of bits in M, this is an extraction.  */
6463
6464       else if (GET_CODE (XEXP (x, 0)) == ROTATE
6465                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6466                && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6467                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6468         {
6469           new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6470           new = make_extraction (mode, new,
6471                                  (GET_MODE_BITSIZE (mode)
6472                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
6473                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
6474         }
6475
6476       /* On machines without logical shifts, if the operand of the AND is
6477          a logical shift and our mask turns off all the propagated sign
6478          bits, we can replace the logical shift with an arithmetic shift.  */
6479       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6480                && !have_insn_for (LSHIFTRT, mode)
6481                && have_insn_for (ASHIFTRT, mode)
6482                && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6483                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6484                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6485                && mode_width <= HOST_BITS_PER_WIDE_INT)
6486         {
6487           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6488
6489           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6490           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6491             SUBST (XEXP (x, 0),
6492                    gen_rtx_ASHIFTRT (mode,
6493                                      make_compound_operation
6494                                      (XEXP (XEXP (x, 0), 0), next_code),
6495                                      XEXP (XEXP (x, 0), 1)));
6496         }
6497
6498       /* If the constant is one less than a power of two, this might be
6499          representable by an extraction even if no shift is present.
6500          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6501          we are in a COMPARE.  */
6502       else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6503         new = make_extraction (mode,
6504                                make_compound_operation (XEXP (x, 0),
6505                                                         next_code),
6506                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6507
6508       /* If we are in a comparison and this is an AND with a power of two,
6509          convert this into the appropriate bit extract.  */
6510       else if (in_code == COMPARE
6511                && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6512         new = make_extraction (mode,
6513                                make_compound_operation (XEXP (x, 0),
6514                                                         next_code),
6515                                i, NULL_RTX, 1, 1, 0, 1);
6516
6517       break;
6518
6519     case LSHIFTRT:
6520       /* If the sign bit is known to be zero, replace this with an
6521          arithmetic shift.  */
6522       if (have_insn_for (ASHIFTRT, mode)
6523           && ! have_insn_for (LSHIFTRT, mode)
6524           && mode_width <= HOST_BITS_PER_WIDE_INT
6525           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6526         {
6527           new = gen_rtx_ASHIFTRT (mode,
6528                                   make_compound_operation (XEXP (x, 0),
6529                                                            next_code),
6530                                   XEXP (x, 1));
6531           break;
6532         }
6533
6534       /* ... fall through ...  */
6535
6536     case ASHIFTRT:
6537       lhs = XEXP (x, 0);
6538       rhs = XEXP (x, 1);
6539
6540       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6541          this is a SIGN_EXTRACT.  */
6542       if (GET_CODE (rhs) == CONST_INT
6543           && GET_CODE (lhs) == ASHIFT
6544           && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6545           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6546         {
6547           new = make_compound_operation (XEXP (lhs, 0), next_code);
6548           new = make_extraction (mode, new,
6549                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6550                                  NULL_RTX, mode_width - INTVAL (rhs),
6551                                  code == LSHIFTRT, 0, in_code == COMPARE);
6552           break;
6553         }
6554
6555       /* See if we have operations between an ASHIFTRT and an ASHIFT.
6556          If so, try to merge the shifts into a SIGN_EXTEND.  We could
6557          also do this for some cases of SIGN_EXTRACT, but it doesn't
6558          seem worth the effort; the case checked for occurs on Alpha.  */
6559
6560       if (!OBJECT_P (lhs)
6561           && ! (GET_CODE (lhs) == SUBREG
6562                 && (OBJECT_P (SUBREG_REG (lhs))))
6563           && GET_CODE (rhs) == CONST_INT
6564           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6565           && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6566         new = make_extraction (mode, make_compound_operation (new, next_code),
6567                                0, NULL_RTX, mode_width - INTVAL (rhs),
6568                                code == LSHIFTRT, 0, in_code == COMPARE);
6569
6570       break;
6571
6572     case SUBREG:
6573       /* Call ourselves recursively on the inner expression.  If we are
6574          narrowing the object and it has a different RTL code from
6575          what it originally did, do this SUBREG as a force_to_mode.  */
6576
6577       tem = make_compound_operation (SUBREG_REG (x), in_code);
6578
6579       {
6580         rtx simplified;
6581         simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6582                                       SUBREG_BYTE (x));
6583
6584         if (simplified)
6585           tem = simplified;
6586
6587         if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6588             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6589             && subreg_lowpart_p (x))
6590           {
6591             rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6592                                        0);
6593
6594             /* If we have something other than a SUBREG, we might have
6595                done an expansion, so rerun ourselves.  */
6596             if (GET_CODE (newer) != SUBREG)
6597               newer = make_compound_operation (newer, in_code);
6598
6599             return newer;
6600           }
6601
6602         if (simplified)
6603           return tem;
6604       }
6605       break;
6606
6607     default:
6608       break;
6609     }
6610
6611   if (new)
6612     {
6613       x = gen_lowpart (mode, new);
6614       code = GET_CODE (x);
6615     }
6616
6617   /* Now recursively process each operand of this operation.  */
6618   fmt = GET_RTX_FORMAT (code);
6619   for (i = 0; i < GET_RTX_LENGTH (code); i++)
6620     if (fmt[i] == 'e')
6621       {
6622         new = make_compound_operation (XEXP (x, i), next_code);
6623         SUBST (XEXP (x, i), new);
6624       }
6625
6626   /* If this is a commutative operation, the changes to the operands
6627      may have made it noncanonical.  */
6628   if (COMMUTATIVE_ARITH_P (x)
6629       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6630     {
6631       tem = XEXP (x, 0);
6632       SUBST (XEXP (x, 0), XEXP (x, 1));
6633       SUBST (XEXP (x, 1), tem);
6634     }
6635
6636   return x;
6637 }
6638 \f
6639 /* Given M see if it is a value that would select a field of bits
6640    within an item, but not the entire word.  Return -1 if not.
6641    Otherwise, return the starting position of the field, where 0 is the
6642    low-order bit.
6643
6644    *PLEN is set to the length of the field.  */
6645
6646 static int
6647 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6648 {
6649   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
6650   int pos = exact_log2 (m & -m);
6651   int len = 0;
6652
6653   if (pos >= 0)
6654     /* Now shift off the low-order zero bits and see if we have a
6655        power of two minus 1.  */
6656     len = exact_log2 ((m >> pos) + 1);
6657
6658   if (len <= 0)
6659     pos = -1;
6660
6661   *plen = len;
6662   return pos;
6663 }
6664 \f
6665 /* If X refers to a register that equals REG in value, replace these
6666    references with REG.  */
6667 static rtx
6668 canon_reg_for_combine (rtx x, rtx reg)
6669 {
6670   rtx op0, op1, op2;
6671   const char *fmt;
6672   int i;
6673   bool copied;
6674
6675   enum rtx_code code = GET_CODE (x);
6676   switch (GET_RTX_CLASS (code))
6677     {
6678     case RTX_UNARY:
6679       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6680       if (op0 != XEXP (x, 0))
6681         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6682                                    GET_MODE (reg));
6683       break;
6684
6685     case RTX_BIN_ARITH:
6686     case RTX_COMM_ARITH:
6687       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6688       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6689       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6690         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6691       break;
6692
6693     case RTX_COMPARE:
6694     case RTX_COMM_COMPARE:
6695       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6696       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6697       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6698         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6699                                         GET_MODE (op0), op0, op1);
6700       break;
6701
6702     case RTX_TERNARY:
6703     case RTX_BITFIELD_OPS:
6704       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6705       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6706       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6707       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6708         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6709                                      GET_MODE (op0), op0, op1, op2);
6710
6711     case RTX_OBJ:
6712       if (REG_P (x))
6713         {
6714           if (rtx_equal_p (get_last_value (reg), x)
6715               || rtx_equal_p (reg, get_last_value (x)))
6716             return reg;
6717           else
6718             break;
6719         }
6720
6721       /* fall through */
6722
6723     default:
6724       fmt = GET_RTX_FORMAT (code);
6725       copied = false;
6726       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6727         if (fmt[i] == 'e')
6728           {
6729             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6730             if (op != XEXP (x, i))
6731               {
6732                 if (!copied)
6733                   {
6734                     copied = true;
6735                     x = copy_rtx (x);
6736                   }
6737                 XEXP (x, i) = op;
6738               }
6739           }
6740         else if (fmt[i] == 'E')
6741           {
6742             int j;
6743             for (j = 0; j < XVECLEN (x, i); j++)
6744               {
6745                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6746                 if (op != XVECEXP (x, i, j))
6747                   {
6748                     if (!copied)
6749                       {
6750                         copied = true;
6751                         x = copy_rtx (x);
6752                       }
6753                     XVECEXP (x, i, j) = op;
6754                   }
6755               }
6756           }
6757
6758       break;
6759     }
6760
6761   return x;
6762 }
6763
6764 /* Return X converted to MODE.  If the value is already truncated to
6765    MODE we can just return a subreg even though in the general case we
6766    would need an explicit truncation.  */
6767
6768 static rtx
6769 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6770 {
6771   if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6772       || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6773                                 GET_MODE_BITSIZE (GET_MODE (x)))
6774       || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6775     return gen_lowpart (mode, x);
6776   else
6777     return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6778 }
6779
6780 /* See if X can be simplified knowing that we will only refer to it in
6781    MODE and will only refer to those bits that are nonzero in MASK.
6782    If other bits are being computed or if masking operations are done
6783    that select a superset of the bits in MASK, they can sometimes be
6784    ignored.
6785
6786    Return a possibly simplified expression, but always convert X to
6787    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
6788
6789    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6790    are all off in X.  This is used when X will be complemented, by either
6791    NOT, NEG, or XOR.  */
6792
6793 static rtx
6794 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6795                int just_select)
6796 {
6797   enum rtx_code code = GET_CODE (x);
6798   int next_select = just_select || code == XOR || code == NOT || code == NEG;
6799   enum machine_mode op_mode;
6800   unsigned HOST_WIDE_INT fuller_mask, nonzero;
6801   rtx op0, op1, temp;
6802
6803   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
6804      code below will do the wrong thing since the mode of such an
6805      expression is VOIDmode.
6806
6807      Also do nothing if X is a CLOBBER; this can happen if X was
6808      the return value from a call to gen_lowpart.  */
6809   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6810     return x;
6811
6812   /* We want to perform the operation is its present mode unless we know
6813      that the operation is valid in MODE, in which case we do the operation
6814      in MODE.  */
6815   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6816               && have_insn_for (code, mode))
6817              ? mode : GET_MODE (x));
6818
6819   /* It is not valid to do a right-shift in a narrower mode
6820      than the one it came in with.  */
6821   if ((code == LSHIFTRT || code == ASHIFTRT)
6822       && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6823     op_mode = GET_MODE (x);
6824
6825   /* Truncate MASK to fit OP_MODE.  */
6826   if (op_mode)
6827     mask &= GET_MODE_MASK (op_mode);
6828
6829   /* When we have an arithmetic operation, or a shift whose count we
6830      do not know, we need to assume that all bits up to the highest-order
6831      bit in MASK will be needed.  This is how we form such a mask.  */
6832   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6833     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6834   else
6835     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6836                    - 1);
6837
6838   /* Determine what bits of X are guaranteed to be (non)zero.  */
6839   nonzero = nonzero_bits (x, mode);
6840
6841   /* If none of the bits in X are needed, return a zero.  */
6842   if (! just_select && (nonzero & mask) == 0)
6843     x = const0_rtx;
6844
6845   /* If X is a CONST_INT, return a new one.  Do this here since the
6846      test below will fail.  */
6847   if (GET_CODE (x) == CONST_INT)
6848     {
6849       if (SCALAR_INT_MODE_P (mode))
6850         return gen_int_mode (INTVAL (x) & mask, mode);
6851       else
6852         {
6853           x = GEN_INT (INTVAL (x) & mask);
6854           return gen_lowpart_common (mode, x);
6855         }
6856     }
6857
6858   /* If X is narrower than MODE and we want all the bits in X's mode, just
6859      get X in the proper mode.  */
6860   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6861       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6862     return gen_lowpart (mode, x);
6863
6864   switch (code)
6865     {
6866     case CLOBBER:
6867       /* If X is a (clobber (const_int)), return it since we know we are
6868          generating something that won't match.  */
6869       return x;
6870
6871     case SIGN_EXTEND:
6872     case ZERO_EXTEND:
6873     case ZERO_EXTRACT:
6874     case SIGN_EXTRACT:
6875       x = expand_compound_operation (x);
6876       if (GET_CODE (x) != code)
6877         return force_to_mode (x, mode, mask, next_select);
6878       break;
6879
6880     case SUBREG:
6881       if (subreg_lowpart_p (x)
6882           /* We can ignore the effect of this SUBREG if it narrows the mode or
6883              if the constant masks to zero all the bits the mode doesn't
6884              have.  */
6885           && ((GET_MODE_SIZE (GET_MODE (x))
6886                < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6887               || (0 == (mask
6888                         & GET_MODE_MASK (GET_MODE (x))
6889                         & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6890         return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6891       break;
6892
6893     case AND:
6894       /* If this is an AND with a constant, convert it into an AND
6895          whose constant is the AND of that constant with MASK.  If it
6896          remains an AND of MASK, delete it since it is redundant.  */
6897
6898       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6899         {
6900           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6901                                       mask & INTVAL (XEXP (x, 1)));
6902
6903           /* If X is still an AND, see if it is an AND with a mask that
6904              is just some low-order bits.  If so, and it is MASK, we don't
6905              need it.  */
6906
6907           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6908               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6909                   == mask))
6910             x = XEXP (x, 0);
6911
6912           /* If it remains an AND, try making another AND with the bits
6913              in the mode mask that aren't in MASK turned on.  If the
6914              constant in the AND is wide enough, this might make a
6915              cheaper constant.  */
6916
6917           if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6918               && GET_MODE_MASK (GET_MODE (x)) != mask
6919               && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6920             {
6921               HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6922                                     | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6923               int width = GET_MODE_BITSIZE (GET_MODE (x));
6924               rtx y;
6925
6926               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6927                  number, sign extend it.  */
6928               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6929                   && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6930                 cval |= (HOST_WIDE_INT) -1 << width;
6931
6932               y = simplify_gen_binary (AND, GET_MODE (x),
6933                                        XEXP (x, 0), GEN_INT (cval));
6934               if (rtx_cost (y, SET) < rtx_cost (x, SET))
6935                 x = y;
6936             }
6937
6938           break;
6939         }
6940
6941       goto binop;
6942
6943     case PLUS:
6944       /* In (and (plus FOO C1) M), if M is a mask that just turns off
6945          low-order bits (as in an alignment operation) and FOO is already
6946          aligned to that boundary, mask C1 to that boundary as well.
6947          This may eliminate that PLUS and, later, the AND.  */
6948
6949       {
6950         unsigned int width = GET_MODE_BITSIZE (mode);
6951         unsigned HOST_WIDE_INT smask = mask;
6952
6953         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6954            number, sign extend it.  */
6955
6956         if (width < HOST_BITS_PER_WIDE_INT
6957             && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6958           smask |= (HOST_WIDE_INT) -1 << width;
6959
6960         if (GET_CODE (XEXP (x, 1)) == CONST_INT
6961             && exact_log2 (- smask) >= 0
6962             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6963             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6964           return force_to_mode (plus_constant (XEXP (x, 0),
6965                                                (INTVAL (XEXP (x, 1)) & smask)),
6966                                 mode, smask, next_select);
6967       }
6968
6969       /* ... fall through ...  */
6970
6971     case MULT:
6972       /* For PLUS, MINUS and MULT, we need any bits less significant than the
6973          most significant bit in MASK since carries from those bits will
6974          affect the bits we are interested in.  */
6975       mask = fuller_mask;
6976       goto binop;
6977
6978     case MINUS:
6979       /* If X is (minus C Y) where C's least set bit is larger than any bit
6980          in the mask, then we may replace with (neg Y).  */
6981       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6982           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6983                                         & -INTVAL (XEXP (x, 0))))
6984               > mask))
6985         {
6986           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6987                                   GET_MODE (x));
6988           return force_to_mode (x, mode, mask, next_select);
6989         }
6990
6991       /* Similarly, if C contains every bit in the fuller_mask, then we may
6992          replace with (not Y).  */
6993       if (GET_CODE (XEXP (x, 0)) == CONST_INT
6994           && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6995               == INTVAL (XEXP (x, 0))))
6996         {
6997           x = simplify_gen_unary (NOT, GET_MODE (x),
6998                                   XEXP (x, 1), GET_MODE (x));
6999           return force_to_mode (x, mode, mask, next_select);
7000         }
7001
7002       mask = fuller_mask;
7003       goto binop;
7004
7005     case IOR:
7006     case XOR:
7007       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7008          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7009          operation which may be a bitfield extraction.  Ensure that the
7010          constant we form is not wider than the mode of X.  */
7011
7012       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7013           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7014           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7015           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7016           && GET_CODE (XEXP (x, 1)) == CONST_INT
7017           && ((INTVAL (XEXP (XEXP (x, 0), 1))
7018                + floor_log2 (INTVAL (XEXP (x, 1))))
7019               < GET_MODE_BITSIZE (GET_MODE (x)))
7020           && (INTVAL (XEXP (x, 1))
7021               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7022         {
7023           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7024                           << INTVAL (XEXP (XEXP (x, 0), 1)));
7025           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7026                                       XEXP (XEXP (x, 0), 0), temp);
7027           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7028                                    XEXP (XEXP (x, 0), 1));
7029           return force_to_mode (x, mode, mask, next_select);
7030         }
7031
7032     binop:
7033       /* For most binary operations, just propagate into the operation and
7034          change the mode if we have an operation of that mode.  */
7035
7036       op0 = gen_lowpart_or_truncate (op_mode,
7037                                      force_to_mode (XEXP (x, 0), mode, mask,
7038                                                     next_select));
7039       op1 = gen_lowpart_or_truncate (op_mode,
7040                                      force_to_mode (XEXP (x, 1), mode, mask,
7041                                         next_select));
7042
7043       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7044         x = simplify_gen_binary (code, op_mode, op0, op1);
7045       break;
7046
7047     case ASHIFT:
7048       /* For left shifts, do the same, but just for the first operand.
7049          However, we cannot do anything with shifts where we cannot
7050          guarantee that the counts are smaller than the size of the mode
7051          because such a count will have a different meaning in a
7052          wider mode.  */
7053
7054       if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7055              && INTVAL (XEXP (x, 1)) >= 0
7056              && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7057           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7058                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7059                     < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7060         break;
7061
7062       /* If the shift count is a constant and we can do arithmetic in
7063          the mode of the shift, refine which bits we need.  Otherwise, use the
7064          conservative form of the mask.  */
7065       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7066           && INTVAL (XEXP (x, 1)) >= 0
7067           && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7068           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7069         mask >>= INTVAL (XEXP (x, 1));
7070       else
7071         mask = fuller_mask;
7072
7073       op0 = gen_lowpart_or_truncate (op_mode,
7074                                      force_to_mode (XEXP (x, 0), op_mode,
7075                                                     mask, next_select));
7076
7077       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7078         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7079       break;
7080
7081     case LSHIFTRT:
7082       /* Here we can only do something if the shift count is a constant,
7083          this shift constant is valid for the host, and we can do arithmetic
7084          in OP_MODE.  */
7085
7086       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7087           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7088           && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7089         {
7090           rtx inner = XEXP (x, 0);
7091           unsigned HOST_WIDE_INT inner_mask;
7092
7093           /* Select the mask of the bits we need for the shift operand.  */
7094           inner_mask = mask << INTVAL (XEXP (x, 1));
7095
7096           /* We can only change the mode of the shift if we can do arithmetic
7097              in the mode of the shift and INNER_MASK is no wider than the
7098              width of X's mode.  */
7099           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7100             op_mode = GET_MODE (x);
7101
7102           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7103
7104           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7105             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7106         }
7107
7108       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7109          shift and AND produces only copies of the sign bit (C2 is one less
7110          than a power of two), we can do this with just a shift.  */
7111
7112       if (GET_CODE (x) == LSHIFTRT
7113           && GET_CODE (XEXP (x, 1)) == CONST_INT
7114           /* The shift puts one of the sign bit copies in the least significant
7115              bit.  */
7116           && ((INTVAL (XEXP (x, 1))
7117                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7118               >= GET_MODE_BITSIZE (GET_MODE (x)))
7119           && exact_log2 (mask + 1) >= 0
7120           /* Number of bits left after the shift must be more than the mask
7121              needs.  */
7122           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7123               <= GET_MODE_BITSIZE (GET_MODE (x)))
7124           /* Must be more sign bit copies than the mask needs.  */
7125           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7126               >= exact_log2 (mask + 1)))
7127         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7128                                  GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7129                                           - exact_log2 (mask + 1)));
7130
7131       goto shiftrt;
7132
7133     case ASHIFTRT:
7134       /* If we are just looking for the sign bit, we don't need this shift at
7135          all, even if it has a variable count.  */
7136       if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7137           && (mask == ((unsigned HOST_WIDE_INT) 1
7138                        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7139         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7140
7141       /* If this is a shift by a constant, get a mask that contains those bits
7142          that are not copies of the sign bit.  We then have two cases:  If
7143          MASK only includes those bits, this can be a logical shift, which may
7144          allow simplifications.  If MASK is a single-bit field not within
7145          those bits, we are requesting a copy of the sign bit and hence can
7146          shift the sign bit to the appropriate location.  */
7147
7148       if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7149           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7150         {
7151           int i;
7152
7153           /* If the considered data is wider than HOST_WIDE_INT, we can't
7154              represent a mask for all its bits in a single scalar.
7155              But we only care about the lower bits, so calculate these.  */
7156
7157           if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7158             {
7159               nonzero = ~(HOST_WIDE_INT) 0;
7160
7161               /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7162                  is the number of bits a full-width mask would have set.
7163                  We need only shift if these are fewer than nonzero can
7164                  hold.  If not, we must keep all bits set in nonzero.  */
7165
7166               if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7167                   < HOST_BITS_PER_WIDE_INT)
7168                 nonzero >>= INTVAL (XEXP (x, 1))
7169                             + HOST_BITS_PER_WIDE_INT
7170                             - GET_MODE_BITSIZE (GET_MODE (x)) ;
7171             }
7172           else
7173             {
7174               nonzero = GET_MODE_MASK (GET_MODE (x));
7175               nonzero >>= INTVAL (XEXP (x, 1));
7176             }
7177
7178           if ((mask & ~nonzero) == 0)
7179             {
7180               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7181                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
7182               if (GET_CODE (x) != ASHIFTRT)
7183                 return force_to_mode (x, mode, mask, next_select);
7184             }
7185
7186           else if ((i = exact_log2 (mask)) >= 0)
7187             {
7188               x = simplify_shift_const
7189                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7190                    GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7191
7192               if (GET_CODE (x) != ASHIFTRT)
7193                 return force_to_mode (x, mode, mask, next_select);
7194             }
7195         }
7196
7197       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
7198          even if the shift count isn't a constant.  */
7199       if (mask == 1)
7200         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7201                                  XEXP (x, 0), XEXP (x, 1));
7202
7203     shiftrt:
7204
7205       /* If this is a zero- or sign-extension operation that just affects bits
7206          we don't care about, remove it.  Be sure the call above returned
7207          something that is still a shift.  */
7208
7209       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7210           && GET_CODE (XEXP (x, 1)) == CONST_INT
7211           && INTVAL (XEXP (x, 1)) >= 0
7212           && (INTVAL (XEXP (x, 1))
7213               <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7214           && GET_CODE (XEXP (x, 0)) == ASHIFT
7215           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7216         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7217                               next_select);
7218
7219       break;
7220
7221     case ROTATE:
7222     case ROTATERT:
7223       /* If the shift count is constant and we can do computations
7224          in the mode of X, compute where the bits we care about are.
7225          Otherwise, we can't do anything.  Don't change the mode of
7226          the shift or propagate MODE into the shift, though.  */
7227       if (GET_CODE (XEXP (x, 1)) == CONST_INT
7228           && INTVAL (XEXP (x, 1)) >= 0)
7229         {
7230           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7231                                             GET_MODE (x), GEN_INT (mask),
7232                                             XEXP (x, 1));
7233           if (temp && GET_CODE (temp) == CONST_INT)
7234             SUBST (XEXP (x, 0),
7235                    force_to_mode (XEXP (x, 0), GET_MODE (x),
7236                                   INTVAL (temp), next_select));
7237         }
7238       break;
7239
7240     case NEG:
7241       /* If we just want the low-order bit, the NEG isn't needed since it
7242          won't change the low-order bit.  */
7243       if (mask == 1)
7244         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7245
7246       /* We need any bits less significant than the most significant bit in
7247          MASK since carries from those bits will affect the bits we are
7248          interested in.  */
7249       mask = fuller_mask;
7250       goto unop;
7251
7252     case NOT:
7253       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7254          same as the XOR case above.  Ensure that the constant we form is not
7255          wider than the mode of X.  */
7256
7257       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7258           && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7259           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7260           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7261               < GET_MODE_BITSIZE (GET_MODE (x)))
7262           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7263         {
7264           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7265                                GET_MODE (x));
7266           temp = simplify_gen_binary (XOR, GET_MODE (x),
7267                                       XEXP (XEXP (x, 0), 0), temp);
7268           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7269                                    temp, XEXP (XEXP (x, 0), 1));
7270
7271           return force_to_mode (x, mode, mask, next_select);
7272         }
7273
7274       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7275          use the full mask inside the NOT.  */
7276       mask = fuller_mask;
7277
7278     unop:
7279       op0 = gen_lowpart_or_truncate (op_mode,
7280                                      force_to_mode (XEXP (x, 0), mode, mask,
7281                                                     next_select));
7282       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7283         x = simplify_gen_unary (code, op_mode, op0, op_mode);
7284       break;
7285
7286     case NE:
7287       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7288          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7289          which is equal to STORE_FLAG_VALUE.  */
7290       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7291           && GET_MODE (XEXP (x, 0)) == mode
7292           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7293           && (nonzero_bits (XEXP (x, 0), mode)
7294               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7295         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7296
7297       break;
7298
7299     case IF_THEN_ELSE:
7300       /* We have no way of knowing if the IF_THEN_ELSE can itself be
7301          written in a narrower mode.  We play it safe and do not do so.  */
7302
7303       SUBST (XEXP (x, 1),
7304              gen_lowpart_or_truncate (GET_MODE (x),
7305                                       force_to_mode (XEXP (x, 1), mode,
7306                                                      mask, next_select)));
7307       SUBST (XEXP (x, 2),
7308              gen_lowpart_or_truncate (GET_MODE (x),
7309                                       force_to_mode (XEXP (x, 2), mode,
7310                                                      mask, next_select)));
7311       break;
7312
7313     default:
7314       break;
7315     }
7316
7317   /* Ensure we return a value of the proper mode.  */
7318   return gen_lowpart_or_truncate (mode, x);
7319 }
7320 \f
7321 /* Return nonzero if X is an expression that has one of two values depending on
7322    whether some other value is zero or nonzero.  In that case, we return the
7323    value that is being tested, *PTRUE is set to the value if the rtx being
7324    returned has a nonzero value, and *PFALSE is set to the other alternative.
7325
7326    If we return zero, we set *PTRUE and *PFALSE to X.  */
7327
7328 static rtx
7329 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7330 {
7331   enum machine_mode mode = GET_MODE (x);
7332   enum rtx_code code = GET_CODE (x);
7333   rtx cond0, cond1, true0, true1, false0, false1;
7334   unsigned HOST_WIDE_INT nz;
7335
7336   /* If we are comparing a value against zero, we are done.  */
7337   if ((code == NE || code == EQ)
7338       && XEXP (x, 1) == const0_rtx)
7339     {
7340       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7341       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7342       return XEXP (x, 0);
7343     }
7344
7345   /* If this is a unary operation whose operand has one of two values, apply
7346      our opcode to compute those values.  */
7347   else if (UNARY_P (x)
7348            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7349     {
7350       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7351       *pfalse = simplify_gen_unary (code, mode, false0,
7352                                     GET_MODE (XEXP (x, 0)));
7353       return cond0;
7354     }
7355
7356   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7357      make can't possibly match and would suppress other optimizations.  */
7358   else if (code == COMPARE)
7359     ;
7360
7361   /* If this is a binary operation, see if either side has only one of two
7362      values.  If either one does or if both do and they are conditional on
7363      the same value, compute the new true and false values.  */
7364   else if (BINARY_P (x))
7365     {
7366       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7367       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7368
7369       if ((cond0 != 0 || cond1 != 0)
7370           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7371         {
7372           /* If if_then_else_cond returned zero, then true/false are the
7373              same rtl.  We must copy one of them to prevent invalid rtl
7374              sharing.  */
7375           if (cond0 == 0)
7376             true0 = copy_rtx (true0);
7377           else if (cond1 == 0)
7378             true1 = copy_rtx (true1);
7379
7380           if (COMPARISON_P (x))
7381             {
7382               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7383                                                 true0, true1);
7384               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7385                                                  false0, false1);
7386              }
7387           else
7388             {
7389               *ptrue = simplify_gen_binary (code, mode, true0, true1);
7390               *pfalse = simplify_gen_binary (code, mode, false0, false1);
7391             }
7392
7393           return cond0 ? cond0 : cond1;
7394         }
7395
7396       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7397          operands is zero when the other is nonzero, and vice-versa,
7398          and STORE_FLAG_VALUE is 1 or -1.  */
7399
7400       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7401           && (code == PLUS || code == IOR || code == XOR || code == MINUS
7402               || code == UMAX)
7403           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7404         {
7405           rtx op0 = XEXP (XEXP (x, 0), 1);
7406           rtx op1 = XEXP (XEXP (x, 1), 1);
7407
7408           cond0 = XEXP (XEXP (x, 0), 0);
7409           cond1 = XEXP (XEXP (x, 1), 0);
7410
7411           if (COMPARISON_P (cond0)
7412               && COMPARISON_P (cond1)
7413               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7414                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7415                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7416                   || ((swap_condition (GET_CODE (cond0))
7417                        == reversed_comparison_code (cond1, NULL))
7418                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7419                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7420               && ! side_effects_p (x))
7421             {
7422               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7423               *pfalse = simplify_gen_binary (MULT, mode,
7424                                              (code == MINUS
7425                                               ? simplify_gen_unary (NEG, mode,
7426                                                                     op1, mode)
7427                                               : op1),
7428                                               const_true_rtx);
7429               return cond0;
7430             }
7431         }
7432
7433       /* Similarly for MULT, AND and UMIN, except that for these the result
7434          is always zero.  */
7435       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7436           && (code == MULT || code == AND || code == UMIN)
7437           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7438         {
7439           cond0 = XEXP (XEXP (x, 0), 0);
7440           cond1 = XEXP (XEXP (x, 1), 0);
7441
7442           if (COMPARISON_P (cond0)
7443               && COMPARISON_P (cond1)
7444               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7445                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7446                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7447                   || ((swap_condition (GET_CODE (cond0))
7448                        == reversed_comparison_code (cond1, NULL))
7449                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7450                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7451               && ! side_effects_p (x))
7452             {
7453               *ptrue = *pfalse = const0_rtx;
7454               return cond0;
7455             }
7456         }
7457     }
7458
7459   else if (code == IF_THEN_ELSE)
7460     {
7461       /* If we have IF_THEN_ELSE already, extract the condition and
7462          canonicalize it if it is NE or EQ.  */
7463       cond0 = XEXP (x, 0);
7464       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7465       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7466         return XEXP (cond0, 0);
7467       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7468         {
7469           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7470           return XEXP (cond0, 0);
7471         }
7472       else
7473         return cond0;
7474     }
7475
7476   /* If X is a SUBREG, we can narrow both the true and false values
7477      if the inner expression, if there is a condition.  */
7478   else if (code == SUBREG
7479            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7480                                                &true0, &false0)))
7481     {
7482       true0 = simplify_gen_subreg (mode, true0,
7483                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7484       false0 = simplify_gen_subreg (mode, false0,
7485                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7486       if (true0 && false0)
7487         {
7488           *ptrue = true0;
7489           *pfalse = false0;
7490           return cond0;
7491         }
7492     }
7493
7494   /* If X is a constant, this isn't special and will cause confusions
7495      if we treat it as such.  Likewise if it is equivalent to a constant.  */
7496   else if (CONSTANT_P (x)
7497            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7498     ;
7499
7500   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7501      will be least confusing to the rest of the compiler.  */
7502   else if (mode == BImode)
7503     {
7504       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7505       return x;
7506     }
7507
7508   /* If X is known to be either 0 or -1, those are the true and
7509      false values when testing X.  */
7510   else if (x == constm1_rtx || x == const0_rtx
7511            || (mode != VOIDmode
7512                && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7513     {
7514       *ptrue = constm1_rtx, *pfalse = const0_rtx;
7515       return x;
7516     }
7517
7518   /* Likewise for 0 or a single bit.  */
7519   else if (SCALAR_INT_MODE_P (mode)
7520            && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7521            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7522     {
7523       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7524       return x;
7525     }
7526
7527   /* Otherwise fail; show no condition with true and false values the same.  */
7528   *ptrue = *pfalse = x;
7529   return 0;
7530 }
7531 \f
7532 /* Return the value of expression X given the fact that condition COND
7533    is known to be true when applied to REG as its first operand and VAL
7534    as its second.  X is known to not be shared and so can be modified in
7535    place.
7536
7537    We only handle the simplest cases, and specifically those cases that
7538    arise with IF_THEN_ELSE expressions.  */
7539
7540 static rtx
7541 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7542 {
7543   enum rtx_code code = GET_CODE (x);
7544   rtx temp;
7545   const char *fmt;
7546   int i, j;
7547
7548   if (side_effects_p (x))
7549     return x;
7550
7551   /* If either operand of the condition is a floating point value,
7552      then we have to avoid collapsing an EQ comparison.  */
7553   if (cond == EQ
7554       && rtx_equal_p (x, reg)
7555       && ! FLOAT_MODE_P (GET_MODE (x))
7556       && ! FLOAT_MODE_P (GET_MODE (val)))
7557     return val;
7558
7559   if (cond == UNEQ && rtx_equal_p (x, reg))
7560     return val;
7561
7562   /* If X is (abs REG) and we know something about REG's relationship
7563      with zero, we may be able to simplify this.  */
7564
7565   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7566     switch (cond)
7567       {
7568       case GE:  case GT:  case EQ:
7569         return XEXP (x, 0);
7570       case LT:  case LE:
7571         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7572                                    XEXP (x, 0),
7573                                    GET_MODE (XEXP (x, 0)));
7574       default:
7575         break;
7576       }
7577
7578   /* The only other cases we handle are MIN, MAX, and comparisons if the
7579      operands are the same as REG and VAL.  */
7580
7581   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7582     {
7583       if (rtx_equal_p (XEXP (x, 0), val))
7584         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7585
7586       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7587         {
7588           if (COMPARISON_P (x))
7589             {
7590               if (comparison_dominates_p (cond, code))
7591                 return const_true_rtx;
7592
7593               code = reversed_comparison_code (x, NULL);
7594               if (code != UNKNOWN
7595                   && comparison_dominates_p (cond, code))
7596                 return const0_rtx;
7597               else
7598                 return x;
7599             }
7600           else if (code == SMAX || code == SMIN
7601                    || code == UMIN || code == UMAX)
7602             {
7603               int unsignedp = (code == UMIN || code == UMAX);
7604
7605               /* Do not reverse the condition when it is NE or EQ.
7606                  This is because we cannot conclude anything about
7607                  the value of 'SMAX (x, y)' when x is not equal to y,
7608                  but we can when x equals y.  */
7609               if ((code == SMAX || code == UMAX)
7610                   && ! (cond == EQ || cond == NE))
7611                 cond = reverse_condition (cond);
7612
7613               switch (cond)
7614                 {
7615                 case GE:   case GT:
7616                   return unsignedp ? x : XEXP (x, 1);
7617                 case LE:   case LT:
7618                   return unsignedp ? x : XEXP (x, 0);
7619                 case GEU:  case GTU:
7620                   return unsignedp ? XEXP (x, 1) : x;
7621                 case LEU:  case LTU:
7622                   return unsignedp ? XEXP (x, 0) : x;
7623                 default:
7624                   break;
7625                 }
7626             }
7627         }
7628     }
7629   else if (code == SUBREG)
7630     {
7631       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7632       rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7633
7634       if (SUBREG_REG (x) != r)
7635         {
7636           /* We must simplify subreg here, before we lose track of the
7637              original inner_mode.  */
7638           new = simplify_subreg (GET_MODE (x), r,
7639                                  inner_mode, SUBREG_BYTE (x));
7640           if (new)
7641             return new;
7642           else
7643             SUBST (SUBREG_REG (x), r);
7644         }
7645
7646       return x;
7647     }
7648   /* We don't have to handle SIGN_EXTEND here, because even in the
7649      case of replacing something with a modeless CONST_INT, a
7650      CONST_INT is already (supposed to be) a valid sign extension for
7651      its narrower mode, which implies it's already properly
7652      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
7653      story is different.  */
7654   else if (code == ZERO_EXTEND)
7655     {
7656       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7657       rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7658
7659       if (XEXP (x, 0) != r)
7660         {
7661           /* We must simplify the zero_extend here, before we lose
7662              track of the original inner_mode.  */
7663           new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7664                                           r, inner_mode);
7665           if (new)
7666             return new;
7667           else
7668             SUBST (XEXP (x, 0), r);
7669         }
7670
7671       return x;
7672     }
7673
7674   fmt = GET_RTX_FORMAT (code);
7675   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7676     {
7677       if (fmt[i] == 'e')
7678         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7679       else if (fmt[i] == 'E')
7680         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7681           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7682                                                 cond, reg, val));
7683     }
7684
7685   return x;
7686 }
7687 \f
7688 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7689    assignment as a field assignment.  */
7690
7691 static int
7692 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7693 {
7694   if (x == y || rtx_equal_p (x, y))
7695     return 1;
7696
7697   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7698     return 0;
7699
7700   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7701      Note that all SUBREGs of MEM are paradoxical; otherwise they
7702      would have been rewritten.  */
7703   if (MEM_P (x) && GET_CODE (y) == SUBREG
7704       && MEM_P (SUBREG_REG (y))
7705       && rtx_equal_p (SUBREG_REG (y),
7706                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7707     return 1;
7708
7709   if (MEM_P (y) && GET_CODE (x) == SUBREG
7710       && MEM_P (SUBREG_REG (x))
7711       && rtx_equal_p (SUBREG_REG (x),
7712                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7713     return 1;
7714
7715   /* We used to see if get_last_value of X and Y were the same but that's
7716      not correct.  In one direction, we'll cause the assignment to have
7717      the wrong destination and in the case, we'll import a register into this
7718      insn that might have already have been dead.   So fail if none of the
7719      above cases are true.  */
7720   return 0;
7721 }
7722 \f
7723 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7724    Return that assignment if so.
7725
7726    We only handle the most common cases.  */
7727
7728 static rtx
7729 make_field_assignment (rtx x)
7730 {
7731   rtx dest = SET_DEST (x);
7732   rtx src = SET_SRC (x);
7733   rtx assign;
7734   rtx rhs, lhs;
7735   HOST_WIDE_INT c1;
7736   HOST_WIDE_INT pos;
7737   unsigned HOST_WIDE_INT len;
7738   rtx other;
7739   enum machine_mode mode;
7740
7741   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7742      a clear of a one-bit field.  We will have changed it to
7743      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
7744      for a SUBREG.  */
7745
7746   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7747       && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7748       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7749       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7750     {
7751       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7752                                 1, 1, 1, 0);
7753       if (assign != 0)
7754         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7755       return x;
7756     }
7757
7758   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7759       && subreg_lowpart_p (XEXP (src, 0))
7760       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7761           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7762       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7763       && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7764       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7765       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7766     {
7767       assign = make_extraction (VOIDmode, dest, 0,
7768                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7769                                 1, 1, 1, 0);
7770       if (assign != 0)
7771         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7772       return x;
7773     }
7774
7775   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7776      one-bit field.  */
7777   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7778       && XEXP (XEXP (src, 0), 0) == const1_rtx
7779       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7780     {
7781       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7782                                 1, 1, 1, 0);
7783       if (assign != 0)
7784         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7785       return x;
7786     }
7787
7788   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7789      SRC is an AND with all bits of that field set, then we can discard
7790      the AND.  */
7791   if (GET_CODE (dest) == ZERO_EXTRACT
7792       && GET_CODE (XEXP (dest, 1)) == CONST_INT
7793       && GET_CODE (src) == AND
7794       && GET_CODE (XEXP (src, 1)) == CONST_INT)
7795     {
7796       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7797       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7798       unsigned HOST_WIDE_INT ze_mask;
7799
7800       if (width >= HOST_BITS_PER_WIDE_INT)
7801         ze_mask = -1;
7802       else
7803         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7804
7805       /* Complete overlap.  We can remove the source AND.  */
7806       if ((and_mask & ze_mask) == ze_mask)
7807         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7808
7809       /* Partial overlap.  We can reduce the source AND.  */
7810       if ((and_mask & ze_mask) != and_mask)
7811         {
7812           mode = GET_MODE (src);
7813           src = gen_rtx_AND (mode, XEXP (src, 0),
7814                              gen_int_mode (and_mask & ze_mask, mode));
7815           return gen_rtx_SET (VOIDmode, dest, src);
7816         }
7817     }
7818
7819   /* The other case we handle is assignments into a constant-position
7820      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
7821      a mask that has all one bits except for a group of zero bits and
7822      OTHER is known to have zeros where C1 has ones, this is such an
7823      assignment.  Compute the position and length from C1.  Shift OTHER
7824      to the appropriate position, force it to the required mode, and
7825      make the extraction.  Check for the AND in both operands.  */
7826
7827   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7828     return x;
7829
7830   rhs = expand_compound_operation (XEXP (src, 0));
7831   lhs = expand_compound_operation (XEXP (src, 1));
7832
7833   if (GET_CODE (rhs) == AND
7834       && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7835       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7836     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7837   else if (GET_CODE (lhs) == AND
7838            && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7839            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7840     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7841   else
7842     return x;
7843
7844   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7845   if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7846       || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7847       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7848     return x;
7849
7850   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7851   if (assign == 0)
7852     return x;
7853
7854   /* The mode to use for the source is the mode of the assignment, or of
7855      what is inside a possible STRICT_LOW_PART.  */
7856   mode = (GET_CODE (assign) == STRICT_LOW_PART
7857           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7858
7859   /* Shift OTHER right POS places and make it the source, restricting it
7860      to the proper length and mode.  */
7861
7862   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7863                                                      GET_MODE (src),
7864                                                      other, pos),
7865                                dest);
7866   src = force_to_mode (src, mode,
7867                        GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7868                        ? ~(unsigned HOST_WIDE_INT) 0
7869                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7870                        0);
7871
7872   /* If SRC is masked by an AND that does not make a difference in
7873      the value being stored, strip it.  */
7874   if (GET_CODE (assign) == ZERO_EXTRACT
7875       && GET_CODE (XEXP (assign, 1)) == CONST_INT
7876       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7877       && GET_CODE (src) == AND
7878       && GET_CODE (XEXP (src, 1)) == CONST_INT
7879       && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7880           == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7881     src = XEXP (src, 0);
7882
7883   return gen_rtx_SET (VOIDmode, assign, src);
7884 }
7885 \f
7886 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7887    if so.  */
7888
7889 static rtx
7890 apply_distributive_law (rtx x)
7891 {
7892   enum rtx_code code = GET_CODE (x);
7893   enum rtx_code inner_code;
7894   rtx lhs, rhs, other;
7895   rtx tem;
7896
7897   /* Distributivity is not true for floating point as it can change the
7898      value.  So we don't do it unless -funsafe-math-optimizations.  */
7899   if (FLOAT_MODE_P (GET_MODE (x))
7900       && ! flag_unsafe_math_optimizations)
7901     return x;
7902
7903   /* The outer operation can only be one of the following:  */
7904   if (code != IOR && code != AND && code != XOR
7905       && code != PLUS && code != MINUS)
7906     return x;
7907
7908   lhs = XEXP (x, 0);
7909   rhs = XEXP (x, 1);
7910
7911   /* If either operand is a primitive we can't do anything, so get out
7912      fast.  */
7913   if (OBJECT_P (lhs) || OBJECT_P (rhs))
7914     return x;
7915
7916   lhs = expand_compound_operation (lhs);
7917   rhs = expand_compound_operation (rhs);
7918   inner_code = GET_CODE (lhs);
7919   if (inner_code != GET_CODE (rhs))
7920     return x;
7921
7922   /* See if the inner and outer operations distribute.  */
7923   switch (inner_code)
7924     {
7925     case LSHIFTRT:
7926     case ASHIFTRT:
7927     case AND:
7928     case IOR:
7929       /* These all distribute except over PLUS.  */
7930       if (code == PLUS || code == MINUS)
7931         return x;
7932       break;
7933
7934     case MULT:
7935       if (code != PLUS && code != MINUS)
7936         return x;
7937       break;
7938
7939     case ASHIFT:
7940       /* This is also a multiply, so it distributes over everything.  */
7941       break;
7942
7943     case SUBREG:
7944       /* Non-paradoxical SUBREGs distributes over all operations,
7945          provided the inner modes and byte offsets are the same, this
7946          is an extraction of a low-order part, we don't convert an fp
7947          operation to int or vice versa, this is not a vector mode,
7948          and we would not be converting a single-word operation into a
7949          multi-word operation.  The latter test is not required, but
7950          it prevents generating unneeded multi-word operations.  Some
7951          of the previous tests are redundant given the latter test,
7952          but are retained because they are required for correctness.
7953
7954          We produce the result slightly differently in this case.  */
7955
7956       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7957           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7958           || ! subreg_lowpart_p (lhs)
7959           || (GET_MODE_CLASS (GET_MODE (lhs))
7960               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7961           || (GET_MODE_SIZE (GET_MODE (lhs))
7962               > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7963           || VECTOR_MODE_P (GET_MODE (lhs))
7964           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7965           /* Result might need to be truncated.  Don't change mode if
7966              explicit truncation is needed.  */
7967           || !TRULY_NOOP_TRUNCATION
7968                (GET_MODE_BITSIZE (GET_MODE (x)),
7969                 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7970         return x;
7971
7972       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7973                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
7974       return gen_lowpart (GET_MODE (x), tem);
7975
7976     default:
7977       return x;
7978     }
7979
7980   /* Set LHS and RHS to the inner operands (A and B in the example
7981      above) and set OTHER to the common operand (C in the example).
7982      There is only one way to do this unless the inner operation is
7983      commutative.  */
7984   if (COMMUTATIVE_ARITH_P (lhs)
7985       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7986     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7987   else if (COMMUTATIVE_ARITH_P (lhs)
7988            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7989     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7990   else if (COMMUTATIVE_ARITH_P (lhs)
7991            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7992     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7993   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7994     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7995   else
7996     return x;
7997
7998   /* Form the new inner operation, seeing if it simplifies first.  */
7999   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8000
8001   /* There is one exception to the general way of distributing:
8002      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
8003   if (code == XOR && inner_code == IOR)
8004     {
8005       inner_code = AND;
8006       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8007     }
8008
8009   /* We may be able to continuing distributing the result, so call
8010      ourselves recursively on the inner operation before forming the
8011      outer operation, which we return.  */
8012   return simplify_gen_binary (inner_code, GET_MODE (x),
8013                               apply_distributive_law (tem), other);
8014 }
8015
8016 /* See if X is of the form (* (+ A B) C), and if so convert to
8017    (+ (* A C) (* B C)) and try to simplify.
8018
8019    Most of the time, this results in no change.  However, if some of
8020    the operands are the same or inverses of each other, simplifications
8021    will result.
8022
8023    For example, (and (ior A B) (not B)) can occur as the result of
8024    expanding a bit field assignment.  When we apply the distributive
8025    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8026    which then simplifies to (and (A (not B))).
8027
8028    Note that no checks happen on the validity of applying the inverse
8029    distributive law.  This is pointless since we can do it in the
8030    few places where this routine is called.
8031
8032    N is the index of the term that is decomposed (the arithmetic operation,
8033    i.e. (+ A B) in the first example above).  !N is the index of the term that
8034    is distributed, i.e. of C in the first example above.  */
8035 static rtx
8036 distribute_and_simplify_rtx (rtx x, int n)
8037 {
8038   enum machine_mode mode;
8039   enum rtx_code outer_code, inner_code;
8040   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8041
8042   decomposed = XEXP (x, n);
8043   if (!ARITHMETIC_P (decomposed))
8044     return NULL_RTX;
8045
8046   mode = GET_MODE (x);
8047   outer_code = GET_CODE (x);
8048   distributed = XEXP (x, !n);
8049
8050   inner_code = GET_CODE (decomposed);
8051   inner_op0 = XEXP (decomposed, 0);
8052   inner_op1 = XEXP (decomposed, 1);
8053
8054   /* Special case (and (xor B C) (not A)), which is equivalent to
8055      (xor (ior A B) (ior A C))  */
8056   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8057     {
8058       distributed = XEXP (distributed, 0);
8059       outer_code = IOR;
8060     }
8061
8062   if (n == 0)
8063     {
8064       /* Distribute the second term.  */
8065       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8066       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8067     }
8068   else
8069     {
8070       /* Distribute the first term.  */
8071       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8072       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8073     }
8074
8075   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8076                                                      new_op0, new_op1));
8077   if (GET_CODE (tmp) != outer_code
8078       && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8079     return tmp;
8080
8081   return NULL_RTX;
8082 }
8083 \f
8084 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8085    in MODE.  Return an equivalent form, if different from (and VAROP
8086    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
8087
8088 static rtx
8089 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8090                           unsigned HOST_WIDE_INT constop)
8091 {
8092   unsigned HOST_WIDE_INT nonzero;
8093   unsigned HOST_WIDE_INT orig_constop;
8094   rtx orig_varop;
8095   int i;
8096
8097   orig_varop = varop;
8098   orig_constop = constop;
8099   if (GET_CODE (varop) == CLOBBER)
8100     return NULL_RTX;
8101
8102   /* Simplify VAROP knowing that we will be only looking at some of the
8103      bits in it.
8104
8105      Note by passing in CONSTOP, we guarantee that the bits not set in
8106      CONSTOP are not significant and will never be examined.  We must
8107      ensure that is the case by explicitly masking out those bits
8108      before returning.  */
8109   varop = force_to_mode (varop, mode, constop, 0);
8110
8111   /* If VAROP is a CLOBBER, we will fail so return it.  */
8112   if (GET_CODE (varop) == CLOBBER)
8113     return varop;
8114
8115   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8116      to VAROP and return the new constant.  */
8117   if (GET_CODE (varop) == CONST_INT)
8118     return gen_int_mode (INTVAL (varop) & constop, mode);
8119
8120   /* See what bits may be nonzero in VAROP.  Unlike the general case of
8121      a call to nonzero_bits, here we don't care about bits outside
8122      MODE.  */
8123
8124   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8125
8126   /* Turn off all bits in the constant that are known to already be zero.
8127      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8128      which is tested below.  */
8129
8130   constop &= nonzero;
8131
8132   /* If we don't have any bits left, return zero.  */
8133   if (constop == 0)
8134     return const0_rtx;
8135
8136   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8137      a power of two, we can replace this with an ASHIFT.  */
8138   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8139       && (i = exact_log2 (constop)) >= 0)
8140     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8141
8142   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8143      or XOR, then try to apply the distributive law.  This may eliminate
8144      operations if either branch can be simplified because of the AND.
8145      It may also make some cases more complex, but those cases probably
8146      won't match a pattern either with or without this.  */
8147
8148   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8149     return
8150       gen_lowpart
8151         (mode,
8152          apply_distributive_law
8153          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8154                                simplify_and_const_int (NULL_RTX,
8155                                                        GET_MODE (varop),
8156                                                        XEXP (varop, 0),
8157                                                        constop),
8158                                simplify_and_const_int (NULL_RTX,
8159                                                        GET_MODE (varop),
8160                                                        XEXP (varop, 1),
8161                                                        constop))));
8162
8163   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8164      the AND and see if one of the operands simplifies to zero.  If so, we
8165      may eliminate it.  */
8166
8167   if (GET_CODE (varop) == PLUS
8168       && exact_log2 (constop + 1) >= 0)
8169     {
8170       rtx o0, o1;
8171
8172       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8173       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8174       if (o0 == const0_rtx)
8175         return o1;
8176       if (o1 == const0_rtx)
8177         return o0;
8178     }
8179
8180   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
8181   varop = gen_lowpart (mode, varop);
8182   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8183     return NULL_RTX;
8184
8185   /* If we are only masking insignificant bits, return VAROP.  */
8186   if (constop == nonzero)
8187     return varop;
8188
8189   if (varop == orig_varop && constop == orig_constop)
8190     return NULL_RTX;
8191
8192   /* Otherwise, return an AND.  */
8193   constop = trunc_int_for_mode (constop, mode);
8194   return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8195 }
8196
8197
8198 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8199    in MODE.
8200
8201    Return an equivalent form, if different from X.  Otherwise, return X.  If
8202    X is zero, we are to always construct the equivalent form.  */
8203
8204 static rtx
8205 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8206                         unsigned HOST_WIDE_INT constop)
8207 {
8208   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8209   if (tem)
8210     return tem;
8211
8212   if (!x)
8213     x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8214   if (GET_MODE (x) != mode)
8215     x = gen_lowpart (mode, x);
8216   return x;
8217 }
8218 \f
8219 /* Given a REG, X, compute which bits in X can be nonzero.
8220    We don't care about bits outside of those defined in MODE.
8221
8222    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8223    a shift, AND, or zero_extract, we can do better.  */
8224
8225 static rtx
8226 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8227                               rtx known_x ATTRIBUTE_UNUSED,
8228                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
8229                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8230                               unsigned HOST_WIDE_INT *nonzero)
8231 {
8232   rtx tem;
8233
8234   /* If X is a register whose nonzero bits value is current, use it.
8235      Otherwise, if X is a register whose value we can find, use that
8236      value.  Otherwise, use the previously-computed global nonzero bits
8237      for this register.  */
8238
8239   if (reg_stat[REGNO (x)].last_set_value != 0
8240       && (reg_stat[REGNO (x)].last_set_mode == mode
8241           || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8242               && GET_MODE_CLASS (mode) == MODE_INT))
8243       && (reg_stat[REGNO (x)].last_set_label == label_tick
8244           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8245               && REG_N_SETS (REGNO (x)) == 1
8246               && ! REGNO_REG_SET_P
8247                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8248                   REGNO (x))))
8249       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8250     {
8251       *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8252       return NULL;
8253     }
8254
8255   tem = get_last_value (x);
8256
8257   if (tem)
8258     {
8259 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8260       /* If X is narrower than MODE and TEM is a non-negative
8261          constant that would appear negative in the mode of X,
8262          sign-extend it for use in reg_nonzero_bits because some
8263          machines (maybe most) will actually do the sign-extension
8264          and this is the conservative approach.
8265
8266          ??? For 2.5, try to tighten up the MD files in this regard
8267          instead of this kludge.  */
8268
8269       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8270           && GET_CODE (tem) == CONST_INT
8271           && INTVAL (tem) > 0
8272           && 0 != (INTVAL (tem)
8273                    & ((HOST_WIDE_INT) 1
8274                       << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8275         tem = GEN_INT (INTVAL (tem)
8276                        | ((HOST_WIDE_INT) (-1)
8277                           << GET_MODE_BITSIZE (GET_MODE (x))));
8278 #endif
8279       return tem;
8280     }
8281   else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8282     {
8283       unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8284
8285       if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8286         /* We don't know anything about the upper bits.  */
8287         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8288       *nonzero &= mask;
8289     }
8290
8291   return NULL;
8292 }
8293
8294 /* Return the number of bits at the high-order end of X that are known to
8295    be equal to the sign bit.  X will be used in mode MODE; if MODE is
8296    VOIDmode, X will be used in its own mode.  The returned value  will always
8297    be between 1 and the number of bits in MODE.  */
8298
8299 static rtx
8300 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8301                                      rtx known_x ATTRIBUTE_UNUSED,
8302                                      enum machine_mode known_mode
8303                                      ATTRIBUTE_UNUSED,
8304                                      unsigned int known_ret ATTRIBUTE_UNUSED,
8305                                      unsigned int *result)
8306 {
8307   rtx tem;
8308
8309   if (reg_stat[REGNO (x)].last_set_value != 0
8310       && reg_stat[REGNO (x)].last_set_mode == mode
8311       && (reg_stat[REGNO (x)].last_set_label == label_tick
8312           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8313               && REG_N_SETS (REGNO (x)) == 1
8314               && ! REGNO_REG_SET_P
8315                  (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8316                   REGNO (x))))
8317       && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8318     {
8319       *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8320       return NULL;
8321     }
8322
8323   tem = get_last_value (x);
8324   if (tem != 0)
8325     return tem;
8326
8327   if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8328       && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8329     *result = reg_stat[REGNO (x)].sign_bit_copies;
8330
8331   return NULL;
8332 }
8333 \f
8334 /* Return the number of "extended" bits there are in X, when interpreted
8335    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
8336    unsigned quantities, this is the number of high-order zero bits.
8337    For signed quantities, this is the number of copies of the sign bit
8338    minus 1.  In both case, this function returns the number of "spare"
8339    bits.  For example, if two quantities for which this function returns
8340    at least 1 are added, the addition is known not to overflow.
8341
8342    This function will always return 0 unless called during combine, which
8343    implies that it must be called from a define_split.  */
8344
8345 unsigned int
8346 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8347 {
8348   if (nonzero_sign_valid == 0)
8349     return 0;
8350
8351   return (unsignedp
8352           ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8353              ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8354                                - floor_log2 (nonzero_bits (x, mode)))
8355              : 0)
8356           : num_sign_bit_copies (x, mode) - 1);
8357 }
8358 \f
8359 /* This function is called from `simplify_shift_const' to merge two
8360    outer operations.  Specifically, we have already found that we need
8361    to perform operation *POP0 with constant *PCONST0 at the outermost
8362    position.  We would now like to also perform OP1 with constant CONST1
8363    (with *POP0 being done last).
8364
8365    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8366    the resulting operation.  *PCOMP_P is set to 1 if we would need to
8367    complement the innermost operand, otherwise it is unchanged.
8368
8369    MODE is the mode in which the operation will be done.  No bits outside
8370    the width of this mode matter.  It is assumed that the width of this mode
8371    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8372
8373    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
8374    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
8375    result is simply *PCONST0.
8376
8377    If the resulting operation cannot be expressed as one operation, we
8378    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
8379
8380 static int
8381 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8382 {
8383   enum rtx_code op0 = *pop0;
8384   HOST_WIDE_INT const0 = *pconst0;
8385
8386   const0 &= GET_MODE_MASK (mode);
8387   const1 &= GET_MODE_MASK (mode);
8388
8389   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
8390   if (op0 == AND)
8391     const1 &= const0;
8392
8393   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
8394      if OP0 is SET.  */
8395
8396   if (op1 == UNKNOWN || op0 == SET)
8397     return 1;
8398
8399   else if (op0 == UNKNOWN)
8400     op0 = op1, const0 = const1;
8401
8402   else if (op0 == op1)
8403     {
8404       switch (op0)
8405         {
8406         case AND:
8407           const0 &= const1;
8408           break;
8409         case IOR:
8410           const0 |= const1;
8411           break;
8412         case XOR:
8413           const0 ^= const1;
8414           break;
8415         case PLUS:
8416           const0 += const1;
8417           break;
8418         case NEG:
8419           op0 = UNKNOWN;
8420           break;
8421         default:
8422           break;
8423         }
8424     }
8425
8426   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
8427   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8428     return 0;
8429
8430   /* If the two constants aren't the same, we can't do anything.  The
8431      remaining six cases can all be done.  */
8432   else if (const0 != const1)
8433     return 0;
8434
8435   else
8436     switch (op0)
8437       {
8438       case IOR:
8439         if (op1 == AND)
8440           /* (a & b) | b == b */
8441           op0 = SET;
8442         else /* op1 == XOR */
8443           /* (a ^ b) | b == a | b */
8444           {;}
8445         break;
8446
8447       case XOR:
8448         if (op1 == AND)
8449           /* (a & b) ^ b == (~a) & b */
8450           op0 = AND, *pcomp_p = 1;
8451         else /* op1 == IOR */
8452           /* (a | b) ^ b == a & ~b */
8453           op0 = AND, const0 = ~const0;
8454         break;
8455
8456       case AND:
8457         if (op1 == IOR)
8458           /* (a | b) & b == b */
8459         op0 = SET;
8460         else /* op1 == XOR */
8461           /* (a ^ b) & b) == (~a) & b */
8462           *pcomp_p = 1;
8463         break;
8464       default:
8465         break;
8466       }
8467
8468   /* Check for NO-OP cases.  */
8469   const0 &= GET_MODE_MASK (mode);
8470   if (const0 == 0
8471       && (op0 == IOR || op0 == XOR || op0 == PLUS))
8472     op0 = UNKNOWN;
8473   else if (const0 == 0 && op0 == AND)
8474     op0 = SET;
8475   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8476            && op0 == AND)
8477     op0 = UNKNOWN;
8478
8479   /* ??? Slightly redundant with the above mask, but not entirely.
8480      Moving this above means we'd have to sign-extend the mode mask
8481      for the final test.  */
8482   const0 = trunc_int_for_mode (const0, mode);
8483
8484   *pop0 = op0;
8485   *pconst0 = const0;
8486
8487   return 1;
8488 }
8489 \f
8490 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
8491    The result of the shift is RESULT_MODE.  Return NULL_RTX if we cannot
8492    simplify it.  Otherwise, return a simplified value.
8493
8494    The shift is normally computed in the widest mode we find in VAROP, as
8495    long as it isn't a different number of words than RESULT_MODE.  Exceptions
8496    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
8497
8498 static rtx
8499 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8500                         rtx varop, int orig_count)
8501 {
8502   enum rtx_code orig_code = code;
8503   rtx orig_varop = varop;
8504   int count;
8505   enum machine_mode mode = result_mode;
8506   enum machine_mode shift_mode, tmode;
8507   unsigned int mode_words
8508     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8509   /* We form (outer_op (code varop count) (outer_const)).  */
8510   enum rtx_code outer_op = UNKNOWN;
8511   HOST_WIDE_INT outer_const = 0;
8512   int complement_p = 0;
8513   rtx new, x;
8514
8515   /* Make sure and truncate the "natural" shift on the way in.  We don't
8516      want to do this inside the loop as it makes it more difficult to
8517      combine shifts.  */
8518   if (SHIFT_COUNT_TRUNCATED)
8519     orig_count &= GET_MODE_BITSIZE (mode) - 1;
8520
8521   /* If we were given an invalid count, don't do anything except exactly
8522      what was requested.  */
8523
8524   if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8525     return NULL_RTX;
8526
8527   count = orig_count;
8528
8529   /* Unless one of the branches of the `if' in this loop does a `continue',
8530      we will `break' the loop after the `if'.  */
8531
8532   while (count != 0)
8533     {
8534       /* If we have an operand of (clobber (const_int 0)), fail.  */
8535       if (GET_CODE (varop) == CLOBBER)
8536         return NULL_RTX;
8537
8538       /* If we discovered we had to complement VAROP, leave.  Making a NOT
8539          here would cause an infinite loop.  */
8540       if (complement_p)
8541         break;
8542
8543       /* Convert ROTATERT to ROTATE.  */
8544       if (code == ROTATERT)
8545         {
8546           unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8547           code = ROTATE;
8548           if (VECTOR_MODE_P (result_mode))
8549             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8550           else
8551             count = bitsize - count;
8552         }
8553
8554       /* We need to determine what mode we will do the shift in.  If the
8555          shift is a right shift or a ROTATE, we must always do it in the mode
8556          it was originally done in.  Otherwise, we can do it in MODE, the
8557          widest mode encountered.  */
8558       shift_mode
8559         = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8560            ? result_mode : mode);
8561
8562       /* Handle cases where the count is greater than the size of the mode
8563          minus 1.  For ASHIFT, use the size minus one as the count (this can
8564          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
8565          take the count modulo the size.  For other shifts, the result is
8566          zero.
8567
8568          Since these shifts are being produced by the compiler by combining
8569          multiple operations, each of which are defined, we know what the
8570          result is supposed to be.  */
8571
8572       if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8573         {
8574           if (code == ASHIFTRT)
8575             count = GET_MODE_BITSIZE (shift_mode) - 1;
8576           else if (code == ROTATE || code == ROTATERT)
8577             count %= GET_MODE_BITSIZE (shift_mode);
8578           else
8579             {
8580               /* We can't simply return zero because there may be an
8581                  outer op.  */
8582               varop = const0_rtx;
8583               count = 0;
8584               break;
8585             }
8586         }
8587
8588       /* An arithmetic right shift of a quantity known to be -1 or 0
8589          is a no-op.  */
8590       if (code == ASHIFTRT
8591           && (num_sign_bit_copies (varop, shift_mode)
8592               == GET_MODE_BITSIZE (shift_mode)))
8593         {
8594           count = 0;
8595           break;
8596         }
8597
8598       /* If we are doing an arithmetic right shift and discarding all but
8599          the sign bit copies, this is equivalent to doing a shift by the
8600          bitsize minus one.  Convert it into that shift because it will often
8601          allow other simplifications.  */
8602
8603       if (code == ASHIFTRT
8604           && (count + num_sign_bit_copies (varop, shift_mode)
8605               >= GET_MODE_BITSIZE (shift_mode)))
8606         count = GET_MODE_BITSIZE (shift_mode) - 1;
8607
8608       /* We simplify the tests below and elsewhere by converting
8609          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8610          `make_compound_operation' will convert it to an ASHIFTRT for
8611          those machines (such as VAX) that don't have an LSHIFTRT.  */
8612       if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8613           && code == ASHIFTRT
8614           && ((nonzero_bits (varop, shift_mode)
8615                & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8616               == 0))
8617         code = LSHIFTRT;
8618
8619       if (code == LSHIFTRT
8620           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8621           && !(nonzero_bits (varop, shift_mode) >> count))
8622         varop = const0_rtx;
8623       if (code == ASHIFT
8624           && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8625           && !((nonzero_bits (varop, shift_mode) << count)
8626                & GET_MODE_MASK (shift_mode)))
8627         varop = const0_rtx;
8628
8629       switch (GET_CODE (varop))
8630         {
8631         case SIGN_EXTEND:
8632         case ZERO_EXTEND:
8633         case SIGN_EXTRACT:
8634         case ZERO_EXTRACT:
8635           new = expand_compound_operation (varop);
8636           if (new != varop)
8637             {
8638               varop = new;
8639               continue;
8640             }
8641           break;
8642
8643         case MEM:
8644           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8645              minus the width of a smaller mode, we can do this with a
8646              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
8647           if ((code == ASHIFTRT || code == LSHIFTRT)
8648               && ! mode_dependent_address_p (XEXP (varop, 0))
8649               && ! MEM_VOLATILE_P (varop)
8650               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8651                                          MODE_INT, 1)) != BLKmode)
8652             {
8653               new = adjust_address_nv (varop, tmode,
8654                                        BYTES_BIG_ENDIAN ? 0
8655                                        : count / BITS_PER_UNIT);
8656
8657               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8658                                      : ZERO_EXTEND, mode, new);
8659               count = 0;
8660               continue;
8661             }
8662           break;
8663
8664         case SUBREG:
8665           /* If VAROP is a SUBREG, strip it as long as the inner operand has
8666              the same number of words as what we've seen so far.  Then store
8667              the widest mode in MODE.  */
8668           if (subreg_lowpart_p (varop)
8669               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8670                   > GET_MODE_SIZE (GET_MODE (varop)))
8671               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8672                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8673                  == mode_words)
8674             {
8675               varop = SUBREG_REG (varop);
8676               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8677                 mode = GET_MODE (varop);
8678               continue;
8679             }
8680           break;
8681
8682         case MULT:
8683           /* Some machines use MULT instead of ASHIFT because MULT
8684              is cheaper.  But it is still better on those machines to
8685              merge two shifts into one.  */
8686           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8687               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8688             {
8689               varop
8690                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8691                                        XEXP (varop, 0),
8692                                        GEN_INT (exact_log2 (
8693                                                 INTVAL (XEXP (varop, 1)))));
8694               continue;
8695             }
8696           break;
8697
8698         case UDIV:
8699           /* Similar, for when divides are cheaper.  */
8700           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8701               && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8702             {
8703               varop
8704                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8705                                        XEXP (varop, 0),
8706                                        GEN_INT (exact_log2 (
8707                                                 INTVAL (XEXP (varop, 1)))));
8708               continue;
8709             }
8710           break;
8711
8712         case ASHIFTRT:
8713           /* If we are extracting just the sign bit of an arithmetic
8714              right shift, that shift is not needed.  However, the sign
8715              bit of a wider mode may be different from what would be
8716              interpreted as the sign bit in a narrower mode, so, if
8717              the result is narrower, don't discard the shift.  */
8718           if (code == LSHIFTRT
8719               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8720               && (GET_MODE_BITSIZE (result_mode)
8721                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
8722             {
8723               varop = XEXP (varop, 0);
8724               continue;
8725             }
8726
8727           /* ... fall through ...  */
8728
8729         case LSHIFTRT:
8730         case ASHIFT:
8731         case ROTATE:
8732           /* Here we have two nested shifts.  The result is usually the
8733              AND of a new shift with a mask.  We compute the result below.  */
8734           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8735               && INTVAL (XEXP (varop, 1)) >= 0
8736               && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8737               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8738               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8739               && !VECTOR_MODE_P (result_mode))
8740             {
8741               enum rtx_code first_code = GET_CODE (varop);
8742               unsigned int first_count = INTVAL (XEXP (varop, 1));
8743               unsigned HOST_WIDE_INT mask;
8744               rtx mask_rtx;
8745
8746               /* We have one common special case.  We can't do any merging if
8747                  the inner code is an ASHIFTRT of a smaller mode.  However, if
8748                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8749                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8750                  we can convert it to
8751                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8752                  This simplifies certain SIGN_EXTEND operations.  */
8753               if (code == ASHIFT && first_code == ASHIFTRT
8754                   && count == (GET_MODE_BITSIZE (result_mode)
8755                                - GET_MODE_BITSIZE (GET_MODE (varop))))
8756                 {
8757                   /* C3 has the low-order C1 bits zero.  */
8758
8759                   mask = (GET_MODE_MASK (mode)
8760                           & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8761
8762                   varop = simplify_and_const_int (NULL_RTX, result_mode,
8763                                                   XEXP (varop, 0), mask);
8764                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8765                                                 varop, count);
8766                   count = first_count;
8767                   code = ASHIFTRT;
8768                   continue;
8769                 }
8770
8771               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8772                  than C1 high-order bits equal to the sign bit, we can convert
8773                  this to either an ASHIFT or an ASHIFTRT depending on the
8774                  two counts.
8775
8776                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
8777
8778               if (code == ASHIFTRT && first_code == ASHIFT
8779                   && GET_MODE (varop) == shift_mode
8780                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8781                       > first_count))
8782                 {
8783                   varop = XEXP (varop, 0);
8784                   count -= first_count;
8785                   if (count < 0)
8786                     {
8787                       count = -count;
8788                       code = ASHIFT;
8789                     }
8790
8791                   continue;
8792                 }
8793
8794               /* There are some cases we can't do.  If CODE is ASHIFTRT,
8795                  we can only do this if FIRST_CODE is also ASHIFTRT.
8796
8797                  We can't do the case when CODE is ROTATE and FIRST_CODE is
8798                  ASHIFTRT.
8799
8800                  If the mode of this shift is not the mode of the outer shift,
8801                  we can't do this if either shift is a right shift or ROTATE.
8802
8803                  Finally, we can't do any of these if the mode is too wide
8804                  unless the codes are the same.
8805
8806                  Handle the case where the shift codes are the same
8807                  first.  */
8808
8809               if (code == first_code)
8810                 {
8811                   if (GET_MODE (varop) != result_mode
8812                       && (code == ASHIFTRT || code == LSHIFTRT
8813                           || code == ROTATE))
8814                     break;
8815
8816                   count += first_count;
8817                   varop = XEXP (varop, 0);
8818                   continue;
8819                 }
8820
8821               if (code == ASHIFTRT
8822                   || (code == ROTATE && first_code == ASHIFTRT)
8823                   || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8824                   || (GET_MODE (varop) != result_mode
8825                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
8826                           || first_code == ROTATE
8827                           || code == ROTATE)))
8828                 break;
8829
8830               /* To compute the mask to apply after the shift, shift the
8831                  nonzero bits of the inner shift the same way the
8832                  outer shift will.  */
8833
8834               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8835
8836               mask_rtx
8837                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8838                                                    GEN_INT (count));
8839
8840               /* Give up if we can't compute an outer operation to use.  */
8841               if (mask_rtx == 0
8842                   || GET_CODE (mask_rtx) != CONST_INT
8843                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
8844                                         INTVAL (mask_rtx),
8845                                         result_mode, &complement_p))
8846                 break;
8847
8848               /* If the shifts are in the same direction, we add the
8849                  counts.  Otherwise, we subtract them.  */
8850               if ((code == ASHIFTRT || code == LSHIFTRT)
8851                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8852                 count += first_count;
8853               else
8854                 count -= first_count;
8855
8856               /* If COUNT is positive, the new shift is usually CODE,
8857                  except for the two exceptions below, in which case it is
8858                  FIRST_CODE.  If the count is negative, FIRST_CODE should
8859                  always be used  */
8860               if (count > 0
8861                   && ((first_code == ROTATE && code == ASHIFT)
8862                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
8863                 code = first_code;
8864               else if (count < 0)
8865                 code = first_code, count = -count;
8866
8867               varop = XEXP (varop, 0);
8868               continue;
8869             }
8870
8871           /* If we have (A << B << C) for any shift, we can convert this to
8872              (A << C << B).  This wins if A is a constant.  Only try this if
8873              B is not a constant.  */
8874
8875           else if (GET_CODE (varop) == code
8876                    && GET_CODE (XEXP (varop, 0)) == CONST_INT
8877                    && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8878             {
8879               rtx new = simplify_const_binary_operation (code, mode,
8880                                                          XEXP (varop, 0),
8881                                                          GEN_INT (count));
8882               varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8883               count = 0;
8884               continue;
8885             }
8886           break;
8887
8888         case NOT:
8889           /* Make this fit the case below.  */
8890           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8891                                GEN_INT (GET_MODE_MASK (mode)));
8892           continue;
8893
8894         case IOR:
8895         case AND:
8896         case XOR:
8897           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8898              with C the size of VAROP - 1 and the shift is logical if
8899              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8900              we have an (le X 0) operation.   If we have an arithmetic shift
8901              and STORE_FLAG_VALUE is 1 or we have a logical shift with
8902              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
8903
8904           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8905               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8906               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8907               && (code == LSHIFTRT || code == ASHIFTRT)
8908               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8909               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8910             {
8911               count = 0;
8912               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8913                                   const0_rtx);
8914
8915               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8916                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8917
8918               continue;
8919             }
8920
8921           /* If we have (shift (logical)), move the logical to the outside
8922              to allow it to possibly combine with another logical and the
8923              shift to combine with another shift.  This also canonicalizes to
8924              what a ZERO_EXTRACT looks like.  Also, some machines have
8925              (and (shift)) insns.  */
8926
8927           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8928               /* We can't do this if we have (ashiftrt (xor))  and the
8929                  constant has its sign bit set in shift_mode.  */
8930               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8931                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8932                                               shift_mode))
8933               && (new = simplify_const_binary_operation (code, result_mode,
8934                                                          XEXP (varop, 1),
8935                                                          GEN_INT (count))) != 0
8936               && GET_CODE (new) == CONST_INT
8937               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8938                                   INTVAL (new), result_mode, &complement_p))
8939             {
8940               varop = XEXP (varop, 0);
8941               continue;
8942             }
8943
8944           /* If we can't do that, try to simplify the shift in each arm of the
8945              logical expression, make a new logical expression, and apply
8946              the inverse distributive law.  This also can't be done
8947              for some (ashiftrt (xor)).  */
8948           if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8949              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8950                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8951                                              shift_mode)))
8952             {
8953               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8954                                               XEXP (varop, 0), count);
8955               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8956                                               XEXP (varop, 1), count);
8957
8958               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8959                                            lhs, rhs);
8960               varop = apply_distributive_law (varop);
8961
8962               count = 0;
8963               continue;
8964             }
8965           break;
8966
8967         case EQ:
8968           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8969              says that the sign bit can be tested, FOO has mode MODE, C is
8970              GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8971              that may be nonzero.  */
8972           if (code == LSHIFTRT
8973               && XEXP (varop, 1) == const0_rtx
8974               && GET_MODE (XEXP (varop, 0)) == result_mode
8975               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8976               && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8977               && STORE_FLAG_VALUE == -1
8978               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8979               && merge_outer_ops (&outer_op, &outer_const, XOR,
8980                                   (HOST_WIDE_INT) 1, result_mode,
8981                                   &complement_p))
8982             {
8983               varop = XEXP (varop, 0);
8984               count = 0;
8985               continue;
8986             }
8987           break;
8988
8989         case NEG:
8990           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8991              than the number of bits in the mode is equivalent to A.  */
8992           if (code == LSHIFTRT
8993               && count == (GET_MODE_BITSIZE (result_mode) - 1)
8994               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8995             {
8996               varop = XEXP (varop, 0);
8997               count = 0;
8998               continue;
8999             }
9000
9001           /* NEG commutes with ASHIFT since it is multiplication.  Move the
9002              NEG outside to allow shifts to combine.  */
9003           if (code == ASHIFT
9004               && merge_outer_ops (&outer_op, &outer_const, NEG,
9005                                   (HOST_WIDE_INT) 0, result_mode,
9006                                   &complement_p))
9007             {
9008               varop = XEXP (varop, 0);
9009               continue;
9010             }
9011           break;
9012
9013         case PLUS:
9014           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9015              is one less than the number of bits in the mode is
9016              equivalent to (xor A 1).  */
9017           if (code == LSHIFTRT
9018               && count == (GET_MODE_BITSIZE (result_mode) - 1)
9019               && XEXP (varop, 1) == constm1_rtx
9020               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9021               && merge_outer_ops (&outer_op, &outer_const, XOR,
9022                                   (HOST_WIDE_INT) 1, result_mode,
9023                                   &complement_p))
9024             {
9025               count = 0;
9026               varop = XEXP (varop, 0);
9027               continue;
9028             }
9029
9030           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9031              that might be nonzero in BAR are those being shifted out and those
9032              bits are known zero in FOO, we can replace the PLUS with FOO.
9033              Similarly in the other operand order.  This code occurs when
9034              we are computing the size of a variable-size array.  */
9035
9036           if ((code == ASHIFTRT || code == LSHIFTRT)
9037               && count < HOST_BITS_PER_WIDE_INT
9038               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9039               && (nonzero_bits (XEXP (varop, 1), result_mode)
9040                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9041             {
9042               varop = XEXP (varop, 0);
9043               continue;
9044             }
9045           else if ((code == ASHIFTRT || code == LSHIFTRT)
9046                    && count < HOST_BITS_PER_WIDE_INT
9047                    && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9048                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9049                             >> count)
9050                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9051                             & nonzero_bits (XEXP (varop, 1),
9052                                                  result_mode)))
9053             {
9054               varop = XEXP (varop, 1);
9055               continue;
9056             }
9057
9058           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
9059           if (code == ASHIFT
9060               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9061               && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9062                                                          XEXP (varop, 1),
9063                                                          GEN_INT (count))) != 0
9064               && GET_CODE (new) == CONST_INT
9065               && merge_outer_ops (&outer_op, &outer_const, PLUS,
9066                                   INTVAL (new), result_mode, &complement_p))
9067             {
9068               varop = XEXP (varop, 0);
9069               continue;
9070             }
9071
9072           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9073              signbit', and attempt to change the PLUS to an XOR and move it to
9074              the outer operation as is done above in the AND/IOR/XOR case
9075              leg for shift(logical). See details in logical handling above
9076              for reasoning in doing so.  */
9077           if (code == LSHIFTRT
9078               && GET_CODE (XEXP (varop, 1)) == CONST_INT
9079               && mode_signbit_p (result_mode, XEXP (varop, 1))
9080               && (new = simplify_const_binary_operation (code, result_mode,
9081                                                          XEXP (varop, 1),
9082                                                          GEN_INT (count))) != 0
9083               && GET_CODE (new) == CONST_INT
9084               && merge_outer_ops (&outer_op, &outer_const, XOR,
9085                                   INTVAL (new), result_mode, &complement_p))
9086             {
9087               varop = XEXP (varop, 0);
9088               continue;
9089             }
9090
9091           break;
9092
9093         case MINUS:
9094           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9095              with C the size of VAROP - 1 and the shift is logical if
9096              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9097              we have a (gt X 0) operation.  If the shift is arithmetic with
9098              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9099              we have a (neg (gt X 0)) operation.  */
9100
9101           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9102               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9103               && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9104               && (code == LSHIFTRT || code == ASHIFTRT)
9105               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9106               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9107               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9108             {
9109               count = 0;
9110               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9111                                   const0_rtx);
9112
9113               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9114                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9115
9116               continue;
9117             }
9118           break;
9119
9120         case TRUNCATE:
9121           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9122              if the truncate does not affect the value.  */
9123           if (code == LSHIFTRT
9124               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9125               && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9126               && (INTVAL (XEXP (XEXP (varop, 0), 1))
9127                   >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9128                       - GET_MODE_BITSIZE (GET_MODE (varop)))))
9129             {
9130               rtx varop_inner = XEXP (varop, 0);
9131
9132               varop_inner
9133                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9134                                     XEXP (varop_inner, 0),
9135                                     GEN_INT
9136                                     (count + INTVAL (XEXP (varop_inner, 1))));
9137               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9138               count = 0;
9139               continue;
9140             }
9141           break;
9142
9143         default:
9144           break;
9145         }
9146
9147       break;
9148     }
9149
9150   /* We need to determine what mode to do the shift in.  If the shift is
9151      a right shift or ROTATE, we must always do it in the mode it was
9152      originally done in.  Otherwise, we can do it in MODE, the widest mode
9153      encountered.  The code we care about is that of the shift that will
9154      actually be done, not the shift that was originally requested.  */
9155   shift_mode
9156     = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9157        ? result_mode : mode);
9158
9159   /* We have now finished analyzing the shift.  The result should be
9160      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
9161      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9162      to the result of the shift.  OUTER_CONST is the relevant constant,
9163      but we must turn off all bits turned off in the shift.  */
9164
9165   if (outer_op == UNKNOWN
9166       && orig_code == code && orig_count == count
9167       && varop == orig_varop
9168       && shift_mode == GET_MODE (varop))
9169     return NULL_RTX;
9170
9171   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9172   varop = gen_lowpart (shift_mode, varop);
9173   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9174     return NULL_RTX;
9175
9176   /* If we have an outer operation and we just made a shift, it is
9177      possible that we could have simplified the shift were it not
9178      for the outer operation.  So try to do the simplification
9179      recursively.  */
9180
9181   if (outer_op != UNKNOWN)
9182     x = simplify_shift_const_1 (code, shift_mode, varop, count);
9183   else
9184     x = NULL_RTX;
9185
9186   if (x == NULL_RTX)
9187     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9188
9189   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9190      turn off all the bits that the shift would have turned off.  */
9191   if (orig_code == LSHIFTRT && result_mode != shift_mode)
9192     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9193                                 GET_MODE_MASK (result_mode) >> orig_count);
9194
9195   /* Do the remainder of the processing in RESULT_MODE.  */
9196   x = gen_lowpart_or_truncate (result_mode, x);
9197
9198   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9199      operation.  */
9200   if (complement_p)
9201     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9202
9203   if (outer_op != UNKNOWN)
9204     {
9205       if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9206         outer_const = trunc_int_for_mode (outer_const, result_mode);
9207
9208       if (outer_op == AND)
9209         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9210       else if (outer_op == SET)
9211         /* This means that we have determined that the result is
9212            equivalent to a constant.  This should be rare.  */
9213         x = GEN_INT (outer_const);
9214       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9215         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9216       else
9217         x = simplify_gen_binary (outer_op, result_mode, x,
9218                                  GEN_INT (outer_const));
9219     }
9220
9221   return x;
9222 }
9223
9224 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
9225    The result of the shift is RESULT_MODE.  If we cannot simplify it,
9226    return X or, if it is NULL, synthesize the expression with
9227    simplify_gen_binary.  Otherwise, return a simplified value.
9228
9229    The shift is normally computed in the widest mode we find in VAROP, as
9230    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9231    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9232
9233 static rtx
9234 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9235                       rtx varop, int count)
9236 {
9237   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9238   if (tem)
9239     return tem;
9240
9241   if (!x)
9242     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9243   if (GET_MODE (x) != result_mode)
9244     x = gen_lowpart (result_mode, x);
9245   return x;
9246 }
9247
9248 \f
9249 /* Like recog, but we receive the address of a pointer to a new pattern.
9250    We try to match the rtx that the pointer points to.
9251    If that fails, we may try to modify or replace the pattern,
9252    storing the replacement into the same pointer object.
9253
9254    Modifications include deletion or addition of CLOBBERs.
9255
9256    PNOTES is a pointer to a location where any REG_UNUSED notes added for
9257    the CLOBBERs are placed.
9258
9259    The value is the final insn code from the pattern ultimately matched,
9260    or -1.  */
9261
9262 static int
9263 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9264 {
9265   rtx pat = *pnewpat;
9266   int insn_code_number;
9267   int num_clobbers_to_add = 0;
9268   int i;
9269   rtx notes = 0;
9270   rtx old_notes, old_pat;
9271
9272   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9273      we use to indicate that something didn't match.  If we find such a
9274      thing, force rejection.  */
9275   if (GET_CODE (pat) == PARALLEL)
9276     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9277       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9278           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9279         return -1;
9280
9281   old_pat = PATTERN (insn);
9282   old_notes = REG_NOTES (insn);
9283   PATTERN (insn) = pat;
9284   REG_NOTES (insn) = 0;
9285
9286   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9287
9288   /* If it isn't, there is the possibility that we previously had an insn
9289      that clobbered some register as a side effect, but the combined
9290      insn doesn't need to do that.  So try once more without the clobbers
9291      unless this represents an ASM insn.  */
9292
9293   if (insn_code_number < 0 && ! check_asm_operands (pat)
9294       && GET_CODE (pat) == PARALLEL)
9295     {
9296       int pos;
9297
9298       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9299         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9300           {
9301             if (i != pos)
9302               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9303             pos++;
9304           }
9305
9306       SUBST_INT (XVECLEN (pat, 0), pos);
9307
9308       if (pos == 1)
9309         pat = XVECEXP (pat, 0, 0);
9310
9311       PATTERN (insn) = pat;
9312       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9313     }
9314   PATTERN (insn) = old_pat;
9315   REG_NOTES (insn) = old_notes;
9316
9317   /* Recognize all noop sets, these will be killed by followup pass.  */
9318   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9319     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9320
9321   /* If we had any clobbers to add, make a new pattern than contains
9322      them.  Then check to make sure that all of them are dead.  */
9323   if (num_clobbers_to_add)
9324     {
9325       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9326                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
9327                                                   ? (XVECLEN (pat, 0)
9328                                                      + num_clobbers_to_add)
9329                                                   : num_clobbers_to_add + 1));
9330
9331       if (GET_CODE (pat) == PARALLEL)
9332         for (i = 0; i < XVECLEN (pat, 0); i++)
9333           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9334       else
9335         XVECEXP (newpat, 0, 0) = pat;
9336
9337       add_clobbers (newpat, insn_code_number);
9338
9339       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9340            i < XVECLEN (newpat, 0); i++)
9341         {
9342           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9343               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9344             return -1;
9345           notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9346                                      XEXP (XVECEXP (newpat, 0, i), 0), notes);
9347         }
9348       pat = newpat;
9349     }
9350
9351   *pnewpat = pat;
9352   *pnotes = notes;
9353
9354   return insn_code_number;
9355 }
9356 \f
9357 /* Like gen_lowpart_general but for use by combine.  In combine it
9358    is not possible to create any new pseudoregs.  However, it is
9359    safe to create invalid memory addresses, because combine will
9360    try to recognize them and all they will do is make the combine
9361    attempt fail.
9362
9363    If for some reason this cannot do its job, an rtx
9364    (clobber (const_int 0)) is returned.
9365    An insn containing that will not be recognized.  */
9366
9367 static rtx
9368 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9369 {
9370   enum machine_mode imode = GET_MODE (x);
9371   unsigned int osize = GET_MODE_SIZE (omode);
9372   unsigned int isize = GET_MODE_SIZE (imode);
9373   rtx result;
9374
9375   if (omode == imode)
9376     return x;
9377
9378   /* Return identity if this is a CONST or symbolic reference.  */
9379   if (omode == Pmode
9380       && (GET_CODE (x) == CONST
9381           || GET_CODE (x) == SYMBOL_REF
9382           || GET_CODE (x) == LABEL_REF))
9383     return x;
9384
9385   /* We can only support MODE being wider than a word if X is a
9386      constant integer or has a mode the same size.  */
9387   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9388       && ! ((imode == VOIDmode
9389              && (GET_CODE (x) == CONST_INT
9390                  || GET_CODE (x) == CONST_DOUBLE))
9391             || isize == osize))
9392     goto fail;
9393
9394   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
9395      won't know what to do.  So we will strip off the SUBREG here and
9396      process normally.  */
9397   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9398     {
9399       x = SUBREG_REG (x);
9400
9401       /* For use in case we fall down into the address adjustments
9402          further below, we need to adjust the known mode and size of
9403          x; imode and isize, since we just adjusted x.  */
9404       imode = GET_MODE (x);
9405
9406       if (imode == omode)
9407         return x;
9408
9409       isize = GET_MODE_SIZE (imode);
9410     }
9411
9412   result = gen_lowpart_common (omode, x);
9413
9414 #ifdef CANNOT_CHANGE_MODE_CLASS
9415   if (result != 0 && GET_CODE (result) == SUBREG)
9416     record_subregs_of_mode (result);
9417 #endif
9418
9419   if (result)
9420     return result;
9421
9422   if (MEM_P (x))
9423     {
9424       int offset = 0;
9425
9426       /* Refuse to work on a volatile memory ref or one with a mode-dependent
9427          address.  */
9428       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9429         goto fail;
9430
9431       /* If we want to refer to something bigger than the original memref,
9432          generate a paradoxical subreg instead.  That will force a reload
9433          of the original memref X.  */
9434       if (isize < osize)
9435         return gen_rtx_SUBREG (omode, x, 0);
9436
9437       if (WORDS_BIG_ENDIAN)
9438         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9439
9440       /* Adjust the address so that the address-after-the-data is
9441          unchanged.  */
9442       if (BYTES_BIG_ENDIAN)
9443         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9444
9445       return adjust_address_nv (x, omode, offset);
9446     }
9447
9448   /* If X is a comparison operator, rewrite it in a new mode.  This
9449      probably won't match, but may allow further simplifications.  */
9450   else if (COMPARISON_P (x))
9451     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9452
9453   /* If we couldn't simplify X any other way, just enclose it in a
9454      SUBREG.  Normally, this SUBREG won't match, but some patterns may
9455      include an explicit SUBREG or we may simplify it further in combine.  */
9456   else
9457     {
9458       int offset = 0;
9459       rtx res;
9460
9461       offset = subreg_lowpart_offset (omode, imode);
9462       if (imode == VOIDmode)
9463         {
9464           imode = int_mode_for_mode (omode);
9465           x = gen_lowpart_common (imode, x);
9466           if (x == NULL)
9467             goto fail;
9468         }
9469       res = simplify_gen_subreg (omode, x, imode, offset);
9470       if (res)
9471         return res;
9472     }
9473
9474  fail:
9475   return gen_rtx_CLOBBER (imode, const0_rtx);
9476 }
9477 \f
9478 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9479    comparison code that will be tested.
9480
9481    The result is a possibly different comparison code to use.  *POP0 and
9482    *POP1 may be updated.
9483
9484    It is possible that we might detect that a comparison is either always
9485    true or always false.  However, we do not perform general constant
9486    folding in combine, so this knowledge isn't useful.  Such tautologies
9487    should have been detected earlier.  Hence we ignore all such cases.  */
9488
9489 static enum rtx_code
9490 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9491 {
9492   rtx op0 = *pop0;
9493   rtx op1 = *pop1;
9494   rtx tem, tem1;
9495   int i;
9496   enum machine_mode mode, tmode;
9497
9498   /* Try a few ways of applying the same transformation to both operands.  */
9499   while (1)
9500     {
9501 #ifndef WORD_REGISTER_OPERATIONS
9502       /* The test below this one won't handle SIGN_EXTENDs on these machines,
9503          so check specially.  */
9504       if (code != GTU && code != GEU && code != LTU && code != LEU
9505           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9506           && GET_CODE (XEXP (op0, 0)) == ASHIFT
9507           && GET_CODE (XEXP (op1, 0)) == ASHIFT
9508           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9509           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9510           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9511               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9512           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9513           && XEXP (op0, 1) == XEXP (op1, 1)
9514           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9515           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9516           && (INTVAL (XEXP (op0, 1))
9517               == (GET_MODE_BITSIZE (GET_MODE (op0))
9518                   - (GET_MODE_BITSIZE
9519                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9520         {
9521           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9522           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9523         }
9524 #endif
9525
9526       /* If both operands are the same constant shift, see if we can ignore the
9527          shift.  We can if the shift is a rotate or if the bits shifted out of
9528          this shift are known to be zero for both inputs and if the type of
9529          comparison is compatible with the shift.  */
9530       if (GET_CODE (op0) == GET_CODE (op1)
9531           && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9532           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9533               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9534                   && (code != GT && code != LT && code != GE && code != LE))
9535               || (GET_CODE (op0) == ASHIFTRT
9536                   && (code != GTU && code != LTU
9537                       && code != GEU && code != LEU)))
9538           && GET_CODE (XEXP (op0, 1)) == CONST_INT
9539           && INTVAL (XEXP (op0, 1)) >= 0
9540           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9541           && XEXP (op0, 1) == XEXP (op1, 1))
9542         {
9543           enum machine_mode mode = GET_MODE (op0);
9544           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9545           int shift_count = INTVAL (XEXP (op0, 1));
9546
9547           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9548             mask &= (mask >> shift_count) << shift_count;
9549           else if (GET_CODE (op0) == ASHIFT)
9550             mask = (mask & (mask << shift_count)) >> shift_count;
9551
9552           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9553               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9554             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9555           else
9556             break;
9557         }
9558
9559       /* If both operands are AND's of a paradoxical SUBREG by constant, the
9560          SUBREGs are of the same mode, and, in both cases, the AND would
9561          be redundant if the comparison was done in the narrower mode,
9562          do the comparison in the narrower mode (e.g., we are AND'ing with 1
9563          and the operand's possibly nonzero bits are 0xffffff01; in that case
9564          if we only care about QImode, we don't need the AND).  This case
9565          occurs if the output mode of an scc insn is not SImode and
9566          STORE_FLAG_VALUE == 1 (e.g., the 386).
9567
9568          Similarly, check for a case where the AND's are ZERO_EXTEND
9569          operations from some narrower mode even though a SUBREG is not
9570          present.  */
9571
9572       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9573                && GET_CODE (XEXP (op0, 1)) == CONST_INT
9574                && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9575         {
9576           rtx inner_op0 = XEXP (op0, 0);
9577           rtx inner_op1 = XEXP (op1, 0);
9578           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9579           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9580           int changed = 0;
9581
9582           if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9583               && (GET_MODE_SIZE (GET_MODE (inner_op0))
9584                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9585               && (GET_MODE (SUBREG_REG (inner_op0))
9586                   == GET_MODE (SUBREG_REG (inner_op1)))
9587               && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9588                   <= HOST_BITS_PER_WIDE_INT)
9589               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9590                                              GET_MODE (SUBREG_REG (inner_op0)))))
9591               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9592                                              GET_MODE (SUBREG_REG (inner_op1))))))
9593             {
9594               op0 = SUBREG_REG (inner_op0);
9595               op1 = SUBREG_REG (inner_op1);
9596
9597               /* The resulting comparison is always unsigned since we masked
9598                  off the original sign bit.  */
9599               code = unsigned_condition (code);
9600
9601               changed = 1;
9602             }
9603
9604           else if (c0 == c1)
9605             for (tmode = GET_CLASS_NARROWEST_MODE
9606                  (GET_MODE_CLASS (GET_MODE (op0)));
9607                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9608               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9609                 {
9610                   op0 = gen_lowpart (tmode, inner_op0);
9611                   op1 = gen_lowpart (tmode, inner_op1);
9612                   code = unsigned_condition (code);
9613                   changed = 1;
9614                   break;
9615                 }
9616
9617           if (! changed)
9618             break;
9619         }
9620
9621       /* If both operands are NOT, we can strip off the outer operation
9622          and adjust the comparison code for swapped operands; similarly for
9623          NEG, except that this must be an equality comparison.  */
9624       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9625                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9626                    && (code == EQ || code == NE)))
9627         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9628
9629       else
9630         break;
9631     }
9632
9633   /* If the first operand is a constant, swap the operands and adjust the
9634      comparison code appropriately, but don't do this if the second operand
9635      is already a constant integer.  */
9636   if (swap_commutative_operands_p (op0, op1))
9637     {
9638       tem = op0, op0 = op1, op1 = tem;
9639       code = swap_condition (code);
9640     }
9641
9642   /* We now enter a loop during which we will try to simplify the comparison.
9643      For the most part, we only are concerned with comparisons with zero,
9644      but some things may really be comparisons with zero but not start
9645      out looking that way.  */
9646
9647   while (GET_CODE (op1) == CONST_INT)
9648     {
9649       enum machine_mode mode = GET_MODE (op0);
9650       unsigned int mode_width = GET_MODE_BITSIZE (mode);
9651       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9652       int equality_comparison_p;
9653       int sign_bit_comparison_p;
9654       int unsigned_comparison_p;
9655       HOST_WIDE_INT const_op;
9656
9657       /* We only want to handle integral modes.  This catches VOIDmode,
9658          CCmode, and the floating-point modes.  An exception is that we
9659          can handle VOIDmode if OP0 is a COMPARE or a comparison
9660          operation.  */
9661
9662       if (GET_MODE_CLASS (mode) != MODE_INT
9663           && ! (mode == VOIDmode
9664                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9665         break;
9666
9667       /* Get the constant we are comparing against and turn off all bits
9668          not on in our mode.  */
9669       const_op = INTVAL (op1);
9670       if (mode != VOIDmode)
9671         const_op = trunc_int_for_mode (const_op, mode);
9672       op1 = GEN_INT (const_op);
9673
9674       /* If we are comparing against a constant power of two and the value
9675          being compared can only have that single bit nonzero (e.g., it was
9676          `and'ed with that bit), we can replace this with a comparison
9677          with zero.  */
9678       if (const_op
9679           && (code == EQ || code == NE || code == GE || code == GEU
9680               || code == LT || code == LTU)
9681           && mode_width <= HOST_BITS_PER_WIDE_INT
9682           && exact_log2 (const_op) >= 0
9683           && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9684         {
9685           code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9686           op1 = const0_rtx, const_op = 0;
9687         }
9688
9689       /* Similarly, if we are comparing a value known to be either -1 or
9690          0 with -1, change it to the opposite comparison against zero.  */
9691
9692       if (const_op == -1
9693           && (code == EQ || code == NE || code == GT || code == LE
9694               || code == GEU || code == LTU)
9695           && num_sign_bit_copies (op0, mode) == mode_width)
9696         {
9697           code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9698           op1 = const0_rtx, const_op = 0;
9699         }
9700
9701       /* Do some canonicalizations based on the comparison code.  We prefer
9702          comparisons against zero and then prefer equality comparisons.
9703          If we can reduce the size of a constant, we will do that too.  */
9704
9705       switch (code)
9706         {
9707         case LT:
9708           /* < C is equivalent to <= (C - 1) */
9709           if (const_op > 0)
9710             {
9711               const_op -= 1;
9712               op1 = GEN_INT (const_op);
9713               code = LE;
9714               /* ... fall through to LE case below.  */
9715             }
9716           else
9717             break;
9718
9719         case LE:
9720           /* <= C is equivalent to < (C + 1); we do this for C < 0  */
9721           if (const_op < 0)
9722             {
9723               const_op += 1;
9724               op1 = GEN_INT (const_op);
9725               code = LT;
9726             }
9727
9728           /* If we are doing a <= 0 comparison on a value known to have
9729              a zero sign bit, we can replace this with == 0.  */
9730           else if (const_op == 0
9731                    && mode_width <= HOST_BITS_PER_WIDE_INT
9732                    && (nonzero_bits (op0, mode)
9733                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9734             code = EQ;
9735           break;
9736
9737         case GE:
9738           /* >= C is equivalent to > (C - 1).  */
9739           if (const_op > 0)
9740             {
9741               const_op -= 1;
9742               op1 = GEN_INT (const_op);
9743               code = GT;
9744               /* ... fall through to GT below.  */
9745             }
9746           else
9747             break;
9748
9749         case GT:
9750           /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
9751           if (const_op < 0)
9752             {
9753               const_op += 1;
9754               op1 = GEN_INT (const_op);
9755               code = GE;
9756             }
9757
9758           /* If we are doing a > 0 comparison on a value known to have
9759              a zero sign bit, we can replace this with != 0.  */
9760           else if (const_op == 0
9761                    && mode_width <= HOST_BITS_PER_WIDE_INT
9762                    && (nonzero_bits (op0, mode)
9763                        & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9764             code = NE;
9765           break;
9766
9767         case LTU:
9768           /* < C is equivalent to <= (C - 1).  */
9769           if (const_op > 0)
9770             {
9771               const_op -= 1;
9772               op1 = GEN_INT (const_op);
9773               code = LEU;
9774               /* ... fall through ...  */
9775             }
9776
9777           /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
9778           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9779                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9780             {
9781               const_op = 0, op1 = const0_rtx;
9782               code = GE;
9783               break;
9784             }
9785           else
9786             break;
9787
9788         case LEU:
9789           /* unsigned <= 0 is equivalent to == 0 */
9790           if (const_op == 0)
9791             code = EQ;
9792
9793           /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
9794           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9795                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9796             {
9797               const_op = 0, op1 = const0_rtx;
9798               code = GE;
9799             }
9800           break;
9801
9802         case GEU:
9803           /* >= C is equivalent to > (C - 1).  */
9804           if (const_op > 1)
9805             {
9806               const_op -= 1;
9807               op1 = GEN_INT (const_op);
9808               code = GTU;
9809               /* ... fall through ...  */
9810             }
9811
9812           /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
9813           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9814                    && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9815             {
9816               const_op = 0, op1 = const0_rtx;
9817               code = LT;
9818               break;
9819             }
9820           else
9821             break;
9822
9823         case GTU:
9824           /* unsigned > 0 is equivalent to != 0 */
9825           if (const_op == 0)
9826             code = NE;
9827
9828           /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
9829           else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9830                    && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9831             {
9832               const_op = 0, op1 = const0_rtx;
9833               code = LT;
9834             }
9835           break;
9836
9837         default:
9838           break;
9839         }
9840
9841       /* Compute some predicates to simplify code below.  */
9842
9843       equality_comparison_p = (code == EQ || code == NE);
9844       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9845       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9846                                || code == GEU);
9847
9848       /* If this is a sign bit comparison and we can do arithmetic in
9849          MODE, say that we will only be needing the sign bit of OP0.  */
9850       if (sign_bit_comparison_p
9851           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9852         op0 = force_to_mode (op0, mode,
9853                              ((HOST_WIDE_INT) 1
9854                               << (GET_MODE_BITSIZE (mode) - 1)),
9855                              0);
9856
9857       /* Now try cases based on the opcode of OP0.  If none of the cases
9858          does a "continue", we exit this loop immediately after the
9859          switch.  */
9860
9861       switch (GET_CODE (op0))
9862         {
9863         case ZERO_EXTRACT:
9864           /* If we are extracting a single bit from a variable position in
9865              a constant that has only a single bit set and are comparing it
9866              with zero, we can convert this into an equality comparison
9867              between the position and the location of the single bit.  */
9868           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9869              have already reduced the shift count modulo the word size.  */
9870           if (!SHIFT_COUNT_TRUNCATED
9871               && GET_CODE (XEXP (op0, 0)) == CONST_INT
9872               && XEXP (op0, 1) == const1_rtx
9873               && equality_comparison_p && const_op == 0
9874               && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9875             {
9876               if (BITS_BIG_ENDIAN)
9877                 {
9878                   enum machine_mode new_mode
9879                     = mode_for_extraction (EP_extzv, 1);
9880                   if (new_mode == MAX_MACHINE_MODE)
9881                     i = BITS_PER_WORD - 1 - i;
9882                   else
9883                     {
9884                       mode = new_mode;
9885                       i = (GET_MODE_BITSIZE (mode) - 1 - i);
9886                     }
9887                 }
9888
9889               op0 = XEXP (op0, 2);
9890               op1 = GEN_INT (i);
9891               const_op = i;
9892
9893               /* Result is nonzero iff shift count is equal to I.  */
9894               code = reverse_condition (code);
9895               continue;
9896             }
9897
9898           /* ... fall through ...  */
9899
9900         case SIGN_EXTRACT:
9901           tem = expand_compound_operation (op0);
9902           if (tem != op0)
9903             {
9904               op0 = tem;
9905               continue;
9906             }
9907           break;
9908
9909         case NOT:
9910           /* If testing for equality, we can take the NOT of the constant.  */
9911           if (equality_comparison_p
9912               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9913             {
9914               op0 = XEXP (op0, 0);
9915               op1 = tem;
9916               continue;
9917             }
9918
9919           /* If just looking at the sign bit, reverse the sense of the
9920              comparison.  */
9921           if (sign_bit_comparison_p)
9922             {
9923               op0 = XEXP (op0, 0);
9924               code = (code == GE ? LT : GE);
9925               continue;
9926             }
9927           break;
9928
9929         case NEG:
9930           /* If testing for equality, we can take the NEG of the constant.  */
9931           if (equality_comparison_p
9932               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9933             {
9934               op0 = XEXP (op0, 0);
9935               op1 = tem;
9936               continue;
9937             }
9938
9939           /* The remaining cases only apply to comparisons with zero.  */
9940           if (const_op != 0)
9941             break;
9942
9943           /* When X is ABS or is known positive,
9944              (neg X) is < 0 if and only if X != 0.  */
9945
9946           if (sign_bit_comparison_p
9947               && (GET_CODE (XEXP (op0, 0)) == ABS
9948                   || (mode_width <= HOST_BITS_PER_WIDE_INT
9949                       && (nonzero_bits (XEXP (op0, 0), mode)
9950                           & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9951             {
9952               op0 = XEXP (op0, 0);
9953               code = (code == LT ? NE : EQ);
9954               continue;
9955             }
9956
9957           /* If we have NEG of something whose two high-order bits are the
9958              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
9959           if (num_sign_bit_copies (op0, mode) >= 2)
9960             {
9961               op0 = XEXP (op0, 0);
9962               code = swap_condition (code);
9963               continue;
9964             }
9965           break;
9966
9967         case ROTATE:
9968           /* If we are testing equality and our count is a constant, we
9969              can perform the inverse operation on our RHS.  */
9970           if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9971               && (tem = simplify_binary_operation (ROTATERT, mode,
9972                                                    op1, XEXP (op0, 1))) != 0)
9973             {
9974               op0 = XEXP (op0, 0);
9975               op1 = tem;
9976               continue;
9977             }
9978
9979           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9980              a particular bit.  Convert it to an AND of a constant of that
9981              bit.  This will be converted into a ZERO_EXTRACT.  */
9982           if (const_op == 0 && sign_bit_comparison_p
9983               && GET_CODE (XEXP (op0, 1)) == CONST_INT
9984               && mode_width <= HOST_BITS_PER_WIDE_INT)
9985             {
9986               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9987                                             ((HOST_WIDE_INT) 1
9988                                              << (mode_width - 1
9989                                                  - INTVAL (XEXP (op0, 1)))));
9990               code = (code == LT ? NE : EQ);
9991               continue;
9992             }
9993
9994           /* Fall through.  */
9995
9996         case ABS:
9997           /* ABS is ignorable inside an equality comparison with zero.  */
9998           if (const_op == 0 && equality_comparison_p)
9999             {
10000               op0 = XEXP (op0, 0);
10001               continue;
10002             }
10003           break;
10004
10005         case SIGN_EXTEND:
10006           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10007              (compare FOO CONST) if CONST fits in FOO's mode and we
10008              are either testing inequality or have an unsigned
10009              comparison with ZERO_EXTEND or a signed comparison with
10010              SIGN_EXTEND.  But don't do it if we don't have a compare
10011              insn of the given mode, since we'd have to revert it
10012              later on, and then we wouldn't know whether to sign- or
10013              zero-extend.  */
10014           mode = GET_MODE (XEXP (op0, 0));
10015           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10016               && ! unsigned_comparison_p
10017               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10018               && ((unsigned HOST_WIDE_INT) const_op
10019                   < (((unsigned HOST_WIDE_INT) 1
10020                       << (GET_MODE_BITSIZE (mode) - 1))))
10021               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10022             {
10023               op0 = XEXP (op0, 0);
10024               continue;
10025             }
10026           break;
10027
10028         case SUBREG:
10029           /* Check for the case where we are comparing A - C1 with C2, that is
10030
10031                (subreg:MODE (plus (A) (-C1))) op (C2)
10032
10033              with C1 a constant, and try to lift the SUBREG, i.e. to do the
10034              comparison in the wider mode.  One of the following two conditions
10035              must be true in order for this to be valid:
10036
10037                1. The mode extension results in the same bit pattern being added
10038                   on both sides and the comparison is equality or unsigned.  As
10039                   C2 has been truncated to fit in MODE, the pattern can only be
10040                   all 0s or all 1s.
10041
10042                2. The mode extension results in the sign bit being copied on
10043                   each side.
10044
10045              The difficulty here is that we have predicates for A but not for
10046              (A - C1) so we need to check that C1 is within proper bounds so
10047              as to perturbate A as little as possible.  */
10048
10049           if (mode_width <= HOST_BITS_PER_WIDE_INT
10050               && subreg_lowpart_p (op0)
10051               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10052               && GET_CODE (SUBREG_REG (op0)) == PLUS
10053               && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10054             {
10055               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10056               rtx a = XEXP (SUBREG_REG (op0), 0);
10057               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10058
10059               if ((c1 > 0
10060                    && (unsigned HOST_WIDE_INT) c1
10061                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10062                    && (equality_comparison_p || unsigned_comparison_p)
10063                    /* (A - C1) zero-extends if it is positive and sign-extends
10064                       if it is negative, C2 both zero- and sign-extends.  */
10065                    && ((0 == (nonzero_bits (a, inner_mode)
10066                               & ~GET_MODE_MASK (mode))
10067                         && const_op >= 0)
10068                        /* (A - C1) sign-extends if it is positive and 1-extends
10069                           if it is negative, C2 both sign- and 1-extends.  */
10070                        || (num_sign_bit_copies (a, inner_mode)
10071                            > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10072                                              - mode_width)
10073                            && const_op < 0)))
10074                   || ((unsigned HOST_WIDE_INT) c1
10075                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10076                       /* (A - C1) always sign-extends, like C2.  */
10077                       && num_sign_bit_copies (a, inner_mode)
10078                          > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10079                                            - (mode_width - 1))))
10080                 {
10081                   op0 = SUBREG_REG (op0);
10082                   continue;
10083                 }
10084             }
10085
10086           /* If the inner mode is narrower and we are extracting the low part,
10087              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
10088           if (subreg_lowpart_p (op0)
10089               && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10090             /* Fall through */ ;
10091           else
10092             break;
10093
10094           /* ... fall through ...  */
10095
10096         case ZERO_EXTEND:
10097           mode = GET_MODE (XEXP (op0, 0));
10098           if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10099               && (unsigned_comparison_p || equality_comparison_p)
10100               && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10101               && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10102               && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10103             {
10104               op0 = XEXP (op0, 0);
10105               continue;
10106             }
10107           break;
10108
10109         case PLUS:
10110           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
10111              this for equality comparisons due to pathological cases involving
10112              overflows.  */
10113           if (equality_comparison_p
10114               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10115                                                         op1, XEXP (op0, 1))))
10116             {
10117               op0 = XEXP (op0, 0);
10118               op1 = tem;
10119               continue;
10120             }
10121
10122           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
10123           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10124               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10125             {
10126               op0 = XEXP (XEXP (op0, 0), 0);
10127               code = (code == LT ? EQ : NE);
10128               continue;
10129             }
10130           break;
10131
10132         case MINUS:
10133           /* We used to optimize signed comparisons against zero, but that
10134              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
10135              arrive here as equality comparisons, or (GEU, LTU) are
10136              optimized away.  No need to special-case them.  */
10137
10138           /* (eq (minus A B) C) -> (eq A (plus B C)) or
10139              (eq B (minus A C)), whichever simplifies.  We can only do
10140              this for equality comparisons due to pathological cases involving
10141              overflows.  */
10142           if (equality_comparison_p
10143               && 0 != (tem = simplify_binary_operation (PLUS, mode,
10144                                                         XEXP (op0, 1), op1)))
10145             {
10146               op0 = XEXP (op0, 0);
10147               op1 = tem;
10148               continue;
10149             }
10150
10151           if (equality_comparison_p
10152               && 0 != (tem = simplify_binary_operation (MINUS, mode,
10153                                                         XEXP (op0, 0), op1)))
10154             {
10155               op0 = XEXP (op0, 1);
10156               op1 = tem;
10157               continue;
10158             }
10159
10160           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10161              of bits in X minus 1, is one iff X > 0.  */
10162           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10163               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10164               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10165                  == mode_width - 1
10166               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10167             {
10168               op0 = XEXP (op0, 1);
10169               code = (code == GE ? LE : GT);
10170               continue;
10171             }
10172           break;
10173
10174         case XOR:
10175           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
10176              if C is zero or B is a constant.  */
10177           if (equality_comparison_p
10178               && 0 != (tem = simplify_binary_operation (XOR, mode,
10179                                                         XEXP (op0, 1), op1)))
10180             {
10181               op0 = XEXP (op0, 0);
10182               op1 = tem;
10183               continue;
10184             }
10185           break;
10186
10187         case EQ:  case NE:
10188         case UNEQ:  case LTGT:
10189         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
10190         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
10191         case UNORDERED: case ORDERED:
10192           /* We can't do anything if OP0 is a condition code value, rather
10193              than an actual data value.  */
10194           if (const_op != 0
10195               || CC0_P (XEXP (op0, 0))
10196               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10197             break;
10198
10199           /* Get the two operands being compared.  */
10200           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10201             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10202           else
10203             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10204
10205           /* Check for the cases where we simply want the result of the
10206              earlier test or the opposite of that result.  */
10207           if (code == NE || code == EQ
10208               || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10209                   && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10210                   && (STORE_FLAG_VALUE
10211                       & (((HOST_WIDE_INT) 1
10212                           << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10213                   && (code == LT || code == GE)))
10214             {
10215               enum rtx_code new_code;
10216               if (code == LT || code == NE)
10217                 new_code = GET_CODE (op0);
10218               else
10219                 new_code = reversed_comparison_code (op0, NULL);
10220
10221               if (new_code != UNKNOWN)
10222                 {
10223                   code = new_code;
10224                   op0 = tem;
10225                   op1 = tem1;
10226                   continue;
10227                 }
10228             }
10229           break;
10230
10231         case IOR:
10232           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10233              iff X <= 0.  */
10234           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10235               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10236               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10237             {
10238               op0 = XEXP (op0, 1);
10239               code = (code == GE ? GT : LE);
10240               continue;
10241             }
10242           break;
10243
10244         case AND:
10245           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
10246              will be converted to a ZERO_EXTRACT later.  */
10247           if (const_op == 0 && equality_comparison_p
10248               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10249               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10250             {
10251               op0 = simplify_and_const_int
10252                 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10253                                                    XEXP (op0, 1),
10254                                                    XEXP (XEXP (op0, 0), 1)),
10255                  (HOST_WIDE_INT) 1);
10256               continue;
10257             }
10258
10259           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10260              zero and X is a comparison and C1 and C2 describe only bits set
10261              in STORE_FLAG_VALUE, we can compare with X.  */
10262           if (const_op == 0 && equality_comparison_p
10263               && mode_width <= HOST_BITS_PER_WIDE_INT
10264               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10265               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10266               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10267               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10268               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10269             {
10270               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10271                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
10272               if ((~STORE_FLAG_VALUE & mask) == 0
10273                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10274                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10275                           && COMPARISON_P (tem))))
10276                 {
10277                   op0 = XEXP (XEXP (op0, 0), 0);
10278                   continue;
10279                 }
10280             }
10281
10282           /* If we are doing an equality comparison of an AND of a bit equal
10283              to the sign bit, replace this with a LT or GE comparison of
10284              the underlying value.  */
10285           if (equality_comparison_p
10286               && const_op == 0
10287               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10288               && mode_width <= HOST_BITS_PER_WIDE_INT
10289               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10290                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10291             {
10292               op0 = XEXP (op0, 0);
10293               code = (code == EQ ? GE : LT);
10294               continue;
10295             }
10296
10297           /* If this AND operation is really a ZERO_EXTEND from a narrower
10298              mode, the constant fits within that mode, and this is either an
10299              equality or unsigned comparison, try to do this comparison in
10300              the narrower mode.
10301
10302              Note that in:
10303
10304              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10305              -> (ne:DI (reg:SI 4) (const_int 0))
10306
10307              unless TRULY_NOOP_TRUNCATION allows it or the register is
10308              known to hold a value of the required mode the
10309              transformation is invalid.  */
10310           if ((equality_comparison_p || unsigned_comparison_p)
10311               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10312               && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10313                                    & GET_MODE_MASK (mode))
10314                                   + 1)) >= 0
10315               && const_op >> i == 0
10316               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10317               && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10318                                          GET_MODE_BITSIZE (GET_MODE (op0)))
10319                   || (REG_P (XEXP (op0, 0))
10320                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10321             {
10322               op0 = gen_lowpart (tmode, XEXP (op0, 0));
10323               continue;
10324             }
10325
10326           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10327              fits in both M1 and M2 and the SUBREG is either paradoxical
10328              or represents the low part, permute the SUBREG and the AND
10329              and try again.  */
10330           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10331             {
10332               unsigned HOST_WIDE_INT c1;
10333               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10334               /* Require an integral mode, to avoid creating something like
10335                  (AND:SF ...).  */
10336               if (SCALAR_INT_MODE_P (tmode)
10337                   /* It is unsafe to commute the AND into the SUBREG if the
10338                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10339                      not defined.  As originally written the upper bits
10340                      have a defined value due to the AND operation.
10341                      However, if we commute the AND inside the SUBREG then
10342                      they no longer have defined values and the meaning of
10343                      the code has been changed.  */
10344                   && (0
10345 #ifdef WORD_REGISTER_OPERATIONS
10346                       || (mode_width > GET_MODE_BITSIZE (tmode)
10347                           && mode_width <= BITS_PER_WORD)
10348 #endif
10349                       || (mode_width <= GET_MODE_BITSIZE (tmode)
10350                           && subreg_lowpart_p (XEXP (op0, 0))))
10351                   && GET_CODE (XEXP (op0, 1)) == CONST_INT
10352                   && mode_width <= HOST_BITS_PER_WIDE_INT
10353                   && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10354                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10355                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
10356                   && c1 != mask
10357                   && c1 != GET_MODE_MASK (tmode))
10358                 {
10359                   op0 = simplify_gen_binary (AND, tmode,
10360                                              SUBREG_REG (XEXP (op0, 0)),
10361                                              gen_int_mode (c1, tmode));
10362                   op0 = gen_lowpart (mode, op0);
10363                   continue;
10364                 }
10365             }
10366
10367           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
10368           if (const_op == 0 && equality_comparison_p
10369               && XEXP (op0, 1) == const1_rtx
10370               && GET_CODE (XEXP (op0, 0)) == NOT)
10371             {
10372               op0 = simplify_and_const_int
10373                 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10374               code = (code == NE ? EQ : NE);
10375               continue;
10376             }
10377
10378           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10379              (eq (and (lshiftrt X) 1) 0).
10380              Also handle the case where (not X) is expressed using xor.  */
10381           if (const_op == 0 && equality_comparison_p
10382               && XEXP (op0, 1) == const1_rtx
10383               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10384             {
10385               rtx shift_op = XEXP (XEXP (op0, 0), 0);
10386               rtx shift_count = XEXP (XEXP (op0, 0), 1);
10387
10388               if (GET_CODE (shift_op) == NOT
10389                   || (GET_CODE (shift_op) == XOR
10390                       && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10391                       && GET_CODE (shift_count) == CONST_INT
10392                       && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10393                       && (INTVAL (XEXP (shift_op, 1))
10394                           == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10395                 {
10396                   op0 = simplify_and_const_int
10397                     (NULL_RTX, mode,
10398                      gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10399                      (HOST_WIDE_INT) 1);
10400                   code = (code == NE ? EQ : NE);
10401                   continue;
10402                 }
10403             }
10404           break;
10405
10406         case ASHIFT:
10407           /* If we have (compare (ashift FOO N) (const_int C)) and
10408              the high order N bits of FOO (N+1 if an inequality comparison)
10409              are known to be zero, we can do this by comparing FOO with C
10410              shifted right N bits so long as the low-order N bits of C are
10411              zero.  */
10412           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10413               && INTVAL (XEXP (op0, 1)) >= 0
10414               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10415                   < HOST_BITS_PER_WIDE_INT)
10416               && ((const_op
10417                    & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10418               && mode_width <= HOST_BITS_PER_WIDE_INT
10419               && (nonzero_bits (XEXP (op0, 0), mode)
10420                   & ~(mask >> (INTVAL (XEXP (op0, 1))
10421                                + ! equality_comparison_p))) == 0)
10422             {
10423               /* We must perform a logical shift, not an arithmetic one,
10424                  as we want the top N bits of C to be zero.  */
10425               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10426
10427               temp >>= INTVAL (XEXP (op0, 1));
10428               op1 = gen_int_mode (temp, mode);
10429               op0 = XEXP (op0, 0);
10430               continue;
10431             }
10432
10433           /* If we are doing a sign bit comparison, it means we are testing
10434              a particular bit.  Convert it to the appropriate AND.  */
10435           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10436               && mode_width <= HOST_BITS_PER_WIDE_INT)
10437             {
10438               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10439                                             ((HOST_WIDE_INT) 1
10440                                              << (mode_width - 1
10441                                                  - INTVAL (XEXP (op0, 1)))));
10442               code = (code == LT ? NE : EQ);
10443               continue;
10444             }
10445
10446           /* If this an equality comparison with zero and we are shifting
10447              the low bit to the sign bit, we can convert this to an AND of the
10448              low-order bit.  */
10449           if (const_op == 0 && equality_comparison_p
10450               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10451               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10452                  == mode_width - 1)
10453             {
10454               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10455                                             (HOST_WIDE_INT) 1);
10456               continue;
10457             }
10458           break;
10459
10460         case ASHIFTRT:
10461           /* If this is an equality comparison with zero, we can do this
10462              as a logical shift, which might be much simpler.  */
10463           if (equality_comparison_p && const_op == 0
10464               && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10465             {
10466               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10467                                           XEXP (op0, 0),
10468                                           INTVAL (XEXP (op0, 1)));
10469               continue;
10470             }
10471
10472           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10473              do the comparison in a narrower mode.  */
10474           if (! unsigned_comparison_p
10475               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476               && GET_CODE (XEXP (op0, 0)) == ASHIFT
10477               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10478               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10479                                          MODE_INT, 1)) != BLKmode
10480               && (((unsigned HOST_WIDE_INT) const_op
10481                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10482                   <= GET_MODE_MASK (tmode)))
10483             {
10484               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10485               continue;
10486             }
10487
10488           /* Likewise if OP0 is a PLUS of a sign extension with a
10489              constant, which is usually represented with the PLUS
10490              between the shifts.  */
10491           if (! unsigned_comparison_p
10492               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10493               && GET_CODE (XEXP (op0, 0)) == PLUS
10494               && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10495               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10496               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10497               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10498                                          MODE_INT, 1)) != BLKmode
10499               && (((unsigned HOST_WIDE_INT) const_op
10500                    + (GET_MODE_MASK (tmode) >> 1) + 1)
10501                   <= GET_MODE_MASK (tmode)))
10502             {
10503               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10504               rtx add_const = XEXP (XEXP (op0, 0), 1);
10505               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10506                                                    add_const, XEXP (op0, 1));
10507
10508               op0 = simplify_gen_binary (PLUS, tmode,
10509                                          gen_lowpart (tmode, inner),
10510                                          new_const);
10511               continue;
10512             }
10513
10514           /* ... fall through ...  */
10515         case LSHIFTRT:
10516           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10517              the low order N bits of FOO are known to be zero, we can do this
10518              by comparing FOO with C shifted left N bits so long as no
10519              overflow occurs.  */
10520           if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10521               && INTVAL (XEXP (op0, 1)) >= 0
10522               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10523               && mode_width <= HOST_BITS_PER_WIDE_INT
10524               && (nonzero_bits (XEXP (op0, 0), mode)
10525                   & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10526               && (((unsigned HOST_WIDE_INT) const_op
10527                    + (GET_CODE (op0) != LSHIFTRT
10528                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10529                          + 1)
10530                       : 0))
10531                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10532             {
10533               /* If the shift was logical, then we must make the condition
10534                  unsigned.  */
10535               if (GET_CODE (op0) == LSHIFTRT)
10536                 code = unsigned_condition (code);
10537
10538               const_op <<= INTVAL (XEXP (op0, 1));
10539               op1 = GEN_INT (const_op);
10540               op0 = XEXP (op0, 0);
10541               continue;
10542             }
10543
10544           /* If we are using this shift to extract just the sign bit, we
10545              can replace this with an LT or GE comparison.  */
10546           if (const_op == 0
10547               && (equality_comparison_p || sign_bit_comparison_p)
10548               && GET_CODE (XEXP (op0, 1)) == CONST_INT
10549               && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10550                  == mode_width - 1)
10551             {
10552               op0 = XEXP (op0, 0);
10553               code = (code == NE || code == GT ? LT : GE);
10554               continue;
10555             }
10556           break;
10557
10558         default:
10559           break;
10560         }
10561
10562       break;
10563     }
10564
10565   /* Now make any compound operations involved in this comparison.  Then,
10566      check for an outmost SUBREG on OP0 that is not doing anything or is
10567      paradoxical.  The latter transformation must only be performed when
10568      it is known that the "extra" bits will be the same in op0 and op1 or
10569      that they don't matter.  There are three cases to consider:
10570
10571      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
10572      care bits and we can assume they have any convenient value.  So
10573      making the transformation is safe.
10574
10575      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10576      In this case the upper bits of op0 are undefined.  We should not make
10577      the simplification in that case as we do not know the contents of
10578      those bits.
10579
10580      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10581      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
10582      also be sure that they are the same as the upper bits of op1.
10583
10584      We can never remove a SUBREG for a non-equality comparison because
10585      the sign bit is in a different place in the underlying object.  */
10586
10587   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10588   op1 = make_compound_operation (op1, SET);
10589
10590   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10591       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10592       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10593       && (code == NE || code == EQ))
10594     {
10595       if (GET_MODE_SIZE (GET_MODE (op0))
10596           > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10597         {
10598           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
10599              implemented.  */
10600           if (REG_P (SUBREG_REG (op0)))
10601             {
10602               op0 = SUBREG_REG (op0);
10603               op1 = gen_lowpart (GET_MODE (op0), op1);
10604             }
10605         }
10606       else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10607                 <= HOST_BITS_PER_WIDE_INT)
10608                && (nonzero_bits (SUBREG_REG (op0),
10609                                  GET_MODE (SUBREG_REG (op0)))
10610                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10611         {
10612           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10613
10614           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10615                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10616             op0 = SUBREG_REG (op0), op1 = tem;
10617         }
10618     }
10619
10620   /* We now do the opposite procedure: Some machines don't have compare
10621      insns in all modes.  If OP0's mode is an integer mode smaller than a
10622      word and we can't do a compare in that mode, see if there is a larger
10623      mode for which we can do the compare.  There are a number of cases in
10624      which we can use the wider mode.  */
10625
10626   mode = GET_MODE (op0);
10627   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10628       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10629       && ! have_insn_for (COMPARE, mode))
10630     for (tmode = GET_MODE_WIDER_MODE (mode);
10631          (tmode != VOIDmode
10632           && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10633          tmode = GET_MODE_WIDER_MODE (tmode))
10634       if (have_insn_for (COMPARE, tmode))
10635         {
10636           int zero_extended;
10637
10638           /* If the only nonzero bits in OP0 and OP1 are those in the
10639              narrower mode and this is an equality or unsigned comparison,
10640              we can use the wider mode.  Similarly for sign-extended
10641              values, in which case it is true for all comparisons.  */
10642           zero_extended = ((code == EQ || code == NE
10643                             || code == GEU || code == GTU
10644                             || code == LEU || code == LTU)
10645                            && (nonzero_bits (op0, tmode)
10646                                & ~GET_MODE_MASK (mode)) == 0
10647                            && ((GET_CODE (op1) == CONST_INT
10648                                 || (nonzero_bits (op1, tmode)
10649                                     & ~GET_MODE_MASK (mode)) == 0)));
10650
10651           if (zero_extended
10652               || ((num_sign_bit_copies (op0, tmode)
10653                    > (unsigned int) (GET_MODE_BITSIZE (tmode)
10654                                      - GET_MODE_BITSIZE (mode)))
10655                   && (num_sign_bit_copies (op1, tmode)
10656                       > (unsigned int) (GET_MODE_BITSIZE (tmode)
10657                                         - GET_MODE_BITSIZE (mode)))))
10658             {
10659               /* If OP0 is an AND and we don't have an AND in MODE either,
10660                  make a new AND in the proper mode.  */
10661               if (GET_CODE (op0) == AND
10662                   && !have_insn_for (AND, mode))
10663                 op0 = simplify_gen_binary (AND, tmode,
10664                                            gen_lowpart (tmode,
10665                                                         XEXP (op0, 0)),
10666                                            gen_lowpart (tmode,
10667                                                         XEXP (op0, 1)));
10668
10669               op0 = gen_lowpart (tmode, op0);
10670               if (zero_extended && GET_CODE (op1) == CONST_INT)
10671                 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10672               op1 = gen_lowpart (tmode, op1);
10673               break;
10674             }
10675
10676           /* If this is a test for negative, we can make an explicit
10677              test of the sign bit.  */
10678
10679           if (op1 == const0_rtx && (code == LT || code == GE)
10680               && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10681             {
10682               op0 = simplify_gen_binary (AND, tmode,
10683                                          gen_lowpart (tmode, op0),
10684                                          GEN_INT ((HOST_WIDE_INT) 1
10685                                                   << (GET_MODE_BITSIZE (mode)
10686                                                       - 1)));
10687               code = (code == LT) ? NE : EQ;
10688               break;
10689             }
10690         }
10691
10692 #ifdef CANONICALIZE_COMPARISON
10693   /* If this machine only supports a subset of valid comparisons, see if we
10694      can convert an unsupported one into a supported one.  */
10695   CANONICALIZE_COMPARISON (code, op0, op1);
10696 #endif
10697
10698   *pop0 = op0;
10699   *pop1 = op1;
10700
10701   return code;
10702 }
10703 \f
10704 /* Utility function for record_value_for_reg.  Count number of
10705    rtxs in X.  */
10706 static int
10707 count_rtxs (rtx x)
10708 {
10709   enum rtx_code code = GET_CODE (x);
10710   const char *fmt;
10711   int i, ret = 1;
10712
10713   if (GET_RTX_CLASS (code) == '2'
10714       || GET_RTX_CLASS (code) == 'c')
10715     {
10716       rtx x0 = XEXP (x, 0);
10717       rtx x1 = XEXP (x, 1);
10718
10719       if (x0 == x1)
10720         return 1 + 2 * count_rtxs (x0);
10721
10722       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10723            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10724           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10725         return 2 + 2 * count_rtxs (x0)
10726                + count_rtxs (x == XEXP (x1, 0)
10727                              ? XEXP (x1, 1) : XEXP (x1, 0));
10728
10729       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10730            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10731           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10732         return 2 + 2 * count_rtxs (x1)
10733                + count_rtxs (x == XEXP (x0, 0)
10734                              ? XEXP (x0, 1) : XEXP (x0, 0));
10735     }
10736
10737   fmt = GET_RTX_FORMAT (code);
10738   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10739     if (fmt[i] == 'e')
10740       ret += count_rtxs (XEXP (x, i));
10741
10742   return ret;
10743 }
10744 \f
10745 /* Utility function for following routine.  Called when X is part of a value
10746    being stored into last_set_value.  Sets last_set_table_tick
10747    for each register mentioned.  Similar to mention_regs in cse.c  */
10748
10749 static void
10750 update_table_tick (rtx x)
10751 {
10752   enum rtx_code code = GET_CODE (x);
10753   const char *fmt = GET_RTX_FORMAT (code);
10754   int i;
10755
10756   if (code == REG)
10757     {
10758       unsigned int regno = REGNO (x);
10759       unsigned int endregno
10760         = regno + (regno < FIRST_PSEUDO_REGISTER
10761                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10762       unsigned int r;
10763
10764       for (r = regno; r < endregno; r++)
10765         reg_stat[r].last_set_table_tick = label_tick;
10766
10767       return;
10768     }
10769
10770   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10771     /* Note that we can't have an "E" in values stored; see
10772        get_last_value_validate.  */
10773     if (fmt[i] == 'e')
10774       {
10775         /* Check for identical subexpressions.  If x contains
10776            identical subexpression we only have to traverse one of
10777            them.  */
10778         if (i == 0 && ARITHMETIC_P (x))
10779           {
10780             /* Note that at this point x1 has already been
10781                processed.  */
10782             rtx x0 = XEXP (x, 0);
10783             rtx x1 = XEXP (x, 1);
10784
10785             /* If x0 and x1 are identical then there is no need to
10786                process x0.  */
10787             if (x0 == x1)
10788               break;
10789
10790             /* If x0 is identical to a subexpression of x1 then while
10791                processing x1, x0 has already been processed.  Thus we
10792                are done with x.  */
10793             if (ARITHMETIC_P (x1)
10794                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10795               break;
10796
10797             /* If x1 is identical to a subexpression of x0 then we
10798                still have to process the rest of x0.  */
10799             if (ARITHMETIC_P (x0)
10800                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10801               {
10802                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10803                 break;
10804               }
10805           }
10806
10807         update_table_tick (XEXP (x, i));
10808       }
10809 }
10810
10811 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
10812    are saying that the register is clobbered and we no longer know its
10813    value.  If INSN is zero, don't update reg_stat[].last_set; this is
10814    only permitted with VALUE also zero and is used to invalidate the
10815    register.  */
10816
10817 static void
10818 record_value_for_reg (rtx reg, rtx insn, rtx value)
10819 {
10820   unsigned int regno = REGNO (reg);
10821   unsigned int endregno
10822     = regno + (regno < FIRST_PSEUDO_REGISTER
10823                ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10824   unsigned int i;
10825
10826   /* If VALUE contains REG and we have a previous value for REG, substitute
10827      the previous value.  */
10828   if (value && insn && reg_overlap_mentioned_p (reg, value))
10829     {
10830       rtx tem;
10831
10832       /* Set things up so get_last_value is allowed to see anything set up to
10833          our insn.  */
10834       subst_low_cuid = INSN_CUID (insn);
10835       tem = get_last_value (reg);
10836
10837       /* If TEM is simply a binary operation with two CLOBBERs as operands,
10838          it isn't going to be useful and will take a lot of time to process,
10839          so just use the CLOBBER.  */
10840
10841       if (tem)
10842         {
10843           if (ARITHMETIC_P (tem)
10844               && GET_CODE (XEXP (tem, 0)) == CLOBBER
10845               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10846             tem = XEXP (tem, 0);
10847           else if (count_occurrences (value, reg, 1) >= 2)
10848             {
10849               /* If there are two or more occurrences of REG in VALUE,
10850                  prevent the value from growing too much.  */
10851               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10852                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10853             }
10854
10855           value = replace_rtx (copy_rtx (value), reg, tem);
10856         }
10857     }
10858
10859   /* For each register modified, show we don't know its value, that
10860      we don't know about its bitwise content, that its value has been
10861      updated, and that we don't know the location of the death of the
10862      register.  */
10863   for (i = regno; i < endregno; i++)
10864     {
10865       if (insn)
10866         reg_stat[i].last_set = insn;
10867
10868       reg_stat[i].last_set_value = 0;
10869       reg_stat[i].last_set_mode = 0;
10870       reg_stat[i].last_set_nonzero_bits = 0;
10871       reg_stat[i].last_set_sign_bit_copies = 0;
10872       reg_stat[i].last_death = 0;
10873       reg_stat[i].truncated_to_mode = 0;
10874     }
10875
10876   /* Mark registers that are being referenced in this value.  */
10877   if (value)
10878     update_table_tick (value);
10879
10880   /* Now update the status of each register being set.
10881      If someone is using this register in this block, set this register
10882      to invalid since we will get confused between the two lives in this
10883      basic block.  This makes using this register always invalid.  In cse, we
10884      scan the table to invalidate all entries using this register, but this
10885      is too much work for us.  */
10886
10887   for (i = regno; i < endregno; i++)
10888     {
10889       reg_stat[i].last_set_label = label_tick;
10890       if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10891         reg_stat[i].last_set_invalid = 1;
10892       else
10893         reg_stat[i].last_set_invalid = 0;
10894     }
10895
10896   /* The value being assigned might refer to X (like in "x++;").  In that
10897      case, we must replace it with (clobber (const_int 0)) to prevent
10898      infinite loops.  */
10899   if (value && ! get_last_value_validate (&value, insn,
10900                                           reg_stat[regno].last_set_label, 0))
10901     {
10902       value = copy_rtx (value);
10903       if (! get_last_value_validate (&value, insn,
10904                                      reg_stat[regno].last_set_label, 1))
10905         value = 0;
10906     }
10907
10908   /* For the main register being modified, update the value, the mode, the
10909      nonzero bits, and the number of sign bit copies.  */
10910
10911   reg_stat[regno].last_set_value = value;
10912
10913   if (value)
10914     {
10915       enum machine_mode mode = GET_MODE (reg);
10916       subst_low_cuid = INSN_CUID (insn);
10917       reg_stat[regno].last_set_mode = mode;
10918       if (GET_MODE_CLASS (mode) == MODE_INT
10919           && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10920         mode = nonzero_bits_mode;
10921       reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10922       reg_stat[regno].last_set_sign_bit_copies
10923         = num_sign_bit_copies (value, GET_MODE (reg));
10924     }
10925 }
10926
10927 /* Called via note_stores from record_dead_and_set_regs to handle one
10928    SET or CLOBBER in an insn.  DATA is the instruction in which the
10929    set is occurring.  */
10930
10931 static void
10932 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10933 {
10934   rtx record_dead_insn = (rtx) data;
10935
10936   if (GET_CODE (dest) == SUBREG)
10937     dest = SUBREG_REG (dest);
10938
10939   if (!record_dead_insn)
10940     {
10941       if (REG_P (dest))
10942         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10943       return;
10944     }
10945
10946   if (REG_P (dest))
10947     {
10948       /* If we are setting the whole register, we know its value.  Otherwise
10949          show that we don't know the value.  We can handle SUBREG in
10950          some cases.  */
10951       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10952         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10953       else if (GET_CODE (setter) == SET
10954                && GET_CODE (SET_DEST (setter)) == SUBREG
10955                && SUBREG_REG (SET_DEST (setter)) == dest
10956                && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10957                && subreg_lowpart_p (SET_DEST (setter)))
10958         record_value_for_reg (dest, record_dead_insn,
10959                               gen_lowpart (GET_MODE (dest),
10960                                                        SET_SRC (setter)));
10961       else
10962         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10963     }
10964   else if (MEM_P (dest)
10965            /* Ignore pushes, they clobber nothing.  */
10966            && ! push_operand (dest, GET_MODE (dest)))
10967     mem_last_set = INSN_CUID (record_dead_insn);
10968 }
10969
10970 /* Update the records of when each REG was most recently set or killed
10971    for the things done by INSN.  This is the last thing done in processing
10972    INSN in the combiner loop.
10973
10974    We update reg_stat[], in particular fields last_set, last_set_value,
10975    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10976    last_death, and also the similar information mem_last_set (which insn
10977    most recently modified memory) and last_call_cuid (which insn was the
10978    most recent subroutine call).  */
10979
10980 static void
10981 record_dead_and_set_regs (rtx insn)
10982 {
10983   rtx link;
10984   unsigned int i;
10985
10986   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10987     {
10988       if (REG_NOTE_KIND (link) == REG_DEAD
10989           && REG_P (XEXP (link, 0)))
10990         {
10991           unsigned int regno = REGNO (XEXP (link, 0));
10992           unsigned int endregno
10993             = regno + (regno < FIRST_PSEUDO_REGISTER
10994                        ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10995                        : 1);
10996
10997           for (i = regno; i < endregno; i++)
10998             reg_stat[i].last_death = insn;
10999         }
11000       else if (REG_NOTE_KIND (link) == REG_INC)
11001         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11002     }
11003
11004   if (CALL_P (insn))
11005     {
11006       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11007         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11008           {
11009             reg_stat[i].last_set_value = 0;
11010             reg_stat[i].last_set_mode = 0;
11011             reg_stat[i].last_set_nonzero_bits = 0;
11012             reg_stat[i].last_set_sign_bit_copies = 0;
11013             reg_stat[i].last_death = 0;
11014             reg_stat[i].truncated_to_mode = 0;
11015           }
11016
11017       last_call_cuid = mem_last_set = INSN_CUID (insn);
11018
11019       /* We can't combine into a call pattern.  Remember, though, that
11020          the return value register is set at this CUID.  We could
11021          still replace a register with the return value from the
11022          wrong subroutine call!  */
11023       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11024     }
11025   else
11026     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11027 }
11028
11029 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11030    register present in the SUBREG, so for each such SUBREG go back and
11031    adjust nonzero and sign bit information of the registers that are
11032    known to have some zero/sign bits set.
11033
11034    This is needed because when combine blows the SUBREGs away, the
11035    information on zero/sign bits is lost and further combines can be
11036    missed because of that.  */
11037
11038 static void
11039 record_promoted_value (rtx insn, rtx subreg)
11040 {
11041   rtx links, set;
11042   unsigned int regno = REGNO (SUBREG_REG (subreg));
11043   enum machine_mode mode = GET_MODE (subreg);
11044
11045   if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11046     return;
11047
11048   for (links = LOG_LINKS (insn); links;)
11049     {
11050       insn = XEXP (links, 0);
11051       set = single_set (insn);
11052
11053       if (! set || !REG_P (SET_DEST (set))
11054           || REGNO (SET_DEST (set)) != regno
11055           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11056         {
11057           links = XEXP (links, 1);
11058           continue;
11059         }
11060
11061       if (reg_stat[regno].last_set == insn)
11062         {
11063           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11064             reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11065         }
11066
11067       if (REG_P (SET_SRC (set)))
11068         {
11069           regno = REGNO (SET_SRC (set));
11070           links = LOG_LINKS (insn);
11071         }
11072       else
11073         break;
11074     }
11075 }
11076
11077 /* Check if X, a register, is known to contain a value already
11078    truncated to MODE.  In this case we can use a subreg to refer to
11079    the truncated value even though in the generic case we would need
11080    an explicit truncation.  */
11081
11082 static bool
11083 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11084 {
11085   enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11086
11087   if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11088     return false;
11089   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11090     return true;
11091   if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11092                              GET_MODE_BITSIZE (truncated)))
11093     return true;
11094   return false;
11095 }
11096
11097 /* X is a REG or a SUBREG.  If X is some sort of a truncation record
11098    it.  For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11099    a truncate into a subreg using this information.  */
11100
11101 static void
11102 record_truncated_value (rtx x)
11103 {
11104   enum machine_mode truncated_mode;
11105
11106   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11107     {
11108       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11109       truncated_mode = GET_MODE (x);
11110
11111       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11112         return;
11113
11114       if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11115                                  GET_MODE_BITSIZE (original_mode)))
11116         return;
11117
11118       x = SUBREG_REG (x);
11119     }
11120   /* ??? For hard-regs we now record everything.  We might be able to
11121      optimize this using last_set_mode.  */
11122   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11123     truncated_mode = GET_MODE (x);
11124   else
11125     return;
11126
11127   if (reg_stat[REGNO (x)].truncated_to_mode == 0
11128       || reg_stat[REGNO (x)].truncation_label < label_tick
11129       || (GET_MODE_SIZE (truncated_mode)
11130           < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11131     {
11132       reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11133       reg_stat[REGNO (x)].truncation_label = label_tick;
11134     }
11135 }
11136
11137 /* Scan X for promoted SUBREGs and truncated REGs.  For each one
11138    found, note what it implies to the registers used in it.  */
11139
11140 static void
11141 check_conversions (rtx insn, rtx x)
11142 {
11143   if (GET_CODE (x) == SUBREG || REG_P (x))
11144     {
11145       if (GET_CODE (x) == SUBREG
11146           && SUBREG_PROMOTED_VAR_P (x)
11147           && REG_P (SUBREG_REG (x)))
11148         record_promoted_value (insn, x);
11149
11150       record_truncated_value (x);
11151     }
11152   else
11153     {
11154       const char *format = GET_RTX_FORMAT (GET_CODE (x));
11155       int i, j;
11156
11157       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11158         switch (format[i])
11159           {
11160           case 'e':
11161             check_conversions (insn, XEXP (x, i));
11162             break;
11163           case 'V':
11164           case 'E':
11165             if (XVEC (x, i) != 0)
11166               for (j = 0; j < XVECLEN (x, i); j++)
11167                 check_conversions (insn, XVECEXP (x, i, j));
11168             break;
11169           }
11170     }
11171 }
11172 \f
11173 /* Utility routine for the following function.  Verify that all the registers
11174    mentioned in *LOC are valid when *LOC was part of a value set when
11175    label_tick == TICK.  Return 0 if some are not.
11176
11177    If REPLACE is nonzero, replace the invalid reference with
11178    (clobber (const_int 0)) and return 1.  This replacement is useful because
11179    we often can get useful information about the form of a value (e.g., if
11180    it was produced by a shift that always produces -1 or 0) even though
11181    we don't know exactly what registers it was produced from.  */
11182
11183 static int
11184 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11185 {
11186   rtx x = *loc;
11187   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11188   int len = GET_RTX_LENGTH (GET_CODE (x));
11189   int i;
11190
11191   if (REG_P (x))
11192     {
11193       unsigned int regno = REGNO (x);
11194       unsigned int endregno
11195         = regno + (regno < FIRST_PSEUDO_REGISTER
11196                    ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11197       unsigned int j;
11198
11199       for (j = regno; j < endregno; j++)
11200         if (reg_stat[j].last_set_invalid
11201             /* If this is a pseudo-register that was only set once and not
11202                live at the beginning of the function, it is always valid.  */
11203             || (! (regno >= FIRST_PSEUDO_REGISTER
11204                    && REG_N_SETS (regno) == 1
11205                    && (! REGNO_REG_SET_P
11206                        (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11207                         regno)))
11208                 && reg_stat[j].last_set_label > tick))
11209           {
11210             if (replace)
11211               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11212             return replace;
11213           }
11214
11215       return 1;
11216     }
11217   /* If this is a memory reference, make sure that there were
11218      no stores after it that might have clobbered the value.  We don't
11219      have alias info, so we assume any store invalidates it.  */
11220   else if (MEM_P (x) && !MEM_READONLY_P (x)
11221            && INSN_CUID (insn) <= mem_last_set)
11222     {
11223       if (replace)
11224         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11225       return replace;
11226     }
11227
11228   for (i = 0; i < len; i++)
11229     {
11230       if (fmt[i] == 'e')
11231         {
11232           /* Check for identical subexpressions.  If x contains
11233              identical subexpression we only have to traverse one of
11234              them.  */
11235           if (i == 1 && ARITHMETIC_P (x))
11236             {
11237               /* Note that at this point x0 has already been checked
11238                  and found valid.  */
11239               rtx x0 = XEXP (x, 0);
11240               rtx x1 = XEXP (x, 1);
11241
11242               /* If x0 and x1 are identical then x is also valid.  */
11243               if (x0 == x1)
11244                 return 1;
11245
11246               /* If x1 is identical to a subexpression of x0 then
11247                  while checking x0, x1 has already been checked.  Thus
11248                  it is valid and so as x.  */
11249               if (ARITHMETIC_P (x0)
11250                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11251                 return 1;
11252
11253               /* If x0 is identical to a subexpression of x1 then x is
11254                  valid iff the rest of x1 is valid.  */
11255               if (ARITHMETIC_P (x1)
11256                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11257                 return
11258                   get_last_value_validate (&XEXP (x1,
11259                                                   x0 == XEXP (x1, 0) ? 1 : 0),
11260                                            insn, tick, replace);
11261             }
11262
11263           if (get_last_value_validate (&XEXP (x, i), insn, tick,
11264                                        replace) == 0)
11265             return 0;
11266         }
11267       /* Don't bother with these.  They shouldn't occur anyway.  */
11268       else if (fmt[i] == 'E')
11269         return 0;
11270     }
11271
11272   /* If we haven't found a reason for it to be invalid, it is valid.  */
11273   return 1;
11274 }
11275
11276 /* Get the last value assigned to X, if known.  Some registers
11277    in the value may be replaced with (clobber (const_int 0)) if their value
11278    is known longer known reliably.  */
11279
11280 static rtx
11281 get_last_value (rtx x)
11282 {
11283   unsigned int regno;
11284   rtx value;
11285
11286   /* If this is a non-paradoxical SUBREG, get the value of its operand and
11287      then convert it to the desired mode.  If this is a paradoxical SUBREG,
11288      we cannot predict what values the "extra" bits might have.  */
11289   if (GET_CODE (x) == SUBREG
11290       && subreg_lowpart_p (x)
11291       && (GET_MODE_SIZE (GET_MODE (x))
11292           <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11293       && (value = get_last_value (SUBREG_REG (x))) != 0)
11294     return gen_lowpart (GET_MODE (x), value);
11295
11296   if (!REG_P (x))
11297     return 0;
11298
11299   regno = REGNO (x);
11300   value = reg_stat[regno].last_set_value;
11301
11302   /* If we don't have a value, or if it isn't for this basic block and
11303      it's either a hard register, set more than once, or it's a live
11304      at the beginning of the function, return 0.
11305
11306      Because if it's not live at the beginning of the function then the reg
11307      is always set before being used (is never used without being set).
11308      And, if it's set only once, and it's always set before use, then all
11309      uses must have the same last value, even if it's not from this basic
11310      block.  */
11311
11312   if (value == 0
11313       || (reg_stat[regno].last_set_label != label_tick
11314           && (regno < FIRST_PSEUDO_REGISTER
11315               || REG_N_SETS (regno) != 1
11316               || (REGNO_REG_SET_P
11317                   (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11318                    regno)))))
11319     return 0;
11320
11321   /* If the value was set in a later insn than the ones we are processing,
11322      we can't use it even if the register was only set once.  */
11323   if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11324     return 0;
11325
11326   /* If the value has all its registers valid, return it.  */
11327   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11328                                reg_stat[regno].last_set_label, 0))
11329     return value;
11330
11331   /* Otherwise, make a copy and replace any invalid register with
11332      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
11333
11334   value = copy_rtx (value);
11335   if (get_last_value_validate (&value, reg_stat[regno].last_set,
11336                                reg_stat[regno].last_set_label, 1))
11337     return value;
11338
11339   return 0;
11340 }
11341 \f
11342 /* Return nonzero if expression X refers to a REG or to memory
11343    that is set in an instruction more recent than FROM_CUID.  */
11344
11345 static int
11346 use_crosses_set_p (rtx x, int from_cuid)
11347 {
11348   const char *fmt;
11349   int i;
11350   enum rtx_code code = GET_CODE (x);
11351
11352   if (code == REG)
11353     {
11354       unsigned int regno = REGNO (x);
11355       unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11356                                  ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11357
11358 #ifdef PUSH_ROUNDING
11359       /* Don't allow uses of the stack pointer to be moved,
11360          because we don't know whether the move crosses a push insn.  */
11361       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11362         return 1;
11363 #endif
11364       for (; regno < endreg; regno++)
11365         if (reg_stat[regno].last_set
11366             && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11367           return 1;
11368       return 0;
11369     }
11370
11371   if (code == MEM && mem_last_set > from_cuid)
11372     return 1;
11373
11374   fmt = GET_RTX_FORMAT (code);
11375
11376   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11377     {
11378       if (fmt[i] == 'E')
11379         {
11380           int j;
11381           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11382             if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11383               return 1;
11384         }
11385       else if (fmt[i] == 'e'
11386                && use_crosses_set_p (XEXP (x, i), from_cuid))
11387         return 1;
11388     }
11389   return 0;
11390 }
11391 \f
11392 /* Define three variables used for communication between the following
11393    routines.  */
11394
11395 static unsigned int reg_dead_regno, reg_dead_endregno;
11396 static int reg_dead_flag;
11397
11398 /* Function called via note_stores from reg_dead_at_p.
11399
11400    If DEST is within [reg_dead_regno, reg_dead_endregno), set
11401    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
11402
11403 static void
11404 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11405 {
11406   unsigned int regno, endregno;
11407
11408   if (!REG_P (dest))
11409     return;
11410
11411   regno = REGNO (dest);
11412   endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11413                       ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11414
11415   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11416     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11417 }
11418
11419 /* Return nonzero if REG is known to be dead at INSN.
11420
11421    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
11422    referencing REG, it is dead.  If we hit a SET referencing REG, it is
11423    live.  Otherwise, see if it is live or dead at the start of the basic
11424    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
11425    must be assumed to be always live.  */
11426
11427 static int
11428 reg_dead_at_p (rtx reg, rtx insn)
11429 {
11430   basic_block block;
11431   unsigned int i;
11432
11433   /* Set variables for reg_dead_at_p_1.  */
11434   reg_dead_regno = REGNO (reg);
11435   reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11436                                         ? hard_regno_nregs[reg_dead_regno]
11437                                                           [GET_MODE (reg)]
11438                                         : 1);
11439
11440   reg_dead_flag = 0;
11441
11442   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
11443      we allow the machine description to decide whether use-and-clobber
11444      patterns are OK.  */
11445   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11446     {
11447       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11448         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11449           return 0;
11450     }
11451
11452   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11453      beginning of function.  */
11454   for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11455        insn = prev_nonnote_insn (insn))
11456     {
11457       note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11458       if (reg_dead_flag)
11459         return reg_dead_flag == 1 ? 1 : 0;
11460
11461       if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11462         return 1;
11463     }
11464
11465   /* Get the basic block that we were in.  */
11466   if (insn == 0)
11467     block = ENTRY_BLOCK_PTR->next_bb;
11468   else
11469     {
11470       FOR_EACH_BB (block)
11471         if (insn == BB_HEAD (block))
11472           break;
11473
11474       if (block == EXIT_BLOCK_PTR)
11475         return 0;
11476     }
11477
11478   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11479     if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11480       return 0;
11481
11482   return 1;
11483 }
11484 \f
11485 /* Note hard registers in X that are used.  This code is similar to
11486    that in flow.c, but much simpler since we don't care about pseudos.  */
11487
11488 static void
11489 mark_used_regs_combine (rtx x)
11490 {
11491   RTX_CODE code = GET_CODE (x);
11492   unsigned int regno;
11493   int i;
11494
11495   switch (code)
11496     {
11497     case LABEL_REF:
11498     case SYMBOL_REF:
11499     case CONST_INT:
11500     case CONST:
11501     case CONST_DOUBLE:
11502     case CONST_VECTOR:
11503     case PC:
11504     case ADDR_VEC:
11505     case ADDR_DIFF_VEC:
11506     case ASM_INPUT:
11507 #ifdef HAVE_cc0
11508     /* CC0 must die in the insn after it is set, so we don't need to take
11509        special note of it here.  */
11510     case CC0:
11511 #endif
11512       return;
11513
11514     case CLOBBER:
11515       /* If we are clobbering a MEM, mark any hard registers inside the
11516          address as used.  */
11517       if (MEM_P (XEXP (x, 0)))
11518         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11519       return;
11520
11521     case REG:
11522       regno = REGNO (x);
11523       /* A hard reg in a wide mode may really be multiple registers.
11524          If so, mark all of them just like the first.  */
11525       if (regno < FIRST_PSEUDO_REGISTER)
11526         {
11527           unsigned int endregno, r;
11528
11529           /* None of this applies to the stack, frame or arg pointers.  */
11530           if (regno == STACK_POINTER_REGNUM
11531 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11532               || regno == HARD_FRAME_POINTER_REGNUM
11533 #endif
11534 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11535               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11536 #endif
11537               || regno == FRAME_POINTER_REGNUM)
11538             return;
11539
11540           endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11541           for (r = regno; r < endregno; r++)
11542             SET_HARD_REG_BIT (newpat_used_regs, r);
11543         }
11544       return;
11545
11546     case SET:
11547       {
11548         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11549            the address.  */
11550         rtx testreg = SET_DEST (x);
11551
11552         while (GET_CODE (testreg) == SUBREG
11553                || GET_CODE (testreg) == ZERO_EXTRACT
11554                || GET_CODE (testreg) == STRICT_LOW_PART)
11555           testreg = XEXP (testreg, 0);
11556
11557         if (MEM_P (testreg))
11558           mark_used_regs_combine (XEXP (testreg, 0));
11559
11560         mark_used_regs_combine (SET_SRC (x));
11561       }
11562       return;
11563
11564     default:
11565       break;
11566     }
11567
11568   /* Recursively scan the operands of this expression.  */
11569
11570   {
11571     const char *fmt = GET_RTX_FORMAT (code);
11572
11573     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11574       {
11575         if (fmt[i] == 'e')
11576           mark_used_regs_combine (XEXP (x, i));
11577         else if (fmt[i] == 'E')
11578           {
11579             int j;
11580
11581             for (j = 0; j < XVECLEN (x, i); j++)
11582               mark_used_regs_combine (XVECEXP (x, i, j));
11583           }
11584       }
11585   }
11586 }
11587 \f
11588 /* Remove register number REGNO from the dead registers list of INSN.
11589
11590    Return the note used to record the death, if there was one.  */
11591
11592 rtx
11593 remove_death (unsigned int regno, rtx insn)
11594 {
11595   rtx note = find_regno_note (insn, REG_DEAD, regno);
11596
11597   if (note)
11598     {
11599       REG_N_DEATHS (regno)--;
11600       remove_note (insn, note);
11601     }
11602
11603   return note;
11604 }
11605
11606 /* For each register (hardware or pseudo) used within expression X, if its
11607    death is in an instruction with cuid between FROM_CUID (inclusive) and
11608    TO_INSN (exclusive), put a REG_DEAD note for that register in the
11609    list headed by PNOTES.
11610
11611    That said, don't move registers killed by maybe_kill_insn.
11612
11613    This is done when X is being merged by combination into TO_INSN.  These
11614    notes will then be distributed as needed.  */
11615
11616 static void
11617 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11618              rtx *pnotes)
11619 {
11620   const char *fmt;
11621   int len, i;
11622   enum rtx_code code = GET_CODE (x);
11623
11624   if (code == REG)
11625     {
11626       unsigned int regno = REGNO (x);
11627       rtx where_dead = reg_stat[regno].last_death;
11628       rtx before_dead, after_dead;
11629
11630       /* Don't move the register if it gets killed in between from and to.  */
11631       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11632           && ! reg_referenced_p (x, maybe_kill_insn))
11633         return;
11634
11635       /* WHERE_DEAD could be a USE insn made by combine, so first we
11636          make sure that we have insns with valid INSN_CUID values.  */
11637       before_dead = where_dead;
11638       while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11639         before_dead = PREV_INSN (before_dead);
11640
11641       after_dead = where_dead;
11642       while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11643         after_dead = NEXT_INSN (after_dead);
11644
11645       if (before_dead && after_dead
11646           && INSN_CUID (before_dead) >= from_cuid
11647           && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11648               || (where_dead != after_dead
11649                   && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11650         {
11651           rtx note = remove_death (regno, where_dead);
11652
11653           /* It is possible for the call above to return 0.  This can occur
11654              when last_death points to I2 or I1 that we combined with.
11655              In that case make a new note.
11656
11657              We must also check for the case where X is a hard register
11658              and NOTE is a death note for a range of hard registers
11659              including X.  In that case, we must put REG_DEAD notes for
11660              the remaining registers in place of NOTE.  */
11661
11662           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11663               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11664                   > GET_MODE_SIZE (GET_MODE (x))))
11665             {
11666               unsigned int deadregno = REGNO (XEXP (note, 0));
11667               unsigned int deadend
11668                 = (deadregno + hard_regno_nregs[deadregno]
11669                                                [GET_MODE (XEXP (note, 0))]);
11670               unsigned int ourend
11671                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11672               unsigned int i;
11673
11674               for (i = deadregno; i < deadend; i++)
11675                 if (i < regno || i >= ourend)
11676                   REG_NOTES (where_dead)
11677                     = gen_rtx_EXPR_LIST (REG_DEAD,
11678                                          regno_reg_rtx[i],
11679                                          REG_NOTES (where_dead));
11680             }
11681
11682           /* If we didn't find any note, or if we found a REG_DEAD note that
11683              covers only part of the given reg, and we have a multi-reg hard
11684              register, then to be safe we must check for REG_DEAD notes
11685              for each register other than the first.  They could have
11686              their own REG_DEAD notes lying around.  */
11687           else if ((note == 0
11688                     || (note != 0
11689                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11690                             < GET_MODE_SIZE (GET_MODE (x)))))
11691                    && regno < FIRST_PSEUDO_REGISTER
11692                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11693             {
11694               unsigned int ourend
11695                 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11696               unsigned int i, offset;
11697               rtx oldnotes = 0;
11698
11699               if (note)
11700                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11701               else
11702                 offset = 1;
11703
11704               for (i = regno + offset; i < ourend; i++)
11705                 move_deaths (regno_reg_rtx[i],
11706                              maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11707             }
11708
11709           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11710             {
11711               XEXP (note, 1) = *pnotes;
11712               *pnotes = note;
11713             }
11714           else
11715             *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11716
11717           REG_N_DEATHS (regno)++;
11718         }
11719
11720       return;
11721     }
11722
11723   else if (GET_CODE (x) == SET)
11724     {
11725       rtx dest = SET_DEST (x);
11726
11727       move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11728
11729       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11730          that accesses one word of a multi-word item, some
11731          piece of everything register in the expression is used by
11732          this insn, so remove any old death.  */
11733       /* ??? So why do we test for equality of the sizes?  */
11734
11735       if (GET_CODE (dest) == ZERO_EXTRACT
11736           || GET_CODE (dest) == STRICT_LOW_PART
11737           || (GET_CODE (dest) == SUBREG
11738               && (((GET_MODE_SIZE (GET_MODE (dest))
11739                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11740                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11741                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11742         {
11743           move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11744           return;
11745         }
11746
11747       /* If this is some other SUBREG, we know it replaces the entire
11748          value, so use that as the destination.  */
11749       if (GET_CODE (dest) == SUBREG)
11750         dest = SUBREG_REG (dest);
11751
11752       /* If this is a MEM, adjust deaths of anything used in the address.
11753          For a REG (the only other possibility), the entire value is
11754          being replaced so the old value is not used in this insn.  */
11755
11756       if (MEM_P (dest))
11757         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11758                      to_insn, pnotes);
11759       return;
11760     }
11761
11762   else if (GET_CODE (x) == CLOBBER)
11763     return;
11764
11765   len = GET_RTX_LENGTH (code);
11766   fmt = GET_RTX_FORMAT (code);
11767
11768   for (i = 0; i < len; i++)
11769     {
11770       if (fmt[i] == 'E')
11771         {
11772           int j;
11773           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11774             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11775                          to_insn, pnotes);
11776         }
11777       else if (fmt[i] == 'e')
11778         move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11779     }
11780 }
11781 \f
11782 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11783    pattern of an insn.  X must be a REG.  */
11784
11785 static int
11786 reg_bitfield_target_p (rtx x, rtx body)
11787 {
11788   int i;
11789
11790   if (GET_CODE (body) == SET)
11791     {
11792       rtx dest = SET_DEST (body);
11793       rtx target;
11794       unsigned int regno, tregno, endregno, endtregno;
11795
11796       if (GET_CODE (dest) == ZERO_EXTRACT)
11797         target = XEXP (dest, 0);
11798       else if (GET_CODE (dest) == STRICT_LOW_PART)
11799         target = SUBREG_REG (XEXP (dest, 0));
11800       else
11801         return 0;
11802
11803       if (GET_CODE (target) == SUBREG)
11804         target = SUBREG_REG (target);
11805
11806       if (!REG_P (target))
11807         return 0;
11808
11809       tregno = REGNO (target), regno = REGNO (x);
11810       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11811         return target == x;
11812
11813       endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11814       endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11815
11816       return endregno > tregno && regno < endtregno;
11817     }
11818
11819   else if (GET_CODE (body) == PARALLEL)
11820     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11821       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11822         return 1;
11823
11824   return 0;
11825 }
11826 \f
11827 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11828    as appropriate.  I3 and I2 are the insns resulting from the combination
11829    insns including FROM (I2 may be zero).
11830
11831    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11832    not need REG_DEAD notes because they are being substituted for.  This
11833    saves searching in the most common cases.
11834
11835    Each note in the list is either ignored or placed on some insns, depending
11836    on the type of note.  */
11837
11838 static void
11839 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11840                   rtx elim_i1)
11841 {
11842   rtx note, next_note;
11843   rtx tem;
11844
11845   for (note = notes; note; note = next_note)
11846     {
11847       rtx place = 0, place2 = 0;
11848
11849       next_note = XEXP (note, 1);
11850       switch (REG_NOTE_KIND (note))
11851         {
11852         case REG_BR_PROB:
11853         case REG_BR_PRED:
11854           /* Doesn't matter much where we put this, as long as it's somewhere.
11855              It is preferable to keep these notes on branches, which is most
11856              likely to be i3.  */
11857           place = i3;
11858           break;
11859
11860         case REG_VALUE_PROFILE:
11861           /* Just get rid of this note, as it is unused later anyway.  */
11862           break;
11863
11864         case REG_NON_LOCAL_GOTO:
11865           if (JUMP_P (i3))
11866             place = i3;
11867           else
11868             {
11869               gcc_assert (i2 && JUMP_P (i2));
11870               place = i2;
11871             }
11872           break;
11873
11874         case REG_EH_REGION:
11875           /* These notes must remain with the call or trapping instruction.  */
11876           if (CALL_P (i3))
11877             place = i3;
11878           else if (i2 && CALL_P (i2))
11879             place = i2;
11880           else
11881             {
11882               gcc_assert (flag_non_call_exceptions);
11883               if (may_trap_p (i3))
11884                 place = i3;
11885               else if (i2 && may_trap_p (i2))
11886                 place = i2;
11887               /* ??? Otherwise assume we've combined things such that we
11888                  can now prove that the instructions can't trap.  Drop the
11889                  note in this case.  */
11890             }
11891           break;
11892
11893         case REG_NORETURN:
11894         case REG_SETJMP:
11895           /* These notes must remain with the call.  It should not be
11896              possible for both I2 and I3 to be a call.  */
11897           if (CALL_P (i3))
11898             place = i3;
11899           else
11900             {
11901               gcc_assert (i2 && CALL_P (i2));
11902               place = i2;
11903             }
11904           break;
11905
11906         case REG_UNUSED:
11907           /* Any clobbers for i3 may still exist, and so we must process
11908              REG_UNUSED notes from that insn.
11909
11910              Any clobbers from i2 or i1 can only exist if they were added by
11911              recog_for_combine.  In that case, recog_for_combine created the
11912              necessary REG_UNUSED notes.  Trying to keep any original
11913              REG_UNUSED notes from these insns can cause incorrect output
11914              if it is for the same register as the original i3 dest.
11915              In that case, we will notice that the register is set in i3,
11916              and then add a REG_UNUSED note for the destination of i3, which
11917              is wrong.  However, it is possible to have REG_UNUSED notes from
11918              i2 or i1 for register which were both used and clobbered, so
11919              we keep notes from i2 or i1 if they will turn into REG_DEAD
11920              notes.  */
11921
11922           /* If this register is set or clobbered in I3, put the note there
11923              unless there is one already.  */
11924           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11925             {
11926               if (from_insn != i3)
11927                 break;
11928
11929               if (! (REG_P (XEXP (note, 0))
11930                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11931                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11932                 place = i3;
11933             }
11934           /* Otherwise, if this register is used by I3, then this register
11935              now dies here, so we must put a REG_DEAD note here unless there
11936              is one already.  */
11937           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11938                    && ! (REG_P (XEXP (note, 0))
11939                          ? find_regno_note (i3, REG_DEAD,
11940                                             REGNO (XEXP (note, 0)))
11941                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11942             {
11943               PUT_REG_NOTE_KIND (note, REG_DEAD);
11944               place = i3;
11945             }
11946           break;
11947
11948         case REG_EQUAL:
11949         case REG_EQUIV:
11950         case REG_NOALIAS:
11951           /* These notes say something about results of an insn.  We can
11952              only support them if they used to be on I3 in which case they
11953              remain on I3.  Otherwise they are ignored.
11954
11955              If the note refers to an expression that is not a constant, we
11956              must also ignore the note since we cannot tell whether the
11957              equivalence is still true.  It might be possible to do
11958              slightly better than this (we only have a problem if I2DEST
11959              or I1DEST is present in the expression), but it doesn't
11960              seem worth the trouble.  */
11961
11962           if (from_insn == i3
11963               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11964             place = i3;
11965           break;
11966
11967         case REG_INC:
11968         case REG_NO_CONFLICT:
11969           /* These notes say something about how a register is used.  They must
11970              be present on any use of the register in I2 or I3.  */
11971           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11972             place = i3;
11973
11974           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11975             {
11976               if (place)
11977                 place2 = i2;
11978               else
11979                 place = i2;
11980             }
11981           break;
11982
11983         case REG_LABEL:
11984           /* This can show up in several ways -- either directly in the
11985              pattern, or hidden off in the constant pool with (or without?)
11986              a REG_EQUAL note.  */
11987           /* ??? Ignore the without-reg_equal-note problem for now.  */
11988           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11989               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11990                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11991                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11992             place = i3;
11993
11994           if (i2
11995               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11996                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11997                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11998                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11999             {
12000               if (place)
12001                 place2 = i2;
12002               else
12003                 place = i2;
12004             }
12005
12006           /* Don't attach REG_LABEL note to a JUMP_INSN.  Add
12007              a JUMP_LABEL instead or decrement LABEL_NUSES.  */
12008           if (place && JUMP_P (place))
12009             {
12010               rtx label = JUMP_LABEL (place);
12011
12012               if (!label)
12013                 JUMP_LABEL (place) = XEXP (note, 0);
12014               else
12015                 {
12016                   gcc_assert (label == XEXP (note, 0));
12017                   if (LABEL_P (label))
12018                     LABEL_NUSES (label)--;
12019                 }
12020               place = 0;
12021             }
12022           if (place2 && JUMP_P (place2))
12023             {
12024               rtx label = JUMP_LABEL (place2);
12025
12026               if (!label)
12027                 JUMP_LABEL (place2) = XEXP (note, 0);
12028               else
12029                 {
12030                   gcc_assert (label == XEXP (note, 0));
12031                   if (LABEL_P (label))
12032                     LABEL_NUSES (label)--;
12033                 }
12034               place2 = 0;
12035             }
12036           break;
12037
12038         case REG_NONNEG:
12039           /* This note says something about the value of a register prior
12040              to the execution of an insn.  It is too much trouble to see
12041              if the note is still correct in all situations.  It is better
12042              to simply delete it.  */
12043           break;
12044
12045         case REG_RETVAL:
12046           /* If the insn previously containing this note still exists,
12047              put it back where it was.  Otherwise move it to the previous
12048              insn.  Adjust the corresponding REG_LIBCALL note.  */
12049           if (!NOTE_P (from_insn))
12050             place = from_insn;
12051           else
12052             {
12053               tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12054               place = prev_real_insn (from_insn);
12055               if (tem && place)
12056                 XEXP (tem, 0) = place;
12057               /* If we're deleting the last remaining instruction of a
12058                  libcall sequence, don't add the notes.  */
12059               else if (XEXP (note, 0) == from_insn)
12060                 tem = place = 0;
12061               /* Don't add the dangling REG_RETVAL note.  */
12062               else if (! tem)
12063                 place = 0;
12064             }
12065           break;
12066
12067         case REG_LIBCALL:
12068           /* This is handled similarly to REG_RETVAL.  */
12069           if (!NOTE_P (from_insn))
12070             place = from_insn;
12071           else
12072             {
12073               tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12074               place = next_real_insn (from_insn);
12075               if (tem && place)
12076                 XEXP (tem, 0) = place;
12077               /* If we're deleting the last remaining instruction of a
12078                  libcall sequence, don't add the notes.  */
12079               else if (XEXP (note, 0) == from_insn)
12080                 tem = place = 0;
12081               /* Don't add the dangling REG_LIBCALL note.  */
12082               else if (! tem)
12083                 place = 0;
12084             }
12085           break;
12086
12087         case REG_DEAD:
12088           /* If the register is used as an input in I3, it dies there.
12089              Similarly for I2, if it is nonzero and adjacent to I3.
12090
12091              If the register is not used as an input in either I3 or I2
12092              and it is not one of the registers we were supposed to eliminate,
12093              there are two possibilities.  We might have a non-adjacent I2
12094              or we might have somehow eliminated an additional register
12095              from a computation.  For example, we might have had A & B where
12096              we discover that B will always be zero.  In this case we will
12097              eliminate the reference to A.
12098
12099              In both cases, we must search to see if we can find a previous
12100              use of A and put the death note there.  */
12101
12102           if (from_insn
12103               && CALL_P (from_insn)
12104               && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12105             place = from_insn;
12106           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12107             place = i3;
12108           else if (i2 != 0 && next_nonnote_insn (i2) == i3
12109                    && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12110             place = i2;
12111
12112           if (place == 0
12113               && (rtx_equal_p (XEXP (note, 0), elim_i2)
12114                   || rtx_equal_p (XEXP (note, 0), elim_i1)))
12115             break;
12116
12117           if (place == 0)
12118             {
12119               basic_block bb = this_basic_block;
12120
12121               /* You might think you could search back from FROM_INSN
12122                  rather than from I3, but combine tries to split invalid
12123                  combined instructions.  This can result in the old I2
12124                  or I1 moving later in the insn sequence.  */
12125               for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12126                 {
12127                   if (! INSN_P (tem))
12128                     {
12129                       if (tem == BB_HEAD (bb))
12130                         break;
12131                       continue;
12132                     }
12133
12134                   /* If the register is being set at TEM, see if that is all
12135                      TEM is doing.  If so, delete TEM.  Otherwise, make this
12136                      into a REG_UNUSED note instead. Don't delete sets to
12137                      global register vars.  */
12138                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12139                        || !global_regs[REGNO (XEXP (note, 0))])
12140                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12141                     {
12142                       rtx set = single_set (tem);
12143                       rtx inner_dest = 0;
12144 #ifdef HAVE_cc0
12145                       rtx cc0_setter = NULL_RTX;
12146 #endif
12147
12148                       if (set != 0)
12149                         for (inner_dest = SET_DEST (set);
12150                              (GET_CODE (inner_dest) == STRICT_LOW_PART
12151                               || GET_CODE (inner_dest) == SUBREG
12152                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
12153                              inner_dest = XEXP (inner_dest, 0))
12154                           ;
12155
12156                       /* Verify that it was the set, and not a clobber that
12157                          modified the register.
12158
12159                          CC0 targets must be careful to maintain setter/user
12160                          pairs.  If we cannot delete the setter due to side
12161                          effects, mark the user with an UNUSED note instead
12162                          of deleting it.  */
12163
12164                       if (set != 0 && ! side_effects_p (SET_SRC (set))
12165                           && rtx_equal_p (XEXP (note, 0), inner_dest)
12166 #ifdef HAVE_cc0
12167                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12168                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12169                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12170 #endif
12171                           )
12172                         {
12173                           /* Move the notes and links of TEM elsewhere.
12174                              This might delete other dead insns recursively.
12175                              First set the pattern to something that won't use
12176                              any register.  */
12177                           rtx old_notes = REG_NOTES (tem);
12178
12179                           PATTERN (tem) = pc_rtx;
12180                           REG_NOTES (tem) = NULL;
12181
12182                           distribute_notes (old_notes, tem, tem, NULL_RTX,
12183                                             NULL_RTX, NULL_RTX);
12184                           distribute_links (LOG_LINKS (tem));
12185
12186                           SET_INSN_DELETED (tem);
12187
12188 #ifdef HAVE_cc0
12189                           /* Delete the setter too.  */
12190                           if (cc0_setter)
12191                             {
12192                               PATTERN (cc0_setter) = pc_rtx;
12193                               old_notes = REG_NOTES (cc0_setter);
12194                               REG_NOTES (cc0_setter) = NULL;
12195
12196                               distribute_notes (old_notes, cc0_setter,
12197                                                 cc0_setter, NULL_RTX,
12198                                                 NULL_RTX, NULL_RTX);
12199                               distribute_links (LOG_LINKS (cc0_setter));
12200
12201                               SET_INSN_DELETED (cc0_setter);
12202                             }
12203 #endif
12204                         }
12205                       else
12206                         {
12207                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
12208
12209                           /*  If there isn't already a REG_UNUSED note, put one
12210                               here.  Do not place a REG_DEAD note, even if
12211                               the register is also used here; that would not
12212                               match the algorithm used in lifetime analysis
12213                               and can cause the consistency check in the
12214                               scheduler to fail.  */
12215                           if (! find_regno_note (tem, REG_UNUSED,
12216                                                  REGNO (XEXP (note, 0))))
12217                             place = tem;
12218                           break;
12219                         }
12220                     }
12221                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12222                            || (CALL_P (tem)
12223                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
12224                     {
12225                       /* This may not be the correct place for the death
12226                          note if FROM_INSN is before TEM, and the reg is
12227                          set between FROM_INSN and TEM.  The reg might
12228                          die two or more times.  An existing death note
12229                          means we are looking at the wrong live range.  */
12230                       if (from_insn
12231                           && INSN_CUID (from_insn) < INSN_CUID (tem)
12232                           && find_regno_note (tem, REG_DEAD,
12233                                               REGNO (XEXP (note, 0))))
12234                         {
12235                           tem = from_insn;
12236                           if (tem == BB_HEAD (bb))
12237                             break;
12238                           continue;
12239                         }
12240
12241                       place = tem;
12242
12243                       /* If we are doing a 3->2 combination, and we have a
12244                          register which formerly died in i3 and was not used
12245                          by i2, which now no longer dies in i3 and is used in
12246                          i2 but does not die in i2, and place is between i2
12247                          and i3, then we may need to move a link from place to
12248                          i2.  */
12249                       if (i2 && INSN_UID (place) <= max_uid_cuid
12250                           && INSN_CUID (place) > INSN_CUID (i2)
12251                           && from_insn
12252                           && INSN_CUID (from_insn) > INSN_CUID (i2)
12253                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12254                         {
12255                           rtx links = LOG_LINKS (place);
12256                           LOG_LINKS (place) = 0;
12257                           distribute_links (links);
12258                         }
12259                       break;
12260                     }
12261
12262                   if (tem == BB_HEAD (bb))
12263                     break;
12264                 }
12265
12266               /* We haven't found an insn for the death note and it
12267                  is still a REG_DEAD note, but we have hit the beginning
12268                  of the block.  If the existing life info says the reg
12269                  was dead, there's nothing left to do.  Otherwise, we'll
12270                  need to do a global life update after combine.  */
12271               if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12272                   && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12273                                       REGNO (XEXP (note, 0))))
12274                 SET_BIT (refresh_blocks, this_basic_block->index);
12275             }
12276
12277           /* If the register is set or already dead at PLACE, we needn't do
12278              anything with this note if it is still a REG_DEAD note.
12279              We check here if it is set at all, not if is it totally replaced,
12280              which is what `dead_or_set_p' checks, so also check for it being
12281              set partially.  */
12282
12283           if (place && REG_NOTE_KIND (note) == REG_DEAD)
12284             {
12285               unsigned int regno = REGNO (XEXP (note, 0));
12286
12287               /* Similarly, if the instruction on which we want to place
12288                  the note is a noop, we'll need do a global live update
12289                  after we remove them in delete_noop_moves.  */
12290               if (noop_move_p (place))
12291                 SET_BIT (refresh_blocks, this_basic_block->index);
12292
12293               if (dead_or_set_p (place, XEXP (note, 0))
12294                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12295                 {
12296                   /* Unless the register previously died in PLACE, clear
12297                      last_death.  [I no longer understand why this is
12298                      being done.] */
12299                   if (reg_stat[regno].last_death != place)
12300                     reg_stat[regno].last_death = 0;
12301                   place = 0;
12302                 }
12303               else
12304                 reg_stat[regno].last_death = place;
12305
12306               /* If this is a death note for a hard reg that is occupying
12307                  multiple registers, ensure that we are still using all
12308                  parts of the object.  If we find a piece of the object
12309                  that is unused, we must arrange for an appropriate REG_DEAD
12310                  note to be added for it.  However, we can't just emit a USE
12311                  and tag the note to it, since the register might actually
12312                  be dead; so we recourse, and the recursive call then finds
12313                  the previous insn that used this register.  */
12314
12315               if (place && regno < FIRST_PSEUDO_REGISTER
12316                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12317                 {
12318                   unsigned int endregno
12319                     = regno + hard_regno_nregs[regno]
12320                                               [GET_MODE (XEXP (note, 0))];
12321                   int all_used = 1;
12322                   unsigned int i;
12323
12324                   for (i = regno; i < endregno; i++)
12325                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12326                          && ! find_regno_fusage (place, USE, i))
12327                         || dead_or_set_regno_p (place, i))
12328                       all_used = 0;
12329
12330                   if (! all_used)
12331                     {
12332                       /* Put only REG_DEAD notes for pieces that are
12333                          not already dead or set.  */
12334
12335                       for (i = regno; i < endregno;
12336                            i += hard_regno_nregs[i][reg_raw_mode[i]])
12337                         {
12338                           rtx piece = regno_reg_rtx[i];
12339                           basic_block bb = this_basic_block;
12340
12341                           if (! dead_or_set_p (place, piece)
12342                               && ! reg_bitfield_target_p (piece,
12343                                                           PATTERN (place)))
12344                             {
12345                               rtx new_note
12346                                 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12347
12348                               distribute_notes (new_note, place, place,
12349                                                 NULL_RTX, NULL_RTX, NULL_RTX);
12350                             }
12351                           else if (! refers_to_regno_p (i, i + 1,
12352                                                         PATTERN (place), 0)
12353                                    && ! find_regno_fusage (place, USE, i))
12354                             for (tem = PREV_INSN (place); ;
12355                                  tem = PREV_INSN (tem))
12356                               {
12357                                 if (! INSN_P (tem))
12358                                   {
12359                                     if (tem == BB_HEAD (bb))
12360                                       {
12361                                         SET_BIT (refresh_blocks,
12362                                                  this_basic_block->index);
12363                                         break;
12364                                       }
12365                                     continue;
12366                                   }
12367                                 if (dead_or_set_p (tem, piece)
12368                                     || reg_bitfield_target_p (piece,
12369                                                               PATTERN (tem)))
12370                                   {
12371                                     REG_NOTES (tem)
12372                                       = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12373                                                            REG_NOTES (tem));
12374                                     break;
12375                                   }
12376                               }
12377
12378                         }
12379
12380                       place = 0;
12381                     }
12382                 }
12383             }
12384           break;
12385
12386         default:
12387           /* Any other notes should not be present at this point in the
12388              compilation.  */
12389           gcc_unreachable ();
12390         }
12391
12392       if (place)
12393         {
12394           XEXP (note, 1) = REG_NOTES (place);
12395           REG_NOTES (place) = note;
12396         }
12397       else if ((REG_NOTE_KIND (note) == REG_DEAD
12398                 || REG_NOTE_KIND (note) == REG_UNUSED)
12399                && REG_P (XEXP (note, 0)))
12400         REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12401
12402       if (place2)
12403         {
12404           if ((REG_NOTE_KIND (note) == REG_DEAD
12405                || REG_NOTE_KIND (note) == REG_UNUSED)
12406               && REG_P (XEXP (note, 0)))
12407             REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12408
12409           REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12410                                                REG_NOTE_KIND (note),
12411                                                XEXP (note, 0),
12412                                                REG_NOTES (place2));
12413         }
12414     }
12415 }
12416 \f
12417 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12418    I3, I2, and I1 to new locations.  This is also called to add a link
12419    pointing at I3 when I3's destination is changed.  */
12420
12421 static void
12422 distribute_links (rtx links)
12423 {
12424   rtx link, next_link;
12425
12426   for (link = links; link; link = next_link)
12427     {
12428       rtx place = 0;
12429       rtx insn;
12430       rtx set, reg;
12431
12432       next_link = XEXP (link, 1);
12433
12434       /* If the insn that this link points to is a NOTE or isn't a single
12435          set, ignore it.  In the latter case, it isn't clear what we
12436          can do other than ignore the link, since we can't tell which
12437          register it was for.  Such links wouldn't be used by combine
12438          anyway.
12439
12440          It is not possible for the destination of the target of the link to
12441          have been changed by combine.  The only potential of this is if we
12442          replace I3, I2, and I1 by I3 and I2.  But in that case the
12443          destination of I2 also remains unchanged.  */
12444
12445       if (NOTE_P (XEXP (link, 0))
12446           || (set = single_set (XEXP (link, 0))) == 0)
12447         continue;
12448
12449       reg = SET_DEST (set);
12450       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12451              || GET_CODE (reg) == STRICT_LOW_PART)
12452         reg = XEXP (reg, 0);
12453
12454       /* A LOG_LINK is defined as being placed on the first insn that uses
12455          a register and points to the insn that sets the register.  Start
12456          searching at the next insn after the target of the link and stop
12457          when we reach a set of the register or the end of the basic block.
12458
12459          Note that this correctly handles the link that used to point from
12460          I3 to I2.  Also note that not much searching is typically done here
12461          since most links don't point very far away.  */
12462
12463       for (insn = NEXT_INSN (XEXP (link, 0));
12464            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12465                      || BB_HEAD (this_basic_block->next_bb) != insn));
12466            insn = NEXT_INSN (insn))
12467         if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12468           {
12469             if (reg_referenced_p (reg, PATTERN (insn)))
12470               place = insn;
12471             break;
12472           }
12473         else if (CALL_P (insn)
12474                  && find_reg_fusage (insn, USE, reg))
12475           {
12476             place = insn;
12477             break;
12478           }
12479         else if (INSN_P (insn) && reg_set_p (reg, insn))
12480           break;
12481
12482       /* If we found a place to put the link, place it there unless there
12483          is already a link to the same insn as LINK at that point.  */
12484
12485       if (place)
12486         {
12487           rtx link2;
12488
12489           for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12490             if (XEXP (link2, 0) == XEXP (link, 0))
12491               break;
12492
12493           if (link2 == 0)
12494             {
12495               XEXP (link, 1) = LOG_LINKS (place);
12496               LOG_LINKS (place) = link;
12497
12498               /* Set added_links_insn to the earliest insn we added a
12499                  link to.  */
12500               if (added_links_insn == 0
12501                   || INSN_CUID (added_links_insn) > INSN_CUID (place))
12502                 added_links_insn = place;
12503             }
12504         }
12505     }
12506 }
12507 \f
12508 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12509    Check whether the expression pointer to by LOC is a register or
12510    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12511    Otherwise return zero.  */
12512
12513 static int
12514 unmentioned_reg_p_1 (rtx *loc, void *expr)
12515 {
12516   rtx x = *loc;
12517
12518   if (x != NULL_RTX
12519       && (REG_P (x) || MEM_P (x))
12520       && ! reg_mentioned_p (x, (rtx) expr))
12521     return 1;
12522   return 0;
12523 }
12524
12525 /* Check for any register or memory mentioned in EQUIV that is not
12526    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
12527    of EXPR where some registers may have been replaced by constants.  */
12528
12529 static bool
12530 unmentioned_reg_p (rtx equiv, rtx expr)
12531 {
12532   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12533 }
12534 \f
12535 /* Compute INSN_CUID for INSN, which is an insn made by combine.  */
12536
12537 static int
12538 insn_cuid (rtx insn)
12539 {
12540   while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12541          && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12542     insn = NEXT_INSN (insn);
12543
12544   gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12545
12546   return INSN_CUID (insn);
12547 }
12548 \f
12549 void
12550 dump_combine_stats (FILE *file)
12551 {
12552   fprintf
12553     (file,
12554      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12555      combine_attempts, combine_merges, combine_extras, combine_successes);
12556 }
12557
12558 void
12559 dump_combine_total_stats (FILE *file)
12560 {
12561   fprintf
12562     (file,
12563      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12564      total_attempts, total_merges, total_extras, total_successes);
12565 }
12566 \f
12567
12568 static bool
12569 gate_handle_combine (void)
12570 {
12571   return (optimize > 0);
12572 }
12573
12574 /* Try combining insns through substitution.  */
12575 static unsigned int
12576 rest_of_handle_combine (void)
12577 {
12578   int rebuild_jump_labels_after_combine
12579     = combine_instructions (get_insns (), max_reg_num ());
12580
12581   /* Combining insns may have turned an indirect jump into a
12582      direct jump.  Rebuild the JUMP_LABEL fields of jumping
12583      instructions.  */
12584   if (rebuild_jump_labels_after_combine)
12585     {
12586       timevar_push (TV_JUMP);
12587       rebuild_jump_labels (get_insns ());
12588       timevar_pop (TV_JUMP);
12589
12590       delete_dead_jumptables ();
12591       cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12592     }
12593   return 0;
12594 }
12595
12596 struct tree_opt_pass pass_combine =
12597 {
12598   "combine",                            /* name */
12599   gate_handle_combine,                  /* gate */
12600   rest_of_handle_combine,               /* execute */
12601   NULL,                                 /* sub */
12602   NULL,                                 /* next */
12603   0,                                    /* static_pass_number */
12604   TV_COMBINE,                           /* tv_id */
12605   0,                                    /* properties_required */
12606   0,                                    /* properties_provided */
12607   0,                                    /* properties_destroyed */
12608   0,                                    /* todo_flags_start */
12609   TODO_dump_func |
12610   TODO_ggc_collect,                     /* todo_flags_finish */
12611   'c'                                   /* letter */
12612 };
12613