| blob | e0af19dd45e47f079dd3ac1328610f793c23f0cd |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
306 rtx *);
367 {
368 rtx match;
369 rtx replacement;
370 rtx insn;
373 /* Nonzero iff INSN is between START and END, inclusive. */
374 #define INSN_IN_RANGE_P(INSN, START, END) \
375 (INSN_UID (INSN) < max_uid_for_loop \
376 && INSN_LUID (INSN) >= INSN_LUID (START) \
377 && INSN_LUID (INSN) <= INSN_LUID (END))
379 /* Indirect_jump_in_function is computed once per function. */
387 \f
388 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
389 copy the value of the strength reduced giv to its original register. */
392 /* Cost of using a register, to normalize the benefits of a giv. */
395 void
397 {
403 }
404 \f
405 /* Compute the mapping from uids to luids.
406 LUIDs are numbers assigned to insns, like uids,
407 except that luids increase monotonically through the code.
408 Start at insn START and stop just before END. Assign LUIDs
409 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
410 static int
412 {
414 rtx insn;
417 {
420 /* Don't assign luids to line-number NOTEs, so that the distance in
421 luids between two insns is not affected by -g. */
425 else
426 /* Give a line number note the same luid as preceding insn. */
428 }
430 }
431 \f
432 /* Entry point of this file. Perform loop optimization
433 on the current function. F is the first insn of the function
434 and DUMPFILE is a stream for output of a trace of actions taken
435 (or 0 if none should be output). */
437 void
439 {
440 rtx insn;
455 /* Count the number of loops. */
459 {
462 max_loop_num++;
463 }
465 /* Don't waste time if no loops. */
471 /* Get size to use for tables indexed by uids.
472 Leave some space for labels allocated by find_and_verify_loops. */
478 /* Allocate storage for array of loops. */
481 /* Find and process each loop.
482 First, find them, and record them in order of their beginnings. */
485 /* Allocate and initialize auxiliary loop information. */
490 /* Now find all register lifetimes. This must be done after
491 find_and_verify_loops, because it might reorder the insns in the
492 function. */
495 /* This must occur after reg_scan so that registers created by gcse
496 will have entries in the register tables.
498 We could have added a call to reg_scan after gcse_main in toplev.c,
499 but moving this call to init_alias_analysis is more efficient. */
502 /* See if we went too far. Note that get_max_uid already returns
503 one more that the maximum uid of all insn. */
506 /* Now reset it to the actual size we need. See above. */
509 /* find_and_verify_loops has already called compute_luids, but it
510 might have rearranged code afterwards, so we need to recompute
511 the luids now. */
514 /* Don't leave gaps in uid_luid for insns that have been
515 deleted. It is possible that the first or last insn
516 using some register has been deleted by cross-jumping.
517 Make sure that uid_luid for that former insn's uid
518 points to the general area where that insn used to be. */
520 {
524 }
529 /* Determine if the function has indirect jump. On some systems
530 this prevents low overhead loop instructions from being used. */
533 /* Now scan the loops, last ones first, since this means inner ones are done
534 before outer ones. */
536 {
540 {
543 }
544 }
548 /* Clean up. */
556 }
557 \f
558 /* Returns the next insn, in execution order, after INSN. START and
559 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
560 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
561 insn-stream; it is used with loops that are entered near the
562 bottom. */
564 static rtx
566 {
570 {
572 /* Go to the top of the loop, and continue there. */
574 else
575 /* We're done. */
577 }
580 /* We're done. */
584 }
586 /* Find any register references hidden inside X and add them to
587 the dependency list DEPS. This is used to look inside CLOBBER (MEM
588 when checking whether a PARALLEL can be pulled out of a loop. */
590 static rtx
592 {
596 else
597 {
601 {
607 }
608 }
610 }
612 /* Optimize one loop described by LOOP. */
614 /* ??? Could also move memory writes out of loops if the destination address
615 is invariant, the source is invariant, the memory write is not volatile,
616 and if we can prove that no read inside the loop can read this address
617 before the write occurs. If there is a read of this address after the
618 write, then we can also mark the memory read as invariant. */
620 static void
622 {
628 rtx p;
629 /* 1 if we are scanning insns that could be executed zero times. */
631 /* 1 if we are scanning insns that might never be executed
632 due to a subroutine call which might exit before they are reached. */
634 /* Number of insns in the loop. */
638 /* The SET from an insn, if it is the only SET in the insn. */
640 /* Chain describing insns movable in current loop. */
642 /* Ratio of extra register life span we can justify
643 for saving an instruction. More if loop doesn't call subroutines
644 since in that case saving an insn makes more difference
645 and more registers are available. */
647 /* Nonzero if we are scanning instructions in a sub-loop. */
656 /* Determine whether this loop starts with a jump down to a test at
657 the end. This will occur for a small number of loops with a test
658 that is too complex to duplicate in front of the loop.
660 We search for the first insn or label in the loop, skipping NOTEs.
661 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
662 (because we might have a loop executed only once that contains a
663 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
664 (in case we have a degenerate loop).
666 Note that if we mistakenly think that a loop is entered at the top
667 when, in fact, it is entered at the exit test, the only effect will be
668 slightly poorer optimization. Making the opposite error can generate
669 incorrect code. Since very few loops now start with a jump to the
670 exit test, the code here to detect that case is very conservative. */
673 p != loop_end
679 ;
683 /* If loop end is the end of the current function, then emit a
684 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
685 note insn. This is the position we use when sinking insns out of
686 the loop. */
689 else
692 /* Set up variables describing this loop. */
696 /* If loop has a jump before the first label,
697 the true entry is the target of that jump.
698 Start scan from there.
699 But record in LOOP->TOP the place where the end-test jumps
700 back to so we can scan that after the end of the loop. */
702 /* Loop entry must be unconditional jump (and not a RETURN) */
705 /* Check to see whether the jump actually
706 jumps out of the loop (meaning it's no loop).
707 This case can happen for things like
708 do {..} while (0). If this label was generated previously
709 by loop, we can't tell anything about it and have to reject
710 the loop. */
712 {
715 }
717 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
718 as required by loop_reg_used_before_p. So skip such loops. (This
719 test may never be true, but it's best to play it safe.)
721 Also, skip loops where we do not start scanning at a label. This
722 test also rejects loops starting with a JUMP_INSN that failed the
723 test above. */
727 {
732 }
734 /* Allocate extra space for REGs that might be created by load_mems.
735 We allocate a little extra slop as well, in the hopes that we
736 won't have to reallocate the regs array. */
741 {
747 }
749 /* Scan through the loop finding insns that are safe to move.
750 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
751 this reg will be considered invariant for subsequent insns.
752 We consider whether subsequent insns use the reg
753 in deciding whether it is worth actually moving.
755 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
756 and therefore it is possible that the insns we are scanning
757 would never be executed. At such times, we must make sure
758 that it is safe to execute the insn once instead of zero times.
759 When MAYBE_NEVER is 0, all insns will be executed at least once
760 so that is not a problem. */
765 {
767 in_libcall--;
769 {
772 in_libcall++;
776 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
778 #endif
780 {
788 /* Figure out what to use as a source of this insn. If a
789 REG_EQUIV note is given or if a REG_EQUAL note with a
790 constant operand is specified, use it as the source and
791 mark that we should move this insn by calling
792 emit_move_insn rather that duplicating the insn.
794 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
795 note is present. */
799 else
800 {
805 {
807 /* A libcall block can use regs that don't appear in
808 the equivalent expression. To move the libcall,
809 we must move those regs too. */
811 }
812 }
814 /* For parallels, add any possible uses to the dependencies, as
815 we can't move the insn without resolving them first.
816 MEMs inside CLOBBERs may also reference registers; these
817 count as implicit uses. */
819 {
821 {
824 dependencies
826 dependencies);
831 }
832 }
835 than the one where it is set (meaning that
836 something after this point in the loop might
837 depend on its value before the set). */
839 /* And the set is not guaranteed to be executed once
840 the loop starts, or the value before the set is
841 needed before the set occurs...
843 ??? Note we have quadratic behavior here, mitigated
844 by the fact that the previous test will often fail for
845 large loops. Rather than re-scanning the entire loop
846 each time for register usage, we should build tables
847 of the register usage and use them here instead. */
848 && (maybe_never
850 /* It is unsafe to move the set. However, it may be OK to
851 move the source into a new pseudo, and substitute a
852 reg-to-reg copy for the original insn.
854 This code used to consider it OK to move a set of a variable
855 which was not created by the user and not used in an exit
856 test.
857 That behavior is incorrect and was removed. */
860 /* Don't try to optimize a MODE_CC set with a constant
861 source. It probably will be combined with a conditional
862 jump. */
865 ;
866 /* Don't try to optimize a register that was made
867 by loop-optimization for an inner loop.
868 We don't know its life-span, so we can't compute
869 the benefit. */
871 ;
872 /* Don't move the source and add a reg-to-reg copy:
873 - with -Os (this certainly increases size),
874 - if the mode doesn't support copy operations (obviously),
875 - if the source is already a reg (the motion will gain nothing),
876 - if the source is a legitimate constant (likewise). */
878 && (optimize_size
883 ;
886 || (tem2
889 || (tem1
890 = consec_sets_invariant_p
893 p)))
894 /* If the insn can cause a trap (such as divide by zero),
895 can't move it unless it's guaranteed to be executed
896 once loop is entered. Even a function call might
897 prevent the trap insn from being reached
898 (since it might exit!) */
901 {
905 /* A potential lossage is where we have a case where two insns
906 can be combined as long as they are both in the loop, but
907 we move one of them outside the loop. For large loops,
908 this can lose. The most common case of this is the address
909 of a function being called.
911 Therefore, if this register is marked as being used
912 exactly once if we are in a loop with calls
913 (a "large loop"), see if we can replace the usage of
914 this register with the source of this SET. If we can,
915 delete this insn.
917 Don't do this if P has a REG_RETVAL note or if we have
918 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
930 && (! SMALL_REGISTER_CLASSES
935 /* This test is not redundant; SET_SRC (set) might be
936 a call-clobbered register and the life of REGNO
937 might span a call. */
944 {
945 /* Replace any usage in a REG_EQUAL note. Must copy
946 the new source, so that we don't get rtx sharing
947 between the SET_SOURCE and REG_NOTES of insn p. */
949 = (replace_rtx
955 i++)
958 }
967 m->consec
978 /* Set M->cond if either loop_invariant_p
979 or consec_sets_invariant_p returned 2
980 (only conditionally invariant). */
990 /* Add M to the end of the chain MOVABLES. */
994 {
995 /* It is possible for the first instruction to have a
996 REG_EQUAL note but a non-invariant SET_SRC, so we must
997 remember the status of the first instruction in case
998 the last instruction doesn't have a REG_EQUAL note. */
1001 /* Skip this insn, not checking REG_LIBCALL notes. */
1003 /* Skip the consecutive insns, if there are any. */
1005 /* Back up to the last insn of the consecutive group. */
1008 /* We must now reset m->move_insn, m->is_equiv, and
1009 possibly m->set_src to correspond to the effects of
1010 all the insns. */
1014 else
1015 {
1019 else
1022 }
1023 m->is_equiv
1025 }
1026 }
1027 /* If this register is always set within a STRICT_LOW_PART
1028 or set to zero, then its high bytes are constant.
1029 So clear them outside the loop and within the loop
1030 just load the low bytes.
1031 We must check that the machine has an instruction to do so.
1032 Also, if the value loaded into the register
1033 depends on the same register, this cannot be done. */
1043 {
1046 {
1061 /* If the insn may not be executed on some cycles,
1062 we can't clear the whole reg; clear just high part.
1063 Not even if the reg is used only within this loop.
1064 Consider this:
1065 while (1)
1066 while (s != t) {
1067 if (foo ()) x = *s;
1068 use (x);
1069 }
1070 Clearing x before the inner loop could clobber a value
1071 being saved from the last time around the outer loop.
1072 However, if the reg is not used outside this loop
1073 and all uses of the register are in the same
1074 basic block as the store, there is no problem.
1076 If this insn was made by loop, we don't know its
1077 INSN_LUID and hence must make a conservative
1078 assumption. */
1081 || (labels_in_range_p
1085 else
1094 i++)
1096 /* Add M to the end of the chain MOVABLES. */
1098 }
1099 }
1100 }
1101 }
1102 /* Past a call insn, we get to insns which might not be executed
1103 because the call might exit. This matters for insns that trap.
1104 Constant and pure call insns always return, so they don't count. */
1107 /* Past a label or a jump, we get to insns for which we
1108 can't count on whether or how many times they will be
1109 executed during each iteration. Therefore, we can
1110 only move out sets of trivial variables
1111 (those not used after the loop). */
1112 /* Similar code appears twice in strength_reduce. */
1114 /* If we enter the loop in the middle, and scan around to the
1115 beginning, don't set maybe_never for that. This must be an
1116 unconditional jump, otherwise the code at the top of the
1117 loop might never be executed. Unconditional jumps are
1118 followed by a barrier then the loop_end. */
1124 {
1125 /* At the virtual top of a converted loop, insns are again known to
1126 be executed: logically, the loop begins here even though the exit
1127 code has been duplicated. */
1131 loop_depth++;
1133 loop_depth--;
1134 }
1135 }
1137 /* If one movable subsumes another, ignore that other. */
1141 /* For each movable insn, see if the reg that it loads
1142 leads when it dies right into another conditionally movable insn.
1143 If so, record that the second insn "forces" the first one,
1144 since the second can be moved only if the first is. */
1148 /* See if there are multiple movable insns that load the same value.
1149 If there are, make all but the first point at the first one
1150 through the `match' field, and add the priorities of them
1151 all together as the priority of the first. */
1155 /* Now consider each movable insn to decide whether it is worth moving.
1156 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1158 For machines with few registers this increases code size, so do not
1159 move moveables when optimizing for code size on such machines.
1160 (The 18 below is the value for i386.) */
1164 {
1167 /* Recalculate regs->array if move_movables has created new
1168 registers. */
1170 {
1176 ;
1181 }
1182 }
1184 /* Now candidates that still are negative are those not moved.
1185 Change regs->array[I].set_in_loop to indicate that those are not actually
1186 invariant. */
1191 /* Now that we've moved some things out of the loop, we might be able to
1192 hoist even more memory references. */
1195 /* Recalculate regs->array if load_mems has created new registers. */
1203 ;
1210 {
1212 /* Ensure our label doesn't go away. */
1223 }
1226 /* The movable information is required for strength reduction. */
1232 }
1233 \f
1234 /* Add elements to *OUTPUT to record all the pseudo-regs
1235 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1237 static void
1239 {
1247 {
1265 }
1269 {
1273 {
1282 }
1283 }
1284 }
1285 \f
1286 /* Check what regs are referred to in the libcall block ending with INSN,
1287 aside from those mentioned in the equivalent value.
1288 If there are none, return 0.
1289 If there are one or more, return an EXPR_LIST containing all of them. */
1291 static rtx
1293 {
1298 /* First, find all the regs used in the libcall block
1299 that are not mentioned as inputs to the result. */
1302 {
1307 }
1310 }
1311 \f
1312 /* Return 1 if all uses of REG
1313 are between INSN and the end of the basic block. */
1315 static int
1317 {
1319 rtx p;
1324 /* Search this basic block for the already recorded last use of the reg. */
1326 {
1328 {
1334 /* Ordinary insn: if this is the last use, we win. */
1340 /* Jump insn: if this is the last use, we win. */
1343 /* Otherwise, it's the end of the basic block, so we lose. */
1348 /* It's the end of the basic block, so we lose. */
1353 }
1354 }
1356 /* The "last use" that was recorded can't be found after the first
1357 use. This can happen when the last use was deleted while
1358 processing an inner loop, this inner loop was then completely
1359 unrolled, and the outer loop is always exited after the inner loop,
1360 so that everything after the first use becomes a single basic block. */
1362 }
1363 \f
1364 /* Compute the benefit of eliminating the insns in the block whose
1365 last insn is LAST. This may be a group of insns used to compute a
1366 value directly or can contain a library call. */
1368 static int
1370 {
1371 rtx insn;
1376 {
1379 routine. */
1383 benefit++;
1384 }
1387 }
1388 \f
1389 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1391 static rtx
1393 {
1395 {
1396 rtx temp;
1398 /* If first insn of libcall sequence, skip to end. */
1399 /* Do this at start of loop, since INSN is guaranteed to
1400 be an insn here. */
1405 do
1408 }
1411 }
1413 /* Ignore any movable whose insn falls within a libcall
1414 which is part of another movable.
1415 We make use of the fact that the movable for the libcall value
1416 was made later and so appears later on the chain. */
1418 static void
1420 {
1424 {
1425 /* Is this a movable for the value of a libcall? */
1428 {
1429 rtx insn;
1430 /* Check for earlier movables inside that range,
1431 and mark them invalid. We cannot use LUIDs here because
1432 insns created by loop.c for prior loops don't have LUIDs.
1433 Rather than reject all such insns from movables, we just
1434 explicitly check each insn in the libcall (since invariant
1435 libcalls aren't that common). */
1440 }
1441 }
1442 }
1444 /* For each movable insn, see if the reg that it loads
1445 leads when it dies right into another conditionally movable insn.
1446 If so, record that the second insn "forces" the first one,
1447 since the second can be moved only if the first is. */
1449 static void
1451 {
1455 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1457 {
1460 /* ??? Could this be a bug? What if CSE caused the
1461 register of M1 to be used after this insn?
1462 Since CSE does not update regno_last_uid,
1463 this insn M->insn might not be where it dies.
1464 But very likely this doesn't matter; what matters is
1465 that M's reg is computed from M1's reg. */
1470 /* If m->consec, m->set_src isn't valid. */
1474 /* Increase the priority of the moving the first insn
1475 since it permits the second to be moved as well.
1476 Likewise for insns already forced by the first insn. */
1478 {
1483 {
1486 }
1487 }
1488 }
1489 }
1490 \f
1491 /* Find invariant expressions that are equal and can be combined into
1492 one register. */
1494 static void
1496 {
1501 /* Regs that are set more than once are not allowed to match
1502 or be matched. I'm no longer sure why not. */
1503 /* Only pseudo registers are allowed to match or be matched,
1504 since move_movables does not validate the change. */
1505 /* Perhaps testing m->consec_sets would be more appropriate here? */
1512 {
1519 /* We want later insns to match the first one. Don't make the first
1520 one match any later ones. So start this loop at m->next. */
1526 /* A reg used outside the loop mustn't be eliminated. */
1528 /* A reg used for zero-extending mustn't be eliminated. */
1531 ||
1532 (
1533 /* Can combine regs with different modes loaded from the
1534 same constant only if the modes are the same or
1535 if both are integer modes with M wider or the same
1536 width as M1. The check for integer is redundant, but
1537 safe, since the only case of differing destination
1538 modes with equal sources is when both sources are
1539 VOIDmode, i.e., CONST_INT. */
1545 /* See if the source of M1 says it matches M. */
1552 {
1558 }
1559 }
1561 /* Now combine the regs used for zero-extension.
1562 This can be done for those not marked `global'
1563 provided their lives don't overlap. */
1567 {
1570 /* Combine all the registers for extension from mode MODE.
1571 Don't combine any that are used outside this loop. */
1575 {
1582 {
1583 /* First one: don't check for overlap, just record it. */
1586 }
1588 /* Make sure they extend to the same mode.
1589 (Almost always true.) */
1593 /* We already have one: check for overlap with those
1594 already combined together. */
1601 /* No overlap: we can combine this with the others. */
1607 overlap:
1608 ;
1609 }
1610 }
1612 /* Clean up. */
1614 }
1616 /* Returns the number of movable instructions in LOOP that were not
1617 moved outside the loop. */
1619 static int
1621 {
1630 }
1632 \f
1633 /* Return 1 if regs X and Y will become the same if moved. */
1635 static int
1637 {
1654 }
1656 /* Return 1 if X and Y are identical-looking rtx's.
1657 This is the Lisp function EQUAL for rtx arguments.
1659 If two registers are matching movables or a movable register and an
1660 equivalent constant, consider them equal. */
1662 static int
1665 {
1679 /* If we have a register and a constant, they may sometimes be
1680 equal. */
1683 {
1688 }
1691 {
1696 }
1698 /* Otherwise, rtx's of different codes cannot be equal. */
1702 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1703 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1708 /* These three types of rtx's can be compared nonrecursively. */
1717 /* Compare the elements. If any pair of corresponding elements
1718 fail to match, return 0 for the whole things. */
1722 {
1724 {
1736 /* Two vectors must have the same length. */
1740 /* And the corresponding elements must match. */
1759 /* These are just backpointers, so they don't matter. */
1765 /* It is believed that rtx's at this level will never
1766 contain anything but integers and other rtx's,
1767 except for within LABEL_REFs and SYMBOL_REFs. */
1770 }
1771 }
1773 }
1774 \f
1775 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1776 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1777 references is incremented once for each added note. */
1779 static void
1781 {
1785 rtx insn;
1788 {
1789 /* This code used to ignore labels that referred to dispatch tables to
1790 avoid flow generating (slightly) worse code.
1792 We no longer ignore such label references (see LABEL_REF handling in
1793 mark_jump_label for additional information). */
1796 {
1801 }
1802 }
1806 {
1812 }
1813 }
1814 \f
1815 /* Scan MOVABLES, and move the insns that deserve to be moved.
1816 If two matching movables are combined, replace one reg with the
1817 other throughout. */
1819 static void
1822 {
1827 rtx p;
1830 /* Map of pseudo-register replacements to handle combining
1831 when we move several insns that load the same value
1832 into different pseudo-registers. */
1837 {
1838 /* Describe this movable insn. */
1841 {
1862 }
1864 /* Ignore the insn if it's already done (it matched something else).
1865 Otherwise, see if it is now safe to move. */
1877 {
1879 rtx p;
1882 /* We have an insn that is safe to move.
1883 Compute its desirability. */
1894 /* An insn MUST be moved if we already moved something else
1895 which is safe only if this one is moved too: that is,
1896 if already_moved[REGNO] is nonzero. */
1898 /* An insn is desirable to move if the new lifetime of the
1899 register is no more than THRESHOLD times the old lifetime.
1900 If it's not desirable, it means the loop is so big
1901 that moving won't speed things up much,
1902 and it is liable to make register usage worse. */
1904 /* It is also desirable to move if it can be moved at no
1905 extra cost because something else was already moved. */
1908 || flag_move_all_movables
1913 {
1922 /* Now move the insns that set the reg. */
1925 {
1928 /* Find the end of this chain of matching regs.
1929 Thus, we load each reg in the chain from that one reg.
1930 And that reg is loaded with 0 directly,
1931 since it has ->match == 0. */
1937 /* Mark the moved, invariant reg as being allowed to
1938 share a hard reg with the other matching invariant. */
1942 regs_may_share
1945 regs_may_share));
1953 }
1954 /* If we are to re-generate the item being moved with a
1955 new move insn, first delete what we have and then emit
1956 the move insn before the loop. */
1958 {
1962 {
1963 /* If this is the first insn of a library call sequence,
1964 something is very wrong. */
1969 /* If this is the last insn of a libcall sequence, then
1970 delete every insn in the sequence except the last.
1971 The last insn is handled in the normal manner. */
1974 {
1978 }
1983 /* simplify_giv_expr expects that it can walk the insns
1984 at m->insn forwards and see this old sequence we are
1985 tossing here. delete_insn does preserve the next
1986 pointers, but when we skip over a NOTE we must fix
1987 it up. Otherwise that code walks into the non-deleted
1988 insn stream. */
1993 {
1994 /* Replace the original insn with a move from
1995 our newly created temp. */
2001 }
2002 }
2021 /* The more regs we move, the less we like moving them. */
2023 }
2024 else
2025 {
2027 {
2030 /* If first insn of libcall sequence, skip to end. */
2031 /* Do this at start of loop, since p is guaranteed to
2032 be an insn here. */
2037 /* If last insn of libcall sequence, move all
2038 insns except the last before the loop. The last
2039 insn is handled in the normal manner. */
2042 {
2050 {
2051 rtx body;
2052 rtx n;
2053 rtx next;
2060 /* Find the next insn after TEMP,
2061 not counting USE or NOTE insns. */
2069 /* If that is the call, this may be the insn
2070 that loads the function address.
2072 Extract the function address from the insn
2073 that loads it into a register.
2074 If this insn was cse'd, we get incorrect code.
2076 So emit a new move insn that copies the
2077 function address into the register that the
2078 call insn will use. flow.c will delete any
2079 redundant stores that we have created. */
2084 NULL_RTX)))
2085 {
2091 }
2092 /* We have the call insn.
2093 If it uses the register we suspect it might,
2094 load it with the correct address directly. */
2099 gen_move_insn
2103 {
2105 /* Because the USAGE information potentially
2106 contains objects other than hard registers
2107 we need to copy it. */
2111 }
2112 else
2121 }
2124 }
2126 {
2127 /* P sets REG to zero; but we should clear only
2128 the bits that are not covered by the mode
2129 m->savemode. */
2131 rtx sequence;
2132 rtx tem;
2135 tem = expand_simple_binop
2148 }
2150 {
2152 /* Because the USAGE information potentially
2153 contains objects other than hard registers
2154 we need to copy it. */
2158 }
2160 {
2161 rtx seq;
2162 /* The SET_SRC might not be invariant, so we must
2163 use the REG_EQUAL note. */
2176 }
2178 {
2186 }
2187 else
2191 {
2195 /* If there is a REG_EQUAL note present whose value
2196 is not loop invariant, then delete it, since it
2197 may cause problems with later optimization passes.
2198 It is possible for cse to create such notes
2199 like this as a result of record_jump_cond. */
2204 }
2213 /* If library call, now fix the REG_NOTES that contain
2214 insn pointers, namely REG_LIBCALL on FIRST
2215 and REG_RETVAL on I1. */
2217 {
2221 }
2227 /* simplify_giv_expr expects that it can walk the insns
2228 at m->insn forwards and see this old sequence we are
2229 tossing here. delete_insn does preserve the next
2230 pointers, but when we skip over a NOTE we must fix
2231 it up. Otherwise that code walks into the non-deleted
2232 insn stream. */
2237 {
2238 rtx seq;
2239 /* Replace the original insn with a move from
2240 our newly created temp. */
2246 }
2247 }
2249 /* The more regs we move, the less we like moving them. */
2251 }
2256 {
2257 /* Any other movable that loads the same register
2258 MUST be moved. */
2261 /* This reg has been moved out of one loop. */
2264 /* The reg set here is now invariant. */
2266 {
2270 }
2272 /* Change the length-of-life info for the register
2273 to say it lives at least the full length of this loop.
2274 This will help guide optimizations in outer loops. */
2277 /* This is the old insn before all the moved insns.
2278 We can't use the moved insn because it is out of range
2279 in uid_luid. Only the old insns have luids. */
2283 }
2285 /* Combine with this moved insn any other matching movables. */
2290 {
2291 rtx temp;
2293 /* Schedule the reg loaded by M1
2294 for replacement so that shares the reg of M.
2295 If the modes differ (only possible in restricted
2296 circumstances, make a SUBREG.
2298 Note this assumes that the target dependent files
2299 treat REG and SUBREG equally, including within
2300 GO_IF_LEGITIMATE_ADDRESS and in all the
2301 predicates since we never verify that replacing the
2302 original register with a SUBREG results in a
2303 recognizable insn. */
2306 else
2311 /* Get rid of the matching insn
2312 and prevent further processing of it. */
2315 /* If library call, delete all insns. */
2317 NULL_RTX)))
2319 else
2322 /* Any other movable that loads the same register
2323 MUST be moved. */
2326 /* The reg merged here is now invariant,
2327 if the reg it matches is invariant. */
2329 {
2333 i++)
2335 }
2336 }
2337 }
2340 }
2346 }
2351 /* Go through all the instructions in the loop, making
2352 all the register substitutions scheduled in REG_MAP. */
2356 {
2360 }
2362 /* Clean up. */
2365 }
2368 static void
2370 {
2373 else
2376 }
2379 static void
2381 {
2386 {
2389 }
2390 }
2391 \f
2392 #if 0
2393 /* Scan X and replace the address of any MEM in it with ADDR.
2394 REG is the address that MEM should have before the replacement. */
2396 static void
2398 {
2407 {
2419 /* Short cut for very common case. */
2424 /* Short cut for very common case. */
2429 /* If this MEM uses a reg other than the one we expected,
2430 something is wrong. */
2438 }
2442 {
2446 {
2450 }
2451 }
2452 }
2453 #endif
2454 \f
2455 /* Return the number of memory refs to addresses that vary
2456 in the rtx X. */
2458 static int
2460 {
2471 {
2488 }
2493 {
2497 {
2501 }
2502 }
2504 }
2505 \f
2506 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2507 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2508 `unknown_address_altered', `unknown_constant_address_altered', and
2509 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2510 list `store_mems' in LOOP. */
2512 static void
2514 {
2516 rtx insn;
2520 /* The label after END. Jumping here is just like falling off the
2521 end of the loop. We use next_nonnote_insn instead of next_label
2522 as a hedge against the (pathological) case where some actual insn
2523 might end up between the two. */
2542 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2547 {
2549 {
2552 }
2553 }
2557 {
2559 {
2562 {
2564 /* Count number of loops contained in this one. */
2566 }
2573 {
2576 }
2583 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2584 attached FUNCTION_USAGE expression list, not accounted for by the
2585 code above. We should note these to avoid missing dependencies in
2586 later references. */
2587 {
2588 rtx fusage_entry;
2592 {
2598 {
2603 }
2604 }
2605 }
2610 {
2614 {
2619 {
2622 }
2623 else
2624 {
2627 }
2629 do
2630 {
2632 {
2634 {
2635 /* Something tricky. */
2638 }
2641 {
2642 /* A jump outside the current loop. */
2645 }
2646 }
2650 }
2652 }
2653 else
2654 {
2655 /* A return, or something tricky. */
2657 }
2658 }
2659 /* Fall through. */
2680 }
2681 }
2683 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2685 anywhere. */
2687 /* We don't want loads for MEMs moved to a location before the
2688 one at which their stack memory becomes allocated. (Note
2689 that this is not a problem for malloc, etc., since those
2690 require actual function calls. */
2691 && ! current_function_calls_alloca
2692 /* There are ways to leave the loop other than falling off the
2693 end. */
2699 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2700 that loop_invariant_p and load_mems can use true_dependence
2701 to determine what is really clobbered. */
2703 {
2706 loop_info->store_mems
2708 }
2710 {
2714 loop_info->store_mems
2716 }
2717 }
2718 \f
2719 /* Invalidate all loops containing LABEL. */
2721 static void
2723 {
2727 }
2729 /* Scan the function looking for loops. Record the start and end of each loop.
2730 Also mark as invalid loops any loops that contain a setjmp or are branched
2731 to from outside the loop. */
2733 static void
2735 {
2736 rtx insn;
2737 rtx label;
2747 /* If there are jumps to undefined labels,
2748 treat them as jumps out of any/all loops.
2749 This also avoids writing past end of tables when there are no loops. */
2752 /* Find boundaries of loops, mark which loops are contained within
2753 loops, and invalidate loops that have setjmp. */
2758 {
2761 {
2765 num_loops++;
2789 }
2793 {
2794 /* In this case, we must invalidate our current loop and any
2795 enclosing loop. */
2797 {
2803 }
2804 }
2806 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2807 enclosing loop, but this doesn't matter. */
2809 }
2811 /* Any loop containing a label used in an initializer must be invalidated,
2812 because it can be jumped into from anywhere. */
2816 /* Any loop containing a label used for an exception handler must be
2817 invalidated, because it can be jumped into from anywhere. */
2820 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2821 loop that it is not contained within, that loop is marked invalid.
2822 If any INSN or CALL_INSN uses a label's address, then the loop containing
2823 that label is marked invalid, because it could be jumped into from
2824 anywhere.
2826 Also look for blocks of code ending in an unconditional branch that
2827 exits the loop. If such a block is surrounded by a conditional
2828 branch around the block, move the block elsewhere (see below) and
2829 invert the jump to point to the code block. This may eliminate a
2830 label in our loop and will simplify processing by both us and a
2831 possible second cse pass. */
2835 {
2839 {
2843 }
2850 /* See if this is an unconditional branch outside the loop. */
2858 {
2859 rtx p;
2865 /* Go backwards until we reach the start of the loop, a label,
2866 or a JUMP_INSN. */
2873 ;
2875 /* Check for the case where we have a jump to an inner nested
2876 loop, and do not perform the optimization in that case. */
2879 {
2882 {
2887 }
2888 }
2890 /* Make sure that the target of P is within the current loop. */
2896 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2897 we have a block of code to try to move.
2899 We look backward and then forward from the target of INSN
2900 to find a BARRIER at the same loop depth as the target.
2901 If we find such a BARRIER, we make a new label for the start
2902 of the block, invert the jump in P and point it to that label,
2903 and move the block of code to the spot we found. */
2908 /* Just ignore jumps to labels that were never emitted.
2909 These always indicate compilation errors. */
2913 /* If it's not safe to move the sequence, then we
2914 mustn't try. */
2917 {
2918 rtx target
2922 rtx tmp;
2924 /* Search for possible garbage past the conditional jumps
2925 and look for the last barrier. */
2933 /* Don't move things inside a tablejump. */
2946 /* Don't move things inside a tablejump. */
2957 {
2961 /* Ensure our label doesn't go away. */
2964 /* Verify that uid_loop is large enough and that
2965 we can invert P. */
2967 {
2970 /* If no suitable BARRIER was found, create a suitable
2971 one before TARGET. Since TARGET is a fall through
2972 path, we'll need to insert a jump around our block
2973 and add a BARRIER before TARGET.
2975 This creates an extra unconditional jump outside
2976 the loop. However, the benefits of removing rarely
2977 executed instructions from inside the loop usually
2978 outweighs the cost of the extra unconditional jump
2979 outside the loop. */
2981 {
2982 rtx temp;
2989 }
2991 /* Include the BARRIER after INSN and copy the
2992 block after LOC. */
2997 /* All those insns are now in TARGET_LOOP. */
3003 /* The label jumped to by INSN is no longer a loop
3004 exit. Unless INSN does not have a label (e.g.,
3005 it is a RETURN insn), search loop->exit_labels
3006 to find its label_ref, and remove it. Also turn
3007 off LABEL_OUTSIDE_LOOP_P bit. */
3009 {
3011 r;
3014 {
3018 else
3021 }
3027 /* If we didn't find it, then something is
3028 wrong. */
3031 }
3033 /* P is now a jump outside the loop, so it must be put
3034 in loop->exit_labels, and marked as such.
3035 The easiest way to do this is to just call
3036 mark_loop_jump again for P. */
3039 /* If INSN now jumps to the insn after it,
3040 delete INSN. */
3045 }
3047 /* Continue the loop after where the conditional
3048 branch used to jump, since the only branch insn
3049 in the block (if it still remains) is an inter-loop
3050 branch and hence needs no processing. */
3056 /* This loop will be continued with NEXT_INSN (insn). */
3058 }
3059 }
3060 }
3061 }
3062 }
3064 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3065 loops it is contained in, mark the target loop invalid.
3067 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3069 static void
3071 {
3077 {
3089 /* There could be a label reference in here. */
3101 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3113 /* Link together all labels that branch outside the loop. This
3114 is used by final_[bg]iv_value and the loop unrolling code. Also
3115 mark this LABEL_REF so we know that this branch should predict
3116 false. */
3118 /* A check to make sure the label is not in an inner nested loop,
3119 since this does not count as a loop exit. */
3121 {
3126 }
3127 else
3131 {
3140 }
3142 /* If this is inside a loop, but not in the current loop or one enclosed
3143 by it, it invalidates at least one loop. */
3148 /* We must invalidate every nested loop containing the target of this
3149 label, except those that also contain the jump insn. */
3152 {
3153 /* Stop when we reach a loop that also contains the jump insn. */
3158 /* If we get here, we know we need to invalidate a loop. */
3165 }
3169 /* If this is not setting pc, ignore. */
3191 /* Strictly speaking this is not a jump into the loop, only a possible
3192 jump out of the loop. However, we have no way to link the destination
3193 of this jump onto the list of exit labels. To be safe we mark this
3194 loop and any containing loops as invalid. */
3196 {
3198 {
3204 }
3205 }
3207 }
3208 }
3209 \f
3210 /* Return nonzero if there is a label in the range from
3211 insn INSN to and including the insn whose luid is END
3212 INSN must have an assigned luid (i.e., it must not have
3213 been previously created by loop.c). */
3215 static int
3217 {
3219 {
3223 }
3226 }
3228 /* Record that a memory reference X is being set. */
3230 static void
3233 {
3239 /* Count number of memory writes.
3240 This affects heuristics in strength_reduce. */
3243 /* BLKmode MEM means all memory is clobbered. */
3245 {
3248 else
3252 }
3256 }
3258 /* X is a value modified by an INSN that references a biv inside a loop
3259 exit test (ie, X is somehow related to the value of the biv). If X
3260 is a pseudo that is used more than once, then the biv is (effectively)
3261 used more than once. DATA is a pointer to a loop_regs structure. */
3263 static void
3265 {
3280 /* If we do not have usage information, or if we know the register
3281 is used more than once, note that fact for check_dbra_loop. */
3286 }
3287 \f
3288 /* Return nonzero if the rtx X is invariant over the current loop.
3290 The value is 2 if we refer to something only conditionally invariant.
3292 A memory ref is invariant if it is not volatile and does not conflict
3293 with anything stored in `loop_info->store_mems'. */
3295 int
3297 {
3304 rtx mem_list_entry;
3310 {
3318 /* A LABEL_REF is normally invariant, however, if we are unrolling
3319 loops, and this label is inside the loop, then it isn't invariant.
3320 This is because each unrolled copy of the loop body will have
3321 a copy of this label. If this was invariant, then an insn loading
3322 the address of this label into a register might get moved outside
3323 the loop, and then each loop body would end up using the same label.
3325 We don't know the loop bounds here though, so just fail for all
3326 labels. */
3329 else
3338 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3339 since the reg might be set by initialization within the loop. */
3350 /* Out-of-range regs can occur when we are called from unrolling.
3351 These registers created by the unroller are set in the loop,
3352 hence are never invariant.
3353 Other out-of-range regs can be generated by load_mems; those that
3354 are written to in the loop are not invariant, while those that are
3355 not written to are invariant. It would be easy for load_mems
3356 to set n_times_set correctly for these registers, however, there
3357 is no easy way to distinguish them from registers created by the
3358 unroller. */
3369 /* Volatile memory references must be rejected. Do this before
3370 checking for read-only items, so that volatile read-only items
3371 will be rejected also. */
3375 /* See if there is any dependence between a store and this load. */
3378 {
3384 }
3386 /* It's not invalidated by a store in memory
3387 but we must still verify the address is invariant. */
3391 /* Don't mess with insns declared volatile. */
3398 }
3402 {
3404 {
3410 }
3412 {
3415 {
3421 }
3423 }
3424 }
3427 }
3428 \f
3429 /* Return nonzero if all the insns in the loop that set REG
3430 are INSN and the immediately following insns,
3431 and if each of those insns sets REG in an invariant way
3432 (not counting uses of REG in them).
3434 The value is 2 if some of these insns are only conditionally invariant.
3436 We assume that INSN itself is the first set of REG
3437 and that its source is invariant. */
3439 static int
3441 rtx insn)
3442 {
3446 rtx temp;
3447 /* Number of sets we have to insist on finding after INSN. */
3453 /* If N_SETS hit the limit, we can't rely on its value. */
3460 {
3462 rtx set;
3467 /* If library call, skip to end of it. */
3476 {
3481 {
3482 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3483 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3484 notes are OK. */
3490 }
3491 }
3493 count--;
3495 {
3498 }
3499 }
3502 /* If loop_invariant_p ever returned 2, we return 2. */
3504 }
3505 \f
3506 /* Look at all uses (not sets) of registers in X. For each, if it is
3507 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3508 a different insn, set USAGE[REGNO] to const0_rtx. */
3510 static void
3512 {
3524 {
3525 /* Don't count SET_DEST if it is a REG; otherwise count things
3526 in SET_DEST because if a register is partially modified, it won't
3527 show up as a potential movable so we don't care how USAGE is set
3528 for it. */
3532 }
3533 else
3535 {
3541 }
3542 }
3543 \f
3544 /* Count and record any set in X which is contained in INSN. Update
3545 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3546 in X. */
3548 static void
3550 {
3552 /* Don't move a reg that has an explicit clobber.
3553 It's not worth the pain to try to do it correctly. */
3557 {
3565 {
3569 {
3570 /* If this is the first setting of this reg
3571 in current basic block, and it was set before,
3572 it must be set in two basic blocks, so it cannot
3573 be moved out of the loop. */
3577 /* If this is not first setting in current basic block,
3578 see if reg was used in between previous one and this.
3579 If so, neither one can be moved. */
3586 }
3587 }
3588 }
3589 }
3590 \f
3591 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3592 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3593 contained in insn INSN is used by any insn that precedes INSN in
3594 cyclic order starting from the loop entry point.
3596 We don't want to use INSN_LUID here because if we restrict INSN to those
3597 that have a valid INSN_LUID, it means we cannot move an invariant out
3598 from an inner loop past two loops. */
3600 static int
3602 {
3604 rtx p;
3606 /* Scan forward checking for register usage. If we hit INSN, we
3607 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3609 {
3615 }
3618 }
3619 \f
3621 /* Information we collect about arrays that we might want to prefetch. */
3622 struct prefetch_info
3623 {
3627 index. */
3628 HOST_WIDE_INT index;
3630 iteration. */
3632 prefetch area in one iteration. */
3634 This is set only for loops with known
3635 iteration counts and is 0xffffffff
3636 otherwise. */
3640 };
3642 /* Data used by check_store function. */
3643 struct check_store_data
3644 {
3645 rtx mem_address;
3647 };
3653 /* Set mem_write when mem_address is found. Used as callback to
3654 note_stores. */
3655 static void
3657 {
3662 }
3663 \f
3664 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3665 important to get some addresses combined. Later more sophisticated
3666 transformations can be added when necessary.
3668 ??? Same trick with swapping operand is done at several other places.
3669 It can be nice to develop some common way to handle this. */
3671 static int
3673 {
3685 {
3690 }
3692 /* Compare the elements. If any pair of corresponding elements fails to
3693 match, return 0 for the whole thing. */
3697 {
3699 {
3711 /* Two vectors must have the same length. */
3715 /* And the corresponding elements must match. */
3733 /* These are just backpointers, so they don't matter. */
3739 /* It is believed that rtx's at this level will never
3740 contain anything but integers and other rtx's,
3741 except for within LABEL_REFs and SYMBOL_REFs. */
3744 }
3745 }
3747 }
3748 \f
3749 /* Remove constant addition value from the expression X (when present)
3750 and return it. */
3752 static HOST_WIDE_INT
3754 {
3758 /* Avoid clobbering a shared CONST expression. */
3760 {
3764 {
3767 }
3769 }
3772 {
3775 }
3777 /* For plus expression recurse on ourself. */
3779 {
3783 /* In case our parameter was constant, remove extra zero from the
3784 expression. */
3789 }
3792 }
3794 /* Attempt to identify accesses to arrays that are most likely to cause cache
3795 misses, and emit prefetch instructions a few prefetch blocks forward.
3797 To detect the arrays we use the GIV information that was collected by the
3798 strength reduction pass.
3800 The prefetch instructions are generated after the GIV information is done
3801 and before the strength reduction process. The new GIVs are injected into
3802 the strength reduction tables, so the prefetch addresses are optimized as
3803 well.
3805 GIVs are split into base address, stride, and constant addition values.
3806 GIVs with the same address, stride and close addition values are combined
3807 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3808 for write instructions can be used for the block we write to, on machines
3809 that support write prefetches.
3811 Several heuristics are used to determine when to prefetch. They are
3812 controlled by defined symbols that can be overridden for each target. */
3814 static void
3816 {
3832 /* Consider only loops w/o calls. When a call is done, the loop is probably
3833 slow enough to read the memory. */
3835 {
3840 }
3842 /* Don't prefetch in loops known to have few iterations. */
3846 {
3851 }
3853 /* Search all induction variables and pick those interesting for the prefetch
3854 machinery. */
3856 {
3862 /* Expect all BIVs to be executed in each iteration. This makes our
3863 analysis more conservative. */
3865 {
3866 /* Discard non-constant additions that we can't handle well yet, and
3867 BIVs that are executed multiple times; such BIVs ought to be
3868 handled in the nested loop. We accept not_every_iteration BIVs,
3869 since these only result in larger strides and make our
3870 heuristics more conservative. */
3872 {
3874 {
3880 }
3882 }
3885 {
3887 {
3893 }
3895 }
3899 }
3905 {
3906 rtx address;
3907 rtx temp;
3916 /* See whether an induction variable is interesting to us and if
3917 not, report the reason. */
3921 /* We are interested only in constant stride memory references
3922 in order to be able to compute density easily. */
3926 else
3927 {
3930 {
3933 }
3935 /* On some targets, reversed order prefetches are not
3936 worthwhile. */
3940 /* Prefetch of accesses with an extreme stride might not be
3941 worthwhile, either. */
3946 /* Ignore GIVs with varying add values; we can't predict the
3947 value for the next iteration. */
3951 /* Ignore GIVs in the nested loops; they ought to have been
3952 handled already. */
3955 }
3958 {
3964 }
3966 /* Determine the pointer to the basic array we are examining. It is
3967 the sum of the BIV's initial value and the GIV's add_val. */
3977 /* When the GIV is not always executed, we might be better off by
3978 not dirtying the cache pages. */
3981 else
3982 {
3987 }
3989 /* Attempt to find another prefetch to the same array and see if we
3990 can merge this one. */
3994 {
3995 /* In case both access same array (same location
3996 just with small difference in constant indexes), merge
3997 the prefetches. Just do the later and the earlier will
3998 get prefetched from previous iteration.
3999 The artificial threshold should not be too small,
4000 but also not bigger than small portion of memory usually
4001 traversed by single loop. */
4004 {
4013 }
4017 {
4022 }
4023 }
4025 /* Merging failed. */
4027 {
4035 num_prefetches++;
4037 {
4042 }
4043 }
4044 }
4045 }
4048 {
4051 /* Attempt to calculate the total number of bytes fetched by all
4052 iterations of the loop. Avoid overflow. */
4057 else
4062 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4067 {
4072 }
4073 else
4074 {
4080 }
4081 else
4084 /* Find how many prefetch instructions we'll use within the loop. */
4086 {
4092 }
4093 }
4095 /* Determine how many iterations ahead to prefetch within the loop, based
4096 on how many prefetches we currently expect to do within the loop. */
4098 {
4100 {
4106 }
4107 }
4108 /* We'll also use AHEAD to determine how many prefetch instructions to
4109 emit before a loop, so don't leave it zero. */
4114 {
4115 /* Update if we've decided not to prefetch anything within the loop. */
4119 /* Find how many prefetch instructions we'll use before the loop. */
4121 {
4129 }
4132 {
4152 }
4153 }
4156 {
4157 /* Record that this loop uses prefetch instructions. */
4161 {
4166 }
4167 }
4170 {
4174 {
4176 rtx insn;
4180 rtx seq;
4182 /* We can save some effort by offsetting the address on
4183 architectures with offsettable memory references. */
4186 else
4187 {
4193 }
4196 /* Make sure the address operand is valid for prefetch. */
4206 /* Check all insns emitted and record the new GIV
4207 information. */
4210 {
4215 }
4216 }
4219 {
4220 /* Emit insns before the loop to fetch the first cache lines or,
4221 if we're not prefetching within the loop, everything we expect
4222 to need. */
4224 {
4232 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4233 non-constant INIT_VAL to have the same mode as REG, which
4234 in this case we know to be Pmode. */
4236 {
4237 rtx seq;
4244 }
4250 loop_start);
4251 }
4252 }
4253 }
4256 }
4257 \f
4258 /* Communication with routines called via `note_stores'. */
4262 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4266 /* ??? Unfinished optimizations, and possible future optimizations,
4267 for the strength reduction code. */
4269 /* ??? The interaction of biv elimination, and recognition of 'constant'
4270 bivs, may cause problems. */
4272 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4273 performance problems.
4275 Perhaps don't eliminate things that can be combined with an addressing
4276 mode. Find all givs that have the same biv, mult_val, and add_val;
4277 then for each giv, check to see if its only use dies in a following
4278 memory address. If so, generate a new memory address and check to see
4279 if it is valid. If it is valid, then store the modified memory address,
4280 otherwise, mark the giv as not done so that it will get its own iv. */
4282 /* ??? Could try to optimize branches when it is known that a biv is always
4283 positive. */
4285 /* ??? When replace a biv in a compare insn, we should replace with closest
4286 giv so that an optimized branch can still be recognized by the combiner,
4287 e.g. the VAX acb insn. */
4289 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4290 was rerun in loop_optimize whenever a register was added or moved.
4291 Also, some of the optimizations could be a little less conservative. */
4292 \f
4293 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4294 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4295 callback.
4297 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4298 least once for every loop iteration except for the last one.
4300 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4301 loop iteration.
4302 */
4303 void
4305 {
4310 rtx p;
4312 /* If loop_scan_start points to the loop exit test, we have to be wary of
4313 subversive use of gotos inside expression statements. */
4317 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4321 {
4324 /* Past CODE_LABEL, we get to insns that may be executed multiple
4325 times. The only way we can be sure that they can't is if every
4326 jump insn between here and the end of the loop either
4327 returns, exits the loop, is a jump to a location that is still
4328 behind the label, or is a jump to the loop start. */
4331 {
4337 {
4342 {
4345 else
4349 }
4357 {
4360 }
4361 }
4362 }
4364 /* Past a jump, we get to insns for which we can't count
4365 on whether they will be executed during each iteration. */
4366 /* This code appears twice in strength_reduce. There is also similar
4367 code in scan_loop. */
4369 /* If we enter the loop in the middle, and scan around to the
4370 beginning, don't set not_every_iteration for that.
4371 This can be any kind of jump, since we want to know if insns
4372 will be executed if the loop is executed. */
4377 {
4380 /* If this is a jump outside the loop, then it also doesn't
4381 matter. Check to see if the target of this branch is on the
4382 loop->exits_labels list. */
4390 }
4393 {
4394 /* At the virtual top of a converted loop, insns are again known to
4395 be executed each iteration: logically, the loop begins here
4396 even though the exit code has been duplicated.
4398 Insns are also again known to be executed each iteration at
4399 the LOOP_CONT note. */
4405 loop_depth++;
4407 loop_depth--;
4408 }
4410 /* Note if we pass a loop latch. If we do, then we can not clear
4411 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4412 a loop since a jump before the last CODE_LABEL may have started
4413 a new loop iteration.
4415 Note that LOOP_TOP is only set for rotated loops and we need
4416 this check for all loops, so compare against the CODE_LABEL
4417 which immediately follows LOOP_START. */
4422 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4423 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4424 or not an insn is known to be executed each iteration of the
4425 loop, whether or not any iterations are known to occur.
4427 Therefore, if we have just passed a label and have no more labels
4428 between here and the test insn of the loop, and we have not passed
4429 a jump to the top of the loop, then we know these insns will be
4430 executed each iteration. */
4433 && !past_loop_latch
4438 }
4439 }
4440 \f
4441 static void
4443 {
4446 /* Temporary list pointers for traversing ivs->list. */
4453 /* Scan ivs->list to remove all regs that proved not to be bivs.
4454 Make a sanity check against regs->n_times_set. */
4456 {
4458 /* Above happens if register modified by subreg, etc. */
4459 /* Make sure it is not recognized as a basic induction var: */
4461 /* If never incremented, it is invariant that we decided not to
4462 move. So leave it alone. */
4464 {
4475 }
4476 else
4477 {
4482 }
4483 }
4484 }
4487 /* Determine how BIVS are initialized by looking through pre-header
4488 extended basic block. */
4489 static void
4491 {
4493 /* Temporary list pointers for traversing ivs->list. */
4496 rtx p;
4498 /* Find initial value for each biv by searching backwards from loop_start,
4499 halting at first label. Also record any test condition. */
4503 {
4504 rtx test;
4514 /* Record any test of a biv that branches around the loop if no store
4515 between it and the start of loop. We only care about tests with
4516 constants and registers and only certain of those. */
4526 {
4527 /* If an NE test, we have an initial value! */
4529 {
4533 }
4534 else
4536 }
4537 }
4538 }
4541 /* Look at the each biv and see if we can say anything better about its
4542 initial value from any initializing insns set up above. (This is done
4543 in two passes to avoid missing SETs in a PARALLEL.) */
4544 static void
4546 {
4548 /* Temporary list pointers for traversing ivs->list. */
4553 {
4554 rtx src;
4555 rtx note;
4560 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4561 is a constant, use the value of that. */
4567 else
4580 {
4584 {
4587 }
4588 }
4589 /* If we can't make it a giv,
4590 let biv keep initial value of "itself". */
4593 }
4594 }
4597 /* Search the loop for general induction variables. */
4599 static void
4601 {
4603 }
4606 /* For each giv for which we still don't know whether or not it is
4607 replaceable, check to see if it is replaceable because its final value
4608 can be calculated. */
4610 static void
4612 {
4617 {
4623 }
4624 }
4627 /* Return nonzero if it is possible to eliminate the biv BL provided
4628 all givs are reduced. This is possible if either the reg is not
4629 used outside the loop, or we can compute what its final value will
4630 be. */
4632 static int
4635 {
4636 /* For architectures with a decrement_and_branch_until_zero insn,
4637 don't do this if we put a REG_NONNEG note on the endtest for this
4638 biv. */
4640 #ifdef HAVE_decrement_and_branch_until_zero
4642 {
4647 }
4648 #endif
4650 /* Check that biv is used outside loop or if it has a final value.
4651 Compare against bl->init_insn rather than loop->start. We aren't
4652 concerned with any uses of the biv between init_insn and
4653 loop->start since these won't be affected by the value of the biv
4654 elsewhere in the function, so long as init_insn doesn't use the
4655 biv itself. */
4666 {
4674 }
4676 }
4679 /* Reduce each giv of BL that we have decided to reduce. */
4681 static void
4683 {
4687 {
4690 {
4693 /* If the code for derived givs immediately below has already
4694 allocated a new_reg, we must keep it. */
4698 #ifdef AUTO_INC_DEC
4699 /* If the target has auto-increment addressing modes, and
4700 this is an address giv, then try to put the increment
4701 immediately after its use, so that flow can create an
4702 auto-increment addressing mode. */
4703 /* Don't do this for loops entered at the bottom, to avoid
4704 this invalid transformation:
4705 jmp L; -> jmp L;
4706 TOP: TOP:
4707 use giv use giv
4708 L: inc giv
4709 inc biv L:
4710 test biv test giv
4711 cbr TOP cbr TOP
4712 */
4715 /* We don't handle reversed biv's because bl->biv->insn
4716 does not have a valid INSN_LUID. */
4721 {
4722 /* If other giv's have been combined with this one, then
4723 this will work only if all uses of the other giv's occur
4724 before this giv's insn. This is difficult to check.
4726 We simplify this by looking for the common case where
4727 there is one DEST_REG giv, and this giv's insn is the
4728 last use of the dest_reg of that DEST_REG giv. If the
4729 increment occurs after the address giv, then we can
4730 perform the optimization. (Otherwise, the increment
4731 would have to go before other_giv, and we would not be
4732 able to combine it with the address giv to get an
4733 auto-inc address.) */
4735 {
4740 {
4743 else
4745 }
4752 }
4753 /* Check for case where increment is before the address
4754 giv. Do this test in "loop order". */
4763 else
4766 #ifdef HAVE_cc0
4767 {
4768 rtx prev;
4770 /* We can't put an insn immediately after one setting
4771 cc0, or immediately before one using cc0. */
4778 }
4779 #endif
4783 }
4784 #endif
4786 /* For each place where the biv is incremented, add an insn
4787 to increment the new, reduced reg for the giv. */
4789 {
4790 rtx insert_before;
4792 /* Skip if location is the same as a previous one. */
4799 else
4807 /* A multiply is acceptable here
4808 since this is presumed to be seldom executed. */
4812 }
4814 /* Add code at loop start to initialize giv's reduced reg. */
4819 }
4820 }
4821 }
4824 /* Check for givs whose first use is their definition and whose
4825 last use is the definition of another giv. If so, it is likely
4826 dead and should not be used to derive another giv nor to
4827 eliminate a biv. */
4829 static void
4831 {
4835 {
4842 {
4848 }
4849 }
4850 }
4853 static void
4855 {
4859 {
4866 /* Update expression if this was combined, in case other giv was
4867 replaced. */
4872 /* See if this register is known to be a pointer to something. If
4873 so, see if we can find the alignment. First see if there is a
4874 destination register that is a pointer. If so, this shares the
4875 alignment too. Next see if we can deduce anything from the
4876 computational information. If not, and this is a DEST_ADDR
4877 giv, at least we know that it's a pointer, though we don't know
4878 the alignment. */
4886 {
4895 }
4899 {
4907 }
4912 /* Store reduced reg as the address in the memref where we found
4913 this giv. */
4916 {
4918 }
4919 else
4920 {
4922 rtx note;
4924 /* Not replaceable; emit an insn to set the original giv reg from
4925 the reduced giv, same as above. */
4930 /* The original insn may have a REG_EQUAL note. This note is
4931 now incorrect and may result in invalid substitutions later.
4932 The original insn is dead, but may be part of a libcall
4933 sequence, which doesn't seem worth the bother of handling. */
4937 }
4939 /* When a loop is reversed, givs which depend on the reversed
4940 biv, and which are live outside the loop, must be set to their
4941 correct final value. This insn is only needed if the giv is
4942 not replaceable. The correct final value is the same as the
4943 value that the giv starts the reversed loop with. */
4954 {
4959 }
4960 }
4961 }
4964 static int
4967 rtx test_reg)
4968 {
4977 /* Reduce benefit if not replaceable, since we will insert a
4978 move-insn to replace the insn that calculates this giv. Don't do
4979 this unless the giv is a user variable, since it will often be
4980 marked non-replaceable because of the duplication of the exit
4981 code outside the loop. In such a case, the copies we insert are
4982 dead and will be deleted. So they don't have a cost. Similar
4983 situations exist. */
4984 /* ??? The new final_[bg]iv_value code does a much better job of
4985 finding replaceable giv's, and hence this code may no longer be
4986 necessary. */
4991 /* Decrease the benefit to count the add-insns that we will insert
4992 to increment the reduced reg for the giv. ??? This can
4993 overestimate the run-time cost of the additional insns, e.g. if
4994 there are multiple basic blocks that increment the biv, but only
4995 one of these blocks is executed during each iteration. There is
4996 no good way to detect cases like this with the current structure
4997 of the loop optimizer. This code is more accurate for
4998 determining code size than run-time benefits. */
5001 /* Decide whether to strength-reduce this giv or to leave the code
5002 unchanged (recompute it from the biv each time it is used). This
5003 decision can be made independently for each giv. */
5005 #ifdef AUTO_INC_DEC
5006 /* Attempt to guess whether autoincrement will handle some of the
5007 new add insns; if so, increase BENEFIT (undo the subtraction of
5008 add_cost that was done above). */
5010 /* Increasing the benefit is risky, since this is only a guess.
5011 Avoid increasing register pressure in cases where there would
5012 be no other benefit from reducing this giv. */
5015 {
5030 }
5031 #endif
5034 }
5037 /* Free IV structures for LOOP. */
5039 static void
5041 {
5048 {
5054 {
5057 }
5059 {
5062 }
5066 }
5067 }
5070 /* Perform strength reduction and induction variable elimination.
5072 Pseudo registers created during this function will be beyond the
5073 last valid index in several tables including
5074 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5075 problem here, because the added registers cannot be givs outside of
5076 their loop, and hence will never be reconsidered. But scan_loop
5077 must check regnos to make sure they are in bounds. */
5079 static void
5081 {
5085 rtx p;
5086 /* Temporary list pointer for traversing ivs->list. */
5088 /* Ratio of extra register life span we can justify
5089 for saving an instruction. More if loop doesn't call subroutines
5090 since in that case saving an insn makes more difference
5091 and more registers are available. */
5092 /* ??? could set this to last value of threshold in move_movables */
5094 /* Map of pseudo-register replacements. */
5106 /* Find all BIVs in loop. */
5109 /* Exit if there are no bivs. */
5111 {
5112 /* Can still unroll the loop anyways, but indicate that there is no
5113 strength reduction info available. */
5119 }
5121 /* Determine how BIVS are initialized by looking through pre-header
5122 extended basic block. */
5125 /* Look at the each biv and see if we can say anything better about its
5126 initial value from any initializing insns set up above. */
5129 /* Search the loop for general induction variables. */
5132 /* Try to calculate and save the number of loop iterations. This is
5133 set to zero if the actual number can not be calculated. This must
5134 be called after all giv's have been identified, since otherwise it may
5135 fail if the iteration variable is a giv. */
5138 #ifdef HAVE_prefetch
5141 #endif
5143 /* Now for each giv for which we still don't know whether or not it is
5144 replaceable, check to see if it is replaceable because its final value
5145 can be calculated. This must be done after loop_iterations is called,
5146 so that final_giv_value will work correctly. */
5149 /* Try to prove that the loop counter variable (if any) is always
5150 nonnegative; if so, record that fact with a REG_NONNEG note
5151 so that "decrement and branch until zero" insn can be used. */
5154 /* Create reg_map to hold substitutions for replaceable giv regs.
5155 Some givs might have been made from biv increments, so look at
5156 ivs->reg_iv_type for a suitable size. */
5160 /* Examine each iv class for feasibility of strength reduction/induction
5161 variable elimination. */
5164 {
5168 /* Test whether it will be possible to eliminate this biv
5169 provided all givs are reduced. */
5172 /* This will be true at the end, if all givs which depend on this
5173 biv have been strength reduced.
5174 We can't (currently) eliminate the biv unless this is so. */
5177 /* Check each extension dependent giv in this class to see if its
5178 root biv is safe from wrapping in the interior mode. */
5181 /* Combine all giv's for this iv_class. */
5185 {
5193 /* If an insn is not to be strength reduced, then set its ignore
5194 flag, and clear bl->all_reduced. */
5196 /* A giv that depends on a reversed biv must be reduced if it is
5197 used after the loop exit, otherwise, it would have the wrong
5198 value after the loop exit. To make it simple, just reduce all
5199 of such giv's whether or not we know they are used after the loop
5200 exit. */
5205 {
5213 }
5214 else
5215 {
5216 /* Check that we can increment the reduced giv without a
5217 multiply insn. If not, reject it. */
5222 {
5230 }
5231 }
5232 }
5234 /* Check for givs whose first use is their definition and whose
5235 last use is the definition of another giv. If so, it is likely
5236 dead and should not be used to derive another giv nor to
5237 eliminate a biv. */
5240 /* Reduce each giv that we decided to reduce. */
5243 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5244 as not reduced.
5246 For each giv register that can be reduced now: if replaceable,
5247 substitute reduced reg wherever the old giv occurs;
5248 else add new move insn "giv_reg = reduced_reg". */
5251 /* All the givs based on the biv bl have been reduced if they
5252 merit it. */
5254 /* For each giv not marked as maybe dead that has been combined with a
5255 second giv, clear any "maybe dead" mark on that second giv.
5256 v->new_reg will either be or refer to the register of the giv it
5257 combined with.
5259 Doing this clearing avoids problems in biv elimination where
5260 a giv's new_reg is a complex value that can't be put in the
5261 insn but the giv combined with (with a reg as new_reg) is
5262 marked maybe_dead. Since the register will be used in either
5263 case, we'd prefer it be used from the simpler giv. */
5269 /* Try to eliminate the biv, if it is a candidate.
5270 This won't work if ! bl->all_reduced,
5271 since the givs we planned to use might not have been reduced.
5273 We have to be careful that we didn't initially think we could
5274 eliminate this biv because of a giv that we now think may be
5275 dead and shouldn't be used as a biv replacement.
5277 Also, there is the possibility that we may have a giv that looks
5278 like it can be used to eliminate a biv, but the resulting insn
5279 isn't valid. This can happen, for example, on the 88k, where a
5280 JUMP_INSN can compare a register only with zero. Attempts to
5281 replace it with a compare with a constant will fail.
5283 Note that in cases where this call fails, we may have replaced some
5284 of the occurrences of the biv with a giv, but no harm was done in
5285 doing so in the rare cases where it can occur. */
5289 {
5290 /* ?? If we created a new test to bypass the loop entirely,
5291 or otherwise drop straight in, based on this test, then
5292 we might want to rewrite it also. This way some later
5293 pass has more hope of removing the initialization of this
5294 biv entirely. */
5296 /* If final_value != 0, then the biv may be used after loop end
5297 and we must emit an insn to set it just in case.
5299 Reversed bivs already have an insn after the loop setting their
5300 value, so we don't need another one. We can't calculate the
5301 proper final value for such a biv here anyways. */
5310 }
5311 /* See above note wrt final_value. But since we couldn't eliminate
5312 the biv, we must set the value after the loop instead of before. */
5316 }
5318 /* Go through all the instructions in the loop, making all the
5319 register substitutions scheduled in REG_MAP. */
5324 {
5328 }
5331 {
5332 /* When we completely unroll a loop we will likely not need the increment
5333 of the loop BIV and we will not need the conditional branch at the
5334 end of the loop. */
5337 #ifdef HAVE_cc0
5338 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5339 need the comparison before the conditional branch at the end of the
5340 loop. */
5342 #endif
5344 /* We'll need one copy for each loop iteration. */
5347 /* A little slop to account for the ability to remove initialization
5348 code, better CSE, and other secondary benefits of completely
5349 unrolling some loops. */
5352 /* Clamp the value. */
5355 }
5357 /* Unroll loops from within strength reduction so that we can use the
5358 induction variable information that strength_reduce has already
5359 collected. Always unroll loops that would be as small or smaller
5360 unrolled than when rolled. */
5373 }
5374 \f
5375 /*Record all basic induction variables calculated in the insn. */
5376 static rtx
5379 {
5381 rtx set;
5382 rtx dest_reg;
5383 rtx inc_val;
5384 rtx mult_val;
5390 {
5395 {
5400 {
5401 /* It is a possible basic induction variable.
5402 Create and initialize an induction structure for it. */
5409 }
5412 }
5413 }
5415 }
5416 \f
5417 /* Record all givs calculated in the insn.
5418 A register is a giv if: it is only set once, it is a function of a
5419 biv and a constant (or invariant), and it is not a biv. */
5420 static rtx
5423 {
5426 rtx set;
5427 /* Look for a general induction variable in a register. */
5432 {
5433 rtx src_reg;
5434 rtx dest_reg;
5435 rtx add_val;
5436 rtx mult_val;
5437 rtx ext_val;
5440 rtx last_consec_insn;
5449 /* Equivalent expression is a giv. */
5454 /* Don't try to handle any regs made by loop optimization.
5455 We have nothing on them in regno_first_uid, etc. */
5457 /* Don't recognize a BASIC_INDUCT_VAR here. */
5459 /* This must be the only place where the register is set. */
5461 /* or all sets must be consecutive and make a giv. */
5466 {
5469 /* If this is a library call, increase benefit. */
5473 /* Skip the consecutive insns, if there are any. */
5481 }
5482 }
5484 /* Look for givs which are memory addresses. */
5487 maybe_multiple);
5489 /* Update the status of whether giv can derive other givs. This can
5490 change when we pass a label or an insn that updates a biv. */
5495 }
5496 \f
5497 /* Return 1 if X is a valid source for an initial value (or as value being
5498 compared against in an initial test).
5500 X must be either a register or constant and must not be clobbered between
5501 the current insn and the start of the loop.
5503 INSN is the insn containing X. */
5505 static int
5507 {
5511 /* Only consider pseudos we know about initialized in insns whose luids
5512 we know. */
5517 /* Don't use call-clobbered registers across a call which clobbers it. On
5518 some machines, don't use any hard registers at all. */
5520 && (SMALL_REGISTER_CLASSES
5524 /* Don't use registers that have been clobbered before the start of the
5525 loop. */
5530 }
5531 \f
5532 /* Scan X for memory refs and check each memory address
5533 as a possible giv. INSN is the insn whose pattern X comes from.
5534 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5535 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5536 more than once in each loop iteration. */
5538 static void
5541 {
5551 {
5567 {
5568 rtx src_reg;
5569 rtx add_val;
5570 rtx mult_val;
5571 rtx ext_val;
5574 /* This code used to disable creating GIVs with mult_val == 1 and
5575 add_val == 0. However, this leads to lost optimizations when
5576 it comes time to combine a set of related DEST_ADDR GIVs, since
5577 this one would not be seen. */
5582 {
5583 /* Found one; record it. */
5591 }
5592 }
5597 }
5599 /* Recursively scan the subexpressions for other mem refs. */
5605 maybe_multiple);
5609 maybe_multiple);
5610 }
5611 \f
5612 /* Fill in the data about one biv update.
5613 V is the `struct induction' in which we record the biv. (It is
5614 allocated by the caller, with alloca.)
5615 INSN is the insn that sets it.
5616 DEST_REG is the biv's reg.
5618 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5619 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5620 being set to INC_VAL.
5622 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5623 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5624 can be executed more than once per iteration. If MAYBE_MULTIPLE
5625 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5626 executed exactly once per iteration. */
5628 static void
5632 {
5649 /* Add this to the reg's iv_class, creating a class
5650 if this is the first incrementation of the reg. */
5654 {
5655 /* Create and initialize new iv_class. */
5665 /* Set initial value to the reg itself. */
5668 /* We haven't seen the initializing insn yet. */
5678 /* Add this class to ivs->list. */
5682 /* Put it in the array of biv register classes. */
5684 }
5685 else
5686 {
5687 /* Check if location is the same as a previous one. */
5691 {
5694 }
5695 }
5697 /* Update IV_CLASS entry for this biv. */
5706 }
5707 \f
5708 /* Fill in the data about one giv.
5709 V is the `struct induction' in which we record the giv. (It is
5710 allocated by the caller, with alloca.)
5711 INSN is the insn that sets it.
5712 BENEFIT estimates the savings from deleting this insn.
5713 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5714 into a register or is used as a memory address.
5716 SRC_REG is the biv reg which the giv is computed from.
5717 DEST_REG is the giv's reg (if the giv is stored in a reg).
5718 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5719 LOCATION points to the place where this giv's value appears in INSN. */
5721 static void
5726 {
5731 rtx temp;
5733 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5734 undo the MULT canonicalization that we performed earlier. */
5764 /* The v->always_computable field is used in update_giv_derive, to
5765 determine whether a giv can be used to derive another giv. For a
5766 DEST_REG giv, INSN computes a new value for the giv, so its value
5767 isn't computable if INSN insn't executed every iteration.
5768 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5769 it does not compute a new value. Hence the value is always computable
5770 regardless of whether INSN is executed each iteration. */
5774 else
5780 {
5783 }
5785 {
5790 /* If the lifetime is zero, it means that this register is
5791 really a dead store. So mark this as a giv that can be
5792 ignored. This will not prevent the biv from being eliminated. */
5798 }
5800 /* Add the giv to the class of givs computed from one biv. */
5804 {
5807 /* Don't count DEST_ADDR. This is supposed to count the number of
5808 insns that calculate givs. */
5812 }
5813 else
5814 /* Fatal error, biv missing for this giv? */
5818 {
5821 }
5822 else
5823 {
5824 /* The giv can be replaced outright by the reduced register only if all
5825 of the following conditions are true:
5826 - the insn that sets the giv is always executed on any iteration
5827 on which the giv is used at all
5828 (there are two ways to deduce this:
5829 either the insn is executed on every iteration,
5830 or all uses follow that insn in the same basic block),
5831 - the giv is not used outside the loop
5832 - no assignments to the biv occur during the giv's lifetime. */
5835 /* Previous line always fails if INSN was moved by loop opt. */
5838 && (! not_every_iteration
5840 {
5841 /* Now check that there are no assignments to the biv within the
5842 giv's lifetime. This requires two separate checks. */
5844 /* Check each biv update, and fail if any are between the first
5845 and last use of the giv.
5847 If this loop contains an inner loop that was unrolled, then
5848 the insn modifying the biv may have been emitted by the loop
5849 unrolling code, and hence does not have a valid luid. Just
5850 mark the biv as not replaceable in this case. It is not very
5851 useful as a biv, because it is used in two different loops.
5852 It is very unlikely that we would be able to optimize the giv
5853 using this biv anyways. */
5858 {
5864 {
5868 }
5869 }
5871 /* If there are any backwards branches that go from after the
5872 biv update to before it, then this giv is not replaceable. */
5876 {
5880 }
5881 }
5882 else
5883 {
5884 /* May still be replaceable, we don't have enough info here to
5885 decide. */
5888 }
5889 }
5891 /* Record whether the add_val contains a const_int, for later use by
5892 combine_givs. */
5893 {
5898 ;
5902 {
5904 {
5909 else
5911 }
5914 }
5915 }
5919 }
5921 /* All this does is determine whether a giv can be made replaceable because
5922 its final value can be calculated. This code can not be part of record_giv
5923 above, because final_giv_value requires that the number of loop iterations
5924 be known, and that can not be accurately calculated until after all givs
5925 have been identified. */
5927 static void
5929 {
5932 /* DEST_ADDR givs will never reach here, because they are always marked
5933 replaceable above in record_giv. */
5935 /* The giv can be replaced outright by the reduced register only if all
5936 of the following conditions are true:
5937 - the insn that sets the giv is always executed on any iteration
5938 on which the giv is used at all
5939 (there are two ways to deduce this:
5940 either the insn is executed on every iteration,
5941 or all uses follow that insn in the same basic block),
5942 - its final value can be calculated (this condition is different
5943 than the one above in record_giv)
5944 - it's not used before the it's set
5945 - no assignments to the biv occur during the giv's lifetime. */
5947 #if 0
5948 /* This is only called now when replaceable is known to be false. */
5949 /* Clear replaceable, so that it won't confuse final_giv_value. */
5951 #endif
5956 {
5959 rtx last_giv_use;
5964 /* When trying to determine whether or not a biv increment occurs
5965 during the lifetime of the giv, we can ignore uses of the variable
5966 outside the loop because final_value is true. Hence we can not
5967 use regno_last_uid and regno_first_uid as above in record_giv. */
5969 /* Search the loop to determine whether any assignments to the
5970 biv occur during the giv's lifetime. Start with the insn
5971 that sets the giv, and search around the loop until we come
5972 back to that insn again.
5974 Also fail if there is a jump within the giv's lifetime that jumps
5975 to somewhere outside the lifetime but still within the loop. This
5976 catches spaghetti code where the execution order is not linear, and
5977 hence the above test fails. Here we assume that the giv lifetime
5978 does not extend from one iteration of the loop to the next, so as
5979 to make the test easier. Since the lifetime isn't known yet,
5980 this requires two loops. See also record_giv above. */
5985 {
5988 {
5991 }
5997 {
5998 /* It is possible for the BIV increment to use the GIV if we
5999 have a cycle. Thus we must be sure to check each insn for
6000 both BIV and GIV uses, and we must check for BIV uses
6001 first. */
6008 {
6010 {
6014 }
6016 }
6017 }
6018 }
6020 /* Now that the lifetime of the giv is known, check for branches
6021 from within the lifetime to outside the lifetime if it is still
6022 replaceable. */
6025 {
6028 {
6041 {
6050 }
6051 }
6052 }
6054 /* If it is replaceable, then save the final value. */
6057 }
6062 }
6063 \f
6064 /* Update the status of whether a giv can derive other givs.
6066 We need to do something special if there is or may be an update to the biv
6067 between the time the giv is defined and the time it is used to derive
6068 another giv.
6070 In addition, a giv that is only conditionally set is not allowed to
6071 derive another giv once a label has been passed.
6073 The cases we look at are when a label or an update to a biv is passed. */
6075 static void
6077 {
6081 rtx tem;
6084 /* Search all IV classes, then all bivs, and finally all givs.
6086 There are three cases we are concerned with. First we have the situation
6087 of a giv that is only updated conditionally. In that case, it may not
6088 derive any givs after a label is passed.
6090 The second case is when a biv update occurs, or may occur, after the
6091 definition of a giv. For certain biv updates (see below) that are
6092 known to occur between the giv definition and use, we can adjust the
6093 giv definition. For others, or when the biv update is conditional,
6094 we must prevent the giv from deriving any other givs. There are two
6095 sub-cases within this case.
6097 If this is a label, we are concerned with any biv update that is done
6098 conditionally, since it may be done after the giv is defined followed by
6099 a branch here (actually, we need to pass both a jump and a label, but
6100 this extra tracking doesn't seem worth it).
6102 If this is a jump, we are concerned about any biv update that may be
6103 executed multiple times. We are actually only concerned about
6104 backward jumps, but it is probably not worth performing the test
6105 on the jump again here.
6107 If this is a biv update, we must adjust the giv status to show that a
6108 subsequent biv update was performed. If this adjustment cannot be done,
6109 the giv cannot derive further givs. */
6115 {
6116 /* Skip if location is the same as a previous one. */
6121 {
6122 /* If cant_derive is already true, there is no point in
6123 checking all of these conditions again. */
6127 /* If this giv is conditionally set and we have passed a label,
6128 it cannot derive anything. */
6132 /* Skip givs that have mult_val == 0, since
6133 they are really invariants. Also skip those that are
6134 replaceable, since we know their lifetime doesn't contain
6135 any biv update. */
6139 /* The only way we can allow this giv to derive another
6140 is if this is a biv increment and we can form the product
6141 of biv->add_val and giv->mult_val. In this case, we will
6142 be able to compute a compensation. */
6144 {
6145 rtx ext_val_dummy;
6156 tem = simplify_giv_expr
6163 else
6165 }
6169 }
6170 }
6171 }
6172 \f
6173 /* Check whether an insn is an increment legitimate for a basic induction var.
6174 X is the source of insn P, or a part of it.
6175 MODE is the mode in which X should be interpreted.
6177 DEST_REG is the putative biv, also the destination of the insn.
6178 We accept patterns of these forms:
6179 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6180 REG = INVARIANT + REG
6182 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6183 store the additive term into *INC_VAL, and store the place where
6184 we found the additive term into *LOCATION.
6186 If X is an assignment of an invariant into DEST_REG, we set
6187 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6189 We also want to detect a BIV when it corresponds to a variable
6190 whose mode was promoted. In that case, an increment
6191 of the variable may be a PLUS that adds a SUBREG of that variable to
6192 an invariant and then sign- or zero-extends the result of the PLUS
6193 into the variable.
6195 Most GIVs in such cases will be in the promoted mode, since that is the
6196 probably the natural computation mode (and almost certainly the mode
6197 used for addresses) on the machine. So we view the pseudo-reg containing
6198 the variable as the BIV, as if it were simply incremented.
6200 Note that treating the entire pseudo as a BIV will result in making
6201 simple increments to any GIVs based on it. However, if the variable
6202 overflows in its declared mode but not its promoted mode, the result will
6203 be incorrect. This is acceptable if the variable is signed, since
6204 overflows in such cases are undefined, but not if it is unsigned, since
6205 those overflows are defined. So we only check for SIGN_EXTEND and
6206 not ZERO_EXTEND.
6208 If we cannot find a biv, we return 0. */
6210 static int
6214 {
6222 {
6228 {
6230 }
6235 {
6237 }
6238 else
6245 /* convert_modes can emit new instructions, e.g. when arg is a loop
6246 invariant MEM and dest_reg has a different mode.
6247 These instructions would be emitted after the end of the function
6248 and then *inc_val would be an uninitialized pseudo.
6249 Detect this and bail in this case.
6250 Other alternatives to solve this can be introducing a convert_modes
6251 variant which is allowed to fail but not allowed to emit new
6252 instructions, emit these instructions before loop start and let
6253 it be garbage collected if *inc_val is never used or saving the
6254 *inc_val initialization sequence generated here and when *inc_val
6255 is going to be actually used, emit it at some suitable place. */
6259 {
6262 }
6270 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6271 handle addition of promoted variables.
6272 ??? The comment at the start of this function is wrong: promoted
6273 variable increments don't look like it says they do. */
6279 /* If this register is assigned in a previous insn, look at its
6280 source, but don't go outside the loop or past a label. */
6282 /* If this sets a register to itself, we would repeat any previous
6283 biv increment if we applied this strategy blindly. */
6289 {
6290 rtx dest;
6291 do
6292 {
6294 }
6323 }
6324 /* Fall through. */
6326 /* Can accept constant setting of biv only when inside inner most loop.
6327 Otherwise, a biv of an inner loop may be incorrectly recognized
6328 as a biv of the outer loop,
6329 causing code to be moved INTO the inner loop. */
6336 /* convert_modes aborts if we try to convert to or from CCmode, so just
6337 exclude that case. It is very unlikely that a condition code value
6338 would be a useful iterator anyways. convert_modes aborts if we try to
6339 convert a float mode to non-float or vice versa too. */
6343 {
6344 /* Possible bug here? Perhaps we don't know the mode of X. */
6348 {
6351 }
6356 }
6357 else
6361 /* Ignore this BIV if signed arithmetic overflow is defined. */
6368 /* Similar, since this can be a sign extension. */
6373 ;
6387 location);
6392 }
6393 }
6394 \f
6395 /* A general induction variable (giv) is any quantity that is a linear
6396 function of a basic induction variable,
6397 i.e. giv = biv * mult_val + add_val.
6398 The coefficients can be any loop invariant quantity.
6399 A giv need not be computed directly from the biv;
6400 it can be computed by way of other givs. */
6402 /* Determine whether X computes a giv.
6403 If it does, return a nonzero value
6404 which is the benefit from eliminating the computation of X;
6405 set *SRC_REG to the register of the biv that it is computed from;
6406 set *ADD_VAL and *MULT_VAL to the coefficients,
6407 such that the value of X is biv * mult + add; */
6409 static int
6414 {
6418 /* If this is an invariant, forget it, it isn't a giv. */
6429 {
6432 /* Since this is now an invariant and wasn't before, it must be a giv
6433 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6434 with. */
6441 /* This is equivalent to a BIV. */
6448 /* Either (plus (biv) (invar)) or
6449 (plus (mult (biv) (invar_1)) (invar_2)). */
6451 {
6454 }
6455 else
6456 {
6459 }
6464 /* ADD_VAL is zero. */
6472 }
6474 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6475 unless they are CONST_INT). */
6483 else
6486 /* Always return true if this is a giv so it will be detected as such,
6487 even if the benefit is zero or negative. This allows elimination
6488 of bivs that might otherwise not be eliminated. */
6490 }
6491 \f
6492 /* Given an expression, X, try to form it as a linear function of a biv.
6493 We will canonicalize it to be of the form
6494 (plus (mult (BIV) (invar_1))
6495 (invar_2))
6496 with possible degeneracies.
6498 The invariant expressions must each be of a form that can be used as a
6499 machine operand. We surround then with a USE rtx (a hack, but localized
6500 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6501 routine; it is the caller's responsibility to strip them.
6503 If no such canonicalization is possible (i.e., two biv's are used or an
6504 expression that is neither invariant nor a biv or giv), this routine
6505 returns 0.
6507 For a nonzero return, the result will have a code of CONST_INT, USE,
6508 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6510 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6515 static rtx
6517 {
6522 rtx tem;
6524 /* If this is not an integer mode, or if we cannot do arithmetic in this
6525 mode, this can't be a giv. */
6532 {
6539 /* Put constant last, CONST_INT last if both constant. */
6547 /* Handle addition of zero, then addition of an invariant. */
6552 {
6555 /* Adding two invariants must result in an invariant, so enclose
6556 addition operation inside a USE and return it. */
6566 else
6575 /* biv + invar or mult + invar. Return sum. */
6579 /* (a + invar_1) + invar_2. Associate. */
6580 return
6586 arg1)),
6591 }
6593 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6594 MULT to reduce cases. */
6600 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6601 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6602 Recurse to associate the second PLUS. */
6607 return
6615 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6631 /* Handle "a - b" as "a + b * (-1)". */
6637 constm1_rtx)),
6646 /* Put constant last, CONST_INT last if both constant. */
6651 /* If second argument is not now constant, not giv. */
6655 /* Handle multiply by 0 or 1. */
6663 {
6665 /* biv * invar. Done. */
6669 /* Product of two constants. */
6673 /* invar * invar is a giv, but attempt to simplify it somehow. */
6679 {
6680 /* (invar_0 * invar_1) * invar_2. Associate. */
6687 arg1)),
6689 }
6690 /* Propagate the MULT expressions to the innermost nodes. */
6692 {
6693 /* (invar_0 + invar_1) * invar_2. Distribute. */
6699 arg1),
6703 arg1)),
6705 }
6709 /* (a * invar_1) * invar_2. Associate. */
6715 arg1)),
6719 /* (a + invar_1) * invar_2. Distribute. */
6724 arg1),
6727 arg1)),
6732 }
6735 /* Shift by constant is multiply by power of two. */
6739 return
6748 /* "-a" is "a * (-1)" */
6754 /* "~a" is "-a - 1". Silly, but easy. */
6758 const1_rtx),
6762 /* Already in proper form for invariant. */
6768 /* Conditionally recognize extensions of simple IVs. After we've
6769 computed loop traversal counts and verified the range of the
6770 source IV, we'll reevaluate this as a GIV. */
6772 {
6775 {
6778 }
6779 }
6783 /* If this is a new register, we can't deal with it. */
6787 /* Check for biv or giv. */
6789 {
6793 {
6796 /* Form expression from giv and add benefit. Ensure this giv
6797 can derive another and subtract any needed adjustment if so. */
6799 /* Increasing the benefit here is risky. The only case in which it
6800 is arguably correct is if this is the only use of V. In other
6801 cases, this will artificially inflate the benefit of the current
6802 giv, and lead to suboptimal code. Thus, it is disabled, since
6803 potentially not reducing an only marginally beneficial giv is
6804 less harmful than reducing many givs that are not really
6805 beneficial. */
6806 {
6810 }
6823 {
6826 }
6827 else
6828 {
6831 }
6833 }
6836 do_default:
6837 /* If it isn't an induction variable, and it is invariant, we
6838 may be able to simplify things further by looking through
6839 the bits we just moved outside the loop. */
6841 {
6847 {
6848 /* Ok, we found a match. Substitute and simplify. */
6850 /* If we match another movable, we must use that, as
6851 this one is going away. */
6856 /* If consec is nonzero, this is a member of a group of
6857 instructions that were moved together. We handle this
6858 case only to the point of seeking to the last insn and
6859 looking for a REG_EQUAL. Fail if we don't find one. */
6861 {
6864 do
6865 {
6867 }
6873 }
6874 else
6875 {
6879 }
6882 {
6883 /* What we are most interested in is pointer
6884 arithmetic on invariants -- only take
6885 patterns we may be able to do something with. */
6891 {
6893 benefit);
6896 }
6901 {
6906 }
6907 }
6909 }
6910 }
6912 }
6914 /* Fall through to general case. */
6916 /* If invariant, return as USE (unless CONST_INT).
6917 Otherwise, not giv. */
6922 {
6931 }
6932 else
6934 }
6935 }
6937 /* This routine folds invariants such that there is only ever one
6938 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6940 static rtx
6942 {
6948 {
6951 }
6954 {
6957 }
6958 else
6959 {
6962 }
6963 }
6965 static rtx
6967 {
6969 {
6973 else
6976 }
6979 else
6982 }
6983 \f
6984 /* Help detect a giv that is calculated by several consecutive insns;
6985 for example,
6986 giv = biv * M
6987 giv = giv + A
6988 The caller has already identified the first insn P as having a giv as dest;
6989 we check that all other insns that set the same register follow
6990 immediately after P, that they alter nothing else,
6991 and that the result of the last is still a giv.
6993 The value is 0 if the reg set in P is not really a giv.
6994 Otherwise, the value is the amount gained by eliminating
6995 all the consecutive insns that compute the value.
6997 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6998 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7000 The coefficients of the ultimate giv value are stored in
7001 *MULT_VAL and *ADD_VAL. */
7003 static int
7007 {
7013 rtx temp;
7014 rtx set;
7016 /* Indicate that this is a giv so that we can update the value produced in
7017 each insn of the multi-insn sequence.
7019 This induction structure will be used only by the call to
7020 general_induction_var below, so we can allocate it on our stack.
7021 If this is a giv, our caller will replace the induct var entry with
7022 a new induction structure. */
7043 {
7047 /* If libcall, skip to end of call sequence. */
7058 /* Giv created by equivalent expression. */
7064 {
7068 count--;
7072 }
7074 {
7075 /* Allow insns that set something other than this giv to a
7076 constant. Such insns are needed on machines which cannot
7077 include long constants and should not disqualify a giv. */
7086 }
7087 }
7092 }
7093 \f
7094 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7095 represented by G1. If no such expression can be found, or it is clear that
7096 it cannot possibly be a valid address, 0 is returned.
7098 To perform the computation, we note that
7099 G1 = x * v + a and
7100 G2 = y * v + b
7101 where `v' is the biv.
7103 So G2 = (y/b) * G1 + (b - a*y/x).
7105 Note that MULT = y/x.
7107 Update: A and B are now allowed to be additive expressions such that
7108 B contains all variables in A. That is, computing B-A will not require
7109 subtracting variables. */
7111 static rtx
7113 {
7114 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7119 /* If MULT is not 1, we cannot handle A with non-constants, since we
7120 would then be required to subtract multiples of the registers in A.
7121 This is theoretically possible, and may even apply to some Fortran
7122 constructs, but it is a lot of work and we do not attempt it here. */
7127 /* In general these structures are sorted top to bottom (down the PLUS
7128 chain), but not left to right across the PLUS. If B is a higher
7129 order giv than A, we can strip one level and recurse. If A is higher
7130 order, we'll eventually bail out, but won't know that until the end.
7131 If they are the same, we'll strip one level around this loop. */
7134 {
7146 /* We matched: remove one reg completely. */
7149 /* An alternate match. */
7152 /* An alternate match. */
7154 else
7155 {
7156 /* Indicates an extra register in B. Strip one level from B and
7157 recurse, hoping B was the higher order expression. */
7162 }
7163 }
7165 /* Here we are at the last level of A, go through the cases hoping to
7166 get rid of everything but a constant. */
7169 {
7182 }
7184 {
7186 }
7188 {
7193 }
7195 {
7200 else
7202 }
7207 }
7209 rtx
7211 {
7214 /* The value that G1 will be multiplied by must be a constant integer. Also,
7215 the only chance we have of getting a valid address is if b*c/a (see above
7216 for notation) is also an integer. */
7219 {
7227 }
7230 else
7231 {
7232 /* ??? Find out if the one is a multiple of the other? */
7234 }
7238 {
7239 /* Failed. If we've got a multiplication factor between G1 and G2,
7240 scale G1's addend and try again. */
7242 {
7246 {
7247 HOST_WIDE_INT m;
7251 }
7252 else
7253 {
7255 mult);
7256 }
7259 }
7260 }
7264 /* Form simplified final result. */
7269 else
7274 else
7275 {
7278 {
7282 }
7285 }
7286 }
7287 \f
7288 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7289 represented by G1. This indicates that G2 should be combined with G1 and
7290 that G2 can use (either directly or via an address expression) a register
7291 used to represent G1. */
7293 static rtx
7295 {
7298 /* With the introduction of ext dependent givs, we must care for modes.
7299 G2 must not use a wider mode than G1. */
7309 /* If these givs are identical, they can be combined. We use the results
7310 of express_from because the addends are not in a canonical form, so
7311 rtx_equal_p is a weaker test. */
7312 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7313 combination to be the other way round. */
7316 {
7318 }
7320 /* If G2 can be expressed as a function of G1 and that function is valid
7321 as an address and no more expensive than using a register for G2,
7322 the expression of G2 in terms of G1 can be used. */
7329 }
7330 \f
7331 /* Check each extension dependent giv in this class to see if its
7332 root biv is safe from wrapping in the interior mode, which would
7333 make the giv illegal. */
7335 static void
7337 {
7341 HOST_WIDE_INT start_val;
7347 /* Make sure the iteration data is available. We must have
7348 constants in order to be certain of no overflow. */
7354 /* Make sure the host can represent the arithmetic. */
7356 {
7358 HOST_WIDE_INT s_end_val;
7370 /* Check for host arithmetic overflow. */
7372 {
7374 HOST_WIDE_INT s_max;
7381 /* Check zero extension of biv ok. */
7383 /* Check for host arithmetic overflow. */
7384 && (neg_incr
7387 /* Check for target arithmetic overflow. */
7388 && (neg_incr
7391 {
7393 }
7395 /* Check sign extension of biv ok. */
7396 /* ??? While it is true that overflow with signed and pointer
7397 arithmetic is undefined, I fear too many programmers don't
7398 keep this fact in mind -- myself included on occasion.
7399 So leave alone with the signed overflow optimizations. */
7401 /* Check for host arithmetic overflow. */
7402 && (neg_incr
7405 /* Check for target arithmetic overflow. */
7406 && (neg_incr
7409 {
7411 }
7412 }
7413 }
7415 /* If we know the BIV is compared at run-time against an
7416 invariant value, and the increment is +/- 1, we may also
7417 be able to prove that the BIV cannot overflow. */
7423 {
7424 /* If the increment is +1, and the exit test is a <,
7425 the BIV cannot overflow. (For <=, we have the
7426 problematic case that the comparison value might
7427 be the maximum value of the range.) */
7429 {
7434 }
7436 /* Likewise for increment -1 and exit test >. */
7438 {
7443 }
7444 }
7446 /* Invalidate givs that fail the tests. */
7449 {
7454 {
7463 /* We don't know whether this value is being used as either
7464 signed or unsigned, so to safely truncate we must satisfy
7465 both. The initial check here verifies the BIV itself;
7466 once that is successful we may check its range wrt the
7467 derived GIV. This works only if we were able to determine
7468 constant start and end values above. */
7470 {
7474 /* We know from the above that both endpoints are nonnegative,
7475 and that there is no wrapping. Verify that both endpoints
7476 are within the (signed) range of the outer mode. */
7479 }
7484 }
7487 {
7489 {
7493 }
7494 }
7495 else
7496 {
7498 {
7503 else
7504 {
7509 else
7511 }
7516 }
7519 }
7520 }
7521 }
7523 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7525 rtx
7527 {
7533 /* Recall that check_ext_dependent_givs verified that the known bounds
7534 of a biv did not overflow or wrap with respect to the extension for
7535 the giv. Therefore, constants need no additional adjustment. */
7539 /* Otherwise, we must adjust the value to compensate for the
7540 differing modes of the biv and the giv. */
7542 }
7543 \f
7544 struct combine_givs_stats
7545 {
7548 };
7550 static int
7552 {
7559 /* Stabilize the sort. */
7563 }
7565 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7566 any other. If so, point SAME to the giv combined with and set NEW_REG to
7567 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7568 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7570 static void
7572 {
7573 /* Additional benefit to add for being combined multiple times. */
7581 /* Count givs, because bl->giv_count is incorrect here. */
7585 giv_count++;
7597 {
7599 rtx single_use;
7604 /* If a DEST_REG GIV is used only once, do not allow it to combine
7605 with anything, for in doing so we will gain nothing that cannot
7606 be had by simply letting the GIV with which we would have combined
7607 to be reduced on its own. The losage shows up in particular with
7608 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7609 be seen elsewhere as well. */
7616 /* Add an additional weight for zero addends. */
7621 {
7622 rtx this_combine;
7627 {
7630 }
7631 }
7633 }
7635 /* Iterate, combining until we can't. */
7636 restart:
7640 {
7643 {
7649 }
7651 }
7654 {
7660 /* If it has already been combined, skip. */
7665 {
7668 /* If it has already been combined, skip. */
7670 {
7675 /* For destination, we now may replace by mem expression instead
7676 of register. This changes the costs considerably, so add the
7677 compensation. */
7687 /* ??? The new final_[bg]iv_value code does a much better job
7688 of finding replaceable giv's, and hence this code may no
7689 longer be necessary. */
7693 /* To help optimize the next set of combinations, remove
7694 this giv from the benefits of other potential mates. */
7696 {
7700 }
7707 }
7708 }
7710 /* To help optimize the next set of combinations, remove
7711 this giv from the benefits of other potential mates. */
7713 {
7715 {
7719 }
7723 /* We've finished with this giv, and everything it touched.
7724 Restart the combination so that proper weights for the
7725 rest of the givs are properly taken into account. */
7726 /* ??? Ideally we would compact the arrays at this point, so
7727 as to not cover old ground. But sanely compacting
7728 can_combine is tricky. */
7730 }
7731 }
7733 /* Clean up. */
7736 }
7737 \f
7738 /* Generate sequence for REG = B * M + A. B is the initial value of
7739 the basic induction variable, M a multiplicative constant, A an
7740 additive constant and REG the destination register. */
7742 static rtx
7744 {
7745 rtx seq;
7746 rtx result;
7749 /* Use unsigned arithmetic. */
7757 }
7760 /* Update registers created in insn sequence SEQ. */
7762 static void
7764 {
7765 rtx insn;
7767 /* Update register info for alias analysis. */
7771 {
7778 }
7779 }
7782 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7783 is the initial value of the basic induction variable, M a
7784 multiplicative constant, A an additive constant and REG the
7785 destination register. */
7787 void
7790 {
7791 rtx seq;
7794 {
7797 }
7799 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7802 /* Increase the lifetime of any invariants moved further in code. */
7807 /* It is possible that the expansion created lots of new registers.
7808 Iterate over the sequence we just created and record them all. We
7809 must do this before inserting the sequence. */
7813 }
7816 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7817 initial value of the basic induction variable, M a multiplicative
7818 constant, A an additive constant and REG the destination
7819 register. */
7821 void
7823 {
7824 rtx seq;
7826 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7829 /* Increase the lifetime of any invariants moved further in code.
7830 ???? Is this really necessary? */
7835 /* It is possible that the expansion created lots of new registers.
7836 Iterate over the sequence we just created and record them all. We
7837 must do this before inserting the sequence. */
7841 }
7844 /* Emit insns after loop to set REG = B * M + A. B is the initial
7845 value of the basic induction variable, M a multiplicative constant,
7846 A an additive constant and REG the destination register. */
7848 void
7850 {
7851 rtx seq;
7853 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7856 /* It is possible that the expansion created lots of new registers.
7857 Iterate over the sequence we just created and record them all. We
7858 must do this before inserting the sequence. */
7862 }
7866 /* Similar to gen_add_mult, but compute cost rather than generating
7867 sequence. */
7869 static int
7871 {
7881 {
7886 }
7889 }
7890 \f
7891 /* Test whether A * B can be computed without
7892 an actual multiply insn. Value is 1 if so.
7894 ??? This function stinks because it generates a ton of wasted RTL
7895 ??? and as a result fragments GC memory to no end. There are other
7896 ??? places in the compiler which are invoked a lot and do the same
7897 ??? thing, generate wasted RTL just to see if something is possible. */
7899 static int
7901 {
7902 rtx tmp;
7905 /* If only one is constant, make it B. */
7909 /* If first constant, both constant, so don't need multiply. */
7913 /* If second not constant, neither is constant, so would need multiply. */
7917 /* One operand is constant, so might not need multiply insn. Generate the
7918 code for the multiply and see if a call or multiply, or long sequence
7919 of insns is generated. */
7928 {
7931 {
7941 {
7944 }
7947 }
7948 }
7958 }
7959 \f
7960 /* Check to see if loop can be terminated by a "decrement and branch until
7961 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7962 Also try reversing an increment loop to a decrement loop
7963 to see if the optimization can be performed.
7964 Value is nonzero if optimization was performed. */
7966 /* This is useful even if the architecture doesn't have such an insn,
7967 because it might change a loops which increments from 0 to n to a loop
7968 which decrements from n to 0. A loop that decrements to zero is usually
7969 faster than one that increments from zero. */
7971 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7972 such as approx_final_value, biv_total_increment, loop_iterations, and
7973 final_[bg]iv_value. */
7975 static int
7977 {
7982 rtx reg;
7984 rtx jump_label;
7985 rtx final_value;
7986 rtx start_value;
7987 rtx new_add_val;
7988 rtx comparison;
7989 rtx before_comparison;
7990 rtx p;
7991 rtx jump;
7992 rtx first_compare;
7997 /* If last insn is a conditional branch, and the insn before tests a
7998 register value, try to optimize it. Otherwise, we can't do anything. */
8007 /* Try to compute whether the compare/branch at the loop end is one or
8008 two instructions. */
8014 else
8017 {
8018 /* If more than one condition is present to control the loop, then
8019 do not proceed, as this function does not know how to rewrite
8020 loop tests with more than one condition.
8022 Look backwards from the first insn in the last comparison
8023 sequence and see if we've got another comparison sequence. */
8025 rtx jump1;
8029 }
8031 /* Check all of the bivs to see if the compare uses one of them.
8032 Skip biv's set more than once because we can't guarantee that
8033 it will be zero on the last iteration. Also skip if the biv is
8034 used between its update and the test insn. */
8037 {
8042 first_compare))
8044 }
8046 /* Try swapping the comparison to identify a suitable biv. */
8053 first_compare))
8054 {
8056 VOIDmode,
8060 }
8065 /* Look for the case where the basic induction variable is always
8066 nonnegative, and equals zero on the last iteration.
8067 In this case, add a reg_note REG_NONNEG, which allows the
8068 m68k DBRA instruction to be used. */
8074 {
8075 /* Initial value must be greater than 0,
8076 init_val % -dec_value == 0 to ensure that it equals zero on
8077 the last iteration */
8083 {
8084 /* Register always nonnegative, add REG_NOTE to branch. */
8092 }
8094 /* If the decrement is 1 and the value was tested as >= 0 before
8095 the loop, then we can safely optimize. */
8097 {
8111 {
8119 }
8120 }
8121 }
8124 {
8125 /* Try to change inc to dec, so can apply above optimization. */
8126 /* Can do this if:
8127 all registers modified are induction variables or invariant,
8128 all memory references have non-overlapping addresses
8129 (obviously true if only one write)
8130 allow 2 insns for the compare/jump at the end of the loop. */
8131 /* Also, we must avoid any instructions which use both the reversed
8132 biv and another biv. Such instructions will fail if the loop is
8133 reversed. We meet this condition by requiring that either
8134 no_use_except_counting is true, or else that there is only
8135 one biv. */
8137 /* 1 if the iteration var is used only to count iterations. */
8139 /* 1 if the loop has no memory store, or it has a single memory store
8140 which is reversible. */
8146 {
8150 /* If there are no givs for this biv, and the only exit is the
8151 fall through at the end of the loop, then
8152 see if perhaps there are no uses except to count. */
8156 {
8161 /* An insn that sets the biv is okay. */
8162 ;
8164 /* An insn that doesn't mention the biv is okay. */
8165 ;
8168 {
8169 /* If either of these insns uses the biv and sets a pseudo
8170 that has more than one usage, then the biv has uses
8171 other than counting since it's used to derive a value
8172 that is used more than one time. */
8174 regs);
8176 {
8179 }
8180 }
8181 else
8182 {
8185 }
8186 }
8188 /* A biv has uses besides counting if it is used to set
8189 another biv. */
8193 {
8196 }
8197 }
8200 /* No need to worry about MEMs. */
8201 ;
8203 {
8208 /* If the loop has a single store, and the destination address is
8209 invariant, then we can't reverse the loop, because this address
8210 might then have the wrong value at loop exit.
8211 This would work if the source was invariant also, however, in that
8212 case, the insn should have been moved out of the loop. */
8215 {
8218 /* If we could prove that each of the memory locations
8219 written to was different, then we could reverse the
8220 store -- but we don't presently have any way of
8221 knowing that. */
8224 /* If the store depends on a register that is set after the
8225 store, it depends on the initial value, and is thus not
8226 reversible. */
8228 {
8235 }
8236 }
8237 }
8238 else
8241 /* This code only acts for innermost loops. Also it simplifies
8242 the memory address check by only reversing loops with
8243 zero or one memory access.
8244 Two memory accesses could involve parts of the same array,
8245 and that can't be reversed.
8246 If the biv is used only for counting, than we don't need to worry
8247 about all these things. */
8253 && reversible_mem_store
8258 {
8259 rtx tem;
8261 /* Loop can be reversed. */
8265 /* Now check other conditions:
8267 The increment must be a constant, as must the initial value,
8268 and the comparison code must be LT.
8270 This test can probably be improved since +/- 1 in the constant
8271 can be obtained by changing LT to LE and vice versa; this is
8272 confusing. */
8275 /* for constants, LE gets turned into LT */
8280 {
8292 comparison_const_width
8294 else
8295 comparison_const_width
8299 comparison_sign_mask
8302 /* If the comparison value is not a loop invariant, then we
8303 can not reverse this loop.
8305 ??? If the insns which initialize the comparison value as
8306 a whole compute an invariant result, then we could move
8307 them out of the loop and proceed with loop reversal. */
8315 /* Normalize the initial value if it is an integer and
8316 has no other use except as a counter. This will allow
8317 a few more loops to be reversed. */
8321 {
8323 /* The code below requires comparison_val to be a multiple
8324 of add_val in order to do the loop reversal, so
8325 round up comparison_val to a multiple of add_val.
8326 Since comparison_value is constant, we know that the
8327 current comparison code is LT. */
8329 comparison_val
8331 /* We postpone overflow checks for COMPARISON_VAL here;
8332 even if there is an overflow, we might still be able to
8333 reverse the loop, if converting the loop exit test to
8334 NE is possible. */
8336 }
8338 /* First check if we can do a vanilla loop reversal. */
8340 /* If we have a decrement_and_branch_on_count,
8341 prefer the NE test, since this will allow that
8342 instruction to be generated. Note that we must
8343 use a vanilla loop reversal if the biv is used to
8344 calculate a giv or has a non-counting use. */
8345 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8346 && defined (HAVE_decrement_and_branch_on_count)
8350 #endif
8352 /* Now do postponed overflow checks on COMPARISON_VAL. */
8355 {
8356 /* Register will always be nonnegative, with value
8357 0 on last iteration */
8361 }
8365 {
8368 }
8369 else
8375 /* If the initial value is not zero, or if the comparison
8376 value is not an exact multiple of the increment, then we
8377 can not reverse this loop. */
8380 {
8383 }
8384 else
8385 {
8388 }
8392 /* Reset these in case we normalized the initial value
8393 and comparison value above. */
8396 {
8398 final_value
8400 }
8403 /* Save some info needed to produce the new insns. */
8409 /* Set start_value; if this is not a CONST_INT, we need
8410 to generate a SUB.
8411 Initialize biv to start_value before loop start.
8412 The old initializing insn will be deleted as a
8413 dead store by flow.c. */
8416 {
8417 start_value
8420 }
8422 {
8429 start_value
8435 }
8437 {
8439 initial_value);
8443 start_value
8446 }
8447 else
8448 /* We could handle the other cases too, but it'll be
8449 better to have a testcase first. */
8452 /* We may not have a single insn which can increment a reg, so
8453 create a sequence to hold all the insns from expand_inc. */
8462 /* Update biv info to reflect its new status. */
8467 /* Update loop info. */
8476 /* Inc LABEL_NUSES so that delete_insn will
8477 not delete the label. */
8480 /* If we have a separate comparison insn that does more
8481 than just set cc0, the result of the comparison might
8482 be used outside the loop. */
8484 #ifdef HAVE_CC0
8486 #endif
8487 );
8489 /* Emit an insn after the end of the loop to set the biv's
8490 proper exit value if it is used anywhere outside the loop. */
8500 /* Delete compare/branch at end of loop. */
8505 /* Add new compare/branch insn at end of loop. */
8517 ;
8523 {
8525 {
8526 /* Increment of LABEL_NUSES done above. */
8527 /* Register is now always nonnegative,
8528 so add REG_NONNEG note to the branch. */
8531 }
8533 }
8535 /* No insn may reference both the reversed and another biv or it
8536 will fail (see comment near the top of the loop reversal
8537 code).
8538 Earlier on, we have verified that the biv has no use except
8539 counting, or it is the only biv in this function.
8540 However, the code that computes no_use_except_counting does
8541 not verify reg notes. It's possible to have an insn that
8542 references another biv, and has a REG_EQUAL note with an
8543 expression based on the reversed biv. To avoid this case,
8544 remove all REG_EQUAL notes based on the reversed biv
8545 here. */
8548 {
8551 /* If this is a set of a GIV based on the reversed biv, any
8552 REG_EQUAL notes should still be correct. */
8559 {
8564 else
8566 }
8567 }
8569 /* Mark that this biv has been reversed. Each giv which depends
8570 on this biv, and which is also live past the end of the loop
8571 will have to be fixed up. */
8576 {
8580 else
8582 }
8585 }
8586 }
8587 }
8590 }
8591 \f
8592 /* Verify whether the biv BL appears to be eliminable,
8593 based on the insns in the loop that refer to it.
8595 If ELIMINATE_P is nonzero, actually do the elimination.
8597 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8598 determine whether invariant insns should be placed inside or at the
8599 start of the loop. */
8601 static int
8604 {
8607 rtx p;
8609 /* Scan all insns in the loop, stopping if we find one that uses the
8610 biv in a way that we cannot eliminate. */
8613 {
8617 rtx note;
8619 /* If this is a libcall that sets a giv, skip ahead to its end. */
8621 {
8625 {
8630 {
8637 }
8638 }
8639 }
8641 /* Closely examine the insn if the biv is mentioned. */
8646 {
8652 }
8654 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8659 }
8662 {
8667 }
8670 }
8671 \f
8672 /* INSN and REFERENCE are instructions in the same insn chain.
8673 Return nonzero if INSN is first. */
8675 int
8677 {
8681 {
8682 /* Start with test for not first so that INSN == REFERENCE yields not
8683 first. */
8689 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8690 previous insn, hence the <= comparison below does not work if
8691 P is a note. */
8702 }
8703 }
8705 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8706 the offset that we have to take into account due to auto-increment /
8707 div derivation is zero. */
8708 static int
8711 {
8712 /* If the giv V had the auto-inc address optimization applied
8713 to it, and INSN occurs between the giv insn and the biv
8714 insn, then we'd have to adjust the value used here.
8715 This is rare, so we don't bother to make this possible. */
8724 }
8726 /* If BL appears in X (part of the pattern of INSN), see if we can
8727 eliminate its use. If so, return 1. If not, return 0.
8729 If BIV does not appear in X, return 1.
8731 If ELIMINATE_P is nonzero, actually do the elimination.
8732 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8733 Depending on how many items have been moved out of the loop, it
8734 will either be before INSN (when WHERE_INSN is nonzero) or at the
8735 start of the loop (when WHERE_INSN is zero). */
8737 static int
8741 {
8747 #ifdef HAVE_cc0
8749 #endif
8755 {
8757 /* If we haven't already been able to do something with this BIV,
8758 we can't eliminate it. */
8764 /* If this sets the BIV, it is not a problem. */
8768 /* If this is an insn that defines a giv, it is also ok because
8769 it will go away when the giv is reduced. */
8774 #ifdef HAVE_cc0
8776 {
8777 /* Can replace with any giv that was reduced and
8778 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8779 Require a constant for MULT_VAL, so we know it's nonzero.
8780 ??? We disable this optimization to avoid potential
8781 overflows. */
8789 {
8796 /* If the giv has the opposite direction of change,
8797 then reverse the comparison. */
8801 else
8804 /* We can probably test that giv's reduced reg. */
8807 }
8809 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8810 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8811 Require a constant for MULT_VAL, so we know it's nonzero.
8812 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8813 overflow problem. */
8825 {
8832 /* If the giv has the opposite direction of change,
8833 then reverse the comparison. */
8837 else
8841 /* Replace biv with the giv's reduced register. */
8846 /* Insn doesn't support that constant or invariant. Copy it
8847 into a register (it will be a loop invariant.) */
8854 /* Substitute the new register for its invariant value in
8855 the compare expression. */
8859 }
8860 }
8861 #endif
8868 /* See if either argument is the biv. */
8873 else
8877 {
8878 /* First try to replace with any giv that has constant positive
8879 mult_val and constant add_val. We might be able to support
8880 negative mult_val, but it seems complex to do it in general. */
8892 {
8896 /* Don't eliminate if the linear combination that makes up
8897 the giv overflows when it is applied to ARG. */
8899 {
8900 rtx add_val;
8904 else
8910 }
8915 /* Replace biv with the giv's reduced reg. */
8918 /* If all constants are actually constant integers and
8919 the derived constant can be directly placed in the COMPARE,
8920 do so. */
8923 {
8926 }
8927 else
8928 {
8929 /* Otherwise, load it into a register. */
8934 }
8940 }
8942 /* Look for giv with positive constant mult_val and nonconst add_val.
8943 Insert insns to calculate new compare value.
8944 ??? Turn this off due to possible overflow. */
8952 {
8953 rtx tem;
8963 /* Replace biv with giv's reduced register. */
8967 /* Compute value to compare against. */
8971 /* Use it in this insn. */
8975 }
8976 }
8978 {
8980 {
8981 /* Look for giv with constant positive mult_val and nonconst
8982 add_val. Insert insns to compute new compare value.
8983 ??? Turn this off due to possible overflow. */
8990 {
8991 rtx tem;
9001 /* Replace biv with giv's reduced register. */
9005 /* Compute value to compare against. */
9012 }
9013 }
9015 /* This code has problems. Basically, you can't know when
9016 seeing if we will eliminate BL, whether a particular giv
9017 of ARG will be reduced. If it isn't going to be reduced,
9018 we can't eliminate BL. We can try forcing it to be reduced,
9019 but that can generate poor code.
9021 The problem is that the benefit of reducing TV, below should
9022 be increased if BL can actually be eliminated, but this means
9023 we might have to do a topological sort of the order in which
9024 we try to process biv. It doesn't seem worthwhile to do
9025 this sort of thing now. */
9027 #if 0
9028 /* Otherwise the reg compared with had better be a biv. */
9033 /* Look for a pair of givs, one for each biv,
9034 with identical coefficients. */
9036 {
9048 {
9055 /* Replace biv with its giv's reduced reg. */
9057 /* Replace other operand with the other giv's
9058 reduced reg. */
9061 }
9062 }
9063 #endif
9064 }
9066 /* If we get here, the biv can't be eliminated. */
9070 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9071 biv is used in it, since it will be replaced. */
9079 }
9081 /* See if any subexpression fails elimination. */
9084 {
9086 {
9099 }
9100 }
9103 }
9104 \f
9105 /* Return nonzero if the last use of REG
9106 is in an insn following INSN in the same basic block. */
9108 static int
9110 {
9111 rtx n;
9115 {
9118 }
9120 }
9121 \f
9122 /* Called via `note_stores' to record the initial value of a biv. Here we
9123 just record the location of the set and process it later. */
9125 static void
9127 {
9138 /* If this is the first set found, record it. */
9140 {
9143 }
9144 }
9145 \f
9146 /* If any of the registers in X are "old" and currently have a last use earlier
9147 than INSN, update them to have a last use of INSN. Their actual last use
9148 will be the previous insn but it will not have a valid uid_luid so we can't
9149 use it. X must be a source expression only. */
9151 static void
9153 {
9154 /* Check for the case where INSN does not have a valid luid. In this case,
9155 there is no need to modify the regno_last_uid, as this can only happen
9156 when code is inserted after the loop_end to set a pseudo's final value,
9157 and hence this insn will never be the last use of x.
9158 ???? This comment is not correct. See for example loop_givs_reduce.
9159 This may insert an insn before another new insn. */
9163 {
9165 }
9166 else
9167 {
9171 {
9177 }
9178 }
9179 }
9180 \f
9181 /* Given an insn INSN and condition COND, return the condition in a
9182 canonical form to simplify testing by callers. Specifically:
9184 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9185 (2) Both operands will be machine operands; (cc0) will have been replaced.
9186 (3) If an operand is a constant, it will be the second operand.
9187 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9188 for GE, GEU, and LEU.
9190 If the condition cannot be understood, or is an inequality floating-point
9191 comparison which needs to be reversed, 0 will be returned.
9193 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9195 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9196 insn used in locating the condition was found. If a replacement test
9197 of the condition is desired, it should be placed in front of that
9198 insn and we will be sure that the inputs are still valid.
9200 If WANT_REG is nonzero, we wish the condition to be relative to that
9201 register, if possible. Therefore, do not canonicalize the condition
9202 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9203 to be a compare to a CC mode register. */
9205 rtx
9208 {
9211 rtx set;
9212 rtx tem;
9230 /* If we are comparing a register with zero, see if the register is set
9231 in the previous insn to a COMPARE or a comparison operation. Perform
9232 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9233 in cse.c */
9239 {
9240 /* Set nonzero when we find something of interest. */
9243 #ifdef HAVE_cc0
9244 /* If comparison with cc0, import actual comparison from compare
9245 insn. */
9247 {
9258 }
9259 #endif
9261 /* If this is a COMPARE, pick up the two things being compared. */
9263 {
9267 }
9271 /* Go back to the previous insn. Stop if it is not an INSN. We also
9272 stop if it isn't a single set or if it has a REG_INC note because
9273 we don't want to bother dealing with it. */
9287 /* If this is setting OP0, get what it sets it to if it looks
9288 relevant. */
9290 {
9292 #ifdef FLOAT_STORE_FLAG_VALUE
9293 REAL_VALUE_TYPE fsfv;
9294 #endif
9296 /* ??? We may not combine comparisons done in a CCmode with
9297 comparisons not done in a CCmode. This is to aid targets
9298 like Alpha that have an IEEE compliant EQ instruction, and
9299 a non-IEEE compliant BEQ instruction. The use of CCmode is
9300 actually artificial, simply to prevent the combination, but
9301 should not affect other platforms.
9303 However, we must allow VOIDmode comparisons to match either
9304 CCmode or non-CCmode comparison, because some ports have
9305 modeless comparisons inside branch patterns.
9307 ??? This mode check should perhaps look more like the mode check
9308 in simplify_comparison in combine. */
9316 && (STORE_FLAG_VALUE
9319 #ifdef FLOAT_STORE_FLAG_VALUE
9324 #endif
9325 ))
9336 && (STORE_FLAG_VALUE
9339 #ifdef FLOAT_STORE_FLAG_VALUE
9344 #endif
9345 ))
9351 {
9354 }
9355 else
9357 }
9360 /* If this sets OP0, but not directly, we have to give up. */
9364 {
9368 {
9373 }
9378 }
9379 }
9381 /* If constant is first, put it last. */
9385 /* If OP0 is the result of a comparison, we weren't able to find what
9386 was really being compared, so fail. */
9391 /* Canonicalize any ordered comparison with integers involving equality
9392 if we can do computations in the relevant mode and we do not
9393 overflow. */
9399 {
9402 unsigned HOST_WIDE_INT max_val
9406 {
9412 /* When cross-compiling, const_val might be sign-extended from
9413 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9433 }
9434 }
9436 /* Never return CC0; return zero instead. */
9441 }
9443 /* Given a jump insn JUMP, return the condition that will cause it to branch
9444 to its JUMP_LABEL. If the condition cannot be understood, or is an
9445 inequality floating-point comparison which needs to be reversed, 0 will
9446 be returned.
9448 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9449 insn used in locating the condition was found. If a replacement test
9450 of the condition is desired, it should be placed in front of that
9451 insn and we will be sure that the inputs are still valid.
9453 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9454 compare CC mode register. */
9456 rtx
9458 {
9459 rtx cond;
9461 rtx set;
9463 /* If this is not a standard conditional jump, we can't parse it. */
9471 /* If this branches to JUMP_LABEL when the condition is false, reverse
9472 the condition. */
9473 reverse
9478 allow_cc_mode);
9479 }
9481 /* Similar to above routine, except that we also put an invariant last
9482 unless both operands are invariants. */
9484 rtx
9486 {
9496 }
9498 /* Scan the function and determine whether it has indirect (computed) jumps.
9500 This is taken mostly from flow.c; similar code exists elsewhere
9501 in the compiler. It may be useful to put this into rtlanal.c. */
9502 static int
9504 {
9505 rtx insn;
9512 }
9514 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9515 documentation for LOOP_MEMS for the definition of `appropriate'.
9516 This function is called from prescan_loop via for_each_rtx. */
9518 static int
9520 {
9529 {
9534 /* We're not interested in MEMs that are only clobbered. */
9538 /* We're not interested in the MEM associated with a
9539 CONST_DOUBLE, so there's no need to traverse into this. */
9543 /* We're not interested in any MEMs that only appear in notes. */
9547 /* This is not a MEM. */
9549 }
9551 /* See if we've already seen this MEM. */
9554 {
9558 /* The modes of the two memory accesses are different. If
9559 this happens, something tricky is going on, and we just
9560 don't optimize accesses to this MEM. */
9564 }
9566 /* Resize the array, if necessary. */
9568 {
9571 else
9576 }
9578 /* Actually insert the MEM. */
9580 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9581 because we can't put it in a register. We still store it in the
9582 table, though, so that if we see the same address later, but in a
9583 non-BLK mode, we'll not think we can optimize it at that point. */
9589 }
9592 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9594 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9595 register that is modified by an insn between FROM and TO. If the
9596 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9597 more, stop incrementing it, to avoid overflow.
9599 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9600 register I is used, if it is only used once. Otherwise, it is set
9601 to 0 (for no uses) or const0_rtx for more than one use. This
9602 parameter may be zero, in which case this processing is not done.
9604 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9605 optimize register I. */
9607 static void
9609 {
9612 /* last_set[n] is nonzero iff reg n has been set in the current
9613 basic block. In that case, it is the insn that last set reg n. */
9615 rtx insn;
9621 /* Grow the regs array if not allocated or too small. */
9623 {
9628 /* Zero the new elements. */
9631 }
9633 /* Clear previously scanned fields but do not clear n_times_set. */
9635 {
9639 }
9643 /* Scan the loop, recording register usage. */
9646 {
9648 {
9649 /* Record registers that have exactly one use. */
9652 /* Include uses in REG_EQUAL notes. */
9660 {
9664 last_set);
9665 }
9666 }
9671 /* Invalidate all registers used for function argument passing.
9672 We check rtx_varies_p for the same reason as below, to allow
9673 optimizing PIC calculations. */
9675 {
9676 rtx link;
9678 link;
9680 {
9687 }
9688 }
9689 }
9691 /* Invalidate all hard registers clobbered by calls. With one exception:
9692 a call-clobbered PIC register is still function-invariant for our
9693 purposes, since we can hoist any PIC calculations out of the loop.
9694 Thus the call to rtx_varies_p. */
9699 {
9702 }
9704 #ifdef AVOID_CCMODE_COPIES
9705 /* Don't try to move insns which set CC registers if we should not
9706 create CCmode register copies. */
9710 #endif
9712 /* Set regs->array[I].n_times_set for the new registers. */
9717 }
9719 /* Returns the number of real INSNs in the LOOP. */
9721 static int
9723 {
9725 rtx insn;
9733 }
9735 /* Move MEMs into registers for the duration of the loop. */
9737 static void
9739 {
9746 rtx end_label;
9747 /* Nonzero if the next instruction may never be executed. */
9754 /* We cannot use next_label here because it skips over normal insns. */
9759 /* Check to see if it's possible that some instructions in the loop are
9760 never executed. Also check if there is a goto out of the loop other
9761 than right after the end of the loop. */
9765 {
9769 /* If we enter the loop in the middle, and scan
9770 around to the beginning, don't set maybe_never
9771 for that. This must be an unconditional jump,
9772 otherwise the code at the top of the loop might
9773 never be executed. Unconditional jumps are
9774 followed a by barrier then loop end. */
9779 {
9780 /* If this is a jump outside of the loop but not right
9781 after the end of the loop, we would have to emit new fixup
9782 sequences for each such label. */
9784 JUMP_INSN is executed, we must be conservative. */
9793 /* Something complicated. */
9795 else
9796 /* If there are any more instructions in the loop, they
9797 might not be reached. */
9799 }
9802 }
9804 /* Find start of the extended basic block that enters the loop. */
9808 ;
9813 /* Build table of mems that get set to constant values before the
9814 loop. */
9818 /* Actually move the MEMs. */
9820 {
9821 regset_head load_copies;
9822 regset_head store_copies;
9824 rtx reg;
9826 rtx mem_list_entry;
9830 /* There's no telling whether or not MEM is modified. */
9833 /* Go through the MEMs written to in the loop to see if this
9834 one is aliased by one of them. */
9837 {
9842 {
9843 /* MEM is indeed aliased by this store. */
9846 }
9848 }
9854 /* If this MEM is written to, we must be sure that there
9855 are no reads from another MEM that aliases this one. */
9857 {
9861 {
9865 VOIDmode,
9867 rtx_varies_p))
9868 {
9869 /* It's not safe to hoist loop_info->mems[i] out of
9870 the loop because writes to it might not be
9871 seen by reads from loop_info->mems[j]. */
9874 }
9875 }
9876 }
9879 /* We can't access the MEM outside the loop; it might
9880 cause a trap that wouldn't have happened otherwise. */
9884 /* We thought we were going to lift this MEM out of the
9885 loop, but later discovered that we could not. */
9891 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9892 order to keep scan_loop from moving stores to this MEM
9893 out of the loop just because this REG is neither a
9894 user-variable nor used in the loop test. */
9899 /* Now, replace all references to the MEM with the
9900 corresponding pseudos. */
9905 {
9907 {
9908 rtx set;
9912 /* See if this copies the mem into a register that isn't
9913 modified afterwards. We'll try to do copy propagation
9914 a little further on. */
9916 /* @@@ This test is _way_ too conservative. */
9917 && ! maybe_never
9925 /* See if this copies the mem from a register that isn't
9926 modified afterwards. We'll try to remove the
9927 redundant copy later on by doing a little register
9928 renaming and copy propagation. This will help
9929 to untangle things for the BIV detection code. */
9931 && ! maybe_never
9939 /* If this is a call which uses / clobbers this memory
9940 location, we must not change the interface here. */
9944 {
9948 }
9949 else
9950 /* Replace the memory reference with the shadow register. */
9953 }
9958 }
9963 /* We couldn't replace all occurrences of the MEM. */
9965 else
9966 {
9967 /* Load the memory immediately before LOOP->START, which is
9968 the NOTE_LOOP_BEG. */
9970 rtx set;
9976 {
9980 {
9984 /* Extending hard register lifetimes causes crash
9985 on SRC targets. Doing so on non-SRC is
9986 probably also not good idea, since we most
9987 probably have pseudoregister equivalence as
9988 well. */
9991 }
9992 /* Use the constant equivalence if that is cheap enough. */
9998 {
10001 }
10003 /* If best_equiv is nonzero, we know that MEM is set to a
10004 constant or register before the loop. We will use this
10005 knowledge to initialize the shadow register with that
10006 constant or reg rather than by loading from MEM. */
10009 }
10014 {
10017 {
10020 }
10021 }
10027 {
10029 {
10032 }
10034 /* Store the memory immediately after END, which is
10035 the NOTE_LOOP_END. */
10038 }
10041 {
10046 }
10048 /* Attempt a bit of copy propagation. This helps untangle the
10049 data flow, and enables {basic,general}_induction_var to find
10050 more bivs/givs. */
10051 EXECUTE_IF_SET_IN_REG_SET
10053 {
10055 });
10058 EXECUTE_IF_SET_IN_REG_SET
10060 {
10062 });
10064 }
10065 }
10067 /* Now, we need to replace all references to the previous exit
10068 label with the new one. */
10075 }
10077 /* For communication between note_reg_stored and its caller. */
10078 struct note_reg_stored_arg
10079 {
10081 rtx reg;
10082 };
10084 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10085 is equal to ARG. */
10086 static void
10088 {
10092 }
10094 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10095 There must be exactly one insn that sets this pseudo; it will be
10096 deleted if all replacements succeed and we can prove that the register
10097 is not used after the loop. */
10099 static void
10101 {
10102 /* This is the reg that we are copying from. */
10105 rtx insn;
10106 /* These help keep track of whether we replaced all uses of the reg. */
10113 {
10114 rtx set;
10116 /* Only substitute within one extended basic block from the initializing
10117 insn. */
10124 /* Is this the initializing insn? */
10129 {
10136 }
10138 /* Only substitute after seeing the initializing insn. */
10140 {
10147 /* Stop replacing when REPLACEMENT is modified. */
10152 {
10155 /* It is possible that we've turned previously valid REG_EQUAL to
10156 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10157 REPLACEMENT is modified, we get different meaning. */
10161 }
10162 }
10163 }
10167 {
10171 {
10172 rtx first;
10173 rtx retval_note;
10175 /* Assume we're just deleting INIT_INSN. */
10177 /* Look for REG_RETVAL note. If we're deleting the end of
10178 the libcall sequence, the whole sequence can go. */
10180 /* If we found a REG_RETVAL note, find the first instruction
10181 in the sequence. */
10185 /* Delete the instructions. */
10187 }
10190 }
10191 }
10193 /* Replace all the instructions from FIRST up to and including LAST
10194 with NOTE_INSN_DELETED notes. */
10196 static void
10198 {
10200 {
10206 /* If this was the LAST instructions we're supposed to delete,
10207 we're done. */
10212 }
10213 }
10215 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10216 loop LOOP if the order of the sets of these registers can be
10217 swapped. There must be exactly one insn within the loop that sets
10218 this pseudo followed immediately by a move insn that sets
10219 REPLACEMENT with REGNO. */
10220 static void
10223 {
10224 rtx insn;
10233 {
10234 /* Search for the insn that copies REGNO to NEW_REGNO? */
10242 }
10245 {
10246 rtx prev_insn;
10247 rtx prev_set;
10249 /* Some DEF-USE info would come in handy here to make this
10250 function more general. For now, just check the previous insn
10251 which is the most likely candidate for setting REGNO. */
10259 {
10260 /* We have:
10261 (set (reg regno) (expr))
10262 (set (reg new_regno) (reg regno))
10264 so try converting this to:
10265 (set (reg new_regno) (expr))
10266 (set (reg regno) (reg new_regno))
10268 The former construct is often generated when a global
10269 variable used for an induction variable is shadowed by a
10270 register (NEW_REGNO). The latter construct improves the
10271 chances of GIV replacement and BIV elimination. */
10281 {
10288 /* Update first use of REGNO. */
10292 /* Now perform copy propagation to hopefully
10293 remove all uses of REGNO within the loop. */
10295 }
10296 }
10297 }
10298 }
10300 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10302 static int
10304 {
10306 {
10310 }
10312 }
10314 /* Returns the first MEM found in NOTE by depth-first search. */
10316 static rtx
10318 {
10322 }
10324 /* Replace MEM with its associated pseudo register. This function is
10325 called from load_mems via for_each_rtx. DATA is actually a pointer
10326 to a structure describing the instruction currently being scanned
10327 and the MEM we are currently replacing. */
10329 static int
10331 {
10339 {
10344 /* We're not interested in the MEM associated with a
10345 CONST_DOUBLE, so there's no need to traverse into one. */
10349 /* This is not a MEM. */
10351 }
10354 /* This is not the MEM we are currently replacing. */
10357 /* Actually replace the MEM. */
10361 }
10363 static void
10365 {
10366 loop_replace_args args;
10374 /* If we hoist a mem write out of the loop, then REG_EQUAL
10375 notes referring to the mem are no longer valid. */
10377 {
10382 {
10386 {
10387 /* Remove the note. */
10390 }
10391 }
10392 }
10393 }
10395 /* Replace one register with another. Called through for_each_rtx; PX points
10396 to the rtx being scanned. DATA is actually a pointer to
10397 a structure of arguments. */
10399 static int
10401 {
10412 }
10414 static void
10416 {
10417 loop_replace_args args;
10424 }
10425 \f
10426 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10427 (ignored in the interim). */
10429 static rtx
10432 rtx pattern)
10433 {
10435 }
10438 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10439 in basic block WHERE_BB (ignored in the interim) within the loop
10440 otherwise hoist PATTERN into the loop pre-header. */
10442 rtx
10444 basic_block where_bb ATTRIBUTE_UNUSED,
10446 {
10450 }
10453 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10454 WHERE_BB (ignored in the interim) within the loop. */
10456 static rtx
10458 basic_block where_bb ATTRIBUTE_UNUSED,
10460 {
10462 }
10465 /* Hoist insn for PATTERN into the loop pre-header. */
10467 rtx
10469 {
10471 }
10474 /* Hoist call insn for PATTERN into the loop pre-header. */
10476 static rtx
10478 {
10480 }
10483 /* Sink insn for PATTERN after the loop end. */
10485 rtx
10487 {
10489 }
10491 /* bl->final_value can be either general_operand or PLUS of general_operand
10492 and constant. Emit sequence of instructions to load it into REG. */
10493 static rtx
10495 {
10496 rtx seq;
10504 }
10506 /* If the loop has multiple exits, emit insn for PATTERN before the
10507 loop to ensure that it will always be executed no matter how the
10508 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10509 since this is slightly more efficient. */
10511 static rtx
10513 {
10516 else
10518 }
10519 \f
10520 static void
10522 {
10530 iv_num++;
10535 {
10538 }
10539 }
10542 static void
10545 {
10547 rtx incr;
10558 {
10561 }
10563 {
10566 }
10570 {
10574 }
10577 {
10581 }
10583 /* List the increments. */
10585 {
10589 }
10591 /* List the givs. */
10593 {
10598 else
10601 }
10602 }
10605 static void
10607 {
10618 {
10622 }
10625 }
10628 static void
10630 {
10637 else
10653 {
10655 {
10667 }
10668 }
10679 {
10683 }
10686 }
10689 void
10691 {
10693 }
10696 void
10698 {
10700 }
10703 void
10705 {
10707 }
10710 void
10712 {
10714 }
10717 #define LOOP_BLOCK_NUM_1(INSN) \
10718 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10720 /* The notes do not have an assigned block, so look at the next insn. */
10721 #define LOOP_BLOCK_NUM(INSN) \
10722 ((INSN) ? (GET_CODE (INSN) == NOTE \
10723 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10724 : LOOP_BLOCK_NUM_1 (INSN)) \
10725 : -1)
10727 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10729 static void
10732 {
10733 rtx label;
10738 /* Print diagnostics to compare our concept of a loop with
10739 what the loop notes say. */
10754 {
10774 {
10777 {
10780 }
10781 }
10784 /* This can happen when a marked loop appears as two nested loops,
10785 say from while (a || b) {}. The inner loop won't match
10786 the loop markers but the outer one will. */
10789 }
10790 }
10792 /* Call this function from the debugger to dump LOOP. */
10794 void
10796 {
10798 }
10800 /* Call this function from the debugger to dump LOOPS. */
10802 void
10804 {
10806 }