| blob | 77567f868d4343e772c7504fce025a414cfd90aa |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
69 /* Not really meaningful values, but at least something. */
70 #ifndef SIMULTANEOUS_PREFETCHES
71 #define SIMULTANEOUS_PREFETCHES 3
72 #endif
73 #ifndef PREFETCH_BLOCK
74 #define PREFETCH_BLOCK 32
75 #endif
76 #ifndef HAVE_prefetch
77 #define HAVE_prefetch 0
78 #define CODE_FOR_prefetch 0
79 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
80 #endif
82 /* Give up the prefetch optimizations once we exceed a given threshold.
83 It is unlikely that we would be able to optimize something in a loop
84 with so many detected prefetches. */
85 #define MAX_PREFETCHES 100
86 /* The number of prefetch blocks that are beneficial to fetch at once before
87 a loop with a known (and low) iteration count. */
88 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
89 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
90 since it is likely that the data are already in the cache. */
91 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
93 /* Parameterize some prefetch heuristics so they can be turned on and off
94 easily for performance testing on new architectures. These can be
95 defined in target-dependent files. */
97 /* Prefetch is worthwhile only when loads/stores are dense. */
98 #ifndef PREFETCH_ONLY_DENSE_MEM
99 #define PREFETCH_ONLY_DENSE_MEM 1
100 #endif
102 /* Define what we mean by "dense" loads and stores; This value divided by 256
103 is the minimum percentage of memory references that worth prefetching. */
104 #ifndef PREFETCH_DENSE_MEM
105 #define PREFETCH_DENSE_MEM 220
106 #endif
108 /* Do not prefetch for a loop whose iteration count is known to be low. */
109 #ifndef PREFETCH_NO_LOW_LOOPCNT
110 #define PREFETCH_NO_LOW_LOOPCNT 1
111 #endif
113 /* Define what we mean by a "low" iteration count. */
114 #ifndef PREFETCH_LOW_LOOPCNT
115 #define PREFETCH_LOW_LOOPCNT 32
116 #endif
118 /* Do not prefetch for a loop that contains a function call; such a loop is
119 probably not an internal loop. */
120 #ifndef PREFETCH_NO_CALL
121 #define PREFETCH_NO_CALL 1
122 #endif
124 /* Do not prefetch accesses with an extreme stride. */
125 #ifndef PREFETCH_NO_EXTREME_STRIDE
126 #define PREFETCH_NO_EXTREME_STRIDE 1
127 #endif
129 /* Define what we mean by an "extreme" stride. */
130 #ifndef PREFETCH_EXTREME_STRIDE
131 #define PREFETCH_EXTREME_STRIDE 4096
132 #endif
134 /* Define a limit to how far apart indices can be and still be merged
135 into a single prefetch. */
136 #ifndef PREFETCH_EXTREME_DIFFERENCE
137 #define PREFETCH_EXTREME_DIFFERENCE 4096
138 #endif
140 /* Issue prefetch instructions before the loop to fetch data to be used
141 in the first few loop iterations. */
142 #ifndef PREFETCH_BEFORE_LOOP
143 #define PREFETCH_BEFORE_LOOP 1
144 #endif
146 /* Do not handle reversed order prefetches (negative stride). */
147 #ifndef PREFETCH_NO_REVERSE_ORDER
148 #define PREFETCH_NO_REVERSE_ORDER 1
149 #endif
151 /* Prefetch even if the GIV is in conditional code. */
152 #ifndef PREFETCH_CONDITIONAL
153 #define PREFETCH_CONDITIONAL 1
154 #endif
156 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
157 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
159 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
160 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
161 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
163 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
164 ((REGNO) < FIRST_PSEUDO_REGISTER \
165 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
168 /* Vector mapping INSN_UIDs to luids.
169 The luids are like uids but increase monotonically always.
170 We use them to see whether a jump comes from outside a given loop. */
174 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
175 number the insn is contained in. */
179 /* 1 + largest uid of any insn. */
183 /* Number of loops detected in current function. Used as index to the
184 next few tables. */
188 /* Bound on pseudo register number before loop optimization.
189 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
192 /* The value to pass to the next call of reg_scan_update. */
194 \f
195 /* During the analysis of a loop, a chain of `struct movable's
196 is made to record all the movable insns found.
197 Then the entire chain can be scanned to decide which to move. */
199 struct movable
200 {
205 of any registers used within the LIBCALL. */
207 that must be moved with this one. */
210 may be adjusted when matching movables
211 that load the same value are found. */
213 including other movables that force this
214 or match this one. */
216 a low part that we should avoid changing when
217 clearing the rest of the reg. */
221 /* If PARTIAL is 1, GLOBAL means something different:
222 that the reg is live outside the range from where it is set
223 to the following label. */
227 In particular, moving it does not make it
228 invariant. */
230 load SRC, rather than copying INSN. */
232 first insn of a consecutive sets group. */
235 the original insn with a copy from that
236 pseudo, rather than deleting it. */
240 };
245 /* Forward declarations. */
259 #if 0
261 #endif
302 rtx *);
363 {
364 rtx match;
365 rtx replacement;
366 rtx insn;
369 /* Nonzero iff INSN is between START and END, inclusive. */
370 #define INSN_IN_RANGE_P(INSN, START, END) \
371 (INSN_UID (INSN) < max_uid_for_loop \
372 && INSN_LUID (INSN) >= INSN_LUID (START) \
373 && INSN_LUID (INSN) <= INSN_LUID (END))
375 /* Indirect_jump_in_function is computed once per function. */
383 \f
384 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
385 copy the value of the strength reduced giv to its original register. */
388 /* Cost of using a register, to normalize the benefits of a giv. */
391 void
393 {
399 }
400 \f
401 /* Compute the mapping from uids to luids.
402 LUIDs are numbers assigned to insns, like uids,
403 except that luids increase monotonically through the code.
404 Start at insn START and stop just before END. Assign LUIDs
405 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
406 static int
408 {
410 rtx insn;
413 {
416 /* Don't assign luids to line-number NOTEs, so that the distance in
417 luids between two insns is not affected by -g. */
421 else
422 /* Give a line number note the same luid as preceding insn. */
424 }
426 }
427 \f
428 /* Entry point of this file. Perform loop optimization
429 on the current function. F is the first insn of the function
430 and DUMPFILE is a stream for output of a trace of actions taken
431 (or 0 if none should be output). */
433 void
435 {
436 rtx insn;
451 /* Count the number of loops. */
455 {
458 max_loop_num++;
459 }
461 /* Don't waste time if no loops. */
467 /* Get size to use for tables indexed by uids.
468 Leave some space for labels allocated by find_and_verify_loops. */
474 /* Allocate storage for array of loops. */
477 /* Find and process each loop.
478 First, find them, and record them in order of their beginnings. */
481 /* Allocate and initialize auxiliary loop information. */
486 /* Now find all register lifetimes. This must be done after
487 find_and_verify_loops, because it might reorder the insns in the
488 function. */
491 /* This must occur after reg_scan so that registers created by gcse
492 will have entries in the register tables.
494 We could have added a call to reg_scan after gcse_main in toplev.c,
495 but moving this call to init_alias_analysis is more efficient. */
498 /* See if we went too far. Note that get_max_uid already returns
499 one more that the maximum uid of all insn. */
502 /* Now reset it to the actual size we need. See above. */
505 /* find_and_verify_loops has already called compute_luids, but it
506 might have rearranged code afterwards, so we need to recompute
507 the luids now. */
510 /* Don't leave gaps in uid_luid for insns that have been
511 deleted. It is possible that the first or last insn
512 using some register has been deleted by cross-jumping.
513 Make sure that uid_luid for that former insn's uid
514 points to the general area where that insn used to be. */
516 {
520 }
525 /* Determine if the function has indirect jump. On some systems
526 this prevents low overhead loop instructions from being used. */
529 /* Now scan the loops, last ones first, since this means inner ones are done
530 before outer ones. */
532 {
537 }
541 /* Clean up. */
546 }
547 \f
548 /* Returns the next insn, in execution order, after INSN. START and
549 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
550 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
551 insn-stream; it is used with loops that are entered near the
552 bottom. */
554 static rtx
556 {
560 {
562 /* Go to the top of the loop, and continue there. */
564 else
565 /* We're done. */
567 }
570 /* We're done. */
574 }
576 /* Optimize one loop described by LOOP. */
578 /* ??? Could also move memory writes out of loops if the destination address
579 is invariant, the source is invariant, the memory write is not volatile,
580 and if we can prove that no read inside the loop can read this address
581 before the write occurs. If there is a read of this address after the
582 write, then we can also mark the memory read as invariant. */
584 static void
586 {
592 rtx p;
593 /* 1 if we are scanning insns that could be executed zero times. */
595 /* 1 if we are scanning insns that might never be executed
596 due to a subroutine call which might exit before they are reached. */
598 /* Number of insns in the loop. */
602 /* The SET from an insn, if it is the only SET in the insn. */
604 /* Chain describing insns movable in current loop. */
606 /* Ratio of extra register life span we can justify
607 for saving an instruction. More if loop doesn't call subroutines
608 since in that case saving an insn makes more difference
609 and more registers are available. */
611 /* Nonzero if we are scanning instructions in a sub-loop. */
620 /* Determine whether this loop starts with a jump down to a test at
621 the end. This will occur for a small number of loops with a test
622 that is too complex to duplicate in front of the loop.
624 We search for the first insn or label in the loop, skipping NOTEs.
625 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
626 (because we might have a loop executed only once that contains a
627 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
628 (in case we have a degenerate loop).
630 Note that if we mistakenly think that a loop is entered at the top
631 when, in fact, it is entered at the exit test, the only effect will be
632 slightly poorer optimization. Making the opposite error can generate
633 incorrect code. Since very few loops now start with a jump to the
634 exit test, the code here to detect that case is very conservative. */
637 p != loop_end
643 ;
647 /* If loop end is the end of the current function, then emit a
648 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
649 note insn. This is the position we use when sinking insns out of
650 the loop. */
653 else
656 /* Set up variables describing this loop. */
660 /* If loop has a jump before the first label,
661 the true entry is the target of that jump.
662 Start scan from there.
663 But record in LOOP->TOP the place where the end-test jumps
664 back to so we can scan that after the end of the loop. */
666 /* Loop entry must be unconditional jump (and not a RETURN) */
669 /* Check to see whether the jump actually
670 jumps out of the loop (meaning it's no loop).
671 This case can happen for things like
672 do {..} while (0). If this label was generated previously
673 by loop, we can't tell anything about it and have to reject
674 the loop. */
676 {
679 }
681 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
682 as required by loop_reg_used_before_p. So skip such loops. (This
683 test may never be true, but it's best to play it safe.)
685 Also, skip loops where we do not start scanning at a label. This
686 test also rejects loops starting with a JUMP_INSN that failed the
687 test above. */
691 {
696 }
698 /* Allocate extra space for REGs that might be created by load_mems.
699 We allocate a little extra slop as well, in the hopes that we
700 won't have to reallocate the regs array. */
705 {
711 }
713 /* Scan through the loop finding insns that are safe to move.
714 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
715 this reg will be considered invariant for subsequent insns.
716 We consider whether subsequent insns use the reg
717 in deciding whether it is worth actually moving.
719 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
720 and therefore it is possible that the insns we are scanning
721 would never be executed. At such times, we must make sure
722 that it is safe to execute the insn once instead of zero times.
723 When MAYBE_NEVER is 0, all insns will be executed at least once
724 so that is not a problem. */
729 {
731 in_libcall--;
733 {
736 in_libcall++;
740 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
742 #endif
744 {
752 /* Figure out what to use as a source of this insn. If a
753 REG_EQUIV note is given or if a REG_EQUAL note with a
754 constant operand is specified, use it as the source and
755 mark that we should move this insn by calling
756 emit_move_insn rather that duplicating the insn.
758 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
759 note is present. */
763 else
764 {
769 {
771 /* A libcall block can use regs that don't appear in
772 the equivalent expression. To move the libcall,
773 we must move those regs too. */
775 }
776 }
778 /* For parallels, add any possible uses to the dependencies, as
779 we can't move the insn without resolving them first. */
781 {
783 {
786 dependencies
788 dependencies);
789 }
790 }
793 than the one where it is set (meaning that
794 something after this point in the loop might
795 depend on its value before the set). */
797 /* And the set is not guaranteed to be executed once
798 the loop starts, or the value before the set is
799 needed before the set occurs...
801 ??? Note we have quadratic behavior here, mitigated
802 by the fact that the previous test will often fail for
803 large loops. Rather than re-scanning the entire loop
804 each time for register usage, we should build tables
805 of the register usage and use them here instead. */
806 && (maybe_never
808 /* It is unsafe to move the set. However, it may be OK to
809 move the source into a new pseudo, and substitute a
810 reg-to-reg copy for the original insn.
812 This code used to consider it OK to move a set of a variable
813 which was not created by the user and not used in an exit
814 test.
815 That behavior is incorrect and was removed. */
818 /* Don't try to optimize a MODE_CC set with a constant
819 source. It probably will be combined with a conditional
820 jump. */
823 ;
824 /* Don't try to optimize a register that was made
825 by loop-optimization for an inner loop.
826 We don't know its life-span, so we can't compute
827 the benefit. */
829 ;
830 /* Don't move the source and add a reg-to-reg copy:
831 - with -Os (this certainly increases size),
832 - if the mode doesn't support copy operations (obviously),
833 - if the source is already a reg (the motion will gain nothing),
834 - if the source is a legitimate constant (likewise). */
836 && (optimize_size
841 ;
844 || (tem2
847 || (tem1
848 = consec_sets_invariant_p
851 p)))
852 /* If the insn can cause a trap (such as divide by zero),
853 can't move it unless it's guaranteed to be executed
854 once loop is entered. Even a function call might
855 prevent the trap insn from being reached
856 (since it might exit!) */
859 {
863 /* A potential lossage is where we have a case where two insns
864 can be combined as long as they are both in the loop, but
865 we move one of them outside the loop. For large loops,
866 this can lose. The most common case of this is the address
867 of a function being called.
869 Therefore, if this register is marked as being used
870 exactly once if we are in a loop with calls
871 (a "large loop"), see if we can replace the usage of
872 this register with the source of this SET. If we can,
873 delete this insn.
875 Don't do this if P has a REG_RETVAL note or if we have
876 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
888 && (! SMALL_REGISTER_CLASSES
892 /* This test is not redundant; SET_SRC (set) might be
893 a call-clobbered register and the life of REGNO
894 might span a call. */
901 {
902 /* Replace any usage in a REG_EQUAL note. Must copy
903 the new source, so that we don't get rtx sharing
904 between the SET_SOURCE and REG_NOTES of insn p. */
906 = (replace_rtx
912 i++)
915 }
924 m->consec
935 /* Set M->cond if either loop_invariant_p
936 or consec_sets_invariant_p returned 2
937 (only conditionally invariant). */
947 /* Add M to the end of the chain MOVABLES. */
951 {
952 /* It is possible for the first instruction to have a
953 REG_EQUAL note but a non-invariant SET_SRC, so we must
954 remember the status of the first instruction in case
955 the last instruction doesn't have a REG_EQUAL note. */
958 /* Skip this insn, not checking REG_LIBCALL notes. */
960 /* Skip the consecutive insns, if there are any. */
962 /* Back up to the last insn of the consecutive group. */
965 /* We must now reset m->move_insn, m->is_equiv, and
966 possibly m->set_src to correspond to the effects of
967 all the insns. */
971 else
972 {
976 else
979 }
980 m->is_equiv
982 }
983 }
984 /* If this register is always set within a STRICT_LOW_PART
985 or set to zero, then its high bytes are constant.
986 So clear them outside the loop and within the loop
987 just load the low bytes.
988 We must check that the machine has an instruction to do so.
989 Also, if the value loaded into the register
990 depends on the same register, this cannot be done. */
1000 {
1003 {
1018 /* If the insn may not be executed on some cycles,
1019 we can't clear the whole reg; clear just high part.
1020 Not even if the reg is used only within this loop.
1021 Consider this:
1022 while (1)
1023 while (s != t) {
1024 if (foo ()) x = *s;
1025 use (x);
1026 }
1027 Clearing x before the inner loop could clobber a value
1028 being saved from the last time around the outer loop.
1029 However, if the reg is not used outside this loop
1030 and all uses of the register are in the same
1031 basic block as the store, there is no problem.
1033 If this insn was made by loop, we don't know its
1034 INSN_LUID and hence must make a conservative
1035 assumption. */
1038 || (labels_in_range_p
1042 else
1051 i++)
1053 /* Add M to the end of the chain MOVABLES. */
1055 }
1056 }
1057 }
1058 }
1059 /* Past a call insn, we get to insns which might not be executed
1060 because the call might exit. This matters for insns that trap.
1061 Constant and pure call insns always return, so they don't count. */
1064 /* Past a label or a jump, we get to insns for which we
1065 can't count on whether or how many times they will be
1066 executed during each iteration. Therefore, we can
1067 only move out sets of trivial variables
1068 (those not used after the loop). */
1069 /* Similar code appears twice in strength_reduce. */
1071 /* If we enter the loop in the middle, and scan around to the
1072 beginning, don't set maybe_never for that. This must be an
1073 unconditional jump, otherwise the code at the top of the
1074 loop might never be executed. Unconditional jumps are
1075 followed by a barrier then the loop_end. */
1081 {
1082 /* At the virtual top of a converted loop, insns are again known to
1083 be executed: logically, the loop begins here even though the exit
1084 code has been duplicated. */
1088 loop_depth++;
1090 loop_depth--;
1091 }
1092 }
1094 /* If one movable subsumes another, ignore that other. */
1098 /* For each movable insn, see if the reg that it loads
1099 leads when it dies right into another conditionally movable insn.
1100 If so, record that the second insn "forces" the first one,
1101 since the second can be moved only if the first is. */
1105 /* See if there are multiple movable insns that load the same value.
1106 If there are, make all but the first point at the first one
1107 through the `match' field, and add the priorities of them
1108 all together as the priority of the first. */
1112 /* Now consider each movable insn to decide whether it is worth moving.
1113 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1115 For machines with few registers this increases code size, so do not
1116 move moveables when optimizing for code size on such machines.
1117 (The 18 below is the value for i386.) */
1121 {
1124 /* Recalculate regs->array if move_movables has created new
1125 registers. */
1127 {
1133 ;
1138 }
1139 }
1141 /* Now candidates that still are negative are those not moved.
1142 Change regs->array[I].set_in_loop to indicate that those are not actually
1143 invariant. */
1148 /* Now that we've moved some things out of the loop, we might be able to
1149 hoist even more memory references. */
1152 /* Recalculate regs->array if load_mems has created new registers. */
1160 ;
1167 {
1169 /* Ensure our label doesn't go away. */
1180 }
1183 /* The movable information is required for strength reduction. */
1189 }
1190 \f
1191 /* Add elements to *OUTPUT to record all the pseudo-regs
1192 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1194 void
1196 {
1204 {
1222 }
1226 {
1230 {
1239 }
1240 }
1241 }
1242 \f
1243 /* Check what regs are referred to in the libcall block ending with INSN,
1244 aside from those mentioned in the equivalent value.
1245 If there are none, return 0.
1246 If there are one or more, return an EXPR_LIST containing all of them. */
1248 rtx
1250 {
1255 /* First, find all the regs used in the libcall block
1256 that are not mentioned as inputs to the result. */
1259 {
1264 }
1267 }
1268 \f
1269 /* Return 1 if all uses of REG
1270 are between INSN and the end of the basic block. */
1272 static int
1274 {
1276 rtx p;
1281 /* Search this basic block for the already recorded last use of the reg. */
1283 {
1285 {
1291 /* Ordinary insn: if this is the last use, we win. */
1297 /* Jump insn: if this is the last use, we win. */
1300 /* Otherwise, it's the end of the basic block, so we lose. */
1305 /* It's the end of the basic block, so we lose. */
1310 }
1311 }
1313 /* The "last use" that was recorded can't be found after the first
1314 use. This can happen when the last use was deleted while
1315 processing an inner loop, this inner loop was then completely
1316 unrolled, and the outer loop is always exited after the inner loop,
1317 so that everything after the first use becomes a single basic block. */
1319 }
1320 \f
1321 /* Compute the benefit of eliminating the insns in the block whose
1322 last insn is LAST. This may be a group of insns used to compute a
1323 value directly or can contain a library call. */
1325 static int
1327 {
1328 rtx insn;
1333 {
1336 routine. */
1340 benefit++;
1341 }
1344 }
1345 \f
1346 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1348 static rtx
1350 {
1352 {
1353 rtx temp;
1355 /* If first insn of libcall sequence, skip to end. */
1356 /* Do this at start of loop, since INSN is guaranteed to
1357 be an insn here. */
1362 do
1365 }
1368 }
1370 /* Ignore any movable whose insn falls within a libcall
1371 which is part of another movable.
1372 We make use of the fact that the movable for the libcall value
1373 was made later and so appears later on the chain. */
1375 static void
1377 {
1381 {
1382 /* Is this a movable for the value of a libcall? */
1385 {
1386 rtx insn;
1387 /* Check for earlier movables inside that range,
1388 and mark them invalid. We cannot use LUIDs here because
1389 insns created by loop.c for prior loops don't have LUIDs.
1390 Rather than reject all such insns from movables, we just
1391 explicitly check each insn in the libcall (since invariant
1392 libcalls aren't that common). */
1397 }
1398 }
1399 }
1401 /* For each movable insn, see if the reg that it loads
1402 leads when it dies right into another conditionally movable insn.
1403 If so, record that the second insn "forces" the first one,
1404 since the second can be moved only if the first is. */
1406 static void
1408 {
1412 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1414 {
1417 /* ??? Could this be a bug? What if CSE caused the
1418 register of M1 to be used after this insn?
1419 Since CSE does not update regno_last_uid,
1420 this insn M->insn might not be where it dies.
1421 But very likely this doesn't matter; what matters is
1422 that M's reg is computed from M1's reg. */
1427 /* If m->consec, m->set_src isn't valid. */
1431 /* Increase the priority of the moving the first insn
1432 since it permits the second to be moved as well. */
1434 {
1438 }
1439 }
1440 }
1441 \f
1442 /* Find invariant expressions that are equal and can be combined into
1443 one register. */
1445 static void
1447 {
1452 /* Regs that are set more than once are not allowed to match
1453 or be matched. I'm no longer sure why not. */
1454 /* Only pseudo registers are allowed to match or be matched,
1455 since move_movables does not validate the change. */
1456 /* Perhaps testing m->consec_sets would be more appropriate here? */
1463 {
1470 /* We want later insns to match the first one. Don't make the first
1471 one match any later ones. So start this loop at m->next. */
1477 /* A reg used outside the loop mustn't be eliminated. */
1479 /* A reg used for zero-extending mustn't be eliminated. */
1482 ||
1483 (
1484 /* Can combine regs with different modes loaded from the
1485 same constant only if the modes are the same or
1486 if both are integer modes with M wider or the same
1487 width as M1. The check for integer is redundant, but
1488 safe, since the only case of differing destination
1489 modes with equal sources is when both sources are
1490 VOIDmode, i.e., CONST_INT. */
1496 /* See if the source of M1 says it matches M. */
1503 {
1509 }
1510 }
1512 /* Now combine the regs used for zero-extension.
1513 This can be done for those not marked `global'
1514 provided their lives don't overlap. */
1518 {
1521 /* Combine all the registers for extension from mode MODE.
1522 Don't combine any that are used outside this loop. */
1526 {
1533 {
1534 /* First one: don't check for overlap, just record it. */
1537 }
1539 /* Make sure they extend to the same mode.
1540 (Almost always true.) */
1544 /* We already have one: check for overlap with those
1545 already combined together. */
1552 /* No overlap: we can combine this with the others. */
1558 overlap:
1559 ;
1560 }
1561 }
1563 /* Clean up. */
1565 }
1567 /* Returns the number of movable instructions in LOOP that were not
1568 moved outside the loop. */
1570 static int
1572 {
1581 }
1583 \f
1584 /* Return 1 if regs X and Y will become the same if moved. */
1586 static int
1588 {
1605 }
1607 /* Return 1 if X and Y are identical-looking rtx's.
1608 This is the Lisp function EQUAL for rtx arguments.
1610 If two registers are matching movables or a movable register and an
1611 equivalent constant, consider them equal. */
1613 static int
1616 {
1630 /* If we have a register and a constant, they may sometimes be
1631 equal. */
1634 {
1639 }
1642 {
1647 }
1649 /* Otherwise, rtx's of different codes cannot be equal. */
1653 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1654 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1659 /* These three types of rtx's can be compared nonrecursively. */
1668 /* Compare the elements. If any pair of corresponding elements
1669 fail to match, return 0 for the whole things. */
1673 {
1675 {
1687 /* Two vectors must have the same length. */
1691 /* And the corresponding elements must match. */
1710 /* These are just backpointers, so they don't matter. */
1716 /* It is believed that rtx's at this level will never
1717 contain anything but integers and other rtx's,
1718 except for within LABEL_REFs and SYMBOL_REFs. */
1721 }
1722 }
1724 }
1725 \f
1726 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1727 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1728 references is incremented once for each added note. */
1730 static void
1732 {
1736 rtx insn;
1739 {
1740 /* This code used to ignore labels that referred to dispatch tables to
1741 avoid flow generating (slightly) worse code.
1743 We no longer ignore such label references (see LABEL_REF handling in
1744 mark_jump_label for additional information). */
1747 {
1752 }
1753 }
1757 {
1763 }
1764 }
1765 \f
1766 /* Scan MOVABLES, and move the insns that deserve to be moved.
1767 If two matching movables are combined, replace one reg with the
1768 other throughout. */
1770 static void
1773 {
1778 rtx p;
1781 /* Map of pseudo-register replacements to handle combining
1782 when we move several insns that load the same value
1783 into different pseudo-registers. */
1788 {
1789 /* Describe this movable insn. */
1792 {
1813 }
1815 /* Ignore the insn if it's already done (it matched something else).
1816 Otherwise, see if it is now safe to move. */
1828 {
1830 rtx p;
1833 /* We have an insn that is safe to move.
1834 Compute its desirability. */
1845 /* An insn MUST be moved if we already moved something else
1846 which is safe only if this one is moved too: that is,
1847 if already_moved[REGNO] is nonzero. */
1849 /* An insn is desirable to move if the new lifetime of the
1850 register is no more than THRESHOLD times the old lifetime.
1851 If it's not desirable, it means the loop is so big
1852 that moving won't speed things up much,
1853 and it is liable to make register usage worse. */
1855 /* It is also desirable to move if it can be moved at no
1856 extra cost because something else was already moved. */
1859 || flag_move_all_movables
1864 {
1873 /* Now move the insns that set the reg. */
1876 {
1879 /* Find the end of this chain of matching regs.
1880 Thus, we load each reg in the chain from that one reg.
1881 And that reg is loaded with 0 directly,
1882 since it has ->match == 0. */
1888 /* Mark the moved, invariant reg as being allowed to
1889 share a hard reg with the other matching invariant. */
1893 regs_may_share
1896 regs_may_share));
1904 }
1905 /* If we are to re-generate the item being moved with a
1906 new move insn, first delete what we have and then emit
1907 the move insn before the loop. */
1909 {
1913 {
1914 /* If this is the first insn of a library call sequence,
1915 something is very wrong. */
1920 /* If this is the last insn of a libcall sequence, then
1921 delete every insn in the sequence except the last.
1922 The last insn is handled in the normal manner. */
1925 {
1929 }
1934 /* simplify_giv_expr expects that it can walk the insns
1935 at m->insn forwards and see this old sequence we are
1936 tossing here. delete_insn does preserve the next
1937 pointers, but when we skip over a NOTE we must fix
1938 it up. Otherwise that code walks into the non-deleted
1939 insn stream. */
1944 {
1945 /* Replace the original insn with a move from
1946 our newly created temp. */
1952 }
1953 }
1972 /* The more regs we move, the less we like moving them. */
1974 }
1975 else
1976 {
1978 {
1981 /* If first insn of libcall sequence, skip to end. */
1982 /* Do this at start of loop, since p is guaranteed to
1983 be an insn here. */
1988 /* If last insn of libcall sequence, move all
1989 insns except the last before the loop. The last
1990 insn is handled in the normal manner. */
1993 {
2001 {
2002 rtx body;
2003 rtx n;
2004 rtx next;
2011 /* Find the next insn after TEMP,
2012 not counting USE or NOTE insns. */
2020 /* If that is the call, this may be the insn
2021 that loads the function address.
2023 Extract the function address from the insn
2024 that loads it into a register.
2025 If this insn was cse'd, we get incorrect code.
2027 So emit a new move insn that copies the
2028 function address into the register that the
2029 call insn will use. flow.c will delete any
2030 redundant stores that we have created. */
2035 NULL_RTX)))
2036 {
2042 }
2043 /* We have the call insn.
2044 If it uses the register we suspect it might,
2045 load it with the correct address directly. */
2050 gen_move_insn
2054 {
2056 /* Because the USAGE information potentially
2057 contains objects other than hard registers
2058 we need to copy it. */
2062 }
2063 else
2072 }
2075 }
2077 {
2078 /* P sets REG to zero; but we should clear only
2079 the bits that are not covered by the mode
2080 m->savemode. */
2082 rtx sequence;
2083 rtx tem;
2086 tem = expand_simple_binop
2099 }
2101 {
2103 /* Because the USAGE information potentially
2104 contains objects other than hard registers
2105 we need to copy it. */
2109 }
2111 {
2112 rtx seq;
2113 /* The SET_SRC might not be invariant, so we must
2114 use the REG_EQUAL note. */
2126 }
2128 {
2136 }
2137 else
2141 {
2145 /* If there is a REG_EQUAL note present whose value
2146 is not loop invariant, then delete it, since it
2147 may cause problems with later optimization passes.
2148 It is possible for cse to create such notes
2149 like this as a result of record_jump_cond. */
2154 }
2163 /* If library call, now fix the REG_NOTES that contain
2164 insn pointers, namely REG_LIBCALL on FIRST
2165 and REG_RETVAL on I1. */
2167 {
2171 }
2177 /* simplify_giv_expr expects that it can walk the insns
2178 at m->insn forwards and see this old sequence we are
2179 tossing here. delete_insn does preserve the next
2180 pointers, but when we skip over a NOTE we must fix
2181 it up. Otherwise that code walks into the non-deleted
2182 insn stream. */
2187 {
2188 rtx seq;
2189 /* Replace the original insn with a move from
2190 our newly created temp. */
2196 }
2197 }
2199 /* The more regs we move, the less we like moving them. */
2201 }
2206 {
2207 /* Any other movable that loads the same register
2208 MUST be moved. */
2211 /* This reg has been moved out of one loop. */
2214 /* The reg set here is now invariant. */
2216 {
2220 }
2222 /* Change the length-of-life info for the register
2223 to say it lives at least the full length of this loop.
2224 This will help guide optimizations in outer loops. */
2227 /* This is the old insn before all the moved insns.
2228 We can't use the moved insn because it is out of range
2229 in uid_luid. Only the old insns have luids. */
2233 }
2235 /* Combine with this moved insn any other matching movables. */
2240 {
2241 rtx temp;
2243 /* Schedule the reg loaded by M1
2244 for replacement so that shares the reg of M.
2245 If the modes differ (only possible in restricted
2246 circumstances, make a SUBREG.
2248 Note this assumes that the target dependent files
2249 treat REG and SUBREG equally, including within
2250 GO_IF_LEGITIMATE_ADDRESS and in all the
2251 predicates since we never verify that replacing the
2252 original register with a SUBREG results in a
2253 recognizable insn. */
2256 else
2261 /* Get rid of the matching insn
2262 and prevent further processing of it. */
2265 /* If library call, delete all insns. */
2267 NULL_RTX)))
2269 else
2272 /* Any other movable that loads the same register
2273 MUST be moved. */
2276 /* The reg merged here is now invariant,
2277 if the reg it matches is invariant. */
2279 {
2283 i++)
2285 }
2286 }
2287 }
2290 }
2296 }
2301 /* Go through all the instructions in the loop, making
2302 all the register substitutions scheduled in REG_MAP. */
2306 {
2310 }
2312 /* Clean up. */
2315 }
2318 static void
2320 {
2323 else
2326 }
2329 static void
2331 {
2336 {
2339 }
2340 }
2341 \f
2342 #if 0
2343 /* Scan X and replace the address of any MEM in it with ADDR.
2344 REG is the address that MEM should have before the replacement. */
2346 static void
2348 {
2357 {
2369 /* Short cut for very common case. */
2374 /* Short cut for very common case. */
2379 /* If this MEM uses a reg other than the one we expected,
2380 something is wrong. */
2388 }
2392 {
2396 {
2400 }
2401 }
2402 }
2403 #endif
2404 \f
2405 /* Return the number of memory refs to addresses that vary
2406 in the rtx X. */
2408 static int
2410 {
2421 {
2438 }
2443 {
2447 {
2451 }
2452 }
2454 }
2455 \f
2456 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2457 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2458 `unknown_address_altered', `unknown_constant_address_altered', and
2459 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2460 list `store_mems' in LOOP. */
2462 static void
2464 {
2466 rtx insn;
2470 /* The label after END. Jumping here is just like falling off the
2471 end of the loop. We use next_nonnote_insn instead of next_label
2472 as a hedge against the (pathological) case where some actual insn
2473 might end up between the two. */
2492 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2497 {
2499 {
2502 }
2503 }
2507 {
2509 {
2512 {
2514 /* Count number of loops contained in this one. */
2516 }
2523 {
2526 }
2533 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2534 attached FUNCTION_USAGE expression list, not accounted for by the
2535 code above. We should note these to avoid missing dependencies in
2536 later references. */
2537 {
2538 rtx fusage_entry;
2542 {
2548 {
2553 }
2554 }
2555 }
2560 {
2564 {
2569 {
2572 }
2573 else
2574 {
2577 }
2579 do
2580 {
2582 {
2584 {
2585 /* Something tricky. */
2588 }
2591 {
2592 /* A jump outside the current loop. */
2595 }
2596 }
2600 }
2602 }
2603 else
2604 {
2605 /* A return, or something tricky. */
2607 }
2608 }
2609 /* FALLTHRU */
2630 }
2631 }
2633 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2635 anywhere. */
2637 /* We don't want loads for MEMs moved to a location before the
2638 one at which their stack memory becomes allocated. (Note
2639 that this is not a problem for malloc, etc., since those
2640 require actual function calls. */
2641 && ! current_function_calls_alloca
2642 /* There are ways to leave the loop other than falling off the
2643 end. */
2649 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2650 that loop_invariant_p and load_mems can use true_dependence
2651 to determine what is really clobbered. */
2653 {
2656 loop_info->store_mems
2658 }
2660 {
2664 loop_info->store_mems
2666 }
2667 }
2668 \f
2669 /* Invalidate all loops containing LABEL. */
2671 static void
2673 {
2677 }
2679 /* Scan the function looking for loops. Record the start and end of each loop.
2680 Also mark as invalid loops any loops that contain a setjmp or are branched
2681 to from outside the loop. */
2683 static void
2685 {
2686 rtx insn;
2687 rtx label;
2697 /* If there are jumps to undefined labels,
2698 treat them as jumps out of any/all loops.
2699 This also avoids writing past end of tables when there are no loops. */
2702 /* Find boundaries of loops, mark which loops are contained within
2703 loops, and invalidate loops that have setjmp. */
2708 {
2711 {
2715 num_loops++;
2739 }
2743 {
2744 /* In this case, we must invalidate our current loop and any
2745 enclosing loop. */
2747 {
2753 }
2754 }
2756 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2757 enclosing loop, but this doesn't matter. */
2759 }
2761 /* Any loop containing a label used in an initializer must be invalidated,
2762 because it can be jumped into from anywhere. */
2766 /* Any loop containing a label used for an exception handler must be
2767 invalidated, because it can be jumped into from anywhere. */
2770 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2771 loop that it is not contained within, that loop is marked invalid.
2772 If any INSN or CALL_INSN uses a label's address, then the loop containing
2773 that label is marked invalid, because it could be jumped into from
2774 anywhere.
2776 Also look for blocks of code ending in an unconditional branch that
2777 exits the loop. If such a block is surrounded by a conditional
2778 branch around the block, move the block elsewhere (see below) and
2779 invert the jump to point to the code block. This may eliminate a
2780 label in our loop and will simplify processing by both us and a
2781 possible second cse pass. */
2785 {
2789 {
2793 }
2800 /* See if this is an unconditional branch outside the loop. */
2808 {
2809 rtx p;
2815 /* Go backwards until we reach the start of the loop, a label,
2816 or a JUMP_INSN. */
2823 ;
2825 /* Check for the case where we have a jump to an inner nested
2826 loop, and do not perform the optimization in that case. */
2829 {
2832 {
2837 }
2838 }
2840 /* Make sure that the target of P is within the current loop. */
2846 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2847 we have a block of code to try to move.
2849 We look backward and then forward from the target of INSN
2850 to find a BARRIER at the same loop depth as the target.
2851 If we find such a BARRIER, we make a new label for the start
2852 of the block, invert the jump in P and point it to that label,
2853 and move the block of code to the spot we found. */
2858 /* Just ignore jumps to labels that were never emitted.
2859 These always indicate compilation errors. */
2863 /* If it's not safe to move the sequence, then we
2864 mustn't try. */
2867 {
2868 rtx target
2872 rtx tmp;
2874 /* Search for possible garbage past the conditional jumps
2875 and look for the last barrier. */
2883 /* Don't move things inside a tablejump. */
2896 /* Don't move things inside a tablejump. */
2907 {
2911 /* Ensure our label doesn't go away. */
2914 /* Verify that uid_loop is large enough and that
2915 we can invert P. */
2917 {
2920 /* If no suitable BARRIER was found, create a suitable
2921 one before TARGET. Since TARGET is a fall through
2922 path, we'll need to insert a jump around our block
2923 and add a BARRIER before TARGET.
2925 This creates an extra unconditional jump outside
2926 the loop. However, the benefits of removing rarely
2927 executed instructions from inside the loop usually
2928 outweighs the cost of the extra unconditional jump
2929 outside the loop. */
2931 {
2932 rtx temp;
2939 }
2941 /* Include the BARRIER after INSN and copy the
2942 block after LOC. */
2947 /* All those insns are now in TARGET_LOOP. */
2953 /* The label jumped to by INSN is no longer a loop
2954 exit. Unless INSN does not have a label (e.g.,
2955 it is a RETURN insn), search loop->exit_labels
2956 to find its label_ref, and remove it. Also turn
2957 off LABEL_OUTSIDE_LOOP_P bit. */
2959 {
2961 r;
2964 {
2968 else
2971 }
2977 /* If we didn't find it, then something is
2978 wrong. */
2981 }
2983 /* P is now a jump outside the loop, so it must be put
2984 in loop->exit_labels, and marked as such.
2985 The easiest way to do this is to just call
2986 mark_loop_jump again for P. */
2989 /* If INSN now jumps to the insn after it,
2990 delete INSN. */
2995 }
2997 /* Continue the loop after where the conditional
2998 branch used to jump, since the only branch insn
2999 in the block (if it still remains) is an inter-loop
3000 branch and hence needs no processing. */
3006 /* This loop will be continued with NEXT_INSN (insn). */
3008 }
3009 }
3010 }
3011 }
3012 }
3014 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3015 loops it is contained in, mark the target loop invalid.
3017 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3019 static void
3021 {
3027 {
3039 /* There could be a label reference in here. */
3051 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3063 /* Link together all labels that branch outside the loop. This
3064 is used by final_[bg]iv_value and the loop unrolling code. Also
3065 mark this LABEL_REF so we know that this branch should predict
3066 false. */
3068 /* A check to make sure the label is not in an inner nested loop,
3069 since this does not count as a loop exit. */
3071 {
3076 }
3077 else
3081 {
3090 }
3092 /* If this is inside a loop, but not in the current loop or one enclosed
3093 by it, it invalidates at least one loop. */
3098 /* We must invalidate every nested loop containing the target of this
3099 label, except those that also contain the jump insn. */
3102 {
3103 /* Stop when we reach a loop that also contains the jump insn. */
3108 /* If we get here, we know we need to invalidate a loop. */
3115 }
3119 /* If this is not setting pc, ignore. */
3141 /* Strictly speaking this is not a jump into the loop, only a possible
3142 jump out of the loop. However, we have no way to link the destination
3143 of this jump onto the list of exit labels. To be safe we mark this
3144 loop and any containing loops as invalid. */
3146 {
3148 {
3154 }
3155 }
3157 }
3158 }
3159 \f
3160 /* Return nonzero if there is a label in the range from
3161 insn INSN to and including the insn whose luid is END
3162 INSN must have an assigned luid (i.e., it must not have
3163 been previously created by loop.c). */
3165 static int
3167 {
3169 {
3173 }
3176 }
3178 /* Record that a memory reference X is being set. */
3180 static void
3183 {
3189 /* Count number of memory writes.
3190 This affects heuristics in strength_reduce. */
3193 /* BLKmode MEM means all memory is clobbered. */
3195 {
3198 else
3202 }
3206 }
3208 /* X is a value modified by an INSN that references a biv inside a loop
3209 exit test (ie, X is somehow related to the value of the biv). If X
3210 is a pseudo that is used more than once, then the biv is (effectively)
3211 used more than once. DATA is a pointer to a loop_regs structure. */
3213 static void
3215 {
3230 /* If we do not have usage information, or if we know the register
3231 is used more than once, note that fact for check_dbra_loop. */
3236 }
3237 \f
3238 /* Return nonzero if the rtx X is invariant over the current loop.
3240 The value is 2 if we refer to something only conditionally invariant.
3242 A memory ref is invariant if it is not volatile and does not conflict
3243 with anything stored in `loop_info->store_mems'. */
3245 int
3247 {
3254 rtx mem_list_entry;
3260 {
3268 /* A LABEL_REF is normally invariant, however, if we are unrolling
3269 loops, and this label is inside the loop, then it isn't invariant.
3270 This is because each unrolled copy of the loop body will have
3271 a copy of this label. If this was invariant, then an insn loading
3272 the address of this label into a register might get moved outside
3273 the loop, and then each loop body would end up using the same label.
3275 We don't know the loop bounds here though, so just fail for all
3276 labels. */
3279 else
3288 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3289 since the reg might be set by initialization within the loop. */
3300 /* Out-of-range regs can occur when we are called from unrolling.
3301 These have always been created by the unroller and are set in
3302 the loop, hence are never invariant. */
3313 /* Volatile memory references must be rejected. Do this before
3314 checking for read-only items, so that volatile read-only items
3315 will be rejected also. */
3319 /* See if there is any dependence between a store and this load. */
3322 {
3328 }
3330 /* It's not invalidated by a store in memory
3331 but we must still verify the address is invariant. */
3335 /* Don't mess with insns declared volatile. */
3342 }
3346 {
3348 {
3354 }
3356 {
3359 {
3365 }
3367 }
3368 }
3371 }
3372 \f
3373 /* Return nonzero if all the insns in the loop that set REG
3374 are INSN and the immediately following insns,
3375 and if each of those insns sets REG in an invariant way
3376 (not counting uses of REG in them).
3378 The value is 2 if some of these insns are only conditionally invariant.
3380 We assume that INSN itself is the first set of REG
3381 and that its source is invariant. */
3383 static int
3385 rtx insn)
3386 {
3390 rtx temp;
3391 /* Number of sets we have to insist on finding after INSN. */
3397 /* If N_SETS hit the limit, we can't rely on its value. */
3404 {
3406 rtx set;
3411 /* If library call, skip to end of it. */
3420 {
3425 {
3426 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3427 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3428 notes are OK. */
3434 }
3435 }
3437 count--;
3439 {
3442 }
3443 }
3446 /* If loop_invariant_p ever returned 2, we return 2. */
3448 }
3450 #if 0
3451 /* I don't think this condition is sufficient to allow INSN
3452 to be moved, so we no longer test it. */
3454 /* Return 1 if all insns in the basic block of INSN and following INSN
3455 that set REG are invariant according to TABLE. */
3457 static int
3459 {
3464 {
3473 {
3476 }
3477 }
3478 }
3480 \f
3481 /* Look at all uses (not sets) of registers in X. For each, if it is
3482 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3483 a different insn, set USAGE[REGNO] to const0_rtx. */
3485 static void
3487 {
3499 {
3500 /* Don't count SET_DEST if it is a REG; otherwise count things
3501 in SET_DEST because if a register is partially modified, it won't
3502 show up as a potential movable so we don't care how USAGE is set
3503 for it. */
3507 }
3508 else
3510 {
3516 }
3517 }
3518 \f
3519 /* Count and record any set in X which is contained in INSN. Update
3520 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3521 in X. */
3523 static void
3525 {
3527 /* Don't move a reg that has an explicit clobber.
3528 It's not worth the pain to try to do it correctly. */
3532 {
3540 {
3544 {
3545 /* If this is the first setting of this reg
3546 in current basic block, and it was set before,
3547 it must be set in two basic blocks, so it cannot
3548 be moved out of the loop. */
3552 /* If this is not first setting in current basic block,
3553 see if reg was used in between previous one and this.
3554 If so, neither one can be moved. */
3561 }
3562 }
3563 }
3564 }
3565 \f
3566 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3567 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3568 contained in insn INSN is used by any insn that precedes INSN in
3569 cyclic order starting from the loop entry point.
3571 We don't want to use INSN_LUID here because if we restrict INSN to those
3572 that have a valid INSN_LUID, it means we cannot move an invariant out
3573 from an inner loop past two loops. */
3575 static int
3577 {
3579 rtx p;
3581 /* Scan forward checking for register usage. If we hit INSN, we
3582 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3584 {
3590 }
3593 }
3594 \f
3596 /* Information we collect about arrays that we might want to prefetch. */
3597 struct prefetch_info
3598 {
3602 index. */
3603 HOST_WIDE_INT index;
3605 iteration. */
3607 prefetch area in one iteration. */
3609 This is set only for loops with known
3610 iteration counts and is 0xffffffff
3611 otherwise. */
3615 };
3617 /* Data used by check_store function. */
3618 struct check_store_data
3619 {
3620 rtx mem_address;
3622 };
3628 /* Set mem_write when mem_address is found. Used as callback to
3629 note_stores. */
3630 static void
3632 {
3637 }
3638 \f
3639 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3640 important to get some addresses combined. Later more sophisticated
3641 transformations can be added when necessary.
3643 ??? Same trick with swapping operand is done at several other places.
3644 It can be nice to develop some common way to handle this. */
3646 static int
3648 {
3662 {
3667 }
3668 /* Compare the elements. If any pair of corresponding elements fails to
3669 match, return 0 for the whole thing. */
3673 {
3675 {
3687 /* Two vectors must have the same length. */
3691 /* And the corresponding elements must match. */
3709 /* These are just backpointers, so they don't matter. */
3715 /* It is believed that rtx's at this level will never
3716 contain anything but integers and other rtx's,
3717 except for within LABEL_REFs and SYMBOL_REFs. */
3720 }
3721 }
3723 }
3724 \f
3725 /* Remove constant addition value from the expression X (when present)
3726 and return it. */
3728 static HOST_WIDE_INT
3730 {
3734 /* Avoid clobbering a shared CONST expression. */
3736 {
3740 {
3743 }
3745 }
3748 {
3751 }
3753 /* For plus expression recurse on ourself. */
3755 {
3759 /* In case our parameter was constant, remove extra zero from the
3760 expression. */
3765 }
3768 }
3770 /* Attempt to identify accesses to arrays that are most likely to cause cache
3771 misses, and emit prefetch instructions a few prefetch blocks forward.
3773 To detect the arrays we use the GIV information that was collected by the
3774 strength reduction pass.
3776 The prefetch instructions are generated after the GIV information is done
3777 and before the strength reduction process. The new GIVs are injected into
3778 the strength reduction tables, so the prefetch addresses are optimized as
3779 well.
3781 GIVs are split into base address, stride, and constant addition values.
3782 GIVs with the same address, stride and close addition values are combined
3783 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3784 for write instructions can be used for the block we write to, on machines
3785 that support write prefetches.
3787 Several heuristics are used to determine when to prefetch. They are
3788 controlled by defined symbols that can be overridden for each target. */
3790 static void
3792 {
3808 /* Consider only loops w/o calls. When a call is done, the loop is probably
3809 slow enough to read the memory. */
3811 {
3816 }
3818 /* Don't prefetch in loops known to have few iterations. */
3822 {
3827 }
3829 /* Search all induction variables and pick those interesting for the prefetch
3830 machinery. */
3832 {
3838 /* Expect all BIVs to be executed in each iteration. This makes our
3839 analysis more conservative. */
3841 {
3842 /* Discard non-constant additions that we can't handle well yet, and
3843 BIVs that are executed multiple times; such BIVs ought to be
3844 handled in the nested loop. We accept not_every_iteration BIVs,
3845 since these only result in larger strides and make our
3846 heuristics more conservative. */
3848 {
3850 {
3856 }
3858 }
3861 {
3863 {
3869 }
3871 }
3875 }
3881 {
3882 rtx address;
3883 rtx temp;
3892 /* See whether an induction variable is interesting to us and if
3893 not, report the reason. */
3897 /* We are interested only in constant stride memory references
3898 in order to be able to compute density easily. */
3902 else
3903 {
3906 {
3909 }
3911 /* On some targets, reversed order prefetches are not
3912 worthwhile. */
3916 /* Prefetch of accesses with an extreme stride might not be
3917 worthwhile, either. */
3922 /* Ignore GIVs with varying add values; we can't predict the
3923 value for the next iteration. */
3927 /* Ignore GIVs in the nested loops; they ought to have been
3928 handled already. */
3931 }
3934 {
3940 }
3942 /* Determine the pointer to the basic array we are examining. It is
3943 the sum of the BIV's initial value and the GIV's add_val. */
3953 /* When the GIV is not always executed, we might be better off by
3954 not dirtying the cache pages. */
3957 else
3958 {
3963 }
3965 /* Attempt to find another prefetch to the same array and see if we
3966 can merge this one. */
3970 {
3971 /* In case both access same array (same location
3972 just with small difference in constant indexes), merge
3973 the prefetches. Just do the later and the earlier will
3974 get prefetched from previous iteration.
3975 The artificial threshold should not be too small,
3976 but also not bigger than small portion of memory usually
3977 traversed by single loop. */
3980 {
3989 }
3993 {
3998 }
3999 }
4001 /* Merging failed. */
4003 {
4011 num_prefetches++;
4013 {
4018 }
4019 }
4020 }
4021 }
4024 {
4027 /* Attempt to calculate the total number of bytes fetched by all
4028 iterations of the loop. Avoid overflow. */
4033 else
4038 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4043 {
4048 }
4049 else
4050 {
4056 }
4057 else
4060 /* Find how many prefetch instructions we'll use within the loop. */
4062 {
4068 }
4069 }
4071 /* Determine how many iterations ahead to prefetch within the loop, based
4072 on how many prefetches we currently expect to do within the loop. */
4074 {
4076 {
4082 }
4083 }
4084 /* We'll also use AHEAD to determine how many prefetch instructions to
4085 emit before a loop, so don't leave it zero. */
4090 {
4091 /* Update if we've decided not to prefetch anything within the loop. */
4095 /* Find how many prefetch instructions we'll use before the loop. */
4097 {
4105 }
4108 {
4128 }
4129 }
4132 {
4133 /* Record that this loop uses prefetch instructions. */
4137 {
4142 }
4143 }
4146 {
4150 {
4152 rtx insn;
4156 rtx seq;
4158 /* We can save some effort by offsetting the address on
4159 architectures with offsettable memory references. */
4162 else
4163 {
4169 }
4172 /* Make sure the address operand is valid for prefetch. */
4182 /* Check all insns emitted and record the new GIV
4183 information. */
4186 {
4191 }
4192 }
4195 {
4196 /* Emit insns before the loop to fetch the first cache lines or,
4197 if we're not prefetching within the loop, everything we expect
4198 to need. */
4200 {
4208 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4209 non-constant INIT_VAL to have the same mode as REG, which
4210 in this case we know to be Pmode. */
4212 {
4213 rtx seq;
4220 }
4226 loop_start);
4227 }
4228 }
4229 }
4232 }
4233 \f
4234 /* Communication with routines called via `note_stores'. */
4238 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4242 /* ??? Unfinished optimizations, and possible future optimizations,
4243 for the strength reduction code. */
4245 /* ??? The interaction of biv elimination, and recognition of 'constant'
4246 bivs, may cause problems. */
4248 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4249 performance problems.
4251 Perhaps don't eliminate things that can be combined with an addressing
4252 mode. Find all givs that have the same biv, mult_val, and add_val;
4253 then for each giv, check to see if its only use dies in a following
4254 memory address. If so, generate a new memory address and check to see
4255 if it is valid. If it is valid, then store the modified memory address,
4256 otherwise, mark the giv as not done so that it will get its own iv. */
4258 /* ??? Could try to optimize branches when it is known that a biv is always
4259 positive. */
4261 /* ??? When replace a biv in a compare insn, we should replace with closest
4262 giv so that an optimized branch can still be recognized by the combiner,
4263 e.g. the VAX acb insn. */
4265 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4266 was rerun in loop_optimize whenever a register was added or moved.
4267 Also, some of the optimizations could be a little less conservative. */
4268 \f
4269 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4270 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4271 callback.
4273 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4274 least once for every loop iteration except for the last one.
4276 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4277 loop iteration.
4278 */
4279 void
4281 {
4286 rtx p;
4288 /* If loop_scan_start points to the loop exit test, we have to be wary of
4289 subversive use of gotos inside expression statements. */
4293 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4297 {
4300 /* Past CODE_LABEL, we get to insns that may be executed multiple
4301 times. The only way we can be sure that they can't is if every
4302 jump insn between here and the end of the loop either
4303 returns, exits the loop, is a jump to a location that is still
4304 behind the label, or is a jump to the loop start. */
4307 {
4313 {
4318 {
4321 else
4325 }
4333 {
4336 }
4337 }
4338 }
4340 /* Past a jump, we get to insns for which we can't count
4341 on whether they will be executed during each iteration. */
4342 /* This code appears twice in strength_reduce. There is also similar
4343 code in scan_loop. */
4345 /* If we enter the loop in the middle, and scan around to the
4346 beginning, don't set not_every_iteration for that.
4347 This can be any kind of jump, since we want to know if insns
4348 will be executed if the loop is executed. */
4353 {
4356 /* If this is a jump outside the loop, then it also doesn't
4357 matter. Check to see if the target of this branch is on the
4358 loop->exits_labels list. */
4366 }
4369 {
4370 /* At the virtual top of a converted loop, insns are again known to
4371 be executed each iteration: logically, the loop begins here
4372 even though the exit code has been duplicated.
4374 Insns are also again known to be executed each iteration at
4375 the LOOP_CONT note. */
4381 loop_depth++;
4383 loop_depth--;
4384 }
4386 /* Note if we pass a loop latch. If we do, then we can not clear
4387 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4388 a loop since a jump before the last CODE_LABEL may have started
4389 a new loop iteration.
4391 Note that LOOP_TOP is only set for rotated loops and we need
4392 this check for all loops, so compare against the CODE_LABEL
4393 which immediately follows LOOP_START. */
4398 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4399 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4400 or not an insn is known to be executed each iteration of the
4401 loop, whether or not any iterations are known to occur.
4403 Therefore, if we have just passed a label and have no more labels
4404 between here and the test insn of the loop, and we have not passed
4405 a jump to the top of the loop, then we know these insns will be
4406 executed each iteration. */
4409 && !past_loop_latch
4414 }
4415 }
4416 \f
4417 static void
4419 {
4422 /* Temporary list pointers for traversing ivs->list. */
4429 /* Scan ivs->list to remove all regs that proved not to be bivs.
4430 Make a sanity check against regs->n_times_set. */
4432 {
4434 /* Above happens if register modified by subreg, etc. */
4435 /* Make sure it is not recognized as a basic induction var: */
4437 /* If never incremented, it is invariant that we decided not to
4438 move. So leave it alone. */
4440 {
4451 }
4452 else
4453 {
4458 }
4459 }
4460 }
4463 /* Determine how BIVS are initialized by looking through pre-header
4464 extended basic block. */
4465 static void
4467 {
4469 /* Temporary list pointers for traversing ivs->list. */
4472 rtx p;
4474 /* Find initial value for each biv by searching backwards from loop_start,
4475 halting at first label. Also record any test condition. */
4479 {
4480 rtx test;
4490 /* Record any test of a biv that branches around the loop if no store
4491 between it and the start of loop. We only care about tests with
4492 constants and registers and only certain of those. */
4502 {
4503 /* If an NE test, we have an initial value! */
4505 {
4509 }
4510 else
4512 }
4513 }
4514 }
4517 /* Look at the each biv and see if we can say anything better about its
4518 initial value from any initializing insns set up above. (This is done
4519 in two passes to avoid missing SETs in a PARALLEL.) */
4520 static void
4522 {
4524 /* Temporary list pointers for traversing ivs->list. */
4529 {
4530 rtx src;
4531 rtx note;
4536 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4537 is a constant, use the value of that. */
4543 else
4556 {
4560 {
4563 }
4564 }
4565 /* If we can't make it a giv,
4566 let biv keep initial value of "itself". */
4569 }
4570 }
4573 /* Search the loop for general induction variables. */
4575 static void
4577 {
4579 }
4582 /* For each giv for which we still don't know whether or not it is
4583 replaceable, check to see if it is replaceable because its final value
4584 can be calculated. */
4586 static void
4588 {
4593 {
4599 }
4600 }
4603 /* Return nonzero if it is possible to eliminate the biv BL provided
4604 all givs are reduced. This is possible if either the reg is not
4605 used outside the loop, or we can compute what its final value will
4606 be. */
4608 static int
4611 {
4612 /* For architectures with a decrement_and_branch_until_zero insn,
4613 don't do this if we put a REG_NONNEG note on the endtest for this
4614 biv. */
4616 #ifdef HAVE_decrement_and_branch_until_zero
4618 {
4623 }
4624 #endif
4626 /* Check that biv is used outside loop or if it has a final value.
4627 Compare against bl->init_insn rather than loop->start. We aren't
4628 concerned with any uses of the biv between init_insn and
4629 loop->start since these won't be affected by the value of the biv
4630 elsewhere in the function, so long as init_insn doesn't use the
4631 biv itself. */
4642 {
4650 }
4652 }
4655 /* Reduce each giv of BL that we have decided to reduce. */
4657 static void
4659 {
4663 {
4666 {
4669 /* If the code for derived givs immediately below has already
4670 allocated a new_reg, we must keep it. */
4674 #ifdef AUTO_INC_DEC
4675 /* If the target has auto-increment addressing modes, and
4676 this is an address giv, then try to put the increment
4677 immediately after its use, so that flow can create an
4678 auto-increment addressing mode. */
4681 /* We don't handle reversed biv's because bl->biv->insn
4682 does not have a valid INSN_LUID. */
4686 {
4687 /* If other giv's have been combined with this one, then
4688 this will work only if all uses of the other giv's occur
4689 before this giv's insn. This is difficult to check.
4691 We simplify this by looking for the common case where
4692 there is one DEST_REG giv, and this giv's insn is the
4693 last use of the dest_reg of that DEST_REG giv. If the
4694 increment occurs after the address giv, then we can
4695 perform the optimization. (Otherwise, the increment
4696 would have to go before other_giv, and we would not be
4697 able to combine it with the address giv to get an
4698 auto-inc address.) */
4700 {
4705 {
4708 else
4710 }
4717 }
4718 /* Check for case where increment is before the address
4719 giv. Do this test in "loop order". */
4728 else
4731 #ifdef HAVE_cc0
4732 {
4733 rtx prev;
4735 /* We can't put an insn immediately after one setting
4736 cc0, or immediately before one using cc0. */
4743 }
4744 #endif
4748 }
4749 #endif
4751 /* For each place where the biv is incremented, add an insn
4752 to increment the new, reduced reg for the giv. */
4754 {
4755 rtx insert_before;
4757 /* Skip if location is the same as a previous one. */
4764 else
4772 /* A multiply is acceptable here
4773 since this is presumed to be seldom executed. */
4777 }
4779 /* Add code at loop start to initialize giv's reduced reg. */
4784 }
4785 }
4786 }
4789 /* Check for givs whose first use is their definition and whose
4790 last use is the definition of another giv. If so, it is likely
4791 dead and should not be used to derive another giv nor to
4792 eliminate a biv. */
4794 static void
4796 {
4800 {
4807 {
4813 }
4814 }
4815 }
4818 static void
4820 {
4824 {
4831 /* Update expression if this was combined, in case other giv was
4832 replaced. */
4837 /* See if this register is known to be a pointer to something. If
4838 so, see if we can find the alignment. First see if there is a
4839 destination register that is a pointer. If so, this shares the
4840 alignment too. Next see if we can deduce anything from the
4841 computational information. If not, and this is a DEST_ADDR
4842 giv, at least we know that it's a pointer, though we don't know
4843 the alignment. */
4851 {
4860 }
4864 {
4872 }
4877 /* Store reduced reg as the address in the memref where we found
4878 this giv. */
4881 {
4883 }
4884 else
4885 {
4887 rtx note;
4889 /* Not replaceable; emit an insn to set the original giv reg from
4890 the reduced giv, same as above. */
4895 /* The original insn may have a REG_EQUAL note. This note is
4896 now incorrect and may result in invalid substitutions later.
4897 The original insn is dead, but may be part of a libcall
4898 sequence, which doesn't seem worth the bother of handling. */
4902 }
4904 /* When a loop is reversed, givs which depend on the reversed
4905 biv, and which are live outside the loop, must be set to their
4906 correct final value. This insn is only needed if the giv is
4907 not replaceable. The correct final value is the same as the
4908 value that the giv starts the reversed loop with. */
4919 {
4924 }
4925 }
4926 }
4929 static int
4932 rtx test_reg)
4933 {
4942 /* Reduce benefit if not replaceable, since we will insert a
4943 move-insn to replace the insn that calculates this giv. Don't do
4944 this unless the giv is a user variable, since it will often be
4945 marked non-replaceable because of the duplication of the exit
4946 code outside the loop. In such a case, the copies we insert are
4947 dead and will be deleted. So they don't have a cost. Similar
4948 situations exist. */
4949 /* ??? The new final_[bg]iv_value code does a much better job of
4950 finding replaceable giv's, and hence this code may no longer be
4951 necessary. */
4956 /* Decrease the benefit to count the add-insns that we will insert
4957 to increment the reduced reg for the giv. ??? This can
4958 overestimate the run-time cost of the additional insns, e.g. if
4959 there are multiple basic blocks that increment the biv, but only
4960 one of these blocks is executed during each iteration. There is
4961 no good way to detect cases like this with the current structure
4962 of the loop optimizer. This code is more accurate for
4963 determining code size than run-time benefits. */
4966 /* Decide whether to strength-reduce this giv or to leave the code
4967 unchanged (recompute it from the biv each time it is used). This
4968 decision can be made independently for each giv. */
4970 #ifdef AUTO_INC_DEC
4971 /* Attempt to guess whether autoincrement will handle some of the
4972 new add insns; if so, increase BENEFIT (undo the subtraction of
4973 add_cost that was done above). */
4975 /* Increasing the benefit is risky, since this is only a guess.
4976 Avoid increasing register pressure in cases where there would
4977 be no other benefit from reducing this giv. */
4980 {
4995 }
4996 #endif
4999 }
5002 /* Free IV structures for LOOP. */
5004 static void
5006 {
5013 {
5019 {
5022 }
5024 {
5027 }
5031 }
5032 }
5035 /* Perform strength reduction and induction variable elimination.
5037 Pseudo registers created during this function will be beyond the
5038 last valid index in several tables including
5039 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5040 problem here, because the added registers cannot be givs outside of
5041 their loop, and hence will never be reconsidered. But scan_loop
5042 must check regnos to make sure they are in bounds. */
5044 static void
5046 {
5050 rtx p;
5051 /* Temporary list pointer for traversing ivs->list. */
5053 /* Ratio of extra register life span we can justify
5054 for saving an instruction. More if loop doesn't call subroutines
5055 since in that case saving an insn makes more difference
5056 and more registers are available. */
5057 /* ??? could set this to last value of threshold in move_movables */
5059 /* Map of pseudo-register replacements. */
5071 /* Find all BIVs in loop. */
5074 /* Exit if there are no bivs. */
5076 {
5077 /* Can still unroll the loop anyways, but indicate that there is no
5078 strength reduction info available. */
5084 }
5086 /* Determine how BIVS are initialized by looking through pre-header
5087 extended basic block. */
5090 /* Look at the each biv and see if we can say anything better about its
5091 initial value from any initializing insns set up above. */
5094 /* Search the loop for general induction variables. */
5097 /* Try to calculate and save the number of loop iterations. This is
5098 set to zero if the actual number can not be calculated. This must
5099 be called after all giv's have been identified, since otherwise it may
5100 fail if the iteration variable is a giv. */
5103 #ifdef HAVE_prefetch
5106 #endif
5108 /* Now for each giv for which we still don't know whether or not it is
5109 replaceable, check to see if it is replaceable because its final value
5110 can be calculated. This must be done after loop_iterations is called,
5111 so that final_giv_value will work correctly. */
5114 /* Try to prove that the loop counter variable (if any) is always
5115 nonnegative; if so, record that fact with a REG_NONNEG note
5116 so that "decrement and branch until zero" insn can be used. */
5119 /* Create reg_map to hold substitutions for replaceable giv regs.
5120 Some givs might have been made from biv increments, so look at
5121 ivs->reg_iv_type for a suitable size. */
5125 /* Examine each iv class for feasibility of strength reduction/induction
5126 variable elimination. */
5129 {
5133 /* Test whether it will be possible to eliminate this biv
5134 provided all givs are reduced. */
5137 /* This will be true at the end, if all givs which depend on this
5138 biv have been strength reduced.
5139 We can't (currently) eliminate the biv unless this is so. */
5142 /* Check each extension dependent giv in this class to see if its
5143 root biv is safe from wrapping in the interior mode. */
5146 /* Combine all giv's for this iv_class. */
5150 {
5158 /* If an insn is not to be strength reduced, then set its ignore
5159 flag, and clear bl->all_reduced. */
5161 /* A giv that depends on a reversed biv must be reduced if it is
5162 used after the loop exit, otherwise, it would have the wrong
5163 value after the loop exit. To make it simple, just reduce all
5164 of such giv's whether or not we know they are used after the loop
5165 exit. */
5170 {
5178 }
5179 else
5180 {
5181 /* Check that we can increment the reduced giv without a
5182 multiply insn. If not, reject it. */
5187 {
5195 }
5196 }
5197 }
5199 /* Check for givs whose first use is their definition and whose
5200 last use is the definition of another giv. If so, it is likely
5201 dead and should not be used to derive another giv nor to
5202 eliminate a biv. */
5205 /* Reduce each giv that we decided to reduce. */
5208 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5209 as not reduced.
5211 For each giv register that can be reduced now: if replaceable,
5212 substitute reduced reg wherever the old giv occurs;
5213 else add new move insn "giv_reg = reduced_reg". */
5216 /* All the givs based on the biv bl have been reduced if they
5217 merit it. */
5219 /* For each giv not marked as maybe dead that has been combined with a
5220 second giv, clear any "maybe dead" mark on that second giv.
5221 v->new_reg will either be or refer to the register of the giv it
5222 combined with.
5224 Doing this clearing avoids problems in biv elimination where
5225 a giv's new_reg is a complex value that can't be put in the
5226 insn but the giv combined with (with a reg as new_reg) is
5227 marked maybe_dead. Since the register will be used in either
5228 case, we'd prefer it be used from the simpler giv. */
5234 /* Try to eliminate the biv, if it is a candidate.
5235 This won't work if ! bl->all_reduced,
5236 since the givs we planned to use might not have been reduced.
5238 We have to be careful that we didn't initially think we could
5239 eliminate this biv because of a giv that we now think may be
5240 dead and shouldn't be used as a biv replacement.
5242 Also, there is the possibility that we may have a giv that looks
5243 like it can be used to eliminate a biv, but the resulting insn
5244 isn't valid. This can happen, for example, on the 88k, where a
5245 JUMP_INSN can compare a register only with zero. Attempts to
5246 replace it with a compare with a constant will fail.
5248 Note that in cases where this call fails, we may have replaced some
5249 of the occurrences of the biv with a giv, but no harm was done in
5250 doing so in the rare cases where it can occur. */
5254 {
5255 /* ?? If we created a new test to bypass the loop entirely,
5256 or otherwise drop straight in, based on this test, then
5257 we might want to rewrite it also. This way some later
5258 pass has more hope of removing the initialization of this
5259 biv entirely. */
5261 /* If final_value != 0, then the biv may be used after loop end
5262 and we must emit an insn to set it just in case.
5264 Reversed bivs already have an insn after the loop setting their
5265 value, so we don't need another one. We can't calculate the
5266 proper final value for such a biv here anyways. */
5275 }
5276 /* See above note wrt final_value. But since we couldn't eliminate
5277 the biv, we must set the value after the loop instead of before. */
5281 }
5283 /* Go through all the instructions in the loop, making all the
5284 register substitutions scheduled in REG_MAP. */
5289 {
5293 }
5296 {
5297 /* When we completely unroll a loop we will likely not need the increment
5298 of the loop BIV and we will not need the conditional branch at the
5299 end of the loop. */
5302 #ifdef HAVE_cc0
5303 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5304 need the comparison before the conditional branch at the end of the
5305 loop. */
5307 #endif
5309 /* We'll need one copy for each loop iteration. */
5312 /* A little slop to account for the ability to remove initialization
5313 code, better CSE, and other secondary benefits of completely
5314 unrolling some loops. */
5317 /* Clamp the value. */
5320 }
5322 /* Unroll loops from within strength reduction so that we can use the
5323 induction variable information that strength_reduce has already
5324 collected. Always unroll loops that would be as small or smaller
5325 unrolled than when rolled. */
5332 #ifdef HAVE_doloop_end
5337 /* In case number of iterations is known, drop branch prediction note
5338 in the branch. Do that only in second loop pass, as loop unrolling
5339 may change the number of iterations performed. */
5341 {
5342 unsigned HOST_WIDE_INT n
5347 }
5355 }
5356 \f
5357 /*Record all basic induction variables calculated in the insn. */
5358 static rtx
5361 {
5363 rtx set;
5364 rtx dest_reg;
5365 rtx inc_val;
5366 rtx mult_val;
5372 {
5377 {
5382 {
5383 /* It is a possible basic induction variable.
5384 Create and initialize an induction structure for it. */
5391 }
5394 }
5395 }
5397 }
5398 \f
5399 /* Record all givs calculated in the insn.
5400 A register is a giv if: it is only set once, it is a function of a
5401 biv and a constant (or invariant), and it is not a biv. */
5402 static rtx
5405 {
5408 rtx set;
5409 /* Look for a general induction variable in a register. */
5414 {
5415 rtx src_reg;
5416 rtx dest_reg;
5417 rtx add_val;
5418 rtx mult_val;
5419 rtx ext_val;
5422 rtx last_consec_insn;
5431 /* Equivalent expression is a giv. */
5436 /* Don't try to handle any regs made by loop optimization.
5437 We have nothing on them in regno_first_uid, etc. */
5439 /* Don't recognize a BASIC_INDUCT_VAR here. */
5441 /* This must be the only place where the register is set. */
5443 /* or all sets must be consecutive and make a giv. */
5448 {
5451 /* If this is a library call, increase benefit. */
5455 /* Skip the consecutive insns, if there are any. */
5463 }
5464 }
5466 /* Look for givs which are memory addresses. */
5469 maybe_multiple);
5471 /* Update the status of whether giv can derive other givs. This can
5472 change when we pass a label or an insn that updates a biv. */
5477 }
5478 \f
5479 /* Return 1 if X is a valid source for an initial value (or as value being
5480 compared against in an initial test).
5482 X must be either a register or constant and must not be clobbered between
5483 the current insn and the start of the loop.
5485 INSN is the insn containing X. */
5487 static int
5489 {
5493 /* Only consider pseudos we know about initialized in insns whose luids
5494 we know. */
5499 /* Don't use call-clobbered registers across a call which clobbers it. On
5500 some machines, don't use any hard registers at all. */
5502 && (SMALL_REGISTER_CLASSES
5506 /* Don't use registers that have been clobbered before the start of the
5507 loop. */
5512 }
5513 \f
5514 /* Scan X for memory refs and check each memory address
5515 as a possible giv. INSN is the insn whose pattern X comes from.
5516 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5517 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5518 more than once in each loop iteration. */
5520 static void
5523 {
5533 {
5549 {
5550 rtx src_reg;
5551 rtx add_val;
5552 rtx mult_val;
5553 rtx ext_val;
5556 /* This code used to disable creating GIVs with mult_val == 1 and
5557 add_val == 0. However, this leads to lost optimizations when
5558 it comes time to combine a set of related DEST_ADDR GIVs, since
5559 this one would not be seen. */
5564 {
5565 /* Found one; record it. */
5573 }
5574 }
5579 }
5581 /* Recursively scan the subexpressions for other mem refs. */
5587 maybe_multiple);
5591 maybe_multiple);
5592 }
5593 \f
5594 /* Fill in the data about one biv update.
5595 V is the `struct induction' in which we record the biv. (It is
5596 allocated by the caller, with alloca.)
5597 INSN is the insn that sets it.
5598 DEST_REG is the biv's reg.
5600 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5601 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5602 being set to INC_VAL.
5604 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5605 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5606 can be executed more than once per iteration. If MAYBE_MULTIPLE
5607 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5608 executed exactly once per iteration. */
5610 static void
5614 {
5631 /* Add this to the reg's iv_class, creating a class
5632 if this is the first incrementation of the reg. */
5636 {
5637 /* Create and initialize new iv_class. */
5647 /* Set initial value to the reg itself. */
5650 /* We haven't seen the initializing insn yet */
5660 /* Add this class to ivs->list. */
5664 /* Put it in the array of biv register classes. */
5666 }
5667 else
5668 {
5669 /* Check if location is the same as a previous one. */
5673 {
5676 }
5677 }
5679 /* Update IV_CLASS entry for this biv. */
5688 }
5689 \f
5690 /* Fill in the data about one giv.
5691 V is the `struct induction' in which we record the giv. (It is
5692 allocated by the caller, with alloca.)
5693 INSN is the insn that sets it.
5694 BENEFIT estimates the savings from deleting this insn.
5695 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5696 into a register or is used as a memory address.
5698 SRC_REG is the biv reg which the giv is computed from.
5699 DEST_REG is the giv's reg (if the giv is stored in a reg).
5700 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5701 LOCATION points to the place where this giv's value appears in INSN. */
5703 static void
5708 {
5713 rtx temp;
5715 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5716 undo the MULT canonicalization that we performed earlier. */
5746 /* The v->always_computable field is used in update_giv_derive, to
5747 determine whether a giv can be used to derive another giv. For a
5748 DEST_REG giv, INSN computes a new value for the giv, so its value
5749 isn't computable if INSN insn't executed every iteration.
5750 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5751 it does not compute a new value. Hence the value is always computable
5752 regardless of whether INSN is executed each iteration. */
5756 else
5762 {
5765 }
5767 {
5772 /* If the lifetime is zero, it means that this register is
5773 really a dead store. So mark this as a giv that can be
5774 ignored. This will not prevent the biv from being eliminated. */
5780 }
5782 /* Add the giv to the class of givs computed from one biv. */
5786 {
5789 /* Don't count DEST_ADDR. This is supposed to count the number of
5790 insns that calculate givs. */
5794 }
5795 else
5796 /* Fatal error, biv missing for this giv? */
5800 {
5803 }
5804 else
5805 {
5806 /* The giv can be replaced outright by the reduced register only if all
5807 of the following conditions are true:
5808 - the insn that sets the giv is always executed on any iteration
5809 on which the giv is used at all
5810 (there are two ways to deduce this:
5811 either the insn is executed on every iteration,
5812 or all uses follow that insn in the same basic block),
5813 - the giv is not used outside the loop
5814 - no assignments to the biv occur during the giv's lifetime. */
5817 /* Previous line always fails if INSN was moved by loop opt. */
5820 && (! not_every_iteration
5822 {
5823 /* Now check that there are no assignments to the biv within the
5824 giv's lifetime. This requires two separate checks. */
5826 /* Check each biv update, and fail if any are between the first
5827 and last use of the giv.
5829 If this loop contains an inner loop that was unrolled, then
5830 the insn modifying the biv may have been emitted by the loop
5831 unrolling code, and hence does not have a valid luid. Just
5832 mark the biv as not replaceable in this case. It is not very
5833 useful as a biv, because it is used in two different loops.
5834 It is very unlikely that we would be able to optimize the giv
5835 using this biv anyways. */
5840 {
5846 {
5850 }
5851 }
5853 /* If there are any backwards branches that go from after the
5854 biv update to before it, then this giv is not replaceable. */
5858 {
5862 }
5863 }
5864 else
5865 {
5866 /* May still be replaceable, we don't have enough info here to
5867 decide. */
5870 }
5871 }
5873 /* Record whether the add_val contains a const_int, for later use by
5874 combine_givs. */
5875 {
5880 ;
5884 {
5886 {
5891 else
5893 }
5896 }
5897 }
5901 }
5903 /* All this does is determine whether a giv can be made replaceable because
5904 its final value can be calculated. This code can not be part of record_giv
5905 above, because final_giv_value requires that the number of loop iterations
5906 be known, and that can not be accurately calculated until after all givs
5907 have been identified. */
5909 static void
5911 {
5914 /* DEST_ADDR givs will never reach here, because they are always marked
5915 replaceable above in record_giv. */
5917 /* The giv can be replaced outright by the reduced register only if all
5918 of the following conditions are true:
5919 - the insn that sets the giv is always executed on any iteration
5920 on which the giv is used at all
5921 (there are two ways to deduce this:
5922 either the insn is executed on every iteration,
5923 or all uses follow that insn in the same basic block),
5924 - its final value can be calculated (this condition is different
5925 than the one above in record_giv)
5926 - it's not used before the it's set
5927 - no assignments to the biv occur during the giv's lifetime. */
5929 #if 0
5930 /* This is only called now when replaceable is known to be false. */
5931 /* Clear replaceable, so that it won't confuse final_giv_value. */
5933 #endif
5938 {
5941 rtx last_giv_use;
5946 /* When trying to determine whether or not a biv increment occurs
5947 during the lifetime of the giv, we can ignore uses of the variable
5948 outside the loop because final_value is true. Hence we can not
5949 use regno_last_uid and regno_first_uid as above in record_giv. */
5951 /* Search the loop to determine whether any assignments to the
5952 biv occur during the giv's lifetime. Start with the insn
5953 that sets the giv, and search around the loop until we come
5954 back to that insn again.
5956 Also fail if there is a jump within the giv's lifetime that jumps
5957 to somewhere outside the lifetime but still within the loop. This
5958 catches spaghetti code where the execution order is not linear, and
5959 hence the above test fails. Here we assume that the giv lifetime
5960 does not extend from one iteration of the loop to the next, so as
5961 to make the test easier. Since the lifetime isn't known yet,
5962 this requires two loops. See also record_giv above. */
5967 {
5970 {
5973 }
5979 {
5980 /* It is possible for the BIV increment to use the GIV if we
5981 have a cycle. Thus we must be sure to check each insn for
5982 both BIV and GIV uses, and we must check for BIV uses
5983 first. */
5990 {
5992 {
5996 }
5998 }
5999 }
6000 }
6002 /* Now that the lifetime of the giv is known, check for branches
6003 from within the lifetime to outside the lifetime if it is still
6004 replaceable. */
6007 {
6010 {
6023 {
6032 }
6033 }
6034 }
6036 /* If it is replaceable, then save the final value. */
6039 }
6044 }
6045 \f
6046 /* Update the status of whether a giv can derive other givs.
6048 We need to do something special if there is or may be an update to the biv
6049 between the time the giv is defined and the time it is used to derive
6050 another giv.
6052 In addition, a giv that is only conditionally set is not allowed to
6053 derive another giv once a label has been passed.
6055 The cases we look at are when a label or an update to a biv is passed. */
6057 static void
6059 {
6063 rtx tem;
6066 /* Search all IV classes, then all bivs, and finally all givs.
6068 There are three cases we are concerned with. First we have the situation
6069 of a giv that is only updated conditionally. In that case, it may not
6070 derive any givs after a label is passed.
6072 The second case is when a biv update occurs, or may occur, after the
6073 definition of a giv. For certain biv updates (see below) that are
6074 known to occur between the giv definition and use, we can adjust the
6075 giv definition. For others, or when the biv update is conditional,
6076 we must prevent the giv from deriving any other givs. There are two
6077 sub-cases within this case.
6079 If this is a label, we are concerned with any biv update that is done
6080 conditionally, since it may be done after the giv is defined followed by
6081 a branch here (actually, we need to pass both a jump and a label, but
6082 this extra tracking doesn't seem worth it).
6084 If this is a jump, we are concerned about any biv update that may be
6085 executed multiple times. We are actually only concerned about
6086 backward jumps, but it is probably not worth performing the test
6087 on the jump again here.
6089 If this is a biv update, we must adjust the giv status to show that a
6090 subsequent biv update was performed. If this adjustment cannot be done,
6091 the giv cannot derive further givs. */
6097 {
6099 {
6100 /* If cant_derive is already true, there is no point in
6101 checking all of these conditions again. */
6105 /* If this giv is conditionally set and we have passed a label,
6106 it cannot derive anything. */
6110 /* Skip givs that have mult_val == 0, since
6111 they are really invariants. Also skip those that are
6112 replaceable, since we know their lifetime doesn't contain
6113 any biv update. */
6117 /* The only way we can allow this giv to derive another
6118 is if this is a biv increment and we can form the product
6119 of biv->add_val and giv->mult_val. In this case, we will
6120 be able to compute a compensation. */
6122 {
6123 rtx ext_val_dummy;
6134 tem = simplify_giv_expr
6141 else
6143 }
6147 }
6148 }
6149 }
6150 \f
6151 /* Check whether an insn is an increment legitimate for a basic induction var.
6152 X is the source of insn P, or a part of it.
6153 MODE is the mode in which X should be interpreted.
6155 DEST_REG is the putative biv, also the destination of the insn.
6156 We accept patterns of these forms:
6157 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6158 REG = INVARIANT + REG
6160 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6161 store the additive term into *INC_VAL, and store the place where
6162 we found the additive term into *LOCATION.
6164 If X is an assignment of an invariant into DEST_REG, we set
6165 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6167 We also want to detect a BIV when it corresponds to a variable
6168 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6169 of the variable may be a PLUS that adds a SUBREG of that variable to
6170 an invariant and then sign- or zero-extends the result of the PLUS
6171 into the variable.
6173 Most GIVs in such cases will be in the promoted mode, since that is the
6174 probably the natural computation mode (and almost certainly the mode
6175 used for addresses) on the machine. So we view the pseudo-reg containing
6176 the variable as the BIV, as if it were simply incremented.
6178 Note that treating the entire pseudo as a BIV will result in making
6179 simple increments to any GIVs based on it. However, if the variable
6180 overflows in its declared mode but not its promoted mode, the result will
6181 be incorrect. This is acceptable if the variable is signed, since
6182 overflows in such cases are undefined, but not if it is unsigned, since
6183 those overflows are defined. So we only check for SIGN_EXTEND and
6184 not ZERO_EXTEND.
6186 If we cannot find a biv, we return 0. */
6188 static int
6192 {
6200 {
6206 {
6208 }
6213 {
6215 }
6216 else
6223 /* convert_modes can emit new instructions, e.g. when arg is a loop
6224 invariant MEM and dest_reg has a different mode.
6225 These instructions would be emitted after the end of the function
6226 and then *inc_val would be an uninitialized pseudo.
6227 Detect this and bail in this case.
6228 Other alternatives to solve this can be introducing a convert_modes
6229 variant which is allowed to fail but not allowed to emit new
6230 instructions, emit these instructions before loop start and let
6231 it be garbage collected if *inc_val is never used or saving the
6232 *inc_val initialization sequence generated here and when *inc_val
6233 is going to be actually used, emit it at some suitable place. */
6237 {
6240 }
6248 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6249 handle addition of promoted variables.
6250 ??? The comment at the start of this function is wrong: promoted
6251 variable increments don't look like it says they do. */
6257 /* If this register is assigned in a previous insn, look at its
6258 source, but don't go outside the loop or past a label. */
6260 /* If this sets a register to itself, we would repeat any previous
6261 biv increment if we applied this strategy blindly. */
6267 {
6268 rtx dest;
6269 do
6270 {
6272 }
6301 }
6302 /* Fall through. */
6304 /* Can accept constant setting of biv only when inside inner most loop.
6305 Otherwise, a biv of an inner loop may be incorrectly recognized
6306 as a biv of the outer loop,
6307 causing code to be moved INTO the inner loop. */
6314 /* convert_modes aborts if we try to convert to or from CCmode, so just
6315 exclude that case. It is very unlikely that a condition code value
6316 would be a useful iterator anyways. convert_modes aborts if we try to
6317 convert a float mode to non-float or vice versa too. */
6321 {
6322 /* Possible bug here? Perhaps we don't know the mode of X. */
6326 {
6329 }
6334 }
6335 else
6339 /* Ignore this BIV if signed arithmetic overflow is defined. */
6346 /* Similar, since this can be a sign extension. */
6351 ;
6365 location);
6370 }
6371 }
6372 \f
6373 /* A general induction variable (giv) is any quantity that is a linear
6374 function of a basic induction variable,
6375 i.e. giv = biv * mult_val + add_val.
6376 The coefficients can be any loop invariant quantity.
6377 A giv need not be computed directly from the biv;
6378 it can be computed by way of other givs. */
6380 /* Determine whether X computes a giv.
6381 If it does, return a nonzero value
6382 which is the benefit from eliminating the computation of X;
6383 set *SRC_REG to the register of the biv that it is computed from;
6384 set *ADD_VAL and *MULT_VAL to the coefficients,
6385 such that the value of X is biv * mult + add; */
6387 static int
6392 {
6396 /* If this is an invariant, forget it, it isn't a giv. */
6407 {
6410 /* Since this is now an invariant and wasn't before, it must be a giv
6411 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6412 with. */
6419 /* This is equivalent to a BIV. */
6426 /* Either (plus (biv) (invar)) or
6427 (plus (mult (biv) (invar_1)) (invar_2)). */
6429 {
6432 }
6433 else
6434 {
6437 }
6442 /* ADD_VAL is zero. */
6450 }
6452 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6453 unless they are CONST_INT). */
6461 else
6464 /* Always return true if this is a giv so it will be detected as such,
6465 even if the benefit is zero or negative. This allows elimination
6466 of bivs that might otherwise not be eliminated. */
6468 }
6469 \f
6470 /* Given an expression, X, try to form it as a linear function of a biv.
6471 We will canonicalize it to be of the form
6472 (plus (mult (BIV) (invar_1))
6473 (invar_2))
6474 with possible degeneracies.
6476 The invariant expressions must each be of a form that can be used as a
6477 machine operand. We surround then with a USE rtx (a hack, but localized
6478 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6479 routine; it is the caller's responsibility to strip them.
6481 If no such canonicalization is possible (i.e., two biv's are used or an
6482 expression that is neither invariant nor a biv or giv), this routine
6483 returns 0.
6485 For a nonzero return, the result will have a code of CONST_INT, USE,
6486 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6488 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6493 static rtx
6495 {
6500 rtx tem;
6502 /* If this is not an integer mode, or if we cannot do arithmetic in this
6503 mode, this can't be a giv. */
6510 {
6517 /* Put constant last, CONST_INT last if both constant. */
6525 /* Handle addition of zero, then addition of an invariant. */
6530 {
6533 /* Adding two invariants must result in an invariant, so enclose
6534 addition operation inside a USE and return it. */
6544 else
6553 /* biv + invar or mult + invar. Return sum. */
6557 /* (a + invar_1) + invar_2. Associate. */
6558 return
6564 arg1)),
6569 }
6571 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6572 MULT to reduce cases. */
6578 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6579 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6580 Recurse to associate the second PLUS. */
6585 return
6593 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6609 /* Handle "a - b" as "a + b * (-1)". */
6615 constm1_rtx)),
6624 /* Put constant last, CONST_INT last if both constant. */
6629 /* If second argument is not now constant, not giv. */
6633 /* Handle multiply by 0 or 1. */
6641 {
6643 /* biv * invar. Done. */
6647 /* Product of two constants. */
6651 /* invar * invar is a giv, but attempt to simplify it somehow. */
6657 {
6658 /* (invar_0 * invar_1) * invar_2. Associate. */
6665 arg1)),
6667 }
6668 /* Propagate the MULT expressions to the innermost nodes. */
6670 {
6671 /* (invar_0 + invar_1) * invar_2. Distribute. */
6677 arg1),
6681 arg1)),
6683 }
6687 /* (a * invar_1) * invar_2. Associate. */
6693 arg1)),
6697 /* (a + invar_1) * invar_2. Distribute. */
6702 arg1),
6705 arg1)),
6710 }
6713 /* Shift by constant is multiply by power of two. */
6717 return
6726 /* "-a" is "a * (-1)" */
6732 /* "~a" is "-a - 1". Silly, but easy. */
6736 const1_rtx),
6740 /* Already in proper form for invariant. */
6746 /* Conditionally recognize extensions of simple IVs. After we've
6747 computed loop traversal counts and verified the range of the
6748 source IV, we'll reevaluate this as a GIV. */
6750 {
6753 {
6756 }
6757 }
6761 /* If this is a new register, we can't deal with it. */
6765 /* Check for biv or giv. */
6767 {
6771 {
6774 /* Form expression from giv and add benefit. Ensure this giv
6775 can derive another and subtract any needed adjustment if so. */
6777 /* Increasing the benefit here is risky. The only case in which it
6778 is arguably correct is if this is the only use of V. In other
6779 cases, this will artificially inflate the benefit of the current
6780 giv, and lead to suboptimal code. Thus, it is disabled, since
6781 potentially not reducing an only marginally beneficial giv is
6782 less harmful than reducing many givs that are not really
6783 beneficial. */
6784 {
6788 }
6801 {
6804 }
6805 else
6806 {
6809 }
6811 }
6814 do_default:
6815 /* If it isn't an induction variable, and it is invariant, we
6816 may be able to simplify things further by looking through
6817 the bits we just moved outside the loop. */
6819 {
6825 {
6826 /* Ok, we found a match. Substitute and simplify. */
6828 /* If we match another movable, we must use that, as
6829 this one is going away. */
6834 /* If consec is nonzero, this is a member of a group of
6835 instructions that were moved together. We handle this
6836 case only to the point of seeking to the last insn and
6837 looking for a REG_EQUAL. Fail if we don't find one. */
6839 {
6842 do
6843 {
6845 }
6851 }
6852 else
6853 {
6857 }
6860 {
6861 /* What we are most interested in is pointer
6862 arithmetic on invariants -- only take
6863 patterns we may be able to do something with. */
6869 {
6871 benefit);
6874 }
6879 {
6884 }
6885 }
6887 }
6888 }
6890 }
6892 /* Fall through to general case. */
6894 /* If invariant, return as USE (unless CONST_INT).
6895 Otherwise, not giv. */
6900 {
6909 }
6910 else
6912 }
6913 }
6915 /* This routine folds invariants such that there is only ever one
6916 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6918 static rtx
6920 {
6926 {
6929 }
6932 {
6935 }
6936 else
6937 {
6940 }
6941 }
6943 static rtx
6945 {
6947 {
6951 else
6954 }
6957 else
6960 }
6961 \f
6962 /* Help detect a giv that is calculated by several consecutive insns;
6963 for example,
6964 giv = biv * M
6965 giv = giv + A
6966 The caller has already identified the first insn P as having a giv as dest;
6967 we check that all other insns that set the same register follow
6968 immediately after P, that they alter nothing else,
6969 and that the result of the last is still a giv.
6971 The value is 0 if the reg set in P is not really a giv.
6972 Otherwise, the value is the amount gained by eliminating
6973 all the consecutive insns that compute the value.
6975 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6976 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6978 The coefficients of the ultimate giv value are stored in
6979 *MULT_VAL and *ADD_VAL. */
6981 static int
6985 {
6991 rtx temp;
6992 rtx set;
6994 /* Indicate that this is a giv so that we can update the value produced in
6995 each insn of the multi-insn sequence.
6997 This induction structure will be used only by the call to
6998 general_induction_var below, so we can allocate it on our stack.
6999 If this is a giv, our caller will replace the induct var entry with
7000 a new induction structure. */
7021 {
7025 /* If libcall, skip to end of call sequence. */
7036 /* Giv created by equivalent expression. */
7042 {
7046 count--;
7050 }
7052 {
7053 /* Allow insns that set something other than this giv to a
7054 constant. Such insns are needed on machines which cannot
7055 include long constants and should not disqualify a giv. */
7064 }
7065 }
7070 }
7071 \f
7072 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7073 represented by G1. If no such expression can be found, or it is clear that
7074 it cannot possibly be a valid address, 0 is returned.
7076 To perform the computation, we note that
7077 G1 = x * v + a and
7078 G2 = y * v + b
7079 where `v' is the biv.
7081 So G2 = (y/b) * G1 + (b - a*y/x).
7083 Note that MULT = y/x.
7085 Update: A and B are now allowed to be additive expressions such that
7086 B contains all variables in A. That is, computing B-A will not require
7087 subtracting variables. */
7089 static rtx
7091 {
7092 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7097 /* If MULT is not 1, we cannot handle A with non-constants, since we
7098 would then be required to subtract multiples of the registers in A.
7099 This is theoretically possible, and may even apply to some Fortran
7100 constructs, but it is a lot of work and we do not attempt it here. */
7105 /* In general these structures are sorted top to bottom (down the PLUS
7106 chain), but not left to right across the PLUS. If B is a higher
7107 order giv than A, we can strip one level and recurse. If A is higher
7108 order, we'll eventually bail out, but won't know that until the end.
7109 If they are the same, we'll strip one level around this loop. */
7112 {
7124 /* We matched: remove one reg completely. */
7127 /* An alternate match. */
7130 /* An alternate match. */
7132 else
7133 {
7134 /* Indicates an extra register in B. Strip one level from B and
7135 recurse, hoping B was the higher order expression. */
7140 }
7141 }
7143 /* Here we are at the last level of A, go through the cases hoping to
7144 get rid of everything but a constant. */
7147 {
7160 }
7162 {
7164 }
7166 {
7171 }
7173 {
7178 else
7180 }
7185 }
7187 rtx
7189 {
7192 /* The value that G1 will be multiplied by must be a constant integer. Also,
7193 the only chance we have of getting a valid address is if b*c/a (see above
7194 for notation) is also an integer. */
7197 {
7202 }
7205 else
7206 {
7207 /* ??? Find out if the one is a multiple of the other? */
7209 }
7213 {
7214 /* Failed. If we've got a multiplication factor between G1 and G2,
7215 scale G1's addend and try again. */
7217 {
7221 {
7222 HOST_WIDE_INT m;
7226 }
7227 else
7228 {
7230 mult);
7231 }
7234 }
7235 }
7239 /* Form simplified final result. */
7244 else
7249 else
7250 {
7253 {
7257 }
7260 }
7261 }
7262 \f
7263 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7264 represented by G1. This indicates that G2 should be combined with G1 and
7265 that G2 can use (either directly or via an address expression) a register
7266 used to represent G1. */
7268 static rtx
7270 {
7273 /* With the introduction of ext dependent givs, we must care for modes.
7274 G2 must not use a wider mode than G1. */
7284 /* If these givs are identical, they can be combined. We use the results
7285 of express_from because the addends are not in a canonical form, so
7286 rtx_equal_p is a weaker test. */
7287 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7288 combination to be the other way round. */
7291 {
7293 }
7295 /* If G2 can be expressed as a function of G1 and that function is valid
7296 as an address and no more expensive than using a register for G2,
7297 the expression of G2 in terms of G1 can be used. */
7304 }
7305 \f
7306 /* Check each extension dependent giv in this class to see if its
7307 root biv is safe from wrapping in the interior mode, which would
7308 make the giv illegal. */
7310 static void
7312 {
7316 HOST_WIDE_INT start_val;
7322 /* Make sure the iteration data is available. We must have
7323 constants in order to be certain of no overflow. */
7329 /* Make sure the host can represent the arithmetic. */
7331 {
7333 HOST_WIDE_INT s_end_val;
7345 /* Check for host arithmetic overflow. */
7347 {
7349 HOST_WIDE_INT s_max;
7356 /* Check zero extension of biv ok. */
7358 /* Check for host arithmetic overflow. */
7359 && (neg_incr
7362 /* Check for target arithmetic overflow. */
7363 && (neg_incr
7366 {
7368 }
7370 /* Check sign extension of biv ok. */
7371 /* ??? While it is true that overflow with signed and pointer
7372 arithmetic is undefined, I fear too many programmers don't
7373 keep this fact in mind -- myself included on occasion.
7374 So leave alone with the signed overflow optimizations. */
7376 /* Check for host arithmetic overflow. */
7377 && (neg_incr
7380 /* Check for target arithmetic overflow. */
7381 && (neg_incr
7384 {
7386 }
7387 }
7388 }
7390 /* If we know the BIV is compared at run-time against an
7391 invariant value, and the increment is +/- 1, we may also
7392 be able to prove that the BIV cannot overflow. */
7398 {
7399 /* If the increment is +1, and the exit test is a <,
7400 the BIV cannot overflow. (For <=, we have the
7401 problematic case that the comparison value might
7402 be the maximum value of the range.) */
7404 {
7409 }
7411 /* Likewise for increment -1 and exit test >. */
7413 {
7418 }
7419 }
7421 /* Invalidate givs that fail the tests. */
7424 {
7429 {
7438 /* We don't know whether this value is being used as either
7439 signed or unsigned, so to safely truncate we must satisfy
7440 both. The initial check here verifies the BIV itself;
7441 once that is successful we may check its range wrt the
7442 derived GIV. This works only if we were able to determine
7443 constant start and end values above. */
7445 {
7449 /* We know from the above that both endpoints are nonnegative,
7450 and that there is no wrapping. Verify that both endpoints
7451 are within the (signed) range of the outer mode. */
7454 }
7459 }
7462 {
7464 {
7468 }
7469 }
7470 else
7471 {
7473 {
7478 else
7479 {
7484 else
7486 }
7491 }
7494 }
7495 }
7496 }
7498 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7500 rtx
7502 {
7508 /* Recall that check_ext_dependent_givs verified that the known bounds
7509 of a biv did not overflow or wrap with respect to the extension for
7510 the giv. Therefore, constants need no additional adjustment. */
7514 /* Otherwise, we must adjust the value to compensate for the
7515 differing modes of the biv and the giv. */
7517 }
7518 \f
7519 struct combine_givs_stats
7520 {
7523 };
7525 static int
7527 {
7534 /* Stabilize the sort. */
7538 }
7540 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7541 any other. If so, point SAME to the giv combined with and set NEW_REG to
7542 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7543 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7545 static void
7547 {
7548 /* Additional benefit to add for being combined multiple times. */
7556 /* Count givs, because bl->giv_count is incorrect here. */
7560 giv_count++;
7572 {
7574 rtx single_use;
7579 /* If a DEST_REG GIV is used only once, do not allow it to combine
7580 with anything, for in doing so we will gain nothing that cannot
7581 be had by simply letting the GIV with which we would have combined
7582 to be reduced on its own. The losage shows up in particular with
7583 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7584 be seen elsewhere as well. */
7591 /* Add an additional weight for zero addends. */
7596 {
7597 rtx this_combine;
7602 {
7605 }
7606 }
7608 }
7610 /* Iterate, combining until we can't. */
7611 restart:
7615 {
7618 {
7624 }
7626 }
7629 {
7635 /* If it has already been combined, skip. */
7640 {
7643 /* If it has already been combined, skip. */
7645 {
7650 /* For destination, we now may replace by mem expression instead
7651 of register. This changes the costs considerably, so add the
7652 compensation. */
7662 /* ??? The new final_[bg]iv_value code does a much better job
7663 of finding replaceable giv's, and hence this code may no
7664 longer be necessary. */
7668 /* To help optimize the next set of combinations, remove
7669 this giv from the benefits of other potential mates. */
7671 {
7675 }
7682 }
7683 }
7685 /* To help optimize the next set of combinations, remove
7686 this giv from the benefits of other potential mates. */
7688 {
7690 {
7694 }
7698 /* We've finished with this giv, and everything it touched.
7699 Restart the combination so that proper weights for the
7700 rest of the givs are properly taken into account. */
7701 /* ??? Ideally we would compact the arrays at this point, so
7702 as to not cover old ground. But sanely compacting
7703 can_combine is tricky. */
7705 }
7706 }
7708 /* Clean up. */
7711 }
7712 \f
7713 /* Generate sequence for REG = B * M + A. B is the initial value of
7714 the basic induction variable, M a multiplicative constant, A an
7715 additive constant and REG the destination register. */
7717 static rtx
7719 {
7720 rtx seq;
7721 rtx result;
7724 /* Use unsigned arithmetic. */
7732 }
7735 /* Update registers created in insn sequence SEQ. */
7737 static void
7739 {
7740 rtx insn;
7742 /* Update register info for alias analysis. */
7746 {
7753 }
7754 }
7757 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7758 is the initial value of the basic induction variable, M a
7759 multiplicative constant, A an additive constant and REG the
7760 destination register. */
7762 void
7765 {
7766 rtx seq;
7769 {
7772 }
7774 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7777 /* Increase the lifetime of any invariants moved further in code. */
7782 /* It is possible that the expansion created lots of new registers.
7783 Iterate over the sequence we just created and record them all. We
7784 must do this before inserting the sequence. */
7788 }
7791 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7792 initial value of the basic induction variable, M a multiplicative
7793 constant, A an additive constant and REG the destination
7794 register. */
7796 void
7798 {
7799 rtx seq;
7801 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7804 /* Increase the lifetime of any invariants moved further in code.
7805 ???? Is this really necessary? */
7810 /* It is possible that the expansion created lots of new registers.
7811 Iterate over the sequence we just created and record them all. We
7812 must do this before inserting the sequence. */
7816 }
7819 /* Emit insns after loop to set REG = B * M + A. B is the initial
7820 value of the basic induction variable, M a multiplicative constant,
7821 A an additive constant and REG the destination register. */
7823 void
7825 {
7826 rtx seq;
7828 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7831 /* It is possible that the expansion created lots of new registers.
7832 Iterate over the sequence we just created and record them all. We
7833 must do this before inserting the sequence. */
7837 }
7841 /* Similar to gen_add_mult, but compute cost rather than generating
7842 sequence. */
7844 static int
7846 {
7856 {
7861 }
7864 }
7865 \f
7866 /* Test whether A * B can be computed without
7867 an actual multiply insn. Value is 1 if so.
7869 ??? This function stinks because it generates a ton of wasted RTL
7870 ??? and as a result fragments GC memory to no end. There are other
7871 ??? places in the compiler which are invoked a lot and do the same
7872 ??? thing, generate wasted RTL just to see if something is possible. */
7874 static int
7876 {
7877 rtx tmp;
7880 /* If only one is constant, make it B. */
7884 /* If first constant, both constant, so don't need multiply. */
7888 /* If second not constant, neither is constant, so would need multiply. */
7892 /* One operand is constant, so might not need multiply insn. Generate the
7893 code for the multiply and see if a call or multiply, or long sequence
7894 of insns is generated. */
7903 {
7906 {
7916 {
7919 }
7922 }
7923 }
7933 }
7934 \f
7935 /* Check to see if loop can be terminated by a "decrement and branch until
7936 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7937 Also try reversing an increment loop to a decrement loop
7938 to see if the optimization can be performed.
7939 Value is nonzero if optimization was performed. */
7941 /* This is useful even if the architecture doesn't have such an insn,
7942 because it might change a loops which increments from 0 to n to a loop
7943 which decrements from n to 0. A loop that decrements to zero is usually
7944 faster than one that increments from zero. */
7946 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7947 such as approx_final_value, biv_total_increment, loop_iterations, and
7948 final_[bg]iv_value. */
7950 static int
7952 {
7957 rtx reg;
7958 rtx jump_label;
7959 rtx final_value;
7960 rtx start_value;
7961 rtx new_add_val;
7962 rtx comparison;
7963 rtx before_comparison;
7964 rtx p;
7965 rtx jump;
7966 rtx first_compare;
7971 /* If last insn is a conditional branch, and the insn before tests a
7972 register value, try to optimize it. Otherwise, we can't do anything. */
7981 /* Try to compute whether the compare/branch at the loop end is one or
7982 two instructions. */
7988 else
7991 {
7992 /* If more than one condition is present to control the loop, then
7993 do not proceed, as this function does not know how to rewrite
7994 loop tests with more than one condition.
7996 Look backwards from the first insn in the last comparison
7997 sequence and see if we've got another comparison sequence. */
7999 rtx jump1;
8003 }
8005 /* Check all of the bivs to see if the compare uses one of them.
8006 Skip biv's set more than once because we can't guarantee that
8007 it will be zero on the last iteration. Also skip if the biv is
8008 used between its update and the test insn. */
8011 {
8016 first_compare))
8018 }
8020 /* Try swapping the comparison to identify a suitable biv. */
8027 first_compare))
8028 {
8030 VOIDmode,
8034 }
8039 /* Look for the case where the basic induction variable is always
8040 nonnegative, and equals zero on the last iteration.
8041 In this case, add a reg_note REG_NONNEG, which allows the
8042 m68k DBRA instruction to be used. */
8048 {
8049 /* Initial value must be greater than 0,
8050 init_val % -dec_value == 0 to ensure that it equals zero on
8051 the last iteration */
8057 {
8058 /* register always nonnegative, add REG_NOTE to branch */
8066 }
8068 /* If the decrement is 1 and the value was tested as >= 0 before
8069 the loop, then we can safely optimize. */
8071 {
8085 {
8093 }
8094 }
8095 }
8098 {
8099 /* Try to change inc to dec, so can apply above optimization. */
8100 /* Can do this if:
8101 all registers modified are induction variables or invariant,
8102 all memory references have non-overlapping addresses
8103 (obviously true if only one write)
8104 allow 2 insns for the compare/jump at the end of the loop. */
8105 /* Also, we must avoid any instructions which use both the reversed
8106 biv and another biv. Such instructions will fail if the loop is
8107 reversed. We meet this condition by requiring that either
8108 no_use_except_counting is true, or else that there is only
8109 one biv. */
8111 /* 1 if the iteration var is used only to count iterations. */
8113 /* 1 if the loop has no memory store, or it has a single memory store
8114 which is reversible. */
8120 {
8124 /* If there are no givs for this biv, and the only exit is the
8125 fall through at the end of the loop, then
8126 see if perhaps there are no uses except to count. */
8130 {
8135 /* An insn that sets the biv is okay. */
8136 ;
8138 /* An insn that doesn't mention the biv is okay. */
8139 ;
8142 {
8143 /* If either of these insns uses the biv and sets a pseudo
8144 that has more than one usage, then the biv has uses
8145 other than counting since it's used to derive a value
8146 that is used more than one time. */
8148 regs);
8150 {
8153 }
8154 }
8155 else
8156 {
8159 }
8160 }
8162 /* A biv has uses besides counting if it is used to set
8163 another biv. */
8167 {
8170 }
8171 }
8174 /* No need to worry about MEMs. */
8175 ;
8177 {
8182 /* If the loop has a single store, and the destination address is
8183 invariant, then we can't reverse the loop, because this address
8184 might then have the wrong value at loop exit.
8185 This would work if the source was invariant also, however, in that
8186 case, the insn should have been moved out of the loop. */
8189 {
8192 /* If we could prove that each of the memory locations
8193 written to was different, then we could reverse the
8194 store -- but we don't presently have any way of
8195 knowing that. */
8198 /* If the store depends on a register that is set after the
8199 store, it depends on the initial value, and is thus not
8200 reversible. */
8202 {
8209 }
8210 }
8211 }
8212 else
8215 /* This code only acts for innermost loops. Also it simplifies
8216 the memory address check by only reversing loops with
8217 zero or one memory access.
8218 Two memory accesses could involve parts of the same array,
8219 and that can't be reversed.
8220 If the biv is used only for counting, than we don't need to worry
8221 about all these things. */
8227 && reversible_mem_store
8232 {
8233 rtx tem;
8235 /* Loop can be reversed. */
8239 /* Now check other conditions:
8241 The increment must be a constant, as must the initial value,
8242 and the comparison code must be LT.
8244 This test can probably be improved since +/- 1 in the constant
8245 can be obtained by changing LT to LE and vice versa; this is
8246 confusing. */
8249 /* for constants, LE gets turned into LT */
8254 {
8265 comparison_const_width
8267 else
8268 comparison_const_width
8272 comparison_sign_mask
8275 /* If the comparison value is not a loop invariant, then we
8276 can not reverse this loop.
8278 ??? If the insns which initialize the comparison value as
8279 a whole compute an invariant result, then we could move
8280 them out of the loop and proceed with loop reversal. */
8288 /* Normalize the initial value if it is an integer and
8289 has no other use except as a counter. This will allow
8290 a few more loops to be reversed. */
8294 {
8296 /* The code below requires comparison_val to be a multiple
8297 of add_val in order to do the loop reversal, so
8298 round up comparison_val to a multiple of add_val.
8299 Since comparison_value is constant, we know that the
8300 current comparison code is LT. */
8302 comparison_val
8304 /* We postpone overflow checks for COMPARISON_VAL here;
8305 even if there is an overflow, we might still be able to
8306 reverse the loop, if converting the loop exit test to
8307 NE is possible. */
8309 }
8311 /* First check if we can do a vanilla loop reversal. */
8313 /* If we have a decrement_and_branch_on_count,
8314 prefer the NE test, since this will allow that
8315 instruction to be generated. Note that we must
8316 use a vanilla loop reversal if the biv is used to
8317 calculate a giv or has a non-counting use. */
8318 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8319 && defined (HAVE_decrement_and_branch_on_count)
8323 #endif
8325 /* Now do postponed overflow checks on COMPARISON_VAL. */
8328 {
8329 /* Register will always be nonnegative, with value
8330 0 on last iteration */
8334 }
8338 {
8341 }
8342 else
8348 /* If the initial value is not zero, or if the comparison
8349 value is not an exact multiple of the increment, then we
8350 can not reverse this loop. */
8353 {
8356 }
8357 else
8358 {
8361 }
8365 /* Reset these in case we normalized the initial value
8366 and comparison value above. */
8369 {
8371 final_value
8373 }
8376 /* Save some info needed to produce the new insns. */
8381 /* Set start_value; if this is not a CONST_INT, we need
8382 to generate a SUB.
8383 Initialize biv to start_value before loop start.
8384 The old initializing insn will be deleted as a
8385 dead store by flow.c. */
8388 {
8391 }
8393 {
8401 start_value
8407 }
8409 {
8412 initial_value);
8416 start_value
8419 }
8420 else
8421 /* We could handle the other cases too, but it'll be
8422 better to have a testcase first. */
8425 /* We may not have a single insn which can increment a reg, so
8426 create a sequence to hold all the insns from expand_inc. */
8435 /* Update biv info to reflect its new status. */
8440 /* Update loop info. */
8449 /* Inc LABEL_NUSES so that delete_insn will
8450 not delete the label. */
8453 /* Emit an insn after the end of the loop to set the biv's
8454 proper exit value if it is used anywhere outside the loop. */
8460 /* Delete compare/branch at end of loop. */
8465 /* Add new compare/branch insn at end of loop. */
8477 ;
8483 {
8485 {
8486 /* Increment of LABEL_NUSES done above. */
8487 /* Register is now always nonnegative,
8488 so add REG_NONNEG note to the branch. */
8491 }
8493 }
8495 /* No insn may reference both the reversed and another biv or it
8496 will fail (see comment near the top of the loop reversal
8497 code).
8498 Earlier on, we have verified that the biv has no use except
8499 counting, or it is the only biv in this function.
8500 However, the code that computes no_use_except_counting does
8501 not verify reg notes. It's possible to have an insn that
8502 references another biv, and has a REG_EQUAL note with an
8503 expression based on the reversed biv. To avoid this case,
8504 remove all REG_EQUAL notes based on the reversed biv
8505 here. */
8508 {
8511 /* If this is a set of a GIV based on the reversed biv, any
8512 REG_EQUAL notes should still be correct. */
8519 {
8524 else
8526 }
8527 }
8529 /* Mark that this biv has been reversed. Each giv which depends
8530 on this biv, and which is also live past the end of the loop
8531 will have to be fixed up. */
8536 {
8540 else
8542 }
8545 }
8546 }
8547 }
8550 }
8551 \f
8552 /* Verify whether the biv BL appears to be eliminable,
8553 based on the insns in the loop that refer to it.
8555 If ELIMINATE_P is nonzero, actually do the elimination.
8557 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8558 determine whether invariant insns should be placed inside or at the
8559 start of the loop. */
8561 static int
8564 {
8567 rtx p;
8569 /* Scan all insns in the loop, stopping if we find one that uses the
8570 biv in a way that we cannot eliminate. */
8573 {
8577 rtx note;
8579 /* If this is a libcall that sets a giv, skip ahead to its end. */
8581 {
8585 {
8590 {
8597 }
8598 }
8599 }
8601 /* Closely examine the insn if the biv is mentioned. */
8606 {
8612 }
8614 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8619 }
8622 {
8627 }
8630 }
8631 \f
8632 /* INSN and REFERENCE are instructions in the same insn chain.
8633 Return nonzero if INSN is first. */
8635 int
8637 {
8641 {
8642 /* Start with test for not first so that INSN == REFERENCE yields not
8643 first. */
8649 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8650 previous insn, hence the <= comparison below does not work if
8651 P is a note. */
8662 }
8663 }
8665 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8666 the offset that we have to take into account due to auto-increment /
8667 div derivation is zero. */
8668 static int
8671 {
8672 /* If the giv V had the auto-inc address optimization applied
8673 to it, and INSN occurs between the giv insn and the biv
8674 insn, then we'd have to adjust the value used here.
8675 This is rare, so we don't bother to make this possible. */
8684 }
8686 /* If BL appears in X (part of the pattern of INSN), see if we can
8687 eliminate its use. If so, return 1. If not, return 0.
8689 If BIV does not appear in X, return 1.
8691 If ELIMINATE_P is nonzero, actually do the elimination.
8692 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8693 Depending on how many items have been moved out of the loop, it
8694 will either be before INSN (when WHERE_INSN is nonzero) or at the
8695 start of the loop (when WHERE_INSN is zero). */
8697 static int
8701 {
8707 #ifdef HAVE_cc0
8709 #endif
8715 {
8717 /* If we haven't already been able to do something with this BIV,
8718 we can't eliminate it. */
8724 /* If this sets the BIV, it is not a problem. */
8728 /* If this is an insn that defines a giv, it is also ok because
8729 it will go away when the giv is reduced. */
8734 #ifdef HAVE_cc0
8736 {
8737 /* Can replace with any giv that was reduced and
8738 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8739 Require a constant for MULT_VAL, so we know it's nonzero.
8740 ??? We disable this optimization to avoid potential
8741 overflows. */
8749 {
8756 /* If the giv has the opposite direction of change,
8757 then reverse the comparison. */
8761 else
8764 /* We can probably test that giv's reduced reg. */
8767 }
8769 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8770 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8771 Require a constant for MULT_VAL, so we know it's nonzero.
8772 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8773 overflow problem. */
8785 {
8792 /* If the giv has the opposite direction of change,
8793 then reverse the comparison. */
8797 else
8801 /* Replace biv with the giv's reduced register. */
8806 /* Insn doesn't support that constant or invariant. Copy it
8807 into a register (it will be a loop invariant.) */
8814 /* Substitute the new register for its invariant value in
8815 the compare expression. */
8819 }
8820 }
8821 #endif
8828 /* See if either argument is the biv. */
8833 else
8837 {
8838 /* First try to replace with any giv that has constant positive
8839 mult_val and constant add_val. We might be able to support
8840 negative mult_val, but it seems complex to do it in general. */
8852 {
8856 /* Don't eliminate if the linear combination that makes up
8857 the giv overflows when it is applied to ARG. */
8859 {
8860 rtx add_val;
8864 else
8870 }
8875 /* Replace biv with the giv's reduced reg. */
8878 /* If all constants are actually constant integers and
8879 the derived constant can be directly placed in the COMPARE,
8880 do so. */
8883 {
8886 }
8887 else
8888 {
8889 /* Otherwise, load it into a register. */
8894 }
8900 }
8902 /* Look for giv with positive constant mult_val and nonconst add_val.
8903 Insert insns to calculate new compare value.
8904 ??? Turn this off due to possible overflow. */
8912 {
8913 rtx tem;
8923 /* Replace biv with giv's reduced register. */
8927 /* Compute value to compare against. */
8931 /* Use it in this insn. */
8935 }
8936 }
8938 {
8940 {
8941 /* Look for giv with constant positive mult_val and nonconst
8942 add_val. Insert insns to compute new compare value.
8943 ??? Turn this off due to possible overflow. */
8950 {
8951 rtx tem;
8961 /* Replace biv with giv's reduced register. */
8965 /* Compute value to compare against. */
8972 }
8973 }
8975 /* This code has problems. Basically, you can't know when
8976 seeing if we will eliminate BL, whether a particular giv
8977 of ARG will be reduced. If it isn't going to be reduced,
8978 we can't eliminate BL. We can try forcing it to be reduced,
8979 but that can generate poor code.
8981 The problem is that the benefit of reducing TV, below should
8982 be increased if BL can actually be eliminated, but this means
8983 we might have to do a topological sort of the order in which
8984 we try to process biv. It doesn't seem worthwhile to do
8985 this sort of thing now. */
8987 #if 0
8988 /* Otherwise the reg compared with had better be a biv. */
8993 /* Look for a pair of givs, one for each biv,
8994 with identical coefficients. */
8996 {
9008 {
9015 /* Replace biv with its giv's reduced reg. */
9017 /* Replace other operand with the other giv's
9018 reduced reg. */
9021 }
9022 }
9023 #endif
9024 }
9026 /* If we get here, the biv can't be eliminated. */
9030 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9031 biv is used in it, since it will be replaced. */
9039 }
9041 /* See if any subexpression fails elimination. */
9044 {
9046 {
9059 }
9060 }
9063 }
9064 \f
9065 /* Return nonzero if the last use of REG
9066 is in an insn following INSN in the same basic block. */
9068 static int
9070 {
9071 rtx n;
9075 {
9078 }
9080 }
9081 \f
9082 /* Called via `note_stores' to record the initial value of a biv. Here we
9083 just record the location of the set and process it later. */
9085 static void
9087 {
9098 /* If this is the first set found, record it. */
9100 {
9103 }
9104 }
9105 \f
9106 /* If any of the registers in X are "old" and currently have a last use earlier
9107 than INSN, update them to have a last use of INSN. Their actual last use
9108 will be the previous insn but it will not have a valid uid_luid so we can't
9109 use it. X must be a source expression only. */
9111 static void
9113 {
9114 /* Check for the case where INSN does not have a valid luid. In this case,
9115 there is no need to modify the regno_last_uid, as this can only happen
9116 when code is inserted after the loop_end to set a pseudo's final value,
9117 and hence this insn will never be the last use of x.
9118 ???? This comment is not correct. See for example loop_givs_reduce.
9119 This may insert an insn before another new insn. */
9123 {
9125 }
9126 else
9127 {
9131 {
9137 }
9138 }
9139 }
9140 \f
9141 /* Given an insn INSN and condition COND, return the condition in a
9142 canonical form to simplify testing by callers. Specifically:
9144 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9145 (2) Both operands will be machine operands; (cc0) will have been replaced.
9146 (3) If an operand is a constant, it will be the second operand.
9147 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9148 for GE, GEU, and LEU.
9150 If the condition cannot be understood, or is an inequality floating-point
9151 comparison which needs to be reversed, 0 will be returned.
9153 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9155 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9156 insn used in locating the condition was found. If a replacement test
9157 of the condition is desired, it should be placed in front of that
9158 insn and we will be sure that the inputs are still valid.
9160 If WANT_REG is nonzero, we wish the condition to be relative to that
9161 register, if possible. Therefore, do not canonicalize the condition
9162 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9163 to be a compare to a CC mode register. */
9165 rtx
9168 {
9171 rtx set;
9172 rtx tem;
9190 /* If we are comparing a register with zero, see if the register is set
9191 in the previous insn to a COMPARE or a comparison operation. Perform
9192 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9193 in cse.c */
9198 {
9199 /* Set nonzero when we find something of interest. */
9202 #ifdef HAVE_cc0
9203 /* If comparison with cc0, import actual comparison from compare
9204 insn. */
9206 {
9217 }
9218 #endif
9220 /* If this is a COMPARE, pick up the two things being compared. */
9222 {
9226 }
9230 /* Go back to the previous insn. Stop if it is not an INSN. We also
9231 stop if it isn't a single set or if it has a REG_INC note because
9232 we don't want to bother dealing with it. */
9246 /* If this is setting OP0, get what it sets it to if it looks
9247 relevant. */
9249 {
9251 #ifdef FLOAT_STORE_FLAG_VALUE
9252 REAL_VALUE_TYPE fsfv;
9253 #endif
9255 /* ??? We may not combine comparisons done in a CCmode with
9256 comparisons not done in a CCmode. This is to aid targets
9257 like Alpha that have an IEEE compliant EQ instruction, and
9258 a non-IEEE compliant BEQ instruction. The use of CCmode is
9259 actually artificial, simply to prevent the combination, but
9260 should not affect other platforms.
9262 However, we must allow VOIDmode comparisons to match either
9263 CCmode or non-CCmode comparison, because some ports have
9264 modeless comparisons inside branch patterns.
9266 ??? This mode check should perhaps look more like the mode check
9267 in simplify_comparison in combine. */
9275 && (STORE_FLAG_VALUE
9278 #ifdef FLOAT_STORE_FLAG_VALUE
9283 #endif
9284 ))
9295 && (STORE_FLAG_VALUE
9298 #ifdef FLOAT_STORE_FLAG_VALUE
9303 #endif
9304 ))
9310 {
9313 }
9314 else
9316 }
9319 /* If this sets OP0, but not directly, we have to give up. */
9323 {
9327 {
9332 }
9337 }
9338 }
9340 /* If constant is first, put it last. */
9344 /* If OP0 is the result of a comparison, we weren't able to find what
9345 was really being compared, so fail. */
9350 /* Canonicalize any ordered comparison with integers involving equality
9351 if we can do computations in the relevant mode and we do not
9352 overflow. */
9358 {
9361 unsigned HOST_WIDE_INT max_val
9365 {
9371 /* When cross-compiling, const_val might be sign-extended from
9372 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9392 }
9393 }
9395 /* Never return CC0; return zero instead. */
9400 }
9402 /* Given a jump insn JUMP, return the condition that will cause it to branch
9403 to its JUMP_LABEL. If the condition cannot be understood, or is an
9404 inequality floating-point comparison which needs to be reversed, 0 will
9405 be returned.
9407 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9408 insn used in locating the condition was found. If a replacement test
9409 of the condition is desired, it should be placed in front of that
9410 insn and we will be sure that the inputs are still valid.
9412 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9413 compare CC mode register. */
9415 rtx
9417 {
9418 rtx cond;
9420 rtx set;
9422 /* If this is not a standard conditional jump, we can't parse it. */
9430 /* If this branches to JUMP_LABEL when the condition is false, reverse
9431 the condition. */
9432 reverse
9437 allow_cc_mode);
9438 }
9440 /* Similar to above routine, except that we also put an invariant last
9441 unless both operands are invariants. */
9443 rtx
9445 {
9455 }
9457 /* Scan the function and determine whether it has indirect (computed) jumps.
9459 This is taken mostly from flow.c; similar code exists elsewhere
9460 in the compiler. It may be useful to put this into rtlanal.c. */
9461 static int
9463 {
9464 rtx insn;
9471 }
9473 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9474 documentation for LOOP_MEMS for the definition of `appropriate'.
9475 This function is called from prescan_loop via for_each_rtx. */
9477 static int
9479 {
9488 {
9493 /* We're not interested in MEMs that are only clobbered. */
9497 /* We're not interested in the MEM associated with a
9498 CONST_DOUBLE, so there's no need to traverse into this. */
9502 /* We're not interested in any MEMs that only appear in notes. */
9506 /* This is not a MEM. */
9508 }
9510 /* See if we've already seen this MEM. */
9513 {
9515 /* The modes of the two memory accesses are different. If
9516 this happens, something tricky is going on, and we just
9517 don't optimize accesses to this MEM. */
9521 }
9523 /* Resize the array, if necessary. */
9525 {
9528 else
9533 }
9535 /* Actually insert the MEM. */
9537 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9538 because we can't put it in a register. We still store it in the
9539 table, though, so that if we see the same address later, but in a
9540 non-BLK mode, we'll not think we can optimize it at that point. */
9546 }
9549 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9551 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9552 register that is modified by an insn between FROM and TO. If the
9553 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9554 more, stop incrementing it, to avoid overflow.
9556 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9557 register I is used, if it is only used once. Otherwise, it is set
9558 to 0 (for no uses) or const0_rtx for more than one use. This
9559 parameter may be zero, in which case this processing is not done.
9561 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9562 optimize register I. */
9564 static void
9566 {
9569 /* last_set[n] is nonzero iff reg n has been set in the current
9570 basic block. In that case, it is the insn that last set reg n. */
9572 rtx insn;
9578 /* Grow the regs array if not allocated or too small. */
9580 {
9585 /* Zero the new elements. */
9588 }
9590 /* Clear previously scanned fields but do not clear n_times_set. */
9592 {
9596 }
9600 /* Scan the loop, recording register usage. */
9603 {
9605 {
9606 /* Record registers that have exactly one use. */
9609 /* Include uses in REG_EQUAL notes. */
9617 {
9621 last_set);
9622 }
9623 }
9628 /* Invalidate all registers used for function argument passing.
9629 We check rtx_varies_p for the same reason as below, to allow
9630 optimizing PIC calculations. */
9632 {
9633 rtx link;
9635 link;
9637 {
9644 }
9645 }
9646 }
9648 /* Invalidate all hard registers clobbered by calls. With one exception:
9649 a call-clobbered PIC register is still function-invariant for our
9650 purposes, since we can hoist any PIC calculations out of the loop.
9651 Thus the call to rtx_varies_p. */
9656 {
9659 }
9661 #ifdef AVOID_CCMODE_COPIES
9662 /* Don't try to move insns which set CC registers if we should not
9663 create CCmode register copies. */
9667 #endif
9669 /* Set regs->array[I].n_times_set for the new registers. */
9674 }
9676 /* Returns the number of real INSNs in the LOOP. */
9678 static int
9680 {
9682 rtx insn;
9690 }
9692 /* Move MEMs into registers for the duration of the loop. */
9694 static void
9696 {
9703 rtx end_label;
9704 /* Nonzero if the next instruction may never be executed. */
9711 /* We cannot use next_label here because it skips over normal insns. */
9716 /* Check to see if it's possible that some instructions in the loop are
9717 never executed. Also check if there is a goto out of the loop other
9718 than right after the end of the loop. */
9722 {
9726 /* If we enter the loop in the middle, and scan
9727 around to the beginning, don't set maybe_never
9728 for that. This must be an unconditional jump,
9729 otherwise the code at the top of the loop might
9730 never be executed. Unconditional jumps are
9731 followed a by barrier then loop end. */
9736 {
9737 /* If this is a jump outside of the loop but not right
9738 after the end of the loop, we would have to emit new fixup
9739 sequences for each such label. */
9741 JUMP_INSN is executed, we must be conservative. */
9750 /* Something complicated. */
9752 else
9753 /* If there are any more instructions in the loop, they
9754 might not be reached. */
9756 }
9759 }
9761 /* Find start of the extended basic block that enters the loop. */
9765 ;
9770 /* Build table of mems that get set to constant values before the
9771 loop. */
9775 /* Actually move the MEMs. */
9777 {
9778 regset_head load_copies;
9779 regset_head store_copies;
9781 rtx reg;
9783 rtx mem_list_entry;
9787 /* There's no telling whether or not MEM is modified. */
9790 /* Go through the MEMs written to in the loop to see if this
9791 one is aliased by one of them. */
9794 {
9799 {
9800 /* MEM is indeed aliased by this store. */
9803 }
9805 }
9811 /* If this MEM is written to, we must be sure that there
9812 are no reads from another MEM that aliases this one. */
9814 {
9818 {
9822 VOIDmode,
9824 rtx_varies_p))
9825 {
9826 /* It's not safe to hoist loop_info->mems[i] out of
9827 the loop because writes to it might not be
9828 seen by reads from loop_info->mems[j]. */
9831 }
9832 }
9833 }
9836 /* We can't access the MEM outside the loop; it might
9837 cause a trap that wouldn't have happened otherwise. */
9841 /* We thought we were going to lift this MEM out of the
9842 loop, but later discovered that we could not. */
9848 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9849 order to keep scan_loop from moving stores to this MEM
9850 out of the loop just because this REG is neither a
9851 user-variable nor used in the loop test. */
9856 /* Now, replace all references to the MEM with the
9857 corresponding pseudos. */
9862 {
9864 {
9865 rtx set;
9869 /* See if this copies the mem into a register that isn't
9870 modified afterwards. We'll try to do copy propagation
9871 a little further on. */
9873 /* @@@ This test is _way_ too conservative. */
9874 && ! maybe_never
9882 /* See if this copies the mem from a register that isn't
9883 modified afterwards. We'll try to remove the
9884 redundant copy later on by doing a little register
9885 renaming and copy propagation. This will help
9886 to untangle things for the BIV detection code. */
9888 && ! maybe_never
9896 /* If this is a call which uses / clobbers this memory
9897 location, we must not change the interface here. */
9901 {
9905 }
9906 else
9907 /* Replace the memory reference with the shadow register. */
9910 }
9915 }
9920 /* We couldn't replace all occurrences of the MEM. */
9922 else
9923 {
9924 /* Load the memory immediately before LOOP->START, which is
9925 the NOTE_LOOP_BEG. */
9927 rtx set;
9933 {
9937 {
9941 /* Extending hard register lifetimes causes crash
9942 on SRC targets. Doing so on non-SRC is
9943 probably also not good idea, since we most
9944 probably have pseudoregister equivalence as
9945 well. */
9948 }
9949 /* Use the constant equivalence if that is cheap enough. */
9955 {
9958 }
9960 /* If best_equiv is nonzero, we know that MEM is set to a
9961 constant or register before the loop. We will use this
9962 knowledge to initialize the shadow register with that
9963 constant or reg rather than by loading from MEM. */
9966 }
9971 {
9974 {
9977 }
9978 }
9984 {
9986 {
9989 }
9991 /* Store the memory immediately after END, which is
9992 the NOTE_LOOP_END. */
9995 }
9998 {
10003 }
10005 /* Attempt a bit of copy propagation. This helps untangle the
10006 data flow, and enables {basic,general}_induction_var to find
10007 more bivs/givs. */
10008 EXECUTE_IF_SET_IN_REG_SET
10010 {
10012 });
10015 EXECUTE_IF_SET_IN_REG_SET
10017 {
10019 });
10021 }
10022 }
10024 /* Now, we need to replace all references to the previous exit
10025 label with the new one. */
10032 }
10034 /* For communication between note_reg_stored and its caller. */
10035 struct note_reg_stored_arg
10036 {
10038 rtx reg;
10039 };
10041 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10042 is equal to ARG. */
10043 static void
10045 {
10049 }
10051 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10052 There must be exactly one insn that sets this pseudo; it will be
10053 deleted if all replacements succeed and we can prove that the register
10054 is not used after the loop. */
10056 static void
10058 {
10059 /* This is the reg that we are copying from. */
10062 rtx insn;
10063 /* These help keep track of whether we replaced all uses of the reg. */
10070 {
10071 rtx set;
10073 /* Only substitute within one extended basic block from the initializing
10074 insn. */
10081 /* Is this the initializing insn? */
10086 {
10093 }
10095 /* Only substitute after seeing the initializing insn. */
10097 {
10104 /* Stop replacing when REPLACEMENT is modified. */
10109 {
10112 /* It is possible that we've turned previously valid REG_EQUAL to
10113 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10114 REPLACEMENT is modified, we get different meaning. */
10118 }
10119 }
10120 }
10124 {
10128 {
10129 rtx first;
10130 rtx retval_note;
10132 /* Assume we're just deleting INIT_INSN. */
10134 /* Look for REG_RETVAL note. If we're deleting the end of
10135 the libcall sequence, the whole sequence can go. */
10137 /* If we found a REG_RETVAL note, find the first instruction
10138 in the sequence. */
10142 /* Delete the instructions. */
10144 }
10147 }
10148 }
10150 /* Replace all the instructions from FIRST up to and including LAST
10151 with NOTE_INSN_DELETED notes. */
10153 static void
10155 {
10157 {
10163 /* If this was the LAST instructions we're supposed to delete,
10164 we're done. */
10169 }
10170 }
10172 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10173 loop LOOP if the order of the sets of these registers can be
10174 swapped. There must be exactly one insn within the loop that sets
10175 this pseudo followed immediately by a move insn that sets
10176 REPLACEMENT with REGNO. */
10177 static void
10180 {
10181 rtx insn;
10190 {
10191 /* Search for the insn that copies REGNO to NEW_REGNO? */
10199 }
10202 {
10203 rtx prev_insn;
10204 rtx prev_set;
10206 /* Some DEF-USE info would come in handy here to make this
10207 function more general. For now, just check the previous insn
10208 which is the most likely candidate for setting REGNO. */
10216 {
10217 /* We have:
10218 (set (reg regno) (expr))
10219 (set (reg new_regno) (reg regno))
10221 so try converting this to:
10222 (set (reg new_regno) (expr))
10223 (set (reg regno) (reg new_regno))
10225 The former construct is often generated when a global
10226 variable used for an induction variable is shadowed by a
10227 register (NEW_REGNO). The latter construct improves the
10228 chances of GIV replacement and BIV elimination. */
10238 {
10245 /* Update first use of REGNO. */
10249 /* Now perform copy propagation to hopefully
10250 remove all uses of REGNO within the loop. */
10252 }
10253 }
10254 }
10255 }
10257 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10259 static int
10261 {
10263 {
10267 }
10269 }
10271 /* Returns the first MEM found in NOTE by depth-first search. */
10273 static rtx
10275 {
10279 }
10281 /* Replace MEM with its associated pseudo register. This function is
10282 called from load_mems via for_each_rtx. DATA is actually a pointer
10283 to a structure describing the instruction currently being scanned
10284 and the MEM we are currently replacing. */
10286 static int
10288 {
10296 {
10301 /* We're not interested in the MEM associated with a
10302 CONST_DOUBLE, so there's no need to traverse into one. */
10306 /* This is not a MEM. */
10308 }
10311 /* This is not the MEM we are currently replacing. */
10314 /* Actually replace the MEM. */
10318 }
10320 static void
10322 {
10323 loop_replace_args args;
10331 /* If we hoist a mem write out of the loop, then REG_EQUAL
10332 notes referring to the mem are no longer valid. */
10334 {
10339 {
10343 {
10344 /* Remove the note. */
10347 }
10348 }
10349 }
10350 }
10352 /* Replace one register with another. Called through for_each_rtx; PX points
10353 to the rtx being scanned. DATA is actually a pointer to
10354 a structure of arguments. */
10356 static int
10358 {
10369 }
10371 static void
10373 {
10374 loop_replace_args args;
10381 }
10382 \f
10383 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10384 (ignored in the interim). */
10386 static rtx
10389 rtx pattern)
10390 {
10392 }
10395 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10396 in basic block WHERE_BB (ignored in the interim) within the loop
10397 otherwise hoist PATTERN into the loop pre-header. */
10399 rtx
10401 basic_block where_bb ATTRIBUTE_UNUSED,
10403 {
10407 }
10410 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10411 WHERE_BB (ignored in the interim) within the loop. */
10413 static rtx
10415 basic_block where_bb ATTRIBUTE_UNUSED,
10417 {
10419 }
10422 /* Hoist insn for PATTERN into the loop pre-header. */
10424 rtx
10426 {
10428 }
10431 /* Hoist call insn for PATTERN into the loop pre-header. */
10433 static rtx
10435 {
10437 }
10440 /* Sink insn for PATTERN after the loop end. */
10442 rtx
10444 {
10446 }
10448 /* bl->final_value can be either general_operand or PLUS of general_operand
10449 and constant. Emit sequence of instructions to load it into REG. */
10450 static rtx
10452 {
10453 rtx seq;
10461 }
10463 /* If the loop has multiple exits, emit insn for PATTERN before the
10464 loop to ensure that it will always be executed no matter how the
10465 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10466 since this is slightly more efficient. */
10468 static rtx
10470 {
10473 else
10475 }
10476 \f
10477 static void
10479 {
10487 iv_num++;
10492 {
10495 }
10496 }
10499 static void
10502 {
10504 rtx incr;
10515 {
10518 }
10520 {
10523 }
10527 {
10531 }
10534 {
10538 }
10540 /* List the increments. */
10542 {
10546 }
10548 /* List the givs. */
10550 {
10555 else
10558 }
10559 }
10562 static void
10564 {
10575 {
10579 }
10582 }
10585 static void
10587 {
10594 else
10610 {
10612 {
10624 }
10625 }
10636 {
10640 }
10643 }
10646 void
10648 {
10650 }
10653 void
10655 {
10657 }
10660 void
10662 {
10664 }
10667 void
10669 {
10671 }
10674 #define LOOP_BLOCK_NUM_1(INSN) \
10675 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10677 /* The notes do not have an assigned block, so look at the next insn. */
10678 #define LOOP_BLOCK_NUM(INSN) \
10679 ((INSN) ? (GET_CODE (INSN) == NOTE \
10680 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10681 : LOOP_BLOCK_NUM_1 (INSN)) \
10682 : -1)
10684 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10686 static void
10689 {
10690 rtx label;
10695 /* Print diagnostics to compare our concept of a loop with
10696 what the loop notes say. */
10711 {
10731 {
10734 {
10737 }
10738 }
10741 /* This can happen when a marked loop appears as two nested loops,
10742 say from while (a || b) {}. The inner loop won't match
10743 the loop markers but the outer one will. */
10746 }
10747 }
10749 /* Call this function from the debugger to dump LOOP. */
10751 void
10753 {
10755 }
10757 /* Call this function from the debugger to dump LOOPS. */
10759 void
10761 {
10763 }