1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "target-def.h"
45 /* The size of the callee register save area. Right now we save everything
46 on entry since it costs us nothing in code size. It does cost us from a
47 speed standpoint, so we want to optimize this sooner or later. */
48 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
49 + 4 * regs_ever_live[3] \
50 + 4 * regs_ever_live[6] \
51 + 4 * regs_ever_live[7] \
52 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
53 || regs_ever_live[16] || regs_ever_live[17]))
55 /* Initialize the GCC target structure. */
56 #undef TARGET_ASM_ALIGNED_HI_OP
57 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
59 struct gcc_target targetm
= TARGET_INITIALIZER
;
65 fprintf (file
, "#\tGCC For the Matsushita MN10300\n");
67 fprintf (file
, "# -O%d\n", optimize
);
69 fprintf (file
, "\n\n");
72 fprintf (file
, "\t.am33\n");
73 output_file_directive (file
, main_input_filename
);
77 /* Print operand X using operand code CODE to assembly language output file
81 print_operand (file
, x
, code
)
90 /* These are normal and reversed branches. */
91 switch (code
== 'b' ? GET_CODE (x
) : reverse_condition (GET_CODE (x
)))
100 fprintf (file
, "ge");
103 fprintf (file
, "gt");
106 fprintf (file
, "le");
109 fprintf (file
, "lt");
112 fprintf (file
, "cc");
115 fprintf (file
, "hi");
118 fprintf (file
, "ls");
121 fprintf (file
, "cs");
128 /* This is used for the operand to a call instruction;
129 if it's a REG, enclose it in parens, else output
130 the operand normally. */
131 if (GET_CODE (x
) == REG
)
134 print_operand (file
, x
, 0);
138 print_operand (file
, x
, 0);
141 /* These are the least significant word in a 64bit value. */
143 switch (GET_CODE (x
))
147 output_address (XEXP (x
, 0));
152 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
156 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
164 switch (GET_MODE (x
))
167 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
168 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
169 fprintf (file
, "0x%lx", val
[0]);
172 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
173 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
174 fprintf (file
, "0x%lx", val
[0]);
178 print_operand_address (file
,
179 GEN_INT (CONST_DOUBLE_LOW (x
)));
190 split_double (x
, &low
, &high
);
191 fprintf (file
, "%ld", (long)INTVAL (low
));
200 /* Similarly, but for the most significant word. */
202 switch (GET_CODE (x
))
206 x
= adjust_address (x
, SImode
, 4);
207 output_address (XEXP (x
, 0));
212 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
216 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
224 switch (GET_MODE (x
))
227 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
228 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
229 fprintf (file
, "0x%lx", val
[1]);
235 print_operand_address (file
,
236 GEN_INT (CONST_DOUBLE_HIGH (x
)));
247 split_double (x
, &low
, &high
);
248 fprintf (file
, "%ld", (long)INTVAL (high
));
259 if (GET_CODE (XEXP (x
, 0)) == REG
)
260 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), GEN_INT (0)));
262 output_address (XEXP (x
, 0));
267 output_address (GEN_INT ((~INTVAL (x
)) & 0xff));
270 /* For shift counts. The hardware ignores the upper bits of
271 any immediate, but the assembler will flag an out of range
272 shift count as an error. So we mask off the high bits
273 of the immediate here. */
275 if (GET_CODE (x
) == CONST_INT
)
277 fprintf (file
, "%d", INTVAL (x
) & 0x1f);
283 switch (GET_CODE (x
))
287 output_address (XEXP (x
, 0));
296 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
300 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
303 /* This will only be single precision.... */
309 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
310 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
311 fprintf (file
, "0x%lx", val
);
320 print_operand_address (file
, x
);
329 /* Output assembly language output for the address ADDR to FILE. */
332 print_operand_address (file
, addr
)
336 switch (GET_CODE (addr
))
339 print_operand_address (file
, XEXP (addr
, 0));
343 print_operand (file
, addr
, 0);
348 if (REG_P (XEXP (addr
, 0))
349 && REG_OK_FOR_BASE_P (XEXP (addr
, 0)))
350 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
351 else if (REG_P (XEXP (addr
, 1))
352 && REG_OK_FOR_BASE_P (XEXP (addr
, 1)))
353 base
= XEXP (addr
, 1), index
= XEXP (addr
, 0);
356 print_operand (file
, index
, 0);
358 print_operand (file
, base
, 0);;
362 output_addr_const (file
, addr
);
365 output_addr_const (file
, addr
);
370 /* Print a set of registers in the format required by "movm" and "ret".
371 Register K is saved if bit K of MASK is set. The data and address
372 registers can be stored individually, but the extended registers cannot.
373 We assume that the mask alread takes that into account. For instance,
374 bits 14 to 17 must have the same value. */
377 mn10300_print_reg_list (file
, mask
)
387 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
388 if ((mask
& (1 << i
)) != 0)
392 fputs (reg_names
[i
], file
);
396 if ((mask
& 0x3c000) != 0)
398 if ((mask
& 0x3c000) != 0x3c000)
402 fputs ("exreg1", file
);
410 can_use_return_insn ()
412 /* size includes the fixed stack space needed for function calls. */
413 int size
= get_frame_size () + current_function_outgoing_args_size
;
415 /* And space for the return pointer. */
416 size
+= current_function_outgoing_args_size
? 4 : 0;
418 return (reload_completed
420 && !regs_ever_live
[2]
421 && !regs_ever_live
[3]
422 && !regs_ever_live
[6]
423 && !regs_ever_live
[7]
424 && !regs_ever_live
[14]
425 && !regs_ever_live
[15]
426 && !regs_ever_live
[16]
427 && !regs_ever_live
[17]
428 && !frame_pointer_needed
);
431 /* Returns the set of live, callee-saved registers as a bitmask. The
432 callee-saved extended registers cannot be stored individually, so
433 all of them will be included in the mask if any one of them is used. */
436 mn10300_get_live_callee_saved_regs ()
442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
443 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
445 if ((mask
& 0x3c000) != 0)
451 /* Generate an instruction that pushes several registers onto the stack.
452 Register K will be saved if bit K in MASK is set. The function does
453 nothing if MASK is zero.
455 To be compatible with the "movm" instruction, the lowest-numbered
456 register must be stored in the lowest slot. If MASK is the set
457 { R1,...,RN }, where R1...RN are ordered least first, the generated
458 instruction will have the form:
461 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
462 (set (mem:SI (plus:SI (reg:SI 9)
466 (set (mem:SI (plus:SI (reg:SI 9)
471 mn10300_gen_multiple_store (mask
)
481 /* Count how many registers need to be saved. */
483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
484 if ((mask
& (1 << i
)) != 0)
487 /* We need one PARALLEL element to update the stack pointer and
488 an additional element for each register that is stored. */
489 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
+ 1));
491 /* Create the instruction that updates the stack pointer. */
493 = gen_rtx_SET (SImode
,
495 gen_rtx_PLUS (SImode
,
497 GEN_INT (-count
* 4)));
499 /* Create each store. */
501 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
502 if ((mask
& (1 << i
)) != 0)
504 rtx address
= gen_rtx_PLUS (SImode
,
506 GEN_INT (-pari
* 4));
507 XVECEXP(par
, 0, pari
)
508 = gen_rtx_SET (VOIDmode
,
509 gen_rtx_MEM (SImode
, address
),
510 gen_rtx_REG (SImode
, i
));
514 par
= emit_insn (par
);
515 RTX_FRAME_RELATED_P (par
) = 1;
524 /* SIZE includes the fixed stack space needed for function calls. */
525 size
= get_frame_size () + current_function_outgoing_args_size
;
526 size
+= (current_function_outgoing_args_size
? 4 : 0);
528 /* If we use any of the callee-saved registers, save them now. */
529 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
531 /* Now put the frame pointer into the frame pointer register. */
532 if (frame_pointer_needed
)
533 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
535 /* Allocate stack for this frame. */
537 emit_insn (gen_addsi3 (stack_pointer_rtx
,
547 /* SIZE includes the fixed stack space needed for function calls. */
548 size
= get_frame_size () + current_function_outgoing_args_size
;
549 size
+= (current_function_outgoing_args_size
? 4 : 0);
551 /* Maybe cut back the stack, except for the register save area.
553 If the frame pointer exists, then use the frame pointer to
556 If the stack size + register save area is more than 255 bytes,
557 then the stack must be cut back here since the size + register
558 save size is too big for a ret/retf instruction.
560 Else leave it alone, it will be cut back as part of the
561 ret/retf instruction, or there wasn't any stack to begin with.
563 Under no circumstanes should the register save area be
564 deallocated here, that would leave a window where an interrupt
565 could occur and trash the register save area. */
566 if (frame_pointer_needed
)
568 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
571 else if (size
+ REG_SAVE_BYTES
> 255)
573 emit_insn (gen_addsi3 (stack_pointer_rtx
,
579 /* Adjust the stack and restore callee-saved registers, if any. */
580 if (size
|| regs_ever_live
[2] || regs_ever_live
[3]
581 || regs_ever_live
[6] || regs_ever_live
[7]
582 || regs_ever_live
[14] || regs_ever_live
[15]
583 || regs_ever_live
[16] || regs_ever_live
[17]
584 || frame_pointer_needed
)
585 emit_jump_insn (gen_return_internal_regs
586 (GEN_INT (size
+ REG_SAVE_BYTES
)));
588 emit_jump_insn (gen_return_internal ());
591 /* Update the condition code from the insn. */
594 notice_update_cc (body
, insn
)
598 switch (get_attr_cc (insn
))
601 /* Insn does not affect CC at all. */
605 /* Insn does not change CC, but the 0'th operand has been changed. */
606 if (cc_status
.value1
!= 0
607 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
608 cc_status
.value1
= 0;
612 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
615 cc_status
.flags
|= CC_NO_CARRY
| CC_OVERFLOW_UNUSABLE
;
616 cc_status
.value1
= recog_data
.operand
[0];
620 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
623 cc_status
.flags
|= CC_NO_CARRY
;
624 cc_status
.value1
= recog_data
.operand
[0];
628 /* The insn is a compare instruction. */
630 cc_status
.value1
= SET_SRC (body
);
634 /* The insn is a compare instruction. */
636 cc_status
.value1
= SET_SRC (body
);
637 cc_status
.flags
|= CC_INVERTED
;
641 /* Insn doesn't leave CC in a usable state. */
650 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
651 This function is for MATCH_PARALLEL and so assumes OP is known to be
652 parallel. If OP is a multiple store, return a mask indicating which
653 registers it saves. Return 0 otherwise. */
656 store_multiple_operation (op
, mode
)
658 enum machine_mode mode ATTRIBUTE_UNUSED
;
666 count
= XVECLEN (op
, 0);
670 /* Check that first instruction has the form (set (sp) (plus A B)) */
671 elt
= XVECEXP (op
, 0, 0);
672 if (GET_CODE (elt
) != SET
673 || GET_CODE (SET_DEST (elt
)) != REG
674 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
675 || GET_CODE (SET_SRC (elt
)) != PLUS
)
678 /* Check that A is the stack pointer and B is the expected stack size.
679 For OP to match, each subsequent instruction should push a word onto
680 the stack. We therefore expect the first instruction to create
681 COUNT-1 stack slots. */
683 if (GET_CODE (XEXP (elt
, 0)) != REG
684 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
685 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
686 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
689 /* Now go through the rest of the vector elements. They must be
690 ordered so that the first instruction stores the highest-numbered
691 register to the highest stack slot and that subsequent instructions
692 store a lower-numbered register to the slot below.
694 LAST keeps track of the smallest-numbered register stored so far.
695 MASK is the set of stored registers. */
696 last
= FIRST_PSEUDO_REGISTER
;
698 for (i
= 1; i
< count
; i
++)
700 /* Check that element i is a (set (mem M) R) and that R is valid. */
701 elt
= XVECEXP (op
, 0, i
);
702 if (GET_CODE (elt
) != SET
703 || GET_CODE (SET_DEST (elt
)) != MEM
704 || GET_CODE (SET_SRC (elt
)) != REG
705 || REGNO (SET_SRC (elt
)) >= last
)
708 /* R was OK, so provisionally add it to MASK. We return 0 in any
709 case if the rest of the instruction has a flaw. */
710 last
= REGNO (SET_SRC (elt
));
713 /* Check that M has the form (plus (sp) (const_int -I*4)) */
714 elt
= XEXP (SET_DEST (elt
), 0);
715 if (GET_CODE (elt
) != PLUS
716 || GET_CODE (XEXP (elt
, 0)) != REG
717 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
718 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
719 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
723 /* All or none of the callee-saved extended registers must be in the set. */
724 if ((mask
& 0x3c000) != 0
725 && (mask
& 0x3c000) != 0x3c000)
731 /* Return true if OP is a valid call operand. */
734 call_address_operand (op
, mode
)
736 enum machine_mode mode ATTRIBUTE_UNUSED
;
738 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
);
741 /* What (if any) secondary registers are needed to move IN with mode
742 MODE into a register in register class CLASS.
744 We might be able to simplify this. */
746 secondary_reload_class (class, mode
, in
)
747 enum reg_class
class;
748 enum machine_mode mode
;
751 /* Memory loads less than a full word wide can't have an
752 address or stack pointer destination. They must use
753 a data register as an intermediate register. */
754 if ((GET_CODE (in
) == MEM
755 || (GET_CODE (in
) == REG
756 && REGNO (in
) >= FIRST_PSEUDO_REGISTER
)
757 || (GET_CODE (in
) == SUBREG
758 && GET_CODE (SUBREG_REG (in
)) == REG
759 && REGNO (SUBREG_REG (in
)) >= FIRST_PSEUDO_REGISTER
))
760 && (mode
== QImode
|| mode
== HImode
)
761 && (class == ADDRESS_REGS
|| class == SP_REGS
762 || class == SP_OR_ADDRESS_REGS
))
765 return DATA_OR_EXTENDED_REGS
;
769 /* We can't directly load sp + const_int into a data register;
770 we must use an address register as an intermediate. */
772 && class != ADDRESS_REGS
773 && class != SP_OR_ADDRESS_REGS
774 && class != SP_OR_EXTENDED_REGS
775 && class != ADDRESS_OR_EXTENDED_REGS
776 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
777 && (in
== stack_pointer_rtx
778 || (GET_CODE (in
) == PLUS
779 && (XEXP (in
, 0) == stack_pointer_rtx
780 || XEXP (in
, 1) == stack_pointer_rtx
))))
783 if (GET_CODE (in
) == PLUS
784 && (XEXP (in
, 0) == stack_pointer_rtx
785 || XEXP (in
, 1) == stack_pointer_rtx
))
788 return DATA_OR_EXTENDED_REGS
;
792 /* Otherwise assume no secondary reloads are needed. */
797 initial_offset (from
, to
)
800 /* The difference between the argument pointer and the frame pointer
801 is the size of the callee register save area. */
802 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
804 if (regs_ever_live
[2] || regs_ever_live
[3]
805 || regs_ever_live
[6] || regs_ever_live
[7]
806 || regs_ever_live
[14] || regs_ever_live
[15]
807 || regs_ever_live
[16] || regs_ever_live
[17]
808 || frame_pointer_needed
)
809 return REG_SAVE_BYTES
;
814 /* The difference between the argument pointer and the stack pointer is
815 the sum of the size of this function's frame, the callee register save
816 area, and the fixed stack space needed for function calls (if any). */
817 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
819 if (regs_ever_live
[2] || regs_ever_live
[3]
820 || regs_ever_live
[6] || regs_ever_live
[7]
821 || regs_ever_live
[14] || regs_ever_live
[15]
822 || regs_ever_live
[16] || regs_ever_live
[17]
823 || frame_pointer_needed
)
824 return (get_frame_size () + REG_SAVE_BYTES
825 + (current_function_outgoing_args_size
826 ? current_function_outgoing_args_size
+ 4 : 0));
828 return (get_frame_size ()
829 + (current_function_outgoing_args_size
830 ? current_function_outgoing_args_size
+ 4 : 0));
833 /* The difference between the frame pointer and stack pointer is the sum
834 of the size of this function's frame and the fixed stack space needed
835 for function calls (if any). */
836 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
837 return (get_frame_size ()
838 + (current_function_outgoing_args_size
839 ? current_function_outgoing_args_size
+ 4 : 0));
844 /* Flush the argument registers to the stack for a stdarg function;
845 return the new argument pointer. */
847 mn10300_builtin_saveregs ()
850 tree fntype
= TREE_TYPE (current_function_decl
);
851 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
852 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
854 ? UNITS_PER_WORD
: 0);
855 int set
= get_varargs_alias_set ();
858 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
860 offset
= current_function_arg_offset_rtx
;
862 mem
= gen_rtx_MEM (SImode
, current_function_internal_arg_pointer
);
863 set_mem_alias_set (mem
, set
);
864 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
866 mem
= gen_rtx_MEM (SImode
,
867 plus_constant (current_function_internal_arg_pointer
, 4));
868 set_mem_alias_set (mem
, set
);
869 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
871 return copy_to_reg (expand_binop (Pmode
, add_optab
,
872 current_function_internal_arg_pointer
,
873 offset
, 0, 0, OPTAB_LIB_WIDEN
));
877 mn10300_va_start (valist
, nextarg
)
881 nextarg
= expand_builtin_saveregs ();
882 std_expand_builtin_va_start (valist
, nextarg
);
886 mn10300_va_arg (valist
, type
)
889 HOST_WIDE_INT align
, rsize
;
892 /* Compute the rounded size of the type. */
893 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
894 rsize
= (((int_size_in_bytes (type
) + align
- 1) / align
) * align
);
896 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (valist
), valist
,
897 build_int_2 ((rsize
> 8 ? 4 : rsize
), 0));
898 TREE_SIDE_EFFECTS (t
) = 1;
900 ptr
= build_pointer_type (type
);
902 /* "Large" types are passed by reference. */
905 pptr
= build_pointer_type (ptr
);
906 t
= build1 (NOP_EXPR
, pptr
, t
);
907 TREE_SIDE_EFFECTS (t
) = 1;
909 t
= build1 (INDIRECT_REF
, ptr
, t
);
910 TREE_SIDE_EFFECTS (t
) = 1;
914 t
= build1 (NOP_EXPR
, ptr
, t
);
915 TREE_SIDE_EFFECTS (t
) = 1;
919 return expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
922 /* Return an RTX to represent where a value with mode MODE will be returned
923 from a function. If the result is 0, the argument is pushed. */
926 function_arg (cum
, mode
, type
, named
)
927 CUMULATIVE_ARGS
*cum
;
928 enum machine_mode mode
;
930 int named ATTRIBUTE_UNUSED
;
935 /* We only support using 2 data registers as argument registers. */
938 /* Figure out the size of the object to be passed. */
940 size
= int_size_in_bytes (type
);
942 size
= GET_MODE_SIZE (mode
);
944 /* Figure out the alignment of the object to be passed. */
947 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
949 /* Don't pass this arg via a register if all the argument registers
951 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
954 /* Don't pass this arg via a register if it would be split between
955 registers and memory. */
956 if (type
== NULL_TREE
957 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
960 switch (cum
->nbytes
/ UNITS_PER_WORD
)
963 result
= gen_rtx_REG (mode
, 0);
966 result
= gen_rtx_REG (mode
, 1);
975 /* Return the number of registers to use for an argument passed partially
976 in registers and partially in memory. */
979 function_arg_partial_nregs (cum
, mode
, type
, named
)
980 CUMULATIVE_ARGS
*cum
;
981 enum machine_mode mode
;
983 int named ATTRIBUTE_UNUSED
;
987 /* We only support using 2 data registers as argument registers. */
990 /* Figure out the size of the object to be passed. */
992 size
= int_size_in_bytes (type
);
994 size
= GET_MODE_SIZE (mode
);
996 /* Figure out the alignment of the object to be passed. */
999 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1001 /* Don't pass this arg via a register if all the argument registers
1003 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1006 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1009 /* Don't pass this arg via a register if it would be split between
1010 registers and memory. */
1011 if (type
== NULL_TREE
1012 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1015 return (nregs
* UNITS_PER_WORD
- cum
->nbytes
) / UNITS_PER_WORD
;
1018 /* Output a tst insn. */
1020 output_tst (operand
, insn
)
1026 /* We can save a byte if we can find a register which has the value
1028 temp
= PREV_INSN (insn
);
1029 while (optimize
&& temp
)
1033 /* We allow the search to go through call insns. We record
1034 the fact that we've past a CALL_INSN and reject matches which
1035 use call clobbered registers. */
1036 if (GET_CODE (temp
) == CODE_LABEL
1037 || GET_CODE (temp
) == JUMP_INSN
1038 || GET_CODE (temp
) == BARRIER
)
1041 if (GET_CODE (temp
) == CALL_INSN
)
1044 if (GET_CODE (temp
) == NOTE
)
1046 temp
= PREV_INSN (temp
);
1050 /* It must be an insn, see if it is a simple set. */
1051 set
= single_set (temp
);
1054 temp
= PREV_INSN (temp
);
1058 /* Are we setting a data register to zero (this does not win for
1061 If it's a call clobbered register, have we past a call?
1063 Make sure the register we find isn't the same as ourself;
1064 the mn10300 can't encode that.
1066 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1067 so the code to detect calls here isn't doing anything useful. */
1068 if (REG_P (SET_DEST (set
))
1069 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1070 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1071 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1072 == REGNO_REG_CLASS (REGNO (operand
)))
1073 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) != EXTENDED_REGS
1074 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1076 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1079 xoperands
[0] = operand
;
1080 xoperands
[1] = SET_DEST (set
);
1082 output_asm_insn ("cmp %1,%0", xoperands
);
1086 if (REGNO_REG_CLASS (REGNO (operand
)) == EXTENDED_REGS
1087 && REG_P (SET_DEST (set
))
1088 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1089 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1090 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1091 != REGNO_REG_CLASS (REGNO (operand
)))
1092 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) == EXTENDED_REGS
1093 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1095 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1098 xoperands
[0] = operand
;
1099 xoperands
[1] = SET_DEST (set
);
1101 output_asm_insn ("cmp %1,%0", xoperands
);
1104 temp
= PREV_INSN (temp
);
1110 impossible_plus_operand (op
, mode
)
1112 enum machine_mode mode ATTRIBUTE_UNUSED
;
1114 if (GET_CODE (op
) != PLUS
)
1117 if (XEXP (op
, 0) == stack_pointer_rtx
1118 || XEXP (op
, 1) == stack_pointer_rtx
)
1124 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1125 for the btst insn which may examine memory or a register (the memory
1126 variant only allows an unsigned 8 bit integer). */
1128 const_8bit_operand (op
, mode
)
1130 enum machine_mode mode ATTRIBUTE_UNUSED
;
1132 return (GET_CODE (op
) == CONST_INT
1134 && INTVAL (op
) < 256);
1137 /* Similarly, but when using a zero_extract pattern for a btst where
1138 the source operand might end up in memory. */
1140 mask_ok_for_mem_btst (len
, bit
)
1153 /* MASK must bit into an 8bit value. */
1154 return (((mask
& 0xff) == mask
)
1155 || ((mask
& 0xff00) == mask
)
1156 || ((mask
& 0xff0000) == mask
)
1157 || ((mask
& 0xff000000) == mask
));
1160 /* Return 1 if X contains a symbolic expression. We know these
1161 expressions will have one of a few well defined forms, so
1162 we need only check those forms. */
1164 symbolic_operand (op
, mode
)
1166 enum machine_mode mode ATTRIBUTE_UNUSED
;
1168 switch (GET_CODE (op
))
1175 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1176 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1177 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1183 /* Try machine dependent ways of modifying an illegitimate address
1184 to be legitimate. If we find one, return the new valid address.
1185 This macro is used in only one place: `memory_address' in explow.c.
1187 OLDX is the address as it was before break_out_memory_refs was called.
1188 In some cases it is useful to look at this to decide what needs to be done.
1190 MODE and WIN are passed so that this macro can use
1191 GO_IF_LEGITIMATE_ADDRESS.
1193 Normally it is always safe for this macro to do nothing. It exists to
1194 recognize opportunities to optimize the output.
1196 But on a few ports with segmented architectures and indexed addressing
1197 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1199 legitimize_address (x
, oldx
, mode
)
1201 rtx oldx ATTRIBUTE_UNUSED
;
1202 enum machine_mode mode ATTRIBUTE_UNUSED
;
1204 /* Uh-oh. We might have an address for x[n-100000]. This needs
1205 special handling to avoid creating an indexed memory address
1206 with x-100000 as the base. */
1207 if (GET_CODE (x
) == PLUS
1208 && symbolic_operand (XEXP (x
, 1), VOIDmode
))
1210 /* Ugly. We modify things here so that the address offset specified
1211 by the index expression is computed first, then added to x to form
1212 the entire address. */
1214 rtx regx1
, regy1
, regy2
, y
;
1216 /* Strip off any CONST. */
1218 if (GET_CODE (y
) == CONST
)
1221 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1223 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1224 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1225 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1226 regx1
= force_reg (Pmode
,
1227 gen_rtx (GET_CODE (y
), Pmode
, regx1
, regy2
));
1228 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1235 mn10300_address_cost (x
, unsig
)
1243 switch (GET_CODE (x
))
1246 switch (REGNO_REG_CLASS (REGNO (x
)))
1271 return (mn10300_address_cost (XEXP (x
, 0), unsig
)
1272 + mn10300_address_cost (XEXP (x
, 1), unsig
));
1277 return ADDRESS_COST (XEXP (x
, 0));
1281 return mn10300_address_cost (XEXP (x
, 0), unsig
);
1284 if (INTVAL (x
) == 0)
1286 if (INTVAL (x
) + (*unsig
? 0 : 0x80) < 0x100)
1288 if (INTVAL (x
) + (*unsig
? 0 : 0x8000) < 0x10000)
1290 if (INTVAL (x
) + (*unsig
? 0 : 0x800000) < 0x1000000)
1300 switch (GET_CODE (XEXP (x
, 0)))
1303 return ADDRESS_COST (XEXP (x
, 0));