1 ;; AMD Athlon Scheduling
2 ;; Copyright (C) 2002 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA. */
20 (define_attr "athlon_decode" "direct,vector"
21 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
22 (const_string "vector")
23 (and (eq_attr "type" "push")
24 (match_operand 1 "memory_operand" ""))
25 (const_string "vector")
26 (and (eq_attr "type" "fmov")
27 (and (eq_attr "memory" "load,store")
28 (eq_attr "mode" "XF")))
29 (const_string "vector")]
30 (const_string "direct")))
32 ;; The Athlon does contain three pipelined FP units, three integer units and
33 ;; three address generation units.
35 ;; The predecode logic is determining boundaries of instructions in the 64
36 ;; byte cache line. So the cache line straddling problem of K6 might be issue
37 ;; here as well, but it is not noted in the documentation.
39 ;; Three DirectPath instructions decoders and only one VectorPath decoder
40 ;; is available. They can decode three DirectPath instructions or one VectorPath
41 ;; instruction per cycle.
42 ;; Decoded macro instructions are then passed to 72 entry instruction control
44 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
46 ;; The load/store queue unit is not attached to the schedulers but
47 ;; communicates with all the execution units separately instead.
49 (define_function_unit "athlon_vectordec" 1 0
50 (and (eq_attr "cpu" "athlon")
51 (eq_attr "athlon_decode" "vector"))
54 (define_function_unit "athlon_directdec" 3 0
55 (and (eq_attr "cpu" "athlon")
56 (eq_attr "athlon_decode" "direct"))
59 (define_function_unit "athlon_vectordec" 1 0
60 (and (eq_attr "cpu" "athlon")
61 (eq_attr "athlon_decode" "direct"))
62 1 1 [(eq_attr "athlon_decode" "vector")])
64 (define_function_unit "athlon_ieu" 3 0
65 (and (eq_attr "cpu" "athlon")
66 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,rotate,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
69 (define_function_unit "athlon_ieu" 3 0
70 (and (eq_attr "cpu" "athlon")
71 (eq_attr "type" "str"))
74 (define_function_unit "athlon_ieu" 3 0
75 (and (eq_attr "cpu" "athlon")
76 (eq_attr "type" "imul"))
79 (define_function_unit "athlon_ieu" 3 0
80 (and (eq_attr "cpu" "athlon")
81 (eq_attr "type" "idiv"))
84 (define_function_unit "athlon_muldiv" 1 0
85 (and (eq_attr "cpu" "athlon")
86 (eq_attr "type" "imul"))
89 (define_function_unit "athlon_muldiv" 1 0
90 (and (eq_attr "cpu" "athlon")
91 (eq_attr "type" "idiv"))
94 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
95 (cond [(eq_attr "type" "fop,fcmp,fistp")
97 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
99 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
100 (const_string "store")
101 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
103 (and (eq_attr "type" "fmov")
104 (ior (match_operand:SI 1 "register_operand" "")
105 (match_operand 1 "immediate_operand" "")))
106 (const_string "store")
107 (eq_attr "type" "fmov")
108 (const_string "muladd")]
109 (const_string "none")))
111 ;; We use latencies 1 for definitions. This is OK to model colisions
112 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
114 ;; fsin, fcos: 96-192
116 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
117 (define_function_unit "athlon_fp" 3 0
118 (and (eq_attr "cpu" "athlon")
119 (eq_attr "type" "fpspc"))
122 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
123 (define_function_unit "athlon_fp" 3 0
124 (and (eq_attr "cpu" "athlon")
125 (eq_attr "type" "fdiv"))
128 (define_function_unit "athlon_fp" 3 0
129 (and (eq_attr "cpu" "athlon")
130 (eq_attr "type" "fop,fmul,fistp"))
133 ;; XFmode loads are slow.
134 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
135 ;; there are no dependent instructions.
137 (define_function_unit "athlon_fp" 3 0
138 (and (eq_attr "cpu" "athlon")
139 (and (eq_attr "type" "fmov")
140 (and (eq_attr "memory" "load")
141 (eq_attr "mode" "XF"))))
144 (define_function_unit "athlon_fp" 3 0
145 (and (eq_attr "cpu" "athlon")
146 (eq_attr "type" "fmov,fsgn"))
149 ;; fcmp and ftst instructions
150 (define_function_unit "athlon_fp" 3 0
151 (and (eq_attr "cpu" "athlon")
152 (and (eq_attr "type" "fcmp")
153 (eq_attr "athlon_decode" "direct")))
156 ;; fcmpi instructions.
157 (define_function_unit "athlon_fp" 3 0
158 (and (eq_attr "cpu" "athlon")
159 (and (eq_attr "type" "fcmp")
160 (eq_attr "athlon_decode" "vector")))
163 (define_function_unit "athlon_fp" 3 0
164 (and (eq_attr "cpu" "athlon")
165 (eq_attr "type" "fcmov"))
168 (define_function_unit "athlon_fp_mul" 1 0
169 (and (eq_attr "cpu" "athlon")
170 (eq_attr "athlon_fpunits" "mul"))
173 (define_function_unit "athlon_fp_add" 1 0
174 (and (eq_attr "cpu" "athlon")
175 (eq_attr "athlon_fpunits" "add"))
178 (define_function_unit "athlon_fp_muladd" 2 0
179 (and (eq_attr "cpu" "athlon")
180 (eq_attr "athlon_fpunits" "muladd,mul,add"))
183 (define_function_unit "athlon_fp_store" 1 0
184 (and (eq_attr "cpu" "athlon")
185 (eq_attr "athlon_fpunits" "store"))
188 ;; We don't need to model the Address Generation Unit, since we don't model
189 ;; the re-order buffer yet and thus we never schedule more than three operations
190 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
191 ;; decoders independently on the functional units.
193 ;(define_function_unit "athlon_agu" 3 0
194 ; (and (eq_attr "cpu" "athlon")
195 ; (and (eq_attr "memory" "!none")
196 ; (eq_attr "athlon_fpunits" "none")))
199 ;; Model load unit to avoid too long sequences of loads. We don't need to
200 ;; model store queue, since it is hardly going to be bottleneck.
202 (define_function_unit "athlon_load" 2 0
203 (and (eq_attr "cpu" "athlon")
204 (eq_attr "memory" "load,both"))