1 ;; GCC machine description for Hitachi H8/300
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Steve Chamberlain (sac@cygnus.com),
6 ;; Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; Some of the extend instructions accept a general_operand_src, which
26 ;; allows all the normal memory addressing modes. The length computations
27 ;; don't take this into account. The lengths in the MD file should be
28 ;; "worst case" and then be adjusted to their correct values by
29 ;; h8300_adjust_insn_length.
31 ;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
32 ;; registers. Right now GCC doesn't expose the "e" half to the
33 ;; compiler, so using add/subs for addhi and subhi is safe. Long
34 ;; term, we want to expose the "e" half to the compiler (gives us 8
35 ;; more 16bit registers). At that point addhi and subhi can't use
38 ;; There's currently no way to have a insv/extzv expander for the H8/300H
39 ;; because word_mode is different for the H8/300 and H8/300H.
41 ;; Shifts/rotates by small constants should be handled by special
42 ;; patterns so we get the length and cc status correct.
44 ;; Bitfield operations no longer accept memory operands. We need
45 ;; to add variants which operate on memory back to the MD.
47 ;; ??? Implement remaining bit ops available on the h8300
49 ;; ----------------------------------------------------------------------
51 ;; ----------------------------------------------------------------------
61 ;; ----------------------------------------------------------------------
63 ;; ----------------------------------------------------------------------
65 (define_attr "cpu" "h8300,h8300h"
66 (const (symbol_ref "cpu_type")))
68 (define_attr "type" "branch,arith"
69 (const_string "arith"))
71 ;; The size of instructions in bytes.
73 (define_attr "length" ""
74 (cond [(eq_attr "type" "branch")
75 (if_then_else (and (ge (minus (match_dup 0) (pc))
77 (le (minus (match_dup 0) (pc))
80 (if_then_else (and (eq_attr "cpu" "h8300h")
81 (and (ge (minus (pc) (match_dup 0))
83 (le (minus (pc) (match_dup 0))
89 ;; The necessity of instruction length adjustment.
91 (define_attr "adjust_length" "yes,no"
92 (cond [(eq_attr "type" "branch") (const_string "no")]
93 (const_string "yes")))
95 ;; Condition code settings.
97 ;; none - insn does not affect cc
98 ;; none_0hit - insn does not affect cc but it does modify operand 0
99 ;; This attribute is used to keep track of when operand 0 changes.
100 ;; See the description of NOTICE_UPDATE_CC for more info.
101 ;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
102 ;; set_zn - insn sets z,n to usable values; v,c are unknown.
103 ;; compare - compare instruction
104 ;; clobber - value of cc is unknown
106 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
107 (const_string "clobber"))
109 ;; ----------------------------------------------------------------------
111 ;; ----------------------------------------------------------------------
115 (define_insn "pushqi1_h8300"
116 [(parallel [(set (reg:HI SP_REG)
117 (plus:HI (reg:HI SP_REG) (const_int -2)))
118 (set (mem:QI (plus:HI (reg:HI SP_REG) (const_int -1)))
119 (match_operand:QI 0 "register_operand" "r"))])]
122 [(set_attr "length" "2")
123 (set_attr "cc" "clobber")])
125 (define_insn "pushqi1_h8300hs"
126 [(parallel [(set (reg:SI SP_REG)
127 (plus:SI (reg:SI SP_REG) (const_int -4)))
128 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int -3)))
129 (match_operand:QI 0 "register_operand" "r"))])]
130 "TARGET_H8300H || TARGET_H8300S"
132 [(set_attr "length" "4")
133 (set_attr "cc" "clobber")])
135 (define_expand "pushqi1"
136 [(use (match_operand:QI 0 "register_operand" ""))]
141 emit_insn (gen_pushqi1_h8300 (operands[0]));
143 emit_insn (gen_pushqi1_h8300hs (operands[0]));
148 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
149 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
151 && (register_operand (operands[0], QImode)
152 || register_operand (operands[1], QImode))"
160 [(set_attr "length" "2,2,2,2,4,4")
161 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
164 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
165 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
166 "(TARGET_H8300H || TARGET_H8300S)
167 && (register_operand (operands[0], QImode)
168 || register_operand (operands[1], QImode))"
176 [(set_attr "length" "2,2,2,2,8,8")
177 (set_attr "cc" "set_zn,set_znv,set_znv,clobber,set_znv,set_znv")])
179 (define_expand "movqi"
180 [(set (match_operand:QI 0 "general_operand_dst" "")
181 (match_operand:QI 1 "general_operand_src" ""))]
185 /* One of the ops has to be in a register. */
186 if (!register_operand (operand0, QImode)
187 && !register_operand (operand1, QImode))
189 operands[1] = copy_to_mode_reg (QImode, operand1);
193 (define_insn "movstrictqi"
194 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r,r,r"))
195 (match_operand:QI 1 "general_operand_src" "I,r,n,m"))]
202 [(set_attr_alternative "length"
203 [(const_int 2) (const_int 2) (const_int 2)
204 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
205 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
209 (define_expand "pushhi1_h8300"
210 [(set (mem:HI (pre_dec:HI (reg:HI SP_REG)))
211 (match_operand:HI 0 "register_operand" ""))]
215 (define_insn "pushhi1_h8300hs"
216 [(parallel [(set (reg:SI SP_REG)
217 (plus:SI (reg:SI SP_REG) (const_int -4)))
218 (set (mem:HI (plus:SI (reg:SI SP_REG) (const_int -2)))
219 (match_operand:HI 0 "register_operand" "r"))])]
220 "TARGET_H8300H || TARGET_H8300S"
222 [(set_attr "length" "4")
223 (set_attr "cc" "clobber")])
225 (define_expand "pushhi1"
226 [(use (match_operand:HI 0 "register_operand" ""))]
231 emit_insn (gen_pushhi1_h8300 (operands[0]));
233 emit_insn (gen_pushhi1_h8300hs (operands[0]));
238 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
239 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
241 && (register_operand (operands[0], HImode)
242 || register_operand (operands[1], HImode))
243 && !(GET_CODE (operands[0]) == MEM
244 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
245 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
246 && GET_CODE (operands[1]) == REG
247 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
255 [(set_attr "length" "2,2,2,4,4,4")
256 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
259 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
260 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
261 "(TARGET_H8300H || TARGET_H8300S)
262 && (register_operand (operands[0], HImode)
263 || register_operand (operands[1], HImode))"
271 [(set_attr "length" "2,2,2,4,8,8")
272 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
274 (define_expand "movhi"
275 [(set (match_operand:HI 0 "general_operand_dst" "")
276 (match_operand:HI 1 "general_operand_src" ""))]
280 /* One of the ops has to be in a register. */
281 if (!register_operand (operand1, HImode)
282 && !register_operand (operand0, HImode))
284 operands[1] = copy_to_mode_reg (HImode, operand1);
288 (define_insn "movstricthi"
289 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r,r"))
290 (match_operand:HI 1 "general_operand_src" "I,r,i,m"))]
297 [(set_attr_alternative "length"
298 [(const_int 2) (const_int 2) (const_int 4)
299 (if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
300 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
304 (define_expand "movsi"
305 [(set (match_operand:SI 0 "general_operand_dst" "")
306 (match_operand:SI 1 "general_operand_src" ""))]
312 if (do_movsi (operands))
317 /* One of the ops has to be in a register. */
318 if (!register_operand (operand1, SImode)
319 && !register_operand (operand0, SImode))
321 operands[1] = copy_to_mode_reg (SImode, operand1);
326 (define_expand "movsf"
327 [(set (match_operand:SF 0 "general_operand_dst" "")
328 (match_operand:SF 1 "general_operand_src" ""))]
334 if (do_movsi (operands))
339 /* One of the ops has to be in a register. */
340 if (!register_operand (operand1, SFmode)
341 && !register_operand (operand0, SFmode))
343 operands[1] = copy_to_mode_reg (SFmode, operand1);
348 (define_insn "movsi_h8300"
349 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,o,<,r")
350 (match_operand:SI 1 "general_operand_src" "I,r,io,r,r,>"))]
352 && (register_operand (operands[0], SImode)
353 || register_operand (operands[1], SImode))"
357 switch (which_alternative)
360 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
362 if (REGNO (operands[0]) < REGNO (operands[1]))
363 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
365 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
367 /* Make sure we don't trample the register we index with. */
368 if (GET_CODE (operands[1]) == MEM)
370 rtx inside = XEXP (operands[1], 0);
375 else if (GET_CODE (inside) == PLUS)
377 rtx lhs = XEXP (inside, 0);
378 rtx rhs = XEXP (inside, 1);
379 if (REG_P (lhs)) rn = REGNO (lhs);
380 if (REG_P (rhs)) rn = REGNO (rhs);
383 if (rn == REGNO (operands[0]))
385 /* Move the second word first. */
386 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
390 /* See if either half is zero. If so, use sub.w to clear
392 if (GET_CODE (operands[1]) == CONST_INT)
394 if ((INTVAL (operands[1]) & 0xffff) == 0)
395 return \"mov.w %e1,%e0\;sub.w %f0,%f0\";
396 if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
397 return \"sub.w %e0,%e0\;mov.w %f1,%f0\";
399 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
402 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
404 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
406 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
411 [(set_attr "length" "4,4,8,8,4,4")
412 (set_attr "cc" "clobber")])
414 (define_insn "movsf_h8300"
415 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,o,<,r")
416 (match_operand:SF 1 "general_operand_src" "I,r,io,r,r,>"))]
418 && (register_operand (operands[0], SFmode)
419 || register_operand (operands[1], SFmode))"
422 /* Copy of the movsi stuff. */
424 switch (which_alternative)
427 return \"sub.w %e0,%e0\;sub.w %f0,%f0\";
429 if (REGNO (operands[0]) < REGNO (operands[1]))
430 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
432 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
434 /* Make sure we don't trample the register we index with. */
435 if (GET_CODE (operands[1]) == MEM)
437 rtx inside = XEXP (operands[1], 0);
442 else if (GET_CODE (inside) == PLUS)
444 rtx lhs = XEXP (inside, 0);
445 rtx rhs = XEXP (inside, 1);
446 if (REG_P (lhs)) rn = REGNO (lhs);
447 if (REG_P (rhs)) rn = REGNO (rhs);
450 if (rn == REGNO (operands[0]))
451 /* Move the second word first. */
452 return \"mov.w %f1,%f0\;mov.w %e1,%e0\";
454 /* Move the first word first. */
455 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
458 return \"mov.w %e1,%e0\;mov.w %f1,%f0\";
460 return \"mov.w %f1,%T0\;mov.w %e1,%T0\";
462 return \"mov.w %T1,%e0\;mov.w %T1,%f0\";
467 [(set_attr "length" "4,4,8,8,4,4")
468 (set_attr "cc" "clobber")])
470 (define_insn "movsi_h8300hs"
471 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,r,m,<,r,*a,*a,r")
472 (match_operand:SI 1 "general_operand_src" "I,r,i,m,r,r,>,I,r,*a"))]
473 "(TARGET_H8300S || TARGET_H8300H)
474 && (register_operand (operands[0], SImode)
475 || register_operand (operands[1], SImode))
476 && !(GET_CODE (operands[0]) == MEM
477 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
478 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
479 && GET_CODE (operands[1]) == REG
480 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == REGNO (operands[1]))"
483 switch (which_alternative)
486 return \"sub.l %S0,%S0\";
490 return \"clrmac\;ldmac %1,macl\";
492 return \"stmac macl,%0\";
494 if (GET_CODE (operands[1]) == CONST_INT)
496 int val = INTVAL (operands[1]);
498 /* Look for constants which can be made by adding an 8-bit
499 number to zero in one of the two low bytes. */
500 if (val == (val & 0xff))
502 operands[1] = GEN_INT ((char) val & 0xff);
503 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%w0\";
506 if (val == (val & 0xff00))
508 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
509 return \"sub.l\\t%S0,%S0\;add.b\\t%1,%x0\";
512 /* Look for constants that can be obtained by subs, inc, and
514 switch (val & 0xffffffff)
517 return \"sub.l\\t%S0,%S0\;subs\\t#1,%S0\";
519 return \"sub.l\\t%S0,%S0\;subs\\t#2,%S0\";
521 return \"sub.l\\t%S0,%S0\;subs\\t#4,%S0\";
524 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%f0\";
526 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%f0\";
529 return \"sub.l\\t%S0,%S0\;dec.w\\t#1,%e0\";
531 return \"sub.l\\t%S0,%S0\;dec.w\\t#2,%e0\";
534 return \"sub.l\\t%S0,%S0\;inc.w\\t#1,%e0\";
536 return \"sub.l\\t%S0,%S0\;inc.w\\t#2,%e0\";
540 return \"mov.l %S1,%S0\";
542 [(set_attr "length" "2,2,6,10,10,4,4,2,6,4")
543 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
545 (define_insn "movsf_h8300h"
546 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
547 (match_operand:SF 1 "general_operand_src" "I,r,im,r,r,>"))]
548 "(TARGET_H8300H || TARGET_H8300S)
549 && (register_operand (operands[0], SFmode)
550 || register_operand (operands[1], SFmode))"
558 [(set_attr "length" "2,2,10,10,4,4")
559 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
561 ;; ----------------------------------------------------------------------
563 ;; ----------------------------------------------------------------------
566 [(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "r,U")
568 (match_operand 1 "const_int_operand" "n,n")))]
571 [(set_attr "length" "2,4")
572 (set_attr "cc" "set_zn,set_zn")])
575 [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
577 (match_operand 1 "const_int_operand" "n")))]
580 [(set_attr "length" "2")
581 (set_attr "cc" "set_zn")])
584 [(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "r,U")
586 (match_operand 1 "const_int_operand" "n,n")))]
587 "TARGET_H8300H || TARGET_H8300S"
589 [(set_attr "length" "2,8")
590 (set_attr "cc" "set_zn,set_zn")])
593 [(set (cc0) (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
595 (match_operand 1 "const_int_operand" "n")))]
596 "(TARGET_H8300H || TARGET_H8300S)
597 && INTVAL (operands[1]) <= 15"
599 [(set_attr "length" "2")
600 (set_attr "cc" "set_zn")])
603 [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
606 [(set_attr "length" "2")
607 (set_attr "cc" "set_znv")])
610 [(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
613 [(set_attr "length" "2")
614 (set_attr "cc" "set_znv")])
617 [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
618 "TARGET_H8300H || TARGET_H8300S"
620 [(set_attr "length" "2")
621 (set_attr "cc" "set_znv")])
625 (compare:QI (match_operand:QI 0 "register_operand" "r")
626 (match_operand:QI 1 "nonmemory_operand" "rn")))]
629 [(set_attr "length" "2")
630 (set_attr "cc" "compare")])
632 (define_expand "cmphi"
634 (compare:HI (match_operand:HI 0 "register_operand" "")
635 (match_operand:HI 1 "nonmemory_operand" "")))]
639 /* Force operand1 into a register if we're compiling
641 if (GET_CODE (operands[1]) != REG && TARGET_H8300)
642 operands[1] = force_reg (HImode, operands[1]);
647 (compare:HI (match_operand:HI 0 "register_operand" "r")
648 (match_operand:HI 1 "register_operand" "r")))]
651 [(set_attr "length" "2")
652 (set_attr "cc" "compare")])
656 (compare:HI (match_operand:HI 0 "register_operand" "r,r")
657 (match_operand:HI 1 "nonmemory_operand" "r,n")))]
658 "TARGET_H8300H || TARGET_H8300S"
660 [(set_attr "length" "2,4")
661 (set_attr "cc" "compare,compare")])
665 (compare:SI (match_operand:SI 0 "register_operand" "r,r")
666 (match_operand:SI 1 "nonmemory_operand" "r,i")))]
667 "TARGET_H8300H || TARGET_H8300S"
669 [(set_attr "length" "2,6")
670 (set_attr "cc" "compare,compare")])
672 ;; ----------------------------------------------------------------------
674 ;; ----------------------------------------------------------------------
676 (define_insn "addqi3"
677 [(set (match_operand:QI 0 "register_operand" "=r")
678 (plus:QI (match_operand:QI 1 "register_operand" "%0")
679 (match_operand:QI 2 "nonmemory_operand" "rn")))]
682 [(set_attr "length" "2")
683 (set_attr "cc" "set_zn")])
685 (define_expand "addhi3"
686 [(set (match_operand:HI 0 "register_operand" "")
687 (plus:HI (match_operand:HI 1 "register_operand" "")
688 (match_operand:HI 2 "nonmemory_operand" "")))]
693 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,&r")
694 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,g")
695 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r,r")))]
700 add.b %s2,%s0\;addx %t2,%t0
702 mov.w %T1,%T0\;add.w %T2,%T0"
703 [(set_attr "length" "2,2,4,2,6")
704 (set_attr "cc" "none_0hit,none_0hit,clobber,set_zn,set_zn")])
707 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
708 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0")
709 (match_operand:HI 2 "nonmemory_operand" "L,N,n,r")))]
710 "TARGET_H8300H || TARGET_H8300S"
716 [(set_attr "length" "2,2,4,2")
717 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
720 [(set (match_operand:HI 0 "register_operand" "")
721 (plus:HI (match_dup 0)
722 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
725 "split_adds_subs (HImode, operands); DONE;")
727 (define_expand "addsi3"
728 [(set (match_operand:SI 0 "register_operand" "")
729 (plus:SI (match_operand:SI 1 "register_operand" "")
730 (match_operand:SI 2 "nonmemory_operand" "")))]
734 (define_insn "addsi_h8300"
735 [(set (match_operand:SI 0 "register_operand" "=r,r,&r")
736 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
737 (match_operand:SI 2 "nonmemory_operand" "n,r,r")))]
740 add %w2,%w0\;addx %x2,%x0\;addx %y2,%y0\;addx %z2,%z0
741 add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0
742 mov.w %f1,%f0\;mov.w %e1,%e0\;add.w %f2,%f0\;addx %y2,%y0\;addx %z2,%z0"
743 [(set_attr "length" "8,6,10")
744 (set_attr "cc" "clobber")])
746 (define_insn "addsi_h8300h"
747 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
748 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
749 (match_operand:SI 2 "nonmemory_operand" "L,N,i,r")))]
750 "TARGET_H8300H || TARGET_H8300S"
756 [(set_attr "length" "2,2,6,2")
757 (set_attr "cc" "none_0hit,none_0hit,set_zn,set_zn")])
760 [(set (match_operand:SI 0 "register_operand" "")
761 (plus:SI (match_dup 0)
762 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
763 "TARGET_H8300H || TARGET_H8300S"
765 "split_adds_subs (SImode, operands); DONE;")
767 ;; ----------------------------------------------------------------------
768 ;; SUBTRACT INSTRUCTIONS
769 ;; ----------------------------------------------------------------------
771 (define_insn "subqi3"
772 [(set (match_operand:QI 0 "register_operand" "=r")
773 (minus:QI (match_operand:QI 1 "register_operand" "0")
774 (match_operand:QI 2 "register_operand" "r")))]
777 [(set_attr "length" "2")
778 (set_attr "cc" "set_zn")])
780 (define_expand "subhi3"
781 [(set (match_operand:HI 0 "register_operand" "")
782 (minus:HI (match_operand:HI 1 "general_operand" "")
783 (match_operand:HI 2 "nonmemory_operand" "")))]
788 [(set (match_operand:HI 0 "register_operand" "=r,&r")
789 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
790 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
794 add.b %E2,%s0\;addx %F2,%t0"
795 [(set_attr "length" "2,4")
796 (set_attr "cc" "set_zn,clobber")])
799 [(set (match_operand:HI 0 "register_operand" "=r,&r")
800 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
801 (match_operand:HI 2 "nonmemory_operand" "r,n")))]
802 "TARGET_H8300H || TARGET_H8300S"
806 [(set_attr "length" "2,4")
807 (set_attr "cc" "set_zn,set_zn")])
809 (define_expand "subsi3"
810 [(set (match_operand:SI 0 "register_operand" "")
811 (minus:SI (match_operand:SI 1 "register_operand" "")
812 (match_operand:SI 2 "nonmemory_operand" "")))]
816 (define_insn "subsi3_h8300"
817 [(set (match_operand:SI 0 "register_operand" "=r")
818 (minus:SI (match_operand:SI 1 "register_operand" "0")
819 (match_operand:SI 2 "register_operand" "r")))]
821 "sub.w %f2,%f0\;subx %y2,%y0\;subx %z2,%z0"
822 [(set_attr "length" "6")
823 (set_attr "cc" "clobber")])
825 (define_insn "subsi3_h8300h"
826 [(set (match_operand:SI 0 "register_operand" "=r,r")
827 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
828 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
829 "TARGET_H8300H || TARGET_H8300S"
833 [(set_attr "length" "2,6")
834 (set_attr "cc" "set_zn,set_zn")])
836 ;; ----------------------------------------------------------------------
837 ;; MULTIPLY INSTRUCTIONS
838 ;; ----------------------------------------------------------------------
840 ;; Note that the H8/300 can only handle umulqihi3.
842 (define_insn "mulqihi3"
843 [(set (match_operand:HI 0 "register_operand" "=r")
844 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
845 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
846 "TARGET_H8300H || TARGET_H8300S"
848 [(set_attr "length" "4")
849 (set_attr "cc" "set_zn")])
851 (define_insn "mulhisi3"
852 [(set (match_operand:SI 0 "register_operand" "=r")
853 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
854 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
855 "TARGET_H8300H || TARGET_H8300S"
857 [(set_attr "length" "4")
858 (set_attr "cc" "set_zn")])
860 (define_insn "umulqihi3"
861 [(set (match_operand:HI 0 "register_operand" "=r")
862 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
863 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
866 [(set_attr "length" "2")
867 (set_attr "cc" "none_0hit")])
869 (define_insn "umulhisi3"
870 [(set (match_operand:SI 0 "register_operand" "=r")
871 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
872 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
873 "TARGET_H8300H || TARGET_H8300S"
875 [(set_attr "length" "2")
876 (set_attr "cc" "none_0hit")])
878 ;; This is a "bridge" instruction. Combine can't cram enough insns
879 ;; together to crate a MAC instruction directly, but it can create
880 ;; this instruction, which then allows combine to create the real
883 ;; Unfortunately, if combine doesn't create a MAC instruction, this
884 ;; insn must generate reasonably correct code. Egad.
886 [(set (match_operand:SI 0 "register_operand" "=a")
889 (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
891 (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
893 "clrmac\;mac @%2+,@%1+"
894 [(set_attr "length" "6")
895 (set_attr "cc" "none_0hit")])
898 [(set (match_operand:SI 0 "register_operand" "=a")
900 (sign_extend:SI (mem:HI
901 (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
902 (sign_extend:SI (mem:HI
903 (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
904 (match_operand:SI 3 "register_operand" "0")))]
907 [(set_attr "length" "4")
908 (set_attr "cc" "none_0hit")])
910 ;; ----------------------------------------------------------------------
911 ;; DIVIDE/MOD INSTRUCTIONS
912 ;; ----------------------------------------------------------------------
914 (define_insn "udivmodqi4"
915 [(set (match_operand:QI 0 "register_operand" "=r")
918 (match_operand:HI 1 "register_operand" "0")
919 (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
920 (set (match_operand:QI 3 "register_operand" "=r")
924 (zero_extend:HI (match_dup 2)))))]
928 if (find_reg_note (insn, REG_UNUSED, operands[3]))
929 return \"divxu.b\\t%X2,%T0\";
931 return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
933 [(set_attr "length" "4")
934 (set_attr "cc" "clobber")])
936 (define_insn "divmodqi4"
937 [(set (match_operand:QI 0 "register_operand" "=r")
940 (match_operand:HI 1 "register_operand" "0")
941 (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
942 (set (match_operand:QI 3 "register_operand" "=r")
946 (sign_extend:HI (match_dup 2)))))]
947 "TARGET_H8300H || TARGET_H8300S"
950 if (find_reg_note (insn, REG_UNUSED, operands[3]))
951 return \"divxs.b\\t%X2,%T0\";
953 return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
955 [(set_attr "length" "6")
956 (set_attr "cc" "clobber")])
958 (define_insn "udivmodhi4"
959 [(set (match_operand:HI 0 "register_operand" "=r")
962 (match_operand:SI 1 "register_operand" "0")
963 (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
964 (set (match_operand:HI 3 "register_operand" "=r")
968 (zero_extend:SI (match_dup 2)))))]
969 "TARGET_H8300H || TARGET_H8300S"
972 if (find_reg_note (insn, REG_UNUSED, operands[3]))
973 return \"divxu.w\\t%T2,%S0\";
975 return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
977 [(set_attr "length" "4")
978 (set_attr "cc" "clobber")])
980 (define_insn "divmodhi4"
981 [(set (match_operand:HI 0 "register_operand" "=r")
984 (match_operand:SI 1 "register_operand" "0")
985 (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
986 (set (match_operand:HI 3 "register_operand" "=r")
990 (sign_extend:SI (match_dup 2)))))]
991 "TARGET_H8300H || TARGET_H8300S"
994 if (find_reg_note (insn, REG_UNUSED, operands[3]))
995 return \"divxs.w\\t%T2,%S0\";
997 return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
999 [(set_attr "length" "6")
1000 (set_attr "cc" "clobber")])
1002 ;; ----------------------------------------------------------------------
1004 ;; ----------------------------------------------------------------------
1007 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1008 (and:QI (match_operand:QI 1 "bit_operand" "%0,0")
1009 (match_operand:QI 2 "nonmemory_operand" "rn,O")))]
1010 "register_operand (operands[0], QImode)
1011 || single_zero_operand (operands[2], QImode)"
1015 [(set_attr "length" "2,8")
1016 (set_attr "adjust_length" "no")
1017 (set_attr "cc" "set_znv,none_0hit")])
1019 (define_expand "andqi3"
1020 [(set (match_operand:QI 0 "bit_operand" "")
1021 (and:QI (match_operand:QI 1 "bit_operand" "")
1022 (match_operand:QI 2 "nonmemory_operand" "")))]
1026 if (fix_bit_operand (operands, 0, AND))
1030 (define_expand "andhi3"
1031 [(set (match_operand:HI 0 "register_operand" "")
1032 (and:HI (match_operand:HI 1 "register_operand" "")
1033 (match_operand:HI 2 "nonmemory_operand" "")))]
1037 (define_insn "*andorqi3"
1038 [(set (match_operand:QI 0 "register_operand" "=r")
1039 (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
1040 (match_operand:QI 3 "single_one_operand" "n"))
1041 (match_operand:QI 1 "register_operand" "0")))]
1043 "bld\\t%V3,%X2\;bst\\t%V3,%X0"
1044 [(set_attr "length" "4")
1045 (set_attr "cc" "clobber")])
1047 (define_insn "*andorhi3"
1048 [(set (match_operand:HI 0 "register_operand" "=r")
1049 (ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
1050 (match_operand:HI 3 "single_one_operand" "n"))
1051 (match_operand:HI 1 "register_operand" "0")))]
1055 operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
1056 if (INTVAL (operands[3]) > 128)
1058 operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
1059 return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
1061 return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
1063 [(set_attr "length" "4")
1064 (set_attr "cc" "clobber")])
1066 (define_expand "andsi3"
1067 [(set (match_operand:SI 0 "register_operand" "")
1068 (and:SI (match_operand:SI 1 "register_operand" "")
1069 (match_operand:SI 2 "nonmemory_operand" "")))]
1073 ;; ----------------------------------------------------------------------
1075 ;; ----------------------------------------------------------------------
1078 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1079 (ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
1080 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1081 "register_operand (operands[0], QImode)
1082 || single_one_operand (operands[2], QImode)"
1086 [(set_attr "length" "2,8")
1087 (set_attr "adjust_length" "no")
1088 (set_attr "cc" "set_znv,none_0hit")])
1090 (define_expand "iorqi3"
1091 [(set (match_operand:QI 0 "bit_operand" "")
1092 (ior:QI (match_operand:QI 1 "bit_operand" "")
1093 (match_operand:QI 2 "nonmemory_operand" "")))]
1097 if (fix_bit_operand (operands, 1, IOR))
1101 (define_expand "iorhi3"
1102 [(set (match_operand:HI 0 "register_operand" "")
1103 (ior:HI (match_operand:HI 1 "register_operand" "")
1104 (match_operand:HI 2 "nonmemory_operand" "")))]
1108 (define_expand "iorsi3"
1109 [(set (match_operand:SI 0 "register_operand" "")
1110 (ior:SI (match_operand:SI 1 "register_operand" "")
1111 (match_operand:SI 2 "nonmemory_operand" "")))]
1115 ;; ----------------------------------------------------------------------
1117 ;; ----------------------------------------------------------------------
1120 [(set (match_operand:QI 0 "bit_operand" "=r,U")
1121 (xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
1122 (match_operand:QI 2 "nonmemory_operand" "rn,n")))]
1123 "register_operand (operands[0], QImode)
1124 || single_one_operand (operands[2], QImode)"
1128 [(set_attr "length" "2,8")
1129 (set_attr "adjust_length" "no")
1130 (set_attr "cc" "set_znv,none_0hit")])
1132 (define_expand "xorqi3"
1133 [(set (match_operand:QI 0 "bit_operand" "")
1134 (xor:QI (match_operand:QI 1 "bit_operand" "")
1135 (match_operand:QI 2 "nonmemory_operand" "")))]
1139 if (fix_bit_operand (operands, 1, XOR))
1143 (define_expand "xorhi3"
1144 [(set (match_operand:HI 0 "register_operand" "")
1145 (xor:HI (match_operand:HI 1 "register_operand" "")
1146 (match_operand:HI 2 "nonmemory_operand" "")))]
1150 (define_expand "xorsi3"
1151 [(set (match_operand:SI 0 "register_operand" "")
1152 (xor:SI (match_operand:SI 1 "register_operand" "")
1153 (match_operand:SI 2 "nonmemory_operand" "")))]
1157 ;; ----------------------------------------------------------------------
1158 ;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
1159 ;; ----------------------------------------------------------------------
1162 [(set (match_operand:HI 0 "register_operand" "=r")
1163 (match_operator:HI 3 "bit_operator"
1164 [(match_operand:HI 1 "register_operand" "%0")
1165 (match_operand:HI 2 "nonmemory_operand" "rn")]))]
1167 "* return output_logical_op (HImode, operands);"
1168 [(set (attr "length")
1169 (symbol_ref "compute_logical_op_length (HImode, operands)"))
1171 (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
1174 [(set (match_operand:SI 0 "register_operand" "=r")
1175 (match_operator:SI 3 "bit_operator"
1176 [(match_operand:SI 1 "register_operand" "%0")
1177 (match_operand:SI 2 "nonmemory_operand" "rn")]))]
1179 "* return output_logical_op (SImode, operands);"
1180 [(set (attr "length")
1181 (symbol_ref "compute_logical_op_length (SImode, operands)"))
1183 (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
1185 ;; ----------------------------------------------------------------------
1186 ;; NEGATION INSTRUCTIONS
1187 ;; ----------------------------------------------------------------------
1189 (define_insn "negqi2"
1190 [(set (match_operand:QI 0 "register_operand" "=r")
1191 (neg:QI (match_operand:QI 1 "register_operand" "0")))]
1194 [(set_attr "length" "2")
1195 (set_attr "cc" "set_zn")])
1197 (define_expand "neghi2"
1198 [(set (match_operand:HI 0 "register_operand" "")
1199 (neg:HI (match_operand:HI 1 "register_operand" "")))]
1205 emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
1210 (define_expand "neghi2_h8300"
1212 (not:HI (match_operand:HI 1 "register_operand" "")))
1213 (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
1214 (set (match_operand:HI 0 "register_operand" "")
1217 "operands[2] = gen_reg_rtx (HImode);")
1219 (define_insn "neghi2_h8300h"
1220 [(set (match_operand:HI 0 "register_operand" "=r")
1221 (neg:HI (match_operand:HI 1 "register_operand" "0")))]
1222 "TARGET_H8300H || TARGET_H8300S"
1224 [(set_attr "length" "2")
1225 (set_attr "cc" "set_zn")])
1227 (define_expand "negsi2"
1228 [(set (match_operand:SI 0 "register_operand" "")
1229 (neg:SI (match_operand:SI 1 "register_operand" "")))]
1235 emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
1240 (define_expand "negsi2_h8300"
1242 (not:SI (match_operand:SI 1 "register_operand" "")))
1243 (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
1244 (set (match_operand:SI 0 "register_operand" "")
1247 "operands[2] = gen_reg_rtx (SImode);")
1249 (define_insn "negsi2_h8300h"
1250 [(set (match_operand:SI 0 "register_operand" "=r")
1251 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
1252 "TARGET_H8300H || TARGET_H8300S"
1254 [(set_attr "length" "2")
1255 (set_attr "cc" "set_zn")])
1257 ;; ----------------------------------------------------------------------
1259 ;; ----------------------------------------------------------------------
1261 (define_insn "one_cmplqi2"
1262 [(set (match_operand:QI 0 "register_operand" "=r")
1263 (not:QI (match_operand:QI 1 "register_operand" "0")))]
1266 [(set_attr "length" "2")
1267 (set_attr "cc" "set_znv")])
1269 (define_expand "one_cmplhi2"
1270 [(set (match_operand:HI 0 "register_operand" "=r")
1271 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1276 [(set (match_operand:HI 0 "register_operand" "=r")
1277 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1280 [(set_attr "cc" "clobber")
1281 (set_attr "length" "4")])
1284 [(set (match_operand:HI 0 "register_operand" "=r")
1285 (not:HI (match_operand:HI 1 "register_operand" "0")))]
1286 "TARGET_H8300H || TARGET_H8300S"
1288 [(set_attr "cc" "set_znv")
1289 (set_attr "length" "2")])
1291 (define_expand "one_cmplsi2"
1292 [(set (match_operand:SI 0 "register_operand" "=r")
1293 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1298 [(set (match_operand:SI 0 "register_operand" "=r")
1299 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1301 "not %w0\;not %x0\;not %y0\;not %z0"
1302 [(set_attr "cc" "clobber")
1303 (set_attr "length" "8")])
1306 [(set (match_operand:SI 0 "register_operand" "=r")
1307 (not:SI (match_operand:SI 1 "register_operand" "0")))]
1308 "TARGET_H8300H || TARGET_H8300S"
1310 [(set_attr "cc" "set_znv")
1311 (set_attr "length" "2")])
1313 ;; ----------------------------------------------------------------------
1314 ;; JUMP INSTRUCTIONS
1315 ;; ----------------------------------------------------------------------
1317 ;; Conditional jump instructions
1319 (define_expand "ble"
1321 (if_then_else (le (cc0)
1323 (label_ref (match_operand 0 "" ""))
1328 (define_expand "bleu"
1330 (if_then_else (leu (cc0)
1332 (label_ref (match_operand 0 "" ""))
1337 (define_expand "bge"
1339 (if_then_else (ge (cc0)
1341 (label_ref (match_operand 0 "" ""))
1346 (define_expand "bgeu"
1348 (if_then_else (geu (cc0)
1350 (label_ref (match_operand 0 "" ""))
1355 (define_expand "blt"
1357 (if_then_else (lt (cc0)
1359 (label_ref (match_operand 0 "" ""))
1364 (define_expand "bltu"
1366 (if_then_else (ltu (cc0)
1368 (label_ref (match_operand 0 "" ""))
1373 (define_expand "bgt"
1375 (if_then_else (gt (cc0)
1377 (label_ref (match_operand 0 "" ""))
1382 (define_expand "bgtu"
1384 (if_then_else (gtu (cc0)
1386 (label_ref (match_operand 0 "" ""))
1391 (define_expand "beq"
1393 (if_then_else (eq (cc0)
1395 (label_ref (match_operand 0 "" ""))
1400 (define_expand "bne"
1402 (if_then_else (ne (cc0)
1404 (label_ref (match_operand 0 "" ""))
1409 (define_insn "branch_true"
1411 (if_then_else (match_operator 1 "comparison_operator"
1412 [(cc0) (const_int 0)])
1413 (label_ref (match_operand 0 "" ""))
1418 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1419 && (GET_CODE (operands[1]) == GT
1420 || GET_CODE (operands[1]) == GE
1421 || GET_CODE (operands[1]) == LE
1422 || GET_CODE (operands[1]) == LT))
1424 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1428 if (get_attr_length (insn) == 2)
1429 return \"b%j1 %l0\";
1430 else if (get_attr_length (insn) == 4)
1431 return \"b%j1 %l0:16\";
1433 return \"b%k1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1435 [(set_attr "type" "branch")
1436 (set_attr "cc" "none")])
1438 (define_insn "branch_false"
1440 (if_then_else (match_operator 1 "comparison_operator"
1441 [(cc0) (const_int 0)])
1443 (label_ref (match_operand 0 "" ""))))]
1447 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
1448 && (GET_CODE (operands[1]) == GT
1449 || GET_CODE (operands[1]) == GE
1450 || GET_CODE (operands[1]) == LE
1451 || GET_CODE (operands[1]) == LT))
1453 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
1457 if (get_attr_length (insn) == 2)
1458 return \"b%k1 %l0\";
1459 else if (get_attr_length (insn) == 4)
1460 return \"b%k1 %l0:16\";
1462 return \"b%j1 .Lh8BR%=\;jmp @%l0\\n.Lh8BR%=:\";
1464 [(set_attr "type" "branch")
1465 (set_attr "cc" "none")])
1467 ;; Unconditional and other jump instructions.
1471 (label_ref (match_operand 0 "" "")))]
1475 if (get_attr_length (insn) == 2)
1477 else if (get_attr_length (insn) == 4)
1478 return \"bra %l0:16\";
1480 return \"jmp @%l0\";
1482 [(set_attr "type" "branch")
1483 (set_attr "cc" "none")])
1485 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1487 (define_expand "tablejump"
1488 [(parallel [(set (pc) (match_operand 0 "register_operand" ""))
1489 (use (label_ref (match_operand 1 "" "")))])]
1493 (define_insn "tablejump_h8300"
1494 [(set (pc) (match_operand:HI 0 "register_operand" "r"))
1495 (use (label_ref (match_operand 1 "" "")))]
1498 [(set_attr "cc" "none")
1499 (set_attr "length" "2")])
1501 (define_insn "tablejump_h8300h"
1502 [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1503 (use (label_ref (match_operand 1 "" "")))]
1504 "TARGET_H8300H || TARGET_H8300S"
1506 [(set_attr "cc" "none")
1507 (set_attr "length" "2")])
1509 ;; This is a define expand, because pointers may be either 16 or 32 bits.
1511 (define_expand "indirect_jump"
1512 [(set (pc) (match_operand 0 "jump_address_operand" ""))]
1516 (define_insn "indirect_jump_h8300"
1517 [(set (pc) (match_operand:HI 0 "jump_address_operand" "Vr"))]
1520 [(set_attr "cc" "none")
1521 (set_attr "length" "2")])
1523 (define_insn "indirect_jump_h8300h"
1524 [(set (pc) (match_operand:SI 0 "jump_address_operand" "Vr"))]
1525 "TARGET_H8300H || TARGET_H8300S"
1527 [(set_attr "cc" "none")
1528 (set_attr "length" "2")])
1530 ;; Call subroutine with no return value.
1532 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1535 [(call (match_operand:QI 0 "call_insn_operand" "or")
1536 (match_operand:HI 1 "general_operand" "g"))]
1540 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
1541 && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
1542 return \"jsr\\t@%0:8\";
1544 return \"jsr\\t%0\";
1546 [(set_attr "cc" "clobber")
1547 (set (attr "length")
1548 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1552 ;; Call subroutine, returning value in operand 0
1553 ;; (which must be a hard register).
1555 ;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
1557 (define_insn "call_value"
1558 [(set (match_operand 0 "" "=r")
1559 (call (match_operand:QI 1 "call_insn_operand" "or")
1560 (match_operand:HI 2 "general_operand" "g")))]
1564 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
1565 && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
1566 return \"jsr\\t@%1:8\";
1568 return \"jsr\\t%1\";
1570 [(set_attr "cc" "clobber")
1571 (set (attr "length")
1572 (if_then_else (match_operand:QI 0 "small_call_insn_operand" "")
1580 [(set_attr "cc" "none")
1581 (set_attr "length" "2")])
1583 ;; ----------------------------------------------------------------------
1584 ;; EXTEND INSTRUCTIONS
1585 ;; ----------------------------------------------------------------------
1587 (define_expand "zero_extendqihi2"
1588 [(set (match_operand:HI 0 "register_operand" "")
1589 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "")))]
1594 [(set (match_operand:HI 0 "register_operand" "=r,r")
1595 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1599 mov.b %R1,%s0\;mov.b #0,%t0"
1600 [(set_attr "length" "2,10")
1601 (set_attr "cc" "clobber,clobber")])
1604 [(set (match_operand:HI 0 "register_operand" "=r,r")
1605 (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1606 "TARGET_H8300H || TARGET_H8300S"
1609 mov.b %R1,%s0\;extu.w %T0"
1610 [(set_attr "length" "2,10")
1611 (set_attr "cc" "set_znv,set_znv")])
1613 ;; The compiler can synthesize a 300H variant of this which is
1614 ;; just as efficient as one that we'd create
1615 (define_insn "zero_extendqisi2"
1616 [(set (match_operand:SI 0 "register_operand" "=r,r")
1617 (zero_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1620 mov.b #0,%x0\;sub.w %e0,%e0
1621 mov.b %R1,%w0\;mov.b #0,%x0\;sub.w %e0,%e0"
1622 [(set_attr "length" "4,6")
1623 (set_attr "cc" "clobber,clobber")])
1625 (define_expand "zero_extendhisi2"
1626 [(set (match_operand:SI 0 "register_operand" "")
1627 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1631 ;; %e prints the high part of a CONST_INT, not the low part. Arggh.
1633 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1634 (zero_extend:SI (match_operand:HI 1 "general_operand_src" "0,i,g>")))]
1638 mov.w %f1,%f0\;sub.w %e0,%e0
1639 mov.w %e1,%f0\;sub.w %e0,%e0"
1640 [(set_attr "length" "2,4,4")
1641 (set_attr "cc" "clobber,clobber,clobber")])
1644 [(set (match_operand:SI 0 "register_operand" "=r")
1645 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1646 "TARGET_H8300H || TARGET_H8300S"
1648 [(set_attr "length" "2")
1649 (set_attr "cc" "set_znv")])
1651 (define_expand "extendqihi2"
1652 [(set (match_operand:HI 0 "register_operand" "")
1653 (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
1658 [(set (match_operand:HI 0 "register_operand" "=r,r")
1659 (sign_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1662 bld #7,%s0\;subx %t0,%t0
1663 mov.b %R1,%s0\;bld #7,%s0\;subx %t0,%t0"
1664 [(set_attr "length" "4,8")
1665 (set_attr "cc" "clobber,clobber")])
1668 [(set (match_operand:HI 0 "register_operand" "=r")
1669 (sign_extend:HI (match_operand:QI 1 "register_operand" "0")))]
1670 "TARGET_H8300H || TARGET_H8300S"
1672 [(set_attr "length" "2")
1673 (set_attr "cc" "set_znv")])
1675 ;; The compiler can synthesize a 300H variant of this which is
1676 ;; just as efficient as one that we'd create
1677 (define_insn "extendqisi2"
1678 [(set (match_operand:SI 0 "register_operand" "=r,r")
1679 (sign_extend:SI (match_operand:QI 1 "general_operand_src" "0,g>")))]
1682 bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0
1683 mov.b %R1,%w0\;bld #7,%w0\;subx %x0,%x0\;subx %y0,%y0\;subx %z0,%z0"
1684 [(set_attr "length" "8,10")
1685 (set_attr "cc" "clobber,clobber")])
1687 (define_expand "extendhisi2"
1688 [(set (match_operand:SI 0 "register_operand" "")
1689 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
1694 [(set (match_operand:SI 0 "register_operand" "=r,r")
1695 (sign_extend:SI (match_operand:HI 1 "general_operand_src" "0,g>")))]
1698 bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0
1699 mov.w %T1,%f0\;bld #7,%x0\;subx %y0,%y0\;subx %z0,%z0"
1700 [(set_attr "length" "6,8")
1701 (set_attr "cc" "clobber,clobber")])
1704 [(set (match_operand:SI 0 "register_operand" "=r")
1705 (sign_extend:SI (match_operand:HI 1 "register_operand" "0")))]
1706 "TARGET_H8300H || TARGET_H8300S"
1708 [(set_attr "length" "2")
1709 (set_attr "cc" "set_znv")])
1711 ;; ----------------------------------------------------------------------
1713 ;; ----------------------------------------------------------------------
1715 ;; We make some attempt to provide real efficient shifting. One example is
1716 ;; doing an 8 bit shift of a 16 bit value by moving a byte reg into the other
1717 ;; reg and moving 0 into the former reg.
1719 ;; We also try to achieve this in a uniform way. IE: We don't try to achieve
1720 ;; this in both rtl and at insn emit time. Ideally, we'd use rtl as that would
1721 ;; give the optimizer more cracks at the code. However, we wish to do things
1722 ;; like optimizing shifting the sign bit to bit 0 by rotating the other way.
1723 ;; There is rtl to handle this (rotate + and), but the H8/300 doesn't handle
1724 ;; 16 bit rotates. Also, if we emit complicated rtl, combine may not be able
1725 ;; to detect cases it can optimize.
1727 ;; For these and other fuzzy reasons, I've decided to go the less pretty but
1728 ;; easier "do it at insn emit time" route.
1732 (define_expand "ashlqi3"
1733 [(set (match_operand:QI 0 "register_operand" "")
1734 (ashift:QI (match_operand:QI 1 "register_operand" "")
1735 (match_operand:QI 2 "nonmemory_operand" "")))]
1737 "if (expand_a_shift (QImode, ASHIFT, operands)) DONE; else FAIL;")
1739 (define_expand "ashrqi3"
1740 [(set (match_operand:QI 0 "register_operand" "")
1741 (ashiftrt:QI (match_operand:QI 1 "register_operand" "")
1742 (match_operand:QI 2 "nonmemory_operand" "")))]
1744 "if (expand_a_shift (QImode, ASHIFTRT, operands)) DONE; else FAIL;")
1746 (define_expand "lshrqi3"
1747 [(set (match_operand:QI 0 "register_operand" "")
1748 (lshiftrt:QI (match_operand:QI 1 "register_operand" "")
1749 (match_operand:QI 2 "nonmemory_operand" "")))]
1751 "if (expand_a_shift (QImode, LSHIFTRT, operands)) DONE; else FAIL;")
1754 [(set (match_operand:QI 0 "register_operand" "=r,r")
1755 (match_operator:QI 3 "nshift_operator"
1756 [ (match_operand:QI 1 "register_operand" "0,0")
1757 (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
1758 (clobber (match_scratch:QI 4 "=X,&r"))]
1760 "* return output_a_shift (operands);"
1761 [(set (attr "length")
1762 (symbol_ref "compute_a_shift_length (insn, operands)"))
1763 (set_attr "cc" "clobber")])
1767 (define_expand "ashlhi3"
1768 [(set (match_operand:HI 0 "register_operand" "")
1769 (ashift:HI (match_operand:HI 1 "nonmemory_operand" "")
1770 (match_operand:QI 2 "nonmemory_operand" "")))]
1772 "if (expand_a_shift (HImode, ASHIFT, operands)) DONE; else FAIL;")
1774 (define_expand "lshrhi3"
1775 [(set (match_operand:HI 0 "register_operand" "")
1776 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1777 (match_operand:QI 2 "nonmemory_operand" "")))]
1779 "if (expand_a_shift (HImode, LSHIFTRT, operands)) DONE; else FAIL;")
1781 (define_expand "ashrhi3"
1782 [(set (match_operand:HI 0 "register_operand" "")
1783 (ashiftrt:HI (match_operand:HI 1 "register_operand" "")
1784 (match_operand:QI 2 "nonmemory_operand" "")))]
1786 "if (expand_a_shift (HImode, ASHIFTRT, operands)) DONE; else FAIL;")
1789 [(set (match_operand:HI 0 "register_operand" "=r,r")
1790 (match_operator:HI 3 "nshift_operator"
1791 [ (match_operand:HI 1 "register_operand" "0,0")
1792 (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
1793 (clobber (match_scratch:QI 4 "=X,&r"))]
1795 "* return output_a_shift (operands);"
1796 [(set (attr "length")
1797 (symbol_ref "compute_a_shift_length (insn, operands)"))
1798 (set_attr "cc" "clobber")])
1802 (define_expand "ashlsi3"
1803 [(set (match_operand:SI 0 "register_operand" "")
1804 (ashift:SI (match_operand:SI 1 "general_operand" "")
1805 (match_operand:QI 2 "nonmemory_operand" "")))]
1807 "if (expand_a_shift (SImode, ASHIFT, operands)) DONE; else FAIL;")
1809 (define_expand "lshrsi3"
1810 [(set (match_operand:SI 0 "register_operand" "")
1811 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
1812 (match_operand:QI 2 "nonmemory_operand" "")))]
1814 "if (expand_a_shift (SImode, LSHIFTRT, operands)) DONE; else FAIL;")
1816 (define_expand "ashrsi3"
1817 [(set (match_operand:SI 0 "register_operand" "")
1818 (ashiftrt:SI (match_operand:SI 1 "general_operand" "")
1819 (match_operand:QI 2 "nonmemory_operand" "")))]
1821 "if (expand_a_shift (SImode, ASHIFTRT, operands)) DONE; else FAIL;")
1824 [(set (match_operand:SI 0 "register_operand" "=r,r")
1825 (match_operator:SI 3 "nshift_operator"
1826 [ (match_operand:SI 1 "register_operand" "0,0")
1827 (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
1828 (clobber (match_scratch:QI 4 "=X,&r"))]
1830 "* return output_a_shift (operands);"
1831 [(set (attr "length")
1832 (symbol_ref "compute_a_shift_length (insn, operands)"))
1833 (set_attr "cc" "clobber")])
1835 ;; ----------------------------------------------------------------------
1837 ;; ----------------------------------------------------------------------
1839 (define_expand "rotlqi3"
1840 [(set (match_operand:QI 0 "register_operand" "")
1841 (rotate:QI (match_operand:QI 1 "register_operand" "")
1842 (match_operand:QI 2 "nonmemory_operand" "")))]
1844 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1846 (define_insn "*rotlqi3_1"
1847 [(set (match_operand:QI 0 "register_operand" "=r")
1848 (rotate:QI (match_operand:QI 1 "register_operand" "0")
1849 (match_operand:QI 2 "immediate_operand" "")))]
1851 "* return emit_a_rotate (ROTATE, operands);"
1852 [(set_attr "length" "20")
1853 (set_attr "cc" "clobber")])
1855 (define_expand "rotlhi3"
1856 [(set (match_operand:HI 0 "register_operand" "")
1857 (rotate:HI (match_operand:HI 1 "register_operand" "")
1858 (match_operand:QI 2 "nonmemory_operand" "")))]
1860 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1862 (define_insn "*rotlhi3_1"
1863 [(set (match_operand:HI 0 "register_operand" "=r")
1864 (rotate:HI (match_operand:HI 1 "register_operand" "0")
1865 (match_operand:QI 2 "immediate_operand" "")))]
1867 "* return emit_a_rotate (ROTATE, operands);"
1868 [(set_attr "length" "20")
1869 (set_attr "cc" "clobber")])
1871 (define_expand "rotlsi3"
1872 [(set (match_operand:SI 0 "register_operand" "")
1873 (rotate:SI (match_operand:SI 1 "register_operand" "")
1874 (match_operand:QI 2 "nonmemory_operand" "")))]
1875 "TARGET_H8300H || TARGET_H8300S"
1876 "if (expand_a_rotate (ROTATE, operands)) DONE; else FAIL;")
1878 (define_insn "*rotlsi3_1"
1879 [(set (match_operand:SI 0 "register_operand" "=r")
1880 (rotate:SI (match_operand:SI 1 "register_operand" "0")
1881 (match_operand:QI 2 "immediate_operand" "")))]
1882 "TARGET_H8300H || TARGET_H8300S"
1883 "* return emit_a_rotate (ROTATE, operands);"
1884 [(set_attr "length" "20")
1885 (set_attr "cc" "clobber")])
1887 ;; -----------------------------------------------------------------
1889 ;; -----------------------------------------------------------------
1890 ;; The H8/300 has given 1/8th of its opcode space to bitfield
1891 ;; instructions so let's use them as well as we can.
1893 ;; You'll never believe all these patterns perform one basic action --
1894 ;; load a bit from the source, optionally invert the bit, then store it
1895 ;; in the destination (which is known to be zero).
1897 ;; Combine obviously need some work to better identify this situation and
1898 ;; canonicalize the form better.
1901 ;; Normal loads with a 16bit destination.
1905 [(set (match_operand:HI 0 "register_operand" "=&r")
1906 (zero_extract:HI (match_operand:HI 1 "register_operand" "r")
1908 (match_operand:HI 2 "immediate_operand" "n")))]
1910 "sub.w %0,%0\;bld %Z2,%Y1\;bst #0,%X0"
1911 [(set_attr "cc" "clobber")
1912 (set_attr "length" "6")])
1915 ;; Inverted loads with a 16bit destination.
1919 [(set (match_operand:HI 0 "register_operand" "=&r")
1920 (zero_extract:HI (xor:HI (match_operand:HI 1 "register_operand" "r")
1921 (match_operand:HI 3 "const_int_operand" "n"))
1923 (match_operand:HI 2 "const_int_operand" "n")))]
1925 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1926 "sub.w %0,%0\;bild %Z2,%Y1\;bst #0,%X0"
1927 [(set_attr "cc" "clobber")
1928 (set_attr "length" "8")])
1931 ;; Normal loads with a 32bit destination.
1935 [(set (match_operand:SI 0 "register_operand" "=&r")
1936 (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1938 (match_operand 2 "const_int_operand" "n")))]
1940 && INTVAL (operands[2]) < 16"
1941 "* return output_simode_bld (0, operands);"
1942 [(set_attr "cc" "clobber")
1943 (set_attr "length" "6")])
1946 [(set (match_operand:SI 0 "register_operand" "=r")
1947 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1949 (match_operand 2 "const_int_operand" "n")))]
1950 "(TARGET_H8300H || TARGET_H8300S)
1951 && INTVAL (operands[2]) < 16"
1952 "* return output_simode_bld (0, operands);"
1953 [(set_attr "cc" "clobber")
1954 (set_attr "length" "6")])
1957 ;; Inverted loads with a 32bit destination.
1961 [(set (match_operand:SI 0 "register_operand" "=&r")
1962 (zero_extract:SI (xor:HI (match_operand:HI 1 "register_operand" "r")
1963 (match_operand:HI 3 "const_int_operand" "n"))
1965 (match_operand 2 "const_int_operand" "n")))]
1967 && INTVAL (operands[2]) < 16
1968 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1969 "* return output_simode_bld (1, operands);"
1970 [(set_attr "cc" "clobber")
1971 (set_attr "length" "6")])
1974 [(set (match_operand:SI 0 "register_operand" "=r")
1975 (zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
1976 (match_operand 3 "const_int_operand" "n"))
1978 (match_operand 2 "const_int_operand" "n")))]
1979 "(TARGET_H8300H || TARGET_H8300S)
1980 && INTVAL (operands[2]) < 16
1981 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
1982 "* return output_simode_bld (1, operands);"
1983 [(set_attr "cc" "clobber")
1984 (set_attr "length" "6")])
1986 (define_expand "insv"
1987 [(set (zero_extract:HI (match_operand:HI 0 "general_operand" "")
1988 (match_operand:HI 1 "general_operand" "")
1989 (match_operand:HI 2 "general_operand" ""))
1990 (match_operand:HI 3 "general_operand" ""))]
1994 /* We only have single bit bitfield instructions. */
1995 if (INTVAL (operands[1]) != 1)
1998 /* For now, we don't allow memory operands. */
1999 if (GET_CODE (operands[0]) == MEM
2000 || GET_CODE (operands[3]) == MEM)
2005 [(set (zero_extract:HI (match_operand:HI 0 "register_operand" "+r")
2007 (match_operand:HI 1 "immediate_operand" "n"))
2008 (match_operand:HI 2 "register_operand" "r"))]
2010 "bld #0,%R2\;bst %Z1,%Y0 ; i1"
2011 [(set_attr "cc" "clobber")
2012 (set_attr "length" "4")])
2014 (define_expand "extzv"
2015 [(set (match_operand:HI 0 "register_operand" "")
2016 (zero_extract:HI (match_operand:HI 1 "bit_operand" "")
2017 (match_operand:HI 2 "general_operand" "")
2018 (match_operand:HI 3 "general_operand" "")))]
2022 /* We only have single bit bitfield instructions. */
2023 if (INTVAL (operands[2]) != 1)
2026 /* For now, we don't allow memory operands. */
2027 if (GET_CODE (operands[1]) == MEM)
2031 ;; BAND, BOR, and BXOR patterns
2034 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2035 (match_operator:HI 4 "bit_operator"
2036 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2038 (match_operand:HI 2 "immediate_operand" "n"))
2039 (match_operand:HI 3 "bit_operand" "0")]))]
2041 "bld %Z2,%Y1\;%b4 #0,%R0\;bst #0,%R0; bl1"
2042 [(set_attr "cc" "clobber")
2043 (set_attr "length" "6")
2044 (set_attr "adjust_length" "no")])
2047 [(set (match_operand:HI 0 "bit_operand" "=Ur")
2048 (match_operator:HI 5 "bit_operator"
2049 [(zero_extract:HI (match_operand:HI 1 "register_operand" "r")
2051 (match_operand:HI 2 "immediate_operand" "n"))
2052 (zero_extract:HI (match_operand:HI 3 "register_operand" "r")
2054 (match_operand:HI 4 "immediate_operand" "n"))]))]
2056 "bld %Z2,%Y1\;%b5 %Z4,%Y3\;bst #0,%R0; bl3"
2057 [(set_attr "cc" "clobber")
2058 (set_attr "length" "6")
2059 (set_attr "adjust_length" "no")])
2061 ;; -----------------------------------------------------------------
2063 ;; -----------------------------------------------------------------
2066 [(set (match_operand:HI 0 "register_operand" "=r")
2067 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2068 (match_operand:HI 2 "register_operand" "0")))]
2069 "REG_P (operands[0])
2070 && REG_P (operands[1])
2071 && REGNO (operands[0]) != REGNO (operands[1])"
2073 [(set_attr "cc" "clobber")
2074 (set_attr "length" "2")])
2077 [(set (match_operand:SI 0 "register_operand" "=r")
2078 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2079 (match_operand:SI 2 "register_operand" "0")))]
2080 "(TARGET_H8300H || TARGET_H8300S)
2081 && REG_P (operands[0])
2082 && REG_P (operands[1])
2083 && (REGNO (operands[0]) != REGNO (operands[1]))"
2085 [(set_attr "cc" "clobber")
2086 (set_attr "length" "2")])
2089 [(set (match_operand:SI 0 "register_operand" "=r")
2090 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2091 (match_operand:SI 2 "register_operand" "0")))]
2092 "REG_P (operands[0])
2093 && REG_P (operands[1])
2094 && REGNO (operands[0]) != REGNO (operands[1])"
2096 [(set_attr "cc" "clobber")
2097 (set_attr "length" "2")])
2100 [(set (match_operand:HI 0 "register_operand" "=r")
2101 (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
2102 (match_operand:HI 2 "register_operand" "0")))]
2103 "REG_P (operands[0])
2104 && REG_P (operands[1])
2105 && REGNO (operands[0]) != REGNO (operands[1])"
2107 [(set_attr "cc" "clobber")
2108 (set_attr "length" "2")])
2111 [(set (match_operand:SI 0 "register_operand" "=r")
2112 (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
2113 (match_operand:SI 2 "register_operand" "0")))]
2114 "(TARGET_H8300H || TARGET_H8300S)
2115 && REG_P (operands[0])
2116 && REG_P (operands[1])
2117 && (REGNO (operands[0]) != REGNO (operands[1]))"
2119 [(set_attr "cc" "clobber")
2120 (set_attr "length" "2")])
2123 [(set (match_operand:SI 0 "register_operand" "=r")
2124 (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
2125 (match_operand:SI 2 "register_operand" "0")))]
2126 "REG_P (operands[0])
2127 && REG_P (operands[1])
2128 && REGNO (operands[0]) != REGNO (operands[1])"
2130 [(set_attr "cc" "clobber")
2131 (set_attr "length" "2")])
2134 [(set (match_operand:HI 0 "register_operand" "=r")
2135 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
2136 (ashift:HI (match_operand:HI 2 "register_operand" "r")
2138 "REG_P (operands[0])
2139 && REG_P (operands[2])
2140 && REGNO (operands[0]) != REGNO (operands[2])"
2142 [(set_attr "cc" "clobber")
2143 (set_attr "length" "2")])
2146 [(set (match_operand:SI 0 "register_operand" "=r")
2147 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
2148 (ashift:SI (match_operand:SI 2 "register_operand" "r")
2150 "(TARGET_H8300H || TARGET_H8300S)
2151 && REG_P (operands[0])
2152 && REG_P (operands[2])
2153 && (REGNO (operands[0]) != REGNO (operands[2]))"
2155 [(set_attr "cc" "clobber")
2156 (set_attr "length" "2")])
2158 (define_insn_and_split ""
2160 (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2164 (label_ref (match_operand 1 "" ""))
2172 (if_then_else (ge (cc0)
2174 (label_ref (match_dup 1))
2178 (define_insn_and_split ""
2180 (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
2184 (label_ref (match_operand 1 "" ""))
2192 (if_then_else (lt (cc0)
2194 (label_ref (match_dup 1))