| blob | 2d52082da35c971cd94e08aef02bacda8c9b84db |
1 ;; Machine description for the TMS320C[34]x for GNU C compiler
2 ;; Copyright (C) 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2002 Free Software Foundation, Inc.
5 ;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 ;; and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; any later version.
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;
26 ; TODO :
27 ; Try using PQImode again for addresses since C30 only uses
28 ; 24-bit addresses. Ideally GCC would emit different insns
29 ; for QImode and Pmode, whether Pmode was QImode or PQImode.
30 ; For addresses we wouldn't have to have a clobber of the CC
31 ; associated with each insn and we could use MPYI in address
32 ; calculations without having to synthesize a proper 32 bit multiply.
34 ; Additional C30/C40 instructions not coded:
35 ; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
36 ; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI
38 ; Additional C40 instructions not coded:
39 ; LDEP, LDPE, LWRct, LAJcond, RETIcondD
41 ;
42 ; C4x MODES
43 ;
44 ; QImode char, short, int, long (32-bits)
45 ; HImode long long (64-bits)
46 ; QFmode float, double (32-bits)
47 ; HFmode long double (40-bits)
48 ; CCmode
49 ; CC_NOOVmode
51 ;
52 ; C4x PREDICATES:
53 ;
54 ; comparison_operator LT, GT, LE, GE, LTU, GTU, LEU, GEU, EQ, NE
55 ; memory_operand memory [m]
56 ; immediate_operand immediate constant [IKN]
57 ; register_operand register [rf]
58 ; general_operand register, memory, constant [rfmI]
60 ; addr_reg_operand AR0-AR7, pseudo reg [a]
61 ; sp_reg_operand SP [b]
62 ; std_reg_operand AR0-AR7, IR0-IR1, RC, RS, RE, SP, pseudo [c]
63 ; ext_reg_operand R0-R11, pseudo reg [f]
64 ; ext_low_reg_operand R0-R7, pseudo reg [q]
65 ; index_reg_operand IR0-IR1, pseudo reg [x]
66 ; st_reg_operand ST [y]
67 ; dp_reg_operand DP [z]
68 ; stik_const_operand 5-bit const [K]
69 ; src_operand general operand [rfHmI]
70 ; par_ind_operand indirect S mode (ARx + 0, 1, IRx) [S<>]
71 ; parallel_operand par_ind_operand or ext_low_reg_operand
72 ; symbolic_address_operand
73 ; call_address_operand
75 ; ADDI src2, src1, dst three operand op
76 ; ADDI src, dst two operand op
78 ; Note that the predicates are only used when selecting a pattern
79 ; to determine if an operand is valid.
81 ; The constraints then select which of the possible valid operands
82 ; is present (and guide register selection). The actual assembly
83 ; instruction is then selected on the basis of the constraints.
85 ; The extra constraint (valid_operands) is used to determine if
86 ; the combination of operands is legitimate for the pattern.
88 ;
89 ; C4x CONSTRAINTS:
90 ;
91 ; a address reg AR0-AR7
92 ; b stack pointer SP
93 ; c other int reg AR0-AR7, IR0-IR1, RC, RS, RE
94 ; d fp reg R0-R11 (sets CC when dst)
95 ; e
96 ; f fp reg R0-R11 (sets CC when dst)
97 ; g general reg, memory, constant
98 ; h fp reg (HFmode) R0-R11 (sets CC when dst)
99 ; i immediate int constant
100 ; j
101 ; k block count BK
102 ; l
103 ; m memory
104 ; n immediate int constant with known numeric value
105 ; o offsettable memory
106 ; p memory address
107 ; q low fp reg R0-R7 (sets CC when dst)
108 ; r general reg R0-R11, AR0-AR7, IR0-IR1, RC, RS, RE
109 ; s immediate int constant (value not explicit)
110 ; t R0-R1
111 ; u R2-R3
112 ; v repeat count reg RC
113 ; w
114 ; x index reg IR0-IR1
115 ; y status (CC) reg ST
116 ; z data pointer DP
118 ; G fp zero
119 ; H fp 16-bit constant
120 ; I signed 16-bit
121 ; J signed 8-bit (C4x only)
122 ; K signed 5-bit (C4x only)
123 ; L unsigned 16-bit
124 ; M unsigned 8-bit (C4x only)
125 ; N ones complement of unsigned 16-bit
126 ; O 16 bit high constant
127 ; Q ARx + 9-bit signed disp
128 ; R ARx + 5-bit unsigned disp (C4x only)
129 ; S ARx + 0, 1, IRx disp
130 ; T direct memory operand
131 ; V non offsettable memory
132 ; X any operand
133 ; < memory operand with autodecrement addressing
134 ; > memory operand with autoincrement addressing
135 ; { memory operand with pre-modify addressing
136 ; } memory operand with post-modify addressing
138 ; Note that the 'd', 'f', and 'h' constraints are equivalent.
139 ; The m constraint is equivalent to 'QT<>{}'
141 ; Note we cannot use the 'g' constraint with Pmode (i.e, QImode)
142 ; operations since LEGITIMATE_CONSTANT_P accepts SYMBOL_REF.
143 ; So instead we use 'rIm' for signed operands or 'rLm' for unsigned operands.
145 ; Note that the constraints are used to select the operands
146 ; for a chosen pattern. The constraint that requires the fewest
147 ; instructions to load an operand is chosen.
149 ; Note that the 'r' constraint is mostly only used for src integer register
150 ; operands, while 'c' and 'd' constraints are generally only used for dst
151 ; integer register operands (the 'r' constraint is the union of the 'c' and
152 ; 'd' constraints). When a register satisfying the 'd' constraint
153 ; is used as a dst operand, the CC gets clobbered (except for LDIcond)---but
154 ; not for 'c'.
156 ; The 'f' constraint is only for float register operands---when
157 ; a register satisying the 'f' constraint is used as a dst operand,
158 ; the CC gets clobbered (except for LDFcond).
160 ; The ! in front of the 'b' constaint says to GCC to disparage the
161 ; use of this constraint. The 'b' constraint applies only to the SP.
163 ; Note that we deal with the condition code CC like some of the RISC
164 ; architectures (arm, sh, sparc) where it is stored in a general register,
165 ; in this case the hard register ST (21). Unlike these other architectures
166 ; that do not set the CC with many instructions, the C[34]x architectures
167 ; sets the CC for many instructions when the destination register is
168 ; an extended precision register. While it would have been easier
169 ; to use the generic cc0 register to store the CC, as with most of
170 ; the other ported architectures, this constrains the setting and testing
171 ; of the CC to be consecutive insns. Thus we would reduce the benefit
172 ; of scheduling instructions to avoid pipeline conflicts and filling of
173 ; delayed branch slots.
175 ; Since the C[34]x has many instructions that set the CC, we pay the
176 ; price of having to explicity define which insns clobber the CC
177 ; (rather than using the macro NOTICE_UPDATE_CC).
179 ; Note that many patterns say that the CC is clobbered when in fact
180 ; that it may not be (depending on the destination register).
181 ; We have to cover ourselves if an extended precision register
182 ; is allocated to the destination register.
183 ; Unfortunately, it is not easy to tell GCC that the clobbering of CC
184 ; is register dependent. If we could tolerate the ST register being
185 ; copied about, then we could store the CC in a pseudo register and
186 ; use constructs such as (clobber (match_scratch:CC N "&y,X")) to
187 ; indicate that the 'y' class (ST register) is clobbered for the
188 ; first combination of operands, but not with the second.
189 ; I tried this approach for a while but reload got unhappy since I
190 ; didn't allow it to move the CC around.
192 ; Note that fundamental operations, such as moves, must not clobber the
193 ; CC. Thus movqi choses a move instruction that doesn't clobber the CC.
194 ; If GCC wants to combine a move with a compare, it is smart enough to
195 ; chose the move instruction that sets the CC.
197 ; Unfortunately, the C[34]x instruction set does not have arithmetic or
198 ; logical operations that never touch the CC. We thus have to assume
199 ; that the CC may be clobbered at all times. If we define patterns
200 ; such as addqi without the clobber of CC, then GCC will be forced
201 ; to use registers such as the auxiliary registers which can cause
202 ; horrible pipeline conflicts. The tradeoff is that GCC can't now
203 ; sneak in an add instruction between setting and testing of the CC.
205 ; Most of the C[34]x instructions require operands of the following formats,
206 ; where imm represents an immediate constant, dir a direct memory reference,
207 ; ind an indirect memory reference, and reg a register:
209 ; src2 (op2) src1 (op1) dst (op0)
210 ; imm dir ind reg | imm dir ind reg | reg Notes
211 ;---------------------+----------------------+------
212 ; ILH T Q<> r | - - - 0 | r 2 operand
213 ; - - S<> r | - - S<> r | r
214 ; J - R - | - - R r | r C4x
216 ; Arithmetic operations use the I, J constraints for immediate constants,
217 ; while logical operations use the L, J constraints. Floating point
218 ; operations use the H constraint for immediate constants.
220 ; With most instructions the src2 and src1 operands are commutative
221 ; (except for SUB, SUBR, ANDN). The assembler considers
222 ; ADDI 10, R0, R1 and ADDI R0, 10, R1 to be equivalent.
223 ; We thus match src2 and src1 with the src_operand predicate and
224 ; use valid_operands as the extra constraint to reject invalid
225 ; operand combinations. For example, ADDI @foo, @bar, R0.
227 ; Note that we use the ? modifier so that reload doesn't preferentially
228 ; try the alternative where three registers are acceptable as
229 ; operands (whenever an operand requires reloading). Instead it will try
230 ; the 2 operand form which will produce better code since it won't require
231 ; a new spill register.
233 ; Note that the floating point representation of 0.0 on the C4x
234 ; is 0x80000000 (-2147483648). This value produces an warning
235 ; message on 32-bit machines about the decimal constant being so large
236 ; that it is unsigned.
238 ; With two operand instructions patterns having two sets,
239 ; the compare set must come first to keep the combiner happy.
240 ; While the combiner seems to cope most of the time with the
241 ; compare set coming second, it's best to have it first.
243 ;
244 ; C4x CONSTANT attributes
245 ;
246 (define_attr "cpu" "c4x,c3x"
247 (const
248 (cond [(symbol_ref "TARGET_C3X") (const_string "c3x")]
249 (const_string "c4x"))))
251 ;
252 ; C4x INSN ATTRIBUTES:
253 ;
254 ; lda load address, non-clobber CC
255 ; store memory store, non-clobber CC
256 ; load_load parallel memory loads, non-clobber CC
257 ; load_store parallel memory load and store, non-clobber CC
258 ; store_load parallel memory store and load, non-clobber CC
259 ; store_store parallel memory stores, non-clobber CC
260 ; unary two operand arithmetic, non-clobber CC
261 ; unarycc two operand arithmetic, clobber CC
262 ; binary three operand arithmetic, non-clobber CC
263 ; binarycc three operand arithmetic, clobber CC
264 ; compare compare, clobber CC
265 ; call function call
266 ; rets return from subroutine
267 ; jump unconditional branch
268 ; jmpc conditional branch
269 ; db decrement and branch (unconditional)
270 ; dbc decrement and branch (conditional)
271 ; ldp load DP
272 ; push stack push
273 ; pop stack pop
274 ; repeat block repeat
275 ; repeat_top block repeat top
276 ; laj link and jump
277 ; multi multiple instruction
278 ; misc nop (default)
280 ; The only real instructions that affect things are the ones that modify
281 ; address registers and ones that call or jump. Note that the number
282 ; of operands refers to the RTL insn pattern, not the number of explicit
283 ; operands in the machine instruction.
284 ;
285 (define_attr "type" "lda,store,unary,unarycc,binary,binarycc,compare,call,rets,jump,jmpc,db,dbc,misc,ldp,repeat,repeat_top,laj,load_load,load_store,store_load,store_store,push,pop,multi"
286 (const_string "misc"))
289 ; Some instructions operate on unsigned data constants, some on signed data
290 ; constants, or the ones complement of unsigned constants.
291 ; This differentiates them. Default to signed. This attribute
292 ; is used by the macro SMALL_CONST () (defined in c4x.h) to determine
293 ; whether an immediate integer constant will fit within the instruction,
294 ; or will have to be loaded using direct addressing from memory.
295 ; Note that logical operations assume unsigned integers whereas
296 ; arithmetic operations assume signed integers. Note that the C4x
297 ; small immediate constant (J) used as src2 in three operand instructions
298 ; is always signed. not_uint16 refers to a number that fits into 16-bits
299 ; when one's complemented.
300 ;
301 (define_attr "data" "int16,uint16,high_16,not_uint16" (const_string "int16"))
303 (define_asm_attributes
304 [(set_attr "type" "multi")])
306 ;
307 ; C4x DELAY SLOTS
308 ;
309 ; Define delay slot scheduling for branch and call instructions.
310 ; The C[34]x has three delay slots. Note that none of the three instructions
311 ; that follow a delayed branch can be a Bcond, BcondD, BR, BRD, DBcond,
312 ; DBcondD, CALL, CALLcond, TRAPcond, RETIcond, RETScond, RPTB, RPTS, or IDLE.
313 ;
314 ; Annulled branches are a bit difficult because the next instructions
315 ; are preprocessed.
316 ; The table below shows what phase of the c4x is executed.
317 ; BccA[TF] label
318 ; op1 fetch, decode and read executed
319 ; op2 fetch and decode executed
320 ; op3 fetch executed
321 ; This means that we can allow any instruction in the last delay slot
322 ; and only instructions which modify registers in the first two.
323 ; lda can not be executed in the first delay slot
324 ; and ldpk can not be executed in the first two delay slots.
326 (define_attr "onlyreg" "false,true"
327 (cond [(eq_attr "type" "unary,unarycc")
328 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
329 (match_operand 1 "reg_imm_operand" ""))
330 (const_string "true") (const_string "false"))
331 (eq_attr "type" "binary,binarycc")
332 (if_then_else (and (match_operand 0 "reg_imm_operand" "")
333 (and (match_operand 1 "reg_imm_operand" "")
334 (match_operand 2 "reg_imm_operand" "")))
335 (const_string "true") (const_string "false"))]
336 (const_string "false")))
338 (define_attr "onlyreg_nomod" "false,true"
339 (cond [(eq_attr "type" "unary,unarycc,compare,lda,store")
340 (if_then_else (and (match_operand 0 "not_modify_reg" "")
341 (match_operand 1 "not_modify_reg" ""))
342 (const_string "true") (const_string "false"))
343 (eq_attr "type" "binary,binarycc")
344 (if_then_else (and (match_operand 0 "not_modify_reg" "")
345 (and (match_operand 1 "not_modify_reg" "")
346 (match_operand 2 "not_modify_reg" "")))
347 (const_string "true") (const_string "false"))]
348 (const_string "false")))
350 (define_attr "not_repeat_reg" "false,true"
351 (cond [(eq_attr "type" "unary,unarycc,compare,lda,ldp,store")
352 (if_then_else (and (match_operand 0 "not_rc_reg" "")
353 (match_operand 1 "not_rc_reg" ""))
354 (const_string "true") (const_string "false"))
355 (eq_attr "type" "binary,binarycc")
356 (if_then_else (and (match_operand 0 "not_rc_reg" "")
357 (and (match_operand 1 "not_rc_reg" "")
358 (match_operand 2 "not_rc_reg" "")))
359 (const_string "true") (const_string "false"))]
360 (const_string "false")))
362 /* Disable compare because the c4x contains a bug. The cmpi insn sets the CC
363 in the read phase of the pipeline instead of the execution phase when
364 two registers are compared. */
365 (define_attr "in_annul_slot_1" "false,true"
366 (if_then_else (and (and (eq_attr "cpu" "c4x")
367 (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi"))
368 (eq_attr "onlyreg" "true"))
369 (const_string "true")
370 (const_string "false")))
372 (define_attr "in_annul_slot_2" "false,true"
373 (if_then_else (and (and (eq_attr "cpu" "c4x")
374 (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
375 (eq_attr "onlyreg_nomod" "true"))
376 (const_string "true")
377 (const_string "false")))
379 /* Disable ldp because the c4x contains a bug. The ldp insn modifies
380 the dp register when the insn is anulled or not.
381 Also disable autoincrement insns because of a silicon bug. */
382 (define_attr "in_annul_slot_3" "false,true"
383 (if_then_else (and (and (eq_attr "cpu" "c4x")
384 (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi"))
385 (eq_attr "onlyreg_nomod" "true"))
386 (const_string "true")
387 (const_string "false")))
389 (define_attr "in_delay_slot" "false,true"
390 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
391 (const_string "true")
392 (const_string "false")))
394 (define_attr "in_repeat_slot" "false,true"
395 (if_then_else (and (eq_attr "cpu" "c4x")
396 (and (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi")
397 (eq_attr "not_repeat_reg" "true")))
398 (const_string "true")
399 (const_string "false")))
401 (define_attr "in_dbc_slot" "false,true"
402 (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,multi")
403 (const_string "true")
404 (const_string "false")))
406 (define_delay (eq_attr "type" "jmpc")
407 [(eq_attr "in_delay_slot" "true")
408 (eq_attr "in_annul_slot_1" "true")
409 (eq_attr "in_annul_slot_1" "true")
411 (eq_attr "in_delay_slot" "true")
412 (eq_attr "in_annul_slot_2" "true")
413 (eq_attr "in_annul_slot_2" "true")
415 (eq_attr "in_delay_slot" "true")
416 (eq_attr "in_annul_slot_3" "true")
417 (eq_attr "in_annul_slot_3" "true") ])
420 (define_delay (eq_attr "type" "repeat_top")
421 [(eq_attr "in_repeat_slot" "true") (nil) (nil)
422 (eq_attr "in_repeat_slot" "true") (nil) (nil)
423 (eq_attr "in_repeat_slot" "true") (nil) (nil)])
425 (define_delay (eq_attr "type" "jump,db")
426 [(eq_attr "in_delay_slot" "true") (nil) (nil)
427 (eq_attr "in_delay_slot" "true") (nil) (nil)
428 (eq_attr "in_delay_slot" "true") (nil) (nil)])
431 ; Decrement and branch conditional instructions cannot modify the
432 ; condition codes for the cycles in the delay slots.
433 ;
434 (define_delay (eq_attr "type" "dbc")
435 [(eq_attr "in_dbc_slot" "true") (nil) (nil)
436 (eq_attr "in_dbc_slot" "true") (nil) (nil)
437 (eq_attr "in_dbc_slot" "true") (nil) (nil)])
439 ; The LAJ instruction has three delay slots but the last slot is
440 ; used for pushing the return address. Thus we can only use two slots.
441 ;
442 (define_delay (eq_attr "type" "laj")
443 [(eq_attr "in_delay_slot" "true") (nil) (nil)
444 (eq_attr "in_delay_slot" "true") (nil) (nil)])
446 ;
447 ; C4x UNSPEC NUMBERS
448 ;
449 ; 1 BU/BUD
450 ; 2 RPTS
451 ; 3 LSH
452 ; 4 cmphi
453 ; 5 RCPF
454 ; 6 RND
455 ; 7 repeat block filler
456 ; 8 loadhf_int
457 ; 9 storehf_int
458 ; 10 RSQRF
459 ; 11 loadqf_int
460 ; 12 storeqf_int
461 ; 13 Conditional load on overflow
462 ; 14 push_st
463 ; 15 pop_st
464 ; 16 push_dp
465 ; 17 pop_dp
466 ; 18 popqi_unspec
467 ; 19 popqf_unspec
468 ; 20 andn_st
469 ; 22 rptb_init
470 ; 23 toieee
471 ; 24 frieee
473 ;
474 ; C4x FUNCTIONAL UNITS
475 ;
476 ; Define functional units for instruction scheduling to minimise
477 ; pipeline conflicts.
478 ;
479 ; With the C3x, an external memory write (with no wait states) takes
480 ; two cycles and an external memory read (with no wait states) takes
481 ; one cycle. However, an external read following an external write
482 ; takes two cycles. With internal memory, reads and writes take
483 ; half a cycle.
484 ;
485 ; When a C4x address register is loaded it will not be available for
486 ; an extra machine cycle. Calculating with a C4x address register
487 ; makes it unavailable for 2 machine cycles. To notify GCC of these
488 ; pipeline delays, each of the auxiliary and index registers are declared
489 ; as separate functional units.
490 ;
491 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
492 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
493 ;
494 ; MULTIPLICITY 1 (C4x has no independent identical function units)
495 ; SIMULTANEITY 0 (C4x is pipelined)
496 ; READY_DELAY 1 (Results usually ready after every cyle)
497 ; ISSUE_DELAY 1 (Can issue insns every cycle)
499 ; Just some dummy definitions. The real work is done in c4x_adjust_cost.
500 ; These are needed so the min/max READY_DELAY is known.
502 (define_function_unit "dummy" 1 0 (const_int 0) 1 1)
503 (define_function_unit "dummy" 1 0 (const_int 0) 2 1)
504 (define_function_unit "dummy" 1 0 (const_int 0) 3 1)
506 ; The attribute setar0 is set to 1 for insns where ar0 is a dst operand.
507 ; Note that the attributes unarycc and binarycc do not apply
508 ; if ar0 is a dst operand (only loading an ext. prec. reg. sets CC)
509 (define_attr "setar0" ""
510 (cond [(eq_attr "type" "unary,binary")
511 (if_then_else (match_operand 0 "ar0_reg_operand" "")
512 (const_int 1) (const_int 0))]
513 (const_int 0)))
515 (define_attr "setlda_ar0" ""
516 (cond [(eq_attr "type" "lda")
517 (if_then_else (match_operand 0 "ar0_reg_operand" "")
518 (const_int 1) (const_int 0))]
519 (const_int 0)))
521 ; The attribute usear0 is set to 1 for insns where ar0 is used
522 ; for addressing, as a src operand, or as a dst operand.
523 (define_attr "usear0" ""
524 (cond [(eq_attr "type" "compare,store")
525 (if_then_else (match_operand 0 "ar0_mem_operand" "")
526 (const_int 1) (const_int 0))
527 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
528 (if_then_else (match_operand 1 "ar0_mem_operand" "")
529 (const_int 1) (const_int 0))
530 (eq_attr "type" "binary,binarycc")
531 (if_then_else (match_operand 2 "ar0_mem_operand" "")
532 (const_int 1) (const_int 0))
533 (eq_attr "type" "db,dbc")
534 (if_then_else (match_operand 0 "ar0_reg_operand" "")
535 (const_int 1) (const_int 0))]
536 (const_int 0)))
538 ; The attribute readar0 is set to 1 for insns where ar0 is a src operand.
539 (define_attr "readar0" ""
540 (cond [(eq_attr "type" "compare")
541 (if_then_else (match_operand 0 "ar0_reg_operand" "")
542 (const_int 1) (const_int 0))
543 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
544 (if_then_else (match_operand 1 "ar0_reg_operand" "")
545 (const_int 1) (const_int 0))
546 (eq_attr "type" "binary,binarycc")
547 (if_then_else (match_operand 2 "ar0_reg_operand" "")
548 (const_int 1) (const_int 0))]
549 (const_int 0)))
551 (define_attr "setar1" ""
552 (cond [(eq_attr "type" "unary,binary")
553 (if_then_else (match_operand 0 "ar1_reg_operand" "")
554 (const_int 1) (const_int 0))]
555 (const_int 0)))
557 (define_attr "setlda_ar1" ""
558 (cond [(eq_attr "type" "lda")
559 (if_then_else (match_operand 0 "ar1_reg_operand" "")
560 (const_int 1) (const_int 0))]
561 (const_int 0)))
563 (define_attr "usear1" ""
564 (cond [(eq_attr "type" "compare,store")
565 (if_then_else (match_operand 0 "ar1_mem_operand" "")
566 (const_int 1) (const_int 0))
567 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
568 (if_then_else (match_operand 1 "ar1_mem_operand" "")
569 (const_int 1) (const_int 0))
570 (eq_attr "type" "binary,binarycc")
571 (if_then_else (match_operand 2 "ar1_mem_operand" "")
572 (const_int 1) (const_int 0))
573 (eq_attr "type" "db,dbc")
574 (if_then_else (match_operand 0 "ar1_reg_operand" "")
575 (const_int 1) (const_int 0))]
576 (const_int 0)))
578 (define_attr "readar1" ""
579 (cond [(eq_attr "type" "compare")
580 (if_then_else (match_operand 0 "ar1_reg_operand" "")
581 (const_int 1) (const_int 0))
582 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
583 (if_then_else (match_operand 1 "ar1_reg_operand" "")
584 (const_int 1) (const_int 0))
585 (eq_attr "type" "binary,binarycc")
586 (if_then_else (match_operand 2 "ar1_reg_operand" "")
587 (const_int 1) (const_int 0))]
588 (const_int 0)))
590 (define_attr "setar2" ""
591 (cond [(eq_attr "type" "unary,binary")
592 (if_then_else (match_operand 0 "ar2_reg_operand" "")
593 (const_int 1) (const_int 0))]
594 (const_int 0)))
596 (define_attr "setlda_ar2" ""
597 (cond [(eq_attr "type" "lda")
598 (if_then_else (match_operand 0 "ar2_reg_operand" "")
599 (const_int 1) (const_int 0))]
600 (const_int 0)))
602 (define_attr "usear2" ""
603 (cond [(eq_attr "type" "compare,store")
604 (if_then_else (match_operand 0 "ar2_mem_operand" "")
605 (const_int 1) (const_int 0))
606 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
607 (if_then_else (match_operand 1 "ar2_mem_operand" "")
608 (const_int 1) (const_int 0))
609 (eq_attr "type" "binary,binarycc")
610 (if_then_else (match_operand 2 "ar2_mem_operand" "")
611 (const_int 1) (const_int 0))
612 (eq_attr "type" "db,dbc")
613 (if_then_else (match_operand 0 "ar2_reg_operand" "")
614 (const_int 1) (const_int 0))]
615 (const_int 0)))
617 (define_attr "readar2" ""
618 (cond [(eq_attr "type" "compare")
619 (if_then_else (match_operand 0 "ar2_reg_operand" "")
620 (const_int 1) (const_int 0))
621 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
622 (if_then_else (match_operand 1 "ar2_reg_operand" "")
623 (const_int 1) (const_int 0))
624 (eq_attr "type" "binary,binarycc")
625 (if_then_else (match_operand 2 "ar2_reg_operand" "")
626 (const_int 1) (const_int 0))]
627 (const_int 0)))
629 (define_attr "setar3" ""
630 (cond [(eq_attr "type" "unary,binary")
631 (if_then_else (match_operand 0 "ar3_reg_operand" "")
632 (const_int 1) (const_int 0))]
633 (const_int 0)))
635 (define_attr "setlda_ar3" ""
636 (cond [(eq_attr "type" "lda")
637 (if_then_else (match_operand 0 "ar3_reg_operand" "")
638 (const_int 1) (const_int 0))]
639 (const_int 0)))
641 (define_attr "usear3" ""
642 (cond [(eq_attr "type" "compare,store")
643 (if_then_else (match_operand 0 "ar3_mem_operand" "")
644 (const_int 1) (const_int 0))
645 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
646 (if_then_else (match_operand 1 "ar3_mem_operand" "")
647 (const_int 1) (const_int 0))
648 (eq_attr "type" "binary,binarycc")
649 (if_then_else (match_operand 2 "ar3_mem_operand" "")
650 (const_int 1) (const_int 0))
651 (eq_attr "type" "db,dbc")
652 (if_then_else (match_operand 0 "ar3_reg_operand" "")
653 (const_int 1) (const_int 0))]
654 (const_int 0)))
656 (define_attr "readar3" ""
657 (cond [(eq_attr "type" "compare")
658 (if_then_else (match_operand 0 "ar3_reg_operand" "")
659 (const_int 1) (const_int 0))
660 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
661 (if_then_else (match_operand 1 "ar3_reg_operand" "")
662 (const_int 1) (const_int 0))
663 (eq_attr "type" "binary,binarycc")
664 (if_then_else (match_operand 2 "ar3_reg_operand" "")
665 (const_int 1) (const_int 0))]
666 (const_int 0)))
668 (define_attr "setar4" ""
669 (cond [(eq_attr "type" "unary,binary")
670 (if_then_else (match_operand 0 "ar4_reg_operand" "")
671 (const_int 1) (const_int 0))]
672 (const_int 0)))
674 (define_attr "setlda_ar4" ""
675 (cond [(eq_attr "type" "lda")
676 (if_then_else (match_operand 0 "ar4_reg_operand" "")
677 (const_int 1) (const_int 0))]
678 (const_int 0)))
680 (define_attr "usear4" ""
681 (cond [(eq_attr "type" "compare,store")
682 (if_then_else (match_operand 0 "ar4_mem_operand" "")
683 (const_int 1) (const_int 0))
684 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
685 (if_then_else (match_operand 1 "ar4_mem_operand" "")
686 (const_int 1) (const_int 0))
687 (eq_attr "type" "binary,binarycc")
688 (if_then_else (match_operand 2 "ar4_mem_operand" "")
689 (const_int 1) (const_int 0))
690 (eq_attr "type" "db,dbc")
691 (if_then_else (match_operand 0 "ar4_reg_operand" "")
692 (const_int 1) (const_int 0))]
693 (const_int 0)))
695 (define_attr "readar4" ""
696 (cond [(eq_attr "type" "compare")
697 (if_then_else (match_operand 0 "ar4_reg_operand" "")
698 (const_int 1) (const_int 0))
699 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
700 (if_then_else (match_operand 1 "ar4_reg_operand" "")
701 (const_int 1) (const_int 0))
702 (eq_attr "type" "binary,binarycc")
703 (if_then_else (match_operand 2 "ar4_reg_operand" "")
704 (const_int 1) (const_int 0))]
705 (const_int 0)))
707 (define_attr "setar5" ""
708 (cond [(eq_attr "type" "unary,binary")
709 (if_then_else (match_operand 0 "ar5_reg_operand" "")
710 (const_int 1) (const_int 0))]
711 (const_int 0)))
713 (define_attr "setlda_ar5" ""
714 (cond [(eq_attr "type" "lda")
715 (if_then_else (match_operand 0 "ar5_reg_operand" "")
716 (const_int 1) (const_int 0))]
717 (const_int 0)))
719 (define_attr "usear5" ""
720 (cond [(eq_attr "type" "compare,store")
721 (if_then_else (match_operand 0 "ar5_mem_operand" "")
722 (const_int 1) (const_int 0))
723 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
724 (if_then_else (match_operand 1 "ar5_mem_operand" "")
725 (const_int 1) (const_int 0))
726 (eq_attr "type" "binary,binarycc")
727 (if_then_else (match_operand 2 "ar5_mem_operand" "")
728 (const_int 1) (const_int 0))
729 (eq_attr "type" "db,dbc")
730 (if_then_else (match_operand 0 "ar5_reg_operand" "")
731 (const_int 1) (const_int 0))]
732 (const_int 0)))
734 (define_attr "readar5" ""
735 (cond [(eq_attr "type" "compare")
736 (if_then_else (match_operand 0 "ar5_reg_operand" "")
737 (const_int 1) (const_int 0))
738 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
739 (if_then_else (match_operand 1 "ar5_reg_operand" "")
740 (const_int 1) (const_int 0))
741 (eq_attr "type" "binary,binarycc")
742 (if_then_else (match_operand 2 "ar5_reg_operand" "")
743 (const_int 1) (const_int 0))]
744 (const_int 0)))
746 (define_attr "setar6" ""
747 (cond [(eq_attr "type" "unary,binary")
748 (if_then_else (match_operand 0 "ar6_reg_operand" "")
749 (const_int 1) (const_int 0))]
750 (const_int 0)))
752 (define_attr "setlda_ar6" ""
753 (cond [(eq_attr "type" "lda")
754 (if_then_else (match_operand 0 "ar6_reg_operand" "")
755 (const_int 1) (const_int 0))]
756 (const_int 0)))
758 (define_attr "usear6" ""
759 (cond [(eq_attr "type" "compare,store")
760 (if_then_else (match_operand 0 "ar6_mem_operand" "")
761 (const_int 1) (const_int 0))
762 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
763 (if_then_else (match_operand 1 "ar6_mem_operand" "")
764 (const_int 1) (const_int 0))
765 (eq_attr "type" "binary,binarycc")
766 (if_then_else (match_operand 2 "ar6_mem_operand" "")
767 (const_int 1) (const_int 0))
768 (eq_attr "type" "db,dbc")
769 (if_then_else (match_operand 0 "ar6_reg_operand" "")
770 (const_int 1) (const_int 0))]
771 (const_int 0)))
773 (define_attr "readar6" ""
774 (cond [(eq_attr "type" "compare")
775 (if_then_else (match_operand 0 "ar6_reg_operand" "")
776 (const_int 1) (const_int 0))
777 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
778 (if_then_else (match_operand 1 "ar6_reg_operand" "")
779 (const_int 1) (const_int 0))
780 (eq_attr "type" "binary,binarycc")
781 (if_then_else (match_operand 2 "ar6_reg_operand" "")
782 (const_int 1) (const_int 0))]
783 (const_int 0)))
785 (define_attr "setar7" ""
786 (cond [(eq_attr "type" "unary,binary")
787 (if_then_else (match_operand 0 "ar7_reg_operand" "")
788 (const_int 1) (const_int 0))]
789 (const_int 0)))
791 (define_attr "setlda_ar7" ""
792 (cond [(eq_attr "type" "lda")
793 (if_then_else (match_operand 0 "ar7_reg_operand" "")
794 (const_int 1) (const_int 0))]
795 (const_int 0)))
797 (define_attr "usear7" ""
798 (cond [(eq_attr "type" "compare,store")
799 (if_then_else (match_operand 0 "ar7_mem_operand" "")
800 (const_int 1) (const_int 0))
801 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
802 (if_then_else (match_operand 1 "ar7_mem_operand" "")
803 (const_int 1) (const_int 0))
804 (eq_attr "type" "binary,binarycc")
805 (if_then_else (match_operand 2 "ar7_mem_operand" "")
806 (const_int 1) (const_int 0))
807 (eq_attr "type" "db,dbc")
808 (if_then_else (match_operand 0 "ar7_reg_operand" "")
809 (const_int 1) (const_int 0))]
810 (const_int 0)))
812 (define_attr "readar7" ""
813 (cond [(eq_attr "type" "compare")
814 (if_then_else (match_operand 0 "ar7_reg_operand" "")
815 (const_int 1) (const_int 0))
816 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
817 (if_then_else (match_operand 1 "ar7_reg_operand" "")
818 (const_int 1) (const_int 0))
819 (eq_attr "type" "binary,binarycc")
820 (if_then_else (match_operand 2 "ar7_reg_operand" "")
821 (const_int 1) (const_int 0))]
822 (const_int 0)))
824 (define_attr "setir0" ""
825 (cond [(eq_attr "type" "unary,binary")
826 (if_then_else (match_operand 0 "ir0_reg_operand" "")
827 (const_int 1) (const_int 0))]
828 (const_int 0)))
830 (define_attr "setlda_ir0" ""
831 (cond [(eq_attr "type" "lda")
832 (if_then_else (match_operand 0 "ir0_reg_operand" "")
833 (const_int 1) (const_int 0))]
834 (const_int 0)))
836 (define_attr "useir0" ""
837 (cond [(eq_attr "type" "compare,store")
838 (if_then_else (match_operand 0 "ir0_mem_operand" "")
839 (const_int 1) (const_int 0))
840 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
841 (if_then_else (match_operand 1 "ir0_mem_operand" "")
842 (const_int 1) (const_int 0))
843 (eq_attr "type" "binary,binarycc")
844 (if_then_else (match_operand 2 "ir0_mem_operand" "")
845 (const_int 1) (const_int 0))]
846 (const_int 0)))
848 (define_attr "setir1" ""
849 (cond [(eq_attr "type" "unary,binary")
850 (if_then_else (match_operand 0 "ir1_reg_operand" "")
851 (const_int 1) (const_int 0))]
852 (const_int 0)))
854 (define_attr "setlda_ir1" ""
855 (cond [(eq_attr "type" "lda")
856 (if_then_else (match_operand 0 "ir1_reg_operand" "")
857 (const_int 1) (const_int 0))]
858 (const_int 0)))
860 (define_attr "useir1" ""
861 (cond [(eq_attr "type" "compare,store")
862 (if_then_else (match_operand 0 "ir1_mem_operand" "")
863 (const_int 1) (const_int 0))
864 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc")
865 (if_then_else (match_operand 1 "ir1_mem_operand" "")
866 (const_int 1) (const_int 0))
867 (eq_attr "type" "binary,binarycc")
868 (if_then_else (match_operand 2 "ir1_mem_operand" "")
869 (const_int 1) (const_int 0))]
870 (const_int 0)))
872 ; With the C3x, things are simpler, but slower, i.e. more pipeline conflicts :(
873 ; There are three functional groups:
874 ; (1) AR0-AR7, IR0-IR1, BK
875 ; (2) DP
876 ; (3) SP
877 ;
878 ; When a register in one of these functional groups is loaded,
879 ; the contents of that or any other register in its group
880 ; will not be available to the next instruction for 2 machine cycles.
881 ; Similarly, when a register in one of the functional groups is read
882 ; excepting (IR0-IR1, BK, DP) the contents of that or any other register
883 ; in its group will not be available to the next instruction for
884 ; 1 machine cycle.
885 ;
886 ; Let's ignore functional groups 2 and 3 for now, since they are not
887 ; so important.
889 (define_attr "setgroup1" ""
890 (cond [(eq_attr "type" "lda,unary,binary")
891 (if_then_else (match_operand 0 "group1_reg_operand" "")
892 (const_int 1) (const_int 0))]
893 (const_int 0)))
895 (define_attr "usegroup1" ""
896 (cond [(eq_attr "type" "compare,store,store_store,store_load")
897 (if_then_else (match_operand 0 "group1_mem_operand" "")
898 (const_int 1) (const_int 0))
899 (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc,load_load,load_store")
900 (if_then_else (match_operand 1 "group1_mem_operand" "")
901 (const_int 1) (const_int 0))
902 (eq_attr "type" "store_store,load_store")
903 (if_then_else (match_operand 2 "group1_mem_operand" "")
904 (const_int 1) (const_int 0))
905 (eq_attr "type" "load_load,store_load")
906 (if_then_else (match_operand 3 "group1_mem_operand" "")
907 (const_int 1) (const_int 0))]
908 (const_int 0)))
910 (define_attr "readarx" ""
911 (cond [(eq_attr "type" "compare")
912 (if_then_else (match_operand 0 "arx_reg_operand" "")
913 (const_int 1) (const_int 0))
914 (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc")
915 (if_then_else (match_operand 1 "arx_reg_operand" "")
916 (const_int 1) (const_int 0))
917 (eq_attr "type" "binary,binarycc")
918 (if_then_else (match_operand 2 "arx_reg_operand" "")
919 (const_int 1) (const_int 0))]
920 (const_int 0)))
923 ;
924 ; C4x INSN PATTERNS:
925 ;
926 ; Note that the movMM and addP patterns can be called during reload
927 ; so we need to take special care with theses patterns since
928 ; we cannot blindly clobber CC or generate new pseudo registers.
930 ;
931 ; TWO OPERAND INTEGER INSTRUCTIONS
932 ;
934 ;
935 ; LDP/LDPK
936 ;
937 (define_insn "set_ldp"
938 [(set (match_operand:QI 0 "dp_reg_operand" "=z")
939 (high:QI (match_operand:QI 1 "" "")))]
940 "! TARGET_SMALL"
941 "* return (TARGET_C3X) ? \"ldp\\t%A1\" : \"ldpk\\t%A1\";"
942 [(set_attr "type" "ldp")])
944 (define_insn "set_ldp_prologue"
945 [(set (match_operand:QI 0 "dp_reg_operand" "=z")
946 (high:QI (match_operand:QI 1 "" "")))]
947 "TARGET_SMALL && TARGET_PARANOID"
948 "* return (TARGET_C3X) ? \"ldp\\t@data_sec\" : \"ldpk\\t@data_sec\";"
949 [(set_attr "type" "ldp")])
951 (define_insn "set_high"
952 [(set (match_operand:QI 0 "std_reg_operand" "=c")
953 (high:QI (match_operand:QI 1 "symbolic_address_operand" "")))]
954 "! TARGET_C3X && ! TARGET_TI"
955 "ldhi\\t^%H1,%0"
956 [(set_attr "type" "unary")])
958 (define_insn "set_lo_sum"
959 [(set (match_operand:QI 0 "std_reg_operand" "+c")
960 (lo_sum:QI (match_dup 0)
961 (match_operand:QI 1 "symbolic_address_operand" "")))]
962 "! TARGET_TI"
963 "or\\t#%H1,%0"
964 [(set_attr "type" "unary")])
966 (define_split
967 [(set (match_operand:QI 0 "std_reg_operand" "")
968 (match_operand:QI 1 "symbolic_address_operand" ""))]
969 "reload_completed && ! TARGET_C3X && ! TARGET_TI"
970 [(set (match_dup 0) (high:QI (match_dup 1)))
971 (set (match_dup 0) (lo_sum:QI (match_dup 0) (match_dup 1)))]
972 "")
974 (define_split
975 [(set (match_operand:QI 0 "reg_operand" "")
976 (match_operand:QI 1 "const_int_operand" ""))
977 (clobber (reg:QI 16))]
978 "! TARGET_C3X
979 && ! IS_INT16_CONST (INTVAL (operands[1]))
980 && ! IS_HIGH_CONST (INTVAL (operands[1]))
981 && reload_completed
982 && std_reg_operand (operands[0], QImode)"
983 [(set (match_dup 0) (match_dup 2))
984 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
985 "
986 {
987 operands[2] = GEN_INT (INTVAL (operands[1]) & ~0xffff);
988 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
989 }")
991 (define_split
992 [(set (match_operand:QI 0 "reg_operand" "")
993 (match_operand:QI 1 "const_int_operand" ""))]
994 "! TARGET_C3X
995 && ! IS_INT16_CONST (INTVAL (operands[1]))
996 && ! IS_HIGH_CONST (INTVAL (operands[1]))
997 && reload_completed
998 && std_reg_operand (operands[0], QImode)"
999 [(set (match_dup 0) (match_dup 2))
1000 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1001 "
1002 {
1003 operands[2] = GEN_INT (INTVAL (operands[1]) & ~0xffff);
1004 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1005 }")
1007 (define_split
1008 [(set (match_operand:QI 0 "reg_operand" "")
1009 (match_operand:QI 1 "const_int_operand" ""))
1010 (clobber (reg:QI 16))]
1011 "TARGET_C3X && ! TARGET_SMALL
1012 && ! IS_INT16_CONST (INTVAL (operands[1]))
1013 && reload_completed
1014 && std_reg_operand (operands[0], QImode)
1015 && c4x_shiftable_constant (operands[1]) < 0"
1016 [(set (match_dup 0) (match_dup 2))
1017 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
1018 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1019 "
1020 {
1021 /* Generate two's complement value of 16 MSBs. */
1022 operands[2] = gen_rtx (CONST_INT, VOIDmode,
1023 (((INTVAL (operands[1]) >> 16) & 0xffff)
1024 - 0x8000) ^ ~0x7fff);
1025 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1026 operands[4] = GEN_INT (16);
1027 }")
1029 (define_split
1030 [(set (match_operand:QI 0 "reg_operand" "")
1031 (match_operand:QI 1 "const_int_operand" ""))]
1032 "TARGET_C3X && ! TARGET_SMALL
1033 && ! IS_INT16_CONST (INTVAL (operands[1]))
1034 && reload_completed
1035 && std_reg_operand (operands[0], QImode)
1036 && c4x_shiftable_constant (operands[1]) < 0"
1037 [(set (match_dup 0) (match_dup 2))
1038 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
1039 (set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
1040 "
1041 {
1042 /* Generate two's complement value of 16 MSBs. */
1043 operands[2] = gen_rtx (CONST_INT, VOIDmode,
1044 (((INTVAL (operands[1]) >> 16) & 0xffff)
1045 - 0x8000) ^ ~0x7fff);
1046 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
1047 operands[4] = GEN_INT (16);
1048 }")
1050 (define_split
1051 [(set (match_operand:QI 0 "reg_operand" "")
1052 (match_operand:QI 1 "const_int_operand" ""))
1053 (clobber (reg:QI 16))]
1054 "TARGET_C3X
1055 && ! IS_INT16_CONST (INTVAL (operands[1]))
1056 && reload_completed
1057 && std_reg_operand (operands[0], QImode)
1058 && c4x_shiftable_constant (operands[1]) >= 0"
1059 [(set (match_dup 0) (match_dup 2))
1060 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
1061 "
1062 {
1063 /* Generate two's complement value of MSBs. */
1064 int shift = c4x_shiftable_constant (operands[1]);
1066 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
1067 - 0x8000) ^ ~0x7fff);
1068 operands[3] = GEN_INT (shift);
1069 }")
1071 (define_split
1072 [(set (match_operand:QI 0 "reg_operand" "")
1073 (match_operand:QI 1 "const_int_operand" ""))]
1074 "TARGET_C3X
1075 && ! IS_INT16_CONST (INTVAL (operands[1]))
1076 && reload_completed
1077 && std_reg_operand (operands[0], QImode)
1078 && c4x_shiftable_constant (operands[1]) >= 0"
1079 [(set (match_dup 0) (match_dup 2))
1080 (set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
1081 "
1082 {
1083 /* Generate two's complement value of MSBs. */
1084 int shift = c4x_shiftable_constant (operands[1]);
1086 operands[2] = GEN_INT ((((INTVAL (operands[1]) >> shift) & 0xffff)
1087 - 0x8000) ^ ~0x7fff);
1088 operands[3] = GEN_INT (shift);
1089 }")
1091 (define_split
1092 [(set (match_operand:QI 0 "reg_operand" "")
1093 (match_operand:QI 1 "const_int_operand" ""))
1094 (clobber (reg:QI 16))]
1095 "! TARGET_SMALL
1096 && ! IS_INT16_CONST (INTVAL (operands[1]))
1097 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1098 && reload_completed
1099 && ! std_reg_operand (operands[0], QImode)"
1100 [(set (match_dup 2) (high:QI (match_dup 3)))
1101 (set (match_dup 0) (match_dup 4))
1102 (use (match_dup 1))]
1103 "
1104 {
1105 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1106 operands[2] = dp_reg;
1107 operands[3] = force_const_mem (Pmode, operands[1]);
1108 operands[4] = change_address (operands[3], QImode,
1109 gen_rtx_LO_SUM (Pmode, dp_reg,
1110 XEXP (operands[3], 0)));
1111 operands[3] = XEXP (operands[3], 0);
1112 }")
1114 (define_split
1115 [(set (match_operand:QI 0 "reg_operand" "")
1116 (match_operand:QI 1 "const_int_operand" ""))]
1117 "! TARGET_SMALL
1118 && ! IS_INT16_CONST (INTVAL (operands[1]))
1119 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1120 && reload_completed
1121 && ! std_reg_operand (operands[0], QImode)"
1122 [(set (match_dup 2) (high:QI (match_dup 3)))
1123 (set (match_dup 0) (match_dup 4))
1124 (use (match_dup 1))]
1125 "
1126 {
1127 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1128 operands[2] = dp_reg;
1129 operands[3] = force_const_mem (Pmode, operands[1]);
1130 operands[4] = change_address (operands[3], QImode,
1131 gen_rtx_LO_SUM (Pmode, dp_reg,
1132 XEXP (operands[3], 0)));
1133 operands[3] = XEXP (operands[3], 0);
1134 }")
1136 (define_split
1137 [(set (match_operand:QI 0 "reg_operand" "")
1138 (match_operand:QI 1 "const_int_operand" ""))
1139 (clobber (reg:QI 16))]
1140 "TARGET_SMALL
1141 && ! IS_INT16_CONST (INTVAL (operands[1]))
1142 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1143 && reload_completed
1144 && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
1145 || ! std_reg_operand (operands[0], QImode))"
1146 [(set (match_dup 0) (match_dup 2))
1147 (use (match_dup 1))]
1148 "
1149 {
1150 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1151 operands[2] = force_const_mem (Pmode, operands[1]);
1152 operands[2] = change_address (operands[2], QImode,
1153 gen_rtx_LO_SUM (Pmode, dp_reg,
1154 XEXP (operands[2], 0)));
1155 }")
1157 (define_split
1158 [(set (match_operand:QI 0 "reg_operand" "")
1159 (match_operand:QI 1 "const_int_operand" ""))]
1160 "TARGET_SMALL
1161 && ! IS_INT16_CONST (INTVAL (operands[1]))
1162 && ! IS_HIGH_CONST (INTVAL (operands[1]))
1163 && reload_completed
1164 && ((TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0)
1165 || ! std_reg_operand (operands[0], QImode))"
1166 [(set (match_dup 0) (match_dup 2))
1167 (use (match_dup 1))]
1168 "
1169 {
1170 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1171 operands[2] = force_const_mem (Pmode, operands[1]);
1172 operands[2] = change_address (operands[2], QImode,
1173 gen_rtx_LO_SUM (Pmode, dp_reg,
1174 XEXP (operands[2], 0)));
1175 }")
1177 (define_split
1178 [(set (match_operand:HI 0 "reg_operand" "")
1179 (match_operand:HI 1 "const_int_operand" ""))
1180 (clobber (reg:QI 16))]
1181 "reload_completed"
1182 [(set (match_dup 2) (match_dup 4))
1183 (set (match_dup 3) (match_dup 5))]
1184 "
1185 {
1186 operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
1187 operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
1188 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
1189 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
1190 }")
1193 ; We need to clobber the DP reg to be safe in case we
1194 ; need to load this address from memory
1195 (define_insn "load_immed_address"
1196 [(set (match_operand:QI 0 "reg_operand" "=a?x?c*r")
1197 (match_operand:QI 1 "symbolic_address_operand" ""))
1198 (clobber (reg:QI 16))]
1199 "TARGET_LOAD_ADDRESS"
1200 "#"
1201 [(set_attr "type" "multi")])
1204 (define_split
1205 [(set (match_operand:QI 0 "std_reg_operand" "")
1206 (match_operand:QI 1 "symbolic_address_operand" ""))
1207 (clobber (reg:QI 16))]
1208 "reload_completed && ! TARGET_C3X && ! TARGET_TI"
1209 [(set (match_dup 0) (high:QI (match_dup 1)))
1210 (set (match_dup 0) (lo_sum:QI (match_dup 0) (match_dup 1)))]
1211 "")
1213 ; CC has been selected to load a symbolic address. We force the address
1214 ; into memory and then generate LDP and LDIU insns.
1215 ; This is also required for the C30 if we pretend that we can
1216 ; easily load symbolic addresses into a register.
1217 (define_split
1218 [(set (match_operand:QI 0 "reg_operand" "")
1219 (match_operand:QI 1 "symbolic_address_operand" ""))
1220 (clobber (reg:QI 16))]
1221 "reload_completed
1222 && ! TARGET_SMALL
1223 && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
1224 [(set (match_dup 2) (high:QI (match_dup 3)))
1225 (set (match_dup 0) (match_dup 4))
1226 (use (match_dup 1))]
1227 "
1228 {
1229 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1230 operands[2] = dp_reg;
1231 operands[3] = force_const_mem (Pmode, operands[1]);
1232 operands[4] = change_address (operands[3], QImode,
1233 gen_rtx_LO_SUM (Pmode, dp_reg,
1234 XEXP (operands[3], 0)));
1235 operands[3] = XEXP (operands[3], 0);
1236 }")
1238 ; This pattern is similar to the above but does not emit a LDP
1239 ; for the small memory model.
1240 (define_split
1241 [(set (match_operand:QI 0 "reg_operand" "")
1242 (match_operand:QI 1 "symbolic_address_operand" ""))
1243 (clobber (reg:QI 16))]
1244 "reload_completed
1245 && TARGET_SMALL
1246 && (TARGET_C3X || TARGET_TI || ! std_reg_operand (operands[0], QImode))"
1247 [(set (match_dup 0) (match_dup 2))
1248 (use (match_dup 1))]
1249 "
1250 {
1251 rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
1252 operands[2] = force_const_mem (Pmode, operands[1]);
1253 operands[2] = change_address (operands[2], QImode,
1254 gen_rtx_LO_SUM (Pmode, dp_reg,
1255 XEXP (operands[2], 0)));
1256 }")
1258 (define_insn "loadhi_big_constant"
1259 [(set (match_operand:HI 0 "reg_operand" "=c*d")
1260 (match_operand:HI 1 "const_int_operand" ""))
1261 (clobber (reg:QI 16))]
1262 ""
1263 "#"
1264 [(set_attr "type" "multi")])
1266 ;
1267 ; LDIU/LDA/STI/STIK
1268 ;
1269 ; The following moves will not set the condition codes register.
1270 ;
1272 ; This must come before the general case
1273 (define_insn "*movqi_stik"
1274 [(set (match_operand:QI 0 "memory_operand" "=m")
1275 (match_operand:QI 1 "stik_const_operand" "K"))]
1276 "! TARGET_C3X"
1277 "stik\\t%1,%0"
1278 [(set_attr "type" "store")])
1280 (define_insn "loadqi_big_constant"
1281 [(set (match_operand:QI 0 "reg_operand" "=c*d")
1282 (match_operand:QI 1 "const_int_operand" ""))
1283 (clobber (reg:QI 16))]
1284 "! IS_INT16_CONST (INTVAL (operands[1]))
1285 && ! IS_HIGH_CONST (INTVAL (operands[1]))"
1286 "#"
1287 [(set_attr "type" "multi")])
1289 ; We must provide an alternative to store to memory in case we have to
1290 ; spill a register.
1291 (define_insn "movqi_noclobber"
1292 [(set (match_operand:QI 0 "dst_operand" "=d,*c,m,r")
1293 (match_operand:QI 1 "src_hi_operand" "rIm,rIm,r,O"))]
1294 "(REG_P (operands[0]) || REG_P (operands[1])
1295 || GET_CODE (operands[0]) == SUBREG
1296 || GET_CODE (operands[1]) == SUBREG)
1297 && ! symbolic_address_operand (operands[1], QImode)"
1298 "*
1299 if (which_alternative == 2)
1300 return \"sti\\t%1,%0\";
1302 if (! TARGET_C3X && which_alternative == 3)
1303 {
1304 operands[1] = GEN_INT ((INTVAL (operands[1]) >> 16) & 0xffff);
1305 return \"ldhi\\t%1,%0\";
1306 }
1308 /* The lda instruction cannot use the same register as source
1309 and destination. */
1310 if (! TARGET_C3X && which_alternative == 1
1311 && ( IS_ADDR_REG (operands[0])
1312 || IS_INDEX_REG (operands[0])
1313 || IS_SP_REG (operands[0]))
1314 && (REGNO (operands[0]) != REGNO (operands[1])))
1315 return \"lda\\t%1,%0\";
1316 return \"ldiu\\t%1,%0\";
1317 "
1318 [(set_attr "type" "unary,lda,store,unary")
1319 (set_attr "data" "int16,int16,int16,high_16")])
1321 ;
1322 ; LDI
1323 ;
1325 ; We shouldn't need these peepholes, but the combiner seems to miss them...
1326 (define_peephole
1327 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1328 (match_operand:QI 1 "src_operand" "rIm"))
1329 (set (reg:CC 21)
1330 (compare:CC (match_dup 0) (const_int 0)))]
1331 ""
1332 "ldi\\t%1,%0"
1333 [(set_attr "type" "unarycc")
1334 (set_attr "data" "int16")])
1336 (define_insn "*movqi_set"
1337 [(set (reg:CC 21)
1338 (compare:CC (match_operand:QI 1 "src_operand" "rIm")
1339 (const_int 0)))
1340 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1341 (match_dup 1))]
1342 ""
1343 "ldi\\t%1,%0"
1344 [(set_attr "type" "unarycc")
1345 (set_attr "data" "int16")])
1347 ; This pattern probably gets in the way and requires a scratch register
1348 ; when a simple compare with zero will suffice.
1349 ;(define_insn "*movqi_test"
1350 ; [(set (reg:CC 21)
1351 ; (compare:CC (match_operand:QI 1 "src_operand" "rIm")
1352 ; (const_int 0)))
1353 ; (clobber (match_scratch:QI 0 "=d"))]
1354 ; ""
1355 ; "@
1356 ; ldi\\t%1,%0"
1357 ; [(set_attr "type" "unarycc")
1358 ; (set_attr "data" "int16")])
1360 ; If one of the operands is not a register, then we should
1361 ; emit two insns, using a scratch register. This will produce
1362 ; better code in loops if the source operand is invariant, since
1363 ; the source reload can be optimized out. During reload we cannot
1364 ; use change_address or force_reg which will allocate new pseudo regs.
1366 ; Unlike most other insns, the move insns can't be split with
1367 ; different predicates, because register spilling and other parts of
1368 ; the compiler, have memoized the insn number already.
1370 (define_expand "movqi"
1371 [(set (match_operand:QI 0 "general_operand" "")
1372 (match_operand:QI 1 "general_operand" ""))]
1373 ""
1374 "
1375 {
1376 if (c4x_emit_move_sequence (operands, QImode))
1377 DONE;
1378 }")
1381 ; As far as GCC is concerned, the moves are performed in parallel
1382 ; thus it must be convinced that there is no aliasing.
1383 ; It also assumes that the input operands are simultaneously loaded
1384 ; and then the output operands are simultaneously stored.
1385 ; With the C4x, if there are parallel stores to the same address
1386 ; both stores are executed.
1387 ; If there is a parallel load and store to the same address,
1388 ; the load is performed first.
1389 ; The problem with this pattern is that reload can spoil
1390 ; the show when it eliminates a reference to the frame pointer.
1391 ; This can invalidate the memory addressing mode, i.e., when
1392 ; the displacement is greater than 1.
1393 (define_insn "movqi_parallel"
1394 [(set (match_operand:QI 0 "parallel_operand" "=q,S<>!V,q,S<>!V")
1395 (match_operand:QI 1 "parallel_operand" "S<>!V,q,S<>!V,q"))
1396 (set (match_operand:QI 2 "parallel_operand" "=q,S<>!V,S<>!V,q")
1397 (match_operand:QI 3 "parallel_operand" "S<>!V,q,q,S<>!V"))]
1398 "TARGET_PARALLEL && valid_parallel_load_store (operands, QImode)"
1399 "@
1400 ldi1\\t%1,%0\\n||\\tldi2\\t%3,%2
1401 sti1\\t%1,%0\\n||\\tsti2\\t%3,%2
1402 ldi\\t%1,%0\\n||\\tsti\\t%3,%2
1403 ldi\\t%3,%2\\n||\\tsti\\t%1,%0"
1404 [(set_attr "type" "load_load,store_store,load_store,store_load")])
1406 ;
1407 ; PUSH/POP
1408 ;
1409 (define_insn "pushqi"
1410 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
1411 (match_operand:QI 0 "reg_operand" "r"))]
1412 ""
1413 "push\\t%0"
1414 [(set_attr "type" "push")])
1416 (define_insn "push_st"
1417 [(set (mem:QI (pre_inc:QI (reg:QI 20))) (unspec:QI [(reg:QI 21)] 14))
1418 (use (reg:QI 21))]
1419 ""
1420 "push\\tst"
1421 [(set_attr "type" "push")])
1423 (define_insn "push_dp"
1424 [(set (mem:QI (pre_inc:QI (reg:QI 20))) (unspec:QI [(reg:QI 16)] 16))
1425 (use (reg:QI 16))]
1426 ""
1427 "push\\tdp"
1428 [(set_attr "type" "push")])
1430 (define_insn "popqi"
1431 [(set (match_operand:QI 0 "reg_operand" "=r")
1432 (mem:QI (post_dec:QI (reg:QI 20))))
1433 (clobber (reg:CC 21))]
1434 ""
1435 "pop\\t%0"
1436 [(set_attr "type" "pop")])
1438 (define_insn "pop_st"
1439 [(set (unspec:QI [(reg:QI 21)] 15) (mem:QI (post_dec:QI (reg:QI 20))))
1440 (clobber (reg:CC 21))]
1441 ""
1442 "pop\\tst"
1443 [(set_attr "type" "pop")])
1445 (define_insn "pop_dp"
1446 [(set (unspec:QI [(reg:QI 16)] 17) (mem:QI (post_dec:QI (reg:QI 20))))
1447 (clobber (reg:CC 16))]
1448 ""
1449 "pop\\tdp"
1450 [(set_attr "type" "pop")])
1452 (define_insn "popqi_unspec"
1453 [(set (unspec:QI [(match_operand:QI 0 "reg_operand" "=r")] 18)
1454 (mem:QI (post_dec:QI (reg:QI 20))))
1455 (clobber (match_dup 0))
1456 (clobber (reg:CC 21))]
1457 ""
1458 "pop\\t%0"
1459 [(set_attr "type" "pop")])
1461 ;
1462 ; ABSI
1463 ;
1464 (define_expand "absqi2"
1465 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1466 (abs:QI (match_operand:QI 1 "src_operand" "")))
1467 (clobber (reg:CC_NOOV 21))])]
1468 ""
1469 "")
1471 (define_insn "*absqi2_clobber"
1472 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1473 (abs:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
1474 (clobber (reg:CC_NOOV 21))]
1475 ""
1476 "absi\\t%1,%0"
1477 [(set_attr "type" "unarycc,unary")
1478 (set_attr "data" "int16,int16")])
1480 (define_insn "*absqi2_noclobber"
1481 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1482 (abs:QI (match_operand:QI 1 "src_operand" "rIm")))]
1483 ""
1484 "absi\\t%1,%0"
1485 [(set_attr "type" "unary")
1486 (set_attr "data" "int16")])
1488 (define_split
1489 [(set (match_operand:QI 0 "std_reg_operand" "")
1490 (abs:QI (match_operand:QI 1 "src_operand" "")))
1491 (clobber (reg:CC_NOOV 21))]
1492 "reload_completed"
1493 [(set (match_dup 0)
1494 (abs:QI (match_dup 1)))]
1495 "")
1497 (define_insn "*absqi2_test"
1498 [(set (reg:CC_NOOV 21)
1499 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
1500 (const_int 0)))
1501 (clobber (match_scratch:QI 0 "=d"))]
1502 ""
1503 "absi\\t%1,%0"
1504 [(set_attr "type" "unarycc")
1505 (set_attr "data" "int16")])
1507 (define_insn "*absqi2_set"
1508 [(set (reg:CC_NOOV 21)
1509 (compare:CC_NOOV (abs:QI (match_operand:QI 1 "src_operand" "rIm"))
1510 (const_int 0)))
1511 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1512 (abs:QI (match_dup 1)))]
1513 ""
1514 "absi\\t%1,%0"
1515 [(set_attr "type" "unarycc")
1516 (set_attr "data" "int16")])
1518 ;
1519 ; NEGI
1520 ;
1521 (define_expand "negqi2"
1522 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1523 (neg:QI (match_operand:QI 1 "src_operand" "")))
1524 (clobber (reg:CC_NOOV 21))])]
1525 ""
1526 "")
1528 (define_insn "*negqi2_clobber"
1529 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1530 (neg:QI (match_operand:QI 1 "src_operand" "rIm,rIm")))
1531 (clobber (reg:CC_NOOV 21))]
1532 ""
1533 "negi\\t%1,%0"
1534 [(set_attr "type" "unarycc,unary")
1535 (set_attr "data" "int16,int16")])
1537 (define_insn "*negqi2_noclobber"
1538 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1539 (neg:QI (match_operand:QI 1 "src_operand" "rIm")))]
1540 ""
1541 "negi\\t%1,%0"
1542 [(set_attr "type" "unary")
1543 (set_attr "data" "int16")])
1545 (define_split
1546 [(set (match_operand:QI 0 "std_reg_operand" "")
1547 (neg:QI (match_operand:QI 1 "src_operand" "")))
1548 (clobber (reg:CC_NOOV 21))]
1549 "reload_completed"
1550 [(set (match_dup 0)
1551 (neg:QI (match_dup 1)))]
1552 "")
1554 (define_insn "*negqi2_test"
1555 [(set (reg:CC_NOOV 21)
1556 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
1557 (const_int 0)))
1558 (clobber (match_scratch:QI 0 "=d"))]
1559 ""
1560 "negi\\t%1,%0"
1561 [(set_attr "type" "unarycc")
1562 (set_attr "data" "int16")])
1564 (define_insn "*negqi2_set"
1565 [(set (reg:CC_NOOV 21)
1566 (compare:CC_NOOV (neg:QI (match_operand:QI 1 "src_operand" "rIm"))
1567 (const_int 0)))
1568 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1569 (neg:QI (match_dup 1)))]
1570 ""
1571 "negi\\t%1,%0"
1572 [(set_attr "type" "unarycc")
1573 (set_attr "data" "int16")])
1575 (define_insn "*negbqi2_clobber"
1576 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
1577 (neg:QI (match_operand:QI 1 "src_operand" "rIm")))
1578 (use (reg:CC_NOOV 21))
1579 (clobber (reg:CC_NOOV 21))]
1580 ""
1581 "negb\\t%1,%0"
1582 [(set_attr "type" "unarycc")
1583 (set_attr "data" "int16")])
1585 ;
1586 ; NOT
1587 ;
1588 (define_expand "one_cmplqi2"
1589 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1590 (not:QI (match_operand:QI 1 "lsrc_operand" "")))
1591 (clobber (reg:CC 21))])]
1592 ""
1593 "")
1595 (define_insn "*one_cmplqi2_clobber"
1596 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1597 (not:QI (match_operand:QI 1 "lsrc_operand" "rLm,rLm")))
1598 (clobber (reg:CC 21))]
1599 ""
1600 "not\\t%1,%0"
1601 [(set_attr "type" "unarycc,unary")
1602 (set_attr "data" "uint16,uint16")])
1604 (define_insn "*one_cmplqi2_noclobber"
1605 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1606 (not:QI (match_operand:QI 1 "lsrc_operand" "rLm")))]
1607 ""
1608 "not\\t%1,%0"
1609 [(set_attr "type" "unary")
1610 (set_attr "data" "uint16")])
1612 (define_split
1613 [(set (match_operand:QI 0 "std_reg_operand" "")
1614 (not:QI (match_operand:QI 1 "lsrc_operand" "")))
1615 (clobber (reg:CC 21))]
1616 "reload_completed"
1617 [(set (match_dup 0)
1618 (not:QI (match_dup 1)))]
1619 "")
1621 (define_insn "*one_cmplqi2_test"
1622 [(set (reg:CC 21)
1623 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
1624 (const_int 0)))
1625 (clobber (match_scratch:QI 0 "=d"))]
1626 ""
1627 "not\\t%1,%0"
1628 [(set_attr "type" "unarycc")
1629 (set_attr "data" "uint16")])
1631 (define_insn "*one_cmplqi2_set"
1632 [(set (reg:CC 21)
1633 (compare:CC (not:QI (match_operand:QI 1 "lsrc_operand" "rLm"))
1634 (const_int 0)))
1635 (set (match_operand:QI 0 "ext_reg_operand" "=d")
1636 (not:QI (match_dup 1)))]
1637 ""
1638 "not\\t%1,%0"
1639 [(set_attr "type" "unarycc")
1640 (set_attr "data" "uint16")])
1642 (define_insn "*one_cmplqi2_const_clobber"
1643 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1644 (match_operand:QI 1 "not_const_operand" "N,N"))
1645 (clobber (reg:CC 21))]
1646 ""
1647 "@
1648 not\\t%N1,%0
1649 not\\t%N1,%0"
1650 [(set_attr "type" "unarycc,unary")
1651 (set_attr "data" "not_uint16,not_uint16")])
1653 ; movqi can use this for loading an integer that can't normally
1654 ; fit into a 16-bit signed integer. The drawback is that it cannot
1655 ; go into R0-R11 since that will clobber the CC and movqi shouldn't
1656 ; do that. This can cause additional reloading but in most cases
1657 ; this will cause only an additional register move. With the large
1658 ; memory model we require an extra instruction to load DP anyway,
1659 ; if we're loading the constant from memory. The big advantage of
1660 ; allowing constants that satisfy not_const_operand in movqi, is that
1661 ; it allows andn to be generated more often.
1662 ; However, there is a problem if GCC has decided that it wants
1663 ; to use R0-R11, since we won't have a matching pattern...
1664 ; In interim, we prevent immed_const allowing `N' constants.
1665 (define_insn "*one_cmplqi2_const_noclobber"
1666 [(set (match_operand:QI 0 "std_reg_operand" "=c")
1667 (match_operand:QI 1 "not_const_operand" "N"))]
1668 ""
1669 "not\\t%N1,%0"
1670 [(set_attr "type" "unary")
1671 (set_attr "data" "not_uint16")])
1673 ;
1674 ; ROL
1675 ;
1676 (define_expand "rotlqi3"
1677 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1678 (rotate:QI (match_operand:QI 1 "reg_operand" "")
1679 (match_operand:QI 2 "const_int_operand" "")))
1680 (clobber (reg:CC 21))])]
1681 ""
1682 "if (INTVAL (operands[2]) > 4)
1683 FAIL; /* Open code as two shifts and an or */
1684 if (INTVAL (operands[2]) > 1)
1685 {
1686 int i;
1687 rtx tmp;
1689 /* If we have 4 or fewer shifts, then it is probably faster
1690 to emit separate ROL instructions. A C3x requires
1691 at least 4 instructions (a C4x requires at least 3), to
1692 perform a rotation by shifts. */
1694 tmp = operands[1];
1695 for (i = 0; i < INTVAL (operands[2]) - 1; i++)
1696 {
1697 tmp = gen_reg_rtx (QImode);
1698 emit_insn (gen_rotl_1_clobber (tmp, operands[1]));
1699 operands[1] = tmp;
1700 }
1701 emit_insn (gen_rotl_1_clobber (operands[0], tmp));
1702 DONE;
1703 }")
1705 (define_insn "rotl_1_clobber"
1706 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1707 (rotate:QI (match_operand:QI 1 "reg_operand" "0,0")
1708 (const_int 1)))
1709 (clobber (reg:CC 21))]
1710 ""
1711 "rol\\t%0"
1712 [(set_attr "type" "unarycc,unary")])
1713 ; Default to int16 data attr.
1715 ;
1716 ; ROR
1717 ;
1718 (define_expand "rotrqi3"
1719 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1720 (rotatert:QI (match_operand:QI 1 "reg_operand" "")
1721 (match_operand:QI 2 "const_int_operand" "")))
1722 (clobber (reg:CC 21))])]
1723 ""
1724 "if (INTVAL (operands[2]) > 4)
1725 FAIL; /* Open code as two shifts and an or */
1726 if (INTVAL (operands[2]) > 1)
1727 {
1728 int i;
1729 rtx tmp;
1731 /* If we have 4 or fewer shifts, then it is probably faster
1732 to emit separate ROL instructions. A C3x requires
1733 at least 4 instructions (a C4x requires at least 3), to
1734 perform a rotation by shifts. */
1736 tmp = operands[1];
1737 for (i = 0; i < INTVAL (operands[2]) - 1; i++)
1738 {
1739 tmp = gen_reg_rtx (QImode);
1740 emit_insn (gen_rotr_1_clobber (tmp, operands[1]));
1741 operands[1] = tmp;
1742 }
1743 emit_insn (gen_rotr_1_clobber (operands[0], tmp));
1744 DONE;
1745 }")
1747 (define_insn "rotr_1_clobber"
1748 [(set (match_operand:QI 0 "reg_operand" "=d,c")
1749 (rotatert:QI (match_operand:QI 1 "reg_operand" "0,0")
1750 (const_int 1)))
1751 (clobber (reg:CC 21))]
1752 ""
1753 "ror\\t%0"
1754 [(set_attr "type" "unarycc,unary")])
1755 ; Default to int16 data attr.
1758 ;
1759 ; THREE OPERAND INTEGER INSTRUCTIONS
1760 ;
1762 ;
1763 ; ADDI
1764 ;
1765 ; This is used by reload when it calls gen_add2_insn for address arithmetic
1766 ; so we must emit the pattern that doesn't clobber CC.
1767 ;
1768 (define_expand "addqi3"
1769 [(parallel [(set (match_operand:QI 0 "std_or_reg_operand" "")
1770 (plus:QI (match_operand:QI 1 "src_operand" "")
1771 (match_operand:QI 2 "src_operand" "")))
1772 (clobber (reg:CC_NOOV 21))])]
1773 ""
1774 "legitimize_operands (PLUS, operands, QImode);
1775 if (reload_in_progress
1776 || (! IS_PSEUDO_REG (operands[0])
1777 && ! IS_EXT_REG (operands[0])))
1778 {
1779 emit_insn (gen_addqi3_noclobber (operands[0], operands[1], operands[2]));
1780 DONE;
1781 }")
1783 (define_insn "*addqi3_clobber"
1784 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
1785 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
1786 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
1787 (clobber (reg:CC_NOOV 21))]
1788 "valid_operands (PLUS, operands, QImode)"
1789 "@
1790 addi\\t%2,%0
1791 addi3\\t%2,%1,%0
1792 addi3\\t%2,%1,%0
1793 addi\\t%2,%0
1794 addi3\\t%2,%1,%0
1795 addi3\\t%2,%1,%0"
1796 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1797 ; Default to int16 data attr.
1799 (define_split
1800 [(set (match_operand:QI 0 "std_reg_operand" "")
1801 (plus:QI (match_operand:QI 1 "src_operand" "")
1802 (match_operand:QI 2 "src_operand" "")))
1803 (clobber (reg:CC_NOOV 21))]
1804 "reload_completed"
1805 [(set (match_dup 0)
1806 (plus:QI (match_dup 1)
1807 (match_dup 2)))]
1808 "")
1810 (define_insn "*addqi3_test"
1811 [(set (reg:CC_NOOV 21)
1812 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1813 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
1814 (const_int 0)))
1815 (clobber (match_scratch:QI 0 "=d,d,d"))]
1816 "valid_operands (PLUS, operands, QImode)"
1817 "@
1818 addi\\t%2,%0
1819 addi3\\t%2,%1,%0
1820 addi3\\t%2,%1,%0"
1821 [(set_attr "type" "binarycc,binarycc,binarycc")])
1822 ; Default to int16 data attr.
1824 ; gcc does this in combine.c we just reverse it here
1825 (define_insn "*cmp_neg"
1826 [(set (reg:CC_NOOV 21)
1827 (compare:CC_NOOV (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1828 (neg: QI (match_operand:QI 2 "src_operand" "g,JR,rS<>"))))
1829 (clobber (match_scratch:QI 0 "=d,d,d"))]
1830 "valid_operands (PLUS, operands, QImode)"
1831 "@
1832 addi\\t%2,%0
1833 addi3\\t%2,%1,%0
1834 addi3\\t%2,%1,%0"
1835 [(set_attr "type" "binarycc,binarycc,binarycc")])
1837 (define_peephole
1838 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
1839 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1840 (match_operand:QI 2 "src_operand" "g,JR,rS<>")))
1841 (clobber (reg:CC_NOOV 21))])
1842 (set (reg:CC_NOOV 21)
1843 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1844 "valid_operands (PLUS, operands, QImode)"
1845 "@
1846 addi\\t%2,%0
1847 addi3\\t%2,%1,%0
1848 addi3\\t%2,%1,%0"
1849 [(set_attr "type" "binarycc,binarycc,binarycc")])
1851 (define_insn "*addqi3_set"
1852 [(set (reg:CC_NOOV 21)
1853 (compare:CC_NOOV (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1854 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
1855 (const_int 0)))
1856 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
1857 (plus:QI (match_dup 1) (match_dup 2)))]
1858 "valid_operands (PLUS, operands, QImode)"
1859 "@
1860 addi\\t%2,%0
1861 addi3\\t%2,%1,%0
1862 addi3\\t%2,%1,%0"
1863 [(set_attr "type" "binarycc,binarycc,binarycc")])
1864 ; Default to int16 data attr.
1866 ; This pattern is required primarily for manipulating the stack pointer
1867 ; where GCC doesn't expect CC to be clobbered or for calculating
1868 ; addresses during reload.
1869 (define_insn "addqi3_noclobber"
1870 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
1871 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1872 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
1873 "valid_operands (PLUS, operands, QImode)"
1874 "@
1875 addi\\t%2,%0
1876 addi3\\t%2,%1,%0
1877 addi3\\t%2,%1,%0"
1878 [(set_attr "type" "binary,binary,binary")])
1879 ; Default to int16 data attr.
1882 ; This pattern is required during reload when eliminate_regs_in_insn
1883 ; effectively converts a move insn into an add insn when the src
1884 ; operand is the frame pointer plus a constant. Without this
1885 ; pattern, gen_addqi3 can be called with a register for operand0
1886 ; that can clobber CC.
1887 ; For example, we may have (set (mem (reg ar0)) (reg 99))
1888 ; with (set (reg 99) (plus (reg ar3) (const_int 8)))
1889 ; Now since ar3, the frame pointer, is unchanging within the function,
1890 ; (plus (reg ar3) (const_int 8)) is considered a constant.
1891 ; eliminate_regs_in_insn substitutes this constant to give
1892 ; (set (mem (reg ar0)) (plus (reg ar3) (const_int 8))).
1893 ; This is an invalid C4x insn but if we don't provide a pattern
1894 ; for it, it will be considered to be a move insn for reloading.
1895 (define_insn "*addqi3_noclobber_reload"
1896 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
1897 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
1898 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
1899 "reload_in_progress"
1900 "@
1901 addi\\t%2,%0
1902 addi3\\t%2,%1,%0
1903 addi3\\t%2,%1,%0"
1904 [(set_attr "type" "binary,binary,binary")])
1905 ; Default to int16 data attr.
1908 (define_insn "*addqi3_carry_clobber"
1909 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
1910 (plus:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
1911 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
1912 (use (reg:CC_NOOV 21))
1913 (clobber (reg:CC_NOOV 21))]
1914 "valid_operands (PLUS, operands, QImode)"
1915 "@
1916 addc\\t%2,%0
1917 addc3\\t%2,%1,%0
1918 addc3\\t%2,%1,%0
1919 addc\\t%2,%0
1920 addc3\\t%2,%1,%0
1921 addc3\\t%2,%1,%0"
1922 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
1923 ; Default to int16 data attr.
1926 ;
1927 ; SUBI/SUBRI
1928 ;
1929 (define_expand "subqi3"
1930 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
1931 (minus:QI (match_operand:QI 1 "src_operand" "")
1932 (match_operand:QI 2 "src_operand" "")))
1933 (clobber (reg:CC_NOOV 21))])]
1934 ""
1935 "legitimize_operands (MINUS, operands, QImode);")
1937 (define_insn "*subqi3_clobber"
1938 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
1939 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>,0,rIm,rR,rS<>")
1940 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>,rIm,0,JR,rS<>")))
1941 (clobber (reg:CC_NOOV 21))]
1942 "valid_operands (MINUS, operands, QImode)"
1943 "@
1944 subi\\t%2,%0
1945 subri\\t%1,%0
1946 subi3\\t%2,%1,%0
1947 subi3\\t%2,%1,%0
1948 subi\\t%2,%0
1949 subri\\t%1,%0
1950 subi3\\t%2,%1,%0
1951 subi3\\t%2,%1,%0"
1952 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
1953 ; Default to int16 data attr.
1955 (define_split
1956 [(set (match_operand:QI 0 "std_reg_operand" "")
1957 (minus:QI (match_operand:QI 1 "src_operand" "")
1958 (match_operand:QI 2 "src_operand" "")))
1959 (clobber (reg:CC_NOOV 21))]
1960 "reload_completed"
1961 [(set (match_dup 0)
1962 (minus:QI (match_dup 1)
1963 (match_dup 2)))]
1964 "")
1966 (define_insn "*subqi3_test"
1967 [(set (reg:CC_NOOV 21)
1968 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
1969 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
1970 (const_int 0)))
1971 (clobber (match_scratch:QI 0 "=d,d,d,?d"))]
1972 "valid_operands (MINUS, operands, QImode)"
1973 "@
1974 subi\\t%2,%0
1975 subri\\t%1,%0
1976 subi3\\t%2,%1,%0
1977 subi3\\t%2,%1,%0"
1978 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1979 ; Default to int16 data attr.
1981 (define_peephole
1982 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
1983 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
1984 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>")))
1985 (clobber (reg:CC_NOOV 21))])
1986 (set (reg:CC_NOOV 21)
1987 (compare:CC_NOOV (match_dup 0) (const_int 0)))]
1988 "valid_operands (MINUS, operands, QImode)"
1989 "@
1990 subi\\t%2,%0
1991 subri\\t%1,%0
1992 subi3\\t%2,%1,%0
1993 subi3\\t%2,%1,%0"
1994 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
1996 (define_insn "*subqi3_set"
1997 [(set (reg:CC_NOOV 21)
1998 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
1999 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
2000 (const_int 0)))
2001 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2002 (minus:QI (match_dup 1)
2003 (match_dup 2)))]
2004 "valid_operands (MINUS, operands, QImode)"
2005 "@
2006 subi\\t%2,%0
2007 subri\\t%1,%0
2008 subi3\\t%2,%1,%0
2009 subi3\\t%2,%1,%0"
2010 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2011 ; Default to int16 data attr.
2013 (define_insn "*subqi3_noclobber"
2014 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c,?c")
2015 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
2016 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>")))]
2017 "valid_operands (MINUS, operands, QImode)"
2018 "@
2019 subi\\t%2,%0
2020 subri\\t%1,%0
2021 subi3\\t%2,%1,%0
2022 subi3\\t%2,%1,%0"
2023 [(set_attr "type" "binary,binary,binary,binary")])
2024 ; Default to int16 data attr.
2026 (define_insn "*subqi3_carry_clobber"
2027 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
2028 (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>,0,rIm,rR,rS<>")
2029 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>,rIm,0,JR,rS<>")))
2030 (use (reg:CC_NOOV 21))
2031 (clobber (reg:CC_NOOV 21))]
2032 "valid_operands (MINUS, operands, QImode)"
2033 "@
2034 subb\\t%2,%0
2035 subrb\\t%1,%0
2036 subb3\\t%2,%1,%0
2037 subb3\\t%2,%1,%0
2038 subb\\t%2,%0
2039 subrb\\t%1,%0
2040 subb3\\t%2,%1,%0
2041 subb3\\t%2,%1,%0"
2042 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")])
2043 ; Default to int16 data attr.
2045 (define_insn "*subqi3_carry_set"
2046 [(set (reg:CC_NOOV 21)
2047 (compare:CC_NOOV (minus:QI (match_operand:QI 1 "src_operand" "0,rIm,rR,rS<>")
2048 (match_operand:QI 2 "src_operand" "rIm,0,JR,rS<>"))
2049 (const_int 0)))
2050 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2051 (minus:QI (match_dup 1)
2052 (match_dup 2)))
2053 (use (reg:CC_NOOV 21))]
2054 "valid_operands (MINUS, operands, QImode)"
2055 "@
2056 subb\\t%2,%0
2057 subrb\\t%1,%0
2058 subb3\\t%2,%1,%0
2059 subb3\\t%2,%1,%0"
2060 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
2061 ; Default to int16 data attr.
2063 ;
2064 ; MPYI
2065 ;
2066 (define_expand "mulqi3"
2067 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2068 (mult:QI (match_operand:QI 1 "src_operand" "")
2069 (match_operand:QI 2 "src_operand" "")))
2070 (clobber (reg:CC_NOOV 21))])]
2071 ""
2072 "if (TARGET_MPYI || (GET_CODE (operands[2]) == CONST_INT
2073 && exact_log2 (INTVAL (operands[2])) >= 0))
2074 legitimize_operands (MULT, operands, QImode);
2075 else
2076 {
2077 if (GET_CODE (operands[2]) == CONST_INT)
2078 {
2079 /* Let GCC try to synthesize the multiplication using shifts
2080 and adds. In most cases this will be more profitable than
2081 using the C3x MPYI. */
2082 FAIL;
2083 }
2084 if (operands[1] == operands[2])
2085 {
2086 /* Do the squaring operation in-line. */
2087 emit_insn (gen_sqrqi2_inline (operands[0], operands[1]));
2088 DONE;
2089 }
2090 if (TARGET_INLINE)
2091 {
2092 emit_insn (gen_mulqi3_inline (operands[0], operands[1],
2093 operands[2]));
2094 DONE;
2095 }
2096 c4x_emit_libcall3 (smul_optab->handlers[(int) QImode].libfunc,
2097 MULT, QImode, operands);
2098 DONE;
2099 }
2100 ")
2102 (define_insn "*mulqi3_clobber"
2103 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2104 (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2105 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2106 (clobber (reg:CC_NOOV 21))]
2107 "valid_operands (MULT, operands, QImode)"
2108 "*
2109 if (which_alternative == 0 || which_alternative == 3)
2110 {
2111 if (TARGET_C3X
2112 && GET_CODE (operands[2]) == CONST_INT
2113 && exact_log2 (INTVAL (operands[2])) >= 0)
2114 return \"ash\\t%L2,%0\";
2115 else
2116 return \"mpyi\\t%2,%0\";
2117 }
2118 else
2119 return \"mpyi3\\t%2,%1,%0\";"
2120 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2121 ; Default to int16 data attr.
2123 (define_insn "*mulqi3_test"
2124 [(set (reg:CC_NOOV 21)
2125 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2126 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2127 (const_int 0)))
2128 (clobber (match_scratch:QI 0 "=d,d,d"))]
2129 "valid_operands (MULT, operands, QImode)"
2130 "*
2131 if (which_alternative == 0)
2132 {
2133 if (TARGET_C3X
2134 && GET_CODE (operands[2]) == CONST_INT
2135 && exact_log2 (INTVAL (operands[2])) >= 0)
2136 return \"ash\\t%L2,%0\";
2137 else
2138 return \"mpyi\\t%2,%0\";
2139 }
2140 else
2141 return \"mpyi3\\t%2,%1,%0\";"
2142 [(set_attr "type" "binarycc,binarycc,binarycc")])
2143 ; Default to int16 data attr.
2145 (define_insn "*mulqi3_set"
2146 [(set (reg:CC_NOOV 21)
2147 (compare:CC_NOOV (mult:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2148 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2149 (const_int 0)))
2150 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2151 (mult:QI (match_dup 1)
2152 (match_dup 2)))]
2153 "valid_operands (MULT, operands, QImode)"
2154 "*
2155 if (which_alternative == 0)
2156 {
2157 if (TARGET_C3X
2158 && GET_CODE (operands[2]) == CONST_INT
2159 && exact_log2 (INTVAL (operands[2])) >= 0)
2160 return \"ash\\t%L2,%0\";
2161 else
2162 return \"mpyi\\t%2,%0\";
2163 }
2164 else
2165 return \"mpyi3\\t%2,%1,%0\";"
2166 [(set_attr "type" "binarycc,binarycc,binarycc")])
2167 ; Default to int16 data attr.
2169 ; The C3x multiply instruction assumes 24-bit signed integer operands
2170 ; and the 48-bit result is truncated to 32-bits.
2171 (define_insn "mulqi3_24_clobber"
2172 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2173 (mult:QI
2174 (sign_extend:QI
2175 (and:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2176 (const_int 16777215)))
2177 (sign_extend:QI
2178 (and:QI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")
2179 (const_int 16777215)))))
2180 (clobber (reg:CC_NOOV 21))]
2181 "TARGET_C3X && valid_operands (MULT, operands, QImode)"
2182 "@
2183 mpyi\\t%2,%0
2184 mpyi3\\t%2,%1,%0
2185 mpyi3\\t%2,%1,%0
2186 mpyi\\t%2,%0
2187 mpyi3\\t%2,%1,%0
2188 mpyi3\\t%2,%1,%0"
2189 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2190 ; Default to int16 data attr.
2193 ; Fast square function for C3x where TARGET_MPYI not asserted
2194 (define_expand "sqrqi2_inline"
2195 [(set (match_dup 7) (match_operand:QI 1 "src_operand" ""))
2196 (parallel [(set (match_dup 3)
2197 (lshiftrt:QI (match_dup 7) (const_int 16)))
2198 (clobber (reg:CC 21))])
2199 (parallel [(set (match_dup 2)
2200 (and:QI (match_dup 7) (const_int 65535)))
2201 (clobber (reg:CC 21))])
2202 (parallel [(set (match_dup 4)
2203 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
2204 (const_int 16777215)))
2205 (sign_extend:QI (and:QI (match_dup 2)
2206 (const_int 16777215)))))
2207 (clobber (reg:CC_NOOV 21))])
2208 (parallel [(set (match_dup 5)
2209 (mult:QI (sign_extend:QI (and:QI (match_dup 2)
2210 (const_int 16777215)))
2211 (sign_extend:QI (and:QI (match_dup 3)
2212 (const_int 16777215)))))
2213 (clobber (reg:CC_NOOV 21))])
2214 (parallel [(set (match_dup 6)
2215 (ashift:QI (match_dup 5) (const_int 17)))
2216 (clobber (reg:CC 21))])
2217 (parallel [(set (match_operand:QI 0 "reg_operand" "")
2218 (plus:QI (match_dup 4) (match_dup 6)))
2219 (clobber (reg:CC_NOOV 21))])]
2220 ""
2221 "
2222 operands[2] = gen_reg_rtx (QImode); /* a = val & 0xffff */
2223 operands[3] = gen_reg_rtx (QImode); /* b = val >> 16 */
2224 operands[4] = gen_reg_rtx (QImode); /* a * a */
2225 operands[5] = gen_reg_rtx (QImode); /* a * b */
2226 operands[6] = gen_reg_rtx (QImode); /* (a * b) << 17 */
2227 operands[7] = gen_reg_rtx (QImode); /* val */
2228 ")
2230 ; Inlined integer multiply for C3x
2231 (define_expand "mulqi3_inline"
2232 [(set (match_dup 12) (const_int -16))
2233 (set (match_dup 13) (match_operand:QI 1 "src_operand" ""))
2234 (set (match_dup 14) (match_operand:QI 2 "src_operand" ""))
2235 (parallel [(set (match_dup 4)
2236 (lshiftrt:QI (match_dup 13) (neg:QI (match_dup 12))))
2237 (clobber (reg:CC 21))])
2238 (parallel [(set (match_dup 6)
2239 (lshiftrt:QI (match_dup 14) (neg:QI (match_dup 12))))
2240 (clobber (reg:CC 21))])
2241 (parallel [(set (match_dup 3)
2242 (and:QI (match_dup 13)
2243 (const_int 65535)))
2244 (clobber (reg:CC 21))])
2245 (parallel [(set (match_dup 5)
2246 (and:QI (match_dup 14)
2247 (const_int 65535)))
2248 (clobber (reg:CC 21))])
2249 (parallel [(set (match_dup 7)
2250 (mult:QI (sign_extend:QI (and:QI (match_dup 4)
2251 (const_int 16777215)))
2252 (sign_extend:QI (and:QI (match_dup 5)
2253 (const_int 16777215)))))
2254 (clobber (reg:CC_NOOV 21))])
2255 (parallel [(set (match_dup 8)
2256 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
2257 (const_int 16777215)))
2258 (sign_extend:QI (and:QI (match_dup 5)
2259 (const_int 16777215)))))
2260 (clobber (reg:CC_NOOV 21))])
2261 (parallel [(set (match_dup 9)
2262 (mult:QI (sign_extend:QI (and:QI (match_dup 3)
2263 (const_int 16777215)))
2264 (sign_extend:QI (and:QI (match_dup 6)
2265 (const_int 16777215)))))
2266 (clobber (reg:CC_NOOV 21))])
2267 (parallel [(set (match_dup 10)
2268 (plus:QI (match_dup 7) (match_dup 9)))
2269 (clobber (reg:CC_NOOV 21))])
2270 (parallel [(set (match_dup 11)
2271 (ashift:QI (match_dup 10) (const_int 16)))
2272 (clobber (reg:CC 21))])
2273 (parallel [(set (match_operand:QI 0 "reg_operand" "")
2274 (plus:QI (match_dup 8) (match_dup 11)))
2275 (clobber (reg:CC_NOOV 21))])]
2276 "TARGET_C3X"
2277 "
2278 operands[3] = gen_reg_rtx (QImode); /* a = arg1 & 0xffff */
2279 operands[4] = gen_reg_rtx (QImode); /* b = arg1 >> 16 */
2280 operands[5] = gen_reg_rtx (QImode); /* a = arg2 & 0xffff */
2281 operands[6] = gen_reg_rtx (QImode); /* b = arg2 >> 16 */
2282 operands[7] = gen_reg_rtx (QImode); /* b * c */
2283 operands[8] = gen_reg_rtx (QImode); /* a * c */
2284 operands[9] = gen_reg_rtx (QImode); /* a * d */
2285 operands[10] = gen_reg_rtx (QImode); /* b * c + a * d */
2286 operands[11] = gen_reg_rtx (QImode); /* (b *c + a * d) << 16 */
2287 operands[12] = gen_reg_rtx (QImode); /* -16 */
2288 operands[13] = gen_reg_rtx (QImode); /* arg1 */
2289 operands[14] = gen_reg_rtx (QImode); /* arg2 */
2290 ")
2292 ;
2293 ; MPYSHI (C4x only)
2294 ;
2295 (define_expand "smulqi3_highpart"
2296 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2297 (truncate:QI
2298 (lshiftrt:HI
2299 (mult:HI
2300 (sign_extend:HI (match_operand:QI 1 "src_operand" ""))
2301 (sign_extend:HI (match_operand:QI 2 "src_operand" "")))
2302 (const_int 32))))
2303 (clobber (reg:CC_NOOV 21))])]
2304 ""
2305 "legitimize_operands (MULT, operands, QImode);
2306 if (TARGET_C3X)
2307 {
2308 c4x_emit_libcall_mulhi (smulhi3_libfunc, SIGN_EXTEND, QImode, operands);
2309 DONE;
2310 }
2311 ")
2313 (define_insn "*smulqi3_highpart_clobber"
2314 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2315 (truncate:QI
2316 (lshiftrt:HI
2317 (mult:HI
2318 (sign_extend:HI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>"))
2319 (sign_extend:HI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2320 (const_int 32))))
2321 (clobber (reg:CC_NOOV 21))]
2322 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2323 "@
2324 mpyshi\\t%2,%0
2325 mpyshi3\\t%2,%1,%0
2326 mpyshi3\\t%2,%1,%0
2327 mpyshi\\t%2,%0
2328 mpyshi3\\t%2,%1,%0
2329 mpyshi3\\t%2,%1,%0"
2330 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2331 (set_attr "data" "int16,int16,int16,int16,int16,int16")])
2333 (define_insn "*smulqi3_highpart_noclobber"
2334 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2335 (truncate:QI
2336 (lshiftrt:HI
2337 (mult:HI
2338 (sign_extend:HI (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2339 (sign_extend:HI (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))
2340 (const_int 32))))]
2341 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2342 "@
2343 mpyshi\\t%2,%0
2344 mpyshi3\\t%2,%1,%0
2345 mpyshi3\\t%2,%1,%0"
2346 [(set_attr "type" "binary,binary,binary")
2347 (set_attr "data" "int16,int16,int16")])
2349 ;
2350 ; MPYUHI (C4x only)
2351 ;
2352 (define_expand "umulqi3_highpart"
2353 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2354 (truncate:QI
2355 (lshiftrt:HI
2356 (mult:HI
2357 (zero_extend:HI (match_operand:QI 1
2358 "nonimmediate_src_operand" ""))
2359 (zero_extend:HI (match_operand:QI 2
2360 "nonimmediate_lsrc_operand" "")))
2361 (const_int 32))))
2362 (clobber (reg:CC_NOOV 21))])]
2363 ""
2364 "legitimize_operands (MULT, operands, QImode);
2365 if (TARGET_C3X)
2366 {
2367 c4x_emit_libcall_mulhi (umulhi3_libfunc, ZERO_EXTEND, QImode, operands);
2368 DONE;
2369 }
2370 ")
2372 (define_insn "*umulqi3_highpart_clobber"
2373 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2374 (truncate:QI
2375 (lshiftrt:HI
2376 (mult:HI
2377 (zero_extend:HI (match_operand:QI 1
2378 "nonimmediate_src_operand" "%0,rR,rS<>,0,rR,rS<>"))
2379 (zero_extend:HI (match_operand:QI 2
2380 "nonimmediate_lsrc_operand" "rm,R,rS<>,rm,R,rS<>")))
2381 (const_int 32))))
2382 (clobber (reg:CC_NOOV 21))]
2383 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2384 "@
2385 mpyuhi\\t%2,%0
2386 mpyuhi3\\t%2,%1,%0
2387 mpyuhi3\\t%2,%1,%0
2388 mpyuhi\\t%2,%0
2389 mpyuhi3\\t%2,%1,%0
2390 mpyuhi3\\t%2,%1,%0"
2391 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2392 (set_attr "data" "uint16,uint16,uint16,uint16,uint16,uint16")])
2394 (define_insn "*umulqi3_highpart_noclobber"
2395 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2396 (truncate:QI
2397 (lshiftrt:HI
2398 (mult:HI
2399 (zero_extend:HI (match_operand:QI 1
2400 "nonimmediate_src_operand" "0,rR,rS<>"))
2401 (zero_extend:HI (match_operand:QI 2
2402 "nonimmediate_lsrc_operand" "rm,R,rS<>")))
2403 (const_int 32))))]
2404 "! TARGET_C3X && valid_operands (MULT, operands, QImode)"
2405 "@
2406 mpyuhi\\t%2,%0
2407 mpyuhi3\\t%2,%1,%0
2408 mpyuhi3\\t%2,%1,%0"
2409 [(set_attr "type" "binary,binary,binary")
2410 (set_attr "data" "uint16,uint16,uint16")])
2412 ;
2413 ; AND
2414 ;
2415 (define_expand "andqi3"
2416 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2417 (and:QI (match_operand:QI 1 "src_operand" "")
2418 (match_operand:QI 2 "tsrc_operand" "")))
2419 (clobber (reg:CC 21))])]
2420 ""
2421 "legitimize_operands (AND, operands, QImode);")
2424 (define_insn "*andqi3_255_clobber"
2425 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2426 (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
2427 (const_int 255)))
2428 (clobber (reg:CC 21))]
2429 "! TARGET_C3X"
2430 "lbu0\\t%1,%0"
2431 [(set_attr "type" "unarycc,unary")])
2433 (define_insn "*andqi3_255_noclobber"
2434 [(set (match_operand:QI 0 "reg_operand" "=c")
2435 (and:QI (match_operand:QI 1 "src_operand" "mr")
2436 (const_int 255)))]
2437 "! TARGET_C3X"
2438 "lbu0\\t%1,%0"
2439 [(set_attr "type" "unary")])
2442 (define_insn "*andqi3_65535_clobber"
2443 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2444 (and:QI (match_operand:QI 1 "src_operand" "mr,mr")
2445 (const_int 65535)))
2446 (clobber (reg:CC 21))]
2447 "! TARGET_C3X"
2448 "lhu0\\t%1,%0"
2449 [(set_attr "type" "unarycc,unary")])
2451 (define_insn "*andqi3_65535_noclobber"
2452 [(set (match_operand:QI 0 "reg_operand" "=c")
2453 (and:QI (match_operand:QI 1 "src_operand" "mr")
2454 (const_int 65535)))]
2455 "! TARGET_C3X"
2456 "lhu0\\t%1,%0"
2457 [(set_attr "type" "unary")])
2459 (define_insn "*andqi3_clobber"
2460 [(set (match_operand:QI 0 "reg_operand" "=d,d,d,?d,c,c,c,?c")
2461 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>,0,0,rR,rS<>")
2462 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>,N,rLm,JR,rS<>")))
2463 (clobber (reg:CC 21))]
2464 "valid_operands (AND, operands, QImode)"
2465 "@
2466 andn\\t%N2,%0
2467 and\\t%2,%0
2468 and3\\t%2,%1,%0
2469 and3\\t%2,%1,%0
2470 andn\\t%N2,%0
2471 and\\t%2,%0
2472 and3\\t%2,%1,%0
2473 and3\\t%2,%1,%0"
2474 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc,binary,binary,binary,binary")
2475 (set_attr "data" "not_uint16,uint16,int16,uint16,not_uint16,uint16,int16,uint16")])
2477 (define_insn "*andqi3_noclobber"
2478 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c,?c")
2479 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2480 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>")))]
2481 "valid_operands (AND, operands, QImode)"
2482 "@
2483 andn\\t%N2,%0
2484 and\\t%2,%0
2485 and3\\t%2,%1,%0
2486 and3\\t%2,%1,%0"
2487 [(set_attr "type" "binary,binary,binary,binary")
2488 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2490 (define_insn "andn_st"
2491 [(set (unspec:QI [(reg:QI 21)] 20)
2492 (and:QI (unspec:QI [(reg:QI 21)] 20)
2493 (match_operand:QI 0 "" "N")))
2494 (use (match_dup 0))
2495 (use (reg:CC 21))
2496 (clobber (reg:CC 21))]
2497 ""
2498 "andn\\t%N0,st"
2499 [(set_attr "type" "misc")
2500 (set_attr "data" "not_uint16")])
2502 (define_split
2503 [(set (match_operand:QI 0 "std_reg_operand" "")
2504 (and:QI (match_operand:QI 1 "src_operand" "")
2505 (match_operand:QI 2 "tsrc_operand" "")))
2506 (clobber (reg:CC 21))]
2507 "reload_completed"
2508 [(set (match_dup 0)
2509 (and:QI (match_dup 1)
2510 (match_dup 2)))]
2511 "")
2513 (define_insn "*andqi3_test"
2514 [(set (reg:CC 21)
2515 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%0,r,rR,rS<>")
2516 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>"))
2517 (const_int 0)))
2518 (clobber (match_scratch:QI 0 "=d,X,X,?X"))]
2519 "valid_operands (AND, operands, QImode)"
2520 "@
2521 andn\\t%N2,%0
2522 tstb\\t%2,%1
2523 tstb3\\t%2,%1
2524 tstb3\\t%2,%1"
2525 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2526 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2528 (define_peephole
2529 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2530 (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2531 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>")))
2532 (clobber (reg:CC 21))])
2533 (set (reg:CC 21)
2534 (compare:CC (match_dup 0) (const_int 0)))]
2535 "valid_operands (AND, operands, QImode)"
2536 "@
2537 andn\\t%N2,%0
2538 and\\t%2,%0
2539 and3\\t%2,%1,%0
2540 and3\\t%2,%1,%0"
2541 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2542 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2544 (define_insn "*andqi3_set"
2545 [(set (reg:CC 21)
2546 (compare:CC (and:QI (match_operand:QI 1 "src_operand" "%0,0,rR,rS<>")
2547 (match_operand:QI 2 "tsrc_operand" "N,rLm,JR,rS<>"))
2548 (const_int 0)))
2549 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d,?d")
2550 (and:QI (match_dup 1)
2551 (match_dup 2)))]
2552 "valid_operands (AND, operands, QImode)"
2553 "@
2554 andn\\t%N2,%0
2555 and\\t%2,%0
2556 and3\\t%2,%1,%0
2557 and3\\t%2,%1,%0"
2558 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")
2559 (set_attr "data" "not_uint16,uint16,int16,uint16")])
2561 ;
2562 ; ANDN
2563 ;
2564 ; NB, this insn doesn't have commutative operands, but valid_operands
2565 ; assumes that the code AND does. We might have to kludge this if
2566 ; we make valid_operands stricter.
2567 (define_insn "*andnqi3_clobber"
2568 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2569 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>"))
2570 (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")))
2571 (clobber (reg:CC 21))]
2572 "valid_operands (AND, operands, QImode)"
2573 "@
2574 andn\\t%2,%0
2575 andn3\\t%2,%1,%0
2576 andn3\\t%2,%1,%0
2577 andn\\t%2,%0
2578 andn3\\t%2,%1,%0
2579 andn3\\t%2,%1,%0"
2580 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2581 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2583 (define_insn "*andnqi3_noclobber"
2584 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2585 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2586 (match_operand:QI 1 "src_operand" "0,rR,rS<>")))]
2587 "valid_operands (AND, operands, QImode)"
2588 "@
2589 andn\\t%2,%0
2590 andn3\\t%2,%1,%0
2591 andn3\\t%2,%1,%0"
2592 [(set_attr "type" "binary,binary,binary")
2593 (set_attr "data" "uint16,int16,uint16")])
2595 (define_split
2596 [(set (match_operand:QI 0 "std_reg_operand" "")
2597 (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" ""))
2598 (match_operand:QI 1 "src_operand" "")))
2599 (clobber (reg:CC 21))]
2600 "reload_completed"
2601 [(set (match_dup 0)
2602 (and:QI (not:QI (match_dup 2))
2603 (match_dup 1)))]
2604 "")
2606 (define_insn "*andnqi3_test"
2607 [(set (reg:CC 21)
2608 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2609 (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2610 (const_int 0)))
2611 (clobber (match_scratch:QI 0 "=d,d,d"))]
2612 "valid_operands (AND, operands, QImode)"
2613 "@
2614 andn\\t%2,%0
2615 andn3\\t%2,%1,%0
2616 andn3\\t%2,%1,%0"
2617 [(set_attr "type" "binarycc,binarycc,binarycc")
2618 (set_attr "data" "uint16,int16,uint16")])
2620 (define_insn "*andnqi3_set"
2621 [(set (reg:CC 21)
2622 (compare:CC (and:QI (not:QI (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2623 (match_operand:QI 1 "src_operand" "0,rR,rS<>"))
2624 (const_int 0)))
2625 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2626 (and:QI (not:QI (match_dup 2))
2627 (match_dup 1)))]
2628 "valid_operands (AND, operands, QImode)"
2629 "@
2630 andn\\t%2,%0
2631 andn3\\t%2,%1,%0
2632 andn3\\t%2,%1,%0"
2633 [(set_attr "type" "binarycc,binarycc,binarycc")
2634 (set_attr "data" "uint16,int16,uint16")])
2636 ;
2637 ; OR
2638 ;
2639 (define_expand "iorqi3"
2640 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2641 (ior:QI (match_operand:QI 1 "src_operand" "")
2642 (match_operand:QI 2 "lsrc_operand" "")))
2643 (clobber (reg:CC 21))])]
2644 ""
2645 "legitimize_operands (IOR, operands, QImode);")
2647 (define_insn "*iorqi3_clobber"
2648 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2649 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2650 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>")))
2651 (clobber (reg:CC 21))]
2652 "valid_operands (IOR, operands, QImode)"
2653 "@
2654 or\\t%2,%0
2655 or3\\t%2,%1,%0
2656 or3\\t%2,%1,%0
2657 or\\t%2,%0
2658 or3\\t%2,%1,%0
2659 or3\\t%2,%1,%0"
2660 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2661 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2663 (define_split
2664 [(set (match_operand:QI 0 "std_reg_operand" "")
2665 (ior:QI (match_operand:QI 1 "src_operand" "")
2666 (match_operand:QI 2 "lsrc_operand" "")))
2667 (clobber (reg:CC 21))]
2668 "reload_completed"
2669 [(set (match_dup 0)
2670 (ior:QI (match_dup 1)
2671 (match_dup 2)))]
2672 "")
2674 (define_insn "*iorqi3_test"
2675 [(set (reg:CC 21)
2676 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2677 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2678 (const_int 0)))
2679 (clobber (match_scratch:QI 0 "=d,d,d"))]
2680 "valid_operands (IOR, operands, QImode)"
2681 "@
2682 or\\t%2,%0
2683 or3\\t%2,%1,%0
2684 or3\\t%2,%1,%0"
2685 [(set_attr "type" "binarycc,binarycc,binarycc")
2686 (set_attr "data" "uint16,int16,uint16")])
2688 (define_peephole
2689 [(parallel [(set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2690 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2691 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))
2692 (clobber (reg:CC 21))])
2693 (set (reg:CC 21)
2694 (compare:CC (match_dup 0) (const_int 0)))]
2695 "valid_operands (IOR, operands, QImode)"
2696 "@
2697 or\\t%2,%0
2698 or3\\t%2,%1,%0
2699 or3\\t%2,%1,%0"
2700 [(set_attr "type" "binarycc,binarycc,binarycc")
2701 (set_attr "data" "uint16,int16,uint16")])
2703 (define_insn "*iorqi3_set"
2704 [(set (reg:CC 21)
2705 (compare:CC (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2706 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2707 (const_int 0)))
2708 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2709 (ior:QI (match_dup 1)
2710 (match_dup 2)))]
2711 "valid_operands (IOR, operands, QImode)"
2712 "@
2713 or\\t%2,%0
2714 or3\\t%2,%1,%0
2715 or3\\t%2,%1,%0"
2716 [(set_attr "type" "binarycc,binarycc,binarycc")
2717 (set_attr "data" "uint16,int16,uint16")])
2719 ; This pattern is used for loading symbol references in several parts.
2720 (define_insn "iorqi3_noclobber"
2721 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,c")
2722 (ior:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2723 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))]
2724 "valid_operands (IOR, operands, QImode)"
2725 "@
2726 or\\t%2,%0
2727 or3\\t%2,%1,%0
2728 or3\\t%2,%1,%0"
2729 [(set_attr "type" "binary,binary,binary")
2730 (set_attr "data" "uint16,int16,uint16")])
2732 ;
2733 ; XOR
2734 ;
2735 (define_expand "xorqi3"
2736 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2737 (xor:QI (match_operand:QI 1 "src_operand" "")
2738 (match_operand:QI 2 "lsrc_operand" "")))
2739 (clobber (reg:CC 21))])]
2740 ""
2741 "legitimize_operands (XOR, operands, QImode);")
2743 (define_insn "*xorqi3_clobber"
2744 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2745 (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>,0,rR,rS<>")
2746 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>,rLm,JR,rS<>")))
2747 (clobber (reg:CC 21))]
2748 "valid_operands (XOR, operands, QImode)"
2749 "@
2750 xor\\t%2,%0
2751 xor3\\t%2,%1,%0
2752 xor3\\t%2,%1,%0
2753 xor\\t%2,%0
2754 xor3\\t%2,%1,%0
2755 xor3\\t%2,%1,%0"
2756 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")
2757 (set_attr "data" "uint16,int16,uint16,uint16,int16,uint16")])
2759 (define_insn "*xorqi3_noclobber"
2760 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2761 (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2762 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>")))]
2763 "valid_operands (XOR, operands, QImode)"
2764 "@
2765 xor\\t%2,%0
2766 xor3\\t%2,%1,%0
2767 xor3\\t%2,%1,%0"
2768 [(set_attr "type" "binary,binary,binary")
2769 (set_attr "data" "uint16,int16,uint16")])
2771 (define_split
2772 [(set (match_operand:QI 0 "std_reg_operand" "")
2773 (xor:QI (match_operand:QI 1 "src_operand" "")
2774 (match_operand:QI 2 "lsrc_operand" "")))
2775 (clobber (reg:CC 21))]
2776 "reload_completed"
2777 [(set (match_dup 0)
2778 (xor:QI (match_dup 1)
2779 (match_dup 2)))]
2780 "")
2782 (define_insn "*xorqi3_test"
2783 [(set (reg:CC 21)
2784 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2785 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2786 (const_int 0)))
2787 (clobber (match_scratch:QI 0 "=d,d,d"))]
2788 "valid_operands (XOR, operands, QImode)"
2789 "@
2790 xor\\t%2,%0
2791 xor3\\t%2,%1,%0
2792 xor3\\t%2,%1,%0"
2793 [(set_attr "type" "binarycc,binarycc,binarycc")
2794 (set_attr "data" "uint16,int16,uint16")])
2796 (define_insn "*xorqi3_set"
2797 [(set (reg:CC 21)
2798 (compare:CC (xor:QI (match_operand:QI 1 "src_operand" "%0,rR,rS<>")
2799 (match_operand:QI 2 "lsrc_operand" "rLm,JR,rS<>"))
2800 (const_int 0)))
2801 (set (match_operand:QI 0 "ext_reg_operand" "=d,d,d")
2802 (xor:QI (match_dup 1)
2803 (match_dup 2)))]
2804 "valid_operands (XOR, operands, QImode)"
2805 "@
2806 xor\\t%2,%0
2807 xor3\\t%2,%1,%0
2808 xor3\\t%2,%1,%0"
2809 [(set_attr "type" "binarycc,binarycc,binarycc")
2810 (set_attr "data" "uint16,int16,uint16")])
2812 ;
2813 ; LSH/ASH (left)
2814 ;
2815 ; The C3x and C4x have two shift instructions ASH and LSH
2816 ; If the shift count is positive, a left shift is performed
2817 ; otherwise a right shift is performed. The number of bits
2818 ; shifted is determined by the seven LSBs of the shift count.
2819 ; If the absolute value of the count is 32 or greater, the result
2820 ; using the LSH instruction is zero; with the ASH insn the result
2821 ; is zero or negative 1. Note that the ISO C standard allows
2822 ; the result to be machine dependent whenever the shift count
2823 ; exceeds the size of the object.
2824 (define_expand "ashlqi3"
2825 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2826 (ashift:QI (match_operand:QI 1 "src_operand" "")
2827 (match_operand:QI 2 "src_operand" "")))
2828 (clobber (reg:CC 21))])]
2829 ""
2830 "legitimize_operands (ASHIFT, operands, QImode);")
2832 (define_insn "*ashlqi3_clobber"
2833 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2834 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
2835 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")))
2836 (clobber (reg:CC 21))]
2837 "valid_operands (ASHIFT, operands, QImode)"
2838 "@
2839 ash\\t%2,%0
2840 ash3\\t%2,%1,%0
2841 ash3\\t%2,%1,%0
2842 ash\\t%2,%0
2843 ash3\\t%2,%1,%0
2844 ash3\\t%2,%1,%0"
2845 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2846 ; Default to int16 data attr.
2848 (define_insn "*ashlqi3_set"
2849 [(set (reg:CC 21)
2850 (compare:CC
2851 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
2852 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>"))
2853 (const_int 0)))
2854 (set (match_operand:QI 0 "reg_operand" "=d,d,d")
2855 (ashift:QI (match_dup 1)
2856 (match_dup 2)))]
2857 "valid_operands (ASHIFT, operands, QImode)"
2858 "@
2859 ash\\t%2,%0
2860 ash3\\t%2,%1,%0
2861 ash3\\t%2,%1,%0"
2862 [(set_attr "type" "binarycc,binarycc,binarycc")])
2863 ; Default to int16 data attr.
2865 (define_insn "ashlqi3_noclobber"
2866 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
2867 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
2868 (match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
2869 "valid_operands (ASHIFT, operands, QImode)"
2870 "@
2871 ash\\t%2,%0
2872 ash3\\t%2,%1,%0
2873 ash3\\t%2,%1,%0"
2874 [(set_attr "type" "binary,binary,binary")])
2875 ; Default to int16 data attr.
2877 (define_split
2878 [(set (match_operand:QI 0 "std_reg_operand" "")
2879 (ashift:QI (match_operand:QI 1 "src_operand" "")
2880 (match_operand:QI 2 "src_operand" "")))
2881 (clobber (reg:CC 21))]
2882 "reload_completed"
2883 [(set (match_dup 0)
2884 (ashift:QI (match_dup 1)
2885 (match_dup 2)))]
2886 "")
2888 ; This is only used by lshrhi3_reg where we need a LSH insn that will
2889 ; shift both ways.
2890 (define_insn "*lshlqi3_clobber"
2891 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
2892 (ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
2893 (unspec:QI [(match_operand:QI 2 "src_operand" "rIm,JR,rS<>,rIm,JR,rS<>")] 3)))
2894 (clobber (reg:CC 21))]
2895 "valid_operands (ASHIFT, operands, QImode)"
2896 "@
2897 lsh\\t%2,%0
2898 lsh3\\t%2,%1,%0
2899 lsh3\\t%2,%1,%0
2900 lsh\\t%2,%0
2901 lsh3\\t%2,%1,%0
2902 lsh3\\t%2,%1,%0"
2903 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
2904 ; Default to int16 data attr.
2906 ;
2907 ; LSH (right)
2908 ;
2909 ; Logical right shift on the C[34]x works by negating the shift count,
2910 ; then emitting a right shift with the shift count negated. This means
2911 ; that all actual shift counts in the RTL will be positive.
2912 ;
2913 (define_expand "lshrqi3"
2914 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
2915 (lshiftrt:QI (match_operand:QI 1 "src_operand" "")
2916 (match_operand:QI 2 "src_operand" "")))
2917 (clobber (reg:CC 21))])]
2918 ""
2919 "legitimize_operands (LSHIFTRT, operands, QImode);")
2922 (define_insn "*lshrqi3_24_clobber"
2923 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2924 (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2925 (const_int 24)))
2926 (clobber (reg:CC 21))]
2927 "! TARGET_C3X"
2928 "lbu3\\t%1,%0"
2929 [(set_attr "type" "unarycc")])
2932 (define_insn "*ashrqi3_24_clobber"
2933 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2934 (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2935 (const_int 24)))
2936 (clobber (reg:CC 21))]
2937 "! TARGET_C3X"
2938 "lb3\\t%1,%0"
2939 [(set_attr "type" "unarycc")])
2942 (define_insn "lshrqi3_16_clobber"
2943 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2944 (lshiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2945 (const_int 16)))
2946 (clobber (reg:CC 21))]
2947 "! TARGET_C3X"
2948 "lhu1\\t%1,%0"
2949 [(set_attr "type" "unarycc")])
2952 (define_insn "*ashrqi3_16_clobber"
2953 [(set (match_operand:QI 0 "reg_operand" "=d,c")
2954 (ashiftrt:QI (match_operand:QI 1 "src_operand" "mr,mr")
2955 (const_int 16)))
2956 (clobber (reg:CC 21))]
2957 "! TARGET_C3X"
2958 "lh1\\t%1,%0"
2959 [(set_attr "type" "unarycc")])
2962 ; When the shift count is greater than the size of the word
2963 ; the result can be implementation specific
2964 (define_insn "*lshrqi3_const_clobber"
2965 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
2966 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
2967 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
2968 (clobber (reg:CC 21))]
2969 "valid_operands (LSHIFTRT, operands, QImode)"
2970 "@
2971 lsh\\t%n2,%0
2972 lsh\\t%n2,%0
2973 lsh3\\t%n2,%1,%0
2974 lsh3\\t%n2,%1,%0"
2975 [(set_attr "type" "binarycc,binary,binarycc,binary")])
2977 (define_insn "*lshrqi3_const_noclobber"
2978 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c")
2979 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
2980 (match_operand:QI 2 "const_int_operand" "n,J")))]
2981 "valid_operands (LSHIFTRT, operands, QImode)"
2982 "@
2983 lsh\\t%n2,%0
2984 lsh3\\t%n2,%1,%0"
2985 [(set_attr "type" "binary,binary")])
2987 ; When the shift count is greater than the size of the word
2988 ; the result can be implementation specific
2989 (define_insn "*lshrqi3_const_set"
2990 [(set (reg:CC 21)
2991 (compare:CC
2992 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
2993 (match_operand:QI 2 "const_int_operand" "n,J"))
2994 (const_int 0)))
2995 (set (match_operand:QI 0 "reg_operand" "=?d,d")
2996 (lshiftrt:QI (match_dup 1)
2997 (match_dup 2)))]
2998 "valid_operands (LSHIFTRT, operands, QImode)"
2999 "@
3000 lsh\\t%n2,%0
3001 lsh3\\t%n2,%1,%0"
3002 [(set_attr "type" "binarycc,binarycc")])
3004 (define_insn "*lshrqi3_nonconst_clobber"
3005 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
3006 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
3007 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>,rm,R,rS<>"))))
3008 (clobber (reg:CC 21))]
3009 "valid_operands (LSHIFTRT, operands, QImode)"
3010 "@
3011 lsh\\t%2,%0
3012 lsh3\\t%2,%1,%0
3013 lsh3\\t%2,%1,%0
3014 lsh\\t%2,%0
3015 lsh3\\t%2,%1,%0
3016 lsh3\\t%2,%1,%0"
3017 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
3018 ; Default to int16 data attr.
3020 (define_insn "*lshrqi3_nonconst_noclobber"
3021 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
3022 (lshiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
3023 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>"))))]
3024 "valid_operands (LSHIFTRT, operands, QImode)"
3025 "@
3026 lsh\\t%2,%0
3027 lsh3\\t%2,%1,%0
3028 lsh3\\t%2,%1,%0"
3029 [(set_attr "type" "binary,binary,binary")])
3030 ; Default to int16 data attr.
3032 ;
3033 ; ASH (right)
3034 ;
3035 ; Arithmetic right shift on the C[34]x works by negating the shift count,
3036 ; then emitting a right shift with the shift count negated. This means
3037 ; that all actual shift counts in the RTL will be positive.
3039 (define_expand "ashrqi3"
3040 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3041 (ashiftrt:QI (match_operand:QI 1 "src_operand" "")
3042 (match_operand:QI 2 "src_operand" "")))
3043 (clobber (reg:CC 21))])]
3044 ""
3045 "legitimize_operands (ASHIFTRT, operands, QImode);")
3047 ; When the shift count is greater than the size of the word
3048 ; the result can be implementation specific
3049 (define_insn "*ashrqi3_const_clobber"
3050 [(set (match_operand:QI 0 "reg_operand" "=d,c,?d,?c")
3051 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,0,r,r")
3052 (match_operand:QI 2 "const_int_operand" "n,n,J,J")))
3053 (clobber (reg:CC 21))]
3054 "valid_operands (ASHIFTRT, operands, QImode)"
3055 "@
3056 ash\\t%n2,%0
3057 ash\\t%n2,%0
3058 ash3\\t%n2,%1,%0
3059 ash3\\t%n2,%1,%0"
3060 [(set_attr "type" "binarycc,binary,binarycc,binary")])
3062 (define_insn "*ashrqi3_const_noclobber"
3063 [(set (match_operand:QI 0 "std_reg_operand" "=c,?c")
3064 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
3065 (match_operand:QI 2 "const_int_operand" "n,J")))]
3066 "valid_operands (ASHIFTRT, operands, QImode)"
3067 "@
3068 ash\\t%n2,%0
3069 ash3\\t%n2,%1,%0"
3070 [(set_attr "type" "binarycc,binarycc")])
3072 ; When the shift count is greater than the size of the word
3073 ; the result can be implementation specific
3074 (define_insn "*ashrqi3_const_set"
3075 [(set (reg:CC 21)
3076 (compare:CC
3077 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,r")
3078 (match_operand:QI 2 "const_int_operand" "n,J"))
3079 (const_int 0)))
3080 (set (match_operand:QI 0 "reg_operand" "=?d,d")
3081 (ashiftrt:QI (match_dup 1)
3082 (match_dup 2)))]
3083 "valid_operands (ASHIFTRT, operands, QImode)"
3084 "@
3085 ash\\t%n2,%0
3086 ash3\\t%n2,%1,%0"
3087 [(set_attr "type" "binarycc,binarycc")])
3089 (define_insn "*ashrqi3_nonconst_clobber"
3090 [(set (match_operand:QI 0 "reg_operand" "=d,d,?d,c,c,?c")
3091 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>,0,rR,rS<>")
3092 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>,rm,R,rS<>"))))
3093 (clobber (reg:CC 21))]
3094 "valid_operands (ASHIFTRT, operands, QImode)"
3095 "@
3096 ash\\t%2,%0
3097 ash3\\t%2,%1,%0
3098 ash3\\t%2,%1,%0
3099 ash\\t%2,%0
3100 ash3\\t%2,%1,%0
3101 ash3\\t%2,%1,%0"
3102 [(set_attr "type" "binarycc,binarycc,binarycc,binary,binary,binary")])
3103 ; Default to int16 data attr.
3105 (define_insn "*ashrqi3_nonconst_noclobber"
3106 [(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
3107 (ashiftrt:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
3108 (neg:QI (match_operand:QI 2 "src_operand" "rm,R,rS<>"))))]
3109 "valid_operands (ASHIFTRT, operands, QImode)"
3110 "@
3111 ash\\t%2,%0
3112 ash3\\t%2,%1,%0
3113 ash3\\t%2,%1,%0"
3114 [(set_attr "type" "binary,binary,binary")])
3115 ; Default to int16 data attr.
3117 ;
3118 ; CMPI
3119 ;
3120 ; Unfortunately the C40 doesn't allow cmpi3 7, *ar0++ so the next best
3121 ; thing would be to get the small constant loaded into a register (say r0)
3122 ; so that it could be hoisted out of the loop so that we only
3123 ; would need to do cmpi3 *ar0++, r0. Now the loop optimisation pass
3124 ; comes before the flow pass (which finds autoincrements) so we're stuck.
3125 ; Ideally, GCC requires another loop optimisation pass (preferably after
3126 ; reload) so that it can hoist invariants out of loops.
3127 ; The current solution modifies legitimize_operands () so that small
3128 ; constants are forced into a pseudo register.
3129 ;
3130 (define_expand "cmpqi"
3131 [(set (reg:CC 21)
3132 (compare:CC (match_operand:QI 0 "src_operand" "")
3133 (match_operand:QI 1 "src_operand" "")))]
3134 ""
3135 "legitimize_operands (COMPARE, operands, QImode);
3136 c4x_compare_op0 = operands[0];
3137 c4x_compare_op1 = operands[1];
3138 DONE;")
3140 (define_insn "*cmpqi_test"
3141 [(set (reg:CC 21)
3142 (compare:CC (match_operand:QI 0 "src_operand" "r,rR,rS<>")
3143 (match_operand:QI 1 "src_operand" "rIm,JR,rS<>")))]
3144 "valid_operands (COMPARE, operands, QImode)"
3145 "@
3146 cmpi\\t%1,%0
3147 cmpi3\\t%1,%0
3148 cmpi3\\t%1,%0"
3149 [(set_attr "type" "compare,compare,compare")])
3151 (define_insn "*cmpqi_test_noov"
3152 [(set (reg:CC_NOOV 21)
3153 (compare:CC_NOOV (match_operand:QI 0 "src_operand" "r,rR,rS<>")
3154 (match_operand:QI 1 "src_operand" "rIm,JR,rS<>")))]
3155 "valid_operands (COMPARE, operands, QImode)"
3156 "@
3157 cmpi\\t%1,%0
3158 cmpi3\\t%1,%0
3159 cmpi3\\t%1,%0"
3160 [(set_attr "type" "compare,compare,compare")])
3163 ;
3164 ; BIT-FIELD INSTRUCTIONS
3165 ;
3167 ;
3168 ; LBx/LHw (C4x only)
3169 ;
3170 (define_expand "extv"
3171 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3172 (sign_extract:QI (match_operand:QI 1 "src_operand" "")
3173 (match_operand:QI 2 "const_int_operand" "")
3174 (match_operand:QI 3 "const_int_operand" "")))
3175 (clobber (reg:CC 21))])]
3176 "! TARGET_C3X"
3177 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
3178 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
3179 FAIL;
3180 ")
3182 (define_insn "*extv_clobber"
3183 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3184 (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm,rLm")
3185 (match_operand:QI 2 "const_int_operand" "n,n")
3186 (match_operand:QI 3 "const_int_operand" "n,n")))
3187 (clobber (reg:CC 21))]
3188 "! TARGET_C3X
3189 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3190 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3191 "*
3192 if (INTVAL (operands[2]) == 8)
3193 {
3194 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3195 return \"lb%3\\t%1,%0\";
3196 }
3197 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3198 return \"lh%3\\t%1,%0\";
3199 "
3200 [(set_attr "type" "binarycc,binary")
3201 (set_attr "data" "int16,int16")])
3203 (define_insn "*extv_clobber_test"
3204 [(set (reg:CC 21)
3205 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3206 (match_operand:QI 2 "const_int_operand" "n")
3207 (match_operand:QI 3 "const_int_operand" "n"))
3208 (const_int 0)))
3209 (clobber (match_scratch:QI 0 "=d"))]
3210 "! TARGET_C3X
3211 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3212 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3213 "*
3214 if (INTVAL (operands[2]) == 8)
3215 {
3216 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3217 return \"lb%3\\t%1,%0\";
3218 }
3219 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3220 return \"lh%3\\t%1,%0\";
3221 "
3222 [(set_attr "type" "binarycc")
3223 (set_attr "data" "int16")])
3225 (define_insn "*extv_clobber_set"
3226 [(set (reg:CC 21)
3227 (compare:CC (sign_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3228 (match_operand:QI 2 "const_int_operand" "n")
3229 (match_operand:QI 3 "const_int_operand" "n"))
3230 (const_int 0)))
3231 (set (match_operand:QI 0 "reg_operand" "=d")
3232 (sign_extract:QI (match_dup 1)
3233 (match_dup 2)
3234 (match_dup 3)))]
3235 "! TARGET_C3X
3236 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3237 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3238 "*
3239 if (INTVAL (operands[2]) == 8)
3240 {
3241 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3242 return \"lb%3\\t%1,%0\";
3243 }
3244 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3245 return \"lh%3\\t%1,%0\";
3246 "
3247 [(set_attr "type" "binarycc")
3248 (set_attr "data" "int16")])
3250 ;
3251 ; LBUx/LHUw (C4x only)
3252 ;
3253 (define_expand "extzv"
3254 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3255 (zero_extract:QI (match_operand:QI 1 "src_operand" "")
3256 (match_operand:QI 2 "const_int_operand" "")
3257 (match_operand:QI 3 "const_int_operand" "")))
3258 (clobber (reg:CC 21))])]
3259 "! TARGET_C3X"
3260 "if ((INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
3261 || (INTVAL (operands[3]) % INTVAL (operands[2]) != 0))
3262 FAIL;
3263 ")
3265 (define_insn "*extzv_clobber"
3266 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3267 (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm,rLm")
3268 (match_operand:QI 2 "const_int_operand" "n,n")
3269 (match_operand:QI 3 "const_int_operand" "n,n")))
3270 (clobber (reg:CC 21))]
3271 "! TARGET_C3X
3272 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3273 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3274 "*
3275 if (INTVAL (operands[2]) == 8)
3276 {
3277 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3278 return \"lbu%3\\t%1,%0\";
3279 }
3280 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3281 return \"lhu%3\\t%1,%0\";
3282 "
3283 [(set_attr "type" "binarycc,binary")
3284 (set_attr "data" "uint16,uint16")])
3286 (define_insn "*extzv_test"
3287 [(set (reg:CC 21)
3288 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3289 (match_operand:QI 2 "const_int_operand" "n")
3290 (match_operand:QI 3 "const_int_operand" "n"))
3291 (const_int 0)))
3292 (clobber (match_scratch:QI 0 "=d"))]
3293 "! TARGET_C3X
3294 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3295 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3296 "*
3297 if (INTVAL (operands[2]) == 8)
3298 {
3299 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3300 return \"lbu%3\\t%1,%0\";
3301 }
3302 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3303 return \"lhu%3\\t%1,%0\";
3304 "
3305 [(set_attr "type" "binarycc")
3306 (set_attr "data" "uint16")])
3308 (define_insn "*extzv_set"
3309 [(set (reg:CC 21)
3310 (compare:CC (zero_extract:QI (match_operand:QI 1 "src_operand" "rLm")
3311 (match_operand:QI 2 "const_int_operand" "n")
3312 (match_operand:QI 3 "const_int_operand" "n"))
3313 (const_int 0)))
3314 (set (match_operand:QI 0 "ext_reg_operand" "=d")
3315 (zero_extract:QI (match_dup 1)
3316 (match_dup 2)
3317 (match_dup 3)))]
3318 "! TARGET_C3X
3319 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
3320 && (INTVAL (operands[3]) % INTVAL (operands[2]) == 0)"
3321 "*
3322 if (INTVAL (operands[2]) == 8)
3323 {
3324 /* 8 bit extract. */
3325 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
3326 return \"lbu%3\\t%1,%0\";
3327 }
3328 /* 16 bit extract. */
3329 operands[3] = GEN_INT (INTVAL (operands[3]) / 16);
3330 return \"lhu%3\\t%1,%0\";
3331 "
3332 [(set_attr "type" "binarycc")
3333 (set_attr "data" "uint16")])
3335 ;
3336 ; MBx/MHw (C4x only)
3337 ;
3338 (define_expand "insv"
3339 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "")
3340 (match_operand:QI 1 "const_int_operand" "")
3341 (match_operand:QI 2 "const_int_operand" ""))
3342 (match_operand:QI 3 "src_operand" ""))
3343 (clobber (reg:CC 21))])]
3344 "! TARGET_C3X"
3345 "if (! (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3346 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
3347 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)))
3348 FAIL;
3349 ")
3351 (define_insn "*insv_clobber"
3352 [(set (zero_extract:QI (match_operand:QI 0 "reg_operand" "+d,c")
3353 (match_operand:QI 1 "const_int_operand" "n,n")
3354 (match_operand:QI 2 "const_int_operand" "n,n"))
3355 (match_operand:QI 3 "src_operand" "rLm,rLm"))
3356 (clobber (reg:CC 21))]
3357 "! TARGET_C3X
3358 && (((INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3359 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0))
3360 || (INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8))"
3361 "*
3362 if (INTVAL (operands[1]) == 8)
3363 {
3364 /* 8 bit insert. */
3365 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
3366 return \"mb%2\\t%3,%0\";
3367 }
3368 else if (INTVAL (operands[1]) == 16)
3369 {
3370 /* 16 bit insert. */
3371 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
3372 return \"mh%2\\t%3,%0\";
3373 }
3374 /* 24 bit insert. */
3375 return \"lwl1\\t%3,%0\";
3376 "
3377 [(set_attr "type" "binarycc,binary")
3378 (set_attr "data" "uint16,uint16")])
3380 (define_peephole
3381 [(parallel [(set (zero_extract:QI (match_operand:QI 0 "ext_reg_operand" "+d")
3382 (match_operand:QI 1 "const_int_operand" "n")
3383 (match_operand:QI 2 "const_int_operand" "n"))
3384 (match_operand:QI 3 "src_operand" "rLm"))
3385 (clobber (reg:CC 21))])
3386 (set (reg:CC 21)
3387 (compare:CC (match_dup 0) (const_int 0)))]
3388 "! TARGET_C3X
3389 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
3390 && (INTVAL (operands[2]) % INTVAL (operands[1]) == 0)"
3391 "*
3392 if (INTVAL (operands[1]) == 8)
3393 {
3394 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
3395 return \"mb%2\\t%3,%0\";
3396 }
3397 operands[2] = GEN_INT (INTVAL (operands[2]) / 16);
3398 return \"mh%2\\t%3,%0\";
3399 "
3400 [(set_attr "type" "binarycc")
3401 (set_attr "data" "uint16")])
3404 ; TWO OPERAND FLOAT INSTRUCTIONS
3405 ;
3407 ;
3408 ; LDF/STF
3409 ;
3410 ; If one of the operands is not a register, then we should
3411 ; emit two insns, using a scratch register. This will produce
3412 ; better code in loops if the source operand is invariant, since
3413 ; the source reload can be optimized out. During reload we cannot
3414 ; use change_address or force_reg.
3415 (define_expand "movqf"
3416 [(set (match_operand:QF 0 "src_operand" "")
3417 (match_operand:QF 1 "src_operand" ""))]
3418 ""
3419 "
3420 {
3421 if (c4x_emit_move_sequence (operands, QFmode))
3422 DONE;
3423 }")
3425 ; This can generate invalid stack slot displacements
3426 (define_split
3427 [(set (match_operand:QI 0 "reg_operand" "")
3428 (unspec:QI [(match_operand:QF 1 "reg_operand" "")] 12))]
3429 "reload_completed"
3430 [(set (match_dup 3) (match_dup 1))
3431 (set (match_dup 0) (match_dup 2))]
3432 "operands[2] = assign_stack_temp (QImode, GET_MODE_SIZE (QImode), 0);
3433 operands[3] = copy_rtx (operands[2]);
3434 PUT_MODE (operands[3], QFmode);")
3437 (define_insn "storeqf_int"
3438 [(set (match_operand:QI 0 "reg_operand" "=r")
3439 (unspec:QI [(match_operand:QF 1 "reg_operand" "f")] 12))]
3440 ""
3441 "#"
3442 [(set_attr "type" "multi")])
3444 (define_split
3445 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
3446 (unspec:QI [(match_operand:QF 1 "reg_operand" "")] 12))
3447 (clobber (reg:CC 21))])]
3448 "reload_completed"
3449 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
3450 (match_dup 1))
3451 (parallel [(set (match_dup 0)
3452 (mem:QI (post_dec:QI (reg:QI 20))))
3453 (clobber (reg:CC 21))])]
3454 "")
3457 ; We need accurate death notes for this...
3458 ;(define_peephole
3459 ; [(set (match_operand:QF 0 "reg_operand" "=f")
3460 ; (match_operand:QF 1 "memory_operand" "m"))
3461 ; (set (mem:QF (pre_inc:QI (reg:QI 20)))
3462 ; (match_dup 0))
3463 ; (parallel [(set (match_operand:QI 2 "reg_operand" "r")
3464 ; (mem:QI (post_dec:QI (reg:QI 20))))
3465 ; (clobber (reg:CC 21))])]
3466 ; ""
3467 ; "ldiu\\t%1,%0")
3469 (define_insn "storeqf_int_clobber"
3470 [(parallel [(set (match_operand:QI 0 "reg_operand" "=r")
3471 (unspec:QI [(match_operand:QF 1 "reg_operand" "f")] 12))
3472 (clobber (reg:CC 21))])]
3473 ""
3474 "#"
3475 [(set_attr "type" "multi")])
3478 ; This can generate invalid stack slot displacements
3479 (define_split
3480 [(set (match_operand:QF 0 "reg_operand" "")
3481 (unspec:QF [(match_operand:QI 1 "reg_operand" "")] 11))]
3482 "reload_completed"
3483 [(set (match_dup 2) (match_dup 1))
3484 (set (match_dup 0) (match_dup 3))]
3485 "operands[2] = assign_stack_temp (QImode, GET_MODE_SIZE (QImode), 0);
3486 operands[3] = copy_rtx (operands[2]);
3487 PUT_MODE (operands[3], QFmode);")
3490 (define_insn "loadqf_int"
3491 [(set (match_operand:QF 0 "reg_operand" "=f")
3492 (unspec:QF [(match_operand:QI 1 "reg_operand" "r")] 11))]
3493 ""
3494 "#"
3495 [(set_attr "type" "multi")])
3497 (define_split
3498 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3499 (unspec:QF [(match_operand:QI 1 "reg_operand" "")] 11))
3500 (clobber (reg:CC 21))])]
3501 "reload_completed"
3502 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
3503 (match_dup 1))
3504 (parallel [(set (match_dup 0)
3505 (mem:QF (post_dec:QI (reg:QI 20))))
3506 (clobber (reg:CC 21))])]
3507 "")
3509 (define_insn "loadqf_int_clobber"
3510 [(parallel [(set (match_operand:QF 0 "reg_operand" "=f")
3511 (unspec:QF [(match_operand:QI 1 "reg_operand" "r")] 11))
3512 (clobber (reg:CC 21))])]
3513 ""
3514 "#"
3515 [(set_attr "type" "multi")])
3517 ; We must provide an alternative to store to memory in case we have to
3518 ; spill a register.
3519 (define_insn "movqf_noclobber"
3520 [(set (match_operand:QF 0 "dst_operand" "=f,m")
3521 (match_operand:QF 1 "src_operand" "fHm,f"))]
3522 "REG_P (operands[0]) || REG_P (operands[1])"
3523 "@
3524 ldfu\\t%1,%0
3525 stf\\t%1,%0"
3526 [(set_attr "type" "unary,store")])
3528 ;(define_insn "*movqf_clobber"
3529 ; [(set (match_operand:QF 0 "reg_operand" "=f")
3530 ; (match_operand:QF 1 "src_operand" "fHm"))
3531 ; (clobber (reg:CC 21))]
3532 ; "0"
3533 ; "ldf\\t%1,%0"
3534 ; [(set_attr "type" "unarycc")])
3536 (define_insn "*movqf_test"
3537 [(set (reg:CC 21)
3538 (compare:CC (match_operand:QF 1 "src_operand" "fHm")
3539 (const_int 0)))
3540 (clobber (match_scratch:QF 0 "=f"))]
3541 ""
3542 "ldf\\t%1,%0"
3543 [(set_attr "type" "unarycc")])
3545 (define_insn "*movqf_set"
3546 [(set (reg:CC 21)
3547 (compare:CC (match_operand:QF 1 "src_operand" "fHm")
3548 (match_operand:QF 2 "fp_zero_operand" "G")))
3549 (set (match_operand:QF 0 "reg_operand" "=f")
3550 (match_dup 1))]
3551 ""
3552 "ldf\\t%1,%0"
3553 [(set_attr "type" "unarycc")])
3556 (define_insn "*movqf_parallel"
3557 [(set (match_operand:QF 0 "parallel_operand" "=q,S<>!V,q,S<>!V")
3558 (match_operand:QF 1 "parallel_operand" "S<>!V,q,S<>!V,q"))
3559 (set (match_operand:QF 2 "parallel_operand" "=q,S<>!V,S<>!V,q")
3560 (match_operand:QF 3 "parallel_operand" "S<>!V,q,q,S<>!V"))]
3561 "TARGET_PARALLEL && valid_parallel_load_store (operands, QFmode)"
3562 "@
3563 ldf1\\t%1,%0\\n||\\tldf2\\t%3,%2
3564 stf1\\t%1,%0\\n||\\tstf2\\t%3,%2
3565 ldf\\t%1,%0\\n||\\tstf\\t%3,%2
3566 ldf\\t%3,%2\\n||\\tstf\\t%1,%0"
3567 [(set_attr "type" "load_load,store_store,load_store,store_load")])
3570 ;
3571 ; PUSH/POP
3572 ;
3573 (define_insn "pushqf"
3574 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
3575 (match_operand:QF 0 "reg_operand" "f"))]
3576 ""
3577 "pushf\\t%0"
3578 [(set_attr "type" "push")])
3580 (define_insn "popqf"
3581 [(set (match_operand:QF 0 "reg_operand" "=f")
3582 (mem:QF (post_dec:QI (reg:QI 20))))
3583 (clobber (reg:CC 21))]
3584 ""
3585 "popf\\t%0"
3586 [(set_attr "type" "pop")])
3588 (define_insn "popqf_unspec"
3589 [(set (unspec:QF [(match_operand:QF 0 "reg_operand" "=f")] 19)
3590 (mem:QF (post_dec:QI (reg:QI 20))))
3591 (clobber (match_dup 0))
3592 (clobber (reg:CC 21))]
3593 ""
3594 "popf\\t%0"
3595 [(set_attr "type" "pop")])
3597 ;
3598 ; ABSF
3599 ;
3600 (define_expand "absqf2"
3601 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3602 (abs:QF (match_operand:QF 1 "src_operand" "")))
3603 (clobber (reg:CC_NOOV 21))])]
3604 ""
3605 "")
3607 (define_insn "*absqf2_clobber"
3608 [(set (match_operand:QF 0 "reg_operand" "=f")
3609 (abs:QF (match_operand:QF 1 "src_operand" "fHm")))
3610 (clobber (reg:CC_NOOV 21))]
3611 ""
3612 "absf\\t%1,%0"
3613 [(set_attr "type" "unarycc")])
3615 (define_insn "*absqf2_test"
3616 [(set (reg:CC_NOOV 21)
3617 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fHm"))
3618 (match_operand:QF 2 "fp_zero_operand" "G")))
3619 (clobber (match_scratch:QF 0 "=f"))]
3620 ""
3621 "absf\\t%1,%0"
3622 [(set_attr "type" "unarycc")])
3624 (define_insn "*absqf2_set"
3625 [(set (reg:CC_NOOV 21)
3626 (compare:CC_NOOV (abs:QF (match_operand:QF 1 "src_operand" "fHm"))
3627 (match_operand:QF 2 "fp_zero_operand" "G")))
3628 (set (match_operand:QF 0 "reg_operand" "=f")
3629 (abs:QF (match_dup 1)))]
3631 ""
3632 "absf\\t%1,%0"
3633 [(set_attr "type" "unarycc")])
3635 ;
3636 ; NEGF
3637 ;
3638 (define_expand "negqf2"
3639 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3640 (neg:QF (match_operand:QF 1 "src_operand" "")))
3641 (clobber (reg:CC_NOOV 21))])]
3642 ""
3643 "")
3645 (define_insn "*negqf2_clobber"
3646 [(set (match_operand:QF 0 "reg_operand" "=f")
3647 (neg:QF (match_operand:QF 1 "src_operand" "fHm")))
3648 (clobber (reg:CC_NOOV 21))]
3649 ""
3650 "negf\\t%1,%0"
3651 [(set_attr "type" "unarycc")])
3653 (define_insn "*negqf2_test"
3654 [(set (reg:CC_NOOV 21)
3655 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fHm"))
3656 (match_operand:QF 2 "fp_zero_operand" "G")))
3657 (clobber (match_scratch:QF 0 "=f"))]
3658 ""
3659 "negf\\t%1,%0"
3660 [(set_attr "type" "unarycc")])
3662 (define_insn "*negqf2_set"
3663 [(set (reg:CC_NOOV 21)
3664 (compare:CC_NOOV (neg:QF (match_operand:QF 1 "src_operand" "fHm"))
3665 (match_operand:QF 2 "fp_zero_operand" "G")))
3666 (set (match_operand:QF 0 "reg_operand" "=f")
3667 (neg:QF (match_dup 1)))]
3668 ""
3669 "negf\\t%1,%0"
3670 [(set_attr "type" "unarycc")])
3672 ;
3673 ; FLOAT
3674 ;
3675 (define_insn "floatqiqf2"
3676 [(set (match_operand:QF 0 "reg_operand" "=f")
3677 (float:QF (match_operand:QI 1 "src_operand" "rIm")))
3678 (clobber (reg:CC 21))]
3679 ""
3680 "float\\t%1,%0"
3681 [(set_attr "type" "unarycc")])
3683 (define_insn "*floatqiqf2_set"
3684 [(set (reg:CC 21)
3685 (compare:CC (float:QF (match_operand:QI 1 "src_operand" "rIm"))
3686 (match_operand:QF 2 "fp_zero_operand" "G")))
3687 (set (match_operand:QF 0 "reg_operand" "=f")
3688 (float:QF (match_dup 1)))]
3689 ""
3690 "float\\t%1,%0"
3691 [(set_attr "type" "unarycc")])
3693 ; Unsigned conversions are a little tricky because we need to
3694 ; add the value for the high bit if necessary.
3695 ;
3696 ;
3697 (define_expand "floatunsqiqf2"
3698 [(set (match_dup 2) (match_dup 3))
3699 (parallel [(set (reg:CC 21)
3700 (compare:CC (float:QF (match_operand:QI 1 "src_operand" ""))
3701 (match_dup 3)))
3702 (set (match_dup 4)
3703 (float:QF (match_dup 1)))])
3704 (set (match_dup 6)
3705 (if_then_else:QF (lt (reg:CC 21) (const_int 0))
3706 (match_dup 5)
3707 (match_dup 2)))
3708 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3709 (plus:QF (match_dup 6) (match_dup 4)))
3710 (clobber (reg:CC_NOOV 21))])]
3711 ""
3712 "operands[2] = gen_reg_rtx (QFmode);
3713 operands[3] = CONST0_RTX (QFmode);
3714 operands[4] = gen_reg_rtx (QFmode);
3715 operands[5] = gen_reg_rtx (QFmode);
3716 operands[6] = gen_reg_rtx (QFmode);
3717 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));")
3719 (define_expand "floatunsqihf2"
3720 [(set (match_dup 2) (match_dup 3))
3721 (parallel [(set (reg:CC 21)
3722 (compare:CC (float:HF (match_operand:QI 1 "src_operand" ""))
3723 (match_dup 3)))
3724 (set (match_dup 4)
3725 (float:HF (match_dup 1)))])
3726 (set (match_dup 6)
3727 (if_then_else:HF (lt (reg:CC 21) (const_int 0))
3728 (match_dup 5)
3729 (match_dup 2)))
3730 (parallel [(set (match_operand:HF 0 "reg_operand" "")
3731 (plus:HF (match_dup 6) (match_dup 4)))
3732 (clobber (reg:CC_NOOV 21))])]
3733 ""
3734 "operands[2] = gen_reg_rtx (HFmode);
3735 operands[3] = CONST0_RTX (HFmode);
3736 operands[4] = gen_reg_rtx (HFmode);
3737 operands[5] = gen_reg_rtx (HFmode);
3738 operands[6] = gen_reg_rtx (HFmode);
3739 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));")
3741 (define_insn "floatqihf2"
3742 [(set (match_operand:HF 0 "reg_operand" "=h")
3743 (float:HF (match_operand:QI 1 "src_operand" "rIm")))
3744 (clobber (reg:CC 21))]
3745 ""
3746 "float\\t%1,%0"
3747 [(set_attr "type" "unarycc")])
3749 (define_insn "*floatqihf2_set"
3750 [(set (reg:CC 21)
3751 (compare:CC (float:HF (match_operand:QI 1 "src_operand" "rIm"))
3752 (match_operand:QF 2 "fp_zero_operand" "G")))
3753 (set (match_operand:HF 0 "reg_operand" "=h")
3754 (float:HF (match_dup 1)))]
3755 ""
3756 "float\\t%1,%0"
3757 [(set_attr "type" "unarycc")])
3759 ;
3760 ; FIX
3761 ;
3762 (define_insn "fixqfqi_clobber"
3763 [(set (match_operand:QI 0 "reg_operand" "=d,c")
3764 (fix:QI (match_operand:QF 1 "src_operand" "fHm,fHm")))
3765 (clobber (reg:CC 21))]
3766 ""
3767 "fix\\t%1,%0"
3768 [(set_attr "type" "unarycc")])
3770 (define_insn "*fixqfqi_set"
3771 [(set (reg:CC 21)
3772 (compare:CC (fix:QI (match_operand:QF 1 "src_operand" "fHm"))
3773 (const_int 0)))
3774 (set (match_operand:QI 0 "ext_reg_operand" "=d")
3775 (fix:QI (match_dup 1)))]
3776 ""
3777 "fix\\t%1,%0"
3778 [(set_attr "type" "unarycc")])
3780 (define_insn "*fixhfqi_set"
3781 [(set (reg:CC 21)
3782 (compare:CC (fix:QI (match_operand:HF 1 "src_operand" "fH"))
3783 (const_int 0)))
3784 (set (match_operand:QI 0 "ext_reg_operand" "=d")
3785 (fix:QI (match_dup 1)))]
3786 ""
3787 "fix\\t%1,%0"
3788 [(set_attr "type" "unarycc")])
3790 ;
3791 ; The C[34]x fix instruction implements a floor, not a straight trunc,
3792 ; so we have to invert the number, fix it, and reinvert it if negative
3793 ;
3794 (define_expand "fix_truncqfqi2"
3795 [(parallel [(set (match_dup 2)
3796 (fix:QI (match_operand:QF 1 "src_operand" "")))
3797 (clobber (reg:CC 21))])
3798 (parallel [(set (match_dup 3) (neg:QF (match_dup 1)))
3799 (clobber (reg:CC_NOOV 21))])
3800 (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
3801 (clobber (reg:CC 21))])
3802 (parallel [(set (reg:CC_NOOV 21)
3803 (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
3804 (set (match_dup 5) (neg:QI (match_dup 4)))])
3805 (set (match_dup 2)
3806 (if_then_else:QI (le (reg:CC 21) (const_int 0))
3807 (match_dup 5)
3808 (match_dup 2)))
3809 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
3810 ""
3811 "if (TARGET_FAST_FIX)
3812 {
3813 emit_insn (gen_fixqfqi_clobber (operands[0], operands[1]));
3814 DONE;
3815 }
3816 operands[2] = gen_reg_rtx (QImode);
3817 operands[3] = gen_reg_rtx (QFmode);
3818 operands[4] = gen_reg_rtx (QImode);
3819 operands[5] = gen_reg_rtx (QImode);
3820 ")
3822 (define_expand "fix_trunchfqi2"
3823 [(parallel [(set (match_dup 2)
3824 (fix:QI (match_operand:HF 1 "src_operand" "")))
3825 (clobber (reg:CC 21))])
3826 (parallel [(set (match_dup 3) (neg:HF (match_dup 1)))
3827 (clobber (reg:CC_NOOV 21))])
3828 (parallel [(set (match_dup 4) (fix:QI (match_dup 3)))
3829 (clobber (reg:CC 21))])
3830 (parallel [(set (reg:CC_NOOV 21)
3831 (compare:CC_NOOV (neg:QI (match_dup 4)) (const_int 0)))
3832 (set (match_dup 5) (neg:QI (match_dup 4)))])
3833 (set (match_dup 2)
3834 (if_then_else:QI (le (reg:CC 21) (const_int 0))
3835 (match_dup 5)
3836 (match_dup 2)))
3837 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 2))]
3838 ""
3839 "if (TARGET_FAST_FIX)
3840 {
3841 emit_insn (gen_fixhfqi_clobber (operands[0], operands[1]));
3842 DONE;
3843 }
3844 operands[2] = gen_reg_rtx (QImode);
3845 operands[3] = gen_reg_rtx (HFmode);
3846 operands[4] = gen_reg_rtx (QImode);
3847 operands[5] = gen_reg_rtx (QImode);
3848 ")
3850 (define_expand "fix_truncqfhi2"
3851 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3852 (fix:HI (match_operand:QF 1 "src_operand" "")))
3853 (clobber (reg:CC 21))])]
3854 ""
3855 "c4x_emit_libcall (fix_truncqfhi2_libfunc, FIX, HImode, QFmode, 2, operands);
3856 DONE;")
3858 (define_expand "fixuns_truncqfqi2"
3859 [(parallel [(set (match_dup 2)
3860 (fix:QI (match_operand:QF 1 "src_operand" "fHm")))
3861 (clobber (reg:CC 21))])
3862 (parallel [(set (match_dup 3)
3863 (minus:QF (match_dup 1) (match_dup 5)))
3864 (clobber (reg:CC_NOOV 21))])
3865 (parallel [(set (reg:CC 21)
3866 (compare:CC (fix:QI (match_dup 3))
3867 (const_int 0)))
3868 (set (match_dup 4)
3869 (fix:QI (match_dup 3)))])
3870 (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] 13))
3871 (use (reg:CC 21))])
3872 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))]
3873 ""
3874 "operands[2] = gen_reg_rtx (QImode);
3875 operands[3] = gen_reg_rtx (QFmode);
3876 operands[4] = gen_reg_rtx (QImode);
3877 operands[5] = gen_reg_rtx (QFmode);
3878 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", QFmode));")
3880 (define_expand "fixuns_trunchfqi2"
3881 [(parallel [(set (match_dup 2)
3882 (fix:QI (match_operand:HF 1 "src_operand" "hH")))
3883 (clobber (reg:CC 21))])
3884 (parallel [(set (match_dup 3)
3885 (minus:HF (match_dup 1) (match_dup 5)))
3886 (clobber (reg:CC_NOOV 21))])
3887 (parallel [(set (reg:CC 21)
3888 (compare:CC (fix:QI (match_dup 3))
3889 (const_int 0)))
3890 (set (match_dup 4)
3891 (fix:QI (match_dup 3)))])
3892 (parallel [(set (match_dup 4) (unspec:QI [(match_dup 2)] 13))
3893 (use (reg:CC 21))])
3894 (set (match_operand:QI 0 "reg_operand" "=r") (match_dup 4))]
3895 ""
3896 "operands[2] = gen_reg_rtx (QImode);
3897 operands[3] = gen_reg_rtx (HFmode);
3898 operands[4] = gen_reg_rtx (QImode);
3899 operands[5] = gen_reg_rtx (HFmode);
3900 emit_move_insn (operands[5], CONST_DOUBLE_ATOF (\"4294967296.0\", HFmode));")
3902 (define_expand "fixuns_truncqfhi2"
3903 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
3904 (unsigned_fix:HI (match_operand:QF 1 "src_operand" "")))
3905 (clobber (reg:CC 21))])]
3906 ""
3907 "c4x_emit_libcall (fixuns_truncqfhi2_libfunc, UNSIGNED_FIX,
3908 HImode, QFmode, 2, operands);
3909 DONE;")
3911 ;
3912 ; RCPF
3913 ;
3914 (define_insn "rcpfqf_clobber"
3915 [(set (match_operand:QF 0 "reg_operand" "=f")
3916 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] 5))
3917 (clobber (reg:CC_NOOV 21))]
3918 "! TARGET_C3X"
3919 "rcpf\\t%1,%0"
3920 [(set_attr "type" "unarycc")])
3922 ;
3923 ; RSQRF
3924 ;
3925 (define_insn "*rsqrfqf_clobber"
3926 [(set (match_operand:QF 0 "reg_operand" "=f")
3927 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] 10))
3928 (clobber (reg:CC_NOOV 21))]
3929 "! TARGET_C3X"
3930 "rsqrf\\t%1,%0"
3931 [(set_attr "type" "unarycc")])
3933 ;
3934 ; RNDF
3935 ;
3936 (define_insn "*rndqf_clobber"
3937 [(set (match_operand:QF 0 "reg_operand" "=f")
3938 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] 6))
3939 (clobber (reg:CC_NOOV 21))]
3940 "! TARGET_C3X"
3941 "rnd\\t%1,%0"
3942 [(set_attr "type" "unarycc")])
3945 ; Inlined float square root for C4x
3946 (define_expand "sqrtqf2_inline"
3947 [(parallel [(set (match_dup 2)
3948 (unspec:QF [(match_operand:QF 1 "src_operand" "")] 10))
3949 (clobber (reg:CC_NOOV 21))])
3950 (parallel [(set (match_dup 3) (mult:QF (match_dup 5) (match_dup 1)))
3951 (clobber (reg:CC_NOOV 21))])
3952 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3953 (clobber (reg:CC_NOOV 21))])
3954 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3955 (clobber (reg:CC_NOOV 21))])
3956 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3957 (clobber (reg:CC_NOOV 21))])
3958 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3959 (clobber (reg:CC_NOOV 21))])
3960 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
3961 (clobber (reg:CC_NOOV 21))])
3962 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 4)))
3963 (clobber (reg:CC_NOOV 21))])
3964 (parallel [(set (match_dup 4) (minus:QF (match_dup 6) (match_dup 4)))
3965 (clobber (reg:CC_NOOV 21))])
3966 (parallel [(set (match_dup 2) (mult:QF (match_dup 2) (match_dup 4)))
3967 (clobber (reg:CC_NOOV 21))])
3968 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 1)))
3969 (clobber (reg:CC_NOOV 21))])
3970 (parallel [(set (match_operand:QF 0 "reg_operand" "")
3971 (unspec:QF [(match_dup 4)] 6))
3972 (clobber (reg:CC_NOOV 21))])]
3973 "! TARGET_C3X"
3974 "if (! reload_in_progress
3975 && ! reg_operand (operands[1], QFmode))
3976 operands[1] = force_reg (QFmode, operands[1]);
3977 operands[2] = gen_reg_rtx (QFmode);
3978 operands[3] = gen_reg_rtx (QFmode);
3979 operands[4] = gen_reg_rtx (QFmode);
3980 operands[5] = CONST_DOUBLE_ATOF (\"0.5\", QFmode);
3981 operands[6] = CONST_DOUBLE_ATOF (\"1.5\", QFmode);")
3983 (define_expand "sqrtqf2"
3984 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
3985 (sqrt:QF (match_operand:QF 1 "src_operand" "")))
3986 (clobber (reg:CC 21))])]
3987 "! TARGET_C3X && TARGET_INLINE"
3988 "emit_insn (gen_sqrtqf2_inline (operands[0], operands[1]));
3989 DONE;")
3991 ;
3992 ; TOIEEE / FRIEEE
3993 ;
3994 (define_insn "toieee"
3995 [(set (match_operand:QF 0 "reg_operand" "=f")
3996 (unspec:QF [(match_operand:QF 1 "src_operand" "fHm")] 23))
3997 (clobber (reg:CC 21))]
3998 ""
3999 "toieee\\t%1,%0")
4001 (define_insn "frieee"
4002 [(set (match_operand:QF 0 "reg_operand" "=f")
4003 (unspec:QF [(match_operand:QF 1 "memory_operand" "m")] 24))
4004 (clobber (reg:CC 21))]
4005 ""
4006 "frieee\\t%1,%0")
4008 ;
4009 ; THREE OPERAND FLOAT INSTRUCTIONS
4010 ;
4012 ;
4013 ; ADDF
4014 ;
4015 (define_expand "addqf3"
4016 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4017 (plus:QF (match_operand:QF 1 "src_operand" "")
4018 (match_operand:QF 2 "src_operand" "")))
4019 (clobber (reg:CC_NOOV 21))])]
4020 ""
4021 "legitimize_operands (PLUS, operands, QFmode);")
4023 (define_insn "*addqf3_clobber"
4024 [(set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4025 (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4026 (match_operand:QF 2 "src_operand" "fHm,R,fS<>")))
4027 (clobber (reg:CC_NOOV 21))]
4028 "valid_operands (PLUS, operands, QFmode)"
4029 "@
4030 addf\\t%2,%0
4031 addf3\\t%2,%1,%0
4032 addf3\\t%2,%1,%0"
4033 [(set_attr "type" "binarycc,binarycc,binarycc")])
4035 (define_insn "*addqf3_test"
4036 [(set (reg:CC_NOOV 21)
4037 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4038 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4039 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4040 (clobber (match_scratch:QF 0 "=f,f,?f"))]
4041 "valid_operands (PLUS, operands, QFmode)"
4042 "@
4043 addf\\t%2,%0
4044 addf3\\t%2,%1,%0
4045 addf3\\t%2,%1,%0"
4046 [(set_attr "type" "binarycc,binarycc,binarycc")])
4048 (define_insn "*addqf3_set"
4049 [(set (reg:CC_NOOV 21)
4050 (compare:CC_NOOV (plus:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4051 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4052 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4053 (set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4054 (plus:QF (match_dup 1)
4055 (match_dup 2)))]
4056 "valid_operands (PLUS, operands, QFmode)"
4057 "@
4058 addf\\t%2,%0
4059 addf3\\t%2,%1,%0
4060 addf3\\t%2,%1,%0"
4061 [(set_attr "type" "binarycc,binarycc,binarycc")])
4063 ;
4064 ; SUBF/SUBRF
4065 ;
4066 (define_expand "subqf3"
4067 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4068 (minus:QF (match_operand:QF 1 "src_operand" "")
4069 (match_operand:QF 2 "src_operand" "")))
4070 (clobber (reg:CC_NOOV 21))])]
4071 ""
4072 "legitimize_operands (MINUS, operands, QFmode);")
4074 (define_insn "*subqf3_clobber"
4075 [(set (match_operand:QF 0 "reg_operand" "=f,f,f,?f")
4076 (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4077 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>")))
4078 (clobber (reg:CC_NOOV 21))]
4079 "valid_operands (MINUS, operands, QFmode)"
4080 "@
4081 subf\\t%2,%0
4082 subrf\\t%1,%0
4083 subf3\\t%2,%1,%0
4084 subf3\\t%2,%1,%0"
4085 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4087 (define_insn "*subqf3_test"
4088 [(set (reg:CC_NOOV 21)
4089 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4090 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>"))
4091 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
4092 (clobber (match_scratch:QF 0 "=f,f,f,?f"))]
4093 "valid_operands (MINUS, operands, QFmode)"
4094 "@
4095 subf\\t%2,%0
4096 subrf\\t%1,%0
4097 subf3\\t%2,%1,%0
4098 subf3\\t%2,%1,%0"
4099 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4101 (define_insn "*subqf3_set"
4102 [(set (reg:CC_NOOV 21)
4103 (compare:CC_NOOV (minus:QF (match_operand:QF 1 "src_operand" "0,fHm,fR,fS<>")
4104 (match_operand:QF 2 "src_operand" "fHm,0,R,fS<>"))
4105 (match_operand:QF 3 "fp_zero_operand" "G,G,G,G")))
4106 (set (match_operand:QF 0 "reg_operand" "=f,f,f,?f")
4107 (minus:QF (match_dup 1)
4108 (match_dup 2)))]
4109 "valid_operands (MINUS, operands, QFmode)"
4110 "@
4111 subf\\t%2,%0
4112 subrf\\t%1,%0
4113 subf3\\t%2,%1,%0
4114 subf3\\t%2,%1,%0"
4115 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4117 ;
4118 ; MPYF
4119 ;
4120 (define_expand "mulqf3"
4121 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4122 (mult:QF (match_operand:QF 1 "src_operand" "")
4123 (match_operand:QF 2 "src_operand" "")))
4124 (clobber (reg:CC_NOOV 21))])]
4125 ""
4126 "legitimize_operands (MULT, operands, QFmode);")
4128 (define_insn "*mulqf3_clobber"
4129 [(set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4130 (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4131 (match_operand:QF 2 "src_operand" "fHm,R,fS<>")))
4132 (clobber (reg:CC_NOOV 21))]
4133 "valid_operands (MULT, operands, QFmode)"
4134 "@
4135 mpyf\\t%2,%0
4136 mpyf3\\t%2,%1,%0
4137 mpyf3\\t%2,%1,%0"
4138 [(set_attr "type" "binarycc,binarycc,binarycc")])
4140 (define_insn "*mulqf3_test"
4141 [(set (reg:CC_NOOV 21)
4142 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4143 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4144 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4145 (clobber (match_scratch:QF 0 "=f,f,?f"))]
4146 "valid_operands (MULT, operands, QFmode)"
4147 "@
4148 mpyf\\t%2,%0
4149 mpyf3\\t%2,%1,%0
4150 mpyf3\\t%2,%1,%0"
4151 [(set_attr "type" "binarycc,binarycc,binarycc")])
4153 (define_insn "*mulqf3_set"
4154 [(set (reg:CC_NOOV 21)
4155 (compare:CC_NOOV (mult:QF (match_operand:QF 1 "src_operand" "%0,fR,fS<>")
4156 (match_operand:QF 2 "src_operand" "fHm,R,fS<>"))
4157 (match_operand:QF 3 "fp_zero_operand" "G,G,G")))
4158 (set (match_operand:QF 0 "reg_operand" "=f,f,?f")
4159 (mult:QF (match_dup 1)
4160 (match_dup 2)))]
4161 "valid_operands (MULT, operands, QFmode)"
4162 "@
4163 mpyf\\t%2,%0
4164 mpyf3\\t%2,%1,%0
4165 mpyf3\\t%2,%1,%0"
4166 [(set_attr "type" "binarycc,binarycc,binarycc")])
4168 ;
4169 ; CMPF
4170 ;
4171 (define_expand "cmpqf"
4172 [(set (reg:CC 21)
4173 (compare:CC (match_operand:QF 0 "src_operand" "")
4174 (match_operand:QF 1 "src_operand" "")))]
4175 ""
4176 "legitimize_operands (COMPARE, operands, QFmode);
4177 c4x_compare_op0 = operands[0];
4178 c4x_compare_op1 = operands[1];
4179 DONE;")
4181 (define_insn "*cmpqf"
4182 [(set (reg:CC 21)
4183 (compare:CC (match_operand:QF 0 "src_operand" "f,fR,fS<>")
4184 (match_operand:QF 1 "src_operand" "fHm,R,fS<>")))]
4185 "valid_operands (COMPARE, operands, QFmode)"
4186 "@
4187 cmpf\\t%1,%0
4188 cmpf3\\t%1,%0
4189 cmpf3\\t%1,%0"
4190 [(set_attr "type" "compare,compare,compare")])
4192 (define_insn "*cmpqf_noov"
4193 [(set (reg:CC_NOOV 21)
4194 (compare:CC_NOOV (match_operand:QF 0 "src_operand" "f,fR,fS<>")
4195 (match_operand:QF 1 "src_operand" "fHm,R,fS<>")))]
4196 "valid_operands (COMPARE, operands, QFmode)"
4197 "@
4198 cmpf\\t%1,%0
4199 cmpf3\\t%1,%0
4200 cmpf3\\t%1,%0"
4201 [(set_attr "type" "compare,compare,compare")])
4203 ; Inlined float divide for C4x
4204 (define_expand "divqf3_inline"
4205 [(parallel [(set (match_dup 3)
4206 (unspec:QF [(match_operand:QF 2 "src_operand" "")] 5))
4207 (clobber (reg:CC_NOOV 21))])
4208 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
4209 (clobber (reg:CC_NOOV 21))])
4210 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
4211 (clobber (reg:CC_NOOV 21))])
4212 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
4213 (clobber (reg:CC_NOOV 21))])
4214 (parallel [(set (match_dup 4) (mult:QF (match_dup 2) (match_dup 3)))
4215 (clobber (reg:CC_NOOV 21))])
4216 (parallel [(set (match_dup 4) (minus:QF (match_dup 5) (match_dup 4)))
4217 (clobber (reg:CC_NOOV 21))])
4218 (parallel [(set (match_dup 3) (mult:QF (match_dup 3) (match_dup 4)))
4219 (clobber (reg:CC_NOOV 21))])
4220 (parallel [(set (match_dup 3)
4221 (mult:QF (match_operand:QF 1 "src_operand" "")
4222 (match_dup 3)))
4223 (clobber (reg:CC_NOOV 21))])
4224 (parallel [(set (match_operand:QF 0 "reg_operand" "")
4225 (unspec:QF [(match_dup 3)] 6))
4226 (clobber (reg:CC_NOOV 21))])]
4227 "! TARGET_C3X"
4228 "if (! reload_in_progress
4229 && ! reg_operand (operands[2], QFmode))
4230 operands[2] = force_reg (QFmode, operands[2]);
4231 operands[3] = gen_reg_rtx (QFmode);
4232 operands[4] = gen_reg_rtx (QFmode);
4233 operands[5] = CONST2_RTX (QFmode);")
4235 (define_expand "divqf3"
4236 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
4237 (div:QF (match_operand:QF 1 "src_operand" "")
4238 (match_operand:QF 2 "src_operand" "")))
4239 (clobber (reg:CC 21))])]
4240 "! TARGET_C3X && TARGET_INLINE"
4241 "emit_insn (gen_divqf3_inline (operands[0], operands[1], operands[2]));
4242 DONE;")
4244 ;
4245 ; CONDITIONAL MOVES
4246 ;
4248 ; ??? We should make these pattern fail if the src operand combination
4249 ; is not valid. Although reload will fix things up, it will introduce
4250 ; extra load instructions that won't be hoisted out of a loop.
4252 (define_insn "*ldi_conditional"
4253 [(set (match_operand:QI 0 "reg_operand" "=r,r")
4254 (if_then_else:QI (match_operator 1 "comparison_operator"
4255 [(reg:CC 21) (const_int 0)])
4256 (match_operand:QI 2 "src_operand" "rIm,0")
4257 (match_operand:QI 3 "src_operand" "0,rIm")))]
4258 ""
4259 "@
4260 ldi%1\\t%2,%0
4261 ldi%I1\\t%3,%0"
4262 [(set_attr "type" "binary")])
4264 (define_insn "*ldi_conditional_noov"
4265 [(set (match_operand:QI 0 "reg_operand" "=r,r")
4266 (if_then_else:QI (match_operator 1 "comparison_operator"
4267 [(reg:CC_NOOV 21) (const_int 0)])
4268 (match_operand:QI 2 "src_operand" "rIm,0")
4269 (match_operand:QI 3 "src_operand" "0,rIm")))]
4270 "GET_CODE (operands[1]) != LE
4271 && GET_CODE (operands[1]) != GE
4272 && GET_CODE (operands[1]) != LT
4273 && GET_CODE (operands[1]) != GT"
4274 "@
4275 ldi%1\\t%2,%0
4276 ldi%I1\\t%3,%0"
4277 [(set_attr "type" "binary")])
4279 (define_insn "*ldi_on_overflow"
4280 [(set (match_operand:QI 0 "reg_operand" "=r")
4281 (unspec:QI [(match_operand:QI 1 "src_operand" "rIm")] 13))
4282 (use (reg:CC 21))]
4283 ""
4284 "ldiv\\t%1,%0"
4285 [(set_attr "type" "unary")])
4287 ; Move operand 2 to operand 0 if condition (operand 1) is true
4288 ; else move operand 3 to operand 0.
4289 ; The temporary register is required below because some of the operands
4290 ; might be identical (namely 0 and 2).
4291 ;
4292 (define_expand "movqicc"
4293 [(set (match_operand:QI 0 "reg_operand" "")
4294 (if_then_else:QI (match_operand 1 "comparison_operator" "")
4295 (match_operand:QI 2 "src_operand" "")
4296 (match_operand:QI 3 "src_operand" "")))]
4297 ""
4298 "{
4299 enum rtx_code code = GET_CODE (operands[1]);
4300 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4301 if (ccreg == NULL_RTX) FAIL;
4302 emit_insn (gen_rtx_SET (QImode, operands[0],
4303 gen_rtx_IF_THEN_ELSE (QImode,
4304 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4305 operands[2], operands[3])));
4306 DONE;}")
4308 (define_insn "*ldf_conditional"
4309 [(set (match_operand:QF 0 "reg_operand" "=f,f")
4310 (if_then_else:QF (match_operator 1 "comparison_operator"
4311 [(reg:CC 21) (const_int 0)])
4312 (match_operand:QF 2 "src_operand" "fHm,0")
4313 (match_operand:QF 3 "src_operand" "0,fHm")))]
4314 ""
4315 "@
4316 ldf%1\\t%2,%0
4317 ldf%I1\\t%3,%0"
4318 [(set_attr "type" "binary")])
4320 (define_insn "*ldf_conditional_noov"
4321 [(set (match_operand:QF 0 "reg_operand" "=f,f")
4322 (if_then_else:QF (match_operator 1 "comparison_operator"
4323 [(reg:CC_NOOV 21) (const_int 0)])
4324 (match_operand:QF 2 "src_operand" "fHm,0")
4325 (match_operand:QF 3 "src_operand" "0,fHm")))]
4326 "GET_CODE (operands[1]) != LE
4327 && GET_CODE (operands[1]) != GE
4328 && GET_CODE (operands[1]) != LT
4329 && GET_CODE (operands[1]) != GT"
4330 "@
4331 ldf%1\\t%2,%0
4332 ldf%I1\\t%3,%0"
4333 [(set_attr "type" "binary")])
4335 (define_expand "movqfcc"
4336 [(set (match_operand:QF 0 "reg_operand" "")
4337 (if_then_else:QF (match_operand 1 "comparison_operator" "")
4338 (match_operand:QF 2 "src_operand" "")
4339 (match_operand:QF 3 "src_operand" "")))]
4340 ""
4341 "{
4342 enum rtx_code code = GET_CODE (operands[1]);
4343 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4344 if (ccreg == NULL_RTX) FAIL;
4345 emit_insn (gen_rtx_SET (QFmode, operands[0],
4346 gen_rtx_IF_THEN_ELSE (QFmode,
4347 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4348 operands[2], operands[3])));
4349 DONE;}")
4351 (define_insn "*ldhf_conditional"
4352 [(set (match_operand:HF 0 "reg_operand" "=h,h")
4353 (if_then_else:HF (match_operator 1 "comparison_operator"
4354 [(reg:CC 21) (const_int 0)])
4355 (match_operand:HF 2 "src_operand" "hH,0")
4356 (match_operand:HF 3 "src_operand" "0,hH")))]
4357 ""
4358 "@
4359 ldf%1\\t%2,%0
4360 ldf%I1\\t%3,%0"
4361 [(set_attr "type" "binary")])
4363 (define_insn "*ldhf_conditional_noov"
4364 [(set (match_operand:HF 0 "reg_operand" "=h,h")
4365 (if_then_else:HF (match_operator 1 "comparison_operator"
4366 [(reg:CC_NOOV 21) (const_int 0)])
4367 (match_operand:HF 2 "src_operand" "hH,0")
4368 (match_operand:HF 3 "src_operand" "0,hH")))]
4369 "GET_CODE (operands[1]) != LE
4370 && GET_CODE (operands[1]) != GE
4371 && GET_CODE (operands[1]) != LT
4372 && GET_CODE (operands[1]) != GT"
4373 "@
4374 ldf%1\\t%2,%0
4375 ldf%I1\\t%3,%0"
4376 [(set_attr "type" "binary")])
4378 (define_expand "movhfcc"
4379 [(set (match_operand:HF 0 "reg_operand" "")
4380 (if_then_else:HF (match_operand 1 "comparison_operator" "")
4381 (match_operand:HF 2 "src_operand" "")
4382 (match_operand:HF 3 "src_operand" "")))]
4383 ""
4384 "{
4385 enum rtx_code code = GET_CODE (operands[1]);
4386 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
4387 if (ccreg == NULL_RTX) FAIL;
4388 emit_insn (gen_rtx_SET (HFmode, operands[0],
4389 gen_rtx_IF_THEN_ELSE (HFmode,
4390 gen_rtx (code, VOIDmode, ccreg, const0_rtx),
4391 operands[2], operands[3])));
4392 DONE;}")
4394 (define_expand "seq"
4395 [(set (match_operand:QI 0 "reg_operand" "")
4396 (const_int 0))
4397 (set (match_dup 0)
4398 (if_then_else:QI (eq (match_dup 1) (const_int 0))
4399 (const_int 1)
4400 (match_dup 0)))]
4401 ""
4402 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
4404 (define_expand "sne"
4405 [(set (match_operand:QI 0 "reg_operand" "")
4406 (const_int 0))
4407 (set (match_dup 0)
4408 (if_then_else:QI (ne (match_dup 1) (const_int 0))
4409 (const_int 1)
4410 (match_dup 0)))]
4411 ""
4412 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
4414 (define_expand "slt"
4415 [(set (match_operand:QI 0 "reg_operand" "")
4416 (const_int 0))
4417 (set (match_dup 0)
4418 (if_then_else:QI (lt (match_dup 1) (const_int 0))
4419 (const_int 1)
4420 (match_dup 0)))]
4421 ""
4422 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
4423 if (operands[1] == NULL_RTX) FAIL;")
4425 (define_expand "sltu"
4426 [(set (match_operand:QI 0 "reg_operand" "")
4427 (const_int 0))
4428 (set (match_dup 0)
4429 (if_then_else:QI (ltu (match_dup 1) (const_int 0))
4430 (const_int 1)
4431 (match_dup 0)))]
4432 ""
4433 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
4435 (define_expand "sgt"
4436 [(set (match_operand:QI 0 "reg_operand" "")
4437 (const_int 0))
4438 (set (match_dup 0)
4439 (if_then_else:QI (gt (match_dup 1) (const_int 0))
4440 (const_int 1)
4441 (match_dup 0)))]
4442 ""
4443 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
4444 if (operands[1] == NULL_RTX) FAIL;")
4446 (define_expand "sgtu"
4447 [(set (match_operand:QI 0 "reg_operand" "")
4448 (const_int 0))
4449 (set (match_dup 0)
4450 (if_then_else:QI (gtu (match_dup 1) (const_int 0))
4451 (const_int 1)
4452 (match_dup 0)))]
4453 ""
4454 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
4456 (define_expand "sle"
4457 [(set (match_operand:QI 0 "reg_operand" "")
4458 (const_int 0))
4459 (set (match_dup 0)
4460 (if_then_else:QI (le (match_dup 1) (const_int 0))
4461 (const_int 1)
4462 (match_dup 0)))]
4463 ""
4464 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
4465 if (operands[1] == NULL_RTX) FAIL;")
4467 (define_expand "sleu"
4468 [(set (match_operand:QI 0 "reg_operand" "")
4469 (const_int 0))
4470 (set (match_dup 0)
4471 (if_then_else:QI (leu (match_dup 1) (const_int 0))
4472 (const_int 1)
4473 (match_dup 0)))]
4474 ""
4475 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
4477 (define_expand "sge"
4478 [(set (match_operand:QI 0 "reg_operand" "")
4479 (const_int 0))
4480 (set (match_dup 0)
4481 (if_then_else:QI (ge (match_dup 1) (const_int 0))
4482 (const_int 1)
4483 (match_dup 0)))]
4484 ""
4485 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
4486 if (operands[1] == NULL_RTX) FAIL;")
4488 (define_expand "sgeu"
4489 [(set (match_operand:QI 0 "reg_operand" "")
4490 (const_int 0))
4491 (set (match_dup 0)
4492 (if_then_else:QI (geu (match_dup 1) (const_int 0))
4493 (const_int 1)
4494 (match_dup 0)))]
4495 ""
4496 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
4498 (define_split
4499 [(set (match_operand:QI 0 "reg_operand" "")
4500 (match_operator:QI 1 "comparison_operator" [(reg:CC 21) (const_int 0)]))]
4501 "reload_completed"
4502 [(set (match_dup 0) (const_int 0))
4503 (set (match_dup 0)
4504 (if_then_else:QI (match_op_dup 1 [(reg:CC 21) (const_int 0)])
4505 (const_int 1)
4506 (match_dup 0)))]
4507 "")
4509 (define_split
4510 [(set (match_operand:QI 0 "reg_operand" "")
4511 (match_operator:QI 1 "comparison_operator" [(reg:CC_NOOV 21) (const_int 0)]))]
4512 "reload_completed"
4513 [(set (match_dup 0) (const_int 0))
4514 (set (match_dup 0)
4515 (if_then_else:QI (match_op_dup 1 [(reg:CC_NOOV 21) (const_int 0)])
4516 (const_int 1)
4517 (match_dup 0)))]
4518 "")
4520 (define_insn "*bu"
4521 [(set (pc)
4522 (unspec [(match_operand:QI 0 "reg_operand" "r")] 1))]
4523 ""
4524 "bu%#\\t%0"
4525 [(set_attr "type" "jump")])
4527 (define_expand "caseqi"
4528 [(parallel [(set (match_dup 5)
4529 (minus:QI (match_operand:QI 0 "reg_operand" "")
4530 (match_operand:QI 1 "src_operand" "")))
4531 (clobber (reg:CC_NOOV 21))])
4532 (set (reg:CC 21)
4533 (compare:CC (match_dup 5)
4534 (match_operand:QI 2 "src_operand" "")))
4535 (set (pc)
4536 (if_then_else (gtu (reg:CC 21)
4537 (const_int 0))
4538 (label_ref (match_operand 4 "" ""))
4539 (pc)))
4540 (parallel [(set (match_dup 6)
4541 (plus:QI (match_dup 5)
4542 (label_ref:QI (match_operand 3 "" ""))))
4543 (clobber (reg:CC_NOOV 21))])
4544 (set (match_dup 7)
4545 (mem:QI (match_dup 6)))
4546 (set (pc) (match_dup 7))]
4547 ""
4548 "operands[5] = gen_reg_rtx (QImode);
4549 operands[6] = gen_reg_rtx (QImode);
4550 operands[7] = gen_reg_rtx (QImode);")
4552 ;
4553 ; PARALLEL FLOAT INSTRUCTIONS
4554 ;
4555 ; This patterns are under development
4557 ;
4558 ; ABSF/STF
4559 ;
4561 (define_insn "*absqf2_movqf_clobber"
4562 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4563 (abs:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
4564 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4565 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4566 (clobber (reg:CC_NOOV 21))]
4567 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4568 "absf\\t%1,%0\\n||\\tstf\\t%3,%2"
4569 [(set_attr "type" "binarycc")])
4571 ;
4572 ; ADDF/STF
4573 ;
4575 (define_insn "*addqf3_movqf_clobber"
4576 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q,q")
4577 (plus:QF (match_operand:QF 1 "parallel_operand" "%q,S<>")
4578 (match_operand:QF 2 "parallel_operand" "S<>,q")))
4579 (set (match_operand:QF 3 "par_ind_operand" "=S<>,S<>")
4580 (match_operand:QF 4 "ext_low_reg_operand" "q,q"))
4581 (clobber (reg:CC 21))]
4582 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4583 "addf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4584 [(set_attr "type" "binarycc,binarycc")])
4586 ;
4587 ; FLOAT/STF
4588 ;
4590 (define_insn "*floatqiqf2_movqf_clobber"
4591 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4592 (float:QF (match_operand:QI 1 "par_ind_operand" "S<>")))
4593 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4594 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4595 (clobber (reg:CC 21))]
4596 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4597 "float\\t%1,%0\\n||\\tstf\\t%3,%2"
4598 [(set_attr "type" "binarycc")])
4600 ;
4601 ; MPYF/ADDF
4602 ;
4604 (define_insn "*mulqf3_addqf3_clobber"
4605 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t,t,t,t")
4606 (mult:QF (match_operand:QF 1 "parallel_operand" "%S<>!V,q,S<>!V,q")
4607 (match_operand:QF 2 "parallel_operand" "q,S<>!V,S<>!V,q")))
4608 (set (match_operand:QF 3 "r2r3_reg_operand" "=u,u,u,u")
4609 (plus:QF (match_operand:QF 4 "parallel_operand" "%S<>!V,q,q,S<>!V")
4610 (match_operand:QF 5 "parallel_operand" "q,S<>!V,q,S<>!V")))
4611 (clobber (reg:CC_NOOV 21))]
4612 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
4613 "mpyf3\\t%2,%1,%0\\n||\\taddf3\\t%5,%4,%3"
4614 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4617 ;
4618 ; MPYF/STF
4619 ;
4621 (define_insn "*mulqf3_movqf_clobber"
4622 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q,q")
4623 (mult:QF (match_operand:QF 1 "parallel_operand" "%q,S<>")
4624 (match_operand:QF 2 "parallel_operand" "S<>,q")))
4625 (set (match_operand:QF 3 "par_ind_operand" "=S<>,S<>")
4626 (match_operand:QF 4 "ext_low_reg_operand" "q,q"))
4627 (clobber (reg:CC 21))]
4628 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4629 "mpyf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4630 [(set_attr "type" "binarycc,binarycc")])
4632 ;
4633 ; MPYF/SUBF
4634 ;
4636 (define_insn "*mulqf3_subqf3_clobber"
4637 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t,t")
4638 (mult:QF (match_operand:QF 1 "parallel_operand" "S<>,q")
4639 (match_operand:QF 2 "parallel_operand" "q,S<>")))
4640 (set (match_operand:QF 3 "r2r3_reg_operand" "=u,u")
4641 (minus:QF (match_operand:QF 4 "parallel_operand" "S<>,q")
4642 (match_operand:QF 5 "parallel_operand" "q,S<>")))
4643 (clobber (reg:CC 21))]
4644 "TARGET_PARALLEL_MPY && valid_parallel_operands_6 (operands, QFmode)"
4645 "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%5,%4,%3"
4646 [(set_attr "type" "binarycc,binarycc")])
4648 ;
4649 ; MPYF/LDF 0
4650 ;
4652 (define_insn "*mulqf3_clrqf_clobber"
4653 [(set (match_operand:QF 0 "r0r1_reg_operand" "=t")
4654 (mult:QF (match_operand:QF 1 "par_ind_operand" "%S<>")
4655 (match_operand:QF 2 "par_ind_operand" "S<>")))
4656 (set (match_operand:QF 3 "r2r3_reg_operand" "=u")
4657 (match_operand:QF 4 "fp_zero_operand" "G"))
4658 (clobber (reg:CC 21))]
4659 "TARGET_PARALLEL_MPY"
4660 "mpyf3\\t%2,%1,%0\\n||\\tsubf3\\t%3,%3,%3"
4661 [(set_attr "type" "binarycc")])
4663 ;
4664 ; NEGF/STF
4665 ;
4667 (define_insn "*negqf2_movqf_clobber"
4668 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4669 (neg:QF (match_operand:QF 1 "par_ind_operand" "S<>")))
4670 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4671 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4672 (clobber (reg:CC 21))]
4673 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4674 "negf\\t%1,%0\\n||\\tstf\\t%3,%2"
4675 [(set_attr "type" "binarycc")])
4677 ;
4678 ; SUBF/STF
4679 ;
4681 (define_insn "*subqf3_movqf_clobber"
4682 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4683 (minus:QF (match_operand:QF 1 "ext_low_reg_operand" "q")
4684 (match_operand:QF 2 "par_ind_operand" "S<>")))
4685 (set (match_operand:QF 3 "par_ind_operand" "=S<>")
4686 (match_operand:QF 4 "ext_low_reg_operand" "q"))
4687 (clobber (reg:CC 21))]
4688 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QFmode)"
4689 "subf3\\t%2,%1,%0\\n||\\tstf\\t%4,%3"
4690 [(set_attr "type" "binarycc")])
4692 ;
4693 ; TOIEEE/STF
4694 ;
4696 (define_insn "*toieee_movqf_clobber"
4697 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4698 (unspec:QF [(match_operand:QF 1 "par_ind_operand" "S<>")] 23))
4699 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4700 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4701 (clobber (reg:CC 21))]
4702 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4703 "toieee\\t%1,%0\\n||\\tstf\\t%3,%2"
4704 [(set_attr "type" "binarycc")])
4706 ;
4707 ; FRIEEE/STF
4708 ;
4710 (define_insn "*frieee_movqf_clobber"
4711 [(set (match_operand:QF 0 "ext_low_reg_operand" "=q")
4712 (unspec:QF [(match_operand:QF 1 "par_ind_operand" "S<>")] 24))
4713 (set (match_operand:QF 2 "par_ind_operand" "=S<>")
4714 (match_operand:QF 3 "ext_low_reg_operand" "q"))
4715 (clobber (reg:CC 21))]
4716 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QFmode)"
4717 "frieee\\t%1,%0\\n||\\tstf\\t%3,%2"
4718 [(set_attr "type" "binarycc")])
4720 ;
4721 ; PARALLEL INTEGER INSTRUCTIONS
4722 ;
4724 ;
4725 ; ABSI/STI
4726 ;
4728 (define_insn "*absqi2_movqi_clobber"
4729 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4730 (abs:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4731 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4732 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4733 (clobber (reg:CC_NOOV 21))]
4734 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4735 "absi\\t%1,%0\\n||\\tsti\\t%3,%2"
4736 [(set_attr "type" "binarycc")])
4738 ;
4739 ; ADDI/STI
4740 ;
4742 (define_insn "*addqi3_movqi_clobber"
4743 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4744 (plus:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4745 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4746 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4747 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4748 (clobber (reg:CC 21))]
4749 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4750 "addi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4751 [(set_attr "type" "binarycc,binarycc")])
4753 ;
4754 ; AND/STI
4755 ;
4757 (define_insn "*andqi3_movqi_clobber"
4758 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4759 (and:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4760 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4761 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4762 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4763 (clobber (reg:CC 21))]
4764 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4765 "and3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4766 [(set_attr "type" "binarycc,binarycc")])
4768 ;
4769 ; ASH(left)/STI
4770 ;
4772 (define_insn "*ashlqi3_movqi_clobber"
4773 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4774 (ashift:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4775 (match_operand:QI 2 "ext_low_reg_operand" "q")))
4776 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4777 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4778 (clobber (reg:CC 21))]
4779 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4780 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4781 [(set_attr "type" "binarycc")])
4783 ;
4784 ; ASH(right)/STI
4785 ;
4787 (define_insn "*ashrqi3_movqi_clobber"
4788 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4789 (ashiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4790 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
4791 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4792 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4793 (clobber (reg:CC 21))]
4794 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4795 "ash3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4796 [(set_attr "type" "binarycc")])
4798 ;
4799 ; FIX/STI
4800 ;
4802 (define_insn "*fixqfqi2_movqi_clobber"
4803 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4804 (fix:QI (match_operand:QF 1 "par_ind_operand" "S<>")))
4805 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4806 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4807 (clobber (reg:CC 21))]
4808 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4809 "fix\\t%1,%0\\n||\\tsti\\t%3,%2"
4810 [(set_attr "type" "binarycc")])
4812 ;
4813 ; LSH(right)/STI
4814 ;
4816 (define_insn "*lshrqi3_movqi_clobber"
4817 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4818 (lshiftrt:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4819 (neg:QI (match_operand:QI 2 "ext_low_reg_operand" "q"))))
4820 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4821 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4822 (clobber (reg:CC 21))]
4823 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4824 "lsh3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4825 [(set_attr "type" "binarycc")])
4827 ;
4828 ; MPYI/ADDI
4829 ;
4831 (define_insn "*mulqi3_addqi3_clobber"
4832 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t,t,t,t")
4833 (mult:QI (match_operand:QI 1 "parallel_operand" "%S<>!V,q,S<>!V,q")
4834 (match_operand:QI 2 "parallel_operand" "q,S<>!V,S<>!V,q")))
4835 (set (match_operand:QI 3 "r2r3_reg_operand" "=u,u,u,u")
4836 (plus:QI (match_operand:QI 4 "parallel_operand" "%S<>!V,q,q,S<>!V")
4837 (match_operand:QI 5 "parallel_operand" "q,S<>!V,q,S<>!V")))
4838 (clobber (reg:CC 21))]
4839 "TARGET_PARALLEL_MPY && TARGET_MPYI
4840 && valid_parallel_operands_6 (operands, QImode)"
4841 "mpyi3\\t%2,%1,%0\\n||\\taddi3\\t%5,%4,%3"
4842 [(set_attr "type" "binarycc,binarycc,binarycc,binarycc")])
4845 ;
4846 ; MPYI/STI
4847 ;
4849 (define_insn "*mulqi3_movqi_clobber"
4850 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4851 (mult:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4852 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4853 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4854 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4855 (clobber (reg:CC 21))]
4856 "TARGET_PARALLEL && TARGET_MPYI
4857 && valid_parallel_operands_5 (operands, QImode)"
4858 "mpyi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4859 [(set_attr "type" "binarycc,binarycc")])
4861 ;
4862 ; MPYI/SUBI
4863 ;
4865 (define_insn "*mulqi3_subqi3_clobber"
4866 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t,t")
4867 (mult:QI (match_operand:QI 1 "parallel_operand" "S<>,q")
4868 (match_operand:QI 2 "parallel_operand" "q,S<>")))
4869 (set (match_operand:QI 3 "r2r3_reg_operand" "=u,u")
4870 (minus:QI (match_operand:QI 4 "parallel_operand" "S<>,q")
4871 (match_operand:QI 5 "parallel_operand" "q,S<>")))
4872 (clobber (reg:CC 21))]
4873 "TARGET_PARALLEL_MPY && TARGET_MPYI
4874 && valid_parallel_operands_6 (operands, QImode)"
4875 "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%5,%4,%3"
4876 [(set_attr "type" "binarycc,binarycc")])
4878 ;
4879 ; MPYI/LDI 0
4880 ;
4882 (define_insn "*mulqi3_clrqi_clobber"
4883 [(set (match_operand:QI 0 "r0r1_reg_operand" "=t")
4884 (mult:QI (match_operand:QI 1 "par_ind_operand" "%S<>")
4885 (match_operand:QI 2 "par_ind_operand" "S<>")))
4886 (set (match_operand:QI 3 "r2r3_reg_operand" "=u")
4887 (const_int 0))
4888 (clobber (reg:CC 21))]
4889 "TARGET_PARALLEL_MPY && TARGET_MPYI"
4890 "mpyi3\\t%2,%1,%0\\n||\\tsubi3\\t%3,%3,%3"
4891 [(set_attr "type" "binarycc")])
4893 ;
4894 ; NEGI/STI
4895 ;
4897 (define_insn "*negqi2_movqi_clobber"
4898 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4899 (neg:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4900 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4901 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4902 (clobber (reg:CC 21))]
4903 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4904 "negi\\t%1,%0\\n||\\tsti\\t%3,%2"
4905 [(set_attr "type" "binarycc")])
4907 ;
4908 ; NOT/STI
4909 ;
4911 (define_insn "*notqi2_movqi_clobber"
4912 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4913 (not:QI (match_operand:QI 1 "par_ind_operand" "S<>")))
4914 (set (match_operand:QI 2 "par_ind_operand" "=S<>")
4915 (match_operand:QI 3 "ext_low_reg_operand" "q"))
4916 (clobber (reg:CC 21))]
4917 "TARGET_PARALLEL && valid_parallel_operands_4 (operands, QImode)"
4918 "not\\t%1,%0\\n||\\tsti\\t%3,%2"
4919 [(set_attr "type" "binarycc")])
4921 ;
4922 ; OR/STI
4923 ;
4925 (define_insn "*iorqi3_movqi_clobber"
4926 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4927 (ior:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4928 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4929 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4930 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4931 (clobber (reg:CC 21))]
4932 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4933 "or3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4934 [(set_attr "type" "binarycc,binarycc")])
4936 ;
4937 ; SUBI/STI
4938 ;
4940 (define_insn "*subqi3_movqi_clobber"
4941 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q")
4942 (minus:QI (match_operand:QI 1 "par_ind_operand" "S<>")
4943 (match_operand:QI 2 "ext_low_reg_operand" "q")))
4944 (set (match_operand:QI 3 "par_ind_operand" "=S<>")
4945 (match_operand:QI 4 "ext_low_reg_operand" "q"))
4946 (clobber (reg:CC 21))]
4947 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4948 "subi3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4949 [(set_attr "type" "binarycc")])
4951 ;
4952 ; XOR/STI
4953 ;
4955 (define_insn "*xorqi3_movqi_clobber"
4956 [(set (match_operand:QI 0 "ext_low_reg_operand" "=q,q")
4957 (xor:QI (match_operand:QI 1 "parallel_operand" "%q,S<>")
4958 (match_operand:QI 2 "parallel_operand" "S<>,q")))
4959 (set (match_operand:QI 3 "par_ind_operand" "=S<>,S<>")
4960 (match_operand:QI 4 "ext_low_reg_operand" "q,q"))
4961 (clobber (reg:CC 21))]
4962 "TARGET_PARALLEL && valid_parallel_operands_5 (operands, QImode)"
4963 "xor3\\t%2,%1,%0\\n||\\tsti\\t%4,%3"
4964 [(set_attr "type" "binarycc,binarycc")])
4966 ;
4967 ; BRANCH/CALL INSTRUCTIONS
4968 ;
4970 ;
4971 ; Branch instructions
4972 ;
4973 (define_insn "*b"
4974 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4975 [(reg:CC 21) (const_int 0)])
4976 (label_ref (match_operand 1 "" ""))
4977 (pc)))]
4978 ""
4979 "*
4980 return c4x_output_cbranch (\"b%0\", insn);"
4981 [(set_attr "type" "jmpc")])
4983 (define_insn "*b_rev"
4984 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4985 [(reg:CC 21) (const_int 0)])
4986 (pc)
4987 (label_ref (match_operand 1 "" ""))))]
4988 ""
4989 "*
4990 return c4x_output_cbranch (\"b%I0\", insn);"
4991 [(set_attr "type" "jmpc")])
4993 (define_insn "*b_noov"
4994 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
4995 [(reg:CC_NOOV 21) (const_int 0)])
4996 (label_ref (match_operand 1 "" ""))
4997 (pc)))]
4998 "GET_CODE (operands[0]) != LE
4999 && GET_CODE (operands[0]) != GE
5000 && GET_CODE (operands[0]) != LT
5001 && GET_CODE (operands[0]) != GT"
5002 "*
5003 return c4x_output_cbranch (\"b%0\", insn);"
5004 [(set_attr "type" "jmpc")])
5006 (define_insn "*b_noov_rev"
5007 [(set (pc) (if_then_else (match_operator 0 "comparison_operator"
5008 [(reg:CC_NOOV 21) (const_int 0)])
5009 (pc)
5010 (label_ref (match_operand 1 "" ""))))]
5011 "GET_CODE (operands[0]) != LE
5012 && GET_CODE (operands[0]) != GE
5013 && GET_CODE (operands[0]) != LT
5014 && GET_CODE (operands[0]) != GT"
5015 "*
5016 return c4x_output_cbranch (\"b%I0\", insn);"
5017 [(set_attr "type" "jmpc")])
5019 (define_expand "beq"
5020 [(set (pc) (if_then_else (eq (match_dup 1) (const_int 0))
5021 (label_ref (match_operand 0 "" ""))
5022 (pc)))]
5023 ""
5024 "operands[1] = c4x_gen_compare_reg (EQ, c4x_compare_op0, c4x_compare_op1);")
5026 (define_expand "bne"
5027 [(set (pc) (if_then_else (ne (match_dup 1) (const_int 0))
5028 (label_ref (match_operand 0 "" ""))
5029 (pc)))]
5030 ""
5031 "operands[1] = c4x_gen_compare_reg (NE, c4x_compare_op0, c4x_compare_op1);")
5033 (define_expand "blt"
5034 [(set (pc) (if_then_else (lt (match_dup 1) (const_int 0))
5035 (label_ref (match_operand 0 "" ""))
5036 (pc)))]
5037 ""
5038 "operands[1] = c4x_gen_compare_reg (LT, c4x_compare_op0, c4x_compare_op1);
5039 if (operands[1] == NULL_RTX) FAIL;")
5041 (define_expand "bltu"
5042 [(set (pc) (if_then_else (ltu (match_dup 1) (const_int 0))
5043 (label_ref (match_operand 0 "" ""))
5044 (pc)))]
5045 ""
5046 "operands[1] = c4x_gen_compare_reg (LTU, c4x_compare_op0, c4x_compare_op1);")
5048 (define_expand "bgt"
5049 [(set (pc) (if_then_else (gt (match_dup 1) (const_int 0))
5050 (label_ref (match_operand 0 "" ""))
5051 (pc)))]
5052 ""
5053 "operands[1] = c4x_gen_compare_reg (GT, c4x_compare_op0, c4x_compare_op1);
5054 if (operands[1] == NULL_RTX) FAIL;")
5056 (define_expand "bgtu"
5057 [(set (pc) (if_then_else (gtu (match_dup 1) (const_int 0))
5058 (label_ref (match_operand 0 "" ""))
5059 (pc)))]
5060 ""
5061 "operands[1] = c4x_gen_compare_reg (GTU, c4x_compare_op0, c4x_compare_op1);")
5063 (define_expand "ble"
5064 [(set (pc) (if_then_else (le (match_dup 1) (const_int 0))
5065 (label_ref (match_operand 0 "" ""))
5066 (pc)))]
5067 ""
5068 "operands[1] = c4x_gen_compare_reg (LE, c4x_compare_op0, c4x_compare_op1);
5069 if (operands[1] == NULL_RTX) FAIL;")
5071 (define_expand "bleu"
5072 [(set (pc) (if_then_else (leu (match_dup 1) (const_int 0))
5073 (label_ref (match_operand 0 "" ""))
5074 (pc)))]
5075 ""
5076 "operands[1] = c4x_gen_compare_reg (LEU, c4x_compare_op0, c4x_compare_op1);")
5078 (define_expand "bge"
5079 [(set (pc) (if_then_else (ge (match_dup 1) (const_int 0))
5080 (label_ref (match_operand 0 "" ""))
5081 (pc)))]
5082 ""
5083 "operands[1] = c4x_gen_compare_reg (GE, c4x_compare_op0, c4x_compare_op1);
5084 if (operands[1] == NULL_RTX) FAIL;")
5086 (define_expand "bgeu"
5087 [(set (pc) (if_then_else (geu (match_dup 1) (const_int 0))
5088 (label_ref (match_operand 0 "" ""))
5089 (pc)))]
5090 ""
5091 "operands[1] = c4x_gen_compare_reg (GEU, c4x_compare_op0, c4x_compare_op1);")
5093 (define_insn "*b_reg"
5094 [(set (pc) (match_operand:QI 0 "reg_operand" "r"))]
5095 ""
5096 "bu%#\\t%0"
5097 [(set_attr "type" "jump")])
5099 (define_expand "indirect_jump"
5100 [(set (pc) (match_operand:QI 0 "reg_operand" ""))]
5101 ""
5102 "")
5104 (define_insn "tablejump"
5105 [(set (pc) (match_operand:QI 0 "src_operand" "r"))
5106 (use (label_ref (match_operand 1 "" "")))]
5107 ""
5108 "bu%#\\t%0"
5109 [(set_attr "type" "jump")])
5111 ;
5112 ; CALL
5113 ;
5114 (define_insn "*call_c3x"
5115 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5116 (match_operand:QI 1 "general_operand" ""))
5117 (clobber (reg:QI 31))]
5118 ;; Operand 1 not really used on the C4x. The C30 doesn't have reg 31.
5120 "TARGET_C3X"
5121 "call%U0\\t%C0"
5122 [(set_attr "type" "call")])
5124 ; LAJ requires R11 (31) for the return address
5125 (define_insn "*laj"
5126 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5127 (match_operand:QI 1 "general_operand" ""))
5128 (clobber (reg:QI 31))]
5129 ;; Operand 1 not really used on the C4x.
5131 "! TARGET_C3X"
5132 "*
5133 if (final_sequence)
5134 return c4x_check_laj_p (insn)
5135 ? \"nop\\n\\tlaj%U0\\t%C0\" : \"laj%U0\\t%C0\";
5136 else
5137 return \"call%U0\\t%C0\";"
5138 [(set_attr "type" "laj")])
5140 (define_expand "call"
5141 [(parallel [(call (match_operand:QI 0 "" "")
5142 (match_operand:QI 1 "general_operand" ""))
5143 (clobber (reg:QI 31))])]
5144 ""
5145 "
5146 {
5147 if (GET_CODE (operands[0]) == MEM
5148 && ! call_address_operand (XEXP (operands[0], 0), Pmode))
5149 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
5150 force_reg (Pmode, XEXP (operands[0], 0)));
5151 }")
5153 (define_insn "nodb_call"
5154 [(call (mem:QI (match_operand:QI 0 "call_address_operand" "Ur"))
5155 (const_int 0))]
5156 ""
5157 "call%U0\\t%C0"
5158 [(set_attr "type" "call")])
5160 (define_insn "*callv_c3x"
5161 [(set (match_operand 0 "" "=r")
5162 (call (mem:QI (match_operand:QI 1 "call_address_operand" "Ur"))
5163 (match_operand:QI 2 "general_operand" "")))
5164 (clobber (reg:QI 31))]
5165 ;; Operand 0 and 2 not really used for the C4x.
5166 ;; The C30 doesn't have reg 31.
5168 "TARGET_C3X"
5169 "call%U1\\t%C1"
5170 [(set_attr "type" "call")])
5172 ; LAJ requires R11 (31) for the return address
5173 (define_insn "*lajv"
5174 [(set (match_operand 0 "" "=r")
5175 (call (mem:QI (match_operand:QI 1 "call_address_operand" "Ur"))
5176 (match_operand:QI 2 "general_operand" "")))
5177 (clobber (reg:QI 31))]
5178 ;; Operand 0 and 2 not really used in the C30 instruction.
5180 "! TARGET_C3X"
5181 "*
5182 if (final_sequence)
5183 return c4x_check_laj_p (insn)
5184 ? \"nop\\n\\tlaj%U1\\t%C1\" : \"laj%U1\\t%C1\";
5185 else
5186 return \"call%U1\\t%C1\";"
5187 [(set_attr "type" "laj")])
5189 (define_expand "call_value"
5190 [(parallel [(set (match_operand 0 "" "")
5191 (call (match_operand:QI 1 "" "")
5192 (match_operand:QI 2 "general_operand" "")))
5193 (clobber (reg:QI 31))])]
5194 ""
5195 "
5196 {
5197 if (GET_CODE (operands[0]) == MEM
5198 && ! call_address_operand (XEXP (operands[1], 0), Pmode))
5199 operands[0] = gen_rtx_MEM (GET_MODE (operands[1]),
5200 force_reg (Pmode, XEXP (operands[1], 0)));
5201 }")
5203 (define_insn "return"
5204 [(return)]
5205 "c4x_null_epilogue_p ()"
5206 "rets"
5207 [(set_attr "type" "rets")])
5209 (define_insn "return_from_epilogue"
5210 [(return)]
5211 "reload_completed && ! c4x_interrupt_function_p ()"
5212 "rets"
5213 [(set_attr "type" "rets")])
5215 (define_insn "return_from_interrupt_epilogue"
5216 [(return)]
5217 "reload_completed && c4x_interrupt_function_p ()"
5218 "reti"
5219 [(set_attr "type" "rets")])
5221 (define_insn "*return_cc"
5222 [(set (pc)
5223 (if_then_else (match_operator 0 "comparison_operator"
5224 [(reg:CC 21) (const_int 0)])
5225 (return)
5226 (pc)))]
5227 "c4x_null_epilogue_p ()"
5228 "rets%0"
5229 [(set_attr "type" "rets")])
5231 (define_insn "*return_cc_noov"
5232 [(set (pc)
5233 (if_then_else (match_operator 0 "comparison_operator"
5234 [(reg:CC_NOOV 21) (const_int 0)])
5235 (return)
5236 (pc)))]
5237 "GET_CODE (operands[0]) != LE
5238 && GET_CODE (operands[0]) != GE
5239 && GET_CODE (operands[0]) != LT
5240 && GET_CODE (operands[0]) != GT
5241 && c4x_null_epilogue_p ()"
5242 "rets%0"
5243 [(set_attr "type" "rets")])
5245 (define_insn "*return_cc_inverse"
5246 [(set (pc)
5247 (if_then_else (match_operator 0 "comparison_operator"
5248 [(reg:CC 21) (const_int 0)])
5249 (pc)
5250 (return)))]
5251 "c4x_null_epilogue_p ()"
5252 "rets%I0"
5253 [(set_attr "type" "rets")])
5255 (define_insn "*return_cc_noov_inverse"
5256 [(set (pc)
5257 (if_then_else (match_operator 0 "comparison_operator"
5258 [(reg:CC_NOOV 21) (const_int 0)])
5259 (pc)
5260 (return)))]
5261 "GET_CODE (operands[0]) != LE
5262 && GET_CODE (operands[0]) != GE
5263 && GET_CODE (operands[0]) != LT
5264 && GET_CODE (operands[0]) != GT
5265 && c4x_null_epilogue_p ()"
5266 "rets%I0"
5267 [(set_attr "type" "rets")])
5269 (define_insn "jump"
5270 [(set (pc) (label_ref (match_operand 0 "" "")))]
5271 ""
5272 "br%#\\t%l0"
5273 [(set_attr "type" "jump")])
5275 (define_insn "trap"
5276 [(trap_if (const_int 1) (const_int 31))]
5277 ""
5278 "trapu\\t31"
5279 [(set_attr "type" "call")])
5281 (define_expand "conditional_trap"
5282 [(trap_if (match_operand 0 "comparison_operator" "")
5283 (match_operand 1 "const_int_operand" ""))]
5284 ""
5285 "{
5286 enum rtx_code code = GET_CODE (operands[1]);
5287 rtx ccreg = c4x_gen_compare_reg (code, c4x_compare_op0, c4x_compare_op1);
5288 if (ccreg == NULL_RTX) FAIL;
5289 if (GET_MODE (ccreg) == CCmode)
5290 emit_insn (gen_cond_trap_cc (operands[0], operands[1]));
5291 else
5292 emit_insn (gen_cond_trap_cc_noov (operands[0], operands[1]));
5293 DONE;}")
5295 (define_insn "cond_trap_cc"
5296 [(trap_if (match_operator 0 "comparison_operator"
5297 [(reg:CC 21) (const_int 0)])
5298 (match_operand 1 "const_int_operand" ""))]
5299 ""
5300 "trap%0\\t31"
5301 [(set_attr "type" "call")])
5303 (define_insn "cond_trap_cc_noov"
5304 [(trap_if (match_operator 0 "comparison_operator"
5305 [(reg:CC_NOOV 21) (const_int 0)])
5306 (match_operand 1 "const_int_operand" ""))]
5307 "GET_CODE (operands[0]) != LE
5308 && GET_CODE (operands[0]) != GE
5309 && GET_CODE (operands[0]) != LT
5310 && GET_CODE (operands[0]) != GT"
5311 "trap%0\\t31"
5312 [(set_attr "type" "call")])
5314 ;
5315 ; DBcond
5316 ;
5317 ; Note we have to emit a dbu instruction if there are no delay slots
5318 ; to fill.
5319 ; Also note that GCC will try to reverse a loop to see if it can
5320 ; utilize this instruction. However, if there are more than one
5321 ; memory reference in the loop, it cannot guarantee that reversing
5322 ; the loop will work :( (see check_dbra_loop() in loop.c)
5323 ; Note that the C3x only decrements the 24 LSBs of the address register
5324 ; and the 8 MSBs are untouched. The C4x uses all 32-bits. We thus
5325 ; have an option to disable this instruction.
5326 (define_insn "*db"
5327 [(set (pc)
5328 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
5329 (const_int 0))
5330 (label_ref (match_operand 1 "" ""))
5331 (pc)))
5332 (set (match_dup 0)
5333 (plus:QI (match_dup 0)
5334 (const_int -1)))
5335 (use (reg:QI 20))
5336 (clobber (reg:CC_NOOV 21))]
5337 "TARGET_DB && TARGET_LOOP_UNSIGNED"
5338 "*
5339 if (which_alternative == 0)
5340 return \"dbu%#\\t%0,%l1\";
5341 else if (which_alternative == 1)
5342 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5343 else if (which_alternative == 2)
5344 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5345 else
5346 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5347 "
5348 [(set_attr "type" "db,jmpc,jmpc,jmpc")])
5350 (define_insn "*db_noclobber"
5351 [(set (pc)
5352 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a")
5353 (const_int 0))
5354 (label_ref (match_operand 1 "" ""))
5355 (pc)))
5356 (set (match_dup 0)
5357 (plus:QI (match_dup 0)
5358 (const_int -1)))]
5359 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5360 "dbu%#\\t%0,%l1"
5361 [(set_attr "type" "db")])
5363 (define_split
5364 [(set (pc)
5365 (if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "")
5366 (const_int 0))
5367 (label_ref (match_operand 1 "" ""))
5368 (pc)))
5369 (set (match_dup 0)
5370 (plus:QI (match_dup 0)
5371 (const_int -1)))
5372 (use (reg:QI 20))
5373 (clobber (reg:CC_NOOV 21))]
5374 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5375 [(parallel [(set (pc)
5376 (if_then_else (ne (match_dup 0)
5377 (const_int 0))
5378 (label_ref (match_dup 1))
5379 (pc)))
5380 (set (match_dup 0)
5381 (plus:QI (match_dup 0)
5382 (const_int -1)))])]
5383 "")
5386 ; This insn is used for some loop tests, typically loops reversed when
5387 ; strength reduction is used. It is actually created when the instruction
5388 ; combination phase combines the special loop test. Since this insn
5389 ; is both a jump insn and has an output, it must deal with its own
5390 ; reloads, hence the `m' constraints.
5392 ; The C4x does the decrement and then compares the result against zero.
5393 ; It branches if the result was greater than or equal to zero.
5394 ; In the RTL the comparison and decrement are assumed to happen
5395 ; at the same time so we bias the iteration counter with by -1
5396 ; when we make the test.
5397 (define_insn "decrement_and_branch_until_zero"
5398 [(set (pc)
5399 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
5400 (const_int -1))
5401 (const_int 0))
5402 (label_ref (match_operand 1 "" ""))
5403 (pc)))
5404 (set (match_dup 0)
5405 (plus:QI (match_dup 0)
5406 (const_int -1)))
5407 (use (reg:QI 20))
5408 (clobber (reg:CC_NOOV 21))]
5409 "TARGET_DB && (find_reg_note (insn, REG_NONNEG, 0) || TARGET_LOOP_UNSIGNED)"
5410 "*
5411 if (which_alternative == 0)
5412 return \"dbu%#\\t%0,%l1\";
5413 else if (which_alternative == 1)
5414 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5415 else if (which_alternative == 2)
5416 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5417 else
5418 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5419 "
5420 [(set_attr "type" "db,jmpc,jmpc,jmpc")])
5422 (define_insn "*decrement_and_branch_until_zero_noclobber"
5423 [(set (pc)
5424 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
5425 (const_int -1))
5426 (const_int 0))
5427 (label_ref (match_operand 1 "" ""))
5428 (pc)))
5429 (set (match_dup 0)
5430 (plus:QI (match_dup 0)
5431 (const_int -1)))]
5432 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5433 "dbu%#\\t%0,%l1"
5434 [(set_attr "type" "db")])
5436 (define_split
5437 [(set (pc)
5438 (if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "")
5439 (const_int -1))
5440 (const_int 0))
5441 (label_ref (match_operand 1 "" ""))
5442 (pc)))
5443 (set (match_dup 0)
5444 (plus:QI (match_dup 0)
5445 (const_int -1)))
5446 (use (reg:QI 20))
5447 (clobber (reg:CC_NOOV 21))]
5448 "reload_completed && TARGET_DB && TARGET_LOOP_UNSIGNED"
5449 [(parallel [(set (pc)
5450 (if_then_else (ge (plus:QI (match_dup 0)
5451 (const_int -1))
5452 (const_int 0))
5453 (label_ref (match_dup 1))
5454 (pc)))
5455 (set (match_dup 0)
5456 (plus:QI (match_dup 0)
5457 (const_int -1)))])]
5458 "")
5460 ;
5461 ; MISC INSTRUCTIONS
5462 ;
5464 ;
5465 ; NOP
5466 ;
5467 (define_insn "nop"
5468 [(const_int 0)]
5469 ""
5470 "nop")
5471 ; Default to misc type attr.
5473 (define_insn "return_indirect_internal"
5474 [(return)
5475 (use (match_operand:QI 0 "reg_operand" ""))]
5476 "reload_completed"
5477 "bu%#\\t%0"
5478 [(set_attr "type" "jump")])
5480 (define_expand "prologue"
5481 [(const_int 1)]
5482 ""
5483 "c4x_expand_prologue (); DONE;")
5485 (define_expand "epilogue"
5486 [(const_int 1)]
5487 ""
5488 "c4x_expand_epilogue (); DONE;")
5490 ;
5491 ; RPTB
5492 ;
5493 (define_insn "rptb_top"
5494 [(use (label_ref (match_operand 0 "" "")))
5495 (use (label_ref (match_operand 1 "" "")))
5496 (clobber (reg:QI 25))
5497 (clobber (reg:QI 26))]
5498 ""
5499 "*
5500 return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
5501 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
5502 "
5503 [(set_attr "type" "repeat_top")])
5505 (define_insn "rpts_top"
5506 [(unspec [(use (label_ref (match_operand 0 "" "")))
5507 (use (label_ref (match_operand 1 "" "")))] 2)
5508 (clobber (reg:QI 25))
5509 (clobber (reg:QI 26))]
5510 ""
5511 "*
5512 return ! final_sequence && c4x_rptb_rpts_p (insn, operands[0])
5513 ? \"rpts\\trc\" : \"rptb%#\\t%l1-1\";
5514 "
5515 [(set_attr "type" "repeat")])
5517 ; This pattern needs to be emitted at the start of the loop to
5518 ; say that RS and RE are loaded.
5519 (define_insn "rptb_init"
5520 [(unspec [(match_operand:QI 0 "register_operand" "va")] 22)
5521 (clobber (reg:QI 25))
5522 (clobber (reg:QI 26))]
5523 ""
5524 ""
5525 [(set_attr "type" "repeat")])
5528 ; operand 0 is the loop count pseudo register
5529 ; operand 1 is the number of loop iterations or 0 if it is unknown
5530 ; operand 2 is the maximum number of loop iterations
5531 ; operand 3 is the number of levels of enclosed loops
5532 (define_expand "doloop_begin"
5533 [(use (match_operand 0 "register_operand" ""))
5534 (use (match_operand:QI 1 "const_int_operand" ""))
5535 (use (match_operand:QI 2 "const_int_operand" ""))
5536 (use (match_operand:QI 3 "const_int_operand" ""))]
5537 ""
5538 "if (INTVAL (operands[3]) > 1 || ! TARGET_RPTB)
5539 FAIL;
5540 emit_insn (gen_rptb_init (operands[0]));
5541 DONE;
5542 ")
5545 ; The RS (25) and RE (26) registers must be unviolate from the top of the loop
5546 ; to here.
5547 (define_insn "rptb_end"
5548 [(set (pc)
5549 (if_then_else (ge (match_operand:QI 0 "register_operand" "+v,?a,!*d,!*x*k,!m")
5550 (const_int 0))
5551 (label_ref (match_operand 1 "" ""))
5552 (pc)))
5553 (set (match_dup 0)
5554 (plus:QI (match_dup 0)
5555 (const_int -1)))
5556 (use (reg:QI 25))
5557 (use (reg:QI 26))
5558 (use (reg:QI 20))
5559 (clobber (reg:CC_NOOV 21))]
5560 ""
5561 "*
5562 if (which_alternative == 0)
5563 return c4x_rptb_nop_p (insn) ? \"nop\" : \"\";
5564 else if (which_alternative == 1 && TARGET_DB)
5565 return \"dbu%#\\t%0,%l1\";
5566 else if (which_alternative == 2)
5567 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tbge\", insn);
5568 else if (which_alternative == 3 || (which_alternative == 1 && ! TARGET_DB))
5569 return c4x_output_cbranch (\"subi\\t1,%0\\n\\tcmpi\\t0,%0\\n\\tbge\", insn);
5570 else
5571 return c4x_output_cbranch (\"push\\tr0\\n\\tldi\\t%0,r0\\n\\tsubi\\t1,r0\\n\\tsti\\tr0,%0\\n\\tpop\\tr0\\n\\tbhs\", insn);
5572 "
5573 [(set_attr "type" "repeat,db,jmpc,jmpc,jmpc")])
5575 (define_split
5576 [(set (pc)
5577 (if_then_else (ge (match_operand:QI 0 "addr_reg_operand" "")
5578 (const_int 0))
5579 (label_ref (match_operand 1 "" ""))
5580 (pc)))
5581 (set (match_dup 0)
5582 (plus:QI (match_dup 0)
5583 (const_int -1)))
5584 (use (match_operand:QI 2 "const_int_operand" ""))
5585 (use (match_operand:QI 3 "const_int_operand" ""))
5586 (use (match_operand:QI 4 "const_int_operand" ""))
5587 (use (reg:QI 25))
5588 (use (reg:QI 26))
5589 (use (reg:QI 20))
5590 (clobber (reg:CC_NOOV 21))]
5591 "reload_completed"
5592 [(parallel [(set (pc)
5593 (if_then_else (ge (match_dup 0)
5594 (const_int 0))
5595 (label_ref (match_dup 1))
5596 (pc)))
5597 (set (match_dup 0)
5598 (plus:QI (match_dup 0)
5599 (const_int -1)))])]
5600 "")
5602 ; operand 0 is the loop count pseudo register
5603 ; operand 1 is the number of loop iterations or 0 if it is unknown
5604 ; operand 2 is the maximum number of loop iterations
5605 ; operand 3 is the number of levels of enclosed loops
5606 ; operand 4 is the label to jump to at the top of the loop
5607 (define_expand "doloop_end"
5608 [(use (match_operand 0 "register_operand" ""))
5609 (use (match_operand:QI 1 "const_int_operand" ""))
5610 (use (match_operand:QI 2 "const_int_operand" ""))
5611 (use (match_operand:QI 3 "const_int_operand" ""))
5612 (use (label_ref (match_operand 4 "" "")))]
5613 ""
5614 "if (! TARGET_LOOP_UNSIGNED
5615 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > ((unsigned) 1 << 31))
5616 FAIL;
5617 if (INTVAL (operands[3]) > 1 || ! TARGET_RPTB)
5618 {
5619 /* The C30 maximum iteration count for DB is 2^24. */
5620 if (! TARGET_DB)
5621 FAIL;
5622 emit_jump_insn (gen_decrement_and_branch_until_zero (operands[0],
5623 operands[4]));
5624 DONE;
5625 }
5626 emit_jump_insn (gen_rptb_end (operands[0], operands[4]));
5627 DONE;
5628 ")
5630 ; The current low overhead looping code is naff and is not failsafe
5631 ; If you want RTPB instructions to be generated, apply the patches
5632 ; from www.elec.canterbury.ac.nz/c4x. This will utilize the
5633 ; doloop_begin and doloop_end patterns in this MD.
5634 (define_expand "decrement_and_branch_on_count"
5635 [(parallel [(set (pc)
5636 (if_then_else (ge (match_operand:QI 0 "register_operand" "")
5637 (const_int 0))
5638 (label_ref (match_operand 1 "" ""))
5639 (pc)))
5640 (set (match_dup 0)
5641 (plus:QI (match_dup 0)
5642 (const_int -1)))
5643 (use (reg:QI 25))
5644 (use (reg:QI 26))
5645 (clobber (reg:CC_NOOV 21))])]
5646 "0"
5647 "")
5649 (define_expand "movstrqi_small2"
5650 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
5651 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
5652 (use (match_operand:QI 2 "immediate_operand" ""))
5653 (use (match_operand:QI 3 "immediate_operand" ""))
5654 (clobber (match_operand:QI 4 "ext_low_reg_operand" ""))])]
5655 ""
5656 "
5657 {
5658 rtx src, dst, tmp;
5659 rtx src_mem, dst_mem;
5660 int len;
5661 int i;
5663 dst = operands[0];
5664 src = operands[1];
5665 len = INTVAL (operands[2]);
5666 tmp = operands[4];
5668 src_mem = gen_rtx_MEM (QImode, src);
5669 dst_mem = gen_rtx_MEM (QImode, dst);
5671 if (TARGET_PARALLEL)
5672 {
5673 emit_insn (gen_movqi (tmp, src_mem));
5674 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5675 for (i = 1; i < len; i++)
5676 {
5677 emit_insn (gen_movqi_parallel (tmp, src_mem, dst_mem, tmp));
5678 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5679 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5680 }
5681 emit_insn (gen_movqi (dst_mem, tmp));
5682 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5683 }
5684 else
5685 {
5686 for (i = 0; i < len; i++)
5687 {
5688 emit_insn (gen_movqi (tmp, src_mem));
5689 emit_insn (gen_movqi (dst_mem, tmp));
5690 emit_insn (gen_addqi3_noclobber (src, src, const1_rtx));
5691 emit_insn (gen_addqi3_noclobber (dst, dst, const1_rtx));
5692 }
5693 }
5694 DONE;
5695 }
5696 ")
5699 ;
5700 ; BLOCK MOVE
5701 ; We should probably get RC loaded when using RPTB automagically...
5702 ; There's probably no need to call _memcpy() if we don't get
5703 ; an immediate operand for the size. We could do a better job here
5704 ; than most memcpy() implementations.
5705 ; operand 2 is the number of bytes
5706 ; operand 3 is the shared alignment
5707 ; operand 4 is a scratch register
5709 (define_insn "movstrqi_small"
5710 [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "+a"))
5711 (mem:BLK (match_operand:QI 1 "addr_reg_operand" "+a")))
5712 (use (match_operand:QI 2 "immediate_operand" "i"))
5713 (use (match_operand:QI 3 "immediate_operand" ""))
5714 (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
5715 (clobber (match_dup 0))
5716 (clobber (match_dup 1))]
5717 ""
5718 "*
5719 {
5720 int i;
5721 int len = INTVAL (operands[2]);
5722 int first = 1;
5724 for (i = 0; i < len; i++)
5725 {
5726 if (first)
5727 output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
5728 else
5729 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5730 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5731 first = 0;
5732 }
5733 return \"\";
5734 }
5735 "
5736 [(set_attr "type" "multi")])
5738 (define_insn "movstrqi_large"
5739 [(set (mem:BLK (match_operand:QI 0 "addr_reg_operand" "+a"))
5740 (mem:BLK (match_operand:QI 1 "addr_reg_operand" "+a")))
5741 (use (match_operand:QI 2 "immediate_operand" "i"))
5742 (use (match_operand:QI 3 "immediate_operand" ""))
5743 (clobber (match_operand:QI 4 "ext_low_reg_operand" "=&q"))
5744 (clobber (match_dup 0))
5745 (clobber (match_dup 1))
5746 (clobber (reg:QI 25))
5747 (clobber (reg:QI 26))
5748 (clobber (reg:QI 27))]
5749 ""
5750 "*
5751 {
5752 int len = INTVAL (operands[2]);
5754 output_asm_insn (\"ldiu\\t*%1++,%4\", operands);
5755 if (TARGET_RPTS_CYCLES (len))
5756 {
5757 output_asm_insn (\"rpts\\t%2-2\", operands);
5758 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5759 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5760 return \"sti\\t%4,*%0++\";
5761 }
5762 else
5763 {
5764 output_asm_insn (\"ldiu\\t%2-2,rc\", operands);
5765 output_asm_insn (\"rptb\\t$+1\", operands);
5766 output_asm_insn (\"sti\\t%4,*%0++\", operands);
5767 output_asm_insn (\"|| ldi\\t*%1++,%4\", operands);
5769 return \"sti\\t%4,*%0++\";
5770 }
5771 }
5772 "
5773 [(set_attr "type" "multi")])
5775 ; Operand 2 is the count, operand 3 is the alignment.
5776 (define_expand "movstrqi"
5777 [(parallel [(set (mem:BLK (match_operand:BLK 0 "src_operand" ""))
5778 (mem:BLK (match_operand:BLK 1 "src_operand" "")))
5779 (use (match_operand:QI 2 "immediate_operand" ""))
5780 (use (match_operand:QI 3 "immediate_operand" ""))])]
5781 ""
5782 "
5783 {
5784 rtx tmp;
5785 if (GET_CODE (operands[2]) != CONST_INT
5786 || INTVAL (operands[2]) > 32767
5787 || INTVAL (operands[2]) <= 0)
5788 {
5789 FAIL; /* Try to call _memcpy */
5790 }
5792 operands[0] = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
5793 operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
5794 tmp = gen_reg_rtx (QImode);
5795 if (INTVAL (operands[2]) < 8)
5796 emit_insn (gen_movstrqi_small2 (operands[0], operands[1], operands[2],
5797 operands[3], tmp));
5798 else
5799 {
5800 emit_insn (gen_movstrqi_large (operands[0], operands[1], operands[2],
5801 operands[3], tmp));
5802 }
5803 DONE;
5804 }")
5807 (define_insn "*cmpstrqi"
5808 [(set (match_operand:QI 0 "ext_reg_operand" "=d")
5809 (compare:QI (mem:BLK (match_operand:QI 1 "addr_reg_operand" "+a"))
5810 (mem:BLK (match_operand:QI 2 "addr_reg_operand" "+a"))))
5811 (use (match_operand:QI 3 "immediate_operand" "i"))
5812 (use (match_operand:QI 4 "immediate_operand" ""))
5813 (clobber (match_operand:QI 5 "std_reg_operand" "=&c"))
5814 (clobber (reg:QI 21))]
5815 ""
5816 "*
5817 {
5818 output_asm_insn (\"ldi\\t%3-1,%5\", operands);
5819 output_asm_insn (\"$1:\tsubi3\\t*%1++,*%2++,%0\", operands);
5820 output_asm_insn (\"dbeq\\t%5,$1\", operands);
5821 return \"\";
5822 }")
5824 (define_expand "cmpstrqi"
5825 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
5826 (compare:QI (match_operand:BLK 1 "general_operand" "")
5827 (match_operand:BLK 2 "general_operand" "")))
5828 (use (match_operand:QI 3 "immediate_operand" ""))
5829 (use (match_operand:QI 4 "immediate_operand" ""))
5830 (clobber (match_dup 5))
5831 (clobber (reg:QI 21))])]
5832 ""
5833 "
5834 {
5835 if (GET_CODE (operands[3]) != CONST_INT
5836 || INTVAL (operands[3]) > 32767
5837 || INTVAL (operands[3]) <= 0)
5838 {
5839 FAIL;
5840 }
5841 operands[1] = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
5842 operands[2] = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
5843 operands[5] = gen_reg_rtx (QImode);
5844 }")
5846 ;
5847 ; TWO OPERAND LONG DOUBLE INSTRUCTIONS
5848 ;
5850 (define_expand "movhf"
5851 [(set (match_operand:HF 0 "src_operand" "")
5852 (match_operand:HF 1 "src_operand" ""))]
5853 ""
5854 "if (c4x_emit_move_sequence (operands, HFmode))
5855 DONE;")
5857 (define_insn "*movhf_noclobber_reg"
5858 [(set (match_operand:HF 0 "reg_operand" "=h")
5859 (match_operand:HF 1 "src_operand" "Hh"))]
5860 "GET_CODE (operands[1]) != MEM"
5861 "ldfu\\t%1,%0"
5862 [(set_attr "type" "unary")])
5864 (define_insn "*movhf_noclobber"
5865 [(set (match_operand:HF 0 "dst_operand" "=h,m")
5866 (match_operand:HF 1 "src_operand" "Hm,h"))]
5867 "reg_operand (operands[0], HFmode) ^ reg_operand (operands[1], HFmode)"
5868 "#"
5869 [(set_attr "type" "multi,multi")])
5871 (define_insn "*movhf_test"
5872 [(set (reg:CC 21)
5873 (compare:CC (match_operand:HF 1 "reg_operand" "h")
5874 (const_int 0)))
5875 (clobber (match_scratch:HF 0 "=h"))]
5876 ""
5877 "ldf\\t%1,%0"
5878 [(set_attr "type" "unarycc")])
5880 (define_insn "*movhf_set"
5881 [(set (reg:CC 21)
5882 (compare:CC (match_operand:HF 1 "reg_operand" "h")
5883 (match_operand:HF 2 "fp_zero_operand" "G")))
5884 (set (match_operand:HF 0 "reg_operand" "=h")
5885 (match_dup 1))]
5886 ""
5887 "ldf\\t%1,%0"
5888 [(set_attr "type" "unarycc")])
5890 (define_split
5891 [(set (match_operand:HF 0 "reg_operand" "")
5892 (match_operand:HF 1 "memory_operand" ""))]
5893 "reload_completed"
5894 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
5895 (set (match_dup 0) (unspec:HF [(subreg:QI (match_dup 0) 0)
5896 (match_dup 3)] 8))]
5897 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
5898 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
5899 PUT_MODE (operands[2], QFmode);
5900 PUT_MODE (operands[3], QImode);")
5902 (define_split
5903 [(set (match_operand:HF 0 "reg_operand" "")
5904 (match_operand:HF 1 "const_operand" ""))]
5905 "reload_completed && 0"
5906 [(set (match_dup 0) (float_extend:HF (match_dup 2)))
5907 (set (match_dup 0) (unspec:HF [(subreg:QI (match_dup 0) 0)
5908 (match_dup 3)] 8))]
5909 "operands[2] = c4x_operand_subword (operands[1], 0, 1, HFmode);
5910 operands[3] = c4x_operand_subword (operands[1], 1, 1, HFmode);
5911 PUT_MODE (operands[2], QFmode);
5912 PUT_MODE (operands[3], QImode);")
5914 (define_split
5915 [(set (match_operand:HF 0 "memory_operand" "")
5916 (match_operand:HF 1 "reg_operand" ""))]
5917 "reload_completed"
5918 [(set (match_dup 2) (float_truncate:QF (match_dup 1)))
5919 (set (match_dup 3) (unspec:QI [(match_dup 1)] 9))]
5920 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HFmode);
5921 operands[3] = c4x_operand_subword (operands[0], 1, 1, HFmode);
5922 PUT_MODE (operands[2], QFmode);
5923 PUT_MODE (operands[3], QImode);")
5925 (define_insn "*loadhf_float"
5926 [(set (match_operand:HF 0 "reg_operand" "=h")
5927 (float_extend:HF (match_operand:QF 1 "src_operand" "fHm")))]
5928 ""
5929 "ldfu\\t%1,%0"
5930 [(set_attr "type" "unary")])
5932 (define_insn "*loadhf_int"
5933 [(set (match_operand:HF 0 "reg_operand" "+h")
5934 (unspec:HF [(subreg:QI (match_dup 0) 0)
5935 (match_operand:QI 1 "src_operand" "rIm")] 8))]
5936 ""
5937 "ldiu\\t%1,%0"
5938 [(set_attr "type" "unary")])
5940 (define_insn "*storehf_float"
5941 [(set (match_operand:QF 0 "memory_operand" "=m")
5942 (float_truncate:QF (match_operand:HF 1 "reg_operand" "h")))]
5943 ""
5944 "stf\\t%1,%0"
5945 [(set_attr "type" "store")])
5947 (define_insn "*storehf_int"
5948 [(set (match_operand:QI 0 "memory_operand" "=m")
5949 (unspec:QI [(match_operand:HF 1 "reg_operand" "h")] 9))]
5950 ""
5951 "sti\\t%1,%0"
5952 [(set_attr "type" "store")])
5954 (define_insn "extendqfhf2"
5955 [(set (match_operand:HF 0 "reg_operand" "=h")
5956 (float_extend:HF (match_operand:QF 1 "reg_operand" "h")))]
5957 ""
5958 "ldfu\\t%1,%0"
5959 [(set_attr "type" "unarycc")])
5961 (define_insn "trunchfqf2"
5962 [(set (match_operand:QF 0 "reg_operand" "=h")
5963 (float_truncate:QF (match_operand:HF 1 "reg_operand" "0")))
5964 (clobber (reg:CC 21))]
5965 ""
5966 "andn\\t0ffh,%0"
5967 [(set_attr "type" "unarycc")])
5969 ;
5970 ; PUSH/POP
5971 ;
5972 (define_insn "pushhf"
5973 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
5974 (match_operand:HF 0 "reg_operand" "h"))]
5975 ""
5976 "#"
5977 [(set_attr "type" "multi")])
5979 (define_split
5980 [(set (mem:HF (pre_inc:QI (reg:QI 20)))
5981 (match_operand:HF 0 "reg_operand" ""))]
5982 "reload_completed"
5983 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
5984 (float_truncate:QF (match_dup 0)))
5985 (set (mem:QI (pre_inc:QI (reg:QI 20)))
5986 (unspec:QI [(match_dup 0)] 9))]
5987 "")
5989 (define_insn "pushhf_trunc"
5990 [(set (mem:QF (pre_inc:QI (reg:QI 20)))
5991 (float_truncate:QF (match_operand:HF 0 "reg_operand" "h")))]
5992 ""
5993 "pushf\\t%0"
5994 [(set_attr "type" "push")])
5996 (define_insn "pushhf_int"
5997 [(set (mem:QI (pre_inc:QI (reg:QI 20)))
5998 (unspec:QI [(match_operand:HF 0 "reg_operand" "h")] 9))]
5999 ""
6000 "push\\t%0"
6001 [(set_attr "type" "push")])
6003 ; we can not use this because the popf will destroy the low 8 bits
6004 ;(define_insn "pophf"
6005 ; [(set (match_operand:HF 0 "reg_operand" "=h")
6006 ; (mem:HF (post_dec:QI (reg:QI 20))))
6007 ; (clobber (reg:CC 21))]
6008 ; ""
6009 ; "#"
6010 ; [(set_attr "type" "multi")])
6012 (define_split
6013 [(set (match_operand:HF 0 "reg_operand" "")
6014 (mem:HF (post_dec:QI (reg:QI 20))))
6015 (clobber (reg:CC 21))]
6016 "reload_completed"
6017 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
6018 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
6019 (clobber (reg:CC 21))])
6020 (parallel [(set (match_dup 0)
6021 (unspec:HF [(subreg:QI (match_dup 0) 0)
6022 (mem:QI (post_dec:QI (reg:QI 20)))] 8))
6023 (clobber (reg:CC 21))])]
6024 "")
6026 (define_insn "*pophf_int"
6027 [(set (match_operand:HF 0 "reg_operand" "+h")
6028 (unspec:HF [(subreg:QI (match_dup 0) 0)
6029 (mem:QI (post_dec:QI (reg:QI 20)))] 8))
6030 (clobber (reg:CC 21))]
6031 ""
6032 "pop\\t%0"
6033 [(set_attr "type" "pop")])
6035 (define_insn "*pophf_float"
6036 [(set (match_operand:HF 0 "reg_operand" "=h")
6037 (float_extend:HF (mem:QF (post_dec:QI (reg:QI 20)))))
6038 (clobber (reg:CC 21))]
6039 ""
6040 "popf\\t%0"
6041 [(set_attr "type" "pop")])
6043 ;
6044 ; FIX
6045 ;
6046 (define_insn "fixhfqi_clobber"
6047 [(set (match_operand:QI 0 "reg_operand" "=dc")
6048 (fix:QI (match_operand:HF 1 "reg_or_const_operand" "hH")))
6049 (clobber (reg:CC 21))]
6050 ""
6051 "fix\\t%1,%0"
6052 [(set_attr "type" "unarycc")])
6054 ;
6055 ; ABSF
6056 ;
6057 (define_expand "abshf2"
6058 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6059 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "")))
6060 (clobber (reg:CC_NOOV 21))])]
6061 ""
6062 "")
6064 (define_insn "*abshf2_clobber"
6065 [(set (match_operand:HF 0 "reg_operand" "=h")
6066 (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
6067 (clobber (reg:CC_NOOV 21))]
6068 ""
6069 "absf\\t%1,%0"
6070 [(set_attr "type" "unarycc")])
6072 (define_insn "*abshf2_test"
6073 [(set (reg:CC_NOOV 21)
6074 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_operand" "h"))
6075 (match_operand:HF 2 "fp_zero_operand" "G")))
6076 (clobber (match_scratch:HF 0 "=h"))]
6077 ""
6078 "absf\\t%1,%0"
6079 [(set_attr "type" "unarycc")])
6081 (define_insn "*abshf2_set"
6082 [(set (reg:CC_NOOV 21)
6083 (compare:CC_NOOV (abs:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6084 (match_operand:HF 2 "fp_zero_operand" "G")))
6085 (set (match_operand:HF 0 "reg_operand" "=h")
6086 (abs:HF (match_dup 1)))]
6088 ""
6089 "absf\\t%1,%0"
6090 [(set_attr "type" "unarycc")])
6092 ;
6093 ; NEGF
6094 ;
6095 (define_expand "neghf2"
6096 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6097 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "")))
6098 (clobber (reg:CC_NOOV 21))])]
6099 ""
6100 "")
6102 (define_insn "*neghf2_clobber"
6103 [(set (match_operand:HF 0 "reg_operand" "=h")
6104 (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH")))
6105 (clobber (reg:CC_NOOV 21))]
6106 ""
6107 "negf\\t%1,%0"
6108 [(set_attr "type" "unarycc")])
6110 (define_insn "*neghf2_test"
6111 [(set (reg:CC_NOOV 21)
6112 (compare:CC_NOOV (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6113 (match_operand:HF 2 "fp_zero_operand" "G")))
6114 (clobber (match_scratch:HF 0 "=h"))]
6115 ""
6116 "negf\\t%1,%0"
6117 [(set_attr "type" "unarycc")])
6119 (define_insn "*neghf2_set"
6120 [(set (reg:CC_NOOV 21)
6121 (compare:CC_NOOV (neg:HF (match_operand:HF 1 "reg_or_const_operand" "hH"))
6122 (match_operand:HF 2 "fp_zero_operand" "G")))
6123 (set (match_operand:HF 0 "reg_operand" "=h")
6124 (neg:HF (match_dup 1)))]
6125 ""
6126 "negf\\t%1,%0"
6127 [(set_attr "type" "unarycc")])
6129 ;
6130 ; RCPF
6131 ;
6132 (define_insn "*rcpfhf_clobber"
6133 [(set (match_operand:HF 0 "reg_operand" "=h")
6134 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] 5))
6135 (clobber (reg:CC_NOOV 21))]
6136 "! TARGET_C3X"
6137 "rcpf\\t%1,%0"
6138 [(set_attr "type" "unarycc")])
6140 ;
6141 ; RSQRF
6142 ;
6143 (define_insn "*rsqrfhf_clobber"
6144 [(set (match_operand:HF 0 "reg_operand" "=h")
6145 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] 10))
6146 (clobber (reg:CC_NOOV 21))]
6147 "! TARGET_C3X"
6148 "rsqrf\\t%1,%0"
6149 [(set_attr "type" "unarycc")])
6151 ;
6152 ; RNDF
6153 ;
6154 (define_insn "*rndhf_clobber"
6155 [(set (match_operand:HF 0 "reg_operand" "=h")
6156 (unspec:HF [(match_operand:HF 1 "reg_or_const_operand" "hH")] 6))
6157 (clobber (reg:CC_NOOV 21))]
6158 "! TARGET_C3X"
6159 "rnd\\t%1,%0"
6160 [(set_attr "type" "unarycc")])
6163 ; Inlined float square root for C4x
6164 (define_expand "sqrthf2_inline"
6165 [(parallel [(set (match_dup 2)
6166 (unspec:HF [(match_operand:HF 1 "reg_operand" "")] 10))
6167 (clobber (reg:CC_NOOV 21))])
6168 (parallel [(set (match_dup 3) (mult:HF (match_dup 5) (match_dup 1)))
6169 (clobber (reg:CC_NOOV 21))])
6170 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6171 (clobber (reg:CC_NOOV 21))])
6172 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
6173 (clobber (reg:CC_NOOV 21))])
6174 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
6175 (clobber (reg:CC_NOOV 21))])
6176 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
6177 (clobber (reg:CC_NOOV 21))])
6178 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6179 (clobber (reg:CC_NOOV 21))])
6180 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 4)))
6181 (clobber (reg:CC_NOOV 21))])
6182 (parallel [(set (match_dup 4) (minus:HF (match_dup 6) (match_dup 4)))
6183 (clobber (reg:CC_NOOV 21))])
6184 (parallel [(set (match_dup 2) (mult:HF (match_dup 2) (match_dup 4)))
6185 (clobber (reg:CC_NOOV 21))])
6186 (parallel [(set (match_operand:HF 0 "reg_operand" "")
6187 (mult:HF (match_dup 2) (match_dup 1)))
6188 (clobber (reg:CC_NOOV 21))])]
6189 "! TARGET_C3X"
6190 "
6191 operands[2] = gen_reg_rtx (HFmode);
6192 operands[3] = gen_reg_rtx (HFmode);
6193 operands[4] = gen_reg_rtx (HFmode);
6194 operands[5] = CONST_DOUBLE_ATOF (\"0.5\", HFmode);
6195 operands[6] = CONST_DOUBLE_ATOF (\"1.5\", HFmode);
6196 ")
6199 (define_expand "sqrthf2"
6200 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6201 (sqrt:HF (match_operand:HF 1 "reg_operand" "")))
6202 (clobber (reg:CC 21))])]
6203 "! TARGET_C3X && TARGET_INLINE"
6204 "emit_insn (gen_sqrthf2_inline (operands[0], operands[1]));
6205 DONE;")
6208 (define_expand "fix_trunchfhi2"
6209 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6210 (fix:HI (match_operand:HF 1 "reg_operand" "")))
6211 (clobber (reg:CC 21))])]
6212 ""
6213 "c4x_emit_libcall (fix_trunchfhi2_libfunc, FIX, HImode, HFmode, 2, operands);
6214 DONE;")
6216 (define_expand "fixuns_trunchfhi2"
6217 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6218 (unsigned_fix:HI (match_operand:HF 1 "reg_operand" "")))
6219 (clobber (reg:CC 21))])]
6220 ""
6221 "c4x_emit_libcall (fixuns_trunchfhi2_libfunc, UNSIGNED_FIX,
6222 HImode, HFmode, 2, operands);
6223 DONE;")
6225 ;
6226 ; THREE OPERAND LONG DOUBLE INSTRUCTIONS
6227 ;
6229 ;
6230 ; ADDF
6231 ;
6232 (define_insn "addhf3"
6233 [(set (match_operand:HF 0 "reg_operand" "=h,?h")
6234 (plus:HF (match_operand:HF 1 "reg_operand" "%0,h")
6235 (match_operand:HF 2 "reg_or_const_operand" "H,h")))
6236 (clobber (reg:CC_NOOV 21))]
6237 ""
6238 "@
6239 addf\\t%2,%0
6240 addf3\\t%2,%1,%0"
6241 [(set_attr "type" "binarycc,binarycc")])
6243 ;
6244 ; SUBF
6245 ;
6246 (define_insn "subhf3"
6247 [(set (match_operand:HF 0 "reg_operand" "=h,h,?h")
6248 (minus:HF (match_operand:HF 1 "reg_or_const_operand" "0,H,h")
6249 (match_operand:HF 2 "reg_or_const_operand" "H,0,h")))
6250 (clobber (reg:CC_NOOV 21))]
6251 ""
6252 "@
6253 subf\\t%2,%0
6254 subrf\\t%1,%0
6255 subf3\\t%2,%1,%0"
6256 [(set_attr "type" "binarycc,binarycc,binarycc")])
6258 ;
6259 ; MULF
6260 ;
6261 ; The C3x MPYF only uses 24 bit precision while the C4x uses 32 bit precison.
6262 ;
6263 (define_expand "mulhf3"
6264 [(parallel [(set (match_operand:HF 0 "reg_operand" "=h")
6265 (mult:HF (match_operand:HF 1 "reg_operand" "h")
6266 (match_operand:HF 2 "reg_operand" "h")))
6267 (clobber (reg:CC_NOOV 21))])]
6268 "! TARGET_C3X"
6269 "")
6271 (define_insn "*mulhf3_c40"
6272 [(set (match_operand:HF 0 "reg_operand" "=h,?h")
6273 (mult:HF (match_operand:HF 1 "reg_operand" "%0,h")
6274 (match_operand:HF 2 "reg_or_const_operand" "hH,h")))
6275 (clobber (reg:CC_NOOV 21))]
6276 ""
6277 "@
6278 mpyf\\t%2,%0
6279 mpyf3\\t%2,%1,%0"
6280 [(set_attr "type" "binarycc,binarycc")])
6282 ;
6283 ; CMPF
6284 ;
6285 (define_expand "cmphf"
6286 [(set (reg:CC 21)
6287 (compare:CC (match_operand:HF 0 "reg_operand" "")
6288 (match_operand:HF 1 "reg_or_const_operand" "")))]
6289 ""
6290 "c4x_compare_op0 = operands[0];
6291 c4x_compare_op1 = operands[1];
6292 DONE;")
6294 (define_insn "*cmphf"
6295 [(set (reg:CC 21)
6296 (compare:CC (match_operand:HF 0 "reg_operand" "h")
6297 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
6298 ""
6299 "cmpf\\t%1,%0"
6300 [(set_attr "type" "compare")])
6302 (define_insn "*cmphf_noov"
6303 [(set (reg:CC_NOOV 21)
6304 (compare:CC_NOOV (match_operand:HF 0 "reg_operand" "h")
6305 (match_operand:HF 1 "reg_or_const_operand" "hH")))]
6306 ""
6307 "cmpf\\t%1,%0"
6308 [(set_attr "type" "compare")])
6310 ; Inlined float divide for C4x
6311 (define_expand "divhf3_inline"
6312 [(parallel [(set (match_dup 3)
6313 (unspec:HF [(match_operand:HF 2 "reg_operand" "")] 5))
6314 (clobber (reg:CC_NOOV 21))])
6315 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6316 (clobber (reg:CC_NOOV 21))])
6317 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
6318 (clobber (reg:CC_NOOV 21))])
6319 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
6320 (clobber (reg:CC_NOOV 21))])
6321 (parallel [(set (match_dup 4) (mult:HF (match_dup 2) (match_dup 3)))
6322 (clobber (reg:CC_NOOV 21))])
6323 (parallel [(set (match_dup 4) (minus:HF (match_dup 5) (match_dup 4)))
6324 (clobber (reg:CC_NOOV 21))])
6325 (parallel [(set (match_dup 3) (mult:HF (match_dup 3) (match_dup 4)))
6326 (clobber (reg:CC_NOOV 21))])
6327 (parallel [(set (match_operand:HF 0 "reg_operand" "")
6328 (mult:HF (match_operand:HF 1 "reg_operand" "")
6329 (match_dup 3)))
6330 (clobber (reg:CC_NOOV 21))])]
6331 "! TARGET_C3X"
6332 "
6333 operands[3] = gen_reg_rtx (HFmode);
6334 operands[4] = gen_reg_rtx (HFmode);
6335 operands[5] = CONST2_RTX (HFmode);
6336 ")
6338 (define_expand "divhf3"
6339 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6340 (div:HF (match_operand:HF 1 "reg_operand" "")
6341 (match_operand:HF 2 "reg_operand" "")))
6342 (clobber (reg:CC 21))])]
6343 "! TARGET_C3X && TARGET_INLINE"
6344 "emit_insn (gen_divhf3_inline (operands[0], operands[1], operands[2]));
6345 DONE;")
6348 ;
6349 ; TWO OPERAND LONG LONG INSTRUCTIONS
6350 ;
6352 (define_insn "*movhi_stik"
6353 [(set (match_operand:HI 0 "memory_operand" "=m")
6354 (match_operand:HI 1 "stik_const_operand" "K"))]
6355 "! TARGET_C3X"
6356 "#"
6357 [(set_attr "type" "multi")])
6359 ; We could load some constants using define_splits for the C30
6360 ; in the large memory model---these would emit shift and or insns.
6361 (define_expand "movhi"
6362 [(set (match_operand:HI 0 "src_operand" "")
6363 (match_operand:HI 1 "src_operand" ""))]
6364 ""
6365 "if (c4x_emit_move_sequence (operands, HImode))
6366 DONE;")
6368 ; The constraints for movhi must include 'r' if we don't
6369 ; restrict HImode regnos to start on an even number, since
6370 ; we can get RC, R8 allocated as a pair. We want more
6371 ; votes for FP_REGS so we use dr as the constraints.
6372 (define_insn "*movhi_noclobber"
6373 [(set (match_operand:HI 0 "dst_operand" "=dr,m")
6374 (match_operand:HI 1 "src_operand" "drIm,r"))]
6375 "reg_operand (operands[0], HImode)
6376 || reg_operand (operands[1], HImode)"
6377 "#"
6378 [(set_attr "type" "multi,multi")])
6380 ; This will fail miserably if the destination register is used in the
6381 ; source memory address.
6382 ; The usual strategy in this case is to swap the order of insns we emit,
6383 ; however, this will fail if we have an autoincrement memory address.
6384 ; For example:
6385 ; ldi *ar0++, ar0
6386 ; ldi *ar0++, ar1
6387 ;
6388 ; We could convert this to
6389 ; ldi *ar0(1), ar1
6390 ; ldi *ar0, ar0
6391 ;
6392 ; However, things are likely to be very screwed up if we get this.
6394 (define_split
6395 [(set (match_operand:HI 0 "dst_operand" "")
6396 (match_operand:HI 1 "src_operand" ""))]
6397 "reload_completed
6398 && (reg_operand (operands[0], HImode)
6399 || reg_operand (operands[1], HImode)
6400 || stik_const_operand (operands[1], HImode))"
6401 [(set (match_dup 2) (match_dup 4))
6402 (set (match_dup 3) (match_dup 5))]
6403 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6404 operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
6405 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6406 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
6407 if (reg_overlap_mentioned_p (operands[2], operands[5]))
6408 {
6409 /* Swap order of move insns. */
6410 rtx tmp;
6411 tmp = operands[2];
6412 operands[2] =operands[3];
6413 operands[3] = tmp;
6414 tmp = operands[4];
6415 operands[4] =operands[5];
6416 operands[5] = tmp;
6417 }")
6420 (define_insn "extendqihi2"
6421 [(set (match_operand:HI 0 "reg_operand" "=dc")
6422 (sign_extend:HI (match_operand:QI 1 "src_operand" "rIm")))
6423 (clobber (reg:CC 21))]
6424 ""
6425 "#"
6426 [(set_attr "type" "multi")])
6428 (define_split
6429 [(set (match_operand:HI 0 "reg_operand" "")
6430 (sign_extend:HI (match_operand:QI 1 "src_operand" "")))
6431 (clobber (reg:CC 21))]
6432 "reload_completed && TARGET_C3X"
6433 [(set (match_dup 2) (match_dup 1))
6434 (set (match_dup 3) (match_dup 2))
6435 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 3) (const_int 31)))
6436 (clobber (reg:CC 21))])]
6437 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6438 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6440 (define_split
6441 [(set (match_operand:HI 0 "reg_operand" "")
6442 (sign_extend:HI (match_operand:QI 1 "src_operand" "")))
6443 (clobber (reg:CC 21))]
6444 "reload_completed && ! TARGET_C3X"
6445 [(set (match_dup 2) (match_dup 1))
6446 (parallel [(set (match_dup 3) (ashiftrt:QI (match_dup 2) (const_int 31)))
6447 (clobber (reg:CC 21))])]
6448 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6449 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6451 (define_insn "zero_extendqihi2"
6452 [(set (match_operand:HI 0 "reg_operand" "=?dc")
6453 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "rm")))
6454 (clobber (reg:CC 21))]
6455 ""
6456 "#"
6457 [(set_attr "type" "multi")])
6459 ; If operand0 and operand1 are the same register we don't need
6460 ; the first set.
6461 (define_split
6462 [(set (match_operand:HI 0 "reg_operand" "")
6463 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))
6464 (clobber (reg:CC 21))]
6465 "reload_completed"
6466 [(set (match_dup 2) (match_dup 1))
6467 (set (match_dup 3) (const_int 0))]
6468 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6469 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6471 ;
6472 ; PUSH/POP
6473 ;
6474 (define_insn "*pushhi"
6475 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
6476 (match_operand:HI 0 "reg_operand" "r"))]
6477 ""
6478 "#"
6479 [(set_attr "type" "multi")])
6481 (define_split
6482 [(set (mem:HI (pre_inc:QI (reg:QI 20)))
6483 (match_operand:HI 0 "reg_operand" ""))]
6484 "reload_completed"
6485 [(set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 2))
6486 (set (mem:QI (pre_inc:QI (reg:QI 20))) (match_dup 3))]
6487 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6488 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6490 (define_insn "*pophi"
6491 [(set (match_operand:HI 0 "reg_operand" "=r")
6492 (mem:HI (post_dec:QI (reg:QI 20))))
6493 (clobber (reg:CC 21))]
6494 ""
6495 "#"
6496 [(set_attr "type" "multi")])
6498 (define_split
6499 [(set (match_operand:HI 0 "reg_operand" "")
6500 (mem:HI (pre_inc:QI (reg:QI 20))))]
6501 "reload_completed"
6502 [(set (match_dup 2) (mem:QI (pre_inc:QI (reg:QI 20))))
6503 (set (match_dup 3) (mem:QI (pre_inc:QI (reg:QI 20))))]
6504 "operands[2] = c4x_operand_subword (operands[0], 0, 0, HImode);
6505 operands[3] = c4x_operand_subword (operands[0], 1, 0, HImode);")
6507 ;
6508 ; NEG
6509 ;
6510 (define_insn "neghi2"
6511 [(set (match_operand:HI 0 "ext_reg_operand" "=d")
6512 (neg:HI (match_operand:HI 1 "src_operand" "rm")))
6513 (clobber (reg:CC_NOOV 21))]
6514 ""
6515 "#"
6516 [(set_attr "type" "multi")])
6518 (define_split
6519 [(set (match_operand:HI 0 "ext_reg_operand" "")
6520 (neg:HI (match_operand:HI 1 "src_operand" "")))
6521 (clobber (reg:CC_NOOV 21))]
6522 "reload_completed"
6523 [(parallel [(set (reg:CC_NOOV 21)
6524 (compare:CC_NOOV (neg:QI (match_dup 3))
6525 (const_int 0)))
6526 (set (match_dup 2) (neg:QI (match_dup 3)))])
6527 (parallel [(set (match_dup 4) (neg:QI (match_dup 5)))
6528 (use (reg:CC_NOOV 21))
6529 (clobber (reg:CC_NOOV 21))])]
6530 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6531 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
6532 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
6533 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
6535 (define_insn "one_cmplhi2"
6536 [(set (match_operand:HI 0 "reg_operand" "=r")
6537 (not:HI (match_operand:HI 1 "src_operand" "rm")))
6538 (clobber (reg:CC 21))]
6539 ""
6540 "#"
6541 [(set_attr "type" "multi")])
6543 (define_split
6544 [(set (match_operand:HI 0 "reg_operand" "")
6545 (not:HI (match_operand:HI 1 "src_operand" "")))
6546 (clobber (reg:CC 21))]
6547 "reload_completed"
6548 [(parallel [(set (match_dup 2) (not:QI (match_dup 3)))
6549 (clobber (reg:CC 21))])
6550 (parallel [(set (match_dup 4) (not:QI (match_dup 5)))
6551 (clobber (reg:CC 21))])]
6552 "operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
6553 operands[3] = c4x_operand_subword (operands[1], 0, 1, HImode);
6554 operands[4] = c4x_operand_subword (operands[0], 1, 1, HImode);
6555 operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);")
6557 (define_expand "floathiqf2"
6558 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
6559 (float:QF (match_operand:HI 1 "src_operand" "")))
6560 (clobber (reg:CC 21))])]
6561 ""
6562 "c4x_emit_libcall (floathiqf2_libfunc, FLOAT, QFmode, HImode, 2, operands);
6563 DONE;")
6565 (define_expand "floatunshiqf2"
6566 [(parallel [(set (match_operand:QF 0 "reg_operand" "")
6567 (unsigned_float:QF (match_operand:HI 1 "src_operand" "")))
6568 (clobber (reg:CC 21))])]
6569 ""
6570 "c4x_emit_libcall (floatunshiqf2_libfunc, UNSIGNED_FLOAT,
6571 QFmode, HImode, 2, operands);
6572 DONE;")
6574 (define_expand "floathihf2"
6575 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6576 (float:HF (match_operand:HI 1 "src_operand" "")))
6577 (clobber (reg:CC 21))])]
6578 ""
6579 "c4x_emit_libcall (floathihf2_libfunc, FLOAT, HFmode, HImode, 2, operands);
6580 DONE;")
6582 (define_expand "floatunshihf2"
6583 [(parallel [(set (match_operand:HF 0 "reg_operand" "")
6584 (unsigned_float:HF (match_operand:HI 1 "src_operand" "")))
6585 (clobber (reg:CC 21))])]
6586 ""
6587 "c4x_emit_libcall (floatunshihf2_libfunc, UNSIGNED_FLOAT,
6588 HFmode, HImode, 2, operands);
6589 DONE;")
6592 ;
6593 ; THREE OPERAND LONG LONG INSTRUCTIONS
6594 ;
6596 (define_expand "addhi3"
6597 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
6598 (plus:HI (match_operand:HI 1 "src_operand" "")
6599 (match_operand:HI 2 "src_operand" "")))
6600 (clobber (reg:CC_NOOV 21))])]
6601 ""
6602 "legitimize_operands (PLUS, operands, HImode);")
6604 (define_insn "*addhi3_clobber"
6605 [(set (match_operand:HI 0 "ext_reg_operand" "=d,d,?d")
6606 (plus:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6607 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6608 (clobber (reg:CC_NOOV 21))]
6609 "valid_operands (PLUS, operands, HImode)"
6610 "#"
6611 [(set_attr "type" "multi,multi,multi")])
6613 (define_split
6614 [(set (match_operand:HI 0 "ext_reg_operand" "")
6615 (plus:HI (match_operand:HI 1 "src_operand" "")
6616 (match_operand:HI 2 "src_operand" "")))
6617 (clobber (reg:CC_NOOV 21))]
6618 "reload_completed"
6619 [(parallel [(set (reg:CC_NOOV 21)
6620 (compare:CC_NOOV (plus:QI (match_dup 4) (match_dup 5))
6621 (const_int 0)))
6622 (set (match_dup 3) (plus:QI (match_dup 4) (match_dup 5)))])
6623 (parallel [(set (match_dup 6) (plus:QI (match_dup 7) (match_dup 8)))
6624 (use (reg:CC_NOOV 21))
6625 (clobber (reg:CC_NOOV 21))])]
6626 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6627 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6628 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6629 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6630 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6631 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6633 (define_expand "subhi3"
6634 [(parallel [(set (match_operand:HI 0 "ext_reg_operand" "")
6635 (minus:HI (match_operand:HI 1 "src_operand" "")
6636 (match_operand:HI 2 "src_operand" "")))
6637 (clobber (reg:CC_NOOV 21))])]
6638 ""
6639 "legitimize_operands (MINUS, operands, HImode);")
6642 (define_insn "*subhi3_clobber"
6643 [(set (match_operand:HI 0 "ext_reg_operand" "=d,d,?d")
6644 (minus:HI (match_operand:HI 1 "src_operand" "0,rR,rS<>")
6645 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6646 (clobber (reg:CC_NOOV 21))]
6647 "valid_operands (MINUS, operands, HImode)"
6648 "#"
6649 [(set_attr "type" "multi,multi,multi")])
6651 (define_split
6652 [(set (match_operand:HI 0 "ext_reg_operand" "")
6653 (minus:HI (match_operand:HI 1 "src_operand" "")
6654 (match_operand:HI 2 "src_operand" "")))
6655 (clobber (reg:CC_NOOV 21))]
6656 "reload_completed"
6657 [(parallel [(set (reg:CC_NOOV 21)
6658 (compare:CC_NOOV (minus:QI (match_dup 4) (match_dup 5))
6659 (const_int 0)))
6660 (set (match_dup 3) (minus:QI (match_dup 4) (match_dup 5)))])
6661 (parallel [(set (match_dup 6) (minus:QI (match_dup 7) (match_dup 8)))
6662 (use (reg:CC_NOOV 21))
6663 (clobber (reg:CC_NOOV 21))])]
6664 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6665 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6666 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6667 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6668 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6669 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6671 (define_expand "iorhi3"
6672 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6673 (ior:HI (match_operand:HI 1 "src_operand" "")
6674 (match_operand:HI 2 "src_operand" "")))
6675 (clobber (reg:CC 21))])]
6676 ""
6677 "legitimize_operands (IOR, operands, HImode);")
6679 (define_insn "*iorhi3_clobber"
6680 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6681 (ior:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6682 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6683 (clobber (reg:CC 21))]
6684 "valid_operands (IOR, operands, HImode)"
6685 "#"
6686 [(set_attr "type" "multi,multi,multi")])
6688 (define_split
6689 [(set (match_operand:HI 0 "reg_operand" "")
6690 (ior:HI (match_operand:HI 1 "src_operand" "")
6691 (match_operand:HI 2 "src_operand" "")))
6692 (clobber (reg:CC 21))]
6693 "reload_completed"
6694 [(parallel [(set (match_dup 3) (ior:QI (match_dup 4) (match_dup 5)))
6695 (clobber (reg:CC 21))])
6696 (parallel [(set (match_dup 6) (ior:QI (match_dup 7) (match_dup 8)))
6697 (clobber (reg:CC 21))])]
6698 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6699 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6700 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6701 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6702 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6703 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6705 (define_expand "andhi3"
6706 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6707 (and:HI (match_operand:HI 1 "src_operand" "")
6708 (match_operand:HI 2 "src_operand" "")))
6709 (clobber (reg:CC 21))])]
6710 ""
6711 "legitimize_operands (AND, operands, HImode);")
6713 (define_insn "*andhi3_clobber"
6714 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6715 (and:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6716 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6717 (clobber (reg:CC 21))]
6718 "valid_operands (AND, operands, HImode)"
6719 "#"
6720 [(set_attr "type" "multi,multi,multi")])
6722 (define_split
6723 [(set (match_operand:HI 0 "reg_operand" "")
6724 (and:HI (match_operand:HI 1 "src_operand" "")
6725 (match_operand:HI 2 "src_operand" "")))
6726 (clobber (reg:CC 21))]
6727 "reload_completed"
6728 [(parallel [(set (match_dup 3) (and:QI (match_dup 4) (match_dup 5)))
6729 (clobber (reg:CC 21))])
6730 (parallel [(set (match_dup 6) (and:QI (match_dup 7) (match_dup 8)))
6731 (clobber (reg:CC 21))])]
6732 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6733 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6734 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6735 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6736 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6737 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6739 (define_expand "xorhi3"
6740 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6741 (xor:HI (match_operand:HI 1 "src_operand" "")
6742 (match_operand:HI 2 "src_operand" "")))
6743 (clobber (reg:CC 21))])]
6744 ""
6745 "legitimize_operands (XOR, operands, HImode);")
6748 (define_insn "*xorhi3_clobber"
6749 [(set (match_operand:HI 0 "reg_operand" "=d,d,?d")
6750 (xor:HI (match_operand:HI 1 "src_operand" "%0,rR,rS<>")
6751 (match_operand:HI 2 "src_operand" "rm,R,rS<>")))
6752 (clobber (reg:CC 21))]
6753 "valid_operands (XOR, operands, HImode)"
6754 "#"
6755 [(set_attr "type" "multi,multi,multi")])
6757 (define_split
6758 [(set (match_operand:HI 0 "reg_operand" "")
6759 (xor:HI (match_operand:HI 1 "src_operand" "")
6760 (match_operand:HI 2 "src_operand" "")))
6761 (clobber (reg:CC 21))]
6762 "reload_completed"
6763 [(parallel [(set (match_dup 3) (xor:QI (match_dup 4) (match_dup 5)))
6764 (clobber (reg:CC 21))])
6765 (parallel [(set (match_dup 6) (xor:QI (match_dup 7) (match_dup 8)))
6766 (clobber (reg:CC 21))])]
6767 "operands[3] = c4x_operand_subword (operands[0], 0, 1, HImode);
6768 operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
6769 operands[5] = c4x_operand_subword (operands[2], 0, 1, HImode);
6770 operands[6] = c4x_operand_subword (operands[0], 1, 1, HImode);
6771 operands[7] = c4x_operand_subword (operands[1], 1, 1, HImode);
6772 operands[8] = c4x_operand_subword (operands[2], 1, 1, HImode);")
6774 (define_expand "ashlhi3"
6775 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6776 (ashift:HI (match_operand:HI 1 "src_operand" "")
6777 (match_operand:QI 2 "src_operand" "")))
6778 (clobber (reg:CC 21))])]
6779 ""
6780 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6781 {
6782 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6783 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6784 rtx op1lo = operand_subword (operands[1], 0, 0, HImode);
6785 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6787 if (INTVAL (count))
6788 emit_insn (gen_ashlqi3 (op0hi, op1lo, count));
6789 else
6790 emit_insn (gen_movqi (op0hi, op1lo));
6791 emit_insn (gen_movqi (op0lo, const0_rtx));
6792 DONE;
6793 }
6794 if (! REG_P (operands[1]))
6795 operands[1] = force_reg (HImode, operands[1]);
6796 emit_insn (gen_ashlhi3_reg (operands[0], operands[1], operands[2]));
6797 DONE;
6798 ")
6800 ; %0.lo = %1.lo << %2
6801 ; %0.hi = (%1.hi << %2 ) | (%1.lo >> (32 - %2))
6802 ; This algorithm should work for shift counts greater than 32
6803 (define_expand "ashlhi3_reg"
6804 [(use (match_operand:HI 1 "reg_operand" ""))
6805 (use (match_operand:HI 0 "reg_operand" ""))
6806 /* If the shift count is greater than 32 this will give zero. */
6807 (parallel [(set (match_dup 7)
6808 (ashift:QI (match_dup 3)
6809 (match_operand:QI 2 "reg_operand" "")))
6810 (clobber (reg:CC 21))])
6811 /* If the shift count is greater than 32 this will give zero. */
6812 (parallel [(set (match_dup 8)
6813 (ashift:QI (match_dup 4) (match_dup 2)))
6814 (clobber (reg:CC 21))])
6815 (parallel [(set (match_dup 10)
6816 (plus:QI (match_dup 2) (const_int -32)))
6817 (clobber (reg:CC_NOOV 21))])
6818 /* If the shift count is greater than 32 this will do a left shift. */
6819 (parallel [(set (match_dup 9)
6820 (lshiftrt:QI (match_dup 3) (neg:QI (match_dup 10))))
6821 (clobber (reg:CC 21))])
6822 (set (match_dup 5) (match_dup 7))
6823 (parallel [(set (match_dup 6)
6824 (ior:QI (match_dup 8) (match_dup 9)))
6825 (clobber (reg:CC 21))])]
6826 ""
6827 "
6828 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6829 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6830 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6831 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6832 operands[7] = gen_reg_rtx (QImode); /* lo << count */
6833 operands[8] = gen_reg_rtx (QImode); /* hi << count */
6834 operands[9] = gen_reg_rtx (QImode); /* lo >> (32 - count) */
6835 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6836 ")
6838 ; This should do all the dirty work with define_split
6839 (define_expand "lshrhi3"
6840 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6841 (lshiftrt:HI (match_operand:HI 1 "src_operand" "")
6842 (match_operand:QI 2 "src_operand" "")))
6843 (clobber (reg:CC 21))])]
6844 ""
6845 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6846 {
6847 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6848 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6849 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
6850 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6852 if (INTVAL (count))
6853 emit_insn (gen_lshrqi3 (op0lo, op1hi, count));
6854 else
6855 emit_insn (gen_movqi (op0lo, op1hi));
6856 emit_insn (gen_movqi (op0hi, const0_rtx));
6857 DONE;
6858 }
6859 if (! REG_P (operands[1]))
6860 operands[1] = force_reg (HImode, operands[1]);
6861 emit_insn (gen_lshrhi3_reg (operands[0], operands[1], operands[2]));
6862 DONE;")
6864 ; %0.hi = %1.hi >> %2
6865 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
6866 ; This algorithm should work for shift counts greater than 32
6867 (define_expand "lshrhi3_reg"
6868 [(use (match_operand:HI 1 "reg_operand" ""))
6869 (use (match_operand:HI 0 "reg_operand" ""))
6870 (parallel [(set (match_dup 11)
6871 (neg:QI (match_operand:QI 2 "reg_operand" "")))
6872 (clobber (reg:CC_NOOV 21))])
6873 /* If the shift count is greater than 32 this will give zero. */
6874 (parallel [(set (match_dup 7)
6875 (lshiftrt:QI (match_dup 3)
6876 (neg:QI (match_dup 11))))
6877 (clobber (reg:CC 21))])
6878 /* If the shift count is greater than 32 this will give zero. */
6879 (parallel [(set (match_dup 8)
6880 (lshiftrt:QI (match_dup 4)
6881 (neg:QI (match_dup 11))))
6882 (clobber (reg:CC 21))])
6883 (parallel [(set (match_dup 10)
6884 (plus:QI (match_dup 11) (const_int 32)))
6885 (clobber (reg:CC_NOOV 21))])
6886 /* If the shift count is greater than 32 this will do an arithmetic
6887 right shift. However, we need a logical right shift. */
6888 (parallel [(set (match_dup 9)
6889 (ashift:QI (match_dup 4) (unspec:QI [(match_dup 10)] 3)))
6890 (clobber (reg:CC 21))])
6891 (set (match_dup 6) (match_dup 8))
6892 (parallel [(set (match_dup 5)
6893 (ior:QI (match_dup 7) (match_dup 9)))
6894 (clobber (reg:CC 21))])]
6895 ""
6896 "
6897 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6898 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6899 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6900 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6901 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
6902 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
6903 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
6904 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6905 operands[11] = gen_reg_rtx (QImode); /* -count */
6906 ")
6908 ; This should do all the dirty work with define_split
6909 (define_expand "ashrhi3"
6910 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
6911 (ashiftrt:HI (match_operand:HI 1 "src_operand" "")
6912 (match_operand:QI 2 "src_operand" "")))
6913 (clobber (reg:CC 21))])]
6914 ""
6915 "if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32)
6916 {
6917 rtx op0hi = operand_subword (operands[0], 1, 0, HImode);
6918 rtx op0lo = operand_subword (operands[0], 0, 0, HImode);
6919 rtx op1hi = operand_subword (operands[1], 1, 0, HImode);
6920 rtx count = GEN_INT ((INTVAL (operands[2]) - 32));
6922 if (INTVAL (count))
6923 emit_insn (gen_ashrqi3 (op0lo, op1hi, count));
6924 else
6925 emit_insn (gen_movqi (op0lo, op1hi));
6926 emit_insn (gen_ashrqi3 (op0hi, op1hi, GEN_INT (31)));
6927 DONE;
6928 }
6929 if (! REG_P (operands[1]))
6930 operands[1] = force_reg (HImode, operands[1]);
6931 emit_insn (gen_ashrhi3_reg (operands[0], operands[1], operands[2]));
6932 DONE;")
6934 ; %0.hi = %1.hi >> %2
6935 ; %0.lo = (%1.lo >> %2 ) | (%1.hi << (32 - %2))
6936 ; This algorithm should work for shift counts greater than 32
6937 (define_expand "ashrhi3_reg"
6938 [(use (match_operand:HI 1 "reg_operand" ""))
6939 (use (match_operand:HI 0 "reg_operand" ""))
6940 (parallel [(set (match_dup 11)
6941 (neg:QI (match_operand:QI 2 "reg_operand" "")))
6942 (clobber (reg:CC_NOOV 21))])
6943 /* If the shift count is greater than 32 this will give zero. */
6944 (parallel [(set (match_dup 7)
6945 (lshiftrt:QI (match_dup 3)
6946 (neg:QI (match_dup 11))))
6947 (clobber (reg:CC 21))])
6948 /* If the shift count is greater than 32 this will give zero. */
6949 (parallel [(set (match_dup 8)
6950 (ashiftrt:QI (match_dup 4)
6951 (neg:QI (match_dup 11))))
6952 (clobber (reg:CC 21))])
6953 (parallel [(set (match_dup 10)
6954 (plus:QI (match_dup 11) (const_int 32)))
6955 (clobber (reg:CC_NOOV 21))])
6956 /* If the shift count is greater than 32 this will do an arithmetic
6957 right shift. */
6958 (parallel [(set (match_dup 9)
6959 (ashift:QI (match_dup 4) (match_dup 10)))
6960 (clobber (reg:CC 21))])
6961 (set (match_dup 6) (match_dup 8))
6962 (parallel [(set (match_dup 5)
6963 (ior:QI (match_dup 7) (match_dup 9)))
6964 (clobber (reg:CC 21))])]
6965 ""
6966 "
6967 operands[3] = operand_subword (operands[1], 0, 1, HImode); /* lo */
6968 operands[4] = operand_subword (operands[1], 1, 1, HImode); /* hi */
6969 operands[5] = operand_subword (operands[0], 0, 1, HImode); /* lo */
6970 operands[6] = operand_subword (operands[0], 1, 1, HImode); /* hi */
6971 operands[7] = gen_reg_rtx (QImode); /* lo >> count */
6972 operands[8] = gen_reg_rtx (QImode); /* hi >> count */
6973 operands[9] = gen_reg_rtx (QImode); /* hi << (32 - count) */
6974 operands[10] = gen_reg_rtx (QImode); /* 32 - count */
6975 operands[11] = gen_reg_rtx (QImode); /* -count */
6976 ")
6978 (define_expand "cmphi"
6979 [(set (reg:CC 21)
6980 (compare:CC (match_operand:HI 0 "src_operand" "")
6981 (match_operand:HI 1 "src_operand" "")))]
6982 ""
6983 "legitimize_operands (COMPARE, operands, HImode);
6984 c4x_compare_op0 = operands[0];
6985 c4x_compare_op1 = operands[1];
6986 DONE;")
6988 (define_insn "*cmphi_cc"
6989 [(set (reg:CC 21)
6990 (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
6991 (match_operand:HI 1 "src_operand" "R,rS<>")))]
6992 "valid_operands (COMPARE, operands, HImode)"
6993 "#"
6994 [(set_attr "type" "multi")])
6996 (define_insn "*cmphi_cc_noov"
6997 [(set (reg:CC_NOOV 21)
6998 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
6999 (match_operand:HI 1 "src_operand" "R,rS<>")))]
7000 "valid_operands (COMPARE, operands, HImode)"
7001 "#"
7002 [(set_attr "type" "multi")])
7004 ; This works only before reload because we need 2 extra registers.
7005 ; Use unspec to avoid recursive split.
7006 (define_split
7007 [(set (reg:CC 21)
7008 (compare:CC (match_operand:HI 0 "src_operand" "")
7009 (match_operand:HI 1 "src_operand" "")))]
7010 "! reload_completed"
7011 [(parallel [(set (reg:CC 21)
7012 (unspec:CC [(compare:CC (match_dup 0)
7013 (match_dup 1))] 4))
7014 (clobber (match_scratch:QI 2 ""))
7015 (clobber (match_scratch:QI 3 ""))])]
7016 "")
7018 (define_split
7019 [(set (reg:CC_NOOV 21)
7020 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
7021 (match_operand:HI 1 "src_operand" "")))]
7022 "! reload_completed"
7023 [(parallel [(set (reg:CC_NOOV 21)
7024 (unspec:CC_NOOV [(compare:CC_NOOV (match_dup 0)
7025 (match_dup 1))] 4))
7026 (clobber (match_scratch:QI 2 ""))
7027 (clobber (match_scratch:QI 3 ""))])]
7028 "")
7030 ; This is normally not used. The define splits above are used first.
7031 (define_split
7032 [(set (reg:CC 21)
7033 (compare:CC (match_operand:HI 0 "src_operand" "")
7034 (match_operand:HI 1 "src_operand" "")))]
7035 "reload_completed"
7036 [(parallel [(set (reg:CC 21)
7037 (compare:CC (match_dup 0) (match_dup 1)))
7038 (use (reg:QI 20))])]
7039 "")
7041 (define_split
7042 [(set (reg:CC_NOOV 21)
7043 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "")
7044 (match_operand:HI 1 "src_operand" "")))]
7045 "reload_completed"
7046 [(parallel [(set (reg:CC_NOOV 21)
7047 (compare:CC_NOOV (match_dup 0) (match_dup 1)))
7048 (use (reg:QI 20))])]
7049 "")
7051 (define_insn "*cmphi"
7052 [(set (reg:CC 21)
7053 (compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
7054 (match_operand:HI 1 "src_operand" "R,rS<>")))
7055 (use (reg:QI 20))]
7056 "valid_operands (COMPARE, operands, HImode)"
7057 "*
7058 {
7059 int use_ir1 = (reg_operand (operands[0], HImode)
7060 && REG_P (operands[0])
7061 && REGNO (operands[0]) == IR1_REGNO)
7062 || (reg_operand (operands[1], HImode)
7063 && REG_P (operands[1])
7064 && REGNO (operands[1]) == IR1_REGNO);
7066 if (use_ir1)
7067 output_asm_insn (\"push\\tir1\", operands);
7068 else
7069 output_asm_insn (\"push\\tbk\", operands);
7070 output_asm_insn (\"push\\tr0\", operands);
7071 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
7072 if (use_ir1)
7073 {
7074 output_asm_insn (\"ldiu\\tst,ir1\", operands);
7075 output_asm_insn (\"or\\t07bh,ir1\", operands);
7076 }
7077 else
7078 {
7079 output_asm_insn (\"ldiu\\tst,bk\", operands);
7080 output_asm_insn (\"or\\t07bh,bk\", operands);
7081 }
7082 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
7083 if (use_ir1)
7084 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
7085 else
7086 output_asm_insn (\"and3\\tbk,st,bk\", operands);
7087 output_asm_insn (\"pop\\tr0\", operands);
7088 if (use_ir1)
7089 {
7090 output_asm_insn (\"ldiu\\tir1,st\", operands);
7091 output_asm_insn (\"pop\\tir1\", operands);
7092 }
7093 else
7094 {
7095 output_asm_insn (\"ldiu\\tbk,st\", operands);
7096 output_asm_insn (\"pop\\tbk\", operands);
7097 }
7098 return \"\";
7099 }"
7100 [(set_attr "type" "multi")])
7102 (define_insn "*cmphi_noov"
7103 [(set (reg:CC_NOOV 21)
7104 (compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
7105 (match_operand:HI 1 "src_operand" "R,rS<>")))
7106 (use (reg:QI 20))]
7107 "valid_operands (COMPARE, operands, HImode)"
7108 "*
7109 {
7110 int use_ir1 = (reg_operand (operands[0], HImode)
7111 && REG_P (operands[0])
7112 && REGNO (operands[0]) == IR1_REGNO)
7113 || (reg_operand (operands[1], HImode)
7114 && REG_P (operands[1])
7115 && REGNO (operands[1]) == IR1_REGNO);
7117 if (use_ir1)
7118 output_asm_insn (\"push\\tir1\", operands);
7119 else
7120 output_asm_insn (\"push\\tbk\", operands);
7121 output_asm_insn (\"push\\tr0\", operands);
7122 output_asm_insn (\"subi3\\t%1,%0,r0\", operands);
7123 if (use_ir1)
7124 {
7125 output_asm_insn (\"ldiu\\tst,ir1\", operands);
7126 output_asm_insn (\"or\\t07bh,ir1\", operands);
7127 }
7128 else
7129 {
7130 output_asm_insn (\"ldiu\\tst,bk\", operands);
7131 output_asm_insn (\"or\\t07bh,bk\", operands);
7132 }
7133 output_asm_insn (\"subb3\\t%O1,%O0,r0\", operands);
7134 if (use_ir1)
7135 output_asm_insn (\"and3\\tir1,st,ir1\", operands);
7136 else
7137 output_asm_insn (\"and3\\tbk,st,bk\", operands);
7138 output_asm_insn (\"pop\\tr0\", operands);
7139 if (use_ir1)
7140 {
7141 output_asm_insn (\"ldiu\\tir1,st\", operands);
7142 output_asm_insn (\"pop\\tir1\", operands);
7143 }
7144 else
7145 {
7146 output_asm_insn (\"ldiu\\tbk,st\", operands);
7147 output_asm_insn (\"pop\\tbk\", operands);
7148 }
7149 return \"\";
7150 }"
7151 [(set_attr "type" "multi")])
7154 (define_insn "cmphi_cc"
7155 [(set (reg:CC 21)
7156 (unspec:CC [(compare:CC (match_operand:HI 0 "src_operand" "rR,rS<>")
7157 (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
7158 (clobber (match_scratch:QI 2 "=&d,&d"))
7159 (clobber (match_scratch:QI 3 "=&c,&c"))]
7160 "valid_operands (COMPARE, operands, HImode)"
7161 "*
7162 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
7163 output_asm_insn (\"ldiu\\tst,%3\", operands);
7164 output_asm_insn (\"or\\t07bh,%3\", operands);
7165 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
7166 output_asm_insn (\"and\\t%3,st\", operands);
7167 return \"\";"
7168 [(set_attr "type" "multi")])
7170 (define_insn "cmphi_cc_noov"
7171 [(set (reg:CC_NOOV 21)
7172 (unspec:CC_NOOV [(compare:CC_NOOV (match_operand:HI 0 "src_operand" "rR,rS<>")
7173 (match_operand:HI 1 "src_operand" "R,rS<>"))] 4))
7174 (clobber (match_scratch:QI 2 "=&d,&d"))
7175 (clobber (match_scratch:QI 3 "=&c,&c"))]
7176 "valid_operands (COMPARE, operands, HImode)"
7177 "*
7178 output_asm_insn (\"subi3\\t%1,%0,%2\", operands);
7179 output_asm_insn (\"ldiu\\tst,%3\", operands);
7180 output_asm_insn (\"or\\t07bh,%3\", operands);
7181 output_asm_insn (\"subb3\\t%O1,%O0,%2\", operands);
7182 output_asm_insn (\"and\\t%3,st\", operands);
7183 return \"\";"
7184 [(set_attr "type" "multi")])
7186 (define_expand "mulhi3"
7187 [(parallel [(set (match_operand:HI 0 "reg_operand" "")
7188 (mult:HI (match_operand:HI 1 "src_operand" "")
7189 (match_operand:HI 2 "src_operand" "")))
7190 (clobber (reg:CC 21))])]
7191 ""
7192 "c4x_emit_libcall3 (smul_optab->handlers[(int) HImode].libfunc,
7193 MULT, HImode, operands);
7194 DONE;")
7197 ;
7198 ; PEEPHOLES
7199 ;
7201 ; dbCC peepholes
7202 ;
7203 ; Turns
7204 ; loop:
7205 ; [ ... ]
7206 ; bCC label ; abnormal loop termination
7207 ; dbu aN, loop ; normal loop termination
7208 ;
7209 ; Into
7210 ; loop:
7211 ; [ ... ]
7212 ; dbCC aN, loop
7213 ; bCC label
7214 ;
7215 ; Which moves the bCC condition outside the inner loop for free.
7216 ;
7217 (define_peephole
7218 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
7219 [(reg:CC 21) (const_int 0)])
7220 (label_ref (match_operand 2 "" ""))
7221 (pc)))
7222 (parallel
7223 [(set (pc)
7224 (if_then_else
7225 (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a")
7226 (const_int -1))
7227 (const_int 0))
7228 (label_ref (match_operand 1 "" ""))
7229 (pc)))
7230 (set (match_dup 0)
7231 (plus:QI (match_dup 0)
7232 (const_int -1)))
7233 (use (reg:QI 20))
7234 (clobber (reg:CC_NOOV 21))])]
7235 "! c4x_label_conflict (insn, operands[2], operands[1])"
7236 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
7237 [(set_attr "type" "multi")])
7239 (define_peephole
7240 [(set (pc) (if_then_else (match_operator 3 "comparison_operator"
7241 [(reg:CC 21) (const_int 0)])
7242 (label_ref (match_operand 2 "" ""))
7243 (pc)))
7244 (parallel
7245 [(set (pc)
7246 (if_then_else
7247 (ne (match_operand:QI 0 "addr_reg_operand" "+a")
7248 (const_int 0))
7249 (label_ref (match_operand 1 "" ""))
7250 (pc)))
7251 (set (match_dup 0)
7252 (plus:QI (match_dup 0)
7253 (const_int -1)))])]
7254 "! c4x_label_conflict (insn, operands[2], operands[1])"
7255 "db%I3\\t%0,%l1\\n\\tb%3\\t%l2"
7256 [(set_attr "type" "multi")])
7258 ;
7259 ; Peepholes to convert 'call label; rets' into jump label
7260 ;
7262 (define_peephole
7263 [(parallel [(call (mem:QI (match_operand:QI 0 "call_address_operand" ""))
7264 (match_operand:QI 1 "general_operand" ""))
7265 (clobber (reg:QI 31))])
7266 (return)]
7267 "c4x_null_epilogue_p ()"
7268 "*
7269 if (REG_P (operands[0]))
7270 return \"bu%#\\t%C0\";
7271 else
7272 return \"br%#\\t%C0\";"
7273 [(set_attr "type" "jump")])
7275 (define_peephole
7276 [(parallel [(set (match_operand 0 "" "")
7277 (call (mem:QI (match_operand:QI 1 "call_address_operand" ""))
7278 (match_operand:QI 2 "general_operand" "")))
7279 (clobber (reg:QI 31))])
7280 (return)]
7281 "c4x_null_epilogue_p ()"
7282 "*
7283 if (REG_P (operands[1]))
7284 return \"bu%#\\t%C1\";
7285 else
7286 return \"br%#\\t%C1\";"
7287 [(set_attr "type" "jump")])
7290 ; This peephole should be unnecessary with my patches to flow.c
7291 ; for better autoincrement detection
7292 (define_peephole
7293 [(set (match_operand:QF 0 "ext_low_reg_operand" "")
7294 (mem:QF (match_operand:QI 1 "addr_reg_operand" "")))
7295 (set (match_operand:QF 2 "ext_low_reg_operand" "")
7296 (mem:QF (plus:QI (match_dup 1) (const_int 1))))
7297 (parallel [(set (match_dup 1) (plus:QI (match_dup 1) (const_int 2)))
7298 (clobber (reg:CC_NOOV 21))])]
7299 ""
7300 "ldf\\t*%1++,%0\\n\\tldf\\t*%1++,%2")
7303 ; This peephole should be unnecessary with my patches to flow.c
7304 ; for better autoincrement detection
7305 (define_peephole
7306 [(set (mem:QF (match_operand:QI 0 "addr_reg_operand" ""))
7307 (match_operand:QF 1 "ext_low_reg_operand" ""))
7308 (set (mem:QF (plus:QI (match_dup 0) (const_int 1)))
7309 (match_operand:QF 2 "ext_low_reg_operand" ""))
7310 (parallel [(set (match_dup 0) (plus:QI (match_dup 0) (const_int 2)))
7311 (clobber (reg:CC_NOOV 21))])]
7312 ""
7313 "stf\\t%1,*%0++\\n\\tstf\\t%2,*%0++")
7316 ; The following two peepholes remove an unecessary load
7317 ; often found at the end of a function. These peepholes
7318 ; could be generalized to other binary operators. They shouldn't
7319 ; be required if we run a post reload mop-up pass.
7320 (define_peephole
7321 [(parallel [(set (match_operand:QF 0 "ext_reg_operand" "")
7322 (plus:QF (match_operand:QF 1 "ext_reg_operand" "")
7323 (match_operand:QF 2 "ext_reg_operand" "")))
7324 (clobber (reg:CC_NOOV 21))])
7325 (set (match_operand:QF 3 "ext_reg_operand" "")
7326 (match_dup 0))]
7327 "dead_or_set_p (insn, operands[0])"
7328 "addf3\\t%2,%1,%3")
7330 (define_peephole
7331 [(parallel [(set (match_operand:QI 0 "reg_operand" "")
7332 (plus:QI (match_operand:QI 1 "reg_operand" "")
7333 (match_operand:QI 2 "reg_operand" "")))
7334 (clobber (reg:CC_NOOV 21))])
7335 (set (match_operand:QI 3 "reg_operand" "")
7336 (match_dup 0))]
7337 "dead_or_set_p (insn, operands[0])"
7338 "addi3\\t%2,%1,%3")