1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode
;
54 typedef struct minipool_fixup Mfix
;
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
63 const struct attribute_spec arm_attribute_table
[];
65 /* Forward function declarations. */
66 static void arm_add_gc_roots
PARAMS ((void));
67 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, Hint
, rtx
, rtx
, int, int));
68 static Ulong bit_count
PARAMS ((signed int));
69 static int const_ok_for_op
PARAMS ((Hint
, enum rtx_code
));
70 static int eliminate_lr2ip
PARAMS ((rtx
*));
71 static rtx emit_multi_reg_push
PARAMS ((int));
72 static rtx emit_sfm
PARAMS ((int, int));
74 static bool arm_assemble_integer
PARAMS ((rtx
, unsigned int, int));
76 static Ccstar fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
77 static arm_cc get_arm_condition_code
PARAMS ((rtx
));
78 static void init_fpa_table
PARAMS ((void));
79 static Hint int_log2
PARAMS ((Hint
));
80 static rtx is_jump_table
PARAMS ((rtx
));
81 static Ccstar output_multi_immediate
PARAMS ((rtx
*, Ccstar
, Ccstar
, int, Hint
));
82 static void print_multi_reg
PARAMS ((FILE *, Ccstar
, int, int));
83 static Mmode select_dominance_cc_mode
PARAMS ((rtx
, rtx
, Hint
));
84 static Ccstar shift_op
PARAMS ((rtx
, Hint
*));
85 static struct machine_function
* arm_init_machine_status
PARAMS ((void));
86 static int number_of_first_bit_set
PARAMS ((int));
87 static void replace_symbols_in_block
PARAMS ((tree
, rtx
, rtx
));
88 static void thumb_exit
PARAMS ((FILE *, int, rtx
));
89 static void thumb_pushpop
PARAMS ((FILE *, int, int));
90 static Ccstar thumb_condition_code
PARAMS ((rtx
, int));
91 static rtx is_jump_table
PARAMS ((rtx
));
92 static Hint get_jump_table_size
PARAMS ((rtx
));
93 static Mnode
* move_minipool_fix_forward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
94 static Mnode
* add_minipool_forward_ref
PARAMS ((Mfix
*));
95 static Mnode
* move_minipool_fix_backward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
96 static Mnode
* add_minipool_backward_ref
PARAMS ((Mfix
*));
97 static void assign_minipool_offsets
PARAMS ((Mfix
*));
98 static void arm_print_value
PARAMS ((FILE *, rtx
));
99 static void dump_minipool
PARAMS ((rtx
));
100 static int arm_barrier_cost
PARAMS ((rtx
));
101 static Mfix
* create_fix_barrier
PARAMS ((Mfix
*, Hint
));
102 static void push_minipool_barrier
PARAMS ((rtx
, Hint
));
103 static void push_minipool_fix
PARAMS ((rtx
, Hint
, rtx
*, Mmode
, rtx
));
104 static void note_invalid_constants
PARAMS ((rtx
, Hint
));
105 static int current_file_function_operand
PARAMS ((rtx
));
106 static Ulong arm_compute_save_reg0_reg12_mask
PARAMS ((void));
107 static Ulong arm_compute_save_reg_mask
PARAMS ((void));
108 static Ulong arm_isr_value
PARAMS ((tree
));
109 static Ulong arm_compute_func_type
PARAMS ((void));
110 static tree arm_handle_fndecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
111 static tree arm_handle_isr_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
112 static void arm_output_function_epilogue
PARAMS ((FILE *, Hint
));
113 static void arm_output_function_prologue
PARAMS ((FILE *, Hint
));
114 static void thumb_output_function_prologue
PARAMS ((FILE *, Hint
));
115 static int arm_comp_type_attributes
PARAMS ((tree
, tree
));
116 static void arm_set_default_type_attributes
PARAMS ((tree
));
117 static int arm_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
118 static int count_insns_for_constant
PARAMS ((HOST_WIDE_INT
, int));
119 static int arm_get_strip_length
PARAMS ((int));
120 #ifdef OBJECT_FORMAT_ELF
121 static void arm_elf_asm_named_section
PARAMS ((const char *, unsigned int));
124 static void arm_encode_section_info
PARAMS ((tree
, int));
127 static void aof_globalize_label
PARAMS ((FILE *, const char *));
135 /* Initialize the GCC target structure. */
136 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
137 #undef TARGET_MERGE_DECL_ATTRIBUTES
138 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
141 #undef TARGET_ATTRIBUTE_TABLE
142 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
145 #undef TARGET_ASM_BYTE_OP
146 #define TARGET_ASM_BYTE_OP "\tDCB\t"
147 #undef TARGET_ASM_ALIGNED_HI_OP
148 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
149 #undef TARGET_ASM_ALIGNED_SI_OP
150 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
151 #undef TARGET_ASM_GLOBALIZE_LABEL
152 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
154 #undef TARGET_ASM_ALIGNED_SI_OP
155 #define TARGET_ASM_ALIGNED_SI_OP NULL
156 #undef TARGET_ASM_INTEGER
157 #define TARGET_ASM_INTEGER arm_assemble_integer
160 #undef TARGET_ASM_FUNCTION_PROLOGUE
161 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
163 #undef TARGET_ASM_FUNCTION_EPILOGUE
164 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
166 #undef TARGET_COMP_TYPE_ATTRIBUTES
167 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
169 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
170 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
172 #undef TARGET_INIT_BUILTINS
173 #define TARGET_INIT_BUILTINS arm_init_builtins
175 #undef TARGET_EXPAND_BUILTIN
176 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
178 #undef TARGET_SCHED_ADJUST_COST
179 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
181 #undef TARGET_ENCODE_SECTION_INFO
183 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
185 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
188 #undef TARGET_STRIP_NAME_ENCODING
189 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
191 struct gcc_target targetm
= TARGET_INITIALIZER
;
193 /* Obstack for minipool constant handling. */
194 static struct obstack minipool_obstack
;
195 static char * minipool_startobj
;
197 /* The maximum number of insns skipped which
198 will be conditionalised if possible. */
199 static int max_insns_skipped
= 5;
201 extern FILE * asm_out_file
;
203 /* True if we are currently building a constant table. */
204 int making_const_table
;
206 /* Define the information needed to generate branch insns. This is
207 stored from the compare operation. */
208 rtx arm_compare_op0
, arm_compare_op1
;
210 /* What type of floating point are we tuning for? */
211 enum floating_point_type arm_fpu
;
213 /* What type of floating point instructions are available? */
214 enum floating_point_type arm_fpu_arch
;
216 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
217 enum prog_mode_type arm_prgmode
;
219 /* Set by the -mfp=... option. */
220 const char * target_fp_name
= NULL
;
222 /* Used to parse -mstructure_size_boundary command line option. */
223 const char * structure_size_string
= NULL
;
224 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
226 /* Bit values used to identify processor capabilities. */
227 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
228 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
229 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
230 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
231 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
232 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
233 #define FL_THUMB (1 << 6) /* Thumb aware */
234 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
235 #define FL_STRONG (1 << 8) /* StrongARM */
236 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
237 #define FL_XSCALE (1 << 10) /* XScale */
239 /* The bits in this mask specify which
240 instructions we are allowed to generate. */
241 static int insn_flags
= 0;
243 /* The bits in this mask specify which instruction scheduling options should
244 be used. Note - there is an overlap with the FL_FAST_MULT. For some
245 hardware we want to be able to generate the multiply instructions, but to
246 tune as if they were not present in the architecture. */
247 static int tune_flags
= 0;
249 /* The following are used in the arm.md file as equivalents to bits
250 in the above two flag variables. */
252 /* Nonzero if this is an "M" variant of the processor. */
253 int arm_fast_multiply
= 0;
255 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
258 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
261 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
264 /* Nonzero if this chip can benefit from load scheduling. */
265 int arm_ld_sched
= 0;
267 /* Nonzero if this chip is a StrongARM. */
268 int arm_is_strong
= 0;
270 /* Nonzero if this chip is an XScale. */
271 int arm_is_xscale
= 0;
273 /* Nonzero if this chip is an ARM6 or an ARM7. */
274 int arm_is_6_or_7
= 0;
276 /* Nonzero if generating Thumb instructions. */
279 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
280 must report the mode of the memory reference from PRINT_OPERAND to
281 PRINT_OPERAND_ADDRESS. */
282 enum machine_mode output_memory_reference_mode
;
284 /* The register number to be used for the PIC offset register. */
285 const char * arm_pic_register_string
= NULL
;
286 int arm_pic_register
= INVALID_REGNUM
;
288 /* Set to 1 when a return insn is output, this means that the epilogue
290 int return_used_this_function
;
292 /* Set to 1 after arm_reorg has started. Reset to start at the start of
293 the next function. */
294 static int after_arm_reorg
= 0;
296 /* The maximum number of insns to be used when loading a constant. */
297 static int arm_constant_limit
= 3;
299 /* For an explanation of these variables, see final_prescan_insn below. */
301 enum arm_cond_code arm_current_cc
;
303 int arm_target_label
;
305 /* The condition codes of the ARM, and the inverse function. */
306 static const char * const arm_condition_codes
[] =
308 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
309 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
312 #define streq(string1, string2) (strcmp (string1, string2) == 0)
314 /* Initialization code. */
318 const char *const name
;
319 const unsigned int flags
;
322 /* Not all of these give usefully different compilation alternatives,
323 but there is no simple way of generalizing them. */
324 static const struct processors all_cores
[] =
328 {"arm2", FL_CO_PROC
| FL_MODE26
},
329 {"arm250", FL_CO_PROC
| FL_MODE26
},
330 {"arm3", FL_CO_PROC
| FL_MODE26
},
331 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
332 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
333 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
334 {"arm610", FL_MODE26
| FL_MODE32
},
335 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
336 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
337 /* arm7m doesn't exist on its own, but only with D, (and I), but
338 those don't alter the code, so arm7m is sometimes used. */
339 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
340 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
341 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
342 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
343 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
344 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
345 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
346 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
347 {"arm710", FL_MODE26
| FL_MODE32
},
348 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
349 {"arm720", FL_MODE26
| FL_MODE32
},
350 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
351 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
352 {"arm710c", FL_MODE26
| FL_MODE32
},
353 {"arm7100", FL_MODE26
| FL_MODE32
},
354 {"arm7500", FL_MODE26
| FL_MODE32
},
355 /* Doesn't have an external co-proc, but does have embedded fpu. */
356 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
357 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
358 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
359 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
360 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
361 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
362 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
363 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
364 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
365 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
366 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
367 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
368 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
369 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
370 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
371 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
372 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
377 static const struct processors all_architectures
[] =
379 /* ARM Architectures */
381 { "armv2", FL_CO_PROC
| FL_MODE26
},
382 { "armv2a", FL_CO_PROC
| FL_MODE26
},
383 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
384 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
385 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
386 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
387 implementations that support it, so we will leave it out for now. */
388 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
389 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
390 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
391 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
395 /* This is a magic stucture. The 'string' field is magically filled in
396 with a pointer to the value specified by the user on the command line
397 assuming that the user has specified such a value. */
399 struct arm_cpu_select arm_select
[] =
401 /* string name processors */
402 { NULL
, "-mcpu=", all_cores
},
403 { NULL
, "-march=", all_architectures
},
404 { NULL
, "-mtune=", all_cores
}
407 /* Return the number of bits set in value' */
412 unsigned long count
= 0;
416 value
&= ~(value
& -value
);
423 /* Fix up any incompatible options that the user has specified.
424 This has now turned into a maze. */
426 arm_override_options ()
430 /* Set up the flags based on the cpu/architecture selected by the user. */
431 for (i
= ARRAY_SIZE (arm_select
); i
--;)
433 struct arm_cpu_select
* ptr
= arm_select
+ i
;
435 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
437 const struct processors
* sel
;
439 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
440 if (streq (ptr
->string
, sel
->name
))
443 tune_flags
= sel
->flags
;
446 /* If we have been given an architecture and a processor
447 make sure that they are compatible. We only generate
448 a warning though, and we prefer the CPU over the
450 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
451 warning ("switch -mcpu=%s conflicts with -march= switch",
454 insn_flags
= sel
->flags
;
460 if (sel
->name
== NULL
)
461 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
465 /* If the user did not specify a processor, choose one for them. */
468 const struct processors
* sel
;
470 static const struct cpu_default
473 const char *const name
;
477 { TARGET_CPU_arm2
, "arm2" },
478 { TARGET_CPU_arm6
, "arm6" },
479 { TARGET_CPU_arm610
, "arm610" },
480 { TARGET_CPU_arm710
, "arm710" },
481 { TARGET_CPU_arm7m
, "arm7m" },
482 { TARGET_CPU_arm7500fe
, "arm7500fe" },
483 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
484 { TARGET_CPU_arm8
, "arm8" },
485 { TARGET_CPU_arm810
, "arm810" },
486 { TARGET_CPU_arm9
, "arm9" },
487 { TARGET_CPU_strongarm
, "strongarm" },
488 { TARGET_CPU_xscale
, "xscale" },
489 { TARGET_CPU_generic
, "arm" },
492 const struct cpu_default
* def
;
494 /* Find the default. */
495 for (def
= cpu_defaults
; def
->name
; def
++)
496 if (def
->cpu
== TARGET_CPU_DEFAULT
)
499 /* Make sure we found the default CPU. */
500 if (def
->name
== NULL
)
503 /* Find the default CPU's flags. */
504 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
505 if (streq (def
->name
, sel
->name
))
508 if (sel
->name
== NULL
)
511 insn_flags
= sel
->flags
;
513 /* Now check to see if the user has specified some command line
514 switch that require certain abilities from the cpu. */
517 if (TARGET_INTERWORK
|| TARGET_THUMB
)
519 sought
|= (FL_THUMB
| FL_MODE32
);
521 /* Force apcs-32 to be used for interworking. */
522 target_flags
|= ARM_FLAG_APCS_32
;
524 /* There are no ARM processors that support both APCS-26 and
525 interworking. Therefore we force FL_MODE26 to be removed
526 from insn_flags here (if it was set), so that the search
527 below will always be able to find a compatible processor. */
528 insn_flags
&= ~FL_MODE26
;
530 else if (!TARGET_APCS_32
)
533 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
535 /* Try to locate a CPU type that supports all of the abilities
536 of the default CPU, plus the extra abilities requested by
538 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
539 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
542 if (sel
->name
== NULL
)
544 unsigned int current_bit_count
= 0;
545 const struct processors
* best_fit
= NULL
;
547 /* Ideally we would like to issue an error message here
548 saying that it was not possible to find a CPU compatible
549 with the default CPU, but which also supports the command
550 line options specified by the programmer, and so they
551 ought to use the -mcpu=<name> command line option to
552 override the default CPU type.
554 Unfortunately this does not work with multilibing. We
555 need to be able to support multilibs for -mapcs-26 and for
556 -mthumb-interwork and there is no CPU that can support both
557 options. Instead if we cannot find a cpu that has both the
558 characteristics of the default cpu and the given command line
559 options we scan the array again looking for a best match. */
560 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
561 if ((sel
->flags
& sought
) == sought
)
565 count
= bit_count (sel
->flags
& insn_flags
);
567 if (count
>= current_bit_count
)
570 current_bit_count
= count
;
574 if (best_fit
== NULL
)
580 insn_flags
= sel
->flags
;
584 /* If tuning has not been specified, tune for whichever processor or
585 architecture has been selected. */
587 tune_flags
= insn_flags
;
589 /* Make sure that the processor choice does not conflict with any of the
590 other command line choices. */
591 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
593 /* If APCS-32 was not the default then it must have been set by the
594 user, so issue a warning message. If the user has specified
595 "-mapcs-32 -mcpu=arm2" then we loose here. */
596 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
597 warning ("target CPU does not support APCS-32" );
598 target_flags
&= ~ARM_FLAG_APCS_32
;
600 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
602 warning ("target CPU does not support APCS-26" );
603 target_flags
|= ARM_FLAG_APCS_32
;
606 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
608 warning ("target CPU does not support interworking" );
609 target_flags
&= ~ARM_FLAG_INTERWORK
;
612 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
614 warning ("target CPU does not support THUMB instructions");
615 target_flags
&= ~ARM_FLAG_THUMB
;
618 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
620 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
621 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
624 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
625 from here where no function is being compiled currently. */
626 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
628 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
630 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
631 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
633 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
634 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
636 /* If interworking is enabled then APCS-32 must be selected as well. */
637 if (TARGET_INTERWORK
)
640 warning ("interworking forces APCS-32 to be used" );
641 target_flags
|= ARM_FLAG_APCS_32
;
644 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
646 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
647 target_flags
|= ARM_FLAG_APCS_FRAME
;
650 if (TARGET_POKE_FUNCTION_NAME
)
651 target_flags
|= ARM_FLAG_APCS_FRAME
;
653 if (TARGET_APCS_REENT
&& flag_pic
)
654 error ("-fpic and -mapcs-reent are incompatible");
656 if (TARGET_APCS_REENT
)
657 warning ("APCS reentrant code not supported. Ignored");
659 /* If this target is normally configured to use APCS frames, warn if they
660 are turned off and debugging is turned on. */
662 && write_symbols
!= NO_DEBUG
663 && !TARGET_APCS_FRAME
664 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
665 warning ("-g with -mno-apcs-frame may not give sensible debugging");
667 /* If stack checking is disabled, we can use r10 as the PIC register,
668 which keeps r9 available. */
670 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
672 if (TARGET_APCS_FLOAT
)
673 warning ("passing floating point arguments in fp regs not yet supported");
675 /* Initialize boolean versions of the flags, for use in the arm.md file. */
676 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
677 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
678 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
679 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
680 arm_is_xscale
= (insn_flags
& FL_XSCALE
) != 0;
682 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
683 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
684 thumb_code
= (TARGET_ARM
== 0);
685 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
686 && !(tune_flags
& FL_ARCH4
))) != 0;
688 /* Default value for floating point code... if no co-processor
689 bus, then schedule for emulated floating point. Otherwise,
690 assume the user has an FPA.
691 Note: this does not prevent use of floating point instructions,
692 -msoft-float does that. */
693 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
697 if (streq (target_fp_name
, "2"))
698 arm_fpu_arch
= FP_SOFT2
;
699 else if (streq (target_fp_name
, "3"))
700 arm_fpu_arch
= FP_SOFT3
;
702 error ("invalid floating point emulation option: -mfpe-%s",
706 arm_fpu_arch
= FP_DEFAULT
;
708 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
711 /* For arm2/3 there is no need to do any scheduling if there is only
712 a floating point emulator, or we are doing software floating-point. */
713 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
714 && (tune_flags
& FL_MODE32
) == 0)
715 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
717 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
719 if (structure_size_string
!= NULL
)
721 int size
= strtol (structure_size_string
, NULL
, 0);
723 if (size
== 8 || size
== 32)
724 arm_structure_size_boundary
= size
;
726 warning ("structure size boundary can only be set to 8 or 32");
729 if (arm_pic_register_string
!= NULL
)
731 int pic_register
= decode_reg_name (arm_pic_register_string
);
734 warning ("-mpic-register= is useless without -fpic");
736 /* Prevent the user from choosing an obviously stupid PIC register. */
737 else if (pic_register
< 0 || call_used_regs
[pic_register
]
738 || pic_register
== HARD_FRAME_POINTER_REGNUM
739 || pic_register
== STACK_POINTER_REGNUM
740 || pic_register
>= PC_REGNUM
)
741 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
743 arm_pic_register
= pic_register
;
746 if (TARGET_THUMB
&& flag_schedule_insns
)
748 /* Don't warn since it's on by default in -O2. */
749 flag_schedule_insns
= 0;
752 /* If optimizing for space, don't synthesize constants.
753 For processors with load scheduling, it never costs more than 2 cycles
754 to load a constant, and the load scheduler may well reduce that to 1. */
755 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
756 arm_constant_limit
= 1;
759 arm_constant_limit
= 2;
761 /* If optimizing for size, bump the number of instructions that we
762 are prepared to conditionally execute (even on a StrongARM).
763 Otherwise for the StrongARM, which has early execution of branches,
764 a sequence that is worth skipping is shorter. */
766 max_insns_skipped
= 6;
767 else if (arm_is_strong
)
768 max_insns_skipped
= 3;
770 /* Register global variables with the garbage collector. */
777 gcc_obstack_init(&minipool_obstack
);
778 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
781 /* A table of known ARM exception types.
782 For use with the interrupt function attribute. */
786 const char *const arg
;
787 const unsigned long return_value
;
791 static const isr_attribute_arg isr_attribute_args
[] =
793 { "IRQ", ARM_FT_ISR
},
794 { "irq", ARM_FT_ISR
},
795 { "FIQ", ARM_FT_FIQ
},
796 { "fiq", ARM_FT_FIQ
},
797 { "ABORT", ARM_FT_ISR
},
798 { "abort", ARM_FT_ISR
},
799 { "ABORT", ARM_FT_ISR
},
800 { "abort", ARM_FT_ISR
},
801 { "UNDEF", ARM_FT_EXCEPTION
},
802 { "undef", ARM_FT_EXCEPTION
},
803 { "SWI", ARM_FT_EXCEPTION
},
804 { "swi", ARM_FT_EXCEPTION
},
805 { NULL
, ARM_FT_NORMAL
}
808 /* Returns the (interrupt) function type of the current
809 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
812 arm_isr_value (argument
)
815 const isr_attribute_arg
* ptr
;
818 /* No argument - default to IRQ. */
819 if (argument
== NULL_TREE
)
822 /* Get the value of the argument. */
823 if (TREE_VALUE (argument
) == NULL_TREE
824 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
825 return ARM_FT_UNKNOWN
;
827 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
829 /* Check it against the list of known arguments. */
830 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
831 if (streq (arg
, ptr
->arg
))
832 return ptr
->return_value
;
834 /* An unrecognized interrupt type. */
835 return ARM_FT_UNKNOWN
;
838 /* Computes the type of the current function. */
841 arm_compute_func_type ()
843 unsigned long type
= ARM_FT_UNKNOWN
;
847 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
850 /* Decide if the current function is volatile. Such functions
851 never return, and many memory cycles can be saved by not storing
852 register values that will never be needed again. This optimization
853 was added to speed up context switching in a kernel application. */
855 && current_function_nothrow
856 && TREE_THIS_VOLATILE (current_function_decl
))
857 type
|= ARM_FT_VOLATILE
;
859 if (current_function_needs_context
)
860 type
|= ARM_FT_NESTED
;
862 attr
= DECL_ATTRIBUTES (current_function_decl
);
864 a
= lookup_attribute ("naked", attr
);
866 type
|= ARM_FT_NAKED
;
868 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
869 type
|= ARM_FT_EXCEPTION_HANDLER
;
872 a
= lookup_attribute ("isr", attr
);
874 a
= lookup_attribute ("interrupt", attr
);
877 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
879 type
|= arm_isr_value (TREE_VALUE (a
));
885 /* Returns the type of the current function. */
888 arm_current_func_type ()
890 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
891 cfun
->machine
->func_type
= arm_compute_func_type ();
893 return cfun
->machine
->func_type
;
896 /* Return 1 if it is possible to return using a single instruction. */
899 use_return_insn (iscond
)
903 unsigned int func_type
;
905 /* Never use a return instruction before reload has run. */
906 if (!reload_completed
)
909 func_type
= arm_current_func_type ();
911 /* Naked functions and volatile functions need special
913 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
916 /* As do variadic functions. */
917 if (current_function_pretend_args_size
918 || cfun
->machine
->uses_anonymous_args
919 /* Of if the function calls __builtin_eh_return () */
920 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
921 /* Or if there is no frame pointer and there is a stack adjustment. */
922 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
923 && !frame_pointer_needed
))
926 /* Can't be done if interworking with Thumb, and any registers have been
927 stacked. Similarly, on StrongARM, conditional returns are expensive
928 if they aren't taken and registers have been stacked. */
929 if (iscond
&& arm_is_strong
&& frame_pointer_needed
)
932 if ((iscond
&& arm_is_strong
)
935 for (regno
= 0; regno
<= LAST_ARM_REGNUM
; regno
++)
936 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
939 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
943 /* Can't be done if any of the FPU regs are pushed,
944 since this also requires an insn. */
945 if (TARGET_HARD_FLOAT
)
946 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
947 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
953 /* Return TRUE if int I is a valid immediate ARM constant. */
959 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
961 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
962 be all zero, or all one. */
963 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
964 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
965 != ((~(unsigned HOST_WIDE_INT
) 0)
966 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
969 /* Fast return for 0 and powers of 2 */
970 if ((i
& (i
- 1)) == 0)
975 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
978 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
979 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
981 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
986 /* Return true if I is a valid constant for the operation CODE. */
988 const_ok_for_op (i
, code
)
992 if (const_ok_for_arm (i
))
998 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1000 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1006 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1013 /* Emit a sequence of insns to handle a large constant.
1014 CODE is the code of the operation required, it can be any of SET, PLUS,
1015 IOR, AND, XOR, MINUS;
1016 MODE is the mode in which the operation is being performed;
1017 VAL is the integer to operate on;
1018 SOURCE is the other operand (a register, or a null-pointer for SET);
1019 SUBTARGETS means it is safe to create scratch registers if that will
1020 either produce a simpler sequence, or we will want to cse the values.
1021 Return value is the number of insns emitted. */
1024 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
1026 enum machine_mode mode
;
1032 if (subtargets
|| code
== SET
1033 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1034 && REGNO (target
) != REGNO (source
)))
1036 /* After arm_reorg has been called, we can't fix up expensive
1037 constants by pushing them into memory so we must synthesize
1038 them in-line, regardless of the cost. This is only likely to
1039 be more costly on chips that have load delay slots and we are
1040 compiling without running the scheduler (so no splitting
1041 occurred before the final instruction emission).
1043 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1045 if (!after_arm_reorg
1046 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1047 > arm_constant_limit
+ (code
!= SET
)))
1051 /* Currently SET is the only monadic value for CODE, all
1052 the rest are diadic. */
1053 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1058 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1060 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1061 /* For MINUS, the value is subtracted from, since we never
1062 have subtraction of a constant. */
1064 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1065 gen_rtx_MINUS (mode
, temp
, source
)));
1067 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1068 gen_rtx (code
, mode
, source
, temp
)));
1074 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1078 count_insns_for_constant (remainder
, i
)
1079 HOST_WIDE_INT remainder
;
1082 HOST_WIDE_INT temp1
;
1090 if (remainder
& (3 << (i
- 2)))
1095 temp1
= remainder
& ((0x0ff << end
)
1096 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1097 remainder
&= ~temp1
;
1102 } while (remainder
);
1106 /* As above, but extra parameter GENERATE which, if clear, suppresses
1110 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
1112 enum machine_mode mode
;
1121 int can_negate_initial
= 0;
1124 int num_bits_set
= 0;
1125 int set_sign_bit_copies
= 0;
1126 int clear_sign_bit_copies
= 0;
1127 int clear_zero_bit_copies
= 0;
1128 int set_zero_bit_copies
= 0;
1130 unsigned HOST_WIDE_INT temp1
, temp2
;
1131 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1133 /* Find out which operations are safe for a given CODE. Also do a quick
1134 check for degenerate cases; these can occur when DImode operations
1146 can_negate_initial
= 1;
1150 if (remainder
== 0xffffffff)
1153 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1154 GEN_INT (ARM_SIGN_EXTEND (val
))));
1159 if (reload_completed
&& rtx_equal_p (target
, source
))
1162 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1171 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1174 if (remainder
== 0xffffffff)
1176 if (reload_completed
&& rtx_equal_p (target
, source
))
1179 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1188 if (reload_completed
&& rtx_equal_p (target
, source
))
1191 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1194 if (remainder
== 0xffffffff)
1197 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1198 gen_rtx_NOT (mode
, source
)));
1202 /* We don't know how to handle this yet below. */
1206 /* We treat MINUS as (val - source), since (source - val) is always
1207 passed as (source + (-val)). */
1211 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1212 gen_rtx_NEG (mode
, source
)));
1215 if (const_ok_for_arm (val
))
1218 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1219 gen_rtx_MINUS (mode
, GEN_INT (val
),
1231 /* If we can do it in one insn get out quickly. */
1232 if (const_ok_for_arm (val
)
1233 || (can_negate_initial
&& const_ok_for_arm (-val
))
1234 || (can_invert
&& const_ok_for_arm (~val
)))
1237 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1238 (source
? gen_rtx (code
, mode
, source
,
1244 /* Calculate a few attributes that may be useful for specific
1246 for (i
= 31; i
>= 0; i
--)
1248 if ((remainder
& (1 << i
)) == 0)
1249 clear_sign_bit_copies
++;
1254 for (i
= 31; i
>= 0; i
--)
1256 if ((remainder
& (1 << i
)) != 0)
1257 set_sign_bit_copies
++;
1262 for (i
= 0; i
<= 31; i
++)
1264 if ((remainder
& (1 << i
)) == 0)
1265 clear_zero_bit_copies
++;
1270 for (i
= 0; i
<= 31; i
++)
1272 if ((remainder
& (1 << i
)) != 0)
1273 set_zero_bit_copies
++;
1281 /* See if we can do this by sign_extending a constant that is known
1282 to be negative. This is a good, way of doing it, since the shift
1283 may well merge into a subsequent insn. */
1284 if (set_sign_bit_copies
> 1)
1286 if (const_ok_for_arm
1287 (temp1
= ARM_SIGN_EXTEND (remainder
1288 << (set_sign_bit_copies
- 1))))
1292 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1293 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1295 emit_insn (gen_ashrsi3 (target
, new_src
,
1296 GEN_INT (set_sign_bit_copies
- 1)));
1300 /* For an inverted constant, we will need to set the low bits,
1301 these will be shifted out of harm's way. */
1302 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1303 if (const_ok_for_arm (~temp1
))
1307 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1308 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1310 emit_insn (gen_ashrsi3 (target
, new_src
,
1311 GEN_INT (set_sign_bit_copies
- 1)));
1317 /* See if we can generate this by setting the bottom (or the top)
1318 16 bits, and then shifting these into the other half of the
1319 word. We only look for the simplest cases, to do more would cost
1320 too much. Be careful, however, not to generate this when the
1321 alternative would take fewer insns. */
1322 if (val
& 0xffff0000)
1324 temp1
= remainder
& 0xffff0000;
1325 temp2
= remainder
& 0x0000ffff;
1327 /* Overlaps outside this range are best done using other methods. */
1328 for (i
= 9; i
< 24; i
++)
1330 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1331 && !const_ok_for_arm (temp2
))
1333 rtx new_src
= (subtargets
1334 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1336 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1337 source
, subtargets
, generate
);
1340 emit_insn (gen_rtx_SET
1343 gen_rtx_ASHIFT (mode
, source
,
1350 /* Don't duplicate cases already considered. */
1351 for (i
= 17; i
< 24; i
++)
1353 if (((temp1
| (temp1
>> i
)) == remainder
)
1354 && !const_ok_for_arm (temp1
))
1356 rtx new_src
= (subtargets
1357 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1359 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1360 source
, subtargets
, generate
);
1364 (gen_rtx_SET (VOIDmode
, target
,
1367 gen_rtx_LSHIFTRT (mode
, source
,
1378 /* If we have IOR or XOR, and the constant can be loaded in a
1379 single instruction, and we can find a temporary to put it in,
1380 then this can be done in two instructions instead of 3-4. */
1382 /* TARGET can't be NULL if SUBTARGETS is 0 */
1383 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1385 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1389 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1391 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1392 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1393 gen_rtx (code
, mode
, source
, sub
)));
1402 if (set_sign_bit_copies
> 8
1403 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1407 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1408 rtx shift
= GEN_INT (set_sign_bit_copies
);
1410 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1412 gen_rtx_ASHIFT (mode
,
1415 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1417 gen_rtx_LSHIFTRT (mode
, sub
,
1423 if (set_zero_bit_copies
> 8
1424 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1428 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1429 rtx shift
= GEN_INT (set_zero_bit_copies
);
1431 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1433 gen_rtx_LSHIFTRT (mode
,
1436 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1438 gen_rtx_ASHIFT (mode
, sub
,
1444 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1448 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1449 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1450 gen_rtx_NOT (mode
, source
)));
1453 sub
= gen_reg_rtx (mode
);
1454 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1455 gen_rtx_AND (mode
, source
,
1457 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1458 gen_rtx_NOT (mode
, sub
)));
1465 /* See if two shifts will do 2 or more insn's worth of work. */
1466 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1468 HOST_WIDE_INT shift_mask
= ((0xffffffff
1469 << (32 - clear_sign_bit_copies
))
1472 if ((remainder
| shift_mask
) != 0xffffffff)
1476 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1477 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1478 new_src
, source
, subtargets
, 1);
1483 rtx targ
= subtargets
? NULL_RTX
: target
;
1484 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1485 targ
, source
, subtargets
, 0);
1491 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1492 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1494 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1495 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1501 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1503 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1505 if ((remainder
| shift_mask
) != 0xffffffff)
1509 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1511 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1512 new_src
, source
, subtargets
, 1);
1517 rtx targ
= subtargets
? NULL_RTX
: target
;
1519 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1520 targ
, source
, subtargets
, 0);
1526 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1527 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1529 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1530 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1542 for (i
= 0; i
< 32; i
++)
1543 if (remainder
& (1 << i
))
1546 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1547 remainder
= (~remainder
) & 0xffffffff;
1548 else if (code
== PLUS
&& num_bits_set
> 16)
1549 remainder
= (-remainder
) & 0xffffffff;
1556 /* Now try and find a way of doing the job in either two or three
1558 We start by looking for the largest block of zeros that are aligned on
1559 a 2-bit boundary, we then fill up the temps, wrapping around to the
1560 top of the word when we drop off the bottom.
1561 In the worst case this code should produce no more than four insns. */
1564 int best_consecutive_zeros
= 0;
1566 for (i
= 0; i
< 32; i
+= 2)
1568 int consecutive_zeros
= 0;
1570 if (!(remainder
& (3 << i
)))
1572 while ((i
< 32) && !(remainder
& (3 << i
)))
1574 consecutive_zeros
+= 2;
1577 if (consecutive_zeros
> best_consecutive_zeros
)
1579 best_consecutive_zeros
= consecutive_zeros
;
1580 best_start
= i
- consecutive_zeros
;
1586 /* So long as it won't require any more insns to do so, it's
1587 desirable to emit a small constant (in bits 0...9) in the last
1588 insn. This way there is more chance that it can be combined with
1589 a later addressing insn to form a pre-indexed load or store
1590 operation. Consider:
1592 *((volatile int *)0xe0000100) = 1;
1593 *((volatile int *)0xe0000110) = 2;
1595 We want this to wind up as:
1599 str rB, [rA, #0x100]
1601 str rB, [rA, #0x110]
1603 rather than having to synthesize both large constants from scratch.
1605 Therefore, we calculate how many insns would be required to emit
1606 the constant starting from `best_start', and also starting from
1607 zero (ie with bit 31 first to be output). If `best_start' doesn't
1608 yield a shorter sequence, we may as well use zero. */
1610 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1611 && (count_insns_for_constant (remainder
, 0) <=
1612 count_insns_for_constant (remainder
, best_start
)))
1615 /* Now start emitting the insns. */
1623 if (remainder
& (3 << (i
- 2)))
1628 temp1
= remainder
& ((0x0ff << end
)
1629 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1630 remainder
&= ~temp1
;
1634 rtx new_src
, temp1_rtx
;
1636 if (code
== SET
|| code
== MINUS
)
1638 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1639 if (can_invert
&& code
!= MINUS
)
1644 if (remainder
&& subtargets
)
1645 new_src
= gen_reg_rtx (mode
);
1650 else if (can_negate
)
1654 temp1
= trunc_int_for_mode (temp1
, mode
);
1655 temp1_rtx
= GEN_INT (temp1
);
1659 else if (code
== MINUS
)
1660 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1662 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1664 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1673 else if (code
== MINUS
)
1687 /* Canonicalize a comparison so that we are more likely to recognize it.
1688 This can be done for a few constant compares, where we can make the
1689 immediate value easier to load. */
1692 arm_canonicalize_comparison (code
, op1
)
1696 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1706 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1707 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1709 *op1
= GEN_INT (i
+ 1);
1710 return code
== GT
? GE
: LT
;
1716 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1717 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1719 *op1
= GEN_INT (i
- 1);
1720 return code
== GE
? GT
: LE
;
1726 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1727 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1729 *op1
= GEN_INT (i
+ 1);
1730 return code
== GTU
? GEU
: LTU
;
1737 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1739 *op1
= GEN_INT (i
- 1);
1740 return code
== GEU
? GTU
: LEU
;
1751 /* Decide whether a type should be returned in memory (true)
1752 or in a register (false). This is called by the macro
1753 RETURN_IN_MEMORY. */
1756 arm_return_in_memory (type
)
1761 if (!AGGREGATE_TYPE_P (type
))
1762 /* All simple types are returned in registers. */
1765 size
= int_size_in_bytes (type
);
1769 /* ATPCS returns aggregate types in memory only if they are
1770 larger than a word (or are variable size). */
1771 return (size
< 0 || size
> UNITS_PER_WORD
);
1774 /* For the arm-wince targets we choose to be compitable with Microsoft's
1775 ARM and Thumb compilers, which always return aggregates in memory. */
1777 /* All structures/unions bigger than one word are returned in memory.
1778 Also catch the case where int_size_in_bytes returns -1. In this case
1779 the aggregate is either huge or of varaible size, and in either case
1780 we will want to return it via memory and not in a register. */
1781 if (size
< 0 || size
> UNITS_PER_WORD
)
1784 if (TREE_CODE (type
) == RECORD_TYPE
)
1788 /* For a struct the APCS says that we only return in a register
1789 if the type is 'integer like' and every addressable element
1790 has an offset of zero. For practical purposes this means
1791 that the structure can have at most one non bit-field element
1792 and that this element must be the first one in the structure. */
1794 /* Find the first field, ignoring non FIELD_DECL things which will
1795 have been created by C++. */
1796 for (field
= TYPE_FIELDS (type
);
1797 field
&& TREE_CODE (field
) != FIELD_DECL
;
1798 field
= TREE_CHAIN (field
))
1802 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1804 /* Check that the first field is valid for returning in a register. */
1806 /* ... Floats are not allowed */
1807 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1810 /* ... Aggregates that are not themselves valid for returning in
1811 a register are not allowed. */
1812 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1815 /* Now check the remaining fields, if any. Only bitfields are allowed,
1816 since they are not addressable. */
1817 for (field
= TREE_CHAIN (field
);
1819 field
= TREE_CHAIN (field
))
1821 if (TREE_CODE (field
) != FIELD_DECL
)
1824 if (!DECL_BIT_FIELD_TYPE (field
))
1831 if (TREE_CODE (type
) == UNION_TYPE
)
1835 /* Unions can be returned in registers if every element is
1836 integral, or can be returned in an integer register. */
1837 for (field
= TYPE_FIELDS (type
);
1839 field
= TREE_CHAIN (field
))
1841 if (TREE_CODE (field
) != FIELD_DECL
)
1844 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1847 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1853 #endif /* not ARM_WINCE */
1855 /* Return all other types in memory. */
1859 /* Indicate whether or not words of a double are in big-endian order. */
1862 arm_float_words_big_endian ()
1865 /* For FPA, float words are always big-endian. For VFP, floats words
1866 follow the memory system mode. */
1868 if (TARGET_HARD_FLOAT
)
1870 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1875 return (TARGET_BIG_END
? 1 : 0);
1880 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1881 for a call to a function whose data type is FNTYPE.
1882 For a library call, FNTYPE is NULL. */
1884 arm_init_cumulative_args (pcum
, fntype
, libname
, indirect
)
1885 CUMULATIVE_ARGS
* pcum
;
1887 rtx libname ATTRIBUTE_UNUSED
;
1888 int indirect ATTRIBUTE_UNUSED
;
1890 /* On the ARM, the offset starts at 0. */
1891 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1893 pcum
->call_cookie
= CALL_NORMAL
;
1895 if (TARGET_LONG_CALLS
)
1896 pcum
->call_cookie
= CALL_LONG
;
1898 /* Check for long call/short call attributes. The attributes
1899 override any command line option. */
1902 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1903 pcum
->call_cookie
= CALL_SHORT
;
1904 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1905 pcum
->call_cookie
= CALL_LONG
;
1909 /* Determine where to put an argument to a function.
1910 Value is zero to push the argument on the stack,
1911 or a hard register in which to store the argument.
1913 MODE is the argument's machine mode.
1914 TYPE is the data type of the argument (as a tree).
1915 This is null for libcalls where that information may
1917 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1918 the preceding args and about the function being called.
1919 NAMED is nonzero if this argument is a named parameter
1920 (otherwise it is an extra parameter matching an ellipsis). */
1923 arm_function_arg (pcum
, mode
, type
, named
)
1924 CUMULATIVE_ARGS
* pcum
;
1925 enum machine_mode mode
;
1926 tree type ATTRIBUTE_UNUSED
;
1929 if (mode
== VOIDmode
)
1930 /* Compute operand 2 of the call insn. */
1931 return GEN_INT (pcum
->call_cookie
);
1933 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
1936 return gen_rtx_REG (mode
, pcum
->nregs
);
1939 /* Encode the current state of the #pragma [no_]long_calls. */
1942 OFF
, /* No #pramgma [no_]long_calls is in effect. */
1943 LONG
, /* #pragma long_calls is in effect. */
1944 SHORT
/* #pragma no_long_calls is in effect. */
1947 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
1950 arm_pr_long_calls (pfile
)
1951 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1953 arm_pragma_long_calls
= LONG
;
1957 arm_pr_no_long_calls (pfile
)
1958 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1960 arm_pragma_long_calls
= SHORT
;
1964 arm_pr_long_calls_off (pfile
)
1965 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1967 arm_pragma_long_calls
= OFF
;
1970 /* Table of machine attributes. */
1971 const struct attribute_spec arm_attribute_table
[] =
1973 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1974 /* Function calls made to this symbol must be done indirectly, because
1975 it may lie outside of the 26 bit addressing range of a normal function
1977 { "long_call", 0, 0, false, true, true, NULL
},
1978 /* Whereas these functions are always known to reside within the 26 bit
1979 addressing range. */
1980 { "short_call", 0, 0, false, true, true, NULL
},
1981 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1982 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
1983 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
1984 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1986 /* ARM/PE has three new attributes:
1988 dllexport - for exporting a function/variable that will live in a dll
1989 dllimport - for importing a function/variable from a dll
1991 Microsoft allows multiple declspecs in one __declspec, separating
1992 them with spaces. We do NOT support this. Instead, use __declspec
1995 { "dllimport", 0, 0, true, false, false, NULL
},
1996 { "dllexport", 0, 0, true, false, false, NULL
},
1997 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
1999 { NULL
, 0, 0, false, false, false, NULL
}
2002 /* Handle an attribute requiring a FUNCTION_DECL;
2003 arguments as in struct attribute_spec.handler. */
2006 arm_handle_fndecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
2009 tree args ATTRIBUTE_UNUSED
;
2010 int flags ATTRIBUTE_UNUSED
;
2011 bool * no_add_attrs
;
2013 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2015 warning ("`%s' attribute only applies to functions",
2016 IDENTIFIER_POINTER (name
));
2017 *no_add_attrs
= true;
2023 /* Handle an "interrupt" or "isr" attribute;
2024 arguments as in struct attribute_spec.handler. */
2027 arm_handle_isr_attribute (node
, name
, args
, flags
, no_add_attrs
)
2032 bool * no_add_attrs
;
2036 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2038 warning ("`%s' attribute only applies to functions",
2039 IDENTIFIER_POINTER (name
));
2040 *no_add_attrs
= true;
2042 /* FIXME: the argument if any is checked for type attributes;
2043 should it be checked for decl ones? */
2047 if (TREE_CODE (*node
) == FUNCTION_TYPE
2048 || TREE_CODE (*node
) == METHOD_TYPE
)
2050 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2052 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2053 *no_add_attrs
= true;
2056 else if (TREE_CODE (*node
) == POINTER_TYPE
2057 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2058 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2059 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2061 *node
= build_type_copy (*node
);
2062 TREE_TYPE (*node
) = build_type_attribute_variant
2064 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2065 *no_add_attrs
= true;
2069 /* Possibly pass this attribute on from the type to a decl. */
2070 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2071 | (int) ATTR_FLAG_FUNCTION_NEXT
2072 | (int) ATTR_FLAG_ARRAY_NEXT
))
2074 *no_add_attrs
= true;
2075 return tree_cons (name
, args
, NULL_TREE
);
2079 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2087 /* Return 0 if the attributes for two types are incompatible, 1 if they
2088 are compatible, and 2 if they are nearly compatible (which causes a
2089 warning to be generated). */
2092 arm_comp_type_attributes (type1
, type2
)
2098 /* Check for mismatch of non-default calling convention. */
2099 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2102 /* Check for mismatched call attributes. */
2103 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2104 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2105 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2106 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2108 /* Only bother to check if an attribute is defined. */
2109 if (l1
| l2
| s1
| s2
)
2111 /* If one type has an attribute, the other must have the same attribute. */
2112 if ((l1
!= l2
) || (s1
!= s2
))
2115 /* Disallow mixed attributes. */
2116 if ((l1
& s2
) || (l2
& s1
))
2120 /* Check for mismatched ISR attribute. */
2121 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2123 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2124 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2126 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2133 /* Encode long_call or short_call attribute by prefixing
2134 symbol name in DECL with a special character FLAG. */
2137 arm_encode_call_attribute (decl
, flag
)
2141 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2142 int len
= strlen (str
);
2145 /* Do not allow weak functions to be treated as short call. */
2146 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2149 newstr
= alloca (len
+ 2);
2151 strcpy (newstr
+ 1, str
);
2153 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2154 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2157 /* Assigns default attributes to newly defined type. This is used to
2158 set short_call/long_call attributes for function types of
2159 functions defined inside corresponding #pragma scopes. */
2162 arm_set_default_type_attributes (type
)
2165 /* Add __attribute__ ((long_call)) to all functions, when
2166 inside #pragma long_calls or __attribute__ ((short_call)),
2167 when inside #pragma no_long_calls. */
2168 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2170 tree type_attr_list
, attr_name
;
2171 type_attr_list
= TYPE_ATTRIBUTES (type
);
2173 if (arm_pragma_long_calls
== LONG
)
2174 attr_name
= get_identifier ("long_call");
2175 else if (arm_pragma_long_calls
== SHORT
)
2176 attr_name
= get_identifier ("short_call");
2180 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2181 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2185 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2186 defined within the current compilation unit. If this caanot be
2187 determined, then 0 is returned. */
2190 current_file_function_operand (sym_ref
)
2193 /* This is a bit of a fib. A function will have a short call flag
2194 applied to its name if it has the short call attribute, or it has
2195 already been defined within the current compilation unit. */
2196 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2199 /* The current function is always defined within the current compilation
2200 unit. if it s a weak definition however, then this may not be the real
2201 definition of the function, and so we have to say no. */
2202 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2203 && !DECL_WEAK (current_function_decl
))
2206 /* We cannot make the determination - default to returning 0. */
2210 /* Return non-zero if a 32 bit "long_call" should be generated for
2211 this call. We generate a long_call if the function:
2213 a. has an __attribute__((long call))
2214 or b. is within the scope of a #pragma long_calls
2215 or c. the -mlong-calls command line switch has been specified
2217 However we do not generate a long call if the function:
2219 d. has an __attribute__ ((short_call))
2220 or e. is inside the scope of a #pragma no_long_calls
2221 or f. has an __attribute__ ((section))
2222 or g. is defined within the current compilation unit.
2224 This function will be called by C fragments contained in the machine
2225 description file. CALL_REF and CALL_COOKIE correspond to the matched
2226 rtl operands. CALL_SYMBOL is used to distinguish between
2227 two different callers of the function. It is set to 1 in the
2228 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2229 and "call_value" patterns. This is because of the difference in the
2230 SYM_REFs passed by these patterns. */
2233 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
2240 if (GET_CODE (sym_ref
) != MEM
)
2243 sym_ref
= XEXP (sym_ref
, 0);
2246 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2249 if (call_cookie
& CALL_SHORT
)
2252 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2255 if (current_file_function_operand (sym_ref
))
2258 return (call_cookie
& CALL_LONG
)
2259 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2260 || TARGET_LONG_CALLS
;
2263 /* Return non-zero if it is ok to make a tail-call to DECL. */
2266 arm_function_ok_for_sibcall (decl
)
2269 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2271 /* Never tailcall something for which we have no decl, or if we
2272 are in Thumb mode. */
2273 if (decl
== NULL
|| TARGET_THUMB
)
2276 /* Get the calling method. */
2277 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2278 call_type
= CALL_SHORT
;
2279 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2280 call_type
= CALL_LONG
;
2282 /* Cannot tail-call to long calls, since these are out of range of
2283 a branch instruction. However, if not compiling PIC, we know
2284 we can reach the symbol if it is in this compilation unit. */
2285 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2288 /* If we are interworking and the function is not declared static
2289 then we can't tail-call it unless we know that it exists in this
2290 compilation unit (since it might be a Thumb routine). */
2291 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2294 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2295 if (IS_INTERRUPT (arm_current_func_type ()))
2298 /* Everything else is ok. */
2304 legitimate_pic_operand_p (x
)
2309 && (GET_CODE (x
) == SYMBOL_REF
2310 || (GET_CODE (x
) == CONST
2311 && GET_CODE (XEXP (x
, 0)) == PLUS
2312 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2319 legitimize_pic_address (orig
, mode
, reg
)
2321 enum machine_mode mode
;
2324 if (GET_CODE (orig
) == SYMBOL_REF
2325 || GET_CODE (orig
) == LABEL_REF
)
2327 #ifndef AOF_ASSEMBLER
2328 rtx pic_ref
, address
;
2338 reg
= gen_reg_rtx (Pmode
);
2343 #ifdef AOF_ASSEMBLER
2344 /* The AOF assembler can generate relocations for these directly, and
2345 understands that the PIC register has to be added into the offset. */
2346 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2349 address
= gen_reg_rtx (Pmode
);
2354 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2356 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2358 if ((GET_CODE (orig
) == LABEL_REF
2359 || (GET_CODE (orig
) == SYMBOL_REF
&&
2360 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig
, 0))))
2362 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2365 pic_ref
= gen_rtx_MEM (Pmode
,
2366 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2368 RTX_UNCHANGING_P (pic_ref
) = 1;
2371 insn
= emit_move_insn (reg
, pic_ref
);
2373 current_function_uses_pic_offset_table
= 1;
2374 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2376 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2380 else if (GET_CODE (orig
) == CONST
)
2384 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2385 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2393 reg
= gen_reg_rtx (Pmode
);
2396 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2398 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2399 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2400 base
== reg
? 0 : reg
);
2405 if (GET_CODE (offset
) == CONST_INT
)
2407 /* The base register doesn't really matter, we only want to
2408 test the index for the appropriate mode. */
2409 ARM_GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
2411 if (!no_new_pseudos
)
2412 offset
= force_reg (Pmode
, offset
);
2417 if (GET_CODE (offset
) == CONST_INT
)
2418 return plus_constant (base
, INTVAL (offset
));
2421 if (GET_MODE_SIZE (mode
) > 4
2422 && (GET_MODE_CLASS (mode
) == MODE_INT
2423 || TARGET_SOFT_FLOAT
))
2425 emit_insn (gen_addsi3 (reg
, base
, offset
));
2429 return gen_rtx_PLUS (Pmode
, base
, offset
);
2435 /* Generate code to load the PIC register. PROLOGUE is true if
2436 called from arm_expand_prologue (in which case we want the
2437 generated insns at the start of the function); false if called
2438 by an exception receiver that needs the PIC register reloaded
2439 (in which case the insns are just dumped at the current location). */
2442 arm_finalize_pic (prologue
)
2443 int prologue ATTRIBUTE_UNUSED
;
2445 #ifndef AOF_ASSEMBLER
2446 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2447 rtx global_offset_table
;
2449 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2456 l1
= gen_label_rtx ();
2458 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2459 /* On the ARM the PC register contains 'dot + 8' at the time of the
2460 addition, on the Thumb it is 'dot + 4'. */
2461 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2463 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2464 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2466 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2468 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2472 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2473 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2477 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2478 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2484 emit_insn_after (seq
, get_insns ());
2488 /* Need to emit this whether or not we obey regdecls,
2489 since setjmp/longjmp can cause life info to screw up. */
2490 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2491 #endif /* AOF_ASSEMBLER */
2494 #define REG_OR_SUBREG_REG(X) \
2495 (GET_CODE (X) == REG \
2496 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2498 #define REG_OR_SUBREG_RTX(X) \
2499 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2501 #ifndef COSTS_N_INSNS
2502 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2506 arm_rtx_costs (x
, code
, outer
)
2509 enum rtx_code outer
;
2511 enum machine_mode mode
= GET_MODE (x
);
2512 enum rtx_code subcode
;
2528 return COSTS_N_INSNS (1);
2531 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2534 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
2541 return COSTS_N_INSNS (2) + cycles
;
2543 return COSTS_N_INSNS (1) + 16;
2546 return (COSTS_N_INSNS (1)
2547 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
2548 + GET_CODE (SET_DEST (x
)) == MEM
));
2553 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2555 if (thumb_shiftable_const (INTVAL (x
)))
2556 return COSTS_N_INSNS (2);
2557 return COSTS_N_INSNS (3);
2559 else if (outer
== PLUS
2560 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
2562 else if (outer
== COMPARE
2563 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2565 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
2566 || outer
== LSHIFTRT
)
2568 return COSTS_N_INSNS (2);
2574 return COSTS_N_INSNS (3);
2593 /* XXX another guess. */
2594 /* Memory costs quite a lot for the first word, but subsequent words
2595 load at the equivalent of a single insn each. */
2596 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2597 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
2602 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2607 /* XXX still guessing. */
2608 switch (GET_MODE (XEXP (x
, 0)))
2611 return (1 + (mode
== DImode
? 4 : 0)
2612 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2615 return (4 + (mode
== DImode
? 4 : 0)
2616 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2619 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2633 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
2643 /* Memory costs quite a lot for the first word, but subsequent words
2644 load at the equivalent of a single insn each. */
2645 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2646 + (GET_CODE (x
) == SYMBOL_REF
2647 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
2654 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
2661 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
2663 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
2664 + ((GET_CODE (XEXP (x
, 0)) == REG
2665 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2666 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2668 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
2669 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2670 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2672 + ((GET_CODE (XEXP (x
, 1)) == REG
2673 || (GET_CODE (XEXP (x
, 1)) == SUBREG
2674 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
2675 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
2680 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
2681 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2682 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
2683 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
2686 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2687 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2688 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2689 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2691 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2692 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
2693 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
2696 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
2697 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
2698 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
2699 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
2700 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
2701 || subcode
== ROTATE
|| subcode
== ROTATERT
2703 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2704 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
2705 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
2706 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
2707 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
2708 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
2709 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
2714 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2715 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2716 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2717 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2718 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2722 case AND
: case XOR
: case IOR
:
2725 /* Normally the frame registers will be spilt into reg+const during
2726 reload, so it is a bad idea to combine them with other instructions,
2727 since then they might not be moved outside of loops. As a compromise
2728 we allow integration with ops that have a constant as their second
2730 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2731 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
2732 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2733 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
2734 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
2738 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2739 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2740 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2741 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2744 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
2745 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
2746 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2747 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2748 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2751 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
2752 return (1 + extra_cost
2753 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
2754 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
2755 || subcode
== ROTATE
|| subcode
== ROTATERT
2757 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2758 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
2759 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
2760 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
2761 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
2762 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
2768 /* There is no point basing this on the tuning, since it is always the
2769 fast variant if it exists at all. */
2770 if (arm_fast_multiply
&& mode
== DImode
2771 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
2772 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2773 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
2776 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2780 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2782 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
2783 & (unsigned HOST_WIDE_INT
) 0xffffffff);
2784 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
2787 /* Tune as appropriate. */
2788 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
2790 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
2792 i
>>= booth_unit_size
;
2799 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
2800 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
2801 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
2804 if (arm_fast_multiply
&& mode
== SImode
2805 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2806 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2807 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
2808 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
2809 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
2810 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
2815 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2816 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
2820 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2822 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2825 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2833 return 4 + (mode
== DImode
? 4 : 0);
2836 if (GET_MODE (XEXP (x
, 0)) == QImode
)
2837 return (4 + (mode
== DImode
? 4 : 0)
2838 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2841 switch (GET_MODE (XEXP (x
, 0)))
2844 return (1 + (mode
== DImode
? 4 : 0)
2845 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2848 return (4 + (mode
== DImode
? 4 : 0)
2849 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2852 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2860 if (const_ok_for_arm (INTVAL (x
)))
2861 return outer
== SET
? 2 : -1;
2862 else if (outer
== AND
2863 && const_ok_for_arm (~INTVAL (x
)))
2865 else if ((outer
== COMPARE
2866 || outer
== PLUS
|| outer
== MINUS
)
2867 && const_ok_for_arm (-INTVAL (x
)))
2878 if (const_double_rtx_ok_for_fpu (x
))
2879 return outer
== SET
? 2 : -1;
2880 else if ((outer
== COMPARE
|| outer
== PLUS
)
2881 && neg_const_double_rtx_ok_for_fpu (x
))
2891 arm_adjust_cost (insn
, link
, dep
, cost
)
2899 /* Some true dependencies can have a higher cost depending
2900 on precisely how certain input operands are used. */
2902 && REG_NOTE_KIND (link
) == 0
2903 && recog_memoized (insn
) < 0
2904 && recog_memoized (dep
) < 0)
2906 int shift_opnum
= get_attr_shift (insn
);
2907 enum attr_type attr_type
= get_attr_type (dep
);
2909 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2910 operand for INSN. If we have a shifted input operand and the
2911 instruction we depend on is another ALU instruction, then we may
2912 have to account for an additional stall. */
2913 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
2915 rtx shifted_operand
;
2918 /* Get the shifted operand. */
2919 extract_insn (insn
);
2920 shifted_operand
= recog_data
.operand
[shift_opnum
];
2922 /* Iterate over all the operands in DEP. If we write an operand
2923 that overlaps with SHIFTED_OPERAND, then we have increase the
2924 cost of this dependency. */
2926 preprocess_constraints ();
2927 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2929 /* We can ignore strict inputs. */
2930 if (recog_data
.operand_type
[opno
] == OP_IN
)
2933 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
2940 /* XXX This is not strictly true for the FPA. */
2941 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
2942 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
2945 /* Call insns don't incur a stall, even if they follow a load. */
2946 if (REG_NOTE_KIND (link
) == 0
2947 && GET_CODE (insn
) == CALL_INSN
)
2950 if ((i_pat
= single_set (insn
)) != NULL
2951 && GET_CODE (SET_SRC (i_pat
)) == MEM
2952 && (d_pat
= single_set (dep
)) != NULL
2953 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
2955 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
2956 /* This is a load after a store, there is no conflict if the load reads
2957 from a cached area. Assume that loads from the stack, and from the
2958 constant pool are cached, and that others will miss. This is a
2961 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
2962 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
2963 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
2964 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
2971 /* This code has been fixed for cross compilation. */
2973 static int fpa_consts_inited
= 0;
2975 static const char * const strings_fpa
[8] =
2978 "4", "5", "0.5", "10"
2981 static REAL_VALUE_TYPE values_fpa
[8];
2989 for (i
= 0; i
< 8; i
++)
2991 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
2995 fpa_consts_inited
= 1;
2998 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3001 const_double_rtx_ok_for_fpu (x
)
3007 if (!fpa_consts_inited
)
3010 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3011 if (REAL_VALUE_MINUS_ZERO (r
))
3014 for (i
= 0; i
< 8; i
++)
3015 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3021 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3024 neg_const_double_rtx_ok_for_fpu (x
)
3030 if (!fpa_consts_inited
)
3033 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3034 r
= REAL_VALUE_NEGATE (r
);
3035 if (REAL_VALUE_MINUS_ZERO (r
))
3038 for (i
= 0; i
< 8; i
++)
3039 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3045 /* Predicates for `match_operand' and `match_operator'. */
3047 /* s_register_operand is the same as register_operand, but it doesn't accept
3050 This function exists because at the time it was put in it led to better
3051 code. SUBREG(MEM) always needs a reload in the places where
3052 s_register_operand is used, and this seemed to lead to excessive
3056 s_register_operand (op
, mode
)
3058 enum machine_mode mode
;
3060 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3063 if (GET_CODE (op
) == SUBREG
)
3064 op
= SUBREG_REG (op
);
3066 /* We don't consider registers whose class is NO_REGS
3067 to be a register operand. */
3068 /* XXX might have to check for lo regs only for thumb ??? */
3069 return (GET_CODE (op
) == REG
3070 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3071 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3074 /* A hard register operand (even before reload. */
3077 arm_hard_register_operand (op
, mode
)
3079 enum machine_mode mode
;
3081 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3084 return (GET_CODE (op
) == REG
3085 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3088 /* Only accept reg, subreg(reg), const_int. */
3091 reg_or_int_operand (op
, mode
)
3093 enum machine_mode mode
;
3095 if (GET_CODE (op
) == CONST_INT
)
3098 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3101 if (GET_CODE (op
) == SUBREG
)
3102 op
= SUBREG_REG (op
);
3104 /* We don't consider registers whose class is NO_REGS
3105 to be a register operand. */
3106 return (GET_CODE (op
) == REG
3107 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3108 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3111 /* Return 1 if OP is an item in memory, given that we are in reload. */
3114 arm_reload_memory_operand (op
, mode
)
3116 enum machine_mode mode ATTRIBUTE_UNUSED
;
3118 int regno
= true_regnum (op
);
3120 return (!CONSTANT_P (op
)
3122 || (GET_CODE (op
) == REG
3123 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3126 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3127 memory access (architecture V4).
3128 MODE is QImode if called when computing constraints, or VOIDmode when
3129 emitting patterns. In this latter case we cannot use memory_operand()
3130 because it will fail on badly formed MEMs, which is precisly what we are
3134 bad_signed_byte_operand (op
, mode
)
3136 enum machine_mode mode ATTRIBUTE_UNUSED
;
3139 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3142 if (GET_CODE (op
) != MEM
)
3147 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3148 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3149 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3150 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3151 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3154 /* Big constants are also bad. */
3155 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3156 && (INTVAL (XEXP (op
, 1)) > 0xff
3157 || -INTVAL (XEXP (op
, 1)) > 0xff))
3160 /* Everything else is good, or can will automatically be made so. */
3164 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3167 arm_rhs_operand (op
, mode
)
3169 enum machine_mode mode
;
3171 return (s_register_operand (op
, mode
)
3172 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3175 /* Return TRUE for valid operands for the
3176 rhs of an ARM instruction, or a load. */
3179 arm_rhsm_operand (op
, mode
)
3181 enum machine_mode mode
;
3183 return (s_register_operand (op
, mode
)
3184 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3185 || memory_operand (op
, mode
));
3188 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3189 constant that is valid when negated. */
3192 arm_add_operand (op
, mode
)
3194 enum machine_mode mode
;
3197 return thumb_cmp_operand (op
, mode
);
3199 return (s_register_operand (op
, mode
)
3200 || (GET_CODE (op
) == CONST_INT
3201 && (const_ok_for_arm (INTVAL (op
))
3202 || const_ok_for_arm (-INTVAL (op
)))));
3206 arm_not_operand (op
, mode
)
3208 enum machine_mode mode
;
3210 return (s_register_operand (op
, mode
)
3211 || (GET_CODE (op
) == CONST_INT
3212 && (const_ok_for_arm (INTVAL (op
))
3213 || const_ok_for_arm (~INTVAL (op
)))));
3216 /* Return TRUE if the operand is a memory reference which contains an
3217 offsettable address. */
3220 offsettable_memory_operand (op
, mode
)
3222 enum machine_mode mode
;
3224 if (mode
== VOIDmode
)
3225 mode
= GET_MODE (op
);
3227 return (mode
== GET_MODE (op
)
3228 && GET_CODE (op
) == MEM
3229 && offsettable_address_p (reload_completed
| reload_in_progress
,
3230 mode
, XEXP (op
, 0)));
3233 /* Return TRUE if the operand is a memory reference which is, or can be
3234 made word aligned by adjusting the offset. */
3237 alignable_memory_operand (op
, mode
)
3239 enum machine_mode mode
;
3243 if (mode
== VOIDmode
)
3244 mode
= GET_MODE (op
);
3246 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3251 return ((GET_CODE (reg
= op
) == REG
3252 || (GET_CODE (op
) == SUBREG
3253 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3254 || (GET_CODE (op
) == PLUS
3255 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3256 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3257 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3258 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3259 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3262 /* Similar to s_register_operand, but does not allow hard integer
3266 f_register_operand (op
, mode
)
3268 enum machine_mode mode
;
3270 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3273 if (GET_CODE (op
) == SUBREG
)
3274 op
= SUBREG_REG (op
);
3276 /* We don't consider registers whose class is NO_REGS
3277 to be a register operand. */
3278 return (GET_CODE (op
) == REG
3279 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3280 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
3283 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3286 fpu_rhs_operand (op
, mode
)
3288 enum machine_mode mode
;
3290 if (s_register_operand (op
, mode
))
3293 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3296 if (GET_CODE (op
) == CONST_DOUBLE
)
3297 return const_double_rtx_ok_for_fpu (op
);
3303 fpu_add_operand (op
, mode
)
3305 enum machine_mode mode
;
3307 if (s_register_operand (op
, mode
))
3310 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3313 if (GET_CODE (op
) == CONST_DOUBLE
)
3314 return (const_double_rtx_ok_for_fpu (op
)
3315 || neg_const_double_rtx_ok_for_fpu (op
));
3320 /* Return nonzero if OP is a constant power of two. */
3323 power_of_two_operand (op
, mode
)
3325 enum machine_mode mode ATTRIBUTE_UNUSED
;
3327 if (GET_CODE (op
) == CONST_INT
)
3329 HOST_WIDE_INT value
= INTVAL (op
);
3331 return value
!= 0 && (value
& (value
- 1)) == 0;
3337 /* Return TRUE for a valid operand of a DImode operation.
3338 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3339 Note that this disallows MEM(REG+REG), but allows
3340 MEM(PRE/POST_INC/DEC(REG)). */
3343 di_operand (op
, mode
)
3345 enum machine_mode mode
;
3347 if (s_register_operand (op
, mode
))
3350 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3353 if (GET_CODE (op
) == SUBREG
)
3354 op
= SUBREG_REG (op
);
3356 switch (GET_CODE (op
))
3363 return memory_address_p (DImode
, XEXP (op
, 0));
3370 /* Like di_operand, but don't accept constants. */
3373 nonimmediate_di_operand (op
, mode
)
3375 enum machine_mode mode
;
3377 if (s_register_operand (op
, mode
))
3380 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3383 if (GET_CODE (op
) == SUBREG
)
3384 op
= SUBREG_REG (op
);
3386 if (GET_CODE (op
) == MEM
)
3387 return memory_address_p (DImode
, XEXP (op
, 0));
3392 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3393 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3394 Note that this disallows MEM(REG+REG), but allows
3395 MEM(PRE/POST_INC/DEC(REG)). */
3398 soft_df_operand (op
, mode
)
3400 enum machine_mode mode
;
3402 if (s_register_operand (op
, mode
))
3405 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3408 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
3411 if (GET_CODE (op
) == SUBREG
)
3412 op
= SUBREG_REG (op
);
3414 switch (GET_CODE (op
))
3420 return memory_address_p (DFmode
, XEXP (op
, 0));
3427 /* Like soft_df_operand, but don't accept constants. */
3430 nonimmediate_soft_df_operand (op
, mode
)
3432 enum machine_mode mode
;
3434 if (s_register_operand (op
, mode
))
3437 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3440 if (GET_CODE (op
) == SUBREG
)
3441 op
= SUBREG_REG (op
);
3443 if (GET_CODE (op
) == MEM
)
3444 return memory_address_p (DFmode
, XEXP (op
, 0));
3448 /* Return TRUE for valid index operands. */
3451 index_operand (op
, mode
)
3453 enum machine_mode mode
;
3455 return (s_register_operand (op
, mode
)
3456 || (immediate_operand (op
, mode
)
3457 && (GET_CODE (op
) != CONST_INT
3458 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
3461 /* Return TRUE for valid shifts by a constant. This also accepts any
3462 power of two on the (somewhat overly relaxed) assumption that the
3463 shift operator in this case was a mult. */
3466 const_shift_operand (op
, mode
)
3468 enum machine_mode mode
;
3470 return (power_of_two_operand (op
, mode
)
3471 || (immediate_operand (op
, mode
)
3472 && (GET_CODE (op
) != CONST_INT
3473 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
3476 /* Return TRUE for arithmetic operators which can be combined with a multiply
3480 shiftable_operator (x
, mode
)
3482 enum machine_mode mode
;
3486 if (GET_MODE (x
) != mode
)
3489 code
= GET_CODE (x
);
3491 return (code
== PLUS
|| code
== MINUS
3492 || code
== IOR
|| code
== XOR
|| code
== AND
);
3495 /* Return TRUE for binary logical operators. */
3498 logical_binary_operator (x
, mode
)
3500 enum machine_mode mode
;
3504 if (GET_MODE (x
) != mode
)
3507 code
= GET_CODE (x
);
3509 return (code
== IOR
|| code
== XOR
|| code
== AND
);
3512 /* Return TRUE for shift operators. */
3515 shift_operator (x
, mode
)
3517 enum machine_mode mode
;
3521 if (GET_MODE (x
) != mode
)
3524 code
= GET_CODE (x
);
3527 return power_of_two_operand (XEXP (x
, 1), mode
);
3529 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
3530 || code
== ROTATERT
);
3533 /* Return TRUE if x is EQ or NE. */
3536 equality_operator (x
, mode
)
3538 enum machine_mode mode ATTRIBUTE_UNUSED
;
3540 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
3543 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3546 arm_comparison_operator (x
, mode
)
3548 enum machine_mode mode
;
3550 return (comparison_operator (x
, mode
)
3551 && GET_CODE (x
) != LTGT
3552 && GET_CODE (x
) != UNEQ
);
3555 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3558 minmax_operator (x
, mode
)
3560 enum machine_mode mode
;
3562 enum rtx_code code
= GET_CODE (x
);
3564 if (GET_MODE (x
) != mode
)
3567 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
3570 /* Return TRUE if this is the condition code register, if we aren't given
3571 a mode, accept any class CCmode register. */
3574 cc_register (x
, mode
)
3576 enum machine_mode mode
;
3578 if (mode
== VOIDmode
)
3580 mode
= GET_MODE (x
);
3582 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3586 if ( GET_MODE (x
) == mode
3587 && GET_CODE (x
) == REG
3588 && REGNO (x
) == CC_REGNUM
)
3594 /* Return TRUE if this is the condition code register, if we aren't given
3595 a mode, accept any class CCmode register which indicates a dominance
3599 dominant_cc_register (x
, mode
)
3601 enum machine_mode mode
;
3603 if (mode
== VOIDmode
)
3605 mode
= GET_MODE (x
);
3607 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3611 if ( mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
3612 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
3613 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
3614 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
3615 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
3618 return cc_register (x
, mode
);
3621 /* Return TRUE if X references a SYMBOL_REF. */
3624 symbol_mentioned_p (x
)
3630 if (GET_CODE (x
) == SYMBOL_REF
)
3633 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3635 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3641 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3642 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
3645 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
3652 /* Return TRUE if X references a LABEL_REF. */
3655 label_mentioned_p (x
)
3661 if (GET_CODE (x
) == LABEL_REF
)
3664 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3665 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3671 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3672 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
3675 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
3686 enum rtx_code code
= GET_CODE (x
);
3690 else if (code
== SMIN
)
3692 else if (code
== UMIN
)
3694 else if (code
== UMAX
)
3700 /* Return 1 if memory locations are adjacent. */
3703 adjacent_mem_locations (a
, b
)
3706 if ((GET_CODE (XEXP (a
, 0)) == REG
3707 || (GET_CODE (XEXP (a
, 0)) == PLUS
3708 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
3709 && (GET_CODE (XEXP (b
, 0)) == REG
3710 || (GET_CODE (XEXP (b
, 0)) == PLUS
3711 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
3713 int val0
= 0, val1
= 0;
3716 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
3718 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
3719 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
3722 reg0
= REGNO (XEXP (a
, 0));
3724 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
3726 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
3727 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
3730 reg1
= REGNO (XEXP (b
, 0));
3732 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
3737 /* Return 1 if OP is a load multiple operation. It is known to be
3738 parallel and the first section will be tested. */
3741 load_multiple_operation (op
, mode
)
3743 enum machine_mode mode ATTRIBUTE_UNUSED
;
3745 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3748 HOST_WIDE_INT i
= 1, base
= 0;
3752 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3755 /* Check to see if this might be a write-back. */
3756 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3761 /* Now check it more carefully. */
3762 if (GET_CODE (SET_DEST (elt
)) != REG
3763 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3764 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3765 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3766 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3770 /* Perform a quick check so we don't blow up below. */
3772 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3773 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
3774 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
3777 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
3778 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
3780 for (; i
< count
; i
++)
3782 elt
= XVECEXP (op
, 0, i
);
3784 if (GET_CODE (elt
) != SET
3785 || GET_CODE (SET_DEST (elt
)) != REG
3786 || GET_MODE (SET_DEST (elt
)) != SImode
3787 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
3788 || GET_CODE (SET_SRC (elt
)) != MEM
3789 || GET_MODE (SET_SRC (elt
)) != SImode
3790 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
3791 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
3792 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
3793 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
3800 /* Return 1 if OP is a store multiple operation. It is known to be
3801 parallel and the first section will be tested. */
3804 store_multiple_operation (op
, mode
)
3806 enum machine_mode mode ATTRIBUTE_UNUSED
;
3808 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3811 HOST_WIDE_INT i
= 1, base
= 0;
3815 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3818 /* Check to see if this might be a write-back. */
3819 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3824 /* Now check it more carefully. */
3825 if (GET_CODE (SET_DEST (elt
)) != REG
3826 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3827 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3828 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3829 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3833 /* Perform a quick check so we don't blow up below. */
3835 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3836 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
3837 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
3840 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
3841 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
3843 for (; i
< count
; i
++)
3845 elt
= XVECEXP (op
, 0, i
);
3847 if (GET_CODE (elt
) != SET
3848 || GET_CODE (SET_SRC (elt
)) != REG
3849 || GET_MODE (SET_SRC (elt
)) != SImode
3850 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
3851 || GET_CODE (SET_DEST (elt
)) != MEM
3852 || GET_MODE (SET_DEST (elt
)) != SImode
3853 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
3854 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
3855 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
3856 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
3864 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
3869 HOST_WIDE_INT
* load_offset
;
3871 int unsorted_regs
[4];
3872 HOST_WIDE_INT unsorted_offsets
[4];
3877 /* Can only handle 2, 3, or 4 insns at present,
3878 though could be easily extended if required. */
3879 if (nops
< 2 || nops
> 4)
3882 /* Loop over the operands and check that the memory references are
3883 suitable (ie immediate offsets from the same base register). At
3884 the same time, extract the target register, and the memory
3886 for (i
= 0; i
< nops
; i
++)
3891 /* Convert a subreg of a mem into the mem itself. */
3892 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
3893 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
3895 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
3898 /* Don't reorder volatile memory references; it doesn't seem worth
3899 looking for the case where the order is ok anyway. */
3900 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
3903 offset
= const0_rtx
;
3905 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
3906 || (GET_CODE (reg
) == SUBREG
3907 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3908 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
3909 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
3911 || (GET_CODE (reg
) == SUBREG
3912 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3913 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
3918 base_reg
= REGNO (reg
);
3919 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
3920 ? REGNO (operands
[i
])
3921 : REGNO (SUBREG_REG (operands
[i
])));
3926 if (base_reg
!= (int) REGNO (reg
))
3927 /* Not addressed from the same base register. */
3930 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3931 ? REGNO (operands
[i
])
3932 : REGNO (SUBREG_REG (operands
[i
])));
3933 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3937 /* If it isn't an integer register, or if it overwrites the
3938 base register but isn't the last insn in the list, then
3939 we can't do this. */
3940 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
3941 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
3944 unsorted_offsets
[i
] = INTVAL (offset
);
3947 /* Not a suitable memory address. */
3951 /* All the useful information has now been extracted from the
3952 operands into unsorted_regs and unsorted_offsets; additionally,
3953 order[0] has been set to the lowest numbered register in the
3954 list. Sort the registers into order, and check that the memory
3955 offsets are ascending and adjacent. */
3957 for (i
= 1; i
< nops
; i
++)
3961 order
[i
] = order
[i
- 1];
3962 for (j
= 0; j
< nops
; j
++)
3963 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3964 && (order
[i
] == order
[i
- 1]
3965 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3968 /* Have we found a suitable register? if not, one must be used more
3970 if (order
[i
] == order
[i
- 1])
3973 /* Is the memory address adjacent and ascending? */
3974 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3982 for (i
= 0; i
< nops
; i
++)
3983 regs
[i
] = unsorted_regs
[order
[i
]];
3985 *load_offset
= unsorted_offsets
[order
[0]];
3988 if (unsorted_offsets
[order
[0]] == 0)
3989 return 1; /* ldmia */
3991 if (unsorted_offsets
[order
[0]] == 4)
3992 return 2; /* ldmib */
3994 if (unsorted_offsets
[order
[nops
- 1]] == 0)
3995 return 3; /* ldmda */
3997 if (unsorted_offsets
[order
[nops
- 1]] == -4)
3998 return 4; /* ldmdb */
4000 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4001 if the offset isn't small enough. The reason 2 ldrs are faster
4002 is because these ARMs are able to do more than one cache access
4003 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4004 whilst the ARM8 has a double bandwidth cache. This means that
4005 these cores can do both an instruction fetch and a data fetch in
4006 a single cycle, so the trick of calculating the address into a
4007 scratch register (one of the result regs) and then doing a load
4008 multiple actually becomes slower (and no smaller in code size).
4009 That is the transformation
4011 ldr rd1, [rbase + offset]
4012 ldr rd2, [rbase + offset + 4]
4016 add rd1, rbase, offset
4017 ldmia rd1, {rd1, rd2}
4019 produces worse code -- '3 cycles + any stalls on rd2' instead of
4020 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4021 access per cycle, the first sequence could never complete in less
4022 than 6 cycles, whereas the ldm sequence would only take 5 and
4023 would make better use of sequential accesses if not hitting the
4026 We cheat here and test 'arm_ld_sched' which we currently know to
4027 only be true for the ARM8, ARM9 and StrongARM. If this ever
4028 changes, then the test below needs to be reworked. */
4029 if (nops
== 2 && arm_ld_sched
)
4032 /* Can't do it without setting up the offset, only do this if it takes
4033 no more than one insn. */
4034 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4035 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4039 emit_ldm_seq (operands
, nops
)
4045 HOST_WIDE_INT offset
;
4049 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4052 strcpy (buf
, "ldm%?ia\t");
4056 strcpy (buf
, "ldm%?ib\t");
4060 strcpy (buf
, "ldm%?da\t");
4064 strcpy (buf
, "ldm%?db\t");
4069 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4070 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4073 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4074 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4076 output_asm_insn (buf
, operands
);
4078 strcpy (buf
, "ldm%?ia\t");
4085 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4086 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4088 for (i
= 1; i
< nops
; i
++)
4089 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4090 reg_names
[regs
[i
]]);
4092 strcat (buf
, "}\t%@ phole ldm");
4094 output_asm_insn (buf
, operands
);
4099 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4104 HOST_WIDE_INT
* load_offset
;
4106 int unsorted_regs
[4];
4107 HOST_WIDE_INT unsorted_offsets
[4];
4112 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4113 extended if required. */
4114 if (nops
< 2 || nops
> 4)
4117 /* Loop over the operands and check that the memory references are
4118 suitable (ie immediate offsets from the same base register). At
4119 the same time, extract the target register, and the memory
4121 for (i
= 0; i
< nops
; i
++)
4126 /* Convert a subreg of a mem into the mem itself. */
4127 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4128 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4130 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4133 /* Don't reorder volatile memory references; it doesn't seem worth
4134 looking for the case where the order is ok anyway. */
4135 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4138 offset
= const0_rtx
;
4140 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4141 || (GET_CODE (reg
) == SUBREG
4142 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4143 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4144 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4146 || (GET_CODE (reg
) == SUBREG
4147 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4148 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4153 base_reg
= REGNO (reg
);
4154 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4155 ? REGNO (operands
[i
])
4156 : REGNO (SUBREG_REG (operands
[i
])));
4161 if (base_reg
!= (int) REGNO (reg
))
4162 /* Not addressed from the same base register. */
4165 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4166 ? REGNO (operands
[i
])
4167 : REGNO (SUBREG_REG (operands
[i
])));
4168 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4172 /* If it isn't an integer register, then we can't do this. */
4173 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4176 unsorted_offsets
[i
] = INTVAL (offset
);
4179 /* Not a suitable memory address. */
4183 /* All the useful information has now been extracted from the
4184 operands into unsorted_regs and unsorted_offsets; additionally,
4185 order[0] has been set to the lowest numbered register in the
4186 list. Sort the registers into order, and check that the memory
4187 offsets are ascending and adjacent. */
4189 for (i
= 1; i
< nops
; i
++)
4193 order
[i
] = order
[i
- 1];
4194 for (j
= 0; j
< nops
; j
++)
4195 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4196 && (order
[i
] == order
[i
- 1]
4197 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4200 /* Have we found a suitable register? if not, one must be used more
4202 if (order
[i
] == order
[i
- 1])
4205 /* Is the memory address adjacent and ascending? */
4206 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4214 for (i
= 0; i
< nops
; i
++)
4215 regs
[i
] = unsorted_regs
[order
[i
]];
4217 *load_offset
= unsorted_offsets
[order
[0]];
4220 if (unsorted_offsets
[order
[0]] == 0)
4221 return 1; /* stmia */
4223 if (unsorted_offsets
[order
[0]] == 4)
4224 return 2; /* stmib */
4226 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4227 return 3; /* stmda */
4229 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4230 return 4; /* stmdb */
4236 emit_stm_seq (operands
, nops
)
4242 HOST_WIDE_INT offset
;
4246 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4249 strcpy (buf
, "stm%?ia\t");
4253 strcpy (buf
, "stm%?ib\t");
4257 strcpy (buf
, "stm%?da\t");
4261 strcpy (buf
, "stm%?db\t");
4268 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4269 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4271 for (i
= 1; i
< nops
; i
++)
4272 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4273 reg_names
[regs
[i
]]);
4275 strcat (buf
, "}\t%@ phole stm");
4277 output_asm_insn (buf
, operands
);
4282 multi_register_push (op
, mode
)
4284 enum machine_mode mode ATTRIBUTE_UNUSED
;
4286 if (GET_CODE (op
) != PARALLEL
4287 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4288 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
4289 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
4295 /* Routines for use in generating RTL. */
4298 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
4299 in_struct_p
, scalar_p
)
4311 int sign
= up
? 1 : -1;
4314 /* XScale has load-store double instructions, but they have stricter
4315 alignment requirements than load-store multiple, so we can not
4318 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4319 the pipeline until completion.
4327 An ldr instruction takes 1-3 cycles, but does not block the
4336 Best case ldr will always win. However, the more ldr instructions
4337 we issue, the less likely we are to be able to schedule them well.
4338 Using ldr instructions also increases code size.
4340 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4341 for counts of 3 or 4 regs. */
4342 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4348 for (i
= 0; i
< count
; i
++)
4350 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
4351 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4352 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4353 MEM_SCALAR_P (mem
) = scalar_p
;
4354 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
4358 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
4366 result
= gen_rtx_PARALLEL (VOIDmode
,
4367 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4370 XVECEXP (result
, 0, 0)
4371 = gen_rtx_SET (GET_MODE (from
), from
,
4372 plus_constant (from
, count
* 4 * sign
));
4377 for (j
= 0; i
< count
; i
++, j
++)
4379 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
4380 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4381 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4382 MEM_SCALAR_P (mem
) = scalar_p
;
4383 XVECEXP (result
, 0, i
)
4384 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
4391 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
4392 in_struct_p
, scalar_p
)
4404 int sign
= up
? 1 : -1;
4407 /* See arm_gen_load_multiple for discussion of
4408 the pros/cons of ldm/stm usage for XScale. */
4409 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4415 for (i
= 0; i
< count
; i
++)
4417 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
4418 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4419 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4420 MEM_SCALAR_P (mem
) = scalar_p
;
4421 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
4425 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
4433 result
= gen_rtx_PARALLEL (VOIDmode
,
4434 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4437 XVECEXP (result
, 0, 0)
4438 = gen_rtx_SET (GET_MODE (to
), to
,
4439 plus_constant (to
, count
* 4 * sign
));
4444 for (j
= 0; i
< count
; i
++, j
++)
4446 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
4447 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4448 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4449 MEM_SCALAR_P (mem
) = scalar_p
;
4451 XVECEXP (result
, 0, i
)
4452 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
4459 arm_gen_movstrqi (operands
)
4462 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
4465 rtx st_src
, st_dst
, fin_src
, fin_dst
;
4466 rtx part_bytes_reg
= NULL
;
4468 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
4469 int dst_scalar_p
, src_scalar_p
;
4471 if (GET_CODE (operands
[2]) != CONST_INT
4472 || GET_CODE (operands
[3]) != CONST_INT
4473 || INTVAL (operands
[2]) > 64
4474 || INTVAL (operands
[3]) & 3)
4477 st_dst
= XEXP (operands
[0], 0);
4478 st_src
= XEXP (operands
[1], 0);
4480 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
4481 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
4482 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
4483 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
4484 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
4485 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
4487 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
4488 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
4490 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
4491 out_words_to_go
= INTVAL (operands
[2]) / 4;
4492 last_bytes
= INTVAL (operands
[2]) & 3;
4494 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
4495 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
4497 for (i
= 0; in_words_to_go
>= 2; i
+=4)
4499 if (in_words_to_go
> 4)
4500 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
4505 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
4506 FALSE
, src_unchanging_p
,
4507 src_in_struct_p
, src_scalar_p
));
4509 if (out_words_to_go
)
4511 if (out_words_to_go
> 4)
4512 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
4516 else if (out_words_to_go
!= 1)
4517 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
4526 mem
= gen_rtx_MEM (SImode
, dst
);
4527 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4528 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4529 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4530 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
4531 if (last_bytes
!= 0)
4532 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
4536 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
4537 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
4540 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4541 if (out_words_to_go
)
4545 mem
= gen_rtx_MEM (SImode
, src
);
4546 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4547 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4548 MEM_SCALAR_P (mem
) = src_scalar_p
;
4549 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
4550 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
4552 mem
= gen_rtx_MEM (SImode
, dst
);
4553 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4554 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4555 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4556 emit_move_insn (mem
, sreg
);
4557 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
4560 if (in_words_to_go
) /* Sanity check */
4566 if (in_words_to_go
< 0)
4569 mem
= gen_rtx_MEM (SImode
, src
);
4570 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4571 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4572 MEM_SCALAR_P (mem
) = src_scalar_p
;
4573 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
4576 if (last_bytes
&& part_bytes_reg
== NULL
)
4579 if (BYTES_BIG_ENDIAN
&& last_bytes
)
4581 rtx tmp
= gen_reg_rtx (SImode
);
4583 /* The bytes we want are in the top end of the word. */
4584 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
4585 GEN_INT (8 * (4 - last_bytes
))));
4586 part_bytes_reg
= tmp
;
4590 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
4591 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4592 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4593 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4594 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4598 tmp
= gen_reg_rtx (SImode
);
4599 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
4600 part_bytes_reg
= tmp
;
4609 mem
= gen_rtx_MEM (HImode
, dst
);
4610 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4611 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4612 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4613 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
4617 rtx tmp
= gen_reg_rtx (SImode
);
4619 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
4620 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
4621 part_bytes_reg
= tmp
;
4627 mem
= gen_rtx_MEM (QImode
, dst
);
4628 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4629 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4630 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4631 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4638 /* Generate a memory reference for a half word, such that it will be loaded
4639 into the top 16 bits of the word. We can assume that the address is
4640 known to be alignable and of the form reg, or plus (reg, const). */
4643 arm_gen_rotated_half_load (memref
)
4646 HOST_WIDE_INT offset
= 0;
4647 rtx base
= XEXP (memref
, 0);
4649 if (GET_CODE (base
) == PLUS
)
4651 offset
= INTVAL (XEXP (base
, 1));
4652 base
= XEXP (base
, 0);
4655 /* If we aren't allowed to generate unaligned addresses, then fail. */
4656 if (TARGET_MMU_TRAPS
4657 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
4660 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
4662 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
4665 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
4668 /* Select a dominance comparison mode if possible. We support three forms.
4669 COND_OR == 0 => (X && Y)
4670 COND_OR == 1 => ((! X( || Y)
4671 COND_OR == 2 => (X || Y)
4672 If we are unable to support a dominance comparsison we return CC mode.
4673 This will then fail to match for the RTL expressions that generate this
4676 static enum machine_mode
4677 select_dominance_cc_mode (x
, y
, cond_or
)
4680 HOST_WIDE_INT cond_or
;
4682 enum rtx_code cond1
, cond2
;
4685 /* Currently we will probably get the wrong result if the individual
4686 comparisons are not simple. This also ensures that it is safe to
4687 reverse a comparison if necessary. */
4688 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
4690 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
4694 /* The if_then_else variant of this tests the second condition if the
4695 first passes, but is true if the first fails. Reverse the first
4696 condition to get a true "inclusive-or" expression. */
4698 cond1
= reverse_condition (cond1
);
4700 /* If the comparisons are not equal, and one doesn't dominate the other,
4701 then we can't do this. */
4703 && !comparison_dominates_p (cond1
, cond2
)
4704 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
4709 enum rtx_code temp
= cond1
;
4717 if (cond2
== EQ
|| !cond_or
)
4722 case LE
: return CC_DLEmode
;
4723 case LEU
: return CC_DLEUmode
;
4724 case GE
: return CC_DGEmode
;
4725 case GEU
: return CC_DGEUmode
;
4732 if (cond2
== LT
|| !cond_or
)
4741 if (cond2
== GT
|| !cond_or
)
4750 if (cond2
== LTU
|| !cond_or
)
4759 if (cond2
== GTU
|| !cond_or
)
4767 /* The remaining cases only occur when both comparisons are the
4792 arm_select_cc_mode (op
, x
, y
)
4797 /* All floating point compares return CCFP if it is an equality
4798 comparison, and CCFPE otherwise. */
4799 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4826 /* A compare with a shifted operand. Because of canonicalization, the
4827 comparison will have to be swapped when we emit the assembler. */
4828 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
4829 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4830 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
4831 || GET_CODE (x
) == ROTATERT
))
4834 /* This is a special case that is used by combine to allow a
4835 comparison of a shifted byte load to be split into a zero-extend
4836 followed by a comparison of the shifted integer (only valid for
4837 equalities and unsigned inequalities). */
4838 if (GET_MODE (x
) == SImode
4839 && GET_CODE (x
) == ASHIFT
4840 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
4841 && GET_CODE (XEXP (x
, 0)) == SUBREG
4842 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
4843 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
4844 && (op
== EQ
|| op
== NE
4845 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
4846 && GET_CODE (y
) == CONST_INT
)
4849 /* A construct for a conditional compare, if the false arm contains
4850 0, then both conditions must be true, otherwise either condition
4851 must be true. Not all conditions are possible, so CCmode is
4852 returned if it can't be done. */
4853 if (GET_CODE (x
) == IF_THEN_ELSE
4854 && (XEXP (x
, 2) == const0_rtx
4855 || XEXP (x
, 2) == const1_rtx
)
4856 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4857 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4858 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
4859 INTVAL (XEXP (x
, 2)));
4861 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4862 if (GET_CODE (x
) == AND
4863 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4864 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4865 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 0);
4867 if (GET_CODE (x
) == IOR
4868 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4869 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4870 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 2);
4872 /* An operation that sets the condition codes as a side-effect, the
4873 V flag is not set correctly, so we can only use comparisons where
4874 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4876 if (GET_MODE (x
) == SImode
4878 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
4879 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
4880 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
4881 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
4882 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
4883 || GET_CODE (x
) == LSHIFTRT
4884 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4885 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
4888 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
4891 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
4892 && GET_CODE (x
) == PLUS
4893 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
4899 /* X and Y are two things to compare using CODE. Emit the compare insn and
4900 return the rtx for register 0 in the proper mode. FP means this is a
4901 floating point compare: I don't think that it is needed on the arm. */
4904 arm_gen_compare_reg (code
, x
, y
)
4908 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
4909 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
4911 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4912 gen_rtx_COMPARE (mode
, x
, y
)));
4917 /* Generate a sequence of insns that will generate the correct return
4918 address mask depending on the physical architecture that the program
4922 arm_gen_return_addr_mask ()
4924 rtx reg
= gen_reg_rtx (Pmode
);
4926 emit_insn (gen_return_addr_mask (reg
));
4931 arm_reload_in_hi (operands
)
4934 rtx ref
= operands
[1];
4936 HOST_WIDE_INT offset
= 0;
4938 if (GET_CODE (ref
) == SUBREG
)
4940 offset
= SUBREG_BYTE (ref
);
4941 ref
= SUBREG_REG (ref
);
4944 if (GET_CODE (ref
) == REG
)
4946 /* We have a pseudo which has been spilt onto the stack; there
4947 are two cases here: the first where there is a simple
4948 stack-slot replacement and a second where the stack-slot is
4949 out of range, or is used as a subreg. */
4950 if (reg_equiv_mem
[REGNO (ref
)])
4952 ref
= reg_equiv_mem
[REGNO (ref
)];
4953 base
= find_replacement (&XEXP (ref
, 0));
4956 /* The slot is out of range, or was dressed up in a SUBREG. */
4957 base
= reg_equiv_address
[REGNO (ref
)];
4960 base
= find_replacement (&XEXP (ref
, 0));
4962 /* Handle the case where the address is too complex to be offset by 1. */
4963 if (GET_CODE (base
) == MINUS
4964 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4966 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4968 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
4971 else if (GET_CODE (base
) == PLUS
)
4973 /* The addend must be CONST_INT, or we would have dealt with it above. */
4974 HOST_WIDE_INT hi
, lo
;
4976 offset
+= INTVAL (XEXP (base
, 1));
4977 base
= XEXP (base
, 0);
4979 /* Rework the address into a legal sequence of insns. */
4980 /* Valid range for lo is -4095 -> 4095 */
4983 : -((-offset
) & 0xfff));
4985 /* Corner case, if lo is the max offset then we would be out of range
4986 once we have added the additional 1 below, so bump the msb into the
4987 pre-loading insn(s). */
4991 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
4992 ^ (HOST_WIDE_INT
) 0x80000000)
4993 - (HOST_WIDE_INT
) 0x80000000);
4995 if (hi
+ lo
!= offset
)
5000 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5002 /* Get the base address; addsi3 knows how to handle constants
5003 that require more than one insn. */
5004 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5010 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5011 emit_insn (gen_zero_extendqisi2 (scratch
,
5012 gen_rtx_MEM (QImode
,
5013 plus_constant (base
,
5015 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5016 gen_rtx_MEM (QImode
,
5017 plus_constant (base
,
5019 if (!BYTES_BIG_ENDIAN
)
5020 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5021 gen_rtx_IOR (SImode
,
5024 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5028 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5029 gen_rtx_IOR (SImode
,
5030 gen_rtx_ASHIFT (SImode
, scratch
,
5032 gen_rtx_SUBREG (SImode
, operands
[0],
5036 /* Handle storing a half-word to memory during reload by synthesising as two
5037 byte stores. Take care not to clobber the input values until after we
5038 have moved them somewhere safe. This code assumes that if the DImode
5039 scratch in operands[2] overlaps either the input value or output address
5040 in some way, then that value must die in this insn (we absolutely need
5041 two scratch registers for some corner cases). */
5044 arm_reload_out_hi (operands
)
5047 rtx ref
= operands
[0];
5048 rtx outval
= operands
[1];
5050 HOST_WIDE_INT offset
= 0;
5052 if (GET_CODE (ref
) == SUBREG
)
5054 offset
= SUBREG_BYTE (ref
);
5055 ref
= SUBREG_REG (ref
);
5058 if (GET_CODE (ref
) == REG
)
5060 /* We have a pseudo which has been spilt onto the stack; there
5061 are two cases here: the first where there is a simple
5062 stack-slot replacement and a second where the stack-slot is
5063 out of range, or is used as a subreg. */
5064 if (reg_equiv_mem
[REGNO (ref
)])
5066 ref
= reg_equiv_mem
[REGNO (ref
)];
5067 base
= find_replacement (&XEXP (ref
, 0));
5070 /* The slot is out of range, or was dressed up in a SUBREG. */
5071 base
= reg_equiv_address
[REGNO (ref
)];
5074 base
= find_replacement (&XEXP (ref
, 0));
5076 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5078 /* Handle the case where the address is too complex to be offset by 1. */
5079 if (GET_CODE (base
) == MINUS
5080 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5082 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5084 /* Be careful not to destroy OUTVAL. */
5085 if (reg_overlap_mentioned_p (base_plus
, outval
))
5087 /* Updating base_plus might destroy outval, see if we can
5088 swap the scratch and base_plus. */
5089 if (!reg_overlap_mentioned_p (scratch
, outval
))
5092 scratch
= base_plus
;
5097 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5099 /* Be conservative and copy OUTVAL into the scratch now,
5100 this should only be necessary if outval is a subreg
5101 of something larger than a word. */
5102 /* XXX Might this clobber base? I can't see how it can,
5103 since scratch is known to overlap with OUTVAL, and
5104 must be wider than a word. */
5105 emit_insn (gen_movhi (scratch_hi
, outval
));
5106 outval
= scratch_hi
;
5110 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5113 else if (GET_CODE (base
) == PLUS
)
5115 /* The addend must be CONST_INT, or we would have dealt with it above. */
5116 HOST_WIDE_INT hi
, lo
;
5118 offset
+= INTVAL (XEXP (base
, 1));
5119 base
= XEXP (base
, 0);
5121 /* Rework the address into a legal sequence of insns. */
5122 /* Valid range for lo is -4095 -> 4095 */
5125 : -((-offset
) & 0xfff));
5127 /* Corner case, if lo is the max offset then we would be out of range
5128 once we have added the additional 1 below, so bump the msb into the
5129 pre-loading insn(s). */
5133 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5134 ^ (HOST_WIDE_INT
) 0x80000000)
5135 - (HOST_WIDE_INT
) 0x80000000);
5137 if (hi
+ lo
!= offset
)
5142 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5144 /* Be careful not to destroy OUTVAL. */
5145 if (reg_overlap_mentioned_p (base_plus
, outval
))
5147 /* Updating base_plus might destroy outval, see if we
5148 can swap the scratch and base_plus. */
5149 if (!reg_overlap_mentioned_p (scratch
, outval
))
5152 scratch
= base_plus
;
5157 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5159 /* Be conservative and copy outval into scratch now,
5160 this should only be necessary if outval is a
5161 subreg of something larger than a word. */
5162 /* XXX Might this clobber base? I can't see how it
5163 can, since scratch is known to overlap with
5165 emit_insn (gen_movhi (scratch_hi
, outval
));
5166 outval
= scratch_hi
;
5170 /* Get the base address; addsi3 knows how to handle constants
5171 that require more than one insn. */
5172 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5178 if (BYTES_BIG_ENDIAN
)
5180 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5181 plus_constant (base
, offset
+ 1)),
5182 gen_lowpart (QImode
, outval
)));
5183 emit_insn (gen_lshrsi3 (scratch
,
5184 gen_rtx_SUBREG (SImode
, outval
, 0),
5186 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5187 gen_lowpart (QImode
, scratch
)));
5191 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5192 gen_lowpart (QImode
, outval
)));
5193 emit_insn (gen_lshrsi3 (scratch
,
5194 gen_rtx_SUBREG (SImode
, outval
, 0),
5196 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5197 plus_constant (base
, offset
+ 1)),
5198 gen_lowpart (QImode
, scratch
)));
5202 /* Print a symbolic form of X to the debug file, F. */
5205 arm_print_value (f
, x
)
5209 switch (GET_CODE (x
))
5212 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5216 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5220 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5224 fprintf (f
, "`%s'", XSTR (x
, 0));
5228 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5232 arm_print_value (f
, XEXP (x
, 0));
5236 arm_print_value (f
, XEXP (x
, 0));
5238 arm_print_value (f
, XEXP (x
, 1));
5246 fprintf (f
, "????");
5251 /* Routines for manipulation of the constant pool. */
5253 /* Arm instructions cannot load a large constant directly into a
5254 register; they have to come from a pc relative load. The constant
5255 must therefore be placed in the addressable range of the pc
5256 relative load. Depending on the precise pc relative load
5257 instruction the range is somewhere between 256 bytes and 4k. This
5258 means that we often have to dump a constant inside a function, and
5259 generate code to branch around it.
5261 It is important to minimize this, since the branches will slow
5262 things down and make the code larger.
5264 Normally we can hide the table after an existing unconditional
5265 branch so that there is no interruption of the flow, but in the
5266 worst case the code looks like this:
5284 We fix this by performing a scan after scheduling, which notices
5285 which instructions need to have their operands fetched from the
5286 constant table and builds the table.
5288 The algorithm starts by building a table of all the constants that
5289 need fixing up and all the natural barriers in the function (places
5290 where a constant table can be dropped without breaking the flow).
5291 For each fixup we note how far the pc-relative replacement will be
5292 able to reach and the offset of the instruction into the function.
5294 Having built the table we then group the fixes together to form
5295 tables that are as large as possible (subject to addressing
5296 constraints) and emit each table of constants after the last
5297 barrier that is within range of all the instructions in the group.
5298 If a group does not contain a barrier, then we forcibly create one
5299 by inserting a jump instruction into the flow. Once the table has
5300 been inserted, the insns are then modified to reference the
5301 relevant entry in the pool.
5303 Possible enhancements to the algorithm (not implemented) are:
5305 1) For some processors and object formats, there may be benefit in
5306 aligning the pools to the start of cache lines; this alignment
5307 would need to be taken into account when calculating addressability
5310 /* These typedefs are located at the start of this file, so that
5311 they can be used in the prototypes there. This comment is to
5312 remind readers of that fact so that the following structures
5313 can be understood more easily.
5315 typedef struct minipool_node Mnode;
5316 typedef struct minipool_fixup Mfix; */
5318 struct minipool_node
5320 /* Doubly linked chain of entries. */
5323 /* The maximum offset into the code that this entry can be placed. While
5324 pushing fixes for forward references, all entries are sorted in order
5325 of increasing max_address. */
5326 HOST_WIDE_INT max_address
;
5327 /* Similarly for an entry inserted for a backwards ref. */
5328 HOST_WIDE_INT min_address
;
5329 /* The number of fixes referencing this entry. This can become zero
5330 if we "unpush" an entry. In this case we ignore the entry when we
5331 come to emit the code. */
5333 /* The offset from the start of the minipool. */
5334 HOST_WIDE_INT offset
;
5335 /* The value in table. */
5337 /* The mode of value. */
5338 enum machine_mode mode
;
5342 struct minipool_fixup
5346 HOST_WIDE_INT address
;
5348 enum machine_mode mode
;
5352 HOST_WIDE_INT forwards
;
5353 HOST_WIDE_INT backwards
;
5356 /* Fixes less than a word need padding out to a word boundary. */
5357 #define MINIPOOL_FIX_SIZE(mode) \
5358 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5360 static Mnode
* minipool_vector_head
;
5361 static Mnode
* minipool_vector_tail
;
5362 static rtx minipool_vector_label
;
5364 /* The linked list of all minipool fixes required for this function. */
5365 Mfix
* minipool_fix_head
;
5366 Mfix
* minipool_fix_tail
;
5367 /* The fix entry for the current minipool, once it has been placed. */
5368 Mfix
* minipool_barrier
;
5370 /* Determines if INSN is the start of a jump table. Returns the end
5371 of the TABLE or NULL_RTX. */
5374 is_jump_table (insn
)
5379 if (GET_CODE (insn
) == JUMP_INSN
5380 && JUMP_LABEL (insn
) != NULL
5381 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
5382 == next_real_insn (insn
))
5384 && GET_CODE (table
) == JUMP_INSN
5385 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
5386 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
5392 #ifndef JUMP_TABLES_IN_TEXT_SECTION
5393 #define JUMP_TABLES_IN_TEXT_SECTION 0
5396 static HOST_WIDE_INT
5397 get_jump_table_size (insn
)
5400 /* ADDR_VECs only take room if read-only data does into the text
5402 if (JUMP_TABLES_IN_TEXT_SECTION
5403 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
5408 rtx body
= PATTERN (insn
);
5409 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
5411 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
5417 /* Move a minipool fix MP from its current location to before MAX_MP.
5418 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5419 contrains may need updating. */
5422 move_minipool_fix_forward_ref (mp
, max_mp
, max_address
)
5425 HOST_WIDE_INT max_address
;
5427 /* This should never be true and the code below assumes these are
5434 if (max_address
< mp
->max_address
)
5435 mp
->max_address
= max_address
;
5439 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5440 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5442 mp
->max_address
= max_address
;
5444 /* Unlink MP from its current position. Since max_mp is non-null,
5445 mp->prev must be non-null. */
5446 mp
->prev
->next
= mp
->next
;
5447 if (mp
->next
!= NULL
)
5448 mp
->next
->prev
= mp
->prev
;
5450 minipool_vector_tail
= mp
->prev
;
5452 /* Re-insert it before MAX_MP. */
5454 mp
->prev
= max_mp
->prev
;
5457 if (mp
->prev
!= NULL
)
5458 mp
->prev
->next
= mp
;
5460 minipool_vector_head
= mp
;
5463 /* Save the new entry. */
5466 /* Scan over the preceding entries and adjust their addresses as
5468 while (mp
->prev
!= NULL
5469 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5471 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5478 /* Add a constant to the minipool for a forward reference. Returns the
5479 node added or NULL if the constant will not fit in this pool. */
5482 add_minipool_forward_ref (fix
)
5485 /* If set, max_mp is the first pool_entry that has a lower
5486 constraint than the one we are trying to add. */
5487 Mnode
* max_mp
= NULL
;
5488 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
5491 /* If this fix's address is greater than the address of the first
5492 entry, then we can't put the fix in this pool. We subtract the
5493 size of the current fix to ensure that if the table is fully
5494 packed we still have enough room to insert this value by suffling
5495 the other fixes forwards. */
5496 if (minipool_vector_head
&&
5497 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
5500 /* Scan the pool to see if a constant with the same value has
5501 already been added. While we are doing this, also note the
5502 location where we must insert the constant if it doesn't already
5504 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5506 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5507 && fix
->mode
== mp
->mode
5508 && (GET_CODE (fix
->value
) != CODE_LABEL
5509 || (CODE_LABEL_NUMBER (fix
->value
)
5510 == CODE_LABEL_NUMBER (mp
->value
)))
5511 && rtx_equal_p (fix
->value
, mp
->value
))
5513 /* More than one fix references this entry. */
5515 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
5518 /* Note the insertion point if necessary. */
5520 && mp
->max_address
> max_address
)
5524 /* The value is not currently in the minipool, so we need to create
5525 a new entry for it. If MAX_MP is NULL, the entry will be put on
5526 the end of the list since the placement is less constrained than
5527 any existing entry. Otherwise, we insert the new fix before
5528 MAX_MP and, if neceesary, adjust the constraints on the other
5530 mp
= xmalloc (sizeof (* mp
));
5531 mp
->fix_size
= fix
->fix_size
;
5532 mp
->mode
= fix
->mode
;
5533 mp
->value
= fix
->value
;
5535 /* Not yet required for a backwards ref. */
5536 mp
->min_address
= -65536;
5540 mp
->max_address
= max_address
;
5542 mp
->prev
= minipool_vector_tail
;
5544 if (mp
->prev
== NULL
)
5546 minipool_vector_head
= mp
;
5547 minipool_vector_label
= gen_label_rtx ();
5550 mp
->prev
->next
= mp
;
5552 minipool_vector_tail
= mp
;
5556 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5557 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5559 mp
->max_address
= max_address
;
5562 mp
->prev
= max_mp
->prev
;
5564 if (mp
->prev
!= NULL
)
5565 mp
->prev
->next
= mp
;
5567 minipool_vector_head
= mp
;
5570 /* Save the new entry. */
5573 /* Scan over the preceding entries and adjust their addresses as
5575 while (mp
->prev
!= NULL
5576 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5578 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5586 move_minipool_fix_backward_ref (mp
, min_mp
, min_address
)
5589 HOST_WIDE_INT min_address
;
5591 HOST_WIDE_INT offset
;
5593 /* This should never be true, and the code below assumes these are
5600 if (min_address
> mp
->min_address
)
5601 mp
->min_address
= min_address
;
5605 /* We will adjust this below if it is too loose. */
5606 mp
->min_address
= min_address
;
5608 /* Unlink MP from its current position. Since min_mp is non-null,
5609 mp->next must be non-null. */
5610 mp
->next
->prev
= mp
->prev
;
5611 if (mp
->prev
!= NULL
)
5612 mp
->prev
->next
= mp
->next
;
5614 minipool_vector_head
= mp
->next
;
5616 /* Reinsert it after MIN_MP. */
5618 mp
->next
= min_mp
->next
;
5620 if (mp
->next
!= NULL
)
5621 mp
->next
->prev
= mp
;
5623 minipool_vector_tail
= mp
;
5629 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5631 mp
->offset
= offset
;
5632 if (mp
->refcount
> 0)
5633 offset
+= mp
->fix_size
;
5635 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5636 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5642 /* Add a constant to the minipool for a backward reference. Returns the
5643 node added or NULL if the constant will not fit in this pool.
5645 Note that the code for insertion for a backwards reference can be
5646 somewhat confusing because the calculated offsets for each fix do
5647 not take into account the size of the pool (which is still under
5651 add_minipool_backward_ref (fix
)
5654 /* If set, min_mp is the last pool_entry that has a lower constraint
5655 than the one we are trying to add. */
5656 Mnode
* min_mp
= NULL
;
5657 /* This can be negative, since it is only a constraint. */
5658 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
5661 /* If we can't reach the current pool from this insn, or if we can't
5662 insert this entry at the end of the pool without pushing other
5663 fixes out of range, then we don't try. This ensures that we
5664 can't fail later on. */
5665 if (min_address
>= minipool_barrier
->address
5666 || (minipool_vector_tail
->min_address
+ fix
->fix_size
5667 >= minipool_barrier
->address
))
5670 /* Scan the pool to see if a constant with the same value has
5671 already been added. While we are doing this, also note the
5672 location where we must insert the constant if it doesn't already
5674 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
5676 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5677 && fix
->mode
== mp
->mode
5678 && (GET_CODE (fix
->value
) != CODE_LABEL
5679 || (CODE_LABEL_NUMBER (fix
->value
)
5680 == CODE_LABEL_NUMBER (mp
->value
)))
5681 && rtx_equal_p (fix
->value
, mp
->value
)
5682 /* Check that there is enough slack to move this entry to the
5683 end of the table (this is conservative). */
5685 > (minipool_barrier
->address
5686 + minipool_vector_tail
->offset
5687 + minipool_vector_tail
->fix_size
)))
5690 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
5694 mp
->min_address
+= fix
->fix_size
;
5697 /* Note the insertion point if necessary. */
5698 if (mp
->min_address
< min_address
)
5700 else if (mp
->max_address
5701 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
5703 /* Inserting before this entry would push the fix beyond
5704 its maximum address (which can happen if we have
5705 re-located a forwards fix); force the new fix to come
5708 min_address
= mp
->min_address
+ fix
->fix_size
;
5713 /* We need to create a new entry. */
5714 mp
= xmalloc (sizeof (* mp
));
5715 mp
->fix_size
= fix
->fix_size
;
5716 mp
->mode
= fix
->mode
;
5717 mp
->value
= fix
->value
;
5719 mp
->max_address
= minipool_barrier
->address
+ 65536;
5721 mp
->min_address
= min_address
;
5726 mp
->next
= minipool_vector_head
;
5728 if (mp
->next
== NULL
)
5730 minipool_vector_tail
= mp
;
5731 minipool_vector_label
= gen_label_rtx ();
5734 mp
->next
->prev
= mp
;
5736 minipool_vector_head
= mp
;
5740 mp
->next
= min_mp
->next
;
5744 if (mp
->next
!= NULL
)
5745 mp
->next
->prev
= mp
;
5747 minipool_vector_tail
= mp
;
5750 /* Save the new entry. */
5758 /* Scan over the following entries and adjust their offsets. */
5759 while (mp
->next
!= NULL
)
5761 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5762 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5765 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
5767 mp
->next
->offset
= mp
->offset
;
5776 assign_minipool_offsets (barrier
)
5779 HOST_WIDE_INT offset
= 0;
5782 minipool_barrier
= barrier
;
5784 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5786 mp
->offset
= offset
;
5788 if (mp
->refcount
> 0)
5789 offset
+= mp
->fix_size
;
5793 /* Output the literal table */
5795 dump_minipool (scan
)
5802 fprintf (rtl_dump_file
,
5803 ";; Emitting minipool after insn %u; address %ld\n",
5804 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
);
5806 scan
= emit_label_after (gen_label_rtx (), scan
);
5807 scan
= emit_insn_after (gen_align_4 (), scan
);
5808 scan
= emit_label_after (minipool_vector_label
, scan
);
5810 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
5812 if (mp
->refcount
> 0)
5816 fprintf (rtl_dump_file
,
5817 ";; Offset %u, min %ld, max %ld ",
5818 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
5819 (unsigned long) mp
->max_address
);
5820 arm_print_value (rtl_dump_file
, mp
->value
);
5821 fputc ('\n', rtl_dump_file
);
5824 switch (mp
->fix_size
)
5826 #ifdef HAVE_consttable_1
5828 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
5832 #ifdef HAVE_consttable_2
5834 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
5838 #ifdef HAVE_consttable_4
5840 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
5844 #ifdef HAVE_consttable_8
5846 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
5860 minipool_vector_head
= minipool_vector_tail
= NULL
;
5861 scan
= emit_insn_after (gen_consttable_end (), scan
);
5862 scan
= emit_barrier_after (scan
);
5865 /* Return the cost of forcibly inserting a barrier after INSN. */
5868 arm_barrier_cost (insn
)
5871 /* Basing the location of the pool on the loop depth is preferable,
5872 but at the moment, the basic block information seems to be
5873 corrupt by this stage of the compilation. */
5875 rtx next
= next_nonnote_insn (insn
);
5877 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
5880 switch (GET_CODE (insn
))
5883 /* It will always be better to place the table before the label, rather
5892 return base_cost
- 10;
5895 return base_cost
+ 10;
5899 /* Find the best place in the insn stream in the range
5900 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5901 Create the barrier by inserting a jump and add a new fix entry for
5905 create_fix_barrier (fix
, max_address
)
5907 HOST_WIDE_INT max_address
;
5909 HOST_WIDE_INT count
= 0;
5911 rtx from
= fix
->insn
;
5912 rtx selected
= from
;
5914 HOST_WIDE_INT selected_address
;
5916 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
5917 rtx label
= gen_label_rtx ();
5919 selected_cost
= arm_barrier_cost (from
);
5920 selected_address
= fix
->address
;
5922 while (from
&& count
< max_count
)
5927 /* This code shouldn't have been called if there was a natural barrier
5929 if (GET_CODE (from
) == BARRIER
)
5932 /* Count the length of this insn. */
5933 count
+= get_attr_length (from
);
5935 /* If there is a jump table, add its length. */
5936 tmp
= is_jump_table (from
);
5939 count
+= get_jump_table_size (tmp
);
5941 /* Jump tables aren't in a basic block, so base the cost on
5942 the dispatch insn. If we select this location, we will
5943 still put the pool after the table. */
5944 new_cost
= arm_barrier_cost (from
);
5946 if (count
< max_count
&& new_cost
<= selected_cost
)
5949 selected_cost
= new_cost
;
5950 selected_address
= fix
->address
+ count
;
5953 /* Continue after the dispatch table. */
5954 from
= NEXT_INSN (tmp
);
5958 new_cost
= arm_barrier_cost (from
);
5960 if (count
< max_count
&& new_cost
<= selected_cost
)
5963 selected_cost
= new_cost
;
5964 selected_address
= fix
->address
+ count
;
5967 from
= NEXT_INSN (from
);
5970 /* Create a new JUMP_INSN that branches around a barrier. */
5971 from
= emit_jump_insn_after (gen_jump (label
), selected
);
5972 JUMP_LABEL (from
) = label
;
5973 barrier
= emit_barrier_after (from
);
5974 emit_label_after (label
, barrier
);
5976 /* Create a minipool barrier entry for the new barrier. */
5977 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
5978 new_fix
->insn
= barrier
;
5979 new_fix
->address
= selected_address
;
5980 new_fix
->next
= fix
->next
;
5981 fix
->next
= new_fix
;
5986 /* Record that there is a natural barrier in the insn stream at
5989 push_minipool_barrier (insn
, address
)
5991 HOST_WIDE_INT address
;
5993 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
5996 fix
->address
= address
;
5999 if (minipool_fix_head
!= NULL
)
6000 minipool_fix_tail
->next
= fix
;
6002 minipool_fix_head
= fix
;
6004 minipool_fix_tail
= fix
;
6007 /* Record INSN, which will need fixing up to load a value from the
6008 minipool. ADDRESS is the offset of the insn since the start of the
6009 function; LOC is a pointer to the part of the insn which requires
6010 fixing; VALUE is the constant that must be loaded, which is of type
6013 push_minipool_fix (insn
, address
, loc
, mode
, value
)
6015 HOST_WIDE_INT address
;
6017 enum machine_mode mode
;
6020 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6022 #ifdef AOF_ASSEMBLER
6023 /* PIC symbol refereneces need to be converted into offsets into the
6025 /* XXX This shouldn't be done here. */
6026 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6027 value
= aof_pic_entry (value
);
6028 #endif /* AOF_ASSEMBLER */
6031 fix
->address
= address
;
6034 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6036 fix
->forwards
= get_attr_pool_range (insn
);
6037 fix
->backwards
= get_attr_neg_pool_range (insn
);
6038 fix
->minipool
= NULL
;
6040 /* If an insn doesn't have a range defined for it, then it isn't
6041 expecting to be reworked by this code. Better to abort now than
6042 to generate duff assembly code. */
6043 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6048 fprintf (rtl_dump_file
,
6049 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6050 GET_MODE_NAME (mode
),
6051 INSN_UID (insn
), (unsigned long) address
,
6052 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6053 arm_print_value (rtl_dump_file
, fix
->value
);
6054 fprintf (rtl_dump_file
, "\n");
6057 /* Add it to the chain of fixes. */
6060 if (minipool_fix_head
!= NULL
)
6061 minipool_fix_tail
->next
= fix
;
6063 minipool_fix_head
= fix
;
6065 minipool_fix_tail
= fix
;
6068 /* Scan INSN and note any of its operands that need fixing. */
6071 note_invalid_constants (insn
, address
)
6073 HOST_WIDE_INT address
;
6077 extract_insn (insn
);
6079 if (!constrain_operands (1))
6080 fatal_insn_not_found (insn
);
6082 /* Fill in recog_op_alt with information about the constraints of this
6084 preprocess_constraints ();
6086 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6088 /* Things we need to fix can only occur in inputs. */
6089 if (recog_data
.operand_type
[opno
] != OP_IN
)
6092 /* If this alternative is a memory reference, then any mention
6093 of constants in this alternative is really to fool reload
6094 into allowing us to accept one there. We need to fix them up
6095 now so that we output the right code. */
6096 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6098 rtx op
= recog_data
.operand
[opno
];
6100 if (CONSTANT_P (op
))
6101 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6102 recog_data
.operand_mode
[opno
], op
);
6104 /* RWE: Now we look correctly at the operands for the insn,
6105 this shouldn't be needed any more. */
6106 #ifndef AOF_ASSEMBLER
6107 /* XXX Is this still needed? */
6108 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == UNSPEC_PIC_SYM
)
6109 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6110 recog_data
.operand_mode
[opno
],
6111 XVECEXP (op
, 0, 0));
6114 else if (GET_CODE (op
) == MEM
6115 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6116 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6117 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6118 recog_data
.operand_mode
[opno
],
6119 get_pool_constant (XEXP (op
, 0)));
6129 HOST_WIDE_INT address
= 0;
6132 minipool_fix_head
= minipool_fix_tail
= NULL
;
6134 /* The first insn must always be a note, or the code below won't
6135 scan it properly. */
6136 if (GET_CODE (first
) != NOTE
)
6139 /* Scan all the insns and record the operands that will need fixing. */
6140 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
6142 if (GET_CODE (insn
) == BARRIER
)
6143 push_minipool_barrier (insn
, address
);
6144 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
6145 || GET_CODE (insn
) == JUMP_INSN
)
6149 note_invalid_constants (insn
, address
);
6150 address
+= get_attr_length (insn
);
6152 /* If the insn is a vector jump, add the size of the table
6153 and skip the table. */
6154 if ((table
= is_jump_table (insn
)) != NULL
)
6156 address
+= get_jump_table_size (table
);
6162 fix
= minipool_fix_head
;
6164 /* Now scan the fixups and perform the required changes. */
6169 Mfix
* last_added_fix
;
6170 Mfix
* last_barrier
= NULL
;
6173 /* Skip any further barriers before the next fix. */
6174 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6177 /* No more fixes. */
6181 last_added_fix
= NULL
;
6183 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6185 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6187 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6190 last_barrier
= ftmp
;
6192 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6195 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6198 /* If we found a barrier, drop back to that; any fixes that we
6199 could have reached but come after the barrier will now go in
6200 the next mini-pool. */
6201 if (last_barrier
!= NULL
)
6203 /* Reduce the refcount for those fixes that won't go into this
6205 for (fdel
= last_barrier
->next
;
6206 fdel
&& fdel
!= ftmp
;
6209 fdel
->minipool
->refcount
--;
6210 fdel
->minipool
= NULL
;
6213 ftmp
= last_barrier
;
6217 /* ftmp is first fix that we can't fit into this pool and
6218 there no natural barriers that we could use. Insert a
6219 new barrier in the code somewhere between the previous
6220 fix and this one, and arrange to jump around it. */
6221 HOST_WIDE_INT max_address
;
6223 /* The last item on the list of fixes must be a barrier, so
6224 we can never run off the end of the list of fixes without
6225 last_barrier being set. */
6229 max_address
= minipool_vector_head
->max_address
;
6230 /* Check that there isn't another fix that is in range that
6231 we couldn't fit into this pool because the pool was
6232 already too large: we need to put the pool before such an
6234 if (ftmp
->address
< max_address
)
6235 max_address
= ftmp
->address
;
6237 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6240 assign_minipool_offsets (last_barrier
);
6244 if (GET_CODE (ftmp
->insn
) != BARRIER
6245 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
6252 /* Scan over the fixes we have identified for this pool, fixing them
6253 up and adding the constants to the pool itself. */
6254 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
6255 this_fix
= this_fix
->next
)
6256 if (GET_CODE (this_fix
->insn
) != BARRIER
)
6259 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
6260 minipool_vector_label
),
6261 this_fix
->minipool
->offset
);
6262 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
6265 dump_minipool (last_barrier
->insn
);
6269 /* From now on we must synthesize any constants that we can't handle
6270 directly. This can happen if the RTL gets split during final
6271 instruction generation. */
6272 after_arm_reorg
= 1;
6274 /* Free the minipool memory. */
6275 obstack_free (&minipool_obstack
, minipool_startobj
);
6278 /* Routines to output assembly language. */
6280 /* If the rtx is the correct value then return the string of the number.
6281 In this way we can ensure that valid double constants are generated even
6282 when cross compiling. */
6285 fp_immediate_constant (x
)
6291 if (!fpa_consts_inited
)
6294 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6295 for (i
= 0; i
< 8; i
++)
6296 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
6297 return strings_fpa
[i
];
6302 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6305 fp_const_from_val (r
)
6306 REAL_VALUE_TYPE
* r
;
6310 if (!fpa_consts_inited
)
6313 for (i
= 0; i
< 8; i
++)
6314 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
6315 return strings_fpa
[i
];
6320 /* Output the operands of a LDM/STM instruction to STREAM.
6321 MASK is the ARM register set mask of which only bits 0-15 are important.
6322 REG is the base register, either the frame pointer or the stack pointer,
6323 INSTR is the possibly suffixed load or store instruction. */
6326 print_multi_reg (stream
, instr
, reg
, mask
)
6333 int not_first
= FALSE
;
6335 fputc ('\t', stream
);
6336 asm_fprintf (stream
, instr
, reg
);
6337 fputs (", {", stream
);
6339 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
6340 if (mask
& (1 << i
))
6343 fprintf (stream
, ", ");
6345 asm_fprintf (stream
, "%r", i
);
6349 fprintf (stream
, "}%s\n", TARGET_APCS_32
? "" : "^");
6352 /* Output a 'call' insn. */
6355 output_call (operands
)
6358 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6360 if (REGNO (operands
[0]) == LR_REGNUM
)
6362 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
6363 output_asm_insn ("mov%?\t%0, %|lr", operands
);
6366 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6368 if (TARGET_INTERWORK
)
6369 output_asm_insn ("bx%?\t%0", operands
);
6371 output_asm_insn ("mov%?\t%|pc, %0", operands
);
6380 int something_changed
= 0;
6382 int code
= GET_CODE (x0
);
6389 if (REGNO (x0
) == LR_REGNUM
)
6391 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
6396 /* Scan through the sub-elements and change any references there. */
6397 fmt
= GET_RTX_FORMAT (code
);
6399 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6401 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
6402 else if (fmt
[i
] == 'E')
6403 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
6404 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
6406 return something_changed
;
6410 /* Output a 'call' insn that is a reference in memory. */
6413 output_call_mem (operands
)
6416 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful. */
6417 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6418 if (eliminate_lr2ip (&operands
[0]))
6419 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
6421 if (TARGET_INTERWORK
)
6423 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
6424 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6425 output_asm_insn ("bx%?\t%|ip", operands
);
6429 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6430 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
6437 /* Output a move from arm registers to an fpu registers.
6438 OPERANDS[0] is an fpu register.
6439 OPERANDS[1] is the first registers of an arm register pair. */
6442 output_mov_long_double_fpu_from_arm (operands
)
6445 int arm_reg0
= REGNO (operands
[1]);
6448 if (arm_reg0
== IP_REGNUM
)
6451 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6452 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6453 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6455 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6456 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
6461 /* Output a move from an fpu register to arm registers.
6462 OPERANDS[0] is the first registers of an arm register pair.
6463 OPERANDS[1] is an fpu register. */
6466 output_mov_long_double_arm_from_fpu (operands
)
6469 int arm_reg0
= REGNO (operands
[0]);
6472 if (arm_reg0
== IP_REGNUM
)
6475 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6476 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6477 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6479 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
6480 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6484 /* Output a move from arm registers to arm registers of a long double
6485 OPERANDS[0] is the destination.
6486 OPERANDS[1] is the source. */
6489 output_mov_long_double_arm_from_arm (operands
)
6492 /* We have to be careful here because the two might overlap. */
6493 int dest_start
= REGNO (operands
[0]);
6494 int src_start
= REGNO (operands
[1]);
6498 if (dest_start
< src_start
)
6500 for (i
= 0; i
< 3; i
++)
6502 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6503 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6504 output_asm_insn ("mov%?\t%0, %1", ops
);
6509 for (i
= 2; i
>= 0; i
--)
6511 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6512 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6513 output_asm_insn ("mov%?\t%0, %1", ops
);
6521 /* Output a move from arm registers to an fpu registers.
6522 OPERANDS[0] is an fpu register.
6523 OPERANDS[1] is the first registers of an arm register pair. */
6526 output_mov_double_fpu_from_arm (operands
)
6529 int arm_reg0
= REGNO (operands
[1]);
6532 if (arm_reg0
== IP_REGNUM
)
6535 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6536 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6537 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
6538 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
6542 /* Output a move from an fpu register to arm registers.
6543 OPERANDS[0] is the first registers of an arm register pair.
6544 OPERANDS[1] is an fpu register. */
6547 output_mov_double_arm_from_fpu (operands
)
6550 int arm_reg0
= REGNO (operands
[0]);
6553 if (arm_reg0
== IP_REGNUM
)
6556 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6557 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6558 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
6559 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
6563 /* Output a move between double words.
6564 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6565 or MEM<-REG and all MEMs must be offsettable addresses. */
6568 output_move_double (operands
)
6571 enum rtx_code code0
= GET_CODE (operands
[0]);
6572 enum rtx_code code1
= GET_CODE (operands
[1]);
6577 int reg0
= REGNO (operands
[0]);
6579 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
6583 int reg1
= REGNO (operands
[1]);
6584 if (reg1
== IP_REGNUM
)
6587 /* Ensure the second source is not overwritten. */
6588 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
6589 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
6591 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
6593 else if (code1
== CONST_DOUBLE
)
6595 if (GET_MODE (operands
[1]) == DFmode
)
6600 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
6601 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
6602 otherops
[1] = GEN_INT (l
[1]);
6603 operands
[1] = GEN_INT (l
[0]);
6605 else if (GET_MODE (operands
[1]) != VOIDmode
)
6607 else if (WORDS_BIG_ENDIAN
)
6609 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6610 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6614 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6615 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6618 output_mov_immediate (operands
);
6619 output_mov_immediate (otherops
);
6621 else if (code1
== CONST_INT
)
6623 #if HOST_BITS_PER_WIDE_INT > 32
6624 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6625 what the upper word is. */
6626 if (WORDS_BIG_ENDIAN
)
6628 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6629 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6633 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6634 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6637 /* Sign extend the intval into the high-order word. */
6638 if (WORDS_BIG_ENDIAN
)
6640 otherops
[1] = operands
[1];
6641 operands
[1] = (INTVAL (operands
[1]) < 0
6642 ? constm1_rtx
: const0_rtx
);
6645 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
6647 output_mov_immediate (otherops
);
6648 output_mov_immediate (operands
);
6650 else if (code1
== MEM
)
6652 switch (GET_CODE (XEXP (operands
[1], 0)))
6655 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
6659 abort (); /* Should never happen now. */
6663 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
6667 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
6671 abort (); /* Should never happen now. */
6676 output_asm_insn ("adr%?\t%0, %1", operands
);
6677 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
6681 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
6682 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
6684 otherops
[0] = operands
[0];
6685 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
6686 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
6688 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
6690 if (GET_CODE (otherops
[2]) == CONST_INT
)
6692 switch (INTVAL (otherops
[2]))
6695 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
6698 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
6701 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
6705 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
6706 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
6708 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6711 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6714 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
6716 return "ldm%?ia\t%0, %M0";
6720 otherops
[1] = adjust_address (operands
[1], VOIDmode
, 4);
6721 /* Take care of overlapping base/data reg. */
6722 if (reg_mentioned_p (operands
[0], operands
[1]))
6724 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6725 output_asm_insn ("ldr%?\t%0, %1", operands
);
6729 output_asm_insn ("ldr%?\t%0, %1", operands
);
6730 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6736 abort (); /* Constraints should prevent this. */
6738 else if (code0
== MEM
&& code1
== REG
)
6740 if (REGNO (operands
[1]) == IP_REGNUM
)
6743 switch (GET_CODE (XEXP (operands
[0], 0)))
6746 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
6750 abort (); /* Should never happen now. */
6754 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
6758 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
6762 abort (); /* Should never happen now. */
6766 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
6768 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
6771 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
6775 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
6779 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
6786 otherops
[0] = adjust_address (operands
[0], VOIDmode
, 4);
6787 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
6788 output_asm_insn ("str%?\t%1, %0", operands
);
6789 output_asm_insn ("str%?\t%1, %0", otherops
);
6793 /* Constraints should prevent this. */
6800 /* Output an arbitrary MOV reg, #n.
6801 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6804 output_mov_immediate (operands
)
6807 HOST_WIDE_INT n
= INTVAL (operands
[1]);
6809 /* Try to use one MOV. */
6810 if (const_ok_for_arm (n
))
6811 output_asm_insn ("mov%?\t%0, %1", operands
);
6813 /* Try to use one MVN. */
6814 else if (const_ok_for_arm (~n
))
6816 operands
[1] = GEN_INT (~n
);
6817 output_asm_insn ("mvn%?\t%0, %1", operands
);
6824 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6825 for (i
= 0; i
< 32; i
++)
6829 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
6830 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
6832 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
6838 /* Output an ADD r, s, #n where n may be too big for one instruction.
6839 If adding zero to one register, output nothing. */
6842 output_add_immediate (operands
)
6845 HOST_WIDE_INT n
= INTVAL (operands
[2]);
6847 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
6850 output_multi_immediate (operands
,
6851 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6854 output_multi_immediate (operands
,
6855 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6862 /* Output a multiple immediate operation.
6863 OPERANDS is the vector of operands referred to in the output patterns.
6864 INSTR1 is the output pattern to use for the first constant.
6865 INSTR2 is the output pattern to use for subsequent constants.
6866 IMMED_OP is the index of the constant slot in OPERANDS.
6867 N is the constant value. */
6870 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
6872 const char * instr1
;
6873 const char * instr2
;
6877 #if HOST_BITS_PER_WIDE_INT > 32
6883 /* Quick and easy output. */
6884 operands
[immed_op
] = const0_rtx
;
6885 output_asm_insn (instr1
, operands
);
6890 const char * instr
= instr1
;
6892 /* Note that n is never zero here (which would give no output). */
6893 for (i
= 0; i
< 32; i
+= 2)
6897 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
6898 output_asm_insn (instr
, operands
);
6908 /* Return the appropriate ARM instruction for the operation code.
6909 The returned result should not be overwritten. OP is the rtx of the
6910 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6914 arithmetic_instr (op
, shift_first_arg
)
6916 int shift_first_arg
;
6918 switch (GET_CODE (op
))
6924 return shift_first_arg
? "rsb" : "sub";
6940 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6941 for the operation code. The returned result should not be overwritten.
6942 OP is the rtx code of the shift.
6943 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6947 shift_op (op
, amountp
)
6949 HOST_WIDE_INT
*amountp
;
6952 enum rtx_code code
= GET_CODE (op
);
6954 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
6956 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6957 *amountp
= INTVAL (XEXP (op
, 1));
6980 /* We never have to worry about the amount being other than a
6981 power of 2, since this case can never be reloaded from a reg. */
6983 *amountp
= int_log2 (*amountp
);
6994 /* This is not 100% correct, but follows from the desire to merge
6995 multiplication by a power of 2 with the recognizer for a
6996 shift. >=32 is not a valid shift for "asl", so we must try and
6997 output a shift that produces the correct arithmetical result.
6998 Using lsr #32 is identical except for the fact that the carry bit
6999 is not set correctly if we set the flags; but we never use the
7000 carry bit from such an operation, so we can ignore that. */
7001 if (code
== ROTATERT
)
7002 /* Rotate is just modulo 32. */
7004 else if (*amountp
!= (*amountp
& 31))
7011 /* Shifts of 0 are no-ops. */
7019 /* Obtain the shift from the POWER of two. */
7021 static HOST_WIDE_INT
7023 HOST_WIDE_INT power
;
7025 HOST_WIDE_INT shift
= 0;
7027 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7037 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7038 /bin/as is horribly restrictive. */
7039 #define MAX_ASCII_LEN 51
7042 output_ascii_pseudo_op (stream
, p
, len
)
7044 const unsigned char * p
;
7050 fputs ("\t.ascii\t\"", stream
);
7052 for (i
= 0; i
< len
; i
++)
7056 if (len_so_far
>= MAX_ASCII_LEN
)
7058 fputs ("\"\n\t.ascii\t\"", stream
);
7065 fputs ("\\t", stream
);
7070 fputs ("\\f", stream
);
7075 fputs ("\\b", stream
);
7080 fputs ("\\r", stream
);
7084 case TARGET_NEWLINE
:
7085 fputs ("\\n", stream
);
7087 if ((c
>= ' ' && c
<= '~')
7089 /* This is a good place for a line break. */
7090 len_so_far
= MAX_ASCII_LEN
;
7097 putc ('\\', stream
);
7102 if (c
>= ' ' && c
<= '~')
7109 fprintf (stream
, "\\%03o", c
);
7116 fputs ("\"\n", stream
);
7119 /* Compute the register sabe mask for registers 0 through 12
7120 inclusive. This code is used by both arm_compute_save_reg_mask
7121 and arm_compute_initial_elimination_offset. */
7123 static unsigned long
7124 arm_compute_save_reg0_reg12_mask ()
7126 unsigned long func_type
= arm_current_func_type ();
7127 unsigned int save_reg_mask
= 0;
7130 if (IS_INTERRUPT (func_type
))
7132 unsigned int max_reg
;
7133 /* Interrupt functions must not corrupt any registers,
7134 even call clobbered ones. If this is a leaf function
7135 we can just examine the registers used by the RTL, but
7136 otherwise we have to assume that whatever function is
7137 called might clobber anything, and so we have to save
7138 all the call-clobbered registers as well. */
7139 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7140 /* FIQ handlers have registers r8 - r12 banked, so
7141 we only need to check r0 - r7, Normal ISRs only
7142 bank r14 and r15, so we must check up to r12.
7143 r13 is the stack pointer which is always preserved,
7144 so we do not need to consider it here. */
7149 for (reg
= 0; reg
<= max_reg
; reg
++)
7150 if (regs_ever_live
[reg
]
7151 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7152 save_reg_mask
|= (1 << reg
);
7156 /* In the normal case we only need to save those registers
7157 which are call saved and which are used by this function. */
7158 for (reg
= 0; reg
<= 10; reg
++)
7159 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7160 save_reg_mask
|= (1 << reg
);
7162 /* Handle the frame pointer as a special case. */
7163 if (! TARGET_APCS_FRAME
7164 && ! frame_pointer_needed
7165 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7166 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7167 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7169 /* If we aren't loading the PIC register,
7170 don't stack it even though it may be live. */
7172 && ! TARGET_SINGLE_PIC_BASE
7173 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7174 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7177 return save_reg_mask
;
7180 /* Compute a bit mask of which registers need to be
7181 saved on the stack for the current function. */
7183 static unsigned long
7184 arm_compute_save_reg_mask ()
7186 unsigned int save_reg_mask
= 0;
7187 unsigned long func_type
= arm_current_func_type ();
7189 if (IS_NAKED (func_type
))
7190 /* This should never really happen. */
7193 /* If we are creating a stack frame, then we must save the frame pointer,
7194 IP (which will hold the old stack pointer), LR and the PC. */
7195 if (frame_pointer_needed
)
7197 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7202 /* Volatile functions do not return, so there
7203 is no need to save any other registers. */
7204 if (IS_VOLATILE (func_type
))
7205 return save_reg_mask
;
7207 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
7209 /* Decide if we need to save the link register.
7210 Interrupt routines have their own banked link register,
7211 so they never need to save it.
7212 Otherwise if we do not use the link register we do not need to save
7213 it. If we are pushing other registers onto the stack however, we
7214 can save an instruction in the epilogue by pushing the link register
7215 now and then popping it back into the PC. This incurs extra memory
7216 accesses though, so we only do it when optimising for size, and only
7217 if we know that we will not need a fancy return sequence. */
7218 if (regs_ever_live
[LR_REGNUM
]
7221 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
7222 save_reg_mask
|= 1 << LR_REGNUM
;
7224 if (cfun
->machine
->lr_save_eliminated
)
7225 save_reg_mask
&= ~ (1 << LR_REGNUM
);
7227 return save_reg_mask
;
7230 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7231 everything bar the final return instruction. */
7234 output_return_instruction (operand
, really_return
, reverse
)
7239 char conditional
[10];
7242 unsigned long live_regs_mask
;
7243 unsigned long func_type
;
7245 func_type
= arm_current_func_type ();
7247 if (IS_NAKED (func_type
))
7250 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7252 /* If this function was declared non-returning, and we have found a tail
7253 call, then we have to trust that the called function won't return. */
7258 /* Otherwise, trap an attempted return by aborting. */
7260 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
7262 assemble_external_libcall (ops
[1]);
7263 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
7269 if (current_function_calls_alloca
&& !really_return
)
7272 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
7274 return_used_this_function
= 1;
7276 live_regs_mask
= arm_compute_save_reg_mask ();
7280 const char * return_reg
;
7282 /* If we do not have any special requirements for function exit
7283 (eg interworking, or ISR) then we can load the return address
7284 directly into the PC. Otherwise we must load it into LR. */
7286 && ! TARGET_INTERWORK
)
7287 return_reg
= reg_names
[PC_REGNUM
];
7289 return_reg
= reg_names
[LR_REGNUM
];
7291 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
7292 /* There are two possible reasons for the IP register being saved.
7293 Either a stack frame was created, in which case IP contains the
7294 old stack pointer, or an ISR routine corrupted it. If this in an
7295 ISR routine then just restore IP, otherwise restore IP into SP. */
7296 if (! IS_INTERRUPT (func_type
))
7298 live_regs_mask
&= ~ (1 << IP_REGNUM
);
7299 live_regs_mask
|= (1 << SP_REGNUM
);
7302 /* On some ARM architectures it is faster to use LDR rather than
7303 LDM to load a single register. On other architectures, the
7304 cost is the same. In 26 bit mode, or for exception handlers,
7305 we have to use LDM to load the PC so that the CPSR is also
7307 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7309 if (live_regs_mask
== (unsigned int)(1 << reg
))
7312 if (reg
<= LAST_ARM_REGNUM
7313 && (reg
!= LR_REGNUM
7315 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
7317 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
7318 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
7325 /* Generate the load multiple instruction to restore the registers. */
7326 if (frame_pointer_needed
)
7327 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
7329 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
7331 p
= instr
+ strlen (instr
);
7333 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
7334 if (live_regs_mask
& (1 << reg
))
7336 int l
= strlen (reg_names
[reg
]);
7342 memcpy (p
, ", ", 2);
7346 memcpy (p
, "%|", 2);
7347 memcpy (p
+ 2, reg_names
[reg
], l
);
7351 if (live_regs_mask
& (1 << LR_REGNUM
))
7353 int l
= strlen (return_reg
);
7357 memcpy (p
, ", ", 2);
7361 memcpy (p
, "%|", 2);
7362 memcpy (p
+ 2, return_reg
, l
);
7363 strcpy (p
+ 2 + l
, ((TARGET_APCS_32
7364 && !IS_INTERRUPT (func_type
))
7372 output_asm_insn (instr
, & operand
);
7374 /* See if we need to generate an extra instruction to
7375 perform the actual function return. */
7377 && func_type
!= ARM_FT_INTERWORKED
7378 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
7380 /* The return has already been handled
7381 by loading the LR into the PC. */
7388 switch ((int) ARM_FUNC_TYPE (func_type
))
7392 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
7395 case ARM_FT_INTERWORKED
:
7396 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7399 case ARM_FT_EXCEPTION
:
7400 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
7404 /* ARMv5 implementations always provide BX, so interworking
7405 is the default unless APCS-26 is in use. */
7406 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
7407 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7409 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
7410 conditional
, TARGET_APCS_32
? "" : "s");
7414 output_asm_insn (instr
, & operand
);
7420 /* Write the function name into the code section, directly preceding
7421 the function prologue.
7423 Code will be output similar to this:
7425 .ascii "arm_poke_function_name", 0
7428 .word 0xff000000 + (t1 - t0)
7429 arm_poke_function_name
7431 stmfd sp!, {fp, ip, lr, pc}
7434 When performing a stack backtrace, code can inspect the value
7435 of 'pc' stored at 'fp' + 0. If the trace function then looks
7436 at location pc - 12 and the top 8 bits are set, then we know
7437 that there is a function name embedded immediately preceding this
7438 location and has length ((pc[-3]) & 0xff000000).
7440 We assume that pc is declared as a pointer to an unsigned long.
7442 It is of no benefit to output the function name if we are assembling
7443 a leaf function. These function types will not contain a stack
7444 backtrace structure, therefore it is not possible to determine the
7448 arm_poke_function_name (stream
, name
)
7452 unsigned long alignlength
;
7453 unsigned long length
;
7456 length
= strlen (name
) + 1;
7457 alignlength
= ROUND_UP (length
);
7459 ASM_OUTPUT_ASCII (stream
, name
, length
);
7460 ASM_OUTPUT_ALIGN (stream
, 2);
7461 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
7462 assemble_aligned_integer (UNITS_PER_WORD
, x
);
7465 /* Place some comments into the assembler stream
7466 describing the current function. */
7469 arm_output_function_prologue (f
, frame_size
)
7471 HOST_WIDE_INT frame_size
;
7473 unsigned long func_type
;
7477 thumb_output_function_prologue (f
, frame_size
);
7482 if (arm_ccfsm_state
|| arm_target_insn
)
7485 func_type
= arm_current_func_type ();
7487 switch ((int) ARM_FUNC_TYPE (func_type
))
7492 case ARM_FT_INTERWORKED
:
7493 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
7495 case ARM_FT_EXCEPTION_HANDLER
:
7496 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
7499 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
7502 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
7504 case ARM_FT_EXCEPTION
:
7505 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
7509 if (IS_NAKED (func_type
))
7510 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7512 if (IS_VOLATILE (func_type
))
7513 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
7515 if (IS_NESTED (func_type
))
7516 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
7518 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
7519 current_function_args_size
,
7520 current_function_pretend_args_size
, frame_size
);
7522 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
7523 frame_pointer_needed
,
7524 cfun
->machine
->uses_anonymous_args
);
7526 if (cfun
->machine
->lr_save_eliminated
)
7527 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
7529 #ifdef AOF_ASSEMBLER
7531 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
7534 return_used_this_function
= 0;
7538 arm_output_epilogue (really_return
)
7542 unsigned long saved_regs_mask
;
7543 unsigned long func_type
;
7544 /* Floats_offset is the offset from the "virtual" frame. In an APCS
7545 frame that is $fp + 4 for a non-variadic function. */
7546 int floats_offset
= 0;
7548 int frame_size
= get_frame_size ();
7549 FILE * f
= asm_out_file
;
7550 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
7552 /* If we have already generated the return instruction
7553 then it is futile to generate anything else. */
7554 if (use_return_insn (FALSE
) && return_used_this_function
)
7557 func_type
= arm_current_func_type ();
7559 if (IS_NAKED (func_type
))
7560 /* Naked functions don't have epilogues. */
7563 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7567 /* A volatile function should never return. Call abort. */
7568 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
7569 assemble_external_libcall (op
);
7570 output_asm_insn ("bl\t%a0", &op
);
7575 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
7577 /* If we are throwing an exception, then we really must
7578 be doing a return, so we can't tail-call. */
7581 saved_regs_mask
= arm_compute_save_reg_mask ();
7583 /* XXX We should adjust floats_offset for any anonymous args, and then
7584 re-adjust vfp_offset below to compensate. */
7586 /* Compute how far away the floats will be. */
7587 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7588 if (saved_regs_mask
& (1 << reg
))
7591 if (frame_pointer_needed
)
7595 if (arm_fpu_arch
== FP_SOFT2
)
7597 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7598 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7600 floats_offset
+= 12;
7601 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
7602 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7607 int start_reg
= LAST_ARM_FP_REGNUM
;
7609 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7611 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7613 floats_offset
+= 12;
7615 /* We can't unstack more than four registers at once. */
7616 if (start_reg
- reg
== 3)
7618 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
7619 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7620 start_reg
= reg
- 1;
7625 if (reg
!= start_reg
)
7626 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7627 reg
+ 1, start_reg
- reg
,
7628 FP_REGNUM
, floats_offset
- vfp_offset
);
7629 start_reg
= reg
- 1;
7633 /* Just in case the last register checked also needs unstacking. */
7634 if (reg
!= start_reg
)
7635 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7636 reg
+ 1, start_reg
- reg
,
7637 FP_REGNUM
, floats_offset
- vfp_offset
);
7640 /* saved_regs_mask should contain the IP, which at the time of stack
7641 frame generation actually contains the old stack pointer. So a
7642 quick way to unwind the stack is just pop the IP register directly
7643 into the stack pointer. */
7644 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
7646 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
7647 saved_regs_mask
|= (1 << SP_REGNUM
);
7649 /* There are two registers left in saved_regs_mask - LR and PC. We
7650 only need to restore the LR register (the return address), but to
7651 save time we can load it directly into the PC, unless we need a
7652 special function exit sequence, or we are not really returning. */
7653 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
7654 /* Delete the LR from the register mask, so that the LR on
7655 the stack is loaded into the PC in the register mask. */
7656 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7658 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
7660 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
7662 if (IS_INTERRUPT (func_type
))
7663 /* Interrupt handlers will have pushed the
7664 IP onto the stack, so restore it now. */
7665 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, 1 << IP_REGNUM
);
7669 /* Restore stack pointer if necessary. */
7670 if (frame_size
+ current_function_outgoing_args_size
!= 0)
7672 operands
[0] = operands
[1] = stack_pointer_rtx
;
7673 operands
[2] = GEN_INT (frame_size
7674 + current_function_outgoing_args_size
);
7675 output_add_immediate (operands
);
7678 if (arm_fpu_arch
== FP_SOFT2
)
7680 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7681 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7682 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
7687 int start_reg
= FIRST_ARM_FP_REGNUM
;
7689 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7691 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7693 if (reg
- start_reg
== 3)
7695 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
7696 start_reg
, SP_REGNUM
);
7697 start_reg
= reg
+ 1;
7702 if (reg
!= start_reg
)
7703 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7704 start_reg
, reg
- start_reg
,
7707 start_reg
= reg
+ 1;
7711 /* Just in case the last register checked also needs unstacking. */
7712 if (reg
!= start_reg
)
7713 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7714 start_reg
, reg
- start_reg
, SP_REGNUM
);
7717 /* If we can, restore the LR into the PC. */
7718 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7720 && current_function_pretend_args_size
== 0
7721 && saved_regs_mask
& (1 << LR_REGNUM
))
7723 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7724 saved_regs_mask
|= (1 << PC_REGNUM
);
7727 /* Load the registers off the stack. If we only have one register
7728 to load use the LDR instruction - it is faster. */
7729 if (saved_regs_mask
== (1 << LR_REGNUM
))
7731 /* The exception handler ignores the LR, so we do
7732 not really need to load it off the stack. */
7734 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
7736 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
7738 else if (saved_regs_mask
)
7739 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
7741 if (current_function_pretend_args_size
)
7743 /* Unwind the pre-pushed regs. */
7744 operands
[0] = operands
[1] = stack_pointer_rtx
;
7745 operands
[2] = GEN_INT (current_function_pretend_args_size
);
7746 output_add_immediate (operands
);
7751 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
7752 /* Adjust the stack to remove the exception handler stuff. */
7753 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
7758 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7759 && current_function_pretend_args_size
== 0
7760 && saved_regs_mask
& (1 << PC_REGNUM
)))
7763 /* Generate the return instruction. */
7764 switch ((int) ARM_FUNC_TYPE (func_type
))
7766 case ARM_FT_EXCEPTION_HANDLER
:
7767 /* Even in 26-bit mode we do a mov (rather than a movs)
7768 because we don't have the PSR bits set in the address. */
7769 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
7774 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
7777 case ARM_FT_EXCEPTION
:
7778 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7781 case ARM_FT_INTERWORKED
:
7782 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
7786 if (frame_pointer_needed
)
7787 /* If we used the frame pointer then the return adddress
7788 will have been loaded off the stack directly into the
7789 PC, so there is no need to issue a MOV instruction
7792 else if (current_function_pretend_args_size
== 0
7793 && (saved_regs_mask
& (1 << LR_REGNUM
)))
7794 /* Similarly we may have been able to load LR into the PC
7795 even if we did not create a stack frame. */
7797 else if (TARGET_APCS_32
)
7798 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7800 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7808 arm_output_function_epilogue (file
, frame_size
)
7809 FILE *file ATTRIBUTE_UNUSED
;
7810 HOST_WIDE_INT frame_size
;
7814 /* ??? Probably not safe to set this here, since it assumes that a
7815 function will be emitted as assembly immediately after we generate
7816 RTL for it. This does not happen for inline functions. */
7817 return_used_this_function
= 0;
7821 if (use_return_insn (FALSE
)
7822 && return_used_this_function
7823 && (frame_size
+ current_function_outgoing_args_size
) != 0
7824 && !frame_pointer_needed
)
7827 /* Reset the ARM-specific per-function variables. */
7828 after_arm_reorg
= 0;
7832 /* Generate and emit an insn that we will recognize as a push_multi.
7833 Unfortunately, since this insn does not reflect very well the actual
7834 semantics of the operation, we need to annotate the insn for the benefit
7835 of DWARF2 frame unwind information. */
7838 emit_multi_reg_push (mask
)
7846 int dwarf_par_index
;
7849 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7850 if (mask
& (1 << i
))
7853 if (num_regs
== 0 || num_regs
> 16)
7856 /* We don't record the PC in the dwarf frame information. */
7857 num_dwarf_regs
= num_regs
;
7858 if (mask
& (1 << PC_REGNUM
))
7861 /* For the body of the insn we are going to generate an UNSPEC in
7862 parallel with several USEs. This allows the insn to be recognized
7863 by the push_multi pattern in the arm.md file. The insn looks
7864 something like this:
7867 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7868 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7869 (use (reg:SI 11 fp))
7870 (use (reg:SI 12 ip))
7871 (use (reg:SI 14 lr))
7872 (use (reg:SI 15 pc))
7875 For the frame note however, we try to be more explicit and actually
7876 show each register being stored into the stack frame, plus a (single)
7877 decrement of the stack pointer. We do it this way in order to be
7878 friendly to the stack unwinding code, which only wants to see a single
7879 stack decrement per instruction. The RTL we generate for the note looks
7880 something like this:
7883 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7884 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7885 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7886 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7887 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7890 This sequence is used both by the code to support stack unwinding for
7891 exceptions handlers and the code to generate dwarf2 frame debugging. */
7893 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
7894 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
7895 dwarf_par_index
= 1;
7897 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7899 if (mask
& (1 << i
))
7901 reg
= gen_rtx_REG (SImode
, i
);
7904 = gen_rtx_SET (VOIDmode
,
7905 gen_rtx_MEM (BLKmode
,
7906 gen_rtx_PRE_DEC (BLKmode
,
7907 stack_pointer_rtx
)),
7908 gen_rtx_UNSPEC (BLKmode
,
7914 tmp
= gen_rtx_SET (VOIDmode
,
7915 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
7917 RTX_FRAME_RELATED_P (tmp
) = 1;
7918 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
7926 for (j
= 1, i
++; j
< num_regs
; i
++)
7928 if (mask
& (1 << i
))
7930 reg
= gen_rtx_REG (SImode
, i
);
7932 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
7936 tmp
= gen_rtx_SET (VOIDmode
,
7937 gen_rtx_MEM (SImode
,
7938 plus_constant (stack_pointer_rtx
,
7941 RTX_FRAME_RELATED_P (tmp
) = 1;
7942 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
7949 par
= emit_insn (par
);
7951 tmp
= gen_rtx_SET (SImode
,
7953 gen_rtx_PLUS (SImode
,
7955 GEN_INT (-4 * num_regs
)));
7956 RTX_FRAME_RELATED_P (tmp
) = 1;
7957 XVECEXP (dwarf
, 0, 0) = tmp
;
7959 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7965 emit_sfm (base_reg
, count
)
7974 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7975 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
7977 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7980 = gen_rtx_SET (VOIDmode
,
7981 gen_rtx_MEM (BLKmode
,
7982 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7983 gen_rtx_UNSPEC (BLKmode
,
7987 = gen_rtx_SET (VOIDmode
,
7988 gen_rtx_MEM (XFmode
,
7989 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
7991 RTX_FRAME_RELATED_P (tmp
) = 1;
7992 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
7994 for (i
= 1; i
< count
; i
++)
7996 reg
= gen_rtx_REG (XFmode
, base_reg
++);
7997 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
7999 tmp
= gen_rtx_SET (VOIDmode
,
8000 gen_rtx_MEM (XFmode
,
8001 gen_rtx_PRE_DEC (BLKmode
,
8002 stack_pointer_rtx
)),
8004 RTX_FRAME_RELATED_P (tmp
) = 1;
8005 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
8008 par
= emit_insn (par
);
8009 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8014 /* Compute the distance from register FROM to register TO.
8015 These can be the arg pointer (26), the soft frame pointer (25),
8016 the stack pointer (13) or the hard frame pointer (11).
8017 Typical stack layout looks like this:
8019 old stack pointer -> | |
8022 | | saved arguments for
8023 | | vararg functions
8026 hard FP & arg pointer -> | | \
8034 soft frame pointer -> | | /
8044 current stack pointer -> | | /
8047 For a given function some or all of these stack compomnents
8048 may not be needed, giving rise to the possibility of
8049 eliminating some of the registers.
8051 The values returned by this function must reflect the behaviour
8052 of arm_expand_prologue() and arm_compute_save_reg_mask().
8054 The sign of the number returned reflects the direction of stack
8055 growth, so the values are positive for all eliminations except
8056 from the soft frame pointer to the hard frame pointer. */
8059 arm_compute_initial_elimination_offset (from
, to
)
8063 unsigned int local_vars
= (get_frame_size () + 3) & ~3;
8064 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8065 unsigned int stack_frame
;
8066 unsigned int call_saved_registers
;
8067 unsigned long func_type
;
8069 func_type
= arm_current_func_type ();
8071 /* Volatile functions never return, so there is
8072 no need to save call saved registers. */
8073 call_saved_registers
= 0;
8074 if (! IS_VOLATILE (func_type
))
8076 unsigned int reg_mask
;
8079 /* Make sure that we compute which registers will be saved
8080 on the stack using the same algorithm that is used by
8081 arm_compute_save_reg_mask(). */
8082 reg_mask
= arm_compute_save_reg0_reg12_mask ();
8084 /* Now count the number of bits set in save_reg_mask.
8085 For each set bit we need 4 bytes of stack space. */
8088 call_saved_registers
+= 4;
8089 reg_mask
= reg_mask
& ~ (reg_mask
& - reg_mask
);
8092 if (regs_ever_live
[LR_REGNUM
]
8093 /* If a stack frame is going to be created, the LR will
8094 be saved as part of that, so we do not need to allow
8096 && ! frame_pointer_needed
)
8097 call_saved_registers
+= 4;
8099 /* If the hard floating point registers are going to be
8100 used then they must be saved on the stack as well.
8101 Each register occupies 12 bytes of stack space. */
8102 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8103 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8104 call_saved_registers
+= 12;
8107 /* The stack frame contains 4 registers - the old frame pointer,
8108 the old stack pointer, the return address and PC of the start
8110 stack_frame
= frame_pointer_needed
? 16 : 0;
8112 /* OK, now we have enough information to compute the distances.
8113 There must be an entry in these switch tables for each pair
8114 of registers in ELIMINABLE_REGS, even if some of the entries
8115 seem to be redundant or useless. */
8118 case ARG_POINTER_REGNUM
:
8121 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8124 case FRAME_POINTER_REGNUM
:
8125 /* This is the reverse of the soft frame pointer
8126 to hard frame pointer elimination below. */
8127 if (call_saved_registers
== 0 && stack_frame
== 0)
8129 return (call_saved_registers
+ stack_frame
- 4);
8131 case ARM_HARD_FRAME_POINTER_REGNUM
:
8132 /* If there is no stack frame then the hard
8133 frame pointer and the arg pointer coincide. */
8134 if (stack_frame
== 0 && call_saved_registers
!= 0)
8136 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8137 return (frame_pointer_needed
8138 && current_function_needs_context
8139 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
8141 case STACK_POINTER_REGNUM
:
8142 /* If nothing has been pushed on the stack at all
8143 then this will return -4. This *is* correct! */
8144 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
8151 case FRAME_POINTER_REGNUM
:
8154 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8157 case ARM_HARD_FRAME_POINTER_REGNUM
:
8158 /* The hard frame pointer points to the top entry in the
8159 stack frame. The soft frame pointer to the bottom entry
8160 in the stack frame. If there is no stack frame at all,
8161 then they are identical. */
8162 if (call_saved_registers
== 0 && stack_frame
== 0)
8164 return - (call_saved_registers
+ stack_frame
- 4);
8166 case STACK_POINTER_REGNUM
:
8167 return local_vars
+ outgoing_args
;
8175 /* You cannot eliminate from the stack pointer.
8176 In theory you could eliminate from the hard frame
8177 pointer to the stack pointer, but this will never
8178 happen, since if a stack frame is not needed the
8179 hard frame pointer will never be used. */
8184 /* Generate the prologue instructions for entry into an ARM function. */
8187 arm_expand_prologue ()
8193 unsigned long live_regs_mask
;
8194 unsigned long func_type
;
8196 int saved_pretend_args
= 0;
8197 unsigned int args_to_push
;
8199 func_type
= arm_current_func_type ();
8201 /* Naked functions don't have prologues. */
8202 if (IS_NAKED (func_type
))
8205 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8206 args_to_push
= current_function_pretend_args_size
;
8208 /* Compute which register we will have to save onto the stack. */
8209 live_regs_mask
= arm_compute_save_reg_mask ();
8211 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
8213 if (frame_pointer_needed
)
8215 if (IS_INTERRUPT (func_type
))
8217 /* Interrupt functions must not corrupt any registers.
8218 Creating a frame pointer however, corrupts the IP
8219 register, so we must push it first. */
8220 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
8222 /* Do not set RTX_FRAME_RELATED_P on this insn.
8223 The dwarf stack unwinding code only wants to see one
8224 stack decrement per function, and this is not it. If
8225 this instruction is labeled as being part of the frame
8226 creation sequence then dwarf2out_frame_debug_expr will
8227 abort when it encounters the assignment of IP to FP
8228 later on, since the use of SP here establishes SP as
8229 the CFA register and not IP.
8231 Anyway this instruction is not really part of the stack
8232 frame creation although it is part of the prologue. */
8234 else if (IS_NESTED (func_type
))
8236 /* The Static chain register is the same as the IP register
8237 used as a scratch register during stack frame creation.
8238 To get around this need to find somewhere to store IP
8239 whilst the frame is being created. We try the following
8242 1. The last argument register.
8243 2. A slot on the stack above the frame. (This only
8244 works if the function is not a varargs function).
8245 3. Register r3, after pushing the argument registers
8248 Note - we only need to tell the dwarf2 backend about the SP
8249 adjustment in the second variant; the static chain register
8250 doesn't need to be unwound, as it doesn't contain a value
8251 inherited from the caller. */
8253 if (regs_ever_live
[3] == 0)
8255 insn
= gen_rtx_REG (SImode
, 3);
8256 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8257 insn
= emit_insn (insn
);
8259 else if (args_to_push
== 0)
8262 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
8263 insn
= gen_rtx_MEM (SImode
, insn
);
8264 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
8265 insn
= emit_insn (insn
);
8269 /* Just tell the dwarf backend that we adjusted SP. */
8270 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8271 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8272 GEN_INT (-fp_offset
)));
8273 RTX_FRAME_RELATED_P (insn
) = 1;
8274 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8275 dwarf
, REG_NOTES (insn
));
8279 /* Store the args on the stack. */
8280 if (cfun
->machine
->uses_anonymous_args
)
8281 insn
= emit_multi_reg_push
8282 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8285 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8286 GEN_INT (- args_to_push
)));
8288 RTX_FRAME_RELATED_P (insn
) = 1;
8290 saved_pretend_args
= 1;
8291 fp_offset
= args_to_push
;
8294 /* Now reuse r3 to preserve IP. */
8295 insn
= gen_rtx_REG (SImode
, 3);
8296 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8297 (void) emit_insn (insn
);
8303 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
8304 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8307 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
8309 insn
= emit_insn (insn
);
8310 RTX_FRAME_RELATED_P (insn
) = 1;
8315 /* Push the argument registers, or reserve space for them. */
8316 if (cfun
->machine
->uses_anonymous_args
)
8317 insn
= emit_multi_reg_push
8318 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8321 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8322 GEN_INT (- args_to_push
)));
8323 RTX_FRAME_RELATED_P (insn
) = 1;
8326 /* If this is an interrupt service routine, and the link register is
8327 going to be pushed, subtracting four now will mean that the
8328 function return can be done with a single instruction. */
8329 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
8330 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8332 emit_insn (gen_rtx_SET (SImode
,
8333 gen_rtx_REG (SImode
, LR_REGNUM
),
8334 gen_rtx_PLUS (SImode
,
8335 gen_rtx_REG (SImode
, LR_REGNUM
),
8341 insn
= emit_multi_reg_push (live_regs_mask
);
8342 RTX_FRAME_RELATED_P (insn
) = 1;
8345 if (! IS_VOLATILE (func_type
))
8347 /* Save any floating point call-saved registers used by this function. */
8348 if (arm_fpu_arch
== FP_SOFT2
)
8350 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8351 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8353 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
8354 insn
= gen_rtx_MEM (XFmode
, insn
);
8355 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
8356 gen_rtx_REG (XFmode
, reg
)));
8357 RTX_FRAME_RELATED_P (insn
) = 1;
8362 int start_reg
= LAST_ARM_FP_REGNUM
;
8364 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8366 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8368 if (start_reg
- reg
== 3)
8370 insn
= emit_sfm (reg
, 4);
8371 RTX_FRAME_RELATED_P (insn
) = 1;
8372 start_reg
= reg
- 1;
8377 if (start_reg
!= reg
)
8379 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8380 RTX_FRAME_RELATED_P (insn
) = 1;
8382 start_reg
= reg
- 1;
8386 if (start_reg
!= reg
)
8388 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8389 RTX_FRAME_RELATED_P (insn
) = 1;
8394 if (frame_pointer_needed
)
8396 /* Create the new frame pointer. */
8397 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
8398 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
8399 RTX_FRAME_RELATED_P (insn
) = 1;
8401 if (IS_NESTED (func_type
))
8403 /* Recover the static chain register. */
8404 if (regs_ever_live
[3] == 0
8405 || saved_pretend_args
)
8406 insn
= gen_rtx_REG (SImode
, 3);
8407 else /* if (current_function_pretend_args_size == 0) */
8409 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
, GEN_INT (4));
8410 insn
= gen_rtx_MEM (SImode
, insn
);
8413 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
8414 /* Add a USE to stop propagate_one_insn() from barfing. */
8415 emit_insn (gen_prologue_use (ip_rtx
));
8419 amount
= GEN_INT (-(get_frame_size ()
8420 + current_function_outgoing_args_size
));
8422 if (amount
!= const0_rtx
)
8424 /* This add can produce multiple insns for a large constant, so we
8425 need to get tricky. */
8426 rtx last
= get_last_insn ();
8427 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8431 last
= last
? NEXT_INSN (last
) : get_insns ();
8432 RTX_FRAME_RELATED_P (last
) = 1;
8434 while (last
!= insn
);
8436 /* If the frame pointer is needed, emit a special barrier that
8437 will prevent the scheduler from moving stores to the frame
8438 before the stack adjustment. */
8439 if (frame_pointer_needed
)
8440 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
8441 hard_frame_pointer_rtx
));
8444 /* If we are profiling, make sure no instructions are scheduled before
8445 the call to mcount. Similarly if the user has requested no
8446 scheduling in the prolog. */
8447 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
8448 emit_insn (gen_blockage ());
8450 /* If the link register is being kept alive, with the return address in it,
8451 then make sure that it does not get reused by the ce2 pass. */
8452 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
8454 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
8455 cfun
->machine
->lr_save_eliminated
= 1;
8459 /* If CODE is 'd', then the X is a condition operand and the instruction
8460 should only be executed if the condition is true.
8461 if CODE is 'D', then the X is a condition operand and the instruction
8462 should only be executed if the condition is false: however, if the mode
8463 of the comparison is CCFPEmode, then always execute the instruction -- we
8464 do this because in these circumstances !GE does not necessarily imply LT;
8465 in these cases the instruction pattern will take care to make sure that
8466 an instruction containing %d will follow, thereby undoing the effects of
8467 doing this instruction unconditionally.
8468 If CODE is 'N' then X is a floating point operand that must be negated
8470 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8471 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8474 arm_print_operand (stream
, x
, code
)
8482 fputs (ASM_COMMENT_START
, stream
);
8486 fputs (user_label_prefix
, stream
);
8490 fputs (REGISTER_PREFIX
, stream
);
8494 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
8496 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
8499 fputs (arm_condition_codes
[arm_current_cc
], stream
);
8501 else if (current_insn_predicate
)
8503 enum arm_cond_code code
;
8508 code
= get_arm_condition_code (current_insn_predicate
);
8509 fputs (arm_condition_codes
[code
], stream
);
8516 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8517 r
= REAL_VALUE_NEGATE (r
);
8518 fprintf (stream
, "%s", fp_const_from_val (&r
));
8523 if (GET_CODE (x
) == CONST_INT
)
8526 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
8527 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8532 output_addr_const (stream
, x
);
8537 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
8541 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
8547 const char * shift
= shift_op (x
, &val
);
8551 fprintf (stream
, ", %s ", shift_op (x
, &val
));
8553 arm_print_operand (stream
, XEXP (x
, 1), 0);
8556 fputc ('#', stream
);
8557 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8563 /* An explanation of the 'Q', 'R' and 'H' register operands:
8565 In a pair of registers containing a DI or DF value the 'Q'
8566 operand returns the register number of the register containing
8567 the least signficant part of the value. The 'R' operand returns
8568 the register number of the register containing the most
8569 significant part of the value.
8571 The 'H' operand returns the higher of the two register numbers.
8572 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8573 same as the 'Q' operand, since the most signficant part of the
8574 value is held in the lower number register. The reverse is true
8575 on systems where WORDS_BIG_ENDIAN is false.
8577 The purpose of these operands is to distinguish between cases
8578 where the endian-ness of the values is important (for example
8579 when they are added together), and cases where the endian-ness
8580 is irrelevant, but the order of register operations is important.
8581 For example when loading a value from memory into a register
8582 pair, the endian-ness does not matter. Provided that the value
8583 from the lower memory address is put into the lower numbered
8584 register, and the value from the higher address is put into the
8585 higher numbered register, the load will work regardless of whether
8586 the value being loaded is big-wordian or little-wordian. The
8587 order of the two register loads can matter however, if the address
8588 of the memory location is actually held in one of the registers
8589 being overwritten by the load. */
8591 if (REGNO (x
) > LAST_ARM_REGNUM
)
8593 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
8597 if (REGNO (x
) > LAST_ARM_REGNUM
)
8599 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
8603 if (REGNO (x
) > LAST_ARM_REGNUM
)
8605 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
8609 asm_fprintf (stream
, "%r",
8610 GET_CODE (XEXP (x
, 0)) == REG
8611 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
8615 asm_fprintf (stream
, "{%r-%r}",
8617 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
8621 /* CONST_TRUE_RTX means always -- that's the default. */
8622 if (x
== const_true_rtx
)
8626 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
8629 fputs (thumb_condition_code (x
, 0), stream
);
8633 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
8635 if (x
== const_true_rtx
)
8639 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
8640 (get_arm_condition_code (x
))],
8643 fputs (thumb_condition_code (x
, 1), stream
);
8650 if (GET_CODE (x
) == REG
)
8651 asm_fprintf (stream
, "%r", REGNO (x
));
8652 else if (GET_CODE (x
) == MEM
)
8654 output_memory_reference_mode
= GET_MODE (x
);
8655 output_address (XEXP (x
, 0));
8657 else if (GET_CODE (x
) == CONST_DOUBLE
)
8658 fprintf (stream
, "#%s", fp_immediate_constant (x
));
8659 else if (GET_CODE (x
) == NEG
)
8660 abort (); /* This should never happen now. */
8663 fputc ('#', stream
);
8664 output_addr_const (stream
, x
);
8669 #ifndef AOF_ASSEMBLER
8670 /* Target hook for assembling integer objects. The ARM version needs to
8671 handle word-sized values specially. */
8674 arm_assemble_integer (x
, size
, aligned_p
)
8679 if (size
== UNITS_PER_WORD
&& aligned_p
)
8681 fputs ("\t.word\t", asm_out_file
);
8682 output_addr_const (asm_out_file
, x
);
8684 /* Mark symbols as position independent. We only do this in the
8685 .text segment, not in the .data segment. */
8686 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
8687 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
8689 if (GET_CODE (x
) == SYMBOL_REF
8690 && (CONSTANT_POOL_ADDRESS_P (x
)
8691 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x
, 0))))
8692 fputs ("(GOTOFF)", asm_out_file
);
8693 else if (GET_CODE (x
) == LABEL_REF
)
8694 fputs ("(GOTOFF)", asm_out_file
);
8696 fputs ("(GOT)", asm_out_file
);
8698 fputc ('\n', asm_out_file
);
8702 return default_assemble_integer (x
, size
, aligned_p
);
8706 /* A finite state machine takes care of noticing whether or not instructions
8707 can be conditionally executed, and thus decrease execution time and code
8708 size by deleting branch instructions. The fsm is controlled by
8709 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8711 /* The state of the fsm controlling condition codes are:
8712 0: normal, do nothing special
8713 1: make ASM_OUTPUT_OPCODE not output this instruction
8714 2: make ASM_OUTPUT_OPCODE not output this instruction
8715 3: make instructions conditional
8716 4: make instructions conditional
8718 State transitions (state->state by whom under condition):
8719 0 -> 1 final_prescan_insn if the `target' is a label
8720 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8721 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8722 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8723 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8724 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8725 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8726 (the target insn is arm_target_insn).
8728 If the jump clobbers the conditions then we use states 2 and 4.
8730 A similar thing can be done with conditional return insns.
8732 XXX In case the `target' is an unconditional branch, this conditionalising
8733 of the instructions always reduces code size, but not always execution
8734 time. But then, I want to reduce the code size to somewhere near what
8735 /bin/cc produces. */
8737 /* Returns the index of the ARM condition code string in
8738 `arm_condition_codes'. COMPARISON should be an rtx like
8739 `(eq (...) (...))'. */
8741 static enum arm_cond_code
8742 get_arm_condition_code (comparison
)
8745 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
8747 enum rtx_code comp_code
= GET_CODE (comparison
);
8749 if (GET_MODE_CLASS (mode
) != MODE_CC
)
8750 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
8751 XEXP (comparison
, 1));
8755 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
8756 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
8757 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
8758 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
8759 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
8760 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
8761 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
8762 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
8763 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
8764 case CC_DLTUmode
: code
= ARM_CC
;
8767 if (comp_code
!= EQ
&& comp_code
!= NE
)
8770 if (comp_code
== EQ
)
8771 return ARM_INVERSE_CONDITION_CODE (code
);
8777 case NE
: return ARM_NE
;
8778 case EQ
: return ARM_EQ
;
8779 case GE
: return ARM_PL
;
8780 case LT
: return ARM_MI
;
8787 case NE
: return ARM_NE
;
8788 case EQ
: return ARM_EQ
;
8794 /* These encodings assume that AC=1 in the FPA system control
8795 byte. This allows us to handle all cases except UNEQ and
8799 case GE
: return ARM_GE
;
8800 case GT
: return ARM_GT
;
8801 case LE
: return ARM_LS
;
8802 case LT
: return ARM_MI
;
8803 case NE
: return ARM_NE
;
8804 case EQ
: return ARM_EQ
;
8805 case ORDERED
: return ARM_VC
;
8806 case UNORDERED
: return ARM_VS
;
8807 case UNLT
: return ARM_LT
;
8808 case UNLE
: return ARM_LE
;
8809 case UNGT
: return ARM_HI
;
8810 case UNGE
: return ARM_PL
;
8811 /* UNEQ and LTGT do not have a representation. */
8812 case UNEQ
: /* Fall through. */
8813 case LTGT
: /* Fall through. */
8820 case NE
: return ARM_NE
;
8821 case EQ
: return ARM_EQ
;
8822 case GE
: return ARM_LE
;
8823 case GT
: return ARM_LT
;
8824 case LE
: return ARM_GE
;
8825 case LT
: return ARM_GT
;
8826 case GEU
: return ARM_LS
;
8827 case GTU
: return ARM_CC
;
8828 case LEU
: return ARM_CS
;
8829 case LTU
: return ARM_HI
;
8836 case LTU
: return ARM_CS
;
8837 case GEU
: return ARM_CC
;
8844 case NE
: return ARM_NE
;
8845 case EQ
: return ARM_EQ
;
8846 case GE
: return ARM_GE
;
8847 case GT
: return ARM_GT
;
8848 case LE
: return ARM_LE
;
8849 case LT
: return ARM_LT
;
8850 case GEU
: return ARM_CS
;
8851 case GTU
: return ARM_HI
;
8852 case LEU
: return ARM_LS
;
8853 case LTU
: return ARM_CC
;
8865 arm_final_prescan_insn (insn
)
8868 /* BODY will hold the body of INSN. */
8869 rtx body
= PATTERN (insn
);
8871 /* This will be 1 if trying to repeat the trick, and things need to be
8872 reversed if it appears to fail. */
8875 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8876 taken are clobbered, even if the rtl suggests otherwise. It also
8877 means that we have to grub around within the jump expression to find
8878 out what the conditions are when the jump isn't taken. */
8879 int jump_clobbers
= 0;
8881 /* If we start with a return insn, we only succeed if we find another one. */
8882 int seeking_return
= 0;
8884 /* START_INSN will hold the insn from where we start looking. This is the
8885 first insn after the following code_label if REVERSE is true. */
8886 rtx start_insn
= insn
;
8888 /* If in state 4, check if the target branch is reached, in order to
8889 change back to state 0. */
8890 if (arm_ccfsm_state
== 4)
8892 if (insn
== arm_target_insn
)
8894 arm_target_insn
= NULL
;
8895 arm_ccfsm_state
= 0;
8900 /* If in state 3, it is possible to repeat the trick, if this insn is an
8901 unconditional branch to a label, and immediately following this branch
8902 is the previous target label which is only used once, and the label this
8903 branch jumps to is not too far off. */
8904 if (arm_ccfsm_state
== 3)
8906 if (simplejump_p (insn
))
8908 start_insn
= next_nonnote_insn (start_insn
);
8909 if (GET_CODE (start_insn
) == BARRIER
)
8911 /* XXX Isn't this always a barrier? */
8912 start_insn
= next_nonnote_insn (start_insn
);
8914 if (GET_CODE (start_insn
) == CODE_LABEL
8915 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8916 && LABEL_NUSES (start_insn
) == 1)
8921 else if (GET_CODE (body
) == RETURN
)
8923 start_insn
= next_nonnote_insn (start_insn
);
8924 if (GET_CODE (start_insn
) == BARRIER
)
8925 start_insn
= next_nonnote_insn (start_insn
);
8926 if (GET_CODE (start_insn
) == CODE_LABEL
8927 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8928 && LABEL_NUSES (start_insn
) == 1)
8940 if (arm_ccfsm_state
!= 0 && !reverse
)
8942 if (GET_CODE (insn
) != JUMP_INSN
)
8945 /* This jump might be paralleled with a clobber of the condition codes
8946 the jump should always come first */
8947 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
8948 body
= XVECEXP (body
, 0, 0);
8951 /* If this is a conditional return then we don't want to know */
8952 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8953 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
8954 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
8955 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
8960 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8961 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
8964 int fail
= FALSE
, succeed
= FALSE
;
8965 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8966 int then_not_else
= TRUE
;
8967 rtx this_insn
= start_insn
, label
= 0;
8969 /* If the jump cannot be done with one instruction, we cannot
8970 conditionally execute the instruction in the inverse case. */
8971 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
8977 /* Register the insn jumped to. */
8980 if (!seeking_return
)
8981 label
= XEXP (SET_SRC (body
), 0);
8983 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
8984 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
8985 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
8987 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
8988 then_not_else
= FALSE
;
8990 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
8992 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
8995 then_not_else
= FALSE
;
9000 /* See how many insns this branch skips, and what kind of insns. If all
9001 insns are okay, and the label or unconditional branch to the same
9002 label is not too far away, succeed. */
9003 for (insns_skipped
= 0;
9004 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
9008 this_insn
= next_nonnote_insn (this_insn
);
9012 switch (GET_CODE (this_insn
))
9015 /* Succeed if it is the target label, otherwise fail since
9016 control falls in from somewhere else. */
9017 if (this_insn
== label
)
9021 arm_ccfsm_state
= 2;
9022 this_insn
= next_nonnote_insn (this_insn
);
9025 arm_ccfsm_state
= 1;
9033 /* Succeed if the following insn is the target label.
9035 If return insns are used then the last insn in a function
9036 will be a barrier. */
9037 this_insn
= next_nonnote_insn (this_insn
);
9038 if (this_insn
&& this_insn
== label
)
9042 arm_ccfsm_state
= 2;
9043 this_insn
= next_nonnote_insn (this_insn
);
9046 arm_ccfsm_state
= 1;
9054 /* If using 32-bit addresses the cc is not preserved over
9058 /* Succeed if the following insn is the target label,
9059 or if the following two insns are a barrier and
9060 the target label. */
9061 this_insn
= next_nonnote_insn (this_insn
);
9062 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
9063 this_insn
= next_nonnote_insn (this_insn
);
9065 if (this_insn
&& this_insn
== label
9066 && insns_skipped
< max_insns_skipped
)
9070 arm_ccfsm_state
= 2;
9071 this_insn
= next_nonnote_insn (this_insn
);
9074 arm_ccfsm_state
= 1;
9083 /* If this is an unconditional branch to the same label, succeed.
9084 If it is to another label, do nothing. If it is conditional,
9086 /* XXX Probably, the tests for SET and the PC are unnecessary. */
9088 scanbody
= PATTERN (this_insn
);
9089 if (GET_CODE (scanbody
) == SET
9090 && GET_CODE (SET_DEST (scanbody
)) == PC
)
9092 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
9093 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
9095 arm_ccfsm_state
= 2;
9098 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
9101 /* Fail if a conditional return is undesirable (eg on a
9102 StrongARM), but still allow this if optimizing for size. */
9103 else if (GET_CODE (scanbody
) == RETURN
9104 && !use_return_insn (TRUE
)
9107 else if (GET_CODE (scanbody
) == RETURN
9110 arm_ccfsm_state
= 2;
9113 else if (GET_CODE (scanbody
) == PARALLEL
)
9115 switch (get_attr_conds (this_insn
))
9125 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
9130 /* Instructions using or affecting the condition codes make it
9132 scanbody
= PATTERN (this_insn
);
9133 if (!(GET_CODE (scanbody
) == SET
9134 || GET_CODE (scanbody
) == PARALLEL
)
9135 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
9145 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
9146 arm_target_label
= CODE_LABEL_NUMBER (label
);
9147 else if (seeking_return
|| arm_ccfsm_state
== 2)
9149 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
9151 this_insn
= next_nonnote_insn (this_insn
);
9152 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
9153 || GET_CODE (this_insn
) == CODE_LABEL
))
9158 /* Oh, dear! we ran off the end.. give up */
9159 recog (PATTERN (insn
), insn
, NULL
);
9160 arm_ccfsm_state
= 0;
9161 arm_target_insn
= NULL
;
9164 arm_target_insn
= this_insn
;
9173 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
9175 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
9176 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9177 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
9178 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9182 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
9185 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
9189 if (reverse
|| then_not_else
)
9190 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9193 /* Restore recog_data (getting the attributes of other insns can
9194 destroy this array, but final.c assumes that it remains intact
9195 across this call; since the insn has been recognized already we
9196 call recog direct). */
9197 recog (PATTERN (insn
), insn
, NULL
);
9201 /* Returns true if REGNO is a valid register
9202 for holding a quantity of tyoe MODE. */
9205 arm_hard_regno_mode_ok (regno
, mode
)
9207 enum machine_mode mode
;
9209 if (GET_MODE_CLASS (mode
) == MODE_CC
)
9210 return regno
== CC_REGNUM
;
9213 /* For the Thumb we only allow values bigger than SImode in
9214 registers 0 - 6, so that there is always a second low
9215 register available to hold the upper part of the value.
9216 We probably we ought to ensure that the register is the
9217 start of an even numbered register pair. */
9218 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
9220 if (regno
<= LAST_ARM_REGNUM
)
9221 /* We allow any value to be stored in the general regisetrs. */
9224 if ( regno
== FRAME_POINTER_REGNUM
9225 || regno
== ARG_POINTER_REGNUM
)
9226 /* We only allow integers in the fake hard registers. */
9227 return GET_MODE_CLASS (mode
) == MODE_INT
;
9229 /* The only registers left are the FPU registers
9230 which we only allow to hold FP values. */
9231 return GET_MODE_CLASS (mode
) == MODE_FLOAT
9232 && regno
>= FIRST_ARM_FP_REGNUM
9233 && regno
<= LAST_ARM_FP_REGNUM
;
9237 arm_regno_class (regno
)
9242 if (regno
== STACK_POINTER_REGNUM
)
9244 if (regno
== CC_REGNUM
)
9251 if ( regno
<= LAST_ARM_REGNUM
9252 || regno
== FRAME_POINTER_REGNUM
9253 || regno
== ARG_POINTER_REGNUM
)
9254 return GENERAL_REGS
;
9256 if (regno
== CC_REGNUM
)
9262 /* Handle a special case when computing the offset
9263 of an argument from the frame pointer. */
9266 arm_debugger_arg_offset (value
, addr
)
9272 /* We are only interested if dbxout_parms() failed to compute the offset. */
9276 /* We can only cope with the case where the address is held in a register. */
9277 if (GET_CODE (addr
) != REG
)
9280 /* If we are using the frame pointer to point at the argument, then
9281 an offset of 0 is correct. */
9282 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
9285 /* If we are using the stack pointer to point at the
9286 argument, then an offset of 0 is correct. */
9287 if ((TARGET_THUMB
|| !frame_pointer_needed
)
9288 && REGNO (addr
) == SP_REGNUM
)
9291 /* Oh dear. The argument is pointed to by a register rather
9292 than being held in a register, or being stored at a known
9293 offset from the frame pointer. Since GDB only understands
9294 those two kinds of argument we must translate the address
9295 held in the register into an offset from the frame pointer.
9296 We do this by searching through the insns for the function
9297 looking to see where this register gets its value. If the
9298 register is initialized from the frame pointer plus an offset
9299 then we are in luck and we can continue, otherwise we give up.
9301 This code is exercised by producing debugging information
9302 for a function with arguments like this:
9304 double func (double a, double b, int c, double d) {return d;}
9306 Without this code the stab for parameter 'd' will be set to
9307 an offset of 0 from the frame pointer, rather than 8. */
9309 /* The if() statement says:
9311 If the insn is a normal instruction
9312 and if the insn is setting the value in a register
9313 and if the register being set is the register holding the address of the argument
9314 and if the address is computing by an addition
9315 that involves adding to a register
9316 which is the frame pointer
9321 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9323 if ( GET_CODE (insn
) == INSN
9324 && GET_CODE (PATTERN (insn
)) == SET
9325 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
9326 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
9327 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
9328 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9329 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
9332 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
9341 warning ("unable to compute real location of stacked parameter");
9342 value
= 8; /* XXX magic hack */
9348 #define def_builtin(NAME, TYPE, CODE) \
9349 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE)
9352 arm_init_builtins ()
9354 tree endlink
= void_list_node
;
9355 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
9356 tree pchar_type_node
= build_pointer_type (char_type_node
);
9358 tree int_ftype_int
, void_ftype_pchar
;
9360 /* void func (char *) */
9362 = build_function_type_list (void_type_node
, pchar_type_node
, NULL_TREE
);
9364 /* int func (int) */
9366 = build_function_type (integer_type_node
, int_endlink
);
9368 /* Initialize arm V5 builtins. */
9370 def_builtin ("__builtin_clz", int_ftype_int
, ARM_BUILTIN_CLZ
);
9373 /* Expand an expression EXP that calls a built-in function,
9374 with result going to TARGET if that's convenient
9375 (and in mode MODE if that's convenient).
9376 SUBTARGET may be used as the target for computing one of EXP's operands.
9377 IGNORE is nonzero if the value is to be ignored. */
9380 arm_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9383 rtx subtarget ATTRIBUTE_UNUSED
;
9384 enum machine_mode mode ATTRIBUTE_UNUSED
;
9385 int ignore ATTRIBUTE_UNUSED
;
9387 enum insn_code icode
;
9388 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9389 tree arglist
= TREE_OPERAND (exp
, 1);
9392 enum machine_mode tmode
, mode0
;
9393 int fcode
= DECL_FUNCTION_CODE (fndecl
);
9400 case ARM_BUILTIN_CLZ
:
9401 icode
= CODE_FOR_clz
;
9402 arg0
= TREE_VALUE (arglist
);
9403 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
9404 tmode
= insn_data
[icode
].operand
[0].mode
;
9405 mode0
= insn_data
[icode
].operand
[1].mode
;
9407 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9408 op0
= copy_to_mode_reg (mode0
, op0
);
9410 || GET_MODE (target
) != tmode
9411 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9412 target
= gen_reg_rtx (tmode
);
9413 pat
= GEN_FCN (icode
) (target
, op0
);
9420 /* @@@ Should really do something sensible here. */
9424 /* Recursively search through all of the blocks in a function
9425 checking to see if any of the variables created in that
9426 function match the RTX called 'orig'. If they do then
9427 replace them with the RTX called 'new'. */
9430 replace_symbols_in_block (block
, orig
, new)
9435 for (; block
; block
= BLOCK_CHAIN (block
))
9439 if (!TREE_USED (block
))
9442 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
9444 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
9445 || DECL_IGNORED_P (sym
)
9446 || TREE_CODE (sym
) != VAR_DECL
9447 || DECL_EXTERNAL (sym
)
9448 || !rtx_equal_p (DECL_RTL (sym
), orig
)
9452 SET_DECL_RTL (sym
, new);
9455 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
9459 /* Return the number (counting from 0) of
9460 the least significant set bit in MASK. */
9466 number_of_first_bit_set (mask
)
9472 (mask
& (1 << bit
)) == 0;
9479 /* Generate code to return from a thumb function.
9480 If 'reg_containing_return_addr' is -1, then the return address is
9481 actually on the stack, at the stack pointer. */
9483 thumb_exit (f
, reg_containing_return_addr
, eh_ofs
)
9485 int reg_containing_return_addr
;
9488 unsigned regs_available_for_popping
;
9489 unsigned regs_to_pop
;
9495 int restore_a4
= FALSE
;
9497 /* Compute the registers we need to pop. */
9501 /* There is an assumption here, that if eh_ofs is not NULL, the
9502 normal return address will have been pushed. */
9503 if (reg_containing_return_addr
== -1 || eh_ofs
)
9505 /* When we are generating a return for __builtin_eh_return,
9506 reg_containing_return_addr must specify the return regno. */
9507 if (eh_ofs
&& reg_containing_return_addr
== -1)
9510 regs_to_pop
|= 1 << LR_REGNUM
;
9514 if (TARGET_BACKTRACE
)
9516 /* Restore the (ARM) frame pointer and stack pointer. */
9517 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
9521 /* If there is nothing to pop then just emit the BX instruction and
9523 if (pops_needed
== 0)
9526 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9528 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9531 /* Otherwise if we are not supporting interworking and we have not created
9532 a backtrace structure and the function was not entered in ARM mode then
9533 just pop the return address straight into the PC. */
9534 else if (!TARGET_INTERWORK
9535 && !TARGET_BACKTRACE
9536 && !is_called_in_ARM_mode (current_function_decl
))
9540 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
9541 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9542 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9545 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
9550 /* Find out how many of the (return) argument registers we can corrupt. */
9551 regs_available_for_popping
= 0;
9553 /* If returning via __builtin_eh_return, the bottom three registers
9554 all contain information needed for the return. */
9560 /* If we can deduce the registers used from the function's
9561 return value. This is more reliable that examining
9562 regs_ever_live[] because that will be set if the register is
9563 ever used in the function, not just if the register is used
9564 to hold a return value. */
9566 if (current_function_return_rtx
!= 0)
9567 mode
= GET_MODE (current_function_return_rtx
);
9570 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9572 size
= GET_MODE_SIZE (mode
);
9576 /* In a void function we can use any argument register.
9577 In a function that returns a structure on the stack
9578 we can use the second and third argument registers. */
9579 if (mode
== VOIDmode
)
9580 regs_available_for_popping
=
9581 (1 << ARG_REGISTER (1))
9582 | (1 << ARG_REGISTER (2))
9583 | (1 << ARG_REGISTER (3));
9585 regs_available_for_popping
=
9586 (1 << ARG_REGISTER (2))
9587 | (1 << ARG_REGISTER (3));
9590 regs_available_for_popping
=
9591 (1 << ARG_REGISTER (2))
9592 | (1 << ARG_REGISTER (3));
9594 regs_available_for_popping
=
9595 (1 << ARG_REGISTER (3));
9598 /* Match registers to be popped with registers into which we pop them. */
9599 for (available
= regs_available_for_popping
,
9600 required
= regs_to_pop
;
9601 required
!= 0 && available
!= 0;
9602 available
&= ~(available
& - available
),
9603 required
&= ~(required
& - required
))
9606 /* If we have any popping registers left over, remove them. */
9608 regs_available_for_popping
&= ~available
;
9610 /* Otherwise if we need another popping register we can use
9611 the fourth argument register. */
9612 else if (pops_needed
)
9614 /* If we have not found any free argument registers and
9615 reg a4 contains the return address, we must move it. */
9616 if (regs_available_for_popping
== 0
9617 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
9619 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9620 reg_containing_return_addr
= LR_REGNUM
;
9624 /* Register a4 is being used to hold part of the return value,
9625 but we have dire need of a free, low register. */
9628 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
9631 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
9633 /* The fourth argument register is available. */
9634 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
9640 /* Pop as many registers as we can. */
9641 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9643 /* Process the registers we popped. */
9644 if (reg_containing_return_addr
== -1)
9646 /* The return address was popped into the lowest numbered register. */
9647 regs_to_pop
&= ~(1 << LR_REGNUM
);
9649 reg_containing_return_addr
=
9650 number_of_first_bit_set (regs_available_for_popping
);
9652 /* Remove this register for the mask of available registers, so that
9653 the return address will not be corrupted by futher pops. */
9654 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
9657 /* If we popped other registers then handle them here. */
9658 if (regs_available_for_popping
)
9662 /* Work out which register currently contains the frame pointer. */
9663 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9665 /* Move it into the correct place. */
9666 asm_fprintf (f
, "\tmov\t%r, %r\n",
9667 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
9669 /* (Temporarily) remove it from the mask of popped registers. */
9670 regs_available_for_popping
&= ~(1 << frame_pointer
);
9671 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
9673 if (regs_available_for_popping
)
9677 /* We popped the stack pointer as well,
9678 find the register that contains it. */
9679 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9681 /* Move it into the stack register. */
9682 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
9684 /* At this point we have popped all necessary registers, so
9685 do not worry about restoring regs_available_for_popping
9686 to its correct value:
9688 assert (pops_needed == 0)
9689 assert (regs_available_for_popping == (1 << frame_pointer))
9690 assert (regs_to_pop == (1 << STACK_POINTER)) */
9694 /* Since we have just move the popped value into the frame
9695 pointer, the popping register is available for reuse, and
9696 we know that we still have the stack pointer left to pop. */
9697 regs_available_for_popping
|= (1 << frame_pointer
);
9701 /* If we still have registers left on the stack, but we no longer have
9702 any registers into which we can pop them, then we must move the return
9703 address into the link register and make available the register that
9705 if (regs_available_for_popping
== 0 && pops_needed
> 0)
9707 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
9709 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
9710 reg_containing_return_addr
);
9712 reg_containing_return_addr
= LR_REGNUM
;
9715 /* If we have registers left on the stack then pop some more.
9716 We know that at most we will want to pop FP and SP. */
9717 if (pops_needed
> 0)
9722 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9724 /* We have popped either FP or SP.
9725 Move whichever one it is into the correct register. */
9726 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9727 move_to
= number_of_first_bit_set (regs_to_pop
);
9729 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
9731 regs_to_pop
&= ~(1 << move_to
);
9736 /* If we still have not popped everything then we must have only
9737 had one register available to us and we are now popping the SP. */
9738 if (pops_needed
> 0)
9742 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9744 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9746 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
9748 assert (regs_to_pop == (1 << STACK_POINTER))
9749 assert (pops_needed == 1)
9753 /* If necessary restore the a4 register. */
9756 if (reg_containing_return_addr
!= LR_REGNUM
)
9758 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9759 reg_containing_return_addr
= LR_REGNUM
;
9762 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
9766 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9768 /* Return to caller. */
9769 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9772 /* Emit code to push or pop registers to or from the stack. */
9775 thumb_pushpop (f
, mask
, push
)
9781 int lo_mask
= mask
& 0xFF;
9783 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
9785 /* Special case. Do not generate a POP PC statement here, do it in
9787 thumb_exit (f
, -1, NULL_RTX
);
9791 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
9793 /* Look at the low registers first. */
9794 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
9798 asm_fprintf (f
, "%r", regno
);
9800 if ((lo_mask
& ~1) != 0)
9805 if (push
&& (mask
& (1 << LR_REGNUM
)))
9807 /* Catch pushing the LR. */
9811 asm_fprintf (f
, "%r", LR_REGNUM
);
9813 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
9815 /* Catch popping the PC. */
9816 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
9818 /* The PC is never poped directly, instead
9819 it is popped into r3 and then BX is used. */
9822 thumb_exit (f
, -1, NULL_RTX
);
9831 asm_fprintf (f
, "%r", PC_REGNUM
);
9839 thumb_final_prescan_insn (insn
)
9842 if (flag_print_asm_name
)
9843 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
9844 INSN_ADDRESSES (INSN_UID (insn
)));
9848 thumb_shiftable_const (val
)
9849 unsigned HOST_WIDE_INT val
;
9851 unsigned HOST_WIDE_INT mask
= 0xff;
9854 if (val
== 0) /* XXX */
9857 for (i
= 0; i
< 25; i
++)
9858 if ((val
& (mask
<< i
)) == val
)
9864 /* Returns non-zero if the current function contains,
9865 or might contain a far jump. */
9868 thumb_far_jump_used_p (in_prologue
)
9873 /* This test is only important for leaf functions. */
9874 /* assert (!leaf_function_p ()); */
9876 /* If we have already decided that far jumps may be used,
9877 do not bother checking again, and always return true even if
9878 it turns out that they are not being used. Once we have made
9879 the decision that far jumps are present (and that hence the link
9880 register will be pushed onto the stack) we cannot go back on it. */
9881 if (cfun
->machine
->far_jump_used
)
9884 /* If this function is not being called from the prologue/epilogue
9885 generation code then it must be being called from the
9886 INITIAL_ELIMINATION_OFFSET macro. */
9889 /* In this case we know that we are being asked about the elimination
9890 of the arg pointer register. If that register is not being used,
9891 then there are no arguments on the stack, and we do not have to
9892 worry that a far jump might force the prologue to push the link
9893 register, changing the stack offsets. In this case we can just
9894 return false, since the presence of far jumps in the function will
9895 not affect stack offsets.
9897 If the arg pointer is live (or if it was live, but has now been
9898 eliminated and so set to dead) then we do have to test to see if
9899 the function might contain a far jump. This test can lead to some
9900 false negatives, since before reload is completed, then length of
9901 branch instructions is not known, so gcc defaults to returning their
9902 longest length, which in turn sets the far jump attribute to true.
9904 A false negative will not result in bad code being generated, but it
9905 will result in a needless push and pop of the link register. We
9906 hope that this does not occur too often. */
9907 if (regs_ever_live
[ARG_POINTER_REGNUM
])
9908 cfun
->machine
->arg_pointer_live
= 1;
9909 else if (!cfun
->machine
->arg_pointer_live
)
9913 /* Check to see if the function contains a branch
9914 insn with the far jump attribute set. */
9915 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9917 if (GET_CODE (insn
) == JUMP_INSN
9918 /* Ignore tablejump patterns. */
9919 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
9920 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
9921 && get_attr_far_jump (insn
) == FAR_JUMP_YES
9924 /* Record the fact that we have decied that
9925 the function does use far jumps. */
9926 cfun
->machine
->far_jump_used
= 1;
9934 /* Return non-zero if FUNC must be entered in ARM mode. */
9937 is_called_in_ARM_mode (func
)
9940 if (TREE_CODE (func
) != FUNCTION_DECL
)
9943 /* Ignore the problem about functions whoes address is taken. */
9944 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
9948 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
9954 /* The bits which aren't usefully expanded as rtl. */
9957 thumb_unexpanded_epilogue ()
9960 int live_regs_mask
= 0;
9961 int high_regs_pushed
= 0;
9962 int leaf_function
= leaf_function_p ();
9964 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9966 if (return_used_this_function
)
9969 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
9970 if (THUMB_REG_PUSHED_P (regno
))
9971 live_regs_mask
|= 1 << regno
;
9973 for (regno
= 8; regno
< 13; regno
++)
9974 if (THUMB_REG_PUSHED_P (regno
))
9977 /* The prolog may have pushed some high registers to use as
9978 work registers. eg the testuite file:
9979 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9980 compiles to produce:
9981 push {r4, r5, r6, r7, lr}
9985 as part of the prolog. We have to undo that pushing here. */
9987 if (high_regs_pushed
)
9989 int mask
= live_regs_mask
;
9995 /* If we can deduce the registers used from the function's return value.
9996 This is more reliable that examining regs_ever_live[] because that
9997 will be set if the register is ever used in the function, not just if
9998 the register is used to hold a return value. */
10000 if (current_function_return_rtx
!= 0)
10001 mode
= GET_MODE (current_function_return_rtx
);
10004 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10006 size
= GET_MODE_SIZE (mode
);
10008 /* Unless we are returning a type of size > 12 register r3 is
10014 /* Oh dear! We have no low registers into which we can pop
10017 ("no low registers available for popping high registers");
10019 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
10020 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10023 while (high_regs_pushed
)
10025 /* Find lo register(s) into which the high register(s) can
10027 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10029 if (mask
& (1 << regno
))
10030 high_regs_pushed
--;
10031 if (high_regs_pushed
== 0)
10035 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
10037 /* Pop the values into the low register(s). */
10038 thumb_pushpop (asm_out_file
, mask
, 0);
10040 /* Move the value(s) into the high registers. */
10041 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10043 if (mask
& (1 << regno
))
10045 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
10048 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
10049 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10056 had_to_push_lr
= (live_regs_mask
|| !leaf_function
10057 || thumb_far_jump_used_p (1));
10059 if (TARGET_BACKTRACE
10060 && ((live_regs_mask
& 0xFF) == 0)
10061 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
10063 /* The stack backtrace structure creation code had to
10064 push R7 in order to get a work register, so we pop
10066 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10069 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
10072 && !is_called_in_ARM_mode (current_function_decl
)
10074 live_regs_mask
|= 1 << PC_REGNUM
;
10076 /* Either no argument registers were pushed or a backtrace
10077 structure was created which includes an adjusted stack
10078 pointer, so just pop everything. */
10079 if (live_regs_mask
)
10080 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10083 thumb_exit (asm_out_file
, 2, eh_ofs
);
10084 /* We have either just popped the return address into the
10085 PC or it is was kept in LR for the entire function or
10086 it is still on the stack because we do not want to
10087 return by doing a pop {pc}. */
10088 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
10089 thumb_exit (asm_out_file
,
10091 && is_called_in_ARM_mode (current_function_decl
)) ?
10092 -1 : LR_REGNUM
, NULL_RTX
);
10096 /* Pop everything but the return address. */
10097 live_regs_mask
&= ~(1 << PC_REGNUM
);
10099 if (live_regs_mask
)
10100 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10102 if (had_to_push_lr
)
10103 /* Get the return address into a temporary register. */
10104 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
10106 /* Remove the argument registers that were pushed onto the stack. */
10107 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
10108 SP_REGNUM
, SP_REGNUM
,
10109 current_function_pretend_args_size
);
10112 thumb_exit (asm_out_file
, 2, eh_ofs
);
10114 thumb_exit (asm_out_file
,
10115 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
10121 /* Functions to save and restore machine-specific function data. */
10123 static struct machine_function
*
10124 arm_init_machine_status ()
10126 struct machine_function
*machine
;
10127 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
10129 #if ARM_FT_UNKNOWN != 0
10130 machine
->func_type
= ARM_FT_UNKNOWN
;
10135 /* Return an RTX indicating where the return address to the
10136 calling function can be found. */
10139 arm_return_addr (count
, frame
)
10141 rtx frame ATTRIBUTE_UNUSED
;
10146 if (TARGET_APCS_32
)
10147 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
10150 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
10151 GEN_INT (RETURN_ADDR_MASK26
));
10152 return get_func_hard_reg_initial_val (cfun
, lr
);
10156 /* Do anything needed before RTL is emitted for each function. */
10159 arm_init_expanders ()
10161 /* Arrange to initialize and mark the machine per-function status. */
10162 init_machine_status
= arm_init_machine_status
;
10165 /* Generate the rest of a function's prologue. */
10168 thumb_expand_prologue ()
10170 HOST_WIDE_INT amount
= (get_frame_size ()
10171 + current_function_outgoing_args_size
);
10172 unsigned long func_type
;
10174 func_type
= arm_current_func_type ();
10176 /* Naked functions don't have prologues. */
10177 if (IS_NAKED (func_type
))
10180 if (IS_INTERRUPT (func_type
))
10182 error ("interrupt Service Routines cannot be coded in Thumb mode");
10186 if (frame_pointer_needed
)
10187 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
10191 amount
= ROUND_UP (amount
);
10194 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10195 GEN_INT (- amount
)));
10201 /* The stack decrement is too big for an immediate value in a single
10202 insn. In theory we could issue multiple subtracts, but after
10203 three of them it becomes more space efficient to place the full
10204 value in the constant pool and load into a register. (Also the
10205 ARM debugger really likes to see only one stack decrement per
10206 function). So instead we look for a scratch register into which
10207 we can load the decrement, and then we subtract this from the
10208 stack pointer. Unfortunately on the thumb the only available
10209 scratch registers are the argument registers, and we cannot use
10210 these as they may hold arguments to the function. Instead we
10211 attempt to locate a call preserved register which is used by this
10212 function. If we can find one, then we know that it will have
10213 been pushed at the start of the prologue and so we can corrupt
10215 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
10216 if (THUMB_REG_PUSHED_P (regno
)
10217 && !(frame_pointer_needed
10218 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
10221 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
10223 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
10225 /* Choose an arbitary, non-argument low register. */
10226 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
10228 /* Save it by copying it into a high, scratch register. */
10229 emit_insn (gen_movsi (spare
, reg
));
10230 /* Add a USE to stop propagate_one_insn() from barfing. */
10231 emit_insn (gen_prologue_use (spare
));
10233 /* Decrement the stack. */
10234 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10235 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10238 /* Restore the low register's original value. */
10239 emit_insn (gen_movsi (reg
, spare
));
10241 /* Emit a USE of the restored scratch register, so that flow
10242 analysis will not consider the restore redundant. The
10243 register won't be used again in this function and isn't
10244 restored by the epilogue. */
10245 emit_insn (gen_prologue_use (reg
));
10249 reg
= gen_rtx (REG
, SImode
, regno
);
10251 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10252 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10258 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10259 emit_insn (gen_blockage ());
10263 thumb_expand_epilogue ()
10265 HOST_WIDE_INT amount
= (get_frame_size ()
10266 + current_function_outgoing_args_size
);
10268 /* Naked functions don't have prologues. */
10269 if (IS_NAKED (arm_current_func_type ()))
10272 if (frame_pointer_needed
)
10273 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
10276 amount
= ROUND_UP (amount
);
10279 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10280 GEN_INT (amount
)));
10283 /* r3 is always free in the epilogue. */
10284 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
10286 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
10287 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
10291 /* Emit a USE (stack_pointer_rtx), so that
10292 the stack adjustment will not be deleted. */
10293 emit_insn (gen_prologue_use (stack_pointer_rtx
));
10295 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10296 emit_insn (gen_blockage ());
10300 thumb_output_function_prologue (f
, size
)
10302 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
10304 int live_regs_mask
= 0;
10305 int high_regs_pushed
= 0;
10308 if (IS_NAKED (arm_current_func_type ()))
10311 if (is_called_in_ARM_mode (current_function_decl
))
10315 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
10317 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
10319 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10321 /* Generate code sequence to switch us into Thumb mode. */
10322 /* The .code 32 directive has already been emitted by
10323 ASM_DECLARE_FUNCTION_NAME. */
10324 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
10325 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
10327 /* Generate a label, so that the debugger will notice the
10328 change in instruction sets. This label is also used by
10329 the assembler to bypass the ARM code when this function
10330 is called from a Thumb encoded function elsewhere in the
10331 same file. Hence the definition of STUB_NAME here must
10332 agree with the definition in gas/config/tc-arm.c */
10334 #define STUB_NAME ".real_start_of"
10336 fprintf (f
, "\t.code\t16\n");
10338 if (arm_dllexport_name_p (name
))
10339 name
= arm_strip_name_encoding (name
);
10341 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
10342 fprintf (f
, "\t.thumb_func\n");
10343 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
10346 if (current_function_pretend_args_size
)
10348 if (cfun
->machine
->uses_anonymous_args
)
10352 fprintf (f
, "\tpush\t{");
10354 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
10356 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
10357 regno
<= LAST_ARG_REGNUM
;
10359 asm_fprintf (f
, "%r%s", regno
,
10360 regno
== LAST_ARG_REGNUM
? "" : ", ");
10362 fprintf (f
, "}\n");
10365 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
10366 SP_REGNUM
, SP_REGNUM
,
10367 current_function_pretend_args_size
);
10370 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10371 if (THUMB_REG_PUSHED_P (regno
))
10372 live_regs_mask
|= 1 << regno
;
10374 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
10375 live_regs_mask
|= 1 << LR_REGNUM
;
10377 if (TARGET_BACKTRACE
)
10380 int work_register
= 0;
10383 /* We have been asked to create a stack backtrace structure.
10384 The code looks like this:
10388 0 sub SP, #16 Reserve space for 4 registers.
10389 2 push {R7} Get a work register.
10390 4 add R7, SP, #20 Get the stack pointer before the push.
10391 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10392 8 mov R7, PC Get hold of the start of this code plus 12.
10393 10 str R7, [SP, #16] Store it.
10394 12 mov R7, FP Get hold of the current frame pointer.
10395 14 str R7, [SP, #4] Store it.
10396 16 mov R7, LR Get hold of the current return address.
10397 18 str R7, [SP, #12] Store it.
10398 20 add R7, SP, #16 Point at the start of the backtrace structure.
10399 22 mov FP, R7 Put this value into the frame pointer. */
10401 if ((live_regs_mask
& 0xFF) == 0)
10403 /* See if the a4 register is free. */
10405 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
10406 work_register
= LAST_ARG_REGNUM
;
10407 else /* We must push a register of our own */
10408 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10411 if (work_register
== 0)
10413 /* Select a register from the list that will be pushed to
10414 use as our work register. */
10415 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
10416 if ((1 << work_register
) & live_regs_mask
)
10421 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10422 SP_REGNUM
, SP_REGNUM
);
10424 if (live_regs_mask
)
10425 thumb_pushpop (f
, live_regs_mask
, 1);
10427 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
10428 if (wr
& live_regs_mask
)
10431 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10432 offset
+ 16 + current_function_pretend_args_size
);
10434 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10437 /* Make sure that the instruction fetching the PC is in the right place
10438 to calculate "start of backtrace creation code + 12". */
10439 if (live_regs_mask
)
10441 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10442 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10444 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10445 ARM_HARD_FRAME_POINTER_REGNUM
);
10446 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10451 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10452 ARM_HARD_FRAME_POINTER_REGNUM
);
10453 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10455 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10456 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10460 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
10461 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10463 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10465 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10466 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
10468 else if (live_regs_mask
)
10469 thumb_pushpop (f
, live_regs_mask
, 1);
10471 for (regno
= 8; regno
< 13; regno
++)
10472 if (THUMB_REG_PUSHED_P (regno
))
10473 high_regs_pushed
++;
10475 if (high_regs_pushed
)
10477 int pushable_regs
= 0;
10478 int mask
= live_regs_mask
& 0xff;
10481 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
10482 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10485 pushable_regs
= mask
;
10487 if (pushable_regs
== 0)
10489 /* Desperation time -- this probably will never happen. */
10490 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
10491 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
10492 mask
= 1 << LAST_ARG_REGNUM
;
10495 while (high_regs_pushed
> 0)
10497 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
10499 if (mask
& (1 << regno
))
10501 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
10503 high_regs_pushed
--;
10505 if (high_regs_pushed
)
10507 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
10509 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10514 mask
&= ~((1 << regno
) - 1);
10520 thumb_pushpop (f
, mask
, 1);
10523 if (pushable_regs
== 0
10524 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
10525 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
10529 /* Handle the case of a double word load into a low register from
10530 a computed memory address. The computed address may involve a
10531 register which is overwritten by the load. */
10534 thumb_load_double_from_address (operands
)
10543 if (GET_CODE (operands
[0]) != REG
)
10546 if (GET_CODE (operands
[1]) != MEM
)
10549 /* Get the memory address. */
10550 addr
= XEXP (operands
[1], 0);
10552 /* Work out how the memory address is computed. */
10553 switch (GET_CODE (addr
))
10556 operands
[2] = gen_rtx (MEM
, SImode
,
10557 plus_constant (XEXP (operands
[1], 0), 4));
10559 if (REGNO (operands
[0]) == REGNO (addr
))
10561 output_asm_insn ("ldr\t%H0, %2", operands
);
10562 output_asm_insn ("ldr\t%0, %1", operands
);
10566 output_asm_insn ("ldr\t%0, %1", operands
);
10567 output_asm_insn ("ldr\t%H0, %2", operands
);
10572 /* Compute <address> + 4 for the high order load. */
10573 operands
[2] = gen_rtx (MEM
, SImode
,
10574 plus_constant (XEXP (operands
[1], 0), 4));
10576 output_asm_insn ("ldr\t%0, %1", operands
);
10577 output_asm_insn ("ldr\t%H0, %2", operands
);
10581 arg1
= XEXP (addr
, 0);
10582 arg2
= XEXP (addr
, 1);
10584 if (CONSTANT_P (arg1
))
10585 base
= arg2
, offset
= arg1
;
10587 base
= arg1
, offset
= arg2
;
10589 if (GET_CODE (base
) != REG
)
10592 /* Catch the case of <address> = <reg> + <reg> */
10593 if (GET_CODE (offset
) == REG
)
10595 int reg_offset
= REGNO (offset
);
10596 int reg_base
= REGNO (base
);
10597 int reg_dest
= REGNO (operands
[0]);
10599 /* Add the base and offset registers together into the
10600 higher destination register. */
10601 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
10602 reg_dest
+ 1, reg_base
, reg_offset
);
10604 /* Load the lower destination register from the address in
10605 the higher destination register. */
10606 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
10607 reg_dest
, reg_dest
+ 1);
10609 /* Load the higher destination register from its own address
10611 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
10612 reg_dest
+ 1, reg_dest
+ 1);
10616 /* Compute <address> + 4 for the high order load. */
10617 operands
[2] = gen_rtx (MEM
, SImode
,
10618 plus_constant (XEXP (operands
[1], 0), 4));
10620 /* If the computed address is held in the low order register
10621 then load the high order register first, otherwise always
10622 load the low order register first. */
10623 if (REGNO (operands
[0]) == REGNO (base
))
10625 output_asm_insn ("ldr\t%H0, %2", operands
);
10626 output_asm_insn ("ldr\t%0, %1", operands
);
10630 output_asm_insn ("ldr\t%0, %1", operands
);
10631 output_asm_insn ("ldr\t%H0, %2", operands
);
10637 /* With no registers to worry about we can just load the value
10639 operands
[2] = gen_rtx (MEM
, SImode
,
10640 plus_constant (XEXP (operands
[1], 0), 4));
10642 output_asm_insn ("ldr\t%H0, %2", operands
);
10643 output_asm_insn ("ldr\t%0, %1", operands
);
10656 thumb_output_move_mem_multiple (n
, operands
)
10665 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10668 operands
[4] = operands
[5];
10671 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
10672 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
10676 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10679 operands
[4] = operands
[5];
10682 if (REGNO (operands
[5]) > REGNO (operands
[6]))
10685 operands
[5] = operands
[6];
10688 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10691 operands
[4] = operands
[5];
10695 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
10696 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
10706 /* Routines for generating rtl. */
10709 thumb_expand_movstrqi (operands
)
10712 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
10713 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
10714 HOST_WIDE_INT len
= INTVAL (operands
[2]);
10715 HOST_WIDE_INT offset
= 0;
10719 emit_insn (gen_movmem12b (out
, in
, out
, in
));
10725 emit_insn (gen_movmem8b (out
, in
, out
, in
));
10731 rtx reg
= gen_reg_rtx (SImode
);
10732 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
10733 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
10740 rtx reg
= gen_reg_rtx (HImode
);
10741 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
10742 plus_constant (in
, offset
))));
10743 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
10751 rtx reg
= gen_reg_rtx (QImode
);
10752 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
10753 plus_constant (in
, offset
))));
10754 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
10760 thumb_cmp_operand (op
, mode
)
10762 enum machine_mode mode
;
10764 return ((GET_CODE (op
) == CONST_INT
10765 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
10766 || register_operand (op
, mode
));
10769 static const char *
10770 thumb_condition_code (x
, invert
)
10774 static const char * const conds
[] =
10776 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10777 "hi", "ls", "ge", "lt", "gt", "le"
10781 switch (GET_CODE (x
))
10783 case EQ
: val
= 0; break;
10784 case NE
: val
= 1; break;
10785 case GEU
: val
= 2; break;
10786 case LTU
: val
= 3; break;
10787 case GTU
: val
= 8; break;
10788 case LEU
: val
= 9; break;
10789 case GE
: val
= 10; break;
10790 case LT
: val
= 11; break;
10791 case GT
: val
= 12; break;
10792 case LE
: val
= 13; break;
10797 return conds
[val
^ invert
];
10800 /* Handle storing a half-word to memory during reload. */
10803 thumb_reload_out_hi (operands
)
10806 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
10809 /* Handle storing a half-word to memory during reload. */
10812 thumb_reload_in_hi (operands
)
10813 rtx
* operands ATTRIBUTE_UNUSED
;
10818 /* Return the length of a function name prefix
10819 that starts with the character 'c'. */
10822 arm_get_strip_length (c
)
10827 ARM_NAME_ENCODING_LENGTHS
10832 /* Return a pointer to a function's name with any
10833 and all prefix encodings stripped from it. */
10836 arm_strip_name_encoding (name
)
10841 while ((skip
= arm_get_strip_length (* name
)))
10847 /* If there is a '*' anywhere in the name's prefix, then
10848 emit the stripped name verbatim, otherwise prepend an
10849 underscore if leading underscores are being used. */
10852 arm_asm_output_labelref (stream
, name
)
10859 while ((skip
= arm_get_strip_length (* name
)))
10861 verbatim
|= (*name
== '*');
10866 fputs (name
, stream
);
10868 asm_fprintf (stream
, "%U%s", name
);
10873 #ifdef AOF_ASSEMBLER
10874 /* Special functions only needed when producing AOF syntax assembler. */
10878 struct pic_chain
* next
;
10879 const char * symname
;
10882 static struct pic_chain
* aof_pic_chain
= NULL
;
10888 struct pic_chain
** chainp
;
10891 if (aof_pic_label
== NULL_RTX
)
10893 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
10896 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
10897 offset
+= 4, chainp
= &(*chainp
)->next
)
10898 if ((*chainp
)->symname
== XSTR (x
, 0))
10899 return plus_constant (aof_pic_label
, offset
);
10901 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
10902 (*chainp
)->next
= NULL
;
10903 (*chainp
)->symname
= XSTR (x
, 0);
10904 return plus_constant (aof_pic_label
, offset
);
10908 aof_dump_pic_table (f
)
10911 struct pic_chain
* chain
;
10913 if (aof_pic_chain
== NULL
)
10916 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
10917 PIC_OFFSET_TABLE_REGNUM
,
10918 PIC_OFFSET_TABLE_REGNUM
);
10919 fputs ("|x$adcons|\n", f
);
10921 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
10923 fputs ("\tDCD\t", f
);
10924 assemble_name (f
, chain
->symname
);
10929 int arm_text_section_count
= 1;
10932 aof_text_section ()
10934 static char buf
[100];
10935 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
10936 arm_text_section_count
++);
10938 strcat (buf
, ", PIC, REENTRANT");
10942 static int arm_data_section_count
= 1;
10945 aof_data_section ()
10947 static char buf
[100];
10948 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
10952 /* The AOF assembler is religiously strict about declarations of
10953 imported and exported symbols, so that it is impossible to declare
10954 a function as imported near the beginning of the file, and then to
10955 export it later on. It is, however, possible to delay the decision
10956 until all the functions in the file have been compiled. To get
10957 around this, we maintain a list of the imports and exports, and
10958 delete from it any that are subsequently defined. At the end of
10959 compilation we spit the remainder of the list out before the END
10964 struct import
* next
;
10968 static struct import
* imports_list
= NULL
;
10971 aof_add_import (name
)
10974 struct import
* new;
10976 for (new = imports_list
; new; new = new->next
)
10977 if (new->name
== name
)
10980 new = (struct import
*) xmalloc (sizeof (struct import
));
10981 new->next
= imports_list
;
10982 imports_list
= new;
10987 aof_delete_import (name
)
10990 struct import
** old
;
10992 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
10994 if ((*old
)->name
== name
)
10996 *old
= (*old
)->next
;
11002 int arm_main_function
= 0;
11005 aof_dump_imports (f
)
11008 /* The AOF assembler needs this to cause the startup code to be extracted
11009 from the library. Brining in __main causes the whole thing to work
11011 if (arm_main_function
)
11014 fputs ("\tIMPORT __main\n", f
);
11015 fputs ("\tDCD __main\n", f
);
11018 /* Now dump the remaining imports. */
11019 while (imports_list
)
11021 fprintf (f
, "\tIMPORT\t");
11022 assemble_name (f
, imports_list
->name
);
11024 imports_list
= imports_list
->next
;
11029 aof_globalize_label (stream
, name
)
11033 default_globalize_label (stream
, name
);
11034 if (! strcmp (name
, "main"))
11035 arm_main_function
= 1;
11037 #endif /* AOF_ASSEMBLER */
11039 #ifdef OBJECT_FORMAT_ELF
11040 /* Switch to an arbitrary section NAME with attributes as specified
11041 by FLAGS. ALIGN specifies any known alignment requirements for
11042 the section; 0 if the default should be used.
11044 Differs from the default elf version only in the prefix character
11045 used before the section type. */
11048 arm_elf_asm_named_section (name
, flags
)
11050 unsigned int flags
;
11052 char flagchars
[8], *f
= flagchars
;
11055 if (!(flags
& SECTION_DEBUG
))
11057 if (flags
& SECTION_WRITE
)
11059 if (flags
& SECTION_CODE
)
11061 if (flags
& SECTION_SMALL
)
11063 if (flags
& SECTION_MERGE
)
11065 if (flags
& SECTION_STRINGS
)
11069 if (flags
& SECTION_BSS
)
11074 if (flags
& SECTION_ENTSIZE
)
11075 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s,%d\n",
11076 name
, flagchars
, type
, flags
& SECTION_ENTSIZE
);
11078 fprintf (asm_out_file
, "\t.section\t%s,\"%s\",%%%s\n",
11079 name
, flagchars
, type
);
11084 /* Symbols in the text segment can be accessed without indirecting via the
11085 constant pool; it may take an extra binary operation, but this is still
11086 faster than indirecting via memory. Don't do this when not optimizing,
11087 since we won't be calculating al of the offsets necessary to do this
11091 arm_encode_section_info (decl
, first
)
11095 /* This doesn't work with AOF syntax, since the string table may be in
11096 a different AREA. */
11097 #ifndef AOF_ASSEMBLER
11098 if (optimize
> 0 && TREE_CONSTANT (decl
)
11099 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
11101 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
11102 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
11103 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
11107 /* If we are referencing a function that is weak then encode a long call
11108 flag in the function name, otherwise if the function is static or
11109 or known to be defined in this file then encode a short call flag. */
11110 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
11112 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
11113 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
11114 else if (! TREE_PUBLIC (decl
))
11115 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
11118 #endif /* !ARM_PE */