1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts
;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges
;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras
;
110 /* Number of instructions combined in this function. */
112 static int combine_successes
;
114 /* Totals over entire compilation. */
116 static int total_attempts
, total_merges
, total_extras
, total_successes
;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid
;
127 static int max_uid_cuid
;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno
;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx
*reg_last_death
;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx
*reg_last_set
;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set
;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid
;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn
;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid
;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs
;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn
;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block
;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks
;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx
*reg_last_set_value
;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label
;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick
;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid
;
267 /* Incremented for each label. */
269 static int label_tick
;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode
;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies
;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid
;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode
*reg_last_set_mode
;
306 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
307 static char *reg_last_set_sign_bit_copies
;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r
; int i
;} old_contents
;
318 union {rtx
*r
; int *i
;} where
;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf
;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences
;
341 static void do_SUBST (rtx
*, rtx
);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx
, rtx
, void *);
346 static int cant_combine_insn_p (rtx
);
347 static int can_combine_p (rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*);
348 static int combinable_i3pat (rtx
, rtx
*, rtx
, rtx
, int, rtx
*);
349 static int contains_muldiv (rtx
);
350 static rtx
try_combine (rtx
, rtx
, rtx
, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx
*find_split_point (rtx
*, rtx
);
354 static rtx
subst (rtx
, rtx
, rtx
, int, int);
355 static rtx
combine_simplify_rtx (rtx
, enum machine_mode
, int, int);
356 static rtx
simplify_if_then_else (rtx
);
357 static rtx
simplify_set (rtx
);
358 static rtx
simplify_logical (rtx
, int);
359 static rtx
expand_compound_operation (rtx
);
360 static rtx
expand_field_assignment (rtx
);
361 static rtx
make_extraction (enum machine_mode
, rtx
, HOST_WIDE_INT
,
362 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
363 static rtx
extract_left_shift (rtx
, int);
364 static rtx
make_compound_operation (rtx
, enum rtx_code
);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
366 unsigned HOST_WIDE_INT
*);
367 static rtx
force_to_mode (rtx
, enum machine_mode
,
368 unsigned HOST_WIDE_INT
, rtx
, int);
369 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
370 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
371 static int rtx_equal_for_field_assignment_p (rtx
, rtx
);
372 static rtx
make_field_assignment (rtx
);
373 static rtx
apply_distributive_law (rtx
);
374 static rtx
simplify_and_const_int (rtx
, enum machine_mode
, rtx
,
375 unsigned HOST_WIDE_INT
);
376 static unsigned HOST_WIDE_INT
cached_nonzero_bits (rtx
, enum machine_mode
,
377 rtx
, enum machine_mode
,
378 unsigned HOST_WIDE_INT
);
379 static unsigned HOST_WIDE_INT
nonzero_bits1 (rtx
, enum machine_mode
, rtx
,
381 unsigned HOST_WIDE_INT
);
382 static unsigned int cached_num_sign_bit_copies (rtx
, enum machine_mode
, rtx
,
385 static unsigned int num_sign_bit_copies1 (rtx
, enum machine_mode
, rtx
,
386 enum machine_mode
, unsigned int);
387 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
388 HOST_WIDE_INT
, enum machine_mode
, int *);
389 static rtx
simplify_shift_const (rtx
, enum rtx_code
, enum machine_mode
, rtx
,
391 static int recog_for_combine (rtx
*, rtx
, rtx
*);
392 static rtx
gen_lowpart_for_combine (enum machine_mode
, rtx
);
393 static rtx
gen_binary (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
394 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
395 static void update_table_tick (rtx
);
396 static void record_value_for_reg (rtx
, rtx
, rtx
);
397 static void check_promoted_subreg (rtx
, rtx
);
398 static void record_dead_and_set_regs_1 (rtx
, rtx
, void *);
399 static void record_dead_and_set_regs (rtx
);
400 static int get_last_value_validate (rtx
*, rtx
, int, int);
401 static rtx
get_last_value (rtx
);
402 static int use_crosses_set_p (rtx
, int);
403 static void reg_dead_at_p_1 (rtx
, rtx
, void *);
404 static int reg_dead_at_p (rtx
, rtx
);
405 static void move_deaths (rtx
, rtx
, int, rtx
, rtx
*);
406 static int reg_bitfield_target_p (rtx
, rtx
);
407 static void distribute_notes (rtx
, rtx
, rtx
, rtx
);
408 static void distribute_links (rtx
);
409 static void mark_used_regs_combine (rtx
);
410 static int insn_cuid (rtx
);
411 static void record_promoted_value (rtx
, rtx
);
412 static rtx
reversed_comparison (rtx
, enum machine_mode
, rtx
, rtx
);
413 static enum rtx_code
combine_reversed_comparison_code (rtx
);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx
*into
, rtx newval
)
427 if (oldval
== newval
)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
436 && GET_CODE (newval
) == CONST_INT
)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval
) != trunc_int_for_mode (INTVAL (newval
),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval
) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval
)) == CONST_INT
)
452 || (GET_CODE (oldval
) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval
, 0)) == CONST_INT
))
458 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
460 buf
= xmalloc (sizeof (struct undo
));
464 buf
->old_contents
.r
= oldval
;
467 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into
, int newval
)
482 if (oldval
== newval
)
486 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
488 buf
= xmalloc (sizeof (struct undo
));
492 buf
->old_contents
.i
= oldval
;
495 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f
, unsigned int nregs
)
513 rtx links
, nextlinks
;
515 int new_direct_jump_p
= 0;
517 combine_attempts
= 0;
520 combine_successes
= 0;
522 combine_max_regno
= nregs
;
524 reg_nonzero_bits
= xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
));
525 reg_sign_bit_copies
= xcalloc (nregs
, sizeof (unsigned char));
527 reg_last_death
= xmalloc (nregs
* sizeof (rtx
));
528 reg_last_set
= xmalloc (nregs
* sizeof (rtx
));
529 reg_last_set_value
= xmalloc (nregs
* sizeof (rtx
));
530 reg_last_set_table_tick
= xmalloc (nregs
* sizeof (int));
531 reg_last_set_label
= xmalloc (nregs
* sizeof (int));
532 reg_last_set_invalid
= xmalloc (nregs
* sizeof (char));
533 reg_last_set_mode
= xmalloc (nregs
* sizeof (enum machine_mode
));
534 reg_last_set_nonzero_bits
= xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
535 reg_last_set_sign_bit_copies
= xmalloc (nregs
* sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
544 if (INSN_UID (insn
) > i
)
547 uid_cuid
= xmalloc ((i
+ 1) * sizeof (int));
550 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid
= 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks
= sbitmap_alloc (last_basic_block
);
573 sbitmap_zero (refresh_blocks
);
575 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
577 uid_cuid
[INSN_UID (insn
)] = ++i
;
583 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
585 record_dead_and_set_regs (insn
);
588 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
589 if (REG_NOTE_KIND (links
) == REG_INC
)
590 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
595 if (GET_CODE (insn
) == CODE_LABEL
)
599 nonzero_sign_valid
= 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block
)
611 for (insn
= BB_HEAD (this_basic_block
);
612 insn
!= NEXT_INSN (BB_END (this_basic_block
));
613 insn
= next
? next
: NEXT_INSN (insn
))
617 if (GET_CODE (insn
) == CODE_LABEL
)
620 else if (INSN_P (insn
))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn
, PATTERN (insn
));
626 /* Try this insn with each insn it links back to. */
628 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
629 if ((next
= try_combine (insn
, XEXP (links
, 0),
630 NULL_RTX
, &new_direct_jump_p
)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
637 rtx link
= XEXP (links
, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link
) == NOTE
)
644 for (nextlinks
= LOG_LINKS (link
);
646 nextlinks
= XEXP (nextlinks
, 1))
647 if ((next
= try_combine (insn
, link
,
649 &new_direct_jump_p
)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn
) == JUMP_INSN
662 && (prev
= prev_nonnote_insn (insn
)) != 0
663 && GET_CODE (prev
) == INSN
664 && sets_cc0_p (PATTERN (prev
)))
666 if ((next
= try_combine (insn
, prev
,
667 NULL_RTX
, &new_direct_jump_p
)) != 0)
670 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
671 nextlinks
= XEXP (nextlinks
, 1))
672 if ((next
= try_combine (insn
, prev
,
674 &new_direct_jump_p
)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn
) == INSN
680 && (prev
= prev_nonnote_insn (insn
)) != 0
681 && GET_CODE (prev
) == INSN
682 && sets_cc0_p (PATTERN (prev
))
683 && GET_CODE (PATTERN (insn
)) == SET
684 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
686 if ((next
= try_combine (insn
, prev
,
687 NULL_RTX
, &new_direct_jump_p
)) != 0)
690 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
691 nextlinks
= XEXP (nextlinks
, 1))
692 if ((next
= try_combine (insn
, prev
,
694 &new_direct_jump_p
)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 if (GET_CODE (XEXP (links
, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
704 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
705 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
706 && GET_CODE (prev
) == INSN
707 && sets_cc0_p (PATTERN (prev
))
708 && (next
= try_combine (insn
, XEXP (links
, 0),
709 prev
, &new_direct_jump_p
)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
716 for (nextlinks
= XEXP (links
, 1); nextlinks
;
717 nextlinks
= XEXP (nextlinks
, 1))
718 if ((next
= try_combine (insn
, XEXP (links
, 0),
720 &new_direct_jump_p
)) != 0)
723 if (GET_CODE (insn
) != NOTE
)
724 record_dead_and_set_regs (insn
);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks
, 0, i
,
734 BASIC_BLOCK (i
)->flags
|= BB_DIRTY
);
735 new_direct_jump_p
|= purge_all_dead_edges (0);
736 delete_noop_moves (f
);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES
,
739 PROP_DEATH_NOTES
| PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE
);
743 sbitmap_free (refresh_blocks
);
744 free (reg_nonzero_bits
);
745 free (reg_sign_bit_copies
);
746 free (reg_last_death
);
748 free (reg_last_set_value
);
749 free (reg_last_set_table_tick
);
750 free (reg_last_set_label
);
751 free (reg_last_set_invalid
);
752 free (reg_last_set_mode
);
753 free (reg_last_set_nonzero_bits
);
754 free (reg_last_set_sign_bit_copies
);
758 struct undo
*undo
, *next
;
759 for (undo
= undobuf
.frees
; undo
; undo
= next
)
767 total_attempts
+= combine_attempts
;
768 total_merges
+= combine_merges
;
769 total_extras
+= combine_extras
;
770 total_successes
+= combine_successes
;
772 nonzero_sign_valid
= 0;
774 /* Make recognizer allow volatile MEMs again. */
777 return new_direct_jump_p
;
780 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
783 init_reg_last_arrays (void)
785 unsigned int nregs
= combine_max_regno
;
787 memset (reg_last_death
, 0, nregs
* sizeof (rtx
));
788 memset (reg_last_set
, 0, nregs
* sizeof (rtx
));
789 memset (reg_last_set_value
, 0, nregs
* sizeof (rtx
));
790 memset (reg_last_set_table_tick
, 0, nregs
* sizeof (int));
791 memset (reg_last_set_label
, 0, nregs
* sizeof (int));
792 memset (reg_last_set_invalid
, 0, nregs
* sizeof (char));
793 memset (reg_last_set_mode
, 0, nregs
* sizeof (enum machine_mode
));
794 memset (reg_last_set_nonzero_bits
, 0, nregs
* sizeof (HOST_WIDE_INT
));
795 memset (reg_last_set_sign_bit_copies
, 0, nregs
* sizeof (char));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions (void)
805 enum machine_mode mode
;
807 rtx first
= get_insns ();
809 if (targetm
.calls
.promote_function_args (TREE_TYPE (cfun
->decl
)))
811 #ifndef OUTGOING_REGNO
812 #define OUTGOING_REGNO(N) N
814 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
815 /* Check whether this register can hold an incoming pointer
816 argument. FUNCTION_ARG_REGNO_P tests outgoing register
817 numbers, so translate if necessary due to register windows. */
818 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
819 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
822 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
825 gen_rtx_CLOBBER (mode
, const0_rtx
)));
830 /* Called via note_stores. If X is a pseudo that is narrower than
831 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
833 If we are setting only a portion of X and we can't figure out what
834 portion, assume all bits will be used since we don't know what will
837 Similarly, set how many bits of X are known to be copies of the sign bit
838 at all locations in the function. This is the smallest number implied
842 set_nonzero_bits_and_sign_copies (rtx x
, rtx set
,
843 void *data ATTRIBUTE_UNUSED
)
847 if (GET_CODE (x
) == REG
848 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
849 /* If this register is undefined at the start of the file, we can't
850 say what its contents were. */
851 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, REGNO (x
))
852 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
854 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
856 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
857 reg_sign_bit_copies
[REGNO (x
)] = 1;
861 /* If this is a complex assignment, see if we can convert it into a
862 simple assignment. */
863 set
= expand_field_assignment (set
);
865 /* If this is a simple assignment, or we have a paradoxical SUBREG,
866 set what we know about X. */
868 if (SET_DEST (set
) == x
869 || (GET_CODE (SET_DEST (set
)) == SUBREG
870 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
872 && SUBREG_REG (SET_DEST (set
)) == x
))
874 rtx src
= SET_SRC (set
);
876 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
877 /* If X is narrower than a word and SRC is a non-negative
878 constant that would appear negative in the mode of X,
879 sign-extend it for use in reg_nonzero_bits because some
880 machines (maybe most) will actually do the sign-extension
881 and this is the conservative approach.
883 ??? For 2.5, try to tighten up the MD files in this regard
884 instead of this kludge. */
886 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
887 && GET_CODE (src
) == CONST_INT
889 && 0 != (INTVAL (src
)
891 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
892 src
= GEN_INT (INTVAL (src
)
893 | ((HOST_WIDE_INT
) (-1)
894 << GET_MODE_BITSIZE (GET_MODE (x
))));
897 /* Don't call nonzero_bits if it cannot change anything. */
898 if (reg_nonzero_bits
[REGNO (x
)] != ~(unsigned HOST_WIDE_INT
) 0)
899 reg_nonzero_bits
[REGNO (x
)]
900 |= nonzero_bits (src
, nonzero_bits_mode
);
901 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
902 if (reg_sign_bit_copies
[REGNO (x
)] == 0
903 || reg_sign_bit_copies
[REGNO (x
)] > num
)
904 reg_sign_bit_copies
[REGNO (x
)] = num
;
908 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
909 reg_sign_bit_copies
[REGNO (x
)] = 1;
914 /* See if INSN can be combined into I3. PRED and SUCC are optionally
915 insns that were previously combined into I3 or that will be combined
916 into the merger of INSN and I3.
918 Return 0 if the combination is not allowed for any reason.
920 If the combination is allowed, *PDEST will be set to the single
921 destination of INSN and *PSRC to the single source, and this function
925 can_combine_p (rtx insn
, rtx i3
, rtx pred ATTRIBUTE_UNUSED
, rtx succ
,
926 rtx
*pdest
, rtx
*psrc
)
929 rtx set
= 0, src
, dest
;
934 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
935 && next_active_insn (succ
) == i3
)
936 : next_active_insn (insn
) == i3
);
938 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
939 or a PARALLEL consisting of such a SET and CLOBBERs.
941 If INSN has CLOBBER parallel parts, ignore them for our processing.
942 By definition, these happen during the execution of the insn. When it
943 is merged with another insn, all bets are off. If they are, in fact,
944 needed and aren't also supplied in I3, they may be added by
945 recog_for_combine. Otherwise, it won't match.
947 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
950 Get the source and destination of INSN. If more than one, can't
953 if (GET_CODE (PATTERN (insn
)) == SET
)
954 set
= PATTERN (insn
);
955 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
956 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
958 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
960 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
962 switch (GET_CODE (elt
))
964 /* This is important to combine floating point insns
967 /* Combining an isolated USE doesn't make sense.
968 We depend here on combinable_i3pat to reject them. */
969 /* The code below this loop only verifies that the inputs of
970 the SET in INSN do not change. We call reg_set_between_p
971 to verify that the REG in the USE does not change between
973 If the USE in INSN was for a pseudo register, the matching
974 insn pattern will likely match any register; combining this
975 with any other USE would only be safe if we knew that the
976 used registers have identical values, or if there was
977 something to tell them apart, e.g. different modes. For
978 now, we forgo such complicated tests and simply disallow
979 combining of USES of pseudo registers with any other USE. */
980 if (GET_CODE (XEXP (elt
, 0)) == REG
981 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
983 rtx i3pat
= PATTERN (i3
);
984 int i
= XVECLEN (i3pat
, 0) - 1;
985 unsigned int regno
= REGNO (XEXP (elt
, 0));
989 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
991 if (GET_CODE (i3elt
) == USE
992 && GET_CODE (XEXP (i3elt
, 0)) == REG
993 && (REGNO (XEXP (i3elt
, 0)) == regno
994 ? reg_set_between_p (XEXP (elt
, 0),
995 PREV_INSN (insn
), i3
)
996 : regno
>= FIRST_PSEUDO_REGISTER
))
1003 /* We can ignore CLOBBERs. */
1008 /* Ignore SETs whose result isn't used but not those that
1009 have side-effects. */
1010 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1011 && ! side_effects_p (elt
))
1014 /* If we have already found a SET, this is a second one and
1015 so we cannot combine with this insn. */
1023 /* Anything else means we can't combine. */
1029 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1030 so don't do anything with it. */
1031 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1040 set
= expand_field_assignment (set
);
1041 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1043 /* Don't eliminate a store in the stack pointer. */
1044 if (dest
== stack_pointer_rtx
1045 /* Don't combine with an insn that sets a register to itself if it has
1046 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1047 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1048 /* Can't merge an ASM_OPERANDS. */
1049 || GET_CODE (src
) == ASM_OPERANDS
1050 /* Can't merge a function call. */
1051 || GET_CODE (src
) == CALL
1052 /* Don't eliminate a function call argument. */
1053 || (GET_CODE (i3
) == CALL_INSN
1054 && (find_reg_fusage (i3
, USE
, dest
)
1055 || (GET_CODE (dest
) == REG
1056 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1057 && global_regs
[REGNO (dest
)])))
1058 /* Don't substitute into an incremented register. */
1059 || FIND_REG_INC_NOTE (i3
, dest
)
1060 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1062 /* Don't combine the end of a libcall into anything. */
1063 /* ??? This gives worse code, and appears to be unnecessary, since no
1064 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1065 use REG_RETVAL notes for noconflict blocks, but other code here
1066 makes sure that those insns don't disappear. */
1067 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1069 /* Make sure that DEST is not used after SUCC but before I3. */
1070 || (succ
&& ! all_adjacent
1071 && reg_used_between_p (dest
, succ
, i3
))
1072 /* Make sure that the value that is to be substituted for the register
1073 does not use any registers whose values alter in between. However,
1074 If the insns are adjacent, a use can't cross a set even though we
1075 think it might (this can happen for a sequence of insns each setting
1076 the same destination; reg_last_set of that register might point to
1077 a NOTE). If INSN has a REG_EQUIV note, the register is always
1078 equivalent to the memory so the substitution is valid even if there
1079 are intervening stores. Also, don't move a volatile asm or
1080 UNSPEC_VOLATILE across any other insns. */
1082 && (((GET_CODE (src
) != MEM
1083 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1084 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1085 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1086 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1087 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1088 better register allocation by not doing the combine. */
1089 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1090 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1091 /* Don't combine across a CALL_INSN, because that would possibly
1092 change whether the life span of some REGs crosses calls or not,
1093 and it is a pain to update that information.
1094 Exception: if source is a constant, moving it later can't hurt.
1095 Accept that special case, because it helps -fforce-addr a lot. */
1096 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1099 /* DEST must either be a REG or CC0. */
1100 if (GET_CODE (dest
) == REG
)
1102 /* If register alignment is being enforced for multi-word items in all
1103 cases except for parameters, it is possible to have a register copy
1104 insn referencing a hard register that is not allowed to contain the
1105 mode being copied and which would not be valid as an operand of most
1106 insns. Eliminate this problem by not combining with such an insn.
1108 Also, on some machines we don't want to extend the life of a hard
1111 if (GET_CODE (src
) == REG
1112 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1113 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1114 /* Don't extend the life of a hard register unless it is
1115 user variable (if we have few registers) or it can't
1116 fit into the desired register (meaning something special
1118 Also avoid substituting a return register into I3, because
1119 reload can't handle a conflict with constraints of other
1121 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1122 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
1125 else if (GET_CODE (dest
) != CC0
)
1128 /* Don't substitute for a register intended as a clobberable operand.
1129 Similarly, don't substitute an expression containing a register that
1130 will be clobbered in I3. */
1131 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1132 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1133 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1134 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1136 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1139 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1140 or not), reject, unless nothing volatile comes between it and I3 */
1142 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1144 /* Make sure succ doesn't contain a volatile reference. */
1145 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1148 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1149 if (INSN_P (p
) && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1153 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1154 to be an explicit register variable, and was chosen for a reason. */
1156 if (GET_CODE (src
) == ASM_OPERANDS
1157 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1160 /* If there are any volatile insns between INSN and I3, reject, because
1161 they might affect machine state. */
1163 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1164 if (INSN_P (p
) && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1167 /* If INSN or I2 contains an autoincrement or autodecrement,
1168 make sure that register is not used between there and I3,
1169 and not already used in I3 either.
1170 Also insist that I3 not be a jump; if it were one
1171 and the incremented register were spilled, we would lose. */
1174 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1175 if (REG_NOTE_KIND (link
) == REG_INC
1176 && (GET_CODE (i3
) == JUMP_INSN
1177 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1178 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1183 /* Don't combine an insn that follows a CC0-setting insn.
1184 An insn that uses CC0 must not be separated from the one that sets it.
1185 We do, however, allow I2 to follow a CC0-setting insn if that insn
1186 is passed as I1; in that case it will be deleted also.
1187 We also allow combining in this case if all the insns are adjacent
1188 because that would leave the two CC0 insns adjacent as well.
1189 It would be more logical to test whether CC0 occurs inside I1 or I2,
1190 but that would be much slower, and this ought to be equivalent. */
1192 p
= prev_nonnote_insn (insn
);
1193 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1198 /* If we get here, we have passed all the tests and the combination is
1207 /* LOC is the location within I3 that contains its pattern or the component
1208 of a PARALLEL of the pattern. We validate that it is valid for combining.
1210 One problem is if I3 modifies its output, as opposed to replacing it
1211 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1212 so would produce an insn that is not equivalent to the original insns.
1216 (set (reg:DI 101) (reg:DI 100))
1217 (set (subreg:SI (reg:DI 101) 0) <foo>)
1219 This is NOT equivalent to:
1221 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1222 (set (reg:DI 101) (reg:DI 100))])
1224 Not only does this modify 100 (in which case it might still be valid
1225 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1227 We can also run into a problem if I2 sets a register that I1
1228 uses and I1 gets directly substituted into I3 (not via I2). In that
1229 case, we would be getting the wrong value of I2DEST into I3, so we
1230 must reject the combination. This case occurs when I2 and I1 both
1231 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1232 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1233 of a SET must prevent combination from occurring.
1235 Before doing the above check, we first try to expand a field assignment
1236 into a set of logical operations.
1238 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1239 we place a register that is both set and used within I3. If more than one
1240 such register is detected, we fail.
1242 Return 1 if the combination is valid, zero otherwise. */
1245 combinable_i3pat (rtx i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
,
1246 int i1_not_in_src
, rtx
*pi3dest_killed
)
1250 if (GET_CODE (x
) == SET
)
1253 rtx dest
= SET_DEST (set
);
1254 rtx src
= SET_SRC (set
);
1255 rtx inner_dest
= dest
;
1257 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1258 || GET_CODE (inner_dest
) == SUBREG
1259 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1260 inner_dest
= XEXP (inner_dest
, 0);
1262 /* Check for the case where I3 modifies its output, as discussed
1263 above. We don't want to prevent pseudos from being combined
1264 into the address of a MEM, so only prevent the combination if
1265 i1 or i2 set the same MEM. */
1266 if ((inner_dest
!= dest
&&
1267 (GET_CODE (inner_dest
) != MEM
1268 || rtx_equal_p (i2dest
, inner_dest
)
1269 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
)))
1270 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1271 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1273 /* This is the same test done in can_combine_p except we can't test
1274 all_adjacent; we don't have to, since this instruction will stay
1275 in place, thus we are not considering increasing the lifetime of
1278 Also, if this insn sets a function argument, combining it with
1279 something that might need a spill could clobber a previous
1280 function argument; the all_adjacent test in can_combine_p also
1281 checks this; here, we do a more specific test for this case. */
1283 || (GET_CODE (inner_dest
) == REG
1284 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1285 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1286 GET_MODE (inner_dest
))))
1287 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1290 /* If DEST is used in I3, it is being killed in this insn,
1291 so record that for later.
1292 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1293 STACK_POINTER_REGNUM, since these are always considered to be
1294 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1295 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1296 && reg_referenced_p (dest
, PATTERN (i3
))
1297 && REGNO (dest
) != FRAME_POINTER_REGNUM
1298 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1299 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1301 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1302 && (REGNO (dest
) != ARG_POINTER_REGNUM
1303 || ! fixed_regs
[REGNO (dest
)])
1305 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1307 if (*pi3dest_killed
)
1310 *pi3dest_killed
= dest
;
1314 else if (GET_CODE (x
) == PARALLEL
)
1318 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1319 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1320 i1_not_in_src
, pi3dest_killed
))
1327 /* Return 1 if X is an arithmetic expression that contains a multiplication
1328 and division. We don't count multiplications by powers of two here. */
1331 contains_muldiv (rtx x
)
1333 switch (GET_CODE (x
))
1335 case MOD
: case DIV
: case UMOD
: case UDIV
:
1339 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1340 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1342 switch (GET_RTX_CLASS (GET_CODE (x
)))
1344 case 'c': case '<': case '2':
1345 return contains_muldiv (XEXP (x
, 0))
1346 || contains_muldiv (XEXP (x
, 1));
1349 return contains_muldiv (XEXP (x
, 0));
1357 /* Determine whether INSN can be used in a combination. Return nonzero if
1358 not. This is used in try_combine to detect early some cases where we
1359 can't perform combinations. */
1362 cant_combine_insn_p (rtx insn
)
1367 /* If this isn't really an insn, we can't do anything.
1368 This can occur when flow deletes an insn that it has merged into an
1369 auto-increment address. */
1370 if (! INSN_P (insn
))
1373 /* Never combine loads and stores involving hard regs that are likely
1374 to be spilled. The register allocator can usually handle such
1375 reg-reg moves by tying. If we allow the combiner to make
1376 substitutions of likely-spilled regs, we may abort in reload.
1377 As an exception, we allow combinations involving fixed regs; these are
1378 not available to the register allocator so there's no risk involved. */
1380 set
= single_set (insn
);
1383 src
= SET_SRC (set
);
1384 dest
= SET_DEST (set
);
1385 if (GET_CODE (src
) == SUBREG
)
1386 src
= SUBREG_REG (src
);
1387 if (GET_CODE (dest
) == SUBREG
)
1388 dest
= SUBREG_REG (dest
);
1389 if (REG_P (src
) && REG_P (dest
)
1390 && ((REGNO (src
) < FIRST_PSEUDO_REGISTER
1391 && ! fixed_regs
[REGNO (src
)]
1392 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src
))))
1393 || (REGNO (dest
) < FIRST_PSEUDO_REGISTER
1394 && ! fixed_regs
[REGNO (dest
)]
1395 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest
))))))
1401 /* Adjust INSN after we made a change to its destination.
1403 Changing the destination can invalidate notes that say something about
1404 the results of the insn and a LOG_LINK pointing to the insn. */
1407 adjust_for_new_dest (rtx insn
)
1411 /* For notes, be conservative and simply remove them. */
1412 loc
= ®_NOTES (insn
);
1415 enum reg_note kind
= REG_NOTE_KIND (*loc
);
1416 if (kind
== REG_EQUAL
|| kind
== REG_EQUIV
)
1417 *loc
= XEXP (*loc
, 1);
1419 loc
= &XEXP (*loc
, 1);
1422 /* The new insn will have a destination that was previously the destination
1423 of an insn just above it. Call distribute_links to make a LOG_LINK from
1424 the next use of that destination. */
1425 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
));
1428 /* Try to combine the insns I1 and I2 into I3.
1429 Here I1 and I2 appear earlier than I3.
1430 I1 can be zero; then we combine just I2 into I3.
1432 If we are combining three insns and the resulting insn is not recognized,
1433 try splitting it into two insns. If that happens, I2 and I3 are retained
1434 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1437 Return 0 if the combination does not work. Then nothing is changed.
1438 If we did the combination, return the insn at which combine should
1441 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1442 new direct jump instruction. */
1445 try_combine (rtx i3
, rtx i2
, rtx i1
, int *new_direct_jump_p
)
1447 /* New patterns for I3 and I2, respectively. */
1448 rtx newpat
, newi2pat
= 0;
1449 int substed_i2
= 0, substed_i1
= 0;
1450 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1451 int added_sets_1
, added_sets_2
;
1452 /* Total number of SETs to put into I3. */
1454 /* Nonzero is I2's body now appears in I3. */
1456 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1457 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1458 /* Contains I3 if the destination of I3 is used in its source, which means
1459 that the old life of I3 is being killed. If that usage is placed into
1460 I2 and not in I3, a REG_DEAD note must be made. */
1461 rtx i3dest_killed
= 0;
1462 /* SET_DEST and SET_SRC of I2 and I1. */
1463 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1464 /* PATTERN (I2), or a copy of it in certain cases. */
1466 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1467 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1468 int i1_feeds_i3
= 0;
1469 /* Notes that must be added to REG_NOTES in I3 and I2. */
1470 rtx new_i3_notes
, new_i2_notes
;
1471 /* Notes that we substituted I3 into I2 instead of the normal case. */
1472 int i3_subst_into_i2
= 0;
1473 /* Notes that I1, I2 or I3 is a MULT operation. */
1481 /* Exit early if one of the insns involved can't be used for
1483 if (cant_combine_insn_p (i3
)
1484 || cant_combine_insn_p (i2
)
1485 || (i1
&& cant_combine_insn_p (i1
))
1486 /* We also can't do anything if I3 has a
1487 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1490 /* ??? This gives worse code, and appears to be unnecessary, since no
1491 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1492 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1498 undobuf
.other_insn
= 0;
1500 /* Reset the hard register usage information. */
1501 CLEAR_HARD_REG_SET (newpat_used_regs
);
1503 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1504 code below, set I1 to be the earlier of the two insns. */
1505 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1506 temp
= i1
, i1
= i2
, i2
= temp
;
1508 added_links_insn
= 0;
1510 /* First check for one important special-case that the code below will
1511 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1512 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1513 we may be able to replace that destination with the destination of I3.
1514 This occurs in the common code where we compute both a quotient and
1515 remainder into a structure, in which case we want to do the computation
1516 directly into the structure to avoid register-register copies.
1518 Note that this case handles both multiple sets in I2 and also
1519 cases where I2 has a number of CLOBBER or PARALLELs.
1521 We make very conservative checks below and only try to handle the
1522 most common cases of this. For example, we only handle the case
1523 where I2 and I3 are adjacent to avoid making difficult register
1526 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1527 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1528 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1529 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1530 && GET_CODE (PATTERN (i2
)) == PARALLEL
1531 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1532 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1533 below would need to check what is inside (and reg_overlap_mentioned_p
1534 doesn't support those codes anyway). Don't allow those destinations;
1535 the resulting insn isn't likely to be recognized anyway. */
1536 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1537 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1538 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1539 SET_DEST (PATTERN (i3
)))
1540 && next_real_insn (i2
) == i3
)
1542 rtx p2
= PATTERN (i2
);
1544 /* Make sure that the destination of I3,
1545 which we are going to substitute into one output of I2,
1546 is not used within another output of I2. We must avoid making this:
1547 (parallel [(set (mem (reg 69)) ...)
1548 (set (reg 69) ...)])
1549 which is not well-defined as to order of actions.
1550 (Besides, reload can't handle output reloads for this.)
1552 The problem can also happen if the dest of I3 is a memory ref,
1553 if another dest in I2 is an indirect memory ref. */
1554 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1555 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1556 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1557 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1558 SET_DEST (XVECEXP (p2
, 0, i
))))
1561 if (i
== XVECLEN (p2
, 0))
1562 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1563 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1564 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1565 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1570 subst_low_cuid
= INSN_CUID (i2
);
1572 added_sets_2
= added_sets_1
= 0;
1573 i2dest
= SET_SRC (PATTERN (i3
));
1575 /* Replace the dest in I2 with our dest and make the resulting
1576 insn the new pattern for I3. Then skip to where we
1577 validate the pattern. Everything was set up above. */
1578 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1579 SET_DEST (PATTERN (i3
)));
1582 i3_subst_into_i2
= 1;
1583 goto validate_replacement
;
1587 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1588 one of those words to another constant, merge them by making a new
1591 && (temp
= single_set (i2
)) != 0
1592 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1593 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1594 && GET_CODE (SET_DEST (temp
)) == REG
1595 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1596 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1597 && GET_CODE (PATTERN (i3
)) == SET
1598 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1599 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1602 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1604 HOST_WIDE_INT lo
, hi
;
1606 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1607 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1610 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1611 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1614 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1616 /* We don't handle the case of the target word being wider
1617 than a host wide int. */
1618 if (HOST_BITS_PER_WIDE_INT
< BITS_PER_WORD
)
1621 lo
&= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1622 lo
|= (INTVAL (SET_SRC (PATTERN (i3
)))
1623 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1625 else if (HOST_BITS_PER_WIDE_INT
== BITS_PER_WORD
)
1626 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1627 else if (HOST_BITS_PER_WIDE_INT
>= 2 * BITS_PER_WORD
)
1629 int sign
= -(int) ((unsigned HOST_WIDE_INT
) lo
1630 >> (HOST_BITS_PER_WIDE_INT
- 1));
1632 lo
&= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1633 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1634 lo
|= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1635 (INTVAL (SET_SRC (PATTERN (i3
)))));
1637 hi
= lo
< 0 ? -1 : 0;
1640 /* We don't handle the case of the higher word not fitting
1641 entirely in either hi or lo. */
1646 subst_low_cuid
= INSN_CUID (i2
);
1647 added_sets_2
= added_sets_1
= 0;
1648 i2dest
= SET_DEST (temp
);
1650 SUBST (SET_SRC (temp
),
1651 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1653 newpat
= PATTERN (i2
);
1654 goto validate_replacement
;
1658 /* If we have no I1 and I2 looks like:
1659 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1661 make up a dummy I1 that is
1664 (set (reg:CC X) (compare:CC Y (const_int 0)))
1666 (We can ignore any trailing CLOBBERs.)
1668 This undoes a previous combination and allows us to match a branch-and-
1671 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1672 && XVECLEN (PATTERN (i2
), 0) >= 2
1673 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1674 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1676 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1677 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1678 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1679 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1680 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1681 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1683 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1684 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1689 /* We make I1 with the same INSN_UID as I2. This gives it
1690 the same INSN_CUID for value tracking. Our fake I1 will
1691 never appear in the insn stream so giving it the same INSN_UID
1692 as I2 will not cause a problem. */
1694 i1
= gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1695 BLOCK_FOR_INSN (i2
), INSN_LOCATOR (i2
),
1696 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1699 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1700 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1701 SET_DEST (PATTERN (i1
)));
1706 /* Verify that I2 and I1 are valid for combining. */
1707 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1708 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1714 /* Record whether I2DEST is used in I2SRC and similarly for the other
1715 cases. Knowing this will help in register status updating below. */
1716 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1717 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1718 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1720 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1722 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1724 /* Ensure that I3's pattern can be the destination of combines. */
1725 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1726 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1733 /* See if any of the insns is a MULT operation. Unless one is, we will
1734 reject a combination that is, since it must be slower. Be conservative
1736 if (GET_CODE (i2src
) == MULT
1737 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1738 || (GET_CODE (PATTERN (i3
)) == SET
1739 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1742 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1743 We used to do this EXCEPT in one case: I3 has a post-inc in an
1744 output operand. However, that exception can give rise to insns like
1746 which is a famous insn on the PDP-11 where the value of r3 used as the
1747 source was model-dependent. Avoid this sort of thing. */
1750 if (!(GET_CODE (PATTERN (i3
)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1752 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1753 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1754 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1755 /* It's not the exception. */
1758 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1759 if (REG_NOTE_KIND (link
) == REG_INC
1760 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1762 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1769 /* See if the SETs in I1 or I2 need to be kept around in the merged
1770 instruction: whenever the value set there is still needed past I3.
1771 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1773 For the SET in I1, we have two cases: If I1 and I2 independently
1774 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1775 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1776 in I1 needs to be kept around unless I1DEST dies or is set in either
1777 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1778 I1DEST. If so, we know I1 feeds into I2. */
1780 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1783 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1784 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1786 /* If the set in I2 needs to be kept around, we must make a copy of
1787 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1788 PATTERN (I2), we are only substituting for the original I1DEST, not into
1789 an already-substituted copy. This also prevents making self-referential
1790 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1793 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1794 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1798 i2pat
= copy_rtx (i2pat
);
1802 /* Substitute in the latest insn for the regs set by the earlier ones. */
1804 maxreg
= max_reg_num ();
1808 /* It is possible that the source of I2 or I1 may be performing an
1809 unneeded operation, such as a ZERO_EXTEND of something that is known
1810 to have the high part zero. Handle that case by letting subst look at
1811 the innermost one of them.
1813 Another way to do this would be to have a function that tries to
1814 simplify a single insn instead of merging two or more insns. We don't
1815 do this because of the potential of infinite loops and because
1816 of the potential extra memory required. However, doing it the way
1817 we are is a bit of a kludge and doesn't catch all cases.
1819 But only do this if -fexpensive-optimizations since it slows things down
1820 and doesn't usually win. */
1822 if (flag_expensive_optimizations
)
1824 /* Pass pc_rtx so no substitutions are done, just simplifications.
1825 The cases that we are interested in here do not involve the few
1826 cases were is_replaced is checked. */
1829 subst_low_cuid
= INSN_CUID (i1
);
1830 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1834 subst_low_cuid
= INSN_CUID (i2
);
1835 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1840 /* Many machines that don't use CC0 have insns that can both perform an
1841 arithmetic operation and set the condition code. These operations will
1842 be represented as a PARALLEL with the first element of the vector
1843 being a COMPARE of an arithmetic operation with the constant zero.
1844 The second element of the vector will set some pseudo to the result
1845 of the same arithmetic operation. If we simplify the COMPARE, we won't
1846 match such a pattern and so will generate an extra insn. Here we test
1847 for this case, where both the comparison and the operation result are
1848 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1849 I2SRC. Later we will make the PARALLEL that contains I2. */
1851 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1852 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1853 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1854 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1856 #ifdef SELECT_CC_MODE
1858 enum machine_mode compare_mode
;
1861 newpat
= PATTERN (i3
);
1862 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1866 #ifdef SELECT_CC_MODE
1867 /* See if a COMPARE with the operand we substituted in should be done
1868 with the mode that is currently being used. If not, do the same
1869 processing we do in `subst' for a SET; namely, if the destination
1870 is used only once, try to replace it with a register of the proper
1871 mode and also replace the COMPARE. */
1872 if (undobuf
.other_insn
== 0
1873 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1874 &undobuf
.other_insn
))
1875 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1877 != GET_MODE (SET_DEST (newpat
))))
1879 unsigned int regno
= REGNO (SET_DEST (newpat
));
1880 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1882 if (regno
< FIRST_PSEUDO_REGISTER
1883 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1884 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1886 if (regno
>= FIRST_PSEUDO_REGISTER
)
1887 SUBST (regno_reg_rtx
[regno
], new_dest
);
1889 SUBST (SET_DEST (newpat
), new_dest
);
1890 SUBST (XEXP (*cc_use
, 0), new_dest
);
1891 SUBST (SET_SRC (newpat
),
1892 gen_rtx_COMPARE (compare_mode
, i2src
, const0_rtx
));
1895 undobuf
.other_insn
= 0;
1902 n_occurrences
= 0; /* `subst' counts here */
1904 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1905 need to make a unique copy of I2SRC each time we substitute it
1906 to avoid self-referential rtl. */
1908 subst_low_cuid
= INSN_CUID (i2
);
1909 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1910 ! i1_feeds_i3
&& i1dest_in_i1src
);
1913 /* Record whether i2's body now appears within i3's body. */
1914 i2_is_used
= n_occurrences
;
1917 /* If we already got a failure, don't try to do more. Otherwise,
1918 try to substitute in I1 if we have it. */
1920 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1922 /* Before we can do this substitution, we must redo the test done
1923 above (see detailed comments there) that ensures that I1DEST
1924 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1926 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1934 subst_low_cuid
= INSN_CUID (i1
);
1935 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1939 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1940 to count all the ways that I2SRC and I1SRC can be used. */
1941 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1942 && i2_is_used
+ added_sets_2
> 1)
1943 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1944 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1946 /* Fail if we tried to make a new register (we used to abort, but there's
1947 really no reason to). */
1948 || max_reg_num () != maxreg
1949 /* Fail if we couldn't do something and have a CLOBBER. */
1950 || GET_CODE (newpat
) == CLOBBER
1951 /* Fail if this new pattern is a MULT and we didn't have one before
1952 at the outer level. */
1953 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1960 /* If the actions of the earlier insns must be kept
1961 in addition to substituting them into the latest one,
1962 we must make a new PARALLEL for the latest insn
1963 to hold additional the SETs. */
1965 if (added_sets_1
|| added_sets_2
)
1969 if (GET_CODE (newpat
) == PARALLEL
)
1971 rtvec old
= XVEC (newpat
, 0);
1972 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1973 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1974 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
1975 sizeof (old
->elem
[0]) * old
->num_elem
);
1980 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1981 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1982 XVECEXP (newpat
, 0, 0) = old
;
1986 XVECEXP (newpat
, 0, --total_sets
)
1987 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1988 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1992 /* If there is no I1, use I2's body as is. We used to also not do
1993 the subst call below if I2 was substituted into I3,
1994 but that could lose a simplification. */
1996 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1998 /* See comment where i2pat is assigned. */
1999 XVECEXP (newpat
, 0, --total_sets
)
2000 = subst (i2pat
, i1dest
, i1src
, 0, 0);
2004 /* We come here when we are replacing a destination in I2 with the
2005 destination of I3. */
2006 validate_replacement
:
2008 /* Note which hard regs this insn has as inputs. */
2009 mark_used_regs_combine (newpat
);
2011 /* Is the result of combination a valid instruction? */
2012 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2014 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2015 the second SET's destination is a register that is unused. In that case,
2016 we just need the first SET. This can occur when simplifying a divmod
2017 insn. We *must* test for this case here because the code below that
2018 splits two independent SETs doesn't handle this case correctly when it
2019 updates the register status. Also check the case where the first
2020 SET's destination is unused. That would not cause incorrect code, but
2021 does cause an unneeded insn to remain. */
2023 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2024 && XVECLEN (newpat
, 0) == 2
2025 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2026 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2027 && asm_noperands (newpat
) < 0)
2029 rtx set0
= XVECEXP (newpat
, 0, 0);
2030 rtx set1
= XVECEXP (newpat
, 0, 1);
2032 if (((GET_CODE (SET_DEST (set1
)) == REG
2033 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
2034 || (GET_CODE (SET_DEST (set1
)) == SUBREG
2035 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
2036 && ! side_effects_p (SET_SRC (set1
)))
2039 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2042 else if (((GET_CODE (SET_DEST (set0
)) == REG
2043 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
2044 || (GET_CODE (SET_DEST (set0
)) == SUBREG
2045 && find_reg_note (i3
, REG_UNUSED
,
2046 SUBREG_REG (SET_DEST (set0
)))))
2047 && ! side_effects_p (SET_SRC (set0
)))
2050 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2052 if (insn_code_number
>= 0)
2054 /* If we will be able to accept this, we have made a
2055 change to the destination of I3. This requires us to
2056 do a few adjustments. */
2058 PATTERN (i3
) = newpat
;
2059 adjust_for_new_dest (i3
);
2064 /* If we were combining three insns and the result is a simple SET
2065 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2066 insns. There are two ways to do this. It can be split using a
2067 machine-specific method (like when you have an addition of a large
2068 constant) or by combine in the function find_split_point. */
2070 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2071 && asm_noperands (newpat
) < 0)
2073 rtx m_split
, *split
;
2074 rtx ni2dest
= i2dest
;
2076 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2077 use I2DEST as a scratch register will help. In the latter case,
2078 convert I2DEST to the mode of the source of NEWPAT if we can. */
2080 m_split
= split_insns (newpat
, i3
);
2082 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2083 inputs of NEWPAT. */
2085 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2086 possible to try that as a scratch reg. This would require adding
2087 more code to make it work though. */
2089 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2091 /* If I2DEST is a hard register or the only use of a pseudo,
2092 we can change its mode. */
2093 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2094 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2095 && GET_CODE (i2dest
) == REG
2096 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2097 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2098 && ! REG_USERVAR_P (i2dest
))))
2099 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2102 m_split
= split_insns (gen_rtx_PARALLEL
2104 gen_rtvec (2, newpat
,
2105 gen_rtx_CLOBBER (VOIDmode
,
2108 /* If the split with the mode-changed register didn't work, try
2109 the original register. */
2110 if (! m_split
&& ni2dest
!= i2dest
)
2113 m_split
= split_insns (gen_rtx_PARALLEL
2115 gen_rtvec (2, newpat
,
2116 gen_rtx_CLOBBER (VOIDmode
,
2122 if (m_split
&& NEXT_INSN (m_split
) == NULL_RTX
)
2124 m_split
= PATTERN (m_split
);
2125 insn_code_number
= recog_for_combine (&m_split
, i3
, &new_i3_notes
);
2126 if (insn_code_number
>= 0)
2129 else if (m_split
&& NEXT_INSN (NEXT_INSN (m_split
)) == NULL_RTX
2130 && (next_real_insn (i2
) == i3
2131 || ! use_crosses_set_p (PATTERN (m_split
), INSN_CUID (i2
))))
2134 rtx newi3pat
= PATTERN (NEXT_INSN (m_split
));
2135 newi2pat
= PATTERN (m_split
);
2137 i3set
= single_set (NEXT_INSN (m_split
));
2138 i2set
= single_set (m_split
);
2140 /* In case we changed the mode of I2DEST, replace it in the
2141 pseudo-register table here. We can't do it above in case this
2142 code doesn't get executed and we do a split the other way. */
2144 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2145 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2147 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2149 /* If I2 or I3 has multiple SETs, we won't know how to track
2150 register status, so don't use these insns. If I2's destination
2151 is used between I2 and I3, we also can't use these insns. */
2153 if (i2_code_number
>= 0 && i2set
&& i3set
2154 && (next_real_insn (i2
) == i3
2155 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2156 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2158 if (insn_code_number
>= 0)
2161 /* It is possible that both insns now set the destination of I3.
2162 If so, we must show an extra use of it. */
2164 if (insn_code_number
>= 0)
2166 rtx new_i3_dest
= SET_DEST (i3set
);
2167 rtx new_i2_dest
= SET_DEST (i2set
);
2169 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2170 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2171 || GET_CODE (new_i3_dest
) == SUBREG
)
2172 new_i3_dest
= XEXP (new_i3_dest
, 0);
2174 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2175 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2176 || GET_CODE (new_i2_dest
) == SUBREG
)
2177 new_i2_dest
= XEXP (new_i2_dest
, 0);
2179 if (GET_CODE (new_i3_dest
) == REG
2180 && GET_CODE (new_i2_dest
) == REG
2181 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2182 REG_N_SETS (REGNO (new_i2_dest
))++;
2186 /* If we can split it and use I2DEST, go ahead and see if that
2187 helps things be recognized. Verify that none of the registers
2188 are set between I2 and I3. */
2189 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2191 && GET_CODE (i2dest
) == REG
2193 /* We need I2DEST in the proper mode. If it is a hard register
2194 or the only use of a pseudo, we can change its mode. */
2195 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2196 || GET_MODE (*split
) == VOIDmode
2197 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2198 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2199 && ! REG_USERVAR_P (i2dest
)))
2200 && (next_real_insn (i2
) == i3
2201 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2202 /* We can't overwrite I2DEST if its value is still used by
2204 && ! reg_referenced_p (i2dest
, newpat
))
2206 rtx newdest
= i2dest
;
2207 enum rtx_code split_code
= GET_CODE (*split
);
2208 enum machine_mode split_mode
= GET_MODE (*split
);
2210 /* Get NEWDEST as a register in the proper mode. We have already
2211 validated that we can do this. */
2212 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2214 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2216 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2217 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2220 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2221 an ASHIFT. This can occur if it was inside a PLUS and hence
2222 appeared to be a memory address. This is a kludge. */
2223 if (split_code
== MULT
2224 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2225 && INTVAL (XEXP (*split
, 1)) > 0
2226 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2228 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
2229 XEXP (*split
, 0), GEN_INT (i
)));
2230 /* Update split_code because we may not have a multiply
2232 split_code
= GET_CODE (*split
);
2235 #ifdef INSN_SCHEDULING
2236 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2237 be written as a ZERO_EXTEND. */
2238 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2240 #ifdef LOAD_EXTEND_OP
2241 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2242 what it really is. */
2243 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
2245 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
2246 SUBREG_REG (*split
)));
2249 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
2250 SUBREG_REG (*split
)));
2254 newi2pat
= gen_rtx_SET (VOIDmode
, newdest
, *split
);
2255 SUBST (*split
, newdest
);
2256 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2258 /* If the split point was a MULT and we didn't have one before,
2259 don't use one now. */
2260 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2261 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2265 /* Check for a case where we loaded from memory in a narrow mode and
2266 then sign extended it, but we need both registers. In that case,
2267 we have a PARALLEL with both loads from the same memory location.
2268 We can split this into a load from memory followed by a register-register
2269 copy. This saves at least one insn, more if register allocation can
2272 We cannot do this if the destination of the first assignment is a
2273 condition code register or cc0. We eliminate this case by making sure
2274 the SET_DEST and SET_SRC have the same mode.
2276 We cannot do this if the destination of the second assignment is
2277 a register that we have already assumed is zero-extended. Similarly
2278 for a SUBREG of such a register. */
2280 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2281 && GET_CODE (newpat
) == PARALLEL
2282 && XVECLEN (newpat
, 0) == 2
2283 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2285 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
2286 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
2287 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2288 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2289 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2290 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2292 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2293 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2294 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2295 (GET_CODE (temp
) == REG
2296 && reg_nonzero_bits
[REGNO (temp
)] != 0
2297 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2298 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2299 && (reg_nonzero_bits
[REGNO (temp
)]
2300 != GET_MODE_MASK (word_mode
))))
2301 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2302 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2303 (GET_CODE (temp
) == REG
2304 && reg_nonzero_bits
[REGNO (temp
)] != 0
2305 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2306 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2307 && (reg_nonzero_bits
[REGNO (temp
)]
2308 != GET_MODE_MASK (word_mode
)))))
2309 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2310 SET_SRC (XVECEXP (newpat
, 0, 1)))
2311 && ! find_reg_note (i3
, REG_UNUSED
,
2312 SET_DEST (XVECEXP (newpat
, 0, 0))))
2316 newi2pat
= XVECEXP (newpat
, 0, 0);
2317 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2318 newpat
= XVECEXP (newpat
, 0, 1);
2319 SUBST (SET_SRC (newpat
),
2320 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2321 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2323 if (i2_code_number
>= 0)
2324 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2326 if (insn_code_number
>= 0)
2331 /* If we will be able to accept this, we have made a change to the
2332 destination of I3. This requires us to do a few adjustments. */
2333 PATTERN (i3
) = newpat
;
2334 adjust_for_new_dest (i3
);
2336 /* I3 now uses what used to be its destination and which is
2337 now I2's destination. That means we need a LOG_LINK from
2338 I3 to I2. But we used to have one, so we still will.
2340 However, some later insn might be using I2's dest and have
2341 a LOG_LINK pointing at I3. We must remove this link.
2342 The simplest way to remove the link is to point it at I1,
2343 which we know will be a NOTE. */
2345 for (insn
= NEXT_INSN (i3
);
2346 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2347 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
2348 insn
= NEXT_INSN (insn
))
2350 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2352 for (link
= LOG_LINKS (insn
); link
;
2353 link
= XEXP (link
, 1))
2354 if (XEXP (link
, 0) == i3
)
2355 XEXP (link
, 0) = i1
;
2363 /* Similarly, check for a case where we have a PARALLEL of two independent
2364 SETs but we started with three insns. In this case, we can do the sets
2365 as two separate insns. This case occurs when some SET allows two
2366 other insns to combine, but the destination of that SET is still live. */
2368 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2369 && GET_CODE (newpat
) == PARALLEL
2370 && XVECLEN (newpat
, 0) == 2
2371 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2372 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2373 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2374 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2375 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2376 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2377 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2379 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2380 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2381 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2382 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2383 XVECEXP (newpat
, 0, 0))
2384 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2385 XVECEXP (newpat
, 0, 1))
2386 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2387 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2389 /* Normally, it doesn't matter which of the two is done first,
2390 but it does if one references cc0. In that case, it has to
2393 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2395 newi2pat
= XVECEXP (newpat
, 0, 0);
2396 newpat
= XVECEXP (newpat
, 0, 1);
2401 newi2pat
= XVECEXP (newpat
, 0, 1);
2402 newpat
= XVECEXP (newpat
, 0, 0);
2405 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2407 if (i2_code_number
>= 0)
2408 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2411 /* If it still isn't recognized, fail and change things back the way they
2413 if ((insn_code_number
< 0
2414 /* Is the result a reasonable ASM_OPERANDS? */
2415 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2421 /* If we had to change another insn, make sure it is valid also. */
2422 if (undobuf
.other_insn
)
2424 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2425 rtx new_other_notes
;
2428 CLEAR_HARD_REG_SET (newpat_used_regs
);
2430 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2433 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2439 PATTERN (undobuf
.other_insn
) = other_pat
;
2441 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2442 are still valid. Then add any non-duplicate notes added by
2443 recog_for_combine. */
2444 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2446 next
= XEXP (note
, 1);
2448 if (REG_NOTE_KIND (note
) == REG_UNUSED
2449 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2451 if (GET_CODE (XEXP (note
, 0)) == REG
)
2452 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2454 remove_note (undobuf
.other_insn
, note
);
2458 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2459 if (GET_CODE (XEXP (note
, 0)) == REG
)
2460 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2462 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2463 undobuf
.other_insn
, NULL_RTX
);
2466 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2467 they are adjacent to each other or not. */
2469 rtx p
= prev_nonnote_insn (i3
);
2470 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
2471 && sets_cc0_p (newi2pat
))
2479 /* We now know that we can do this combination. Merge the insns and
2480 update the status of registers and LOG_LINKS. */
2483 rtx i3notes
, i2notes
, i1notes
= 0;
2484 rtx i3links
, i2links
, i1links
= 0;
2488 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2490 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2491 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2493 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2495 /* Ensure that we do not have something that should not be shared but
2496 occurs multiple times in the new insns. Check this by first
2497 resetting all the `used' flags and then copying anything is shared. */
2499 reset_used_flags (i3notes
);
2500 reset_used_flags (i2notes
);
2501 reset_used_flags (i1notes
);
2502 reset_used_flags (newpat
);
2503 reset_used_flags (newi2pat
);
2504 if (undobuf
.other_insn
)
2505 reset_used_flags (PATTERN (undobuf
.other_insn
));
2507 i3notes
= copy_rtx_if_shared (i3notes
);
2508 i2notes
= copy_rtx_if_shared (i2notes
);
2509 i1notes
= copy_rtx_if_shared (i1notes
);
2510 newpat
= copy_rtx_if_shared (newpat
);
2511 newi2pat
= copy_rtx_if_shared (newi2pat
);
2512 if (undobuf
.other_insn
)
2513 reset_used_flags (PATTERN (undobuf
.other_insn
));
2515 INSN_CODE (i3
) = insn_code_number
;
2516 PATTERN (i3
) = newpat
;
2518 if (GET_CODE (i3
) == CALL_INSN
&& CALL_INSN_FUNCTION_USAGE (i3
))
2520 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
2522 reset_used_flags (call_usage
);
2523 call_usage
= copy_rtx (call_usage
);
2526 replace_rtx (call_usage
, i2dest
, i2src
);
2529 replace_rtx (call_usage
, i1dest
, i1src
);
2531 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
2534 if (undobuf
.other_insn
)
2535 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2537 /* We had one special case above where I2 had more than one set and
2538 we replaced a destination of one of those sets with the destination
2539 of I3. In that case, we have to update LOG_LINKS of insns later
2540 in this basic block. Note that this (expensive) case is rare.
2542 Also, in this case, we must pretend that all REG_NOTEs for I2
2543 actually came from I3, so that REG_UNUSED notes from I2 will be
2544 properly handled. */
2546 if (i3_subst_into_i2
)
2548 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2549 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != USE
2550 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2551 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2552 && ! find_reg_note (i2
, REG_UNUSED
,
2553 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2554 for (temp
= NEXT_INSN (i2
);
2555 temp
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
2556 || BB_HEAD (this_basic_block
) != temp
);
2557 temp
= NEXT_INSN (temp
))
2558 if (temp
!= i3
&& INSN_P (temp
))
2559 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2560 if (XEXP (link
, 0) == i2
)
2561 XEXP (link
, 0) = i3
;
2566 while (XEXP (link
, 1))
2567 link
= XEXP (link
, 1);
2568 XEXP (link
, 1) = i2notes
;
2582 INSN_CODE (i2
) = i2_code_number
;
2583 PATTERN (i2
) = newi2pat
;
2587 PUT_CODE (i2
, NOTE
);
2588 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2589 NOTE_SOURCE_FILE (i2
) = 0;
2596 PUT_CODE (i1
, NOTE
);
2597 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2598 NOTE_SOURCE_FILE (i1
) = 0;
2601 /* Get death notes for everything that is now used in either I3 or
2602 I2 and used to die in a previous insn. If we built two new
2603 patterns, move from I1 to I2 then I2 to I3 so that we get the
2604 proper movement on registers that I2 modifies. */
2608 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2609 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2612 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2615 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2617 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
);
2619 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
);
2621 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
);
2623 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2625 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2626 know these are REG_UNUSED and want them to go to the desired insn,
2627 so we always pass it as i3. We have not counted the notes in
2628 reg_n_deaths yet, so we need to do so now. */
2630 if (newi2pat
&& new_i2_notes
)
2632 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2633 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2634 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2636 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
);
2641 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2642 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2643 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2645 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
);
2648 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2649 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2650 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2651 in that case, it might delete I2. Similarly for I2 and I1.
2652 Show an additional death due to the REG_DEAD note we make here. If
2653 we discard it in distribute_notes, we will decrement it again. */
2657 if (GET_CODE (i3dest_killed
) == REG
)
2658 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2660 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2661 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2663 NULL_RTX
, i2
, NULL_RTX
);
2665 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2667 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2670 if (i2dest_in_i2src
)
2672 if (GET_CODE (i2dest
) == REG
)
2673 REG_N_DEATHS (REGNO (i2dest
))++;
2675 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2676 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2677 NULL_RTX
, i2
, NULL_RTX
);
2679 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2680 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2683 if (i1dest_in_i1src
)
2685 if (GET_CODE (i1dest
) == REG
)
2686 REG_N_DEATHS (REGNO (i1dest
))++;
2688 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2689 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2690 NULL_RTX
, i2
, NULL_RTX
);
2692 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2693 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
);
2696 distribute_links (i3links
);
2697 distribute_links (i2links
);
2698 distribute_links (i1links
);
2700 if (GET_CODE (i2dest
) == REG
)
2703 rtx i2_insn
= 0, i2_val
= 0, set
;
2705 /* The insn that used to set this register doesn't exist, and
2706 this life of the register may not exist either. See if one of
2707 I3's links points to an insn that sets I2DEST. If it does,
2708 that is now the last known value for I2DEST. If we don't update
2709 this and I2 set the register to a value that depended on its old
2710 contents, we will get confused. If this insn is used, thing
2711 will be set correctly in combine_instructions. */
2713 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2714 if ((set
= single_set (XEXP (link
, 0))) != 0
2715 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2716 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2718 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2720 /* If the reg formerly set in I2 died only once and that was in I3,
2721 zero its use count so it won't make `reload' do any work. */
2723 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2724 && ! i2dest_in_i2src
)
2726 regno
= REGNO (i2dest
);
2727 REG_N_SETS (regno
)--;
2731 if (i1
&& GET_CODE (i1dest
) == REG
)
2734 rtx i1_insn
= 0, i1_val
= 0, set
;
2736 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2737 if ((set
= single_set (XEXP (link
, 0))) != 0
2738 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2739 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2741 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2743 regno
= REGNO (i1dest
);
2744 if (! added_sets_1
&& ! i1dest_in_i1src
)
2745 REG_N_SETS (regno
)--;
2748 /* Update reg_nonzero_bits et al for any changes that may have been made
2749 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2750 important. Because newi2pat can affect nonzero_bits of newpat */
2752 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2753 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2755 /* Set new_direct_jump_p if a new return or simple jump instruction
2758 If I3 is now an unconditional jump, ensure that it has a
2759 BARRIER following it since it may have initially been a
2760 conditional jump. It may also be the last nonnote insn. */
2762 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
2764 *new_direct_jump_p
= 1;
2765 mark_jump_label (PATTERN (i3
), i3
, 0);
2767 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2768 || GET_CODE (temp
) != BARRIER
)
2769 emit_barrier_after (i3
);
2772 if (undobuf
.other_insn
!= NULL_RTX
2773 && (returnjump_p (undobuf
.other_insn
)
2774 || any_uncondjump_p (undobuf
.other_insn
)))
2776 *new_direct_jump_p
= 1;
2778 if ((temp
= next_nonnote_insn (undobuf
.other_insn
)) == NULL_RTX
2779 || GET_CODE (temp
) != BARRIER
)
2780 emit_barrier_after (undobuf
.other_insn
);
2783 /* An NOOP jump does not need barrier, but it does need cleaning up
2785 if (GET_CODE (newpat
) == SET
2786 && SET_SRC (newpat
) == pc_rtx
2787 && SET_DEST (newpat
) == pc_rtx
)
2788 *new_direct_jump_p
= 1;
2791 combine_successes
++;
2794 if (added_links_insn
2795 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2796 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2797 return added_links_insn
;
2799 return newi2pat
? i2
: i3
;
2802 /* Undo all the modifications recorded in undobuf. */
2807 struct undo
*undo
, *next
;
2809 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2813 *undo
->where
.i
= undo
->old_contents
.i
;
2815 *undo
->where
.r
= undo
->old_contents
.r
;
2817 undo
->next
= undobuf
.frees
;
2818 undobuf
.frees
= undo
;
2824 /* We've committed to accepting the changes we made. Move all
2825 of the undos to the free list. */
2830 struct undo
*undo
, *next
;
2832 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2835 undo
->next
= undobuf
.frees
;
2836 undobuf
.frees
= undo
;
2842 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2843 where we have an arithmetic expression and return that point. LOC will
2846 try_combine will call this function to see if an insn can be split into
2850 find_split_point (rtx
*loc
, rtx insn
)
2853 enum rtx_code code
= GET_CODE (x
);
2855 unsigned HOST_WIDE_INT len
= 0;
2856 HOST_WIDE_INT pos
= 0;
2858 rtx inner
= NULL_RTX
;
2860 /* First special-case some codes. */
2864 #ifdef INSN_SCHEDULING
2865 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2867 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2870 return find_split_point (&SUBREG_REG (x
), insn
);
2874 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2875 using LO_SUM and HIGH. */
2876 if (GET_CODE (XEXP (x
, 0)) == CONST
2877 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2880 gen_rtx_LO_SUM (Pmode
,
2881 gen_rtx_HIGH (Pmode
, XEXP (x
, 0)),
2883 return &XEXP (XEXP (x
, 0), 0);
2887 /* If we have a PLUS whose second operand is a constant and the
2888 address is not valid, perhaps will can split it up using
2889 the machine-specific way to split large constants. We use
2890 the first pseudo-reg (one of the virtual regs) as a placeholder;
2891 it will not remain in the result. */
2892 if (GET_CODE (XEXP (x
, 0)) == PLUS
2893 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2894 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2896 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2897 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2900 /* This should have produced two insns, each of which sets our
2901 placeholder. If the source of the second is a valid address,
2902 we can make put both sources together and make a split point
2906 && NEXT_INSN (seq
) != NULL_RTX
2907 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
2908 && GET_CODE (seq
) == INSN
2909 && GET_CODE (PATTERN (seq
)) == SET
2910 && SET_DEST (PATTERN (seq
)) == reg
2911 && ! reg_mentioned_p (reg
,
2912 SET_SRC (PATTERN (seq
)))
2913 && GET_CODE (NEXT_INSN (seq
)) == INSN
2914 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
2915 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
2916 && memory_address_p (GET_MODE (x
),
2917 SET_SRC (PATTERN (NEXT_INSN (seq
)))))
2919 rtx src1
= SET_SRC (PATTERN (seq
));
2920 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
2922 /* Replace the placeholder in SRC2 with SRC1. If we can
2923 find where in SRC2 it was placed, that can become our
2924 split point and we can replace this address with SRC2.
2925 Just try two obvious places. */
2927 src2
= replace_rtx (src2
, reg
, src1
);
2929 if (XEXP (src2
, 0) == src1
)
2930 split
= &XEXP (src2
, 0);
2931 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2932 && XEXP (XEXP (src2
, 0), 0) == src1
)
2933 split
= &XEXP (XEXP (src2
, 0), 0);
2937 SUBST (XEXP (x
, 0), src2
);
2942 /* If that didn't work, perhaps the first operand is complex and
2943 needs to be computed separately, so make a split point there.
2944 This will occur on machines that just support REG + CONST
2945 and have a constant moved through some previous computation. */
2947 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2948 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2949 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2951 return &XEXP (XEXP (x
, 0), 0);
2957 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2958 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2959 we need to put the operand into a register. So split at that
2962 if (SET_DEST (x
) == cc0_rtx
2963 && GET_CODE (SET_SRC (x
)) != COMPARE
2964 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2965 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2966 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2967 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2968 return &SET_SRC (x
);
2971 /* See if we can split SET_SRC as it stands. */
2972 split
= find_split_point (&SET_SRC (x
), insn
);
2973 if (split
&& split
!= &SET_SRC (x
))
2976 /* See if we can split SET_DEST as it stands. */
2977 split
= find_split_point (&SET_DEST (x
), insn
);
2978 if (split
&& split
!= &SET_DEST (x
))
2981 /* See if this is a bitfield assignment with everything constant. If
2982 so, this is an IOR of an AND, so split it into that. */
2983 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2984 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2985 <= HOST_BITS_PER_WIDE_INT
)
2986 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2987 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2988 && GET_CODE (SET_SRC (x
)) == CONST_INT
2989 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2990 + INTVAL (XEXP (SET_DEST (x
), 2)))
2991 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2992 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2994 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2995 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
2996 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
2997 rtx dest
= XEXP (SET_DEST (x
), 0);
2998 enum machine_mode mode
= GET_MODE (dest
);
2999 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
3001 if (BITS_BIG_ENDIAN
)
3002 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
3006 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
3009 gen_binary (IOR
, mode
,
3010 gen_binary (AND
, mode
, dest
,
3011 gen_int_mode (~(mask
<< pos
),
3013 GEN_INT (src
<< pos
)));
3015 SUBST (SET_DEST (x
), dest
);
3017 split
= find_split_point (&SET_SRC (x
), insn
);
3018 if (split
&& split
!= &SET_SRC (x
))
3022 /* Otherwise, see if this is an operation that we can split into two.
3023 If so, try to split that. */
3024 code
= GET_CODE (SET_SRC (x
));
3029 /* If we are AND'ing with a large constant that is only a single
3030 bit and the result is only being used in a context where we
3031 need to know if it is zero or nonzero, replace it with a bit
3032 extraction. This will avoid the large constant, which might
3033 have taken more than one insn to make. If the constant were
3034 not a valid argument to the AND but took only one insn to make,
3035 this is no worse, but if it took more than one insn, it will
3038 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3039 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
3040 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
3041 && GET_CODE (SET_DEST (x
)) == REG
3042 && (split
= find_single_use (SET_DEST (x
), insn
, (rtx
*) 0)) != 0
3043 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
3044 && XEXP (*split
, 0) == SET_DEST (x
)
3045 && XEXP (*split
, 1) == const0_rtx
)
3047 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
3048 XEXP (SET_SRC (x
), 0),
3049 pos
, NULL_RTX
, 1, 1, 0, 0);
3050 if (extraction
!= 0)
3052 SUBST (SET_SRC (x
), extraction
);
3053 return find_split_point (loc
, insn
);
3059 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3060 is known to be on, this can be converted into a NEG of a shift. */
3061 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3062 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3063 && 1 <= (pos
= exact_log2
3064 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3065 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3067 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3071 gen_rtx_LSHIFTRT (mode
,
3072 XEXP (SET_SRC (x
), 0),
3075 split
= find_split_point (&SET_SRC (x
), insn
);
3076 if (split
&& split
!= &SET_SRC (x
))
3082 inner
= XEXP (SET_SRC (x
), 0);
3084 /* We can't optimize if either mode is a partial integer
3085 mode as we don't know how many bits are significant
3087 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3088 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3092 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3098 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3099 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3101 inner
= XEXP (SET_SRC (x
), 0);
3102 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3103 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3105 if (BITS_BIG_ENDIAN
)
3106 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3107 unsignedp
= (code
== ZERO_EXTRACT
);
3115 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3117 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3119 /* For unsigned, we have a choice of a shift followed by an
3120 AND or two shifts. Use two shifts for field sizes where the
3121 constant might be too large. We assume here that we can
3122 always at least get 8-bit constants in an AND insn, which is
3123 true for every current RISC. */
3125 if (unsignedp
&& len
<= 8)
3130 (mode
, gen_lowpart_for_combine (mode
, inner
),
3132 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3134 split
= find_split_point (&SET_SRC (x
), insn
);
3135 if (split
&& split
!= &SET_SRC (x
))
3142 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3143 gen_rtx_ASHIFT (mode
,
3144 gen_lowpart_for_combine (mode
, inner
),
3145 GEN_INT (GET_MODE_BITSIZE (mode
)
3147 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3149 split
= find_split_point (&SET_SRC (x
), insn
);
3150 if (split
&& split
!= &SET_SRC (x
))
3155 /* See if this is a simple operation with a constant as the second
3156 operand. It might be that this constant is out of range and hence
3157 could be used as a split point. */
3158 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3159 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3160 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3161 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3162 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3163 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3164 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3166 return &XEXP (SET_SRC (x
), 1);
3168 /* Finally, see if this is a simple operation with its first operand
3169 not in a register. The operation might require this operand in a
3170 register, so return it as a split point. We can always do this
3171 because if the first operand were another operation, we would have
3172 already found it as a split point. */
3173 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3174 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3175 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3176 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3177 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3178 return &XEXP (SET_SRC (x
), 0);
3184 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3185 it is better to write this as (not (ior A B)) so we can split it.
3186 Similarly for IOR. */
3187 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3190 gen_rtx_NOT (GET_MODE (x
),
3191 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
3193 XEXP (XEXP (x
, 0), 0),
3194 XEXP (XEXP (x
, 1), 0))));
3195 return find_split_point (loc
, insn
);
3198 /* Many RISC machines have a large set of logical insns. If the
3199 second operand is a NOT, put it first so we will try to split the
3200 other operand first. */
3201 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3203 rtx tem
= XEXP (x
, 0);
3204 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3205 SUBST (XEXP (x
, 1), tem
);
3213 /* Otherwise, select our actions depending on our rtx class. */
3214 switch (GET_RTX_CLASS (code
))
3216 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3218 split
= find_split_point (&XEXP (x
, 2), insn
);
3221 /* ... fall through ... */
3225 split
= find_split_point (&XEXP (x
, 1), insn
);
3228 /* ... fall through ... */
3230 /* Some machines have (and (shift ...) ...) insns. If X is not
3231 an AND, but XEXP (X, 0) is, use it as our split point. */
3232 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3233 return &XEXP (x
, 0);
3235 split
= find_split_point (&XEXP (x
, 0), insn
);
3241 /* Otherwise, we don't have a split point. */
3245 /* Throughout X, replace FROM with TO, and return the result.
3246 The result is TO if X is FROM;
3247 otherwise the result is X, but its contents may have been modified.
3248 If they were modified, a record was made in undobuf so that
3249 undo_all will (among other things) return X to its original state.
3251 If the number of changes necessary is too much to record to undo,
3252 the excess changes are not made, so the result is invalid.
3253 The changes already made can still be undone.
3254 undobuf.num_undo is incremented for such changes, so by testing that
3255 the caller can tell whether the result is valid.
3257 `n_occurrences' is incremented each time FROM is replaced.
3259 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3261 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3262 by copying if `n_occurrences' is nonzero. */
3265 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int unique_copy
)
3267 enum rtx_code code
= GET_CODE (x
);
3268 enum machine_mode op0_mode
= VOIDmode
;
3273 /* Two expressions are equal if they are identical copies of a shared
3274 RTX or if they are both registers with the same register number
3277 #define COMBINE_RTX_EQUAL_P(X,Y) \
3279 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3280 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3282 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3285 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3288 /* If X and FROM are the same register but different modes, they will
3289 not have been seen as equal above. However, flow.c will make a
3290 LOG_LINKS entry for that case. If we do nothing, we will try to
3291 rerecognize our original insn and, when it succeeds, we will
3292 delete the feeding insn, which is incorrect.
3294 So force this insn not to match in this (rare) case. */
3295 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3296 && REGNO (x
) == REGNO (from
))
3297 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3299 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3300 of which may contain things that can be combined. */
3301 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3304 /* It is possible to have a subexpression appear twice in the insn.
3305 Suppose that FROM is a register that appears within TO.
3306 Then, after that subexpression has been scanned once by `subst',
3307 the second time it is scanned, TO may be found. If we were
3308 to scan TO here, we would find FROM within it and create a
3309 self-referent rtl structure which is completely wrong. */
3310 if (COMBINE_RTX_EQUAL_P (x
, to
))
3313 /* Parallel asm_operands need special attention because all of the
3314 inputs are shared across the arms. Furthermore, unsharing the
3315 rtl results in recognition failures. Failure to handle this case
3316 specially can result in circular rtl.
3318 Solve this by doing a normal pass across the first entry of the
3319 parallel, and only processing the SET_DESTs of the subsequent
3322 if (code
== PARALLEL
3323 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3324 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3326 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3328 /* If this substitution failed, this whole thing fails. */
3329 if (GET_CODE (new) == CLOBBER
3330 && XEXP (new, 0) == const0_rtx
)
3333 SUBST (XVECEXP (x
, 0, 0), new);
3335 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3337 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3339 if (GET_CODE (dest
) != REG
3340 && GET_CODE (dest
) != CC0
3341 && GET_CODE (dest
) != PC
)
3343 new = subst (dest
, from
, to
, 0, unique_copy
);
3345 /* If this substitution failed, this whole thing fails. */
3346 if (GET_CODE (new) == CLOBBER
3347 && XEXP (new, 0) == const0_rtx
)
3350 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3356 len
= GET_RTX_LENGTH (code
);
3357 fmt
= GET_RTX_FORMAT (code
);
3359 /* We don't need to process a SET_DEST that is a register, CC0,
3360 or PC, so set up to skip this common case. All other cases
3361 where we want to suppress replacing something inside a
3362 SET_SRC are handled via the IN_DEST operand. */
3364 && (GET_CODE (SET_DEST (x
)) == REG
3365 || GET_CODE (SET_DEST (x
)) == CC0
3366 || GET_CODE (SET_DEST (x
)) == PC
))
3369 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3372 op0_mode
= GET_MODE (XEXP (x
, 0));
3374 for (i
= 0; i
< len
; i
++)
3379 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3381 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3383 new = (unique_copy
&& n_occurrences
3384 ? copy_rtx (to
) : to
);
3389 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3392 /* If this substitution failed, this whole thing
3394 if (GET_CODE (new) == CLOBBER
3395 && XEXP (new, 0) == const0_rtx
)
3399 SUBST (XVECEXP (x
, i
, j
), new);
3402 else if (fmt
[i
] == 'e')
3404 /* If this is a register being set, ignore it. */
3407 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3408 || code
== ZERO_EXTRACT
)
3410 && GET_CODE (new) == REG
)
3413 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3415 /* In general, don't install a subreg involving two
3416 modes not tieable. It can worsen register
3417 allocation, and can even make invalid reload
3418 insns, since the reg inside may need to be copied
3419 from in the outside mode, and that may be invalid
3420 if it is an fp reg copied in integer mode.
3422 We allow two exceptions to this: It is valid if
3423 it is inside another SUBREG and the mode of that
3424 SUBREG and the mode of the inside of TO is
3425 tieable and it is valid if X is a SET that copies
3428 if (GET_CODE (to
) == SUBREG
3429 && ! MODES_TIEABLE_P (GET_MODE (to
),
3430 GET_MODE (SUBREG_REG (to
)))
3431 && ! (code
== SUBREG
3432 && MODES_TIEABLE_P (GET_MODE (x
),
3433 GET_MODE (SUBREG_REG (to
))))
3435 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3438 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3440 #ifdef CANNOT_CHANGE_MODE_CLASS
3442 && GET_CODE (to
) == REG
3443 && REGNO (to
) < FIRST_PSEUDO_REGISTER
3444 && REG_CANNOT_CHANGE_MODE_P (REGNO (to
),
3447 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3450 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3454 /* If we are in a SET_DEST, suppress most cases unless we
3455 have gone inside a MEM, in which case we want to
3456 simplify the address. We assume here that things that
3457 are actually part of the destination have their inner
3458 parts in the first expression. This is true for SUBREG,
3459 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3460 things aside from REG and MEM that should appear in a
3462 new = subst (XEXP (x
, i
), from
, to
,
3464 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3465 || code
== ZERO_EXTRACT
))
3467 && i
== 0), unique_copy
);
3469 /* If we found that we will have to reject this combination,
3470 indicate that by returning the CLOBBER ourselves, rather than
3471 an expression containing it. This will speed things up as
3472 well as prevent accidents where two CLOBBERs are considered
3473 to be equal, thus producing an incorrect simplification. */
3475 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3478 if (GET_CODE (x
) == SUBREG
3479 && (GET_CODE (new) == CONST_INT
3480 || GET_CODE (new) == CONST_DOUBLE
))
3482 enum machine_mode mode
= GET_MODE (x
);
3484 x
= simplify_subreg (GET_MODE (x
), new,
3485 GET_MODE (SUBREG_REG (x
)),
3488 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
3490 else if (GET_CODE (new) == CONST_INT
3491 && GET_CODE (x
) == ZERO_EXTEND
)
3493 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
3494 new, GET_MODE (XEXP (x
, 0)));
3499 SUBST (XEXP (x
, i
), new);
3504 /* Try to simplify X. If the simplification changed the code, it is likely
3505 that further simplification will help, so loop, but limit the number
3506 of repetitions that will be performed. */
3508 for (i
= 0; i
< 4; i
++)
3510 /* If X is sufficiently simple, don't bother trying to do anything
3512 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3513 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3515 if (GET_CODE (x
) == code
)
3518 code
= GET_CODE (x
);
3520 /* We no longer know the original mode of operand 0 since we
3521 have changed the form of X) */
3522 op0_mode
= VOIDmode
;
3528 /* Simplify X, a piece of RTL. We just operate on the expression at the
3529 outer level; call `subst' to simplify recursively. Return the new
3532 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3533 will be the iteration even if an expression with a code different from
3534 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3537 combine_simplify_rtx (rtx x
, enum machine_mode op0_mode
, int last
,
3540 enum rtx_code code
= GET_CODE (x
);
3541 enum machine_mode mode
= GET_MODE (x
);
3546 /* If this is a commutative operation, put a constant last and a complex
3547 expression first. We don't need to do this for comparisons here. */
3548 if (GET_RTX_CLASS (code
) == 'c'
3549 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
3552 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3553 SUBST (XEXP (x
, 1), temp
);
3556 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3557 sign extension of a PLUS with a constant, reverse the order of the sign
3558 extension and the addition. Note that this not the same as the original
3559 code, but overflow is undefined for signed values. Also note that the
3560 PLUS will have been partially moved "inside" the sign-extension, so that
3561 the first operand of X will really look like:
3562 (ashiftrt (plus (ashift A C4) C5) C4).
3564 (plus (ashiftrt (ashift A C4) C2) C4)
3565 and replace the first operand of X with that expression. Later parts
3566 of this function may simplify the expression further.
3568 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3569 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3570 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3572 We do this to simplify address expressions. */
3574 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3575 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3576 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3577 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3578 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3579 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3580 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3581 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3582 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3583 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3584 XEXP (XEXP (x
, 0), 1))) != 0)
3587 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3588 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3589 INTVAL (XEXP (XEXP (x
, 0), 1)));
3591 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3592 INTVAL (XEXP (XEXP (x
, 0), 1)));
3594 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3597 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3598 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3599 things. Check for cases where both arms are testing the same
3602 Don't do anything if all operands are very simple. */
3604 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3605 || GET_RTX_CLASS (code
) == '<')
3606 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3607 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3608 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3610 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3611 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3612 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3614 || (GET_RTX_CLASS (code
) == '1'
3615 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3616 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3617 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3620 rtx cond
, true_rtx
, false_rtx
;
3622 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
3624 /* If everything is a comparison, what we have is highly unlikely
3625 to be simpler, so don't use it. */
3626 && ! (GET_RTX_CLASS (code
) == '<'
3627 && (GET_RTX_CLASS (GET_CODE (true_rtx
)) == '<'
3628 || GET_RTX_CLASS (GET_CODE (false_rtx
)) == '<')))
3630 rtx cop1
= const0_rtx
;
3631 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3633 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3636 /* Simplify the alternative arms; this may collapse the true and
3637 false arms to store-flag values. Be careful to use copy_rtx
3638 here since true_rtx or false_rtx might share RTL with x as a
3639 result of the if_then_else_cond call above. */
3640 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3641 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0);
3643 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3644 is unlikely to be simpler. */
3645 if (general_operand (true_rtx
, VOIDmode
)
3646 && general_operand (false_rtx
, VOIDmode
))
3648 enum rtx_code reversed
;
3650 /* Restarting if we generate a store-flag expression will cause
3651 us to loop. Just drop through in this case. */
3653 /* If the result values are STORE_FLAG_VALUE and zero, we can
3654 just make the comparison operation. */
3655 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
3656 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3657 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
3658 && ((reversed
= reversed_comparison_code_parts
3659 (cond_code
, cond
, cop1
, NULL
))
3661 x
= gen_binary (reversed
, mode
, cond
, cop1
);
3663 /* Likewise, we can make the negate of a comparison operation
3664 if the result values are - STORE_FLAG_VALUE and zero. */
3665 else if (GET_CODE (true_rtx
) == CONST_INT
3666 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
3667 && false_rtx
== const0_rtx
)
3668 x
= simplify_gen_unary (NEG
, mode
,
3669 gen_binary (cond_code
, mode
, cond
,
3672 else if (GET_CODE (false_rtx
) == CONST_INT
3673 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
3674 && true_rtx
== const0_rtx
3675 && ((reversed
= reversed_comparison_code_parts
3676 (cond_code
, cond
, cop1
, NULL
))
3678 x
= simplify_gen_unary (NEG
, mode
,
3679 gen_binary (reversed
, mode
,
3683 return gen_rtx_IF_THEN_ELSE (mode
,
3684 gen_binary (cond_code
, VOIDmode
,
3686 true_rtx
, false_rtx
);
3688 code
= GET_CODE (x
);
3689 op0_mode
= VOIDmode
;
3694 /* Try to fold this expression in case we have constants that weren't
3697 switch (GET_RTX_CLASS (code
))
3700 if (op0_mode
== VOIDmode
)
3701 op0_mode
= GET_MODE (XEXP (x
, 0));
3702 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3706 enum machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
3707 if (cmp_mode
== VOIDmode
)
3709 cmp_mode
= GET_MODE (XEXP (x
, 1));
3710 if (cmp_mode
== VOIDmode
)
3711 cmp_mode
= op0_mode
;
3713 temp
= simplify_relational_operation (code
, cmp_mode
,
3714 XEXP (x
, 0), XEXP (x
, 1));
3716 #ifdef FLOAT_STORE_FLAG_VALUE
3717 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3719 if (temp
== const0_rtx
)
3720 temp
= CONST0_RTX (mode
);
3722 temp
= CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode
),
3729 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3733 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3734 XEXP (x
, 1), XEXP (x
, 2));
3741 code
= GET_CODE (temp
);
3742 op0_mode
= VOIDmode
;
3743 mode
= GET_MODE (temp
);
3746 /* First see if we can apply the inverse distributive law. */
3747 if (code
== PLUS
|| code
== MINUS
3748 || code
== AND
|| code
== IOR
|| code
== XOR
)
3750 x
= apply_distributive_law (x
);
3751 code
= GET_CODE (x
);
3752 op0_mode
= VOIDmode
;
3755 /* If CODE is an associative operation not otherwise handled, see if we
3756 can associate some operands. This can win if they are constants or
3757 if they are logically related (i.e. (a & b) & a). */
3758 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
3759 || code
== AND
|| code
== IOR
|| code
== XOR
3760 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3761 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
3762 || (flag_unsafe_math_optimizations
&& FLOAT_MODE_P (mode
))))
3764 if (GET_CODE (XEXP (x
, 0)) == code
)
3766 rtx other
= XEXP (XEXP (x
, 0), 0);
3767 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3768 rtx inner_op1
= XEXP (x
, 1);
3771 /* Make sure we pass the constant operand if any as the second
3772 one if this is a commutative operation. */
3773 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3775 rtx tem
= inner_op0
;
3776 inner_op0
= inner_op1
;
3779 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3780 : code
== DIV
? MULT
3782 mode
, inner_op0
, inner_op1
);
3784 /* For commutative operations, try the other pair if that one
3786 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3788 other
= XEXP (XEXP (x
, 0), 1);
3789 inner
= simplify_binary_operation (code
, mode
,
3790 XEXP (XEXP (x
, 0), 0),
3795 return gen_binary (code
, mode
, other
, inner
);
3799 /* A little bit of algebraic simplification here. */
3803 /* Ensure that our address has any ASHIFTs converted to MULT in case
3804 address-recognizing predicates are called later. */
3805 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3806 SUBST (XEXP (x
, 0), temp
);
3810 if (op0_mode
== VOIDmode
)
3811 op0_mode
= GET_MODE (SUBREG_REG (x
));
3813 /* simplify_subreg can't use gen_lowpart_for_combine. */
3814 if (CONSTANT_P (SUBREG_REG (x
))
3815 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
3816 /* Don't call gen_lowpart_for_combine if the inner mode
3817 is VOIDmode and we cannot simplify it, as SUBREG without
3818 inner mode is invalid. */
3819 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
3820 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
3821 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3823 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
3827 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
3833 /* Don't change the mode of the MEM if that would change the meaning
3835 if (GET_CODE (SUBREG_REG (x
)) == MEM
3836 && (MEM_VOLATILE_P (SUBREG_REG (x
))
3837 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0))))
3838 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3840 /* Note that we cannot do any narrowing for non-constants since
3841 we might have been counting on using the fact that some bits were
3842 zero. We now do this in the SET. */
3847 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3848 && subreg_lowpart_p (XEXP (x
, 0))
3849 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3850 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3851 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3852 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3854 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3856 x
= gen_rtx_ROTATE (inner_mode
,
3857 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
3859 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3860 return gen_lowpart_for_combine (mode
, x
);
3863 /* Apply De Morgan's laws to reduce number of patterns for machines
3864 with negating logical insns (and-not, nand, etc.). If result has
3865 only one NOT, put it first, since that is how the patterns are
3868 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3870 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3871 enum machine_mode op_mode
;
3873 op_mode
= GET_MODE (in1
);
3874 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
3876 op_mode
= GET_MODE (in2
);
3877 if (op_mode
== VOIDmode
)
3879 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
3881 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
3884 in2
= in1
; in1
= tem
;
3887 return gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3893 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3894 if (GET_CODE (XEXP (x
, 0)) == XOR
3895 && XEXP (XEXP (x
, 0), 1) == const1_rtx
3896 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3897 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3899 temp
= expand_compound_operation (XEXP (x
, 0));
3901 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3902 replaced by (lshiftrt X C). This will convert
3903 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3905 if (GET_CODE (temp
) == ASHIFTRT
3906 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3907 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3908 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3909 INTVAL (XEXP (temp
, 1)));
3911 /* If X has only a single bit that might be nonzero, say, bit I, convert
3912 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3913 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3914 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3915 or a SUBREG of one since we'd be making the expression more
3916 complex if it was just a register. */
3918 if (GET_CODE (temp
) != REG
3919 && ! (GET_CODE (temp
) == SUBREG
3920 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3921 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3923 rtx temp1
= simplify_shift_const
3924 (NULL_RTX
, ASHIFTRT
, mode
,
3925 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3926 GET_MODE_BITSIZE (mode
) - 1 - i
),
3927 GET_MODE_BITSIZE (mode
) - 1 - i
);
3929 /* If all we did was surround TEMP with the two shifts, we
3930 haven't improved anything, so don't use it. Otherwise,
3931 we are better off with TEMP1. */
3932 if (GET_CODE (temp1
) != ASHIFTRT
3933 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3934 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3940 /* We can't handle truncation to a partial integer mode here
3941 because we don't know the real bitsize of the partial
3943 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3946 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3947 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3948 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3950 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3951 GET_MODE_MASK (mode
), NULL_RTX
, 0));
3953 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3954 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
3955 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
3956 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
3957 return XEXP (XEXP (x
, 0), 0);
3959 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3960 (OP:SI foo:SI) if OP is NEG or ABS. */
3961 if ((GET_CODE (XEXP (x
, 0)) == ABS
3962 || GET_CODE (XEXP (x
, 0)) == NEG
)
3963 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
3964 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
3965 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
3966 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
3967 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
3969 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3971 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3972 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
3973 && subreg_lowpart_p (XEXP (x
, 0)))
3974 return SUBREG_REG (XEXP (x
, 0));
3976 /* If we know that the value is already truncated, we can
3977 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3978 is nonzero for the corresponding modes. But don't do this
3979 for an (LSHIFTRT (MULT ...)) since this will cause problems
3980 with the umulXi3_highpart patterns. */
3981 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3982 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
3983 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
3984 >= (unsigned int) (GET_MODE_BITSIZE (mode
) + 1)
3985 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
3986 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
3987 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3989 /* A truncate of a comparison can be replaced with a subreg if
3990 STORE_FLAG_VALUE permits. This is like the previous test,
3991 but it works even if the comparison is done in a mode larger
3992 than HOST_BITS_PER_WIDE_INT. */
3993 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3994 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3995 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
3996 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
3998 /* Similarly, a truncate of a register whose value is a
3999 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4001 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4002 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
4003 && (temp
= get_last_value (XEXP (x
, 0)))
4004 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4005 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4009 case FLOAT_TRUNCATE
:
4010 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4011 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4012 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4013 return XEXP (XEXP (x
, 0), 0);
4015 /* (float_truncate:SF (float_truncate:DF foo:XF))
4016 = (float_truncate:SF foo:XF).
4017 This may eliminate double rounding, so it is unsafe.
4019 (float_truncate:SF (float_extend:XF foo:DF))
4020 = (float_truncate:SF foo:DF).
4022 (float_truncate:DF (float_extend:XF foo:SF))
4023 = (float_extend:SF foo:DF). */
4024 if ((GET_CODE (XEXP (x
, 0)) == FLOAT_TRUNCATE
4025 && flag_unsafe_math_optimizations
)
4026 || GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
)
4027 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x
, 0),
4029 > GET_MODE_SIZE (mode
)
4030 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
4032 XEXP (XEXP (x
, 0), 0), mode
);
4034 /* (float_truncate (float x)) is (float x) */
4035 if (GET_CODE (XEXP (x
, 0)) == FLOAT
4036 && (flag_unsafe_math_optimizations
4037 || ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4038 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4039 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4040 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4041 return simplify_gen_unary (FLOAT
, mode
,
4042 XEXP (XEXP (x
, 0), 0),
4043 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4045 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4046 (OP:SF foo:SF) if OP is NEG or ABS. */
4047 if ((GET_CODE (XEXP (x
, 0)) == ABS
4048 || GET_CODE (XEXP (x
, 0)) == NEG
)
4049 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4050 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4051 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4052 XEXP (XEXP (XEXP (x
, 0), 0), 0), mode
);
4054 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4055 is (float_truncate:SF x). */
4056 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4057 && subreg_lowpart_p (XEXP (x
, 0))
4058 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4059 return SUBREG_REG (XEXP (x
, 0));
4062 /* (float_extend (float_extend x)) is (float_extend x)
4064 (float_extend (float x)) is (float x) assuming that double
4065 rounding can't happen.
4067 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4068 || (GET_CODE (XEXP (x
, 0)) == FLOAT
4069 && ((unsigned)significand_size (GET_MODE (XEXP (x
, 0)))
4070 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x
, 0), 0)))
4071 - num_sign_bit_copies (XEXP (XEXP (x
, 0), 0),
4072 GET_MODE (XEXP (XEXP (x
, 0), 0)))))))
4073 return simplify_gen_unary (GET_CODE (XEXP (x
, 0)), mode
,
4074 XEXP (XEXP (x
, 0), 0),
4075 GET_MODE (XEXP (XEXP (x
, 0), 0)));
4080 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4081 using cc0, in which case we want to leave it as a COMPARE
4082 so we can distinguish it from a register-register-copy. */
4083 if (XEXP (x
, 1) == const0_rtx
)
4086 /* x - 0 is the same as x unless x's mode has signed zeros and
4087 allows rounding towards -infinity. Under those conditions,
4089 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x
, 0)))
4090 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x
, 0))))
4091 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4097 /* (const (const X)) can become (const X). Do it this way rather than
4098 returning the inner CONST since CONST can be shared with a
4100 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4101 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4106 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4107 can add in an offset. find_split_point will split this address up
4108 again if it doesn't match. */
4109 if (GET_CODE (XEXP (x
, 0)) == HIGH
4110 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4116 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4118 if (GET_CODE (XEXP (x
, 0)) == MULT
4119 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == NEG
)
4123 in1
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
4124 in2
= XEXP (XEXP (x
, 0), 1);
4125 return gen_binary (MINUS
, mode
, XEXP (x
, 1),
4126 gen_binary (MULT
, mode
, in1
, in2
));
4129 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4130 outermost. That's because that's the way indexed addresses are
4131 supposed to appear. This code used to check many more cases, but
4132 they are now checked elsewhere. */
4133 if (GET_CODE (XEXP (x
, 0)) == PLUS
4134 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4135 return gen_binary (PLUS
, mode
,
4136 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4138 XEXP (XEXP (x
, 0), 1));
4140 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4141 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4142 bit-field and can be replaced by either a sign_extend or a
4143 sign_extract. The `and' may be a zero_extend and the two
4144 <c>, -<c> constants may be reversed. */
4145 if (GET_CODE (XEXP (x
, 0)) == XOR
4146 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4147 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4148 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
4149 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4150 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4151 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4152 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4153 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4154 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4155 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4156 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4157 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4158 == (unsigned int) i
+ 1))))
4159 return simplify_shift_const
4160 (NULL_RTX
, ASHIFTRT
, mode
,
4161 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4162 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4163 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4164 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4166 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4167 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4168 is 1. This produces better code than the alternative immediately
4170 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4171 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4172 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
))
4173 && (reversed
= reversed_comparison (XEXP (x
, 0), mode
,
4174 XEXP (XEXP (x
, 0), 0),
4175 XEXP (XEXP (x
, 0), 1))))
4177 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
4179 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4180 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4181 the bitsize of the mode - 1. This allows simplification of
4182 "a = (b & 8) == 0;" */
4183 if (XEXP (x
, 1) == constm1_rtx
4184 && GET_CODE (XEXP (x
, 0)) != REG
4185 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
4186 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4187 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4188 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4189 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4190 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
4191 GET_MODE_BITSIZE (mode
) - 1),
4192 GET_MODE_BITSIZE (mode
) - 1);
4194 /* If we are adding two things that have no bits in common, convert
4195 the addition into an IOR. This will often be further simplified,
4196 for example in cases like ((a & 1) + (a & 2)), which can
4199 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4200 && (nonzero_bits (XEXP (x
, 0), mode
)
4201 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4203 /* Try to simplify the expression further. */
4204 rtx tor
= gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4205 temp
= combine_simplify_rtx (tor
, mode
, last
, in_dest
);
4207 /* If we could, great. If not, do not go ahead with the IOR
4208 replacement, since PLUS appears in many special purpose
4209 address arithmetic instructions. */
4210 if (GET_CODE (temp
) != CLOBBER
&& temp
!= tor
)
4216 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4217 by reversing the comparison code if valid. */
4218 if (STORE_FLAG_VALUE
== 1
4219 && XEXP (x
, 0) == const1_rtx
4220 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4221 && (reversed
= reversed_comparison (XEXP (x
, 1), mode
,
4222 XEXP (XEXP (x
, 1), 0),
4223 XEXP (XEXP (x
, 1), 1))))
4226 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4227 (and <foo> (const_int pow2-1)) */
4228 if (GET_CODE (XEXP (x
, 1)) == AND
4229 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4230 && exact_log2 (-INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4231 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4232 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4233 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4235 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4237 if (GET_CODE (XEXP (x
, 1)) == MULT
4238 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == NEG
)
4242 in1
= XEXP (XEXP (XEXP (x
, 1), 0), 0);
4243 in2
= XEXP (XEXP (x
, 1), 1);
4244 return gen_binary (PLUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4248 /* Canonicalize (minus (neg A) (mult B C)) to
4249 (minus (mult (neg B) C) A). */
4250 if (GET_CODE (XEXP (x
, 1)) == MULT
4251 && GET_CODE (XEXP (x
, 0)) == NEG
)
4255 in1
= simplify_gen_unary (NEG
, mode
, XEXP (XEXP (x
, 1), 0), mode
);
4256 in2
= XEXP (XEXP (x
, 1), 1);
4257 return gen_binary (MINUS
, mode
, gen_binary (MULT
, mode
, in1
, in2
),
4258 XEXP (XEXP (x
, 0), 0));
4261 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4263 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4264 return gen_binary (MINUS
, mode
,
4265 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4266 XEXP (XEXP (x
, 1), 0)),
4267 XEXP (XEXP (x
, 1), 1));
4271 /* If we have (mult (plus A B) C), apply the distributive law and then
4272 the inverse distributive law to see if things simplify. This
4273 occurs mostly in addresses, often when unrolling loops. */
4275 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4277 x
= apply_distributive_law
4278 (gen_binary (PLUS
, mode
,
4279 gen_binary (MULT
, mode
,
4280 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4281 gen_binary (MULT
, mode
,
4282 XEXP (XEXP (x
, 0), 1),
4283 copy_rtx (XEXP (x
, 1)))));
4285 if (GET_CODE (x
) != MULT
)
4288 /* Try simplify a*(b/c) as (a*b)/c. */
4289 if (FLOAT_MODE_P (mode
) && flag_unsafe_math_optimizations
4290 && GET_CODE (XEXP (x
, 0)) == DIV
)
4292 rtx tem
= simplify_binary_operation (MULT
, mode
,
4293 XEXP (XEXP (x
, 0), 0),
4296 return gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
4301 /* If this is a divide by a power of two, treat it as a shift if
4302 its first operand is a shift. */
4303 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4304 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4305 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4306 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4307 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4308 || GET_CODE (XEXP (x
, 0)) == ROTATE
4309 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4310 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4314 case GT
: case GTU
: case GE
: case GEU
:
4315 case LT
: case LTU
: case LE
: case LEU
:
4316 case UNEQ
: case LTGT
:
4317 case UNGT
: case UNGE
:
4318 case UNLT
: case UNLE
:
4319 case UNORDERED
: case ORDERED
:
4320 /* If the first operand is a condition code, we can't do anything
4322 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4323 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4324 && ! CC0_P (XEXP (x
, 0))))
4326 rtx op0
= XEXP (x
, 0);
4327 rtx op1
= XEXP (x
, 1);
4328 enum rtx_code new_code
;
4330 if (GET_CODE (op0
) == COMPARE
)
4331 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4333 /* Simplify our comparison, if possible. */
4334 new_code
= simplify_comparison (code
, &op0
, &op1
);
4336 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4337 if only the low-order bit is possibly nonzero in X (such as when
4338 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4339 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4340 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4343 Remove any ZERO_EXTRACT we made when thinking this was a
4344 comparison. It may now be simpler to use, e.g., an AND. If a
4345 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4346 the call to make_compound_operation in the SET case. */
4348 if (STORE_FLAG_VALUE
== 1
4349 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4350 && op1
== const0_rtx
4351 && mode
== GET_MODE (op0
)
4352 && nonzero_bits (op0
, mode
) == 1)
4353 return gen_lowpart_for_combine (mode
,
4354 expand_compound_operation (op0
));
4356 else if (STORE_FLAG_VALUE
== 1
4357 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4358 && op1
== const0_rtx
4359 && mode
== GET_MODE (op0
)
4360 && (num_sign_bit_copies (op0
, mode
)
4361 == GET_MODE_BITSIZE (mode
)))
4363 op0
= expand_compound_operation (op0
);
4364 return simplify_gen_unary (NEG
, mode
,
4365 gen_lowpart_for_combine (mode
, op0
),
4369 else if (STORE_FLAG_VALUE
== 1
4370 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4371 && op1
== const0_rtx
4372 && mode
== GET_MODE (op0
)
4373 && nonzero_bits (op0
, mode
) == 1)
4375 op0
= expand_compound_operation (op0
);
4376 return gen_binary (XOR
, mode
,
4377 gen_lowpart_for_combine (mode
, op0
),
4381 else if (STORE_FLAG_VALUE
== 1
4382 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4383 && op1
== const0_rtx
4384 && mode
== GET_MODE (op0
)
4385 && (num_sign_bit_copies (op0
, mode
)
4386 == GET_MODE_BITSIZE (mode
)))
4388 op0
= expand_compound_operation (op0
);
4389 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4392 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4394 if (STORE_FLAG_VALUE
== -1
4395 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4396 && op1
== const0_rtx
4397 && (num_sign_bit_copies (op0
, mode
)
4398 == GET_MODE_BITSIZE (mode
)))
4399 return gen_lowpart_for_combine (mode
,
4400 expand_compound_operation (op0
));
4402 else if (STORE_FLAG_VALUE
== -1
4403 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4404 && op1
== const0_rtx
4405 && mode
== GET_MODE (op0
)
4406 && nonzero_bits (op0
, mode
) == 1)
4408 op0
= expand_compound_operation (op0
);
4409 return simplify_gen_unary (NEG
, mode
,
4410 gen_lowpart_for_combine (mode
, op0
),
4414 else if (STORE_FLAG_VALUE
== -1
4415 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4416 && op1
== const0_rtx
4417 && mode
== GET_MODE (op0
)
4418 && (num_sign_bit_copies (op0
, mode
)
4419 == GET_MODE_BITSIZE (mode
)))
4421 op0
= expand_compound_operation (op0
);
4422 return simplify_gen_unary (NOT
, mode
,
4423 gen_lowpart_for_combine (mode
, op0
),
4427 /* If X is 0/1, (eq X 0) is X-1. */
4428 else if (STORE_FLAG_VALUE
== -1
4429 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4430 && op1
== const0_rtx
4431 && mode
== GET_MODE (op0
)
4432 && nonzero_bits (op0
, mode
) == 1)
4434 op0
= expand_compound_operation (op0
);
4435 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4438 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4439 one bit that might be nonzero, we can convert (ne x 0) to
4440 (ashift x c) where C puts the bit in the sign bit. Remove any
4441 AND with STORE_FLAG_VALUE when we are done, since we are only
4442 going to test the sign bit. */
4443 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4444 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4445 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4446 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
4447 && op1
== const0_rtx
4448 && mode
== GET_MODE (op0
)
4449 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4451 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4452 expand_compound_operation (op0
),
4453 GET_MODE_BITSIZE (mode
) - 1 - i
);
4454 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4460 /* If the code changed, return a whole new comparison. */
4461 if (new_code
!= code
)
4462 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
4464 /* Otherwise, keep this operation, but maybe change its operands.
4465 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4466 SUBST (XEXP (x
, 0), op0
);
4467 SUBST (XEXP (x
, 1), op1
);
4472 return simplify_if_then_else (x
);
4478 /* If we are processing SET_DEST, we are done. */
4482 return expand_compound_operation (x
);
4485 return simplify_set (x
);
4490 return simplify_logical (x
, last
);
4493 /* (abs (neg <foo>)) -> (abs <foo>) */
4494 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4495 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4497 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4499 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4502 /* If operand is something known to be positive, ignore the ABS. */
4503 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4504 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4505 <= HOST_BITS_PER_WIDE_INT
)
4506 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4507 & ((HOST_WIDE_INT
) 1
4508 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4512 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4513 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4514 return gen_rtx_NEG (mode
, XEXP (x
, 0));
4519 /* (ffs (*_extend <X>)) = (ffs <X>) */
4520 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4521 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4522 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4527 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4528 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4529 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4533 /* (float (sign_extend <X>)) = (float <X>). */
4534 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4535 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4543 /* If this is a shift by a constant amount, simplify it. */
4544 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4545 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4546 INTVAL (XEXP (x
, 1)));
4548 #ifdef SHIFT_COUNT_TRUNCATED
4549 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4551 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
4553 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4562 rtx op0
= XEXP (x
, 0);
4563 rtx op1
= XEXP (x
, 1);
4566 if (GET_CODE (op1
) != PARALLEL
)
4568 len
= XVECLEN (op1
, 0);
4570 && GET_CODE (XVECEXP (op1
, 0, 0)) == CONST_INT
4571 && GET_CODE (op0
) == VEC_CONCAT
)
4573 int offset
= INTVAL (XVECEXP (op1
, 0, 0)) * GET_MODE_SIZE (GET_MODE (x
));
4575 /* Try to find the element in the VEC_CONCAT. */
4578 if (GET_MODE (op0
) == GET_MODE (x
))
4580 if (GET_CODE (op0
) == VEC_CONCAT
)
4582 HOST_WIDE_INT op0_size
= GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)));
4583 if (op0_size
< offset
)
4584 op0
= XEXP (op0
, 0);
4588 op0
= XEXP (op0
, 1);
4606 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4609 simplify_if_then_else (rtx x
)
4611 enum machine_mode mode
= GET_MODE (x
);
4612 rtx cond
= XEXP (x
, 0);
4613 rtx true_rtx
= XEXP (x
, 1);
4614 rtx false_rtx
= XEXP (x
, 2);
4615 enum rtx_code true_code
= GET_CODE (cond
);
4616 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4619 enum rtx_code false_code
;
4622 /* Simplify storing of the truth value. */
4623 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
4624 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4626 /* Also when the truth value has to be reversed. */
4628 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
4629 && (reversed
= reversed_comparison (cond
, mode
, XEXP (cond
, 0),
4633 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4634 in it is being compared against certain values. Get the true and false
4635 comparisons and see if that says anything about the value of each arm. */
4638 && ((false_code
= combine_reversed_comparison_code (cond
))
4640 && GET_CODE (XEXP (cond
, 0)) == REG
)
4643 rtx from
= XEXP (cond
, 0);
4644 rtx true_val
= XEXP (cond
, 1);
4645 rtx false_val
= true_val
;
4648 /* If FALSE_CODE is EQ, swap the codes and arms. */
4650 if (false_code
== EQ
)
4652 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4653 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4656 /* If we are comparing against zero and the expression being tested has
4657 only a single bit that might be nonzero, that is its value when it is
4658 not equal to zero. Similarly if it is known to be -1 or 0. */
4660 if (true_code
== EQ
&& true_val
== const0_rtx
4661 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4662 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4663 else if (true_code
== EQ
&& true_val
== const0_rtx
4664 && (num_sign_bit_copies (from
, GET_MODE (from
))
4665 == GET_MODE_BITSIZE (GET_MODE (from
))))
4666 false_code
= EQ
, false_val
= constm1_rtx
;
4668 /* Now simplify an arm if we know the value of the register in the
4669 branch and it is used in the arm. Be careful due to the potential
4670 of locally-shared RTL. */
4672 if (reg_mentioned_p (from
, true_rtx
))
4673 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
4675 pc_rtx
, pc_rtx
, 0, 0);
4676 if (reg_mentioned_p (from
, false_rtx
))
4677 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
4679 pc_rtx
, pc_rtx
, 0, 0);
4681 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
4682 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
4684 true_rtx
= XEXP (x
, 1);
4685 false_rtx
= XEXP (x
, 2);
4686 true_code
= GET_CODE (cond
);
4689 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4690 reversed, do so to avoid needing two sets of patterns for
4691 subtract-and-branch insns. Similarly if we have a constant in the true
4692 arm, the false arm is the same as the first operand of the comparison, or
4693 the false arm is more complicated than the true arm. */
4696 && combine_reversed_comparison_code (cond
) != UNKNOWN
4697 && (true_rtx
== pc_rtx
4698 || (CONSTANT_P (true_rtx
)
4699 && GET_CODE (false_rtx
) != CONST_INT
&& false_rtx
!= pc_rtx
)
4700 || true_rtx
== const0_rtx
4701 || (GET_RTX_CLASS (GET_CODE (true_rtx
)) == 'o'
4702 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4703 || (GET_CODE (true_rtx
) == SUBREG
4704 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx
))) == 'o'
4705 && GET_RTX_CLASS (GET_CODE (false_rtx
)) != 'o')
4706 || reg_mentioned_p (true_rtx
, false_rtx
)
4707 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
4709 true_code
= reversed_comparison_code (cond
, NULL
);
4711 reversed_comparison (cond
, GET_MODE (cond
), XEXP (cond
, 0),
4714 SUBST (XEXP (x
, 1), false_rtx
);
4715 SUBST (XEXP (x
, 2), true_rtx
);
4717 temp
= true_rtx
, true_rtx
= false_rtx
, false_rtx
= temp
;
4720 /* It is possible that the conditional has been simplified out. */
4721 true_code
= GET_CODE (cond
);
4722 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4725 /* If the two arms are identical, we don't need the comparison. */
4727 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
4730 /* Convert a == b ? b : a to "a". */
4731 if (true_code
== EQ
&& ! side_effects_p (cond
)
4732 && !HONOR_NANS (mode
)
4733 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
4734 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
4736 else if (true_code
== NE
&& ! side_effects_p (cond
)
4737 && !HONOR_NANS (mode
)
4738 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4739 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
4742 /* Look for cases where we have (abs x) or (neg (abs X)). */
4744 if (GET_MODE_CLASS (mode
) == MODE_INT
4745 && GET_CODE (false_rtx
) == NEG
4746 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
4748 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
4749 && ! side_effects_p (true_rtx
))
4754 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
4758 simplify_gen_unary (NEG
, mode
,
4759 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
4765 /* Look for MIN or MAX. */
4767 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
4769 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
4770 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
4771 && ! side_effects_p (cond
))
4776 return gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
4779 return gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
4782 return gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
4785 return gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
4790 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4791 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4792 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4793 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4794 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4795 neither 1 or -1, but it isn't worth checking for. */
4797 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4799 && GET_MODE_CLASS (mode
) == MODE_INT
4800 && ! side_effects_p (x
))
4802 rtx t
= make_compound_operation (true_rtx
, SET
);
4803 rtx f
= make_compound_operation (false_rtx
, SET
);
4804 rtx cond_op0
= XEXP (cond
, 0);
4805 rtx cond_op1
= XEXP (cond
, 1);
4806 enum rtx_code op
= NIL
, extend_op
= NIL
;
4807 enum machine_mode m
= mode
;
4808 rtx z
= 0, c1
= NULL_RTX
;
4810 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4811 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4812 || GET_CODE (t
) == ASHIFT
4813 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4814 && rtx_equal_p (XEXP (t
, 0), f
))
4815 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4817 /* If an identity-zero op is commutative, check whether there
4818 would be a match if we swapped the operands. */
4819 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4820 || GET_CODE (t
) == XOR
)
4821 && rtx_equal_p (XEXP (t
, 1), f
))
4822 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4823 else if (GET_CODE (t
) == SIGN_EXTEND
4824 && (GET_CODE (XEXP (t
, 0)) == PLUS
4825 || GET_CODE (XEXP (t
, 0)) == MINUS
4826 || GET_CODE (XEXP (t
, 0)) == IOR
4827 || GET_CODE (XEXP (t
, 0)) == XOR
4828 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4829 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4830 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4831 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4832 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4833 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4834 && (num_sign_bit_copies (f
, GET_MODE (f
))
4836 (GET_MODE_BITSIZE (mode
)
4837 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4839 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4840 extend_op
= SIGN_EXTEND
;
4841 m
= GET_MODE (XEXP (t
, 0));
4843 else if (GET_CODE (t
) == SIGN_EXTEND
4844 && (GET_CODE (XEXP (t
, 0)) == PLUS
4845 || GET_CODE (XEXP (t
, 0)) == IOR
4846 || GET_CODE (XEXP (t
, 0)) == XOR
)
4847 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4848 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4849 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4850 && (num_sign_bit_copies (f
, GET_MODE (f
))
4852 (GET_MODE_BITSIZE (mode
)
4853 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4855 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4856 extend_op
= SIGN_EXTEND
;
4857 m
= GET_MODE (XEXP (t
, 0));
4859 else if (GET_CODE (t
) == ZERO_EXTEND
4860 && (GET_CODE (XEXP (t
, 0)) == PLUS
4861 || GET_CODE (XEXP (t
, 0)) == MINUS
4862 || GET_CODE (XEXP (t
, 0)) == IOR
4863 || GET_CODE (XEXP (t
, 0)) == XOR
4864 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4865 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4866 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4867 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4868 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4869 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4870 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4871 && ((nonzero_bits (f
, GET_MODE (f
))
4872 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4875 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4876 extend_op
= ZERO_EXTEND
;
4877 m
= GET_MODE (XEXP (t
, 0));
4879 else if (GET_CODE (t
) == ZERO_EXTEND
4880 && (GET_CODE (XEXP (t
, 0)) == PLUS
4881 || GET_CODE (XEXP (t
, 0)) == IOR
4882 || GET_CODE (XEXP (t
, 0)) == XOR
)
4883 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4884 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4885 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4886 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4887 && ((nonzero_bits (f
, GET_MODE (f
))
4888 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4891 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4892 extend_op
= ZERO_EXTEND
;
4893 m
= GET_MODE (XEXP (t
, 0));
4898 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4899 pc_rtx
, pc_rtx
, 0, 0);
4900 temp
= gen_binary (MULT
, m
, temp
,
4901 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4902 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4903 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4905 if (extend_op
!= NIL
)
4906 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
4912 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4913 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4914 negation of a single bit, we can convert this operation to a shift. We
4915 can actually do this more generally, but it doesn't seem worth it. */
4917 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4918 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4919 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4920 && (i
= exact_log2 (INTVAL (true_rtx
))) >= 0)
4921 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4922 == GET_MODE_BITSIZE (mode
))
4923 && (i
= exact_log2 (-INTVAL (true_rtx
))) >= 0)))
4925 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4926 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4928 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4929 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4930 && false_rtx
== const0_rtx
&& GET_CODE (true_rtx
) == CONST_INT
4931 && (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))
4932 == nonzero_bits (XEXP (cond
, 0), mode
)
4933 && (i
= exact_log2 (INTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
4934 return XEXP (cond
, 0);
4939 /* Simplify X, a SET expression. Return the new expression. */
4942 simplify_set (rtx x
)
4944 rtx src
= SET_SRC (x
);
4945 rtx dest
= SET_DEST (x
);
4946 enum machine_mode mode
4947 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4951 /* (set (pc) (return)) gets written as (return). */
4952 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4955 /* Now that we know for sure which bits of SRC we are using, see if we can
4956 simplify the expression for the object knowing that we only need the
4959 if (GET_MODE_CLASS (mode
) == MODE_INT
4960 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
4962 src
= force_to_mode (src
, mode
, ~(HOST_WIDE_INT
) 0, NULL_RTX
, 0);
4963 SUBST (SET_SRC (x
), src
);
4966 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4967 the comparison result and try to simplify it unless we already have used
4968 undobuf.other_insn. */
4969 if ((GET_MODE_CLASS (mode
) == MODE_CC
4970 || GET_CODE (src
) == COMPARE
4972 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4973 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4974 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4975 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4977 enum rtx_code old_code
= GET_CODE (*cc_use
);
4978 enum rtx_code new_code
;
4980 int other_changed
= 0;
4981 enum machine_mode compare_mode
= GET_MODE (dest
);
4982 enum machine_mode tmp_mode
;
4984 if (GET_CODE (src
) == COMPARE
)
4985 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4987 op0
= src
, op1
= const0_rtx
;
4989 /* Check whether the comparison is known at compile time. */
4990 if (GET_MODE (op0
) != VOIDmode
)
4991 tmp_mode
= GET_MODE (op0
);
4992 else if (GET_MODE (op1
) != VOIDmode
)
4993 tmp_mode
= GET_MODE (op1
);
4995 tmp_mode
= compare_mode
;
4996 tmp
= simplify_relational_operation (old_code
, tmp_mode
, op0
, op1
);
4997 if (tmp
!= NULL_RTX
)
4999 rtx pat
= PATTERN (other_insn
);
5000 undobuf
.other_insn
= other_insn
;
5001 SUBST (*cc_use
, tmp
);
5003 /* Attempt to simplify CC user. */
5004 if (GET_CODE (pat
) == SET
)
5006 rtx
new = simplify_rtx (SET_SRC (pat
));
5007 if (new != NULL_RTX
)
5008 SUBST (SET_SRC (pat
), new);
5011 /* Convert X into a no-op move. */
5012 SUBST (SET_DEST (x
), pc_rtx
);
5013 SUBST (SET_SRC (x
), pc_rtx
);
5017 /* Simplify our comparison, if possible. */
5018 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
5020 #ifdef SELECT_CC_MODE
5021 /* If this machine has CC modes other than CCmode, check to see if we
5022 need to use a different CC mode here. */
5023 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
5026 /* If the mode changed, we have to change SET_DEST, the mode in the
5027 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5028 a hard register, just build new versions with the proper mode. If it
5029 is a pseudo, we lose unless it is only time we set the pseudo, in
5030 which case we can safely change its mode. */
5031 if (compare_mode
!= GET_MODE (dest
))
5033 unsigned int regno
= REGNO (dest
);
5034 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
5036 if (regno
< FIRST_PSEUDO_REGISTER
5037 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
5039 if (regno
>= FIRST_PSEUDO_REGISTER
)
5040 SUBST (regno_reg_rtx
[regno
], new_dest
);
5042 SUBST (SET_DEST (x
), new_dest
);
5043 SUBST (XEXP (*cc_use
, 0), new_dest
);
5050 #endif /* SELECT_CC_MODE */
5052 /* If the code changed, we have to build a new comparison in
5053 undobuf.other_insn. */
5054 if (new_code
!= old_code
)
5056 int other_changed_previously
= other_changed
;
5057 unsigned HOST_WIDE_INT mask
;
5059 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
5063 /* If the only change we made was to change an EQ into an NE or
5064 vice versa, OP0 has only one bit that might be nonzero, and OP1
5065 is zero, check if changing the user of the condition code will
5066 produce a valid insn. If it won't, we can keep the original code
5067 in that insn by surrounding our operation with an XOR. */
5069 if (((old_code
== NE
&& new_code
== EQ
)
5070 || (old_code
== EQ
&& new_code
== NE
))
5071 && ! other_changed_previously
&& op1
== const0_rtx
5072 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
5073 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
5075 rtx pat
= PATTERN (other_insn
), note
= 0;
5077 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
5078 && ! check_asm_operands (pat
)))
5080 PUT_CODE (*cc_use
, old_code
);
5083 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
5089 undobuf
.other_insn
= other_insn
;
5092 /* If we are now comparing against zero, change our source if
5093 needed. If we do not use cc0, we always have a COMPARE. */
5094 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
5096 SUBST (SET_SRC (x
), op0
);
5102 /* Otherwise, if we didn't previously have a COMPARE in the
5103 correct mode, we need one. */
5104 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
5106 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
5111 /* Otherwise, update the COMPARE if needed. */
5112 SUBST (XEXP (src
, 0), op0
);
5113 SUBST (XEXP (src
, 1), op1
);
5118 /* Get SET_SRC in a form where we have placed back any
5119 compound expressions. Then do the checks below. */
5120 src
= make_compound_operation (src
, SET
);
5121 SUBST (SET_SRC (x
), src
);
5124 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5125 and X being a REG or (subreg (reg)), we may be able to convert this to
5126 (set (subreg:m2 x) (op)).
5128 We can always do this if M1 is narrower than M2 because that means that
5129 we only care about the low bits of the result.
5131 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5132 perform a narrower operation than requested since the high-order bits will
5133 be undefined. On machine where it is defined, this transformation is safe
5134 as long as M1 and M2 have the same number of words. */
5136 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5137 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
5138 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
5140 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
5141 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
5142 #ifndef WORD_REGISTER_OPERATIONS
5143 && (GET_MODE_SIZE (GET_MODE (src
))
5144 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5146 #ifdef CANNOT_CHANGE_MODE_CLASS
5147 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
5148 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
5149 GET_MODE (SUBREG_REG (src
)),
5152 && (GET_CODE (dest
) == REG
5153 || (GET_CODE (dest
) == SUBREG
5154 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
5156 SUBST (SET_DEST (x
),
5157 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
5159 SUBST (SET_SRC (x
), SUBREG_REG (src
));
5161 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5165 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5168 && GET_CODE (src
) == SUBREG
5169 && subreg_lowpart_p (src
)
5170 && (GET_MODE_BITSIZE (GET_MODE (src
))
5171 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src
)))))
5173 rtx inner
= SUBREG_REG (src
);
5174 enum machine_mode inner_mode
= GET_MODE (inner
);
5176 /* Here we make sure that we don't have a sign bit on. */
5177 if (GET_MODE_BITSIZE (inner_mode
) <= HOST_BITS_PER_WIDE_INT
5178 && (nonzero_bits (inner
, inner_mode
)
5179 < ((unsigned HOST_WIDE_INT
) 1
5180 << (GET_MODE_BITSIZE (GET_MODE (src
)) - 1))))
5182 SUBST (SET_SRC (x
), inner
);
5188 #ifdef LOAD_EXTEND_OP
5189 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5190 would require a paradoxical subreg. Replace the subreg with a
5191 zero_extend to avoid the reload that would otherwise be required. */
5193 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5194 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5195 && SUBREG_BYTE (src
) == 0
5196 && (GET_MODE_SIZE (GET_MODE (src
))
5197 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5198 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5201 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5202 GET_MODE (src
), SUBREG_REG (src
)));
5208 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5209 are comparing an item known to be 0 or -1 against 0, use a logical
5210 operation instead. Check for one of the arms being an IOR of the other
5211 arm with some value. We compute three terms to be IOR'ed together. In
5212 practice, at most two will be nonzero. Then we do the IOR's. */
5214 if (GET_CODE (dest
) != PC
5215 && GET_CODE (src
) == IF_THEN_ELSE
5216 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5217 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5218 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5219 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5220 #ifdef HAVE_conditional_move
5221 && ! can_conditionally_move_p (GET_MODE (src
))
5223 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5224 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5225 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5226 && ! side_effects_p (src
))
5228 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5229 ? XEXP (src
, 1) : XEXP (src
, 2));
5230 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
5231 ? XEXP (src
, 2) : XEXP (src
, 1));
5232 rtx term1
= const0_rtx
, term2
, term3
;
5234 if (GET_CODE (true_rtx
) == IOR
5235 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
5236 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
5237 else if (GET_CODE (true_rtx
) == IOR
5238 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
5239 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
5240 else if (GET_CODE (false_rtx
) == IOR
5241 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
5242 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
5243 else if (GET_CODE (false_rtx
) == IOR
5244 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
5245 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
5247 term2
= gen_binary (AND
, GET_MODE (src
),
5248 XEXP (XEXP (src
, 0), 0), true_rtx
);
5249 term3
= gen_binary (AND
, GET_MODE (src
),
5250 simplify_gen_unary (NOT
, GET_MODE (src
),
5251 XEXP (XEXP (src
, 0), 0),
5256 gen_binary (IOR
, GET_MODE (src
),
5257 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5263 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5264 whole thing fail. */
5265 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5267 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5270 /* Convert this into a field assignment operation, if possible. */
5271 return make_field_assignment (x
);
5274 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5275 result. LAST is nonzero if this is the last retry. */
5278 simplify_logical (rtx x
, int last
)
5280 enum machine_mode mode
= GET_MODE (x
);
5281 rtx op0
= XEXP (x
, 0);
5282 rtx op1
= XEXP (x
, 1);
5285 switch (GET_CODE (x
))
5288 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5289 insn (and may simplify more). */
5290 if (GET_CODE (op0
) == XOR
5291 && rtx_equal_p (XEXP (op0
, 0), op1
)
5292 && ! side_effects_p (op1
))
5293 x
= gen_binary (AND
, mode
,
5294 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5297 if (GET_CODE (op0
) == XOR
5298 && rtx_equal_p (XEXP (op0
, 1), op1
)
5299 && ! side_effects_p (op1
))
5300 x
= gen_binary (AND
, mode
,
5301 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5304 /* Similarly for (~(A ^ B)) & A. */
5305 if (GET_CODE (op0
) == NOT
5306 && GET_CODE (XEXP (op0
, 0)) == XOR
5307 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5308 && ! side_effects_p (op1
))
5309 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5311 if (GET_CODE (op0
) == NOT
5312 && GET_CODE (XEXP (op0
, 0)) == XOR
5313 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5314 && ! side_effects_p (op1
))
5315 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5317 /* We can call simplify_and_const_int only if we don't lose
5318 any (sign) bits when converting INTVAL (op1) to
5319 "unsigned HOST_WIDE_INT". */
5320 if (GET_CODE (op1
) == CONST_INT
5321 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5322 || INTVAL (op1
) > 0))
5324 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5326 /* If we have (ior (and (X C1) C2)) and the next restart would be
5327 the last, simplify this by making C1 as small as possible
5330 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5331 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5332 && GET_CODE (op1
) == CONST_INT
)
5333 return gen_binary (IOR
, mode
,
5334 gen_binary (AND
, mode
, XEXP (op0
, 0),
5335 GEN_INT (INTVAL (XEXP (op0
, 1))
5336 & ~INTVAL (op1
))), op1
);
5338 if (GET_CODE (x
) != AND
)
5341 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5342 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5343 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5346 /* Convert (A | B) & A to A. */
5347 if (GET_CODE (op0
) == IOR
5348 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5349 || rtx_equal_p (XEXP (op0
, 1), op1
))
5350 && ! side_effects_p (XEXP (op0
, 0))
5351 && ! side_effects_p (XEXP (op0
, 1)))
5354 /* In the following group of tests (and those in case IOR below),
5355 we start with some combination of logical operations and apply
5356 the distributive law followed by the inverse distributive law.
5357 Most of the time, this results in no change. However, if some of
5358 the operands are the same or inverses of each other, simplifications
5361 For example, (and (ior A B) (not B)) can occur as the result of
5362 expanding a bit field assignment. When we apply the distributive
5363 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5364 which then simplifies to (and (A (not B))).
5366 If we have (and (ior A B) C), apply the distributive law and then
5367 the inverse distributive law to see if things simplify. */
5369 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5371 x
= apply_distributive_law
5372 (gen_binary (GET_CODE (op0
), mode
,
5373 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5374 gen_binary (AND
, mode
, XEXP (op0
, 1),
5376 if (GET_CODE (x
) != AND
)
5380 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5381 return apply_distributive_law
5382 (gen_binary (GET_CODE (op1
), mode
,
5383 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5384 gen_binary (AND
, mode
, XEXP (op1
, 1),
5387 /* Similarly, taking advantage of the fact that
5388 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5390 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5391 return apply_distributive_law
5392 (gen_binary (XOR
, mode
,
5393 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5394 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5397 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5398 return apply_distributive_law
5399 (gen_binary (XOR
, mode
,
5400 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5401 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5405 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5406 if (GET_CODE (op1
) == CONST_INT
5407 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5408 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
5411 /* Convert (A & B) | A to A. */
5412 if (GET_CODE (op0
) == AND
5413 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5414 || rtx_equal_p (XEXP (op0
, 1), op1
))
5415 && ! side_effects_p (XEXP (op0
, 0))
5416 && ! side_effects_p (XEXP (op0
, 1)))
5419 /* If we have (ior (and A B) C), apply the distributive law and then
5420 the inverse distributive law to see if things simplify. */
5422 if (GET_CODE (op0
) == AND
)
5424 x
= apply_distributive_law
5425 (gen_binary (AND
, mode
,
5426 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5427 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5430 if (GET_CODE (x
) != IOR
)
5434 if (GET_CODE (op1
) == AND
)
5436 x
= apply_distributive_law
5437 (gen_binary (AND
, mode
,
5438 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5439 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5442 if (GET_CODE (x
) != IOR
)
5446 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5447 mode size to (rotate A CX). */
5449 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5450 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5451 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5452 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5453 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5454 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5455 == GET_MODE_BITSIZE (mode
)))
5456 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5457 (GET_CODE (op0
) == ASHIFT
5458 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5460 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5461 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5462 does not affect any of the bits in OP1, it can really be done
5463 as a PLUS and we can associate. We do this by seeing if OP1
5464 can be safely shifted left C bits. */
5465 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5466 && GET_CODE (XEXP (op0
, 0)) == PLUS
5467 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5468 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5469 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5471 int count
= INTVAL (XEXP (op0
, 1));
5472 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5474 if (mask
>> count
== INTVAL (op1
)
5475 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5477 SUBST (XEXP (XEXP (op0
, 0), 1),
5478 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5485 /* If we are XORing two things that have no bits in common,
5486 convert them into an IOR. This helps to detect rotation encoded
5487 using those methods and possibly other simplifications. */
5489 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5490 && (nonzero_bits (op0
, mode
)
5491 & nonzero_bits (op1
, mode
)) == 0)
5492 return (gen_binary (IOR
, mode
, op0
, op1
));
5494 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5495 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5498 int num_negated
= 0;
5500 if (GET_CODE (op0
) == NOT
)
5501 num_negated
++, op0
= XEXP (op0
, 0);
5502 if (GET_CODE (op1
) == NOT
)
5503 num_negated
++, op1
= XEXP (op1
, 0);
5505 if (num_negated
== 2)
5507 SUBST (XEXP (x
, 0), op0
);
5508 SUBST (XEXP (x
, 1), op1
);
5510 else if (num_negated
== 1)
5512 simplify_gen_unary (NOT
, mode
, gen_binary (XOR
, mode
, op0
, op1
),
5516 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5517 correspond to a machine insn or result in further simplifications
5518 if B is a constant. */
5520 if (GET_CODE (op0
) == AND
5521 && rtx_equal_p (XEXP (op0
, 1), op1
)
5522 && ! side_effects_p (op1
))
5523 return gen_binary (AND
, mode
,
5524 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 0), mode
),
5527 else if (GET_CODE (op0
) == AND
5528 && rtx_equal_p (XEXP (op0
, 0), op1
)
5529 && ! side_effects_p (op1
))
5530 return gen_binary (AND
, mode
,
5531 simplify_gen_unary (NOT
, mode
, XEXP (op0
, 1), mode
),
5534 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5535 comparison if STORE_FLAG_VALUE is 1. */
5536 if (STORE_FLAG_VALUE
== 1
5537 && op1
== const1_rtx
5538 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5539 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5543 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5544 is (lt foo (const_int 0)), so we can perform the above
5545 simplification if STORE_FLAG_VALUE is 1. */
5547 if (STORE_FLAG_VALUE
== 1
5548 && op1
== const1_rtx
5549 && GET_CODE (op0
) == LSHIFTRT
5550 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5551 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5552 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
5554 /* (xor (comparison foo bar) (const_int sign-bit))
5555 when STORE_FLAG_VALUE is the sign bit. */
5556 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5557 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5558 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5559 && op1
== const_true_rtx
5560 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5561 && (reversed
= reversed_comparison (op0
, mode
, XEXP (op0
, 0),
5574 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5575 operations" because they can be replaced with two more basic operations.
5576 ZERO_EXTEND is also considered "compound" because it can be replaced with
5577 an AND operation, which is simpler, though only one operation.
5579 The function expand_compound_operation is called with an rtx expression
5580 and will convert it to the appropriate shifts and AND operations,
5581 simplifying at each stage.
5583 The function make_compound_operation is called to convert an expression
5584 consisting of shifts and ANDs into the equivalent compound expression.
5585 It is the inverse of this function, loosely speaking. */
5588 expand_compound_operation (rtx x
)
5590 unsigned HOST_WIDE_INT pos
= 0, len
;
5592 unsigned int modewidth
;
5595 switch (GET_CODE (x
))
5600 /* We can't necessarily use a const_int for a multiword mode;
5601 it depends on implicitly extending the value.
5602 Since we don't know the right way to extend it,
5603 we can't tell whether the implicit way is right.
5605 Even for a mode that is no wider than a const_int,
5606 we can't win, because we need to sign extend one of its bits through
5607 the rest of it, and we don't know which bit. */
5608 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5611 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5612 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5613 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5614 reloaded. If not for that, MEM's would very rarely be safe.
5616 Reject MODEs bigger than a word, because we might not be able
5617 to reference a two-register group starting with an arbitrary register
5618 (and currently gen_lowpart might crash for a SUBREG). */
5620 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5623 /* Reject MODEs that aren't scalar integers because turning vector
5624 or complex modes into shifts causes problems. */
5626 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5629 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5630 /* If the inner object has VOIDmode (the only way this can happen
5631 is if it is an ASM_OPERANDS), we can't do anything since we don't
5632 know how much masking to do. */
5641 /* If the operand is a CLOBBER, just return it. */
5642 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5645 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5646 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5647 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5650 /* Reject MODEs that aren't scalar integers because turning vector
5651 or complex modes into shifts causes problems. */
5653 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
5656 len
= INTVAL (XEXP (x
, 1));
5657 pos
= INTVAL (XEXP (x
, 2));
5659 /* If this goes outside the object being extracted, replace the object
5660 with a (use (mem ...)) construct that only combine understands
5661 and is used only for this purpose. */
5662 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5663 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5665 if (BITS_BIG_ENDIAN
)
5666 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5673 /* Convert sign extension to zero extension, if we know that the high
5674 bit is not set, as this is easier to optimize. It will be converted
5675 back to cheaper alternative in make_extraction. */
5676 if (GET_CODE (x
) == SIGN_EXTEND
5677 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5678 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5679 & ~(((unsigned HOST_WIDE_INT
)
5680 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5684 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5685 rtx temp2
= expand_compound_operation (temp
);
5687 /* Make sure this is a profitable operation. */
5688 if (rtx_cost (x
, SET
) > rtx_cost (temp2
, SET
))
5690 else if (rtx_cost (x
, SET
) > rtx_cost (temp
, SET
))
5696 /* We can optimize some special cases of ZERO_EXTEND. */
5697 if (GET_CODE (x
) == ZERO_EXTEND
)
5699 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5700 know that the last value didn't have any inappropriate bits
5702 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5703 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5704 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5705 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5706 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5707 return XEXP (XEXP (x
, 0), 0);
5709 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5710 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5711 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5712 && subreg_lowpart_p (XEXP (x
, 0))
5713 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5714 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5715 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5716 return SUBREG_REG (XEXP (x
, 0));
5718 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5719 is a comparison and STORE_FLAG_VALUE permits. This is like
5720 the first case, but it works even when GET_MODE (x) is larger
5721 than HOST_WIDE_INT. */
5722 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5723 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5724 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5725 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5726 <= HOST_BITS_PER_WIDE_INT
)
5727 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5728 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5729 return XEXP (XEXP (x
, 0), 0);
5731 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5732 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5733 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5734 && subreg_lowpart_p (XEXP (x
, 0))
5735 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5736 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5737 <= HOST_BITS_PER_WIDE_INT
)
5738 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5739 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5740 return SUBREG_REG (XEXP (x
, 0));
5744 /* If we reach here, we want to return a pair of shifts. The inner
5745 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5746 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5747 logical depending on the value of UNSIGNEDP.
5749 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5750 converted into an AND of a shift.
5752 We must check for the case where the left shift would have a negative
5753 count. This can happen in a case like (x >> 31) & 255 on machines
5754 that can't shift by a constant. On those machines, we would first
5755 combine the shift with the AND to produce a variable-position
5756 extraction. Then the constant of 31 would be substituted in to produce
5757 a such a position. */
5759 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5760 if (modewidth
+ len
>= pos
)
5761 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5763 simplify_shift_const (NULL_RTX
, ASHIFT
,
5766 modewidth
- pos
- len
),
5769 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5770 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5771 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5774 ((HOST_WIDE_INT
) 1 << len
) - 1);
5776 /* Any other cases we can't handle. */
5779 /* If we couldn't do this for some reason, return the original
5781 if (GET_CODE (tem
) == CLOBBER
)
5787 /* X is a SET which contains an assignment of one object into
5788 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5789 or certain SUBREGS). If possible, convert it into a series of
5792 We half-heartedly support variable positions, but do not at all
5793 support variable lengths. */
5796 expand_field_assignment (rtx x
)
5799 rtx pos
; /* Always counts from low bit. */
5802 enum machine_mode compute_mode
;
5804 /* Loop until we find something we can't simplify. */
5807 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5808 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5810 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5811 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5812 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
5814 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5815 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5817 inner
= XEXP (SET_DEST (x
), 0);
5818 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5819 pos
= XEXP (SET_DEST (x
), 2);
5821 /* If the position is constant and spans the width of INNER,
5822 surround INNER with a USE to indicate this. */
5823 if (GET_CODE (pos
) == CONST_INT
5824 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5825 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5827 if (BITS_BIG_ENDIAN
)
5829 if (GET_CODE (pos
) == CONST_INT
)
5830 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5832 else if (GET_CODE (pos
) == MINUS
5833 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5834 && (INTVAL (XEXP (pos
, 1))
5835 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5836 /* If position is ADJUST - X, new position is X. */
5837 pos
= XEXP (pos
, 0);
5839 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5840 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5846 /* A SUBREG between two modes that occupy the same numbers of words
5847 can be done by moving the SUBREG to the source. */
5848 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5849 /* We need SUBREGs to compute nonzero_bits properly. */
5850 && nonzero_sign_valid
5851 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5852 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5853 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5854 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5856 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5857 gen_lowpart_for_combine
5858 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5865 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5866 inner
= SUBREG_REG (inner
);
5868 compute_mode
= GET_MODE (inner
);
5870 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5871 if (! SCALAR_INT_MODE_P (compute_mode
))
5873 enum machine_mode imode
;
5875 /* Don't do anything for vector or complex integral types. */
5876 if (! FLOAT_MODE_P (compute_mode
))
5879 /* Try to find an integral mode to pun with. */
5880 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5881 if (imode
== BLKmode
)
5884 compute_mode
= imode
;
5885 inner
= gen_lowpart_for_combine (imode
, inner
);
5888 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5889 if (len
< HOST_BITS_PER_WIDE_INT
)
5890 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5894 /* Now compute the equivalent expression. Make a copy of INNER
5895 for the SET_DEST in case it is a MEM into which we will substitute;
5896 we don't want shared RTL in that case. */
5898 (VOIDmode
, copy_rtx (inner
),
5899 gen_binary (IOR
, compute_mode
,
5900 gen_binary (AND
, compute_mode
,
5901 simplify_gen_unary (NOT
, compute_mode
,
5907 gen_binary (ASHIFT
, compute_mode
,
5908 gen_binary (AND
, compute_mode
,
5909 gen_lowpart_for_combine
5910 (compute_mode
, SET_SRC (x
)),
5918 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5919 it is an RTX that represents a variable starting position; otherwise,
5920 POS is the (constant) starting bit position (counted from the LSB).
5922 INNER may be a USE. This will occur when we started with a bitfield
5923 that went outside the boundary of the object in memory, which is
5924 allowed on most machines. To isolate this case, we produce a USE
5925 whose mode is wide enough and surround the MEM with it. The only
5926 code that understands the USE is this routine. If it is not removed,
5927 it will cause the resulting insn not to match.
5929 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5932 IN_DEST is nonzero if this is a reference in the destination of a
5933 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5934 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5937 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5938 ZERO_EXTRACT should be built even for bits starting at bit 0.
5940 MODE is the desired mode of the result (if IN_DEST == 0).
5942 The result is an RTX for the extraction or NULL_RTX if the target
5946 make_extraction (enum machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
5947 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
5948 int in_dest
, int in_compare
)
5950 /* This mode describes the size of the storage area
5951 to fetch the overall value from. Within that, we
5952 ignore the POS lowest bits, etc. */
5953 enum machine_mode is_mode
= GET_MODE (inner
);
5954 enum machine_mode inner_mode
;
5955 enum machine_mode wanted_inner_mode
= byte_mode
;
5956 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5957 enum machine_mode pos_mode
= word_mode
;
5958 enum machine_mode extraction_mode
= word_mode
;
5959 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5962 rtx orig_pos_rtx
= pos_rtx
;
5963 HOST_WIDE_INT orig_pos
;
5965 /* Get some information about INNER and get the innermost object. */
5966 if (GET_CODE (inner
) == USE
)
5967 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5968 /* We don't need to adjust the position because we set up the USE
5969 to pretend that it was a full-word object. */
5970 spans_byte
= 1, inner
= XEXP (inner
, 0);
5971 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5973 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5974 consider just the QI as the memory to extract from.
5975 The subreg adds or removes high bits; its mode is
5976 irrelevant to the meaning of this extraction,
5977 since POS and LEN count from the lsb. */
5978 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5979 is_mode
= GET_MODE (SUBREG_REG (inner
));
5980 inner
= SUBREG_REG (inner
);
5982 else if (GET_CODE (inner
) == ASHIFT
5983 && GET_CODE (XEXP (inner
, 1)) == CONST_INT
5984 && pos_rtx
== 0 && pos
== 0
5985 && len
> (unsigned HOST_WIDE_INT
) INTVAL (XEXP (inner
, 1)))
5987 /* We're extracting the least significant bits of an rtx
5988 (ashift X (const_int C)), where LEN > C. Extract the
5989 least significant (LEN - C) bits of X, giving an rtx
5990 whose mode is MODE, then shift it left C times. */
5991 new = make_extraction (mode
, XEXP (inner
, 0),
5992 0, 0, len
- INTVAL (XEXP (inner
, 1)),
5993 unsignedp
, in_dest
, in_compare
);
5995 return gen_rtx_ASHIFT (mode
, new, XEXP (inner
, 1));
5998 inner_mode
= GET_MODE (inner
);
6000 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
6001 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
6003 /* See if this can be done without an extraction. We never can if the
6004 width of the field is not the same as that of some integer mode. For
6005 registers, we can only avoid the extraction if the position is at the
6006 low-order bit and this is either not in the destination or we have the
6007 appropriate STRICT_LOW_PART operation available.
6009 For MEM, we can avoid an extract if the field starts on an appropriate
6010 boundary and we can change the mode of the memory reference. However,
6011 we cannot directly access the MEM if we have a USE and the underlying
6012 MEM is not TMODE. This combination means that MEM was being used in a
6013 context where bits outside its mode were being referenced; that is only
6014 valid in bit-field insns. */
6016 if (tmode
!= BLKmode
6017 && ! (spans_byte
&& inner_mode
!= tmode
)
6018 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
6019 && GET_CODE (inner
) != MEM
6021 || (GET_CODE (inner
) == REG
6022 && have_insn_for (STRICT_LOW_PART
, tmode
))))
6023 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
6025 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
6026 : BITS_PER_UNIT
)) == 0
6027 /* We can't do this if we are widening INNER_MODE (it
6028 may not be aligned, for one thing). */
6029 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
6030 && (inner_mode
== tmode
6031 || (! mode_dependent_address_p (XEXP (inner
, 0))
6032 && ! MEM_VOLATILE_P (inner
))))))
6034 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6035 field. If the original and current mode are the same, we need not
6036 adjust the offset. Otherwise, we do if bytes big endian.
6038 If INNER is not a MEM, get a piece consisting of just the field
6039 of interest (in this case POS % BITS_PER_WORD must be 0). */
6041 if (GET_CODE (inner
) == MEM
)
6043 HOST_WIDE_INT offset
;
6045 /* POS counts from lsb, but make OFFSET count in memory order. */
6046 if (BYTES_BIG_ENDIAN
)
6047 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
6049 offset
= pos
/ BITS_PER_UNIT
;
6051 new = adjust_address_nv (inner
, tmode
, offset
);
6053 else if (GET_CODE (inner
) == REG
)
6055 if (tmode
!= inner_mode
)
6057 /* We can't call gen_lowpart_for_combine in a DEST since we
6058 always want a SUBREG (see below) and it would sometimes
6059 return a new hard register. */
6062 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
6064 if (WORDS_BIG_ENDIAN
6065 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
6066 final_word
= ((GET_MODE_SIZE (inner_mode
)
6067 - GET_MODE_SIZE (tmode
))
6068 / UNITS_PER_WORD
) - final_word
;
6070 final_word
*= UNITS_PER_WORD
;
6071 if (BYTES_BIG_ENDIAN
&&
6072 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
6073 final_word
+= (GET_MODE_SIZE (inner_mode
)
6074 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
6076 /* Avoid creating invalid subregs, for example when
6077 simplifying (x>>32)&255. */
6078 if (final_word
>= GET_MODE_SIZE (inner_mode
))
6081 new = gen_rtx_SUBREG (tmode
, inner
, final_word
);
6084 new = gen_lowpart_for_combine (tmode
, inner
);
6090 new = force_to_mode (inner
, tmode
,
6091 len
>= HOST_BITS_PER_WIDE_INT
6092 ? ~(unsigned HOST_WIDE_INT
) 0
6093 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
6096 /* If this extraction is going into the destination of a SET,
6097 make a STRICT_LOW_PART unless we made a MEM. */
6100 return (GET_CODE (new) == MEM
? new
6101 : (GET_CODE (new) != SUBREG
6102 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
6103 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new)));
6108 if (GET_CODE (new) == CONST_INT
)
6109 return gen_int_mode (INTVAL (new), mode
);
6111 /* If we know that no extraneous bits are set, and that the high
6112 bit is not set, convert the extraction to the cheaper of
6113 sign and zero extension, that are equivalent in these cases. */
6114 if (flag_expensive_optimizations
6115 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
6116 && ((nonzero_bits (new, tmode
)
6117 & ~(((unsigned HOST_WIDE_INT
)
6118 GET_MODE_MASK (tmode
))
6122 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
6123 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
6125 /* Prefer ZERO_EXTENSION, since it gives more information to
6127 if (rtx_cost (temp
, SET
) <= rtx_cost (temp1
, SET
))
6132 /* Otherwise, sign- or zero-extend unless we already are in the
6135 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
6139 /* Unless this is a COMPARE or we have a funny memory reference,
6140 don't do anything with zero-extending field extracts starting at
6141 the low-order bit since they are simple AND operations. */
6142 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
6143 && ! in_compare
&& ! spans_byte
&& unsignedp
)
6146 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6147 we would be spanning bytes or if the position is not a constant and the
6148 length is not 1. In all other cases, we would only be going outside
6149 our object in cases when an original shift would have been
6151 if (! spans_byte
&& GET_CODE (inner
) == MEM
6152 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
6153 || (pos_rtx
!= 0 && len
!= 1)))
6156 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6157 and the mode for the result. */
6158 if (in_dest
&& mode_for_extraction (EP_insv
, -1) != MAX_MACHINE_MODE
)
6160 wanted_inner_reg_mode
= mode_for_extraction (EP_insv
, 0);
6161 pos_mode
= mode_for_extraction (EP_insv
, 2);
6162 extraction_mode
= mode_for_extraction (EP_insv
, 3);
6165 if (! in_dest
&& unsignedp
6166 && mode_for_extraction (EP_extzv
, -1) != MAX_MACHINE_MODE
)
6168 wanted_inner_reg_mode
= mode_for_extraction (EP_extzv
, 1);
6169 pos_mode
= mode_for_extraction (EP_extzv
, 3);
6170 extraction_mode
= mode_for_extraction (EP_extzv
, 0);
6173 if (! in_dest
&& ! unsignedp
6174 && mode_for_extraction (EP_extv
, -1) != MAX_MACHINE_MODE
)
6176 wanted_inner_reg_mode
= mode_for_extraction (EP_extv
, 1);
6177 pos_mode
= mode_for_extraction (EP_extv
, 3);
6178 extraction_mode
= mode_for_extraction (EP_extv
, 0);
6181 /* Never narrow an object, since that might not be safe. */
6183 if (mode
!= VOIDmode
6184 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6185 extraction_mode
= mode
;
6187 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6188 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6189 pos_mode
= GET_MODE (pos_rtx
);
6191 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6192 if we have to change the mode of memory and cannot, the desired mode is
6194 if (GET_CODE (inner
) != MEM
)
6195 wanted_inner_mode
= wanted_inner_reg_mode
;
6196 else if (inner_mode
!= wanted_inner_mode
6197 && (mode_dependent_address_p (XEXP (inner
, 0))
6198 || MEM_VOLATILE_P (inner
)))
6199 wanted_inner_mode
= extraction_mode
;
6203 if (BITS_BIG_ENDIAN
)
6205 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6206 BITS_BIG_ENDIAN style. If position is constant, compute new
6207 position. Otherwise, build subtraction.
6208 Note that POS is relative to the mode of the original argument.
6209 If it's a MEM we need to recompute POS relative to that.
6210 However, if we're extracting from (or inserting into) a register,
6211 we want to recompute POS relative to wanted_inner_mode. */
6212 int width
= (GET_CODE (inner
) == MEM
6213 ? GET_MODE_BITSIZE (is_mode
)
6214 : GET_MODE_BITSIZE (wanted_inner_mode
));
6217 pos
= width
- len
- pos
;
6220 = gen_rtx_MINUS (GET_MODE (pos_rtx
), GEN_INT (width
- len
), pos_rtx
);
6221 /* POS may be less than 0 now, but we check for that below.
6222 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6225 /* If INNER has a wider mode, make it smaller. If this is a constant
6226 extract, try to adjust the byte to point to the byte containing
6228 if (wanted_inner_mode
!= VOIDmode
6229 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6230 && ((GET_CODE (inner
) == MEM
6231 && (inner_mode
== wanted_inner_mode
6232 || (! mode_dependent_address_p (XEXP (inner
, 0))
6233 && ! MEM_VOLATILE_P (inner
))))))
6237 /* The computations below will be correct if the machine is big
6238 endian in both bits and bytes or little endian in bits and bytes.
6239 If it is mixed, we must adjust. */
6241 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6242 adjust OFFSET to compensate. */
6243 if (BYTES_BIG_ENDIAN
6245 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6246 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6248 /* If this is a constant position, we can move to the desired byte. */
6251 offset
+= pos
/ BITS_PER_UNIT
;
6252 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6255 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6257 && is_mode
!= wanted_inner_mode
)
6258 offset
= (GET_MODE_SIZE (is_mode
)
6259 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6261 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6262 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
6265 /* If INNER is not memory, we can always get it into the proper mode. If we
6266 are changing its mode, POS must be a constant and smaller than the size
6268 else if (GET_CODE (inner
) != MEM
)
6270 if (GET_MODE (inner
) != wanted_inner_mode
6272 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6275 inner
= force_to_mode (inner
, wanted_inner_mode
,
6277 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6278 ? ~(unsigned HOST_WIDE_INT
) 0
6279 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6284 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6285 have to zero extend. Otherwise, we can just use a SUBREG. */
6287 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6289 rtx temp
= gen_rtx_ZERO_EXTEND (pos_mode
, pos_rtx
);
6291 /* If we know that no extraneous bits are set, and that the high
6292 bit is not set, convert extraction to cheaper one - either
6293 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6295 if (flag_expensive_optimizations
6296 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6297 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6298 & ~(((unsigned HOST_WIDE_INT
)
6299 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6303 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6305 /* Prefer ZERO_EXTENSION, since it gives more information to
6307 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6312 else if (pos_rtx
!= 0
6313 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6314 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6316 /* Make POS_RTX unless we already have it and it is correct. If we don't
6317 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6319 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6320 pos_rtx
= orig_pos_rtx
;
6322 else if (pos_rtx
== 0)
6323 pos_rtx
= GEN_INT (pos
);
6325 /* Make the required operation. See if we can use existing rtx. */
6326 new = gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6327 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6329 new = gen_lowpart_for_combine (mode
, new);
6334 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6335 with any other operations in X. Return X without that shift if so. */
6338 extract_left_shift (rtx x
, int count
)
6340 enum rtx_code code
= GET_CODE (x
);
6341 enum machine_mode mode
= GET_MODE (x
);
6347 /* This is the shift itself. If it is wide enough, we will return
6348 either the value being shifted if the shift count is equal to
6349 COUNT or a shift for the difference. */
6350 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6351 && INTVAL (XEXP (x
, 1)) >= count
)
6352 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6353 INTVAL (XEXP (x
, 1)) - count
);
6357 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6358 return simplify_gen_unary (code
, mode
, tem
, mode
);
6362 case PLUS
: case IOR
: case XOR
: case AND
:
6363 /* If we can safely shift this constant and we find the inner shift,
6364 make a new operation. */
6365 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6366 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6367 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6368 return gen_binary (code
, mode
, tem
,
6369 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6380 /* Look at the expression rooted at X. Look for expressions
6381 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6382 Form these expressions.
6384 Return the new rtx, usually just X.
6386 Also, for machines like the VAX that don't have logical shift insns,
6387 try to convert logical to arithmetic shift operations in cases where
6388 they are equivalent. This undoes the canonicalizations to logical
6389 shifts done elsewhere.
6391 We try, as much as possible, to re-use rtl expressions to save memory.
6393 IN_CODE says what kind of expression we are processing. Normally, it is
6394 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6395 being kludges), it is MEM. When processing the arguments of a comparison
6396 or a COMPARE against zero, it is COMPARE. */
6399 make_compound_operation (rtx x
, enum rtx_code in_code
)
6401 enum rtx_code code
= GET_CODE (x
);
6402 enum machine_mode mode
= GET_MODE (x
);
6403 int mode_width
= GET_MODE_BITSIZE (mode
);
6405 enum rtx_code next_code
;
6411 /* Select the code to be used in recursive calls. Once we are inside an
6412 address, we stay there. If we have a comparison, set to COMPARE,
6413 but once inside, go back to our default of SET. */
6415 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6416 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6417 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6418 : in_code
== COMPARE
? SET
: in_code
);
6420 /* Process depending on the code of this operation. If NEW is set
6421 nonzero, it will be returned. */
6426 /* Convert shifts by constants into multiplications if inside
6428 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6429 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6430 && INTVAL (XEXP (x
, 1)) >= 0)
6432 new = make_compound_operation (XEXP (x
, 0), next_code
);
6433 new = gen_rtx_MULT (mode
, new,
6434 GEN_INT ((HOST_WIDE_INT
) 1
6435 << INTVAL (XEXP (x
, 1))));
6440 /* If the second operand is not a constant, we can't do anything
6442 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6445 /* If the constant is a power of two minus one and the first operand
6446 is a logical right shift, make an extraction. */
6447 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6448 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6450 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6451 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6452 0, in_code
== COMPARE
);
6455 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6456 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6457 && subreg_lowpart_p (XEXP (x
, 0))
6458 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6459 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6461 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6463 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6464 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6465 0, in_code
== COMPARE
);
6467 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6468 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6469 || GET_CODE (XEXP (x
, 0)) == IOR
)
6470 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6471 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6472 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6474 /* Apply the distributive law, and then try to make extractions. */
6475 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
6476 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6478 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6480 new = make_compound_operation (new, in_code
);
6483 /* If we are have (and (rotate X C) M) and C is larger than the number
6484 of bits in M, this is an extraction. */
6486 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6487 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6488 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6489 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6491 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6492 new = make_extraction (mode
, new,
6493 (GET_MODE_BITSIZE (mode
)
6494 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6495 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6498 /* On machines without logical shifts, if the operand of the AND is
6499 a logical shift and our mask turns off all the propagated sign
6500 bits, we can replace the logical shift with an arithmetic shift. */
6501 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6502 && !have_insn_for (LSHIFTRT
, mode
)
6503 && have_insn_for (ASHIFTRT
, mode
)
6504 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6505 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6506 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6507 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6509 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6511 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6512 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6514 gen_rtx_ASHIFTRT (mode
,
6515 make_compound_operation
6516 (XEXP (XEXP (x
, 0), 0), next_code
),
6517 XEXP (XEXP (x
, 0), 1)));
6520 /* If the constant is one less than a power of two, this might be
6521 representable by an extraction even if no shift is present.
6522 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6523 we are in a COMPARE. */
6524 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6525 new = make_extraction (mode
,
6526 make_compound_operation (XEXP (x
, 0),
6528 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6530 /* If we are in a comparison and this is an AND with a power of two,
6531 convert this into the appropriate bit extract. */
6532 else if (in_code
== COMPARE
6533 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6534 new = make_extraction (mode
,
6535 make_compound_operation (XEXP (x
, 0),
6537 i
, NULL_RTX
, 1, 1, 0, 1);
6542 /* If the sign bit is known to be zero, replace this with an
6543 arithmetic shift. */
6544 if (have_insn_for (ASHIFTRT
, mode
)
6545 && ! have_insn_for (LSHIFTRT
, mode
)
6546 && mode_width
<= HOST_BITS_PER_WIDE_INT
6547 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6549 new = gen_rtx_ASHIFTRT (mode
,
6550 make_compound_operation (XEXP (x
, 0),
6556 /* ... fall through ... */
6562 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6563 this is a SIGN_EXTRACT. */
6564 if (GET_CODE (rhs
) == CONST_INT
6565 && GET_CODE (lhs
) == ASHIFT
6566 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6567 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6569 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6570 new = make_extraction (mode
, new,
6571 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6572 NULL_RTX
, mode_width
- INTVAL (rhs
),
6573 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6577 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6578 If so, try to merge the shifts into a SIGN_EXTEND. We could
6579 also do this for some cases of SIGN_EXTRACT, but it doesn't
6580 seem worth the effort; the case checked for occurs on Alpha. */
6582 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6583 && ! (GET_CODE (lhs
) == SUBREG
6584 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6585 && GET_CODE (rhs
) == CONST_INT
6586 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6587 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6588 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6589 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6590 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6595 /* Call ourselves recursively on the inner expression. If we are
6596 narrowing the object and it has a different RTL code from
6597 what it originally did, do this SUBREG as a force_to_mode. */
6599 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6600 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6601 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6602 && subreg_lowpart_p (x
))
6604 rtx newer
= force_to_mode (tem
, mode
, ~(HOST_WIDE_INT
) 0,
6607 /* If we have something other than a SUBREG, we might have
6608 done an expansion, so rerun ourselves. */
6609 if (GET_CODE (newer
) != SUBREG
)
6610 newer
= make_compound_operation (newer
, in_code
);
6615 /* If this is a paradoxical subreg, and the new code is a sign or
6616 zero extension, omit the subreg and widen the extension. If it
6617 is a regular subreg, we can still get rid of the subreg by not
6618 widening so much, or in fact removing the extension entirely. */
6619 if ((GET_CODE (tem
) == SIGN_EXTEND
6620 || GET_CODE (tem
) == ZERO_EXTEND
)
6621 && subreg_lowpart_p (x
))
6623 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6624 || (GET_MODE_SIZE (mode
) >
6625 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6627 if (! SCALAR_INT_MODE_P (mode
))
6629 tem
= gen_rtx_fmt_e (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6632 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6643 x
= gen_lowpart_for_combine (mode
, new);
6644 code
= GET_CODE (x
);
6647 /* Now recursively process each operand of this operation. */
6648 fmt
= GET_RTX_FORMAT (code
);
6649 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6652 new = make_compound_operation (XEXP (x
, i
), next_code
);
6653 SUBST (XEXP (x
, i
), new);
6659 /* Given M see if it is a value that would select a field of bits
6660 within an item, but not the entire word. Return -1 if not.
6661 Otherwise, return the starting position of the field, where 0 is the
6664 *PLEN is set to the length of the field. */
6667 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
6669 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6670 int pos
= exact_log2 (m
& -m
);
6676 /* Now shift off the low-order zero bits and see if we have a power of
6678 len
= exact_log2 ((m
>> pos
) + 1);
6687 /* See if X can be simplified knowing that we will only refer to it in
6688 MODE and will only refer to those bits that are nonzero in MASK.
6689 If other bits are being computed or if masking operations are done
6690 that select a superset of the bits in MASK, they can sometimes be
6693 Return a possibly simplified expression, but always convert X to
6694 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6696 Also, if REG is nonzero and X is a register equal in value to REG,
6699 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6700 are all off in X. This is used when X will be complemented, by either
6701 NOT, NEG, or XOR. */
6704 force_to_mode (rtx x
, enum machine_mode mode
, unsigned HOST_WIDE_INT mask
,
6705 rtx reg
, int just_select
)
6707 enum rtx_code code
= GET_CODE (x
);
6708 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6709 enum machine_mode op_mode
;
6710 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6713 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6714 code below will do the wrong thing since the mode of such an
6715 expression is VOIDmode.
6717 Also do nothing if X is a CLOBBER; this can happen if X was
6718 the return value from a call to gen_lowpart_for_combine. */
6719 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6722 /* We want to perform the operation is its present mode unless we know
6723 that the operation is valid in MODE, in which case we do the operation
6725 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6726 && have_insn_for (code
, mode
))
6727 ? mode
: GET_MODE (x
));
6729 /* It is not valid to do a right-shift in a narrower mode
6730 than the one it came in with. */
6731 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6732 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6733 op_mode
= GET_MODE (x
);
6735 /* Truncate MASK to fit OP_MODE. */
6737 mask
&= GET_MODE_MASK (op_mode
);
6739 /* When we have an arithmetic operation, or a shift whose count we
6740 do not know, we need to assume that all bits up to the highest-order
6741 bit in MASK will be needed. This is how we form such a mask. */
6742 if (mask
& ((unsigned HOST_WIDE_INT
) 1 << (HOST_BITS_PER_WIDE_INT
- 1)))
6743 fuller_mask
= ~(unsigned HOST_WIDE_INT
) 0;
6745 fuller_mask
= (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6748 /* Determine what bits of X are guaranteed to be (non)zero. */
6749 nonzero
= nonzero_bits (x
, mode
);
6751 /* If none of the bits in X are needed, return a zero. */
6752 if (! just_select
&& (nonzero
& mask
) == 0)
6755 /* If X is a CONST_INT, return a new one. Do this here since the
6756 test below will fail. */
6757 if (GET_CODE (x
) == CONST_INT
)
6759 if (SCALAR_INT_MODE_P (mode
))
6760 return gen_int_mode (INTVAL (x
) & mask
, mode
);
6763 x
= GEN_INT (INTVAL (x
) & mask
);
6764 return gen_lowpart_common (mode
, x
);
6768 /* If X is narrower than MODE and we want all the bits in X's mode, just
6769 get X in the proper mode. */
6770 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6771 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
6772 return gen_lowpart_for_combine (mode
, x
);
6774 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6775 MASK are already known to be zero in X, we need not do anything. */
6776 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~mask
& nonzero
) == 0)
6782 /* If X is a (clobber (const_int)), return it since we know we are
6783 generating something that won't match. */
6787 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6788 spanned the boundary of the MEM. If we are now masking so it is
6789 within that boundary, we don't need the USE any more. */
6790 if (! BITS_BIG_ENDIAN
6791 && (mask
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6792 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6799 x
= expand_compound_operation (x
);
6800 if (GET_CODE (x
) != code
)
6801 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6805 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6806 || rtx_equal_p (reg
, get_last_value (x
))))
6811 if (subreg_lowpart_p (x
)
6812 /* We can ignore the effect of this SUBREG if it narrows the mode or
6813 if the constant masks to zero all the bits the mode doesn't
6815 && ((GET_MODE_SIZE (GET_MODE (x
))
6816 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6818 & GET_MODE_MASK (GET_MODE (x
))
6819 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6820 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6824 /* If this is an AND with a constant, convert it into an AND
6825 whose constant is the AND of that constant with MASK. If it
6826 remains an AND of MASK, delete it since it is redundant. */
6828 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6830 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6831 mask
& INTVAL (XEXP (x
, 1)));
6833 /* If X is still an AND, see if it is an AND with a mask that
6834 is just some low-order bits. If so, and it is MASK, we don't
6837 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6838 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
6842 /* If it remains an AND, try making another AND with the bits
6843 in the mode mask that aren't in MASK turned on. If the
6844 constant in the AND is wide enough, this might make a
6845 cheaper constant. */
6847 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6848 && GET_MODE_MASK (GET_MODE (x
)) != mask
6849 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6851 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6852 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
));
6853 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6856 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6857 number, sign extend it. */
6858 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6859 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6860 cval
|= (HOST_WIDE_INT
) -1 << width
;
6862 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6863 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6873 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6874 low-order bits (as in an alignment operation) and FOO is already
6875 aligned to that boundary, mask C1 to that boundary as well.
6876 This may eliminate that PLUS and, later, the AND. */
6879 unsigned int width
= GET_MODE_BITSIZE (mode
);
6880 unsigned HOST_WIDE_INT smask
= mask
;
6882 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6883 number, sign extend it. */
6885 if (width
< HOST_BITS_PER_WIDE_INT
6886 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6887 smask
|= (HOST_WIDE_INT
) -1 << width
;
6889 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6890 && exact_log2 (- smask
) >= 0
6891 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
6892 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
6893 return force_to_mode (plus_constant (XEXP (x
, 0),
6894 (INTVAL (XEXP (x
, 1)) & smask
)),
6895 mode
, smask
, reg
, next_select
);
6898 /* ... fall through ... */
6901 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6902 most significant bit in MASK since carries from those bits will
6903 affect the bits we are interested in. */
6908 /* If X is (minus C Y) where C's least set bit is larger than any bit
6909 in the mask, then we may replace with (neg Y). */
6910 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6911 && (((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 0))
6912 & -INTVAL (XEXP (x
, 0))))
6915 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
6917 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6920 /* Similarly, if C contains every bit in the fuller_mask, then we may
6921 replace with (not Y). */
6922 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
6923 && ((INTVAL (XEXP (x
, 0)) | (HOST_WIDE_INT
) fuller_mask
)
6924 == INTVAL (XEXP (x
, 0))))
6926 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
6927 XEXP (x
, 1), GET_MODE (x
));
6928 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6936 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6937 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6938 operation which may be a bitfield extraction. Ensure that the
6939 constant we form is not wider than the mode of X. */
6941 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6942 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6943 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6944 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6945 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6946 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6947 + floor_log2 (INTVAL (XEXP (x
, 1))))
6948 < GET_MODE_BITSIZE (GET_MODE (x
)))
6949 && (INTVAL (XEXP (x
, 1))
6950 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6952 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6953 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6954 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6955 XEXP (XEXP (x
, 0), 0), temp
);
6956 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6957 XEXP (XEXP (x
, 0), 1));
6958 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6962 /* For most binary operations, just propagate into the operation and
6963 change the mode if we have an operation of that mode. */
6965 op0
= gen_lowpart_for_combine (op_mode
,
6966 force_to_mode (XEXP (x
, 0), mode
, mask
,
6968 op1
= gen_lowpart_for_combine (op_mode
,
6969 force_to_mode (XEXP (x
, 1), mode
, mask
,
6972 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6973 x
= gen_binary (code
, op_mode
, op0
, op1
);
6977 /* For left shifts, do the same, but just for the first operand.
6978 However, we cannot do anything with shifts where we cannot
6979 guarantee that the counts are smaller than the size of the mode
6980 because such a count will have a different meaning in a
6983 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6984 && INTVAL (XEXP (x
, 1)) >= 0
6985 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6986 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6987 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6988 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6991 /* If the shift count is a constant and we can do arithmetic in
6992 the mode of the shift, refine which bits we need. Otherwise, use the
6993 conservative form of the mask. */
6994 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6995 && INTVAL (XEXP (x
, 1)) >= 0
6996 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6997 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6998 mask
>>= INTVAL (XEXP (x
, 1));
7002 op0
= gen_lowpart_for_combine (op_mode
,
7003 force_to_mode (XEXP (x
, 0), op_mode
,
7004 mask
, reg
, next_select
));
7006 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7007 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
7011 /* Here we can only do something if the shift count is a constant,
7012 this shift constant is valid for the host, and we can do arithmetic
7015 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7016 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7017 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
7019 rtx inner
= XEXP (x
, 0);
7020 unsigned HOST_WIDE_INT inner_mask
;
7022 /* Select the mask of the bits we need for the shift operand. */
7023 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
7025 /* We can only change the mode of the shift if we can do arithmetic
7026 in the mode of the shift and INNER_MASK is no wider than the
7027 width of OP_MODE. */
7028 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
7029 || (inner_mask
& ~GET_MODE_MASK (op_mode
)) != 0)
7030 op_mode
= GET_MODE (x
);
7032 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
7034 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
7035 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
7038 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7039 shift and AND produces only copies of the sign bit (C2 is one less
7040 than a power of two), we can do this with just a shift. */
7042 if (GET_CODE (x
) == LSHIFTRT
7043 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7044 /* The shift puts one of the sign bit copies in the least significant
7046 && ((INTVAL (XEXP (x
, 1))
7047 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
7048 >= GET_MODE_BITSIZE (GET_MODE (x
)))
7049 && exact_log2 (mask
+ 1) >= 0
7050 /* Number of bits left after the shift must be more than the mask
7052 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
7053 <= GET_MODE_BITSIZE (GET_MODE (x
)))
7054 /* Must be more sign bit copies than the mask needs. */
7055 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7056 >= exact_log2 (mask
+ 1)))
7057 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7058 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
7059 - exact_log2 (mask
+ 1)));
7064 /* If we are just looking for the sign bit, we don't need this shift at
7065 all, even if it has a variable count. */
7066 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7067 && (mask
== ((unsigned HOST_WIDE_INT
) 1
7068 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7069 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7071 /* If this is a shift by a constant, get a mask that contains those bits
7072 that are not copies of the sign bit. We then have two cases: If
7073 MASK only includes those bits, this can be a logical shift, which may
7074 allow simplifications. If MASK is a single-bit field not within
7075 those bits, we are requesting a copy of the sign bit and hence can
7076 shift the sign bit to the appropriate location. */
7078 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
7079 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
7083 /* If the considered data is wider than HOST_WIDE_INT, we can't
7084 represent a mask for all its bits in a single scalar.
7085 But we only care about the lower bits, so calculate these. */
7087 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
7089 nonzero
= ~(HOST_WIDE_INT
) 0;
7091 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7092 is the number of bits a full-width mask would have set.
7093 We need only shift if these are fewer than nonzero can
7094 hold. If not, we must keep all bits set in nonzero. */
7096 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
7097 < HOST_BITS_PER_WIDE_INT
)
7098 nonzero
>>= INTVAL (XEXP (x
, 1))
7099 + HOST_BITS_PER_WIDE_INT
7100 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
7104 nonzero
= GET_MODE_MASK (GET_MODE (x
));
7105 nonzero
>>= INTVAL (XEXP (x
, 1));
7108 if ((mask
& ~nonzero
) == 0
7109 || (i
= exact_log2 (mask
)) >= 0)
7111 x
= simplify_shift_const
7112 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
7113 i
< 0 ? INTVAL (XEXP (x
, 1))
7114 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
7116 if (GET_CODE (x
) != ASHIFTRT
)
7117 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7121 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7122 even if the shift count isn't a constant. */
7124 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
7128 /* If this is a zero- or sign-extension operation that just affects bits
7129 we don't care about, remove it. Be sure the call above returned
7130 something that is still a shift. */
7132 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7133 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7134 && INTVAL (XEXP (x
, 1)) >= 0
7135 && (INTVAL (XEXP (x
, 1))
7136 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7137 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7138 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
7139 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7146 /* If the shift count is constant and we can do computations
7147 in the mode of X, compute where the bits we care about are.
7148 Otherwise, we can't do anything. Don't change the mode of
7149 the shift or propagate MODE into the shift, though. */
7150 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7151 && INTVAL (XEXP (x
, 1)) >= 0)
7153 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7154 GET_MODE (x
), GEN_INT (mask
),
7156 if (temp
&& GET_CODE (temp
) == CONST_INT
)
7158 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7159 INTVAL (temp
), reg
, next_select
));
7164 /* If we just want the low-order bit, the NEG isn't needed since it
7165 won't change the low-order bit. */
7167 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7169 /* We need any bits less significant than the most significant bit in
7170 MASK since carries from those bits will affect the bits we are
7176 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7177 same as the XOR case above. Ensure that the constant we form is not
7178 wider than the mode of X. */
7180 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7181 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7182 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7183 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7184 < GET_MODE_BITSIZE (GET_MODE (x
)))
7185 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7187 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
7189 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7190 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7192 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7195 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7196 use the full mask inside the NOT. */
7200 op0
= gen_lowpart_for_combine (op_mode
,
7201 force_to_mode (XEXP (x
, 0), mode
, mask
,
7203 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7204 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
7208 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7209 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7210 which is equal to STORE_FLAG_VALUE. */
7211 if ((mask
& ~STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7212 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7213 && (nonzero_bits (XEXP (x
, 0), mode
)
7214 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
7215 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7220 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7221 written in a narrower mode. We play it safe and do not do so. */
7224 gen_lowpart_for_combine (GET_MODE (x
),
7225 force_to_mode (XEXP (x
, 1), mode
,
7226 mask
, reg
, next_select
)));
7228 gen_lowpart_for_combine (GET_MODE (x
),
7229 force_to_mode (XEXP (x
, 2), mode
,
7230 mask
, reg
, next_select
)));
7237 /* Ensure we return a value of the proper mode. */
7238 return gen_lowpart_for_combine (mode
, x
);
7241 /* Return nonzero if X is an expression that has one of two values depending on
7242 whether some other value is zero or nonzero. In that case, we return the
7243 value that is being tested, *PTRUE is set to the value if the rtx being
7244 returned has a nonzero value, and *PFALSE is set to the other alternative.
7246 If we return zero, we set *PTRUE and *PFALSE to X. */
7249 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
7251 enum machine_mode mode
= GET_MODE (x
);
7252 enum rtx_code code
= GET_CODE (x
);
7253 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7254 unsigned HOST_WIDE_INT nz
;
7256 /* If we are comparing a value against zero, we are done. */
7257 if ((code
== NE
|| code
== EQ
)
7258 && XEXP (x
, 1) == const0_rtx
)
7260 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7261 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7265 /* If this is a unary operation whose operand has one of two values, apply
7266 our opcode to compute those values. */
7267 else if (GET_RTX_CLASS (code
) == '1'
7268 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7270 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
7271 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
7272 GET_MODE (XEXP (x
, 0)));
7276 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7277 make can't possibly match and would suppress other optimizations. */
7278 else if (code
== COMPARE
)
7281 /* If this is a binary operation, see if either side has only one of two
7282 values. If either one does or if both do and they are conditional on
7283 the same value, compute the new true and false values. */
7284 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7285 || GET_RTX_CLASS (code
) == '<')
7287 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7288 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7290 if ((cond0
!= 0 || cond1
!= 0)
7291 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7293 /* If if_then_else_cond returned zero, then true/false are the
7294 same rtl. We must copy one of them to prevent invalid rtl
7297 true0
= copy_rtx (true0
);
7298 else if (cond1
== 0)
7299 true1
= copy_rtx (true1
);
7301 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7302 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7303 return cond0
? cond0
: cond1
;
7306 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7307 operands is zero when the other is nonzero, and vice-versa,
7308 and STORE_FLAG_VALUE is 1 or -1. */
7310 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7311 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7313 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7315 rtx op0
= XEXP (XEXP (x
, 0), 1);
7316 rtx op1
= XEXP (XEXP (x
, 1), 1);
7318 cond0
= XEXP (XEXP (x
, 0), 0);
7319 cond1
= XEXP (XEXP (x
, 1), 0);
7321 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7322 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7323 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7324 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7325 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7326 || ((swap_condition (GET_CODE (cond0
))
7327 == combine_reversed_comparison_code (cond1
))
7328 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7329 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7330 && ! side_effects_p (x
))
7332 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7333 *pfalse
= gen_binary (MULT
, mode
,
7335 ? simplify_gen_unary (NEG
, mode
, op1
,
7343 /* Similarly for MULT, AND and UMIN, except that for these the result
7345 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7346 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7347 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7349 cond0
= XEXP (XEXP (x
, 0), 0);
7350 cond1
= XEXP (XEXP (x
, 1), 0);
7352 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7353 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7354 && ((GET_CODE (cond0
) == combine_reversed_comparison_code (cond1
)
7355 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7356 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7357 || ((swap_condition (GET_CODE (cond0
))
7358 == combine_reversed_comparison_code (cond1
))
7359 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7360 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7361 && ! side_effects_p (x
))
7363 *ptrue
= *pfalse
= const0_rtx
;
7369 else if (code
== IF_THEN_ELSE
)
7371 /* If we have IF_THEN_ELSE already, extract the condition and
7372 canonicalize it if it is NE or EQ. */
7373 cond0
= XEXP (x
, 0);
7374 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7375 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7376 return XEXP (cond0
, 0);
7377 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7379 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7380 return XEXP (cond0
, 0);
7386 /* If X is a SUBREG, we can narrow both the true and false values
7387 if the inner expression, if there is a condition. */
7388 else if (code
== SUBREG
7389 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7392 *ptrue
= simplify_gen_subreg (mode
, true0
,
7393 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7394 *pfalse
= simplify_gen_subreg (mode
, false0
,
7395 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
7400 /* If X is a constant, this isn't special and will cause confusions
7401 if we treat it as such. Likewise if it is equivalent to a constant. */
7402 else if (CONSTANT_P (x
)
7403 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7406 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7407 will be least confusing to the rest of the compiler. */
7408 else if (mode
== BImode
)
7410 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
7414 /* If X is known to be either 0 or -1, those are the true and
7415 false values when testing X. */
7416 else if (x
== constm1_rtx
|| x
== const0_rtx
7417 || (mode
!= VOIDmode
7418 && num_sign_bit_copies (x
, mode
) == GET_MODE_BITSIZE (mode
)))
7420 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7424 /* Likewise for 0 or a single bit. */
7425 else if (SCALAR_INT_MODE_P (mode
)
7426 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
7427 && exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7429 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
7433 /* Otherwise fail; show no condition with true and false values the same. */
7434 *ptrue
= *pfalse
= x
;
7438 /* Return the value of expression X given the fact that condition COND
7439 is known to be true when applied to REG as its first operand and VAL
7440 as its second. X is known to not be shared and so can be modified in
7443 We only handle the simplest cases, and specifically those cases that
7444 arise with IF_THEN_ELSE expressions. */
7447 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
7449 enum rtx_code code
= GET_CODE (x
);
7454 if (side_effects_p (x
))
7457 /* If either operand of the condition is a floating point value,
7458 then we have to avoid collapsing an EQ comparison. */
7460 && rtx_equal_p (x
, reg
)
7461 && ! FLOAT_MODE_P (GET_MODE (x
))
7462 && ! FLOAT_MODE_P (GET_MODE (val
)))
7465 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
7468 /* If X is (abs REG) and we know something about REG's relationship
7469 with zero, we may be able to simplify this. */
7471 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7474 case GE
: case GT
: case EQ
:
7477 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
7479 GET_MODE (XEXP (x
, 0)));
7484 /* The only other cases we handle are MIN, MAX, and comparisons if the
7485 operands are the same as REG and VAL. */
7487 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7489 if (rtx_equal_p (XEXP (x
, 0), val
))
7490 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7492 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7494 if (GET_RTX_CLASS (code
) == '<')
7496 if (comparison_dominates_p (cond
, code
))
7497 return const_true_rtx
;
7499 code
= combine_reversed_comparison_code (x
);
7501 && comparison_dominates_p (cond
, code
))
7506 else if (code
== SMAX
|| code
== SMIN
7507 || code
== UMIN
|| code
== UMAX
)
7509 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7511 /* Do not reverse the condition when it is NE or EQ.
7512 This is because we cannot conclude anything about
7513 the value of 'SMAX (x, y)' when x is not equal to y,
7514 but we can when x equals y. */
7515 if ((code
== SMAX
|| code
== UMAX
)
7516 && ! (cond
== EQ
|| cond
== NE
))
7517 cond
= reverse_condition (cond
);
7522 return unsignedp
? x
: XEXP (x
, 1);
7524 return unsignedp
? x
: XEXP (x
, 0);
7526 return unsignedp
? XEXP (x
, 1) : x
;
7528 return unsignedp
? XEXP (x
, 0) : x
;
7535 else if (code
== SUBREG
)
7537 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
7538 rtx
new, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
7540 if (SUBREG_REG (x
) != r
)
7542 /* We must simplify subreg here, before we lose track of the
7543 original inner_mode. */
7544 new = simplify_subreg (GET_MODE (x
), r
,
7545 inner_mode
, SUBREG_BYTE (x
));
7549 SUBST (SUBREG_REG (x
), r
);
7554 /* We don't have to handle SIGN_EXTEND here, because even in the
7555 case of replacing something with a modeless CONST_INT, a
7556 CONST_INT is already (supposed to be) a valid sign extension for
7557 its narrower mode, which implies it's already properly
7558 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7559 story is different. */
7560 else if (code
== ZERO_EXTEND
)
7562 enum machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
7563 rtx
new, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
7565 if (XEXP (x
, 0) != r
)
7567 /* We must simplify the zero_extend here, before we lose
7568 track of the original inner_mode. */
7569 new = simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
7574 SUBST (XEXP (x
, 0), r
);
7580 fmt
= GET_RTX_FORMAT (code
);
7581 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7584 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7585 else if (fmt
[i
] == 'E')
7586 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7587 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7594 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7595 assignment as a field assignment. */
7598 rtx_equal_for_field_assignment_p (rtx x
, rtx y
)
7600 if (x
== y
|| rtx_equal_p (x
, y
))
7603 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7606 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7607 Note that all SUBREGs of MEM are paradoxical; otherwise they
7608 would have been rewritten. */
7609 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7610 && GET_CODE (SUBREG_REG (y
)) == MEM
7611 && rtx_equal_p (SUBREG_REG (y
),
7612 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7615 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7616 && GET_CODE (SUBREG_REG (x
)) == MEM
7617 && rtx_equal_p (SUBREG_REG (x
),
7618 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7621 /* We used to see if get_last_value of X and Y were the same but that's
7622 not correct. In one direction, we'll cause the assignment to have
7623 the wrong destination and in the case, we'll import a register into this
7624 insn that might have already have been dead. So fail if none of the
7625 above cases are true. */
7629 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7630 Return that assignment if so.
7632 We only handle the most common cases. */
7635 make_field_assignment (rtx x
)
7637 rtx dest
= SET_DEST (x
);
7638 rtx src
= SET_SRC (x
);
7643 unsigned HOST_WIDE_INT len
;
7645 enum machine_mode mode
;
7647 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7648 a clear of a one-bit field. We will have changed it to
7649 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7652 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7653 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7654 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7655 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7657 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7660 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7664 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7665 && subreg_lowpart_p (XEXP (src
, 0))
7666 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7667 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7668 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7669 && GET_CODE (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == CONST_INT
7670 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7671 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7673 assign
= make_extraction (VOIDmode
, dest
, 0,
7674 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7677 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7681 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7683 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7684 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7685 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7687 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7690 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7694 /* The other case we handle is assignments into a constant-position
7695 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7696 a mask that has all one bits except for a group of zero bits and
7697 OTHER is known to have zeros where C1 has ones, this is such an
7698 assignment. Compute the position and length from C1. Shift OTHER
7699 to the appropriate position, force it to the required mode, and
7700 make the extraction. Check for the AND in both operands. */
7702 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7705 rhs
= expand_compound_operation (XEXP (src
, 0));
7706 lhs
= expand_compound_operation (XEXP (src
, 1));
7708 if (GET_CODE (rhs
) == AND
7709 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7710 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7711 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7712 else if (GET_CODE (lhs
) == AND
7713 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7714 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7715 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7719 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7720 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7721 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7722 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7725 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7729 /* The mode to use for the source is the mode of the assignment, or of
7730 what is inside a possible STRICT_LOW_PART. */
7731 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7732 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7734 /* Shift OTHER right POS places and make it the source, restricting it
7735 to the proper length and mode. */
7737 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7738 GET_MODE (src
), other
, pos
),
7740 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7741 ? ~(unsigned HOST_WIDE_INT
) 0
7742 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7745 /* If SRC is masked by an AND that does not make a difference in
7746 the value being stored, strip it. */
7747 if (GET_CODE (assign
) == ZERO_EXTRACT
7748 && GET_CODE (XEXP (assign
, 1)) == CONST_INT
7749 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
7750 && GET_CODE (src
) == AND
7751 && GET_CODE (XEXP (src
, 1)) == CONST_INT
7752 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (src
, 1))
7753 == ((unsigned HOST_WIDE_INT
) 1 << INTVAL (XEXP (assign
, 1))) - 1))
7754 src
= XEXP (src
, 0);
7756 return gen_rtx_SET (VOIDmode
, assign
, src
);
7759 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7763 apply_distributive_law (rtx x
)
7765 enum rtx_code code
= GET_CODE (x
);
7766 enum rtx_code inner_code
;
7767 rtx lhs
, rhs
, other
;
7770 /* Distributivity is not true for floating point as it can change the
7771 value. So we don't do it unless -funsafe-math-optimizations. */
7772 if (FLOAT_MODE_P (GET_MODE (x
))
7773 && ! flag_unsafe_math_optimizations
)
7776 /* The outer operation can only be one of the following: */
7777 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7778 && code
!= PLUS
&& code
!= MINUS
)
7784 /* If either operand is a primitive we can't do anything, so get out
7786 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7787 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7790 lhs
= expand_compound_operation (lhs
);
7791 rhs
= expand_compound_operation (rhs
);
7792 inner_code
= GET_CODE (lhs
);
7793 if (inner_code
!= GET_CODE (rhs
))
7796 /* See if the inner and outer operations distribute. */
7803 /* These all distribute except over PLUS. */
7804 if (code
== PLUS
|| code
== MINUS
)
7809 if (code
!= PLUS
&& code
!= MINUS
)
7814 /* This is also a multiply, so it distributes over everything. */
7818 /* Non-paradoxical SUBREGs distributes over all operations, provided
7819 the inner modes and byte offsets are the same, this is an extraction
7820 of a low-order part, we don't convert an fp operation to int or
7821 vice versa, and we would not be converting a single-word
7822 operation into a multi-word operation. The latter test is not
7823 required, but it prevents generating unneeded multi-word operations.
7824 Some of the previous tests are redundant given the latter test, but
7825 are retained because they are required for correctness.
7827 We produce the result slightly differently in this case. */
7829 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7830 || SUBREG_BYTE (lhs
) != SUBREG_BYTE (rhs
)
7831 || ! subreg_lowpart_p (lhs
)
7832 || (GET_MODE_CLASS (GET_MODE (lhs
))
7833 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7834 || (GET_MODE_SIZE (GET_MODE (lhs
))
7835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7836 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7839 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7840 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7841 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7847 /* Set LHS and RHS to the inner operands (A and B in the example
7848 above) and set OTHER to the common operand (C in the example).
7849 These is only one way to do this unless the inner operation is
7851 if (GET_RTX_CLASS (inner_code
) == 'c'
7852 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7853 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7854 else if (GET_RTX_CLASS (inner_code
) == 'c'
7855 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7856 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7857 else if (GET_RTX_CLASS (inner_code
) == 'c'
7858 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7859 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7860 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7861 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7865 /* Form the new inner operation, seeing if it simplifies first. */
7866 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7868 /* There is one exception to the general way of distributing:
7869 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7870 if (code
== XOR
&& inner_code
== IOR
)
7873 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
7876 /* We may be able to continuing distributing the result, so call
7877 ourselves recursively on the inner operation before forming the
7878 outer operation, which we return. */
7879 return gen_binary (inner_code
, GET_MODE (x
),
7880 apply_distributive_law (tem
), other
);
7883 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7886 Return an equivalent form, if different from X. Otherwise, return X. If
7887 X is zero, we are to always construct the equivalent form. */
7890 simplify_and_const_int (rtx x
, enum machine_mode mode
, rtx varop
,
7891 unsigned HOST_WIDE_INT constop
)
7893 unsigned HOST_WIDE_INT nonzero
;
7896 /* Simplify VAROP knowing that we will be only looking at some of the
7899 Note by passing in CONSTOP, we guarantee that the bits not set in
7900 CONSTOP are not significant and will never be examined. We must
7901 ensure that is the case by explicitly masking out those bits
7902 before returning. */
7903 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7905 /* If VAROP is a CLOBBER, we will fail so return it. */
7906 if (GET_CODE (varop
) == CLOBBER
)
7909 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7910 to VAROP and return the new constant. */
7911 if (GET_CODE (varop
) == CONST_INT
)
7912 return GEN_INT (trunc_int_for_mode (INTVAL (varop
) & constop
, mode
));
7914 /* See what bits may be nonzero in VAROP. Unlike the general case of
7915 a call to nonzero_bits, here we don't care about bits outside
7918 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7920 /* Turn off all bits in the constant that are known to already be zero.
7921 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7922 which is tested below. */
7926 /* If we don't have any bits left, return zero. */
7930 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7931 a power of two, we can replace this with an ASHIFT. */
7932 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7933 && (i
= exact_log2 (constop
)) >= 0)
7934 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7936 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7937 or XOR, then try to apply the distributive law. This may eliminate
7938 operations if either branch can be simplified because of the AND.
7939 It may also make some cases more complex, but those cases probably
7940 won't match a pattern either with or without this. */
7942 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7944 gen_lowpart_for_combine
7946 apply_distributive_law
7947 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7948 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7949 XEXP (varop
, 0), constop
),
7950 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7951 XEXP (varop
, 1), constop
))));
7953 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7954 the AND and see if one of the operands simplifies to zero. If so, we
7955 may eliminate it. */
7957 if (GET_CODE (varop
) == PLUS
7958 && exact_log2 (constop
+ 1) >= 0)
7962 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
7963 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
7964 if (o0
== const0_rtx
)
7966 if (o1
== const0_rtx
)
7970 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7971 if we already had one (just check for the simplest cases). */
7972 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7973 && GET_MODE (XEXP (x
, 0)) == mode
7974 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7975 varop
= XEXP (x
, 0);
7977 varop
= gen_lowpart_for_combine (mode
, varop
);
7979 /* If we can't make the SUBREG, try to return what we were given. */
7980 if (GET_CODE (varop
) == CLOBBER
)
7981 return x
? x
: varop
;
7983 /* If we are only masking insignificant bits, return VAROP. */
7984 if (constop
== nonzero
)
7988 /* Otherwise, return an AND. */
7989 constop
= trunc_int_for_mode (constop
, mode
);
7990 /* See how much, if any, of X we can use. */
7991 if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7992 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7996 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7997 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7998 SUBST (XEXP (x
, 1), GEN_INT (constop
));
8000 SUBST (XEXP (x
, 0), varop
);
8007 #define nonzero_bits_with_known(X, MODE) \
8008 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8010 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8011 It avoids exponential behavior in nonzero_bits1 when X has
8012 identical subexpressions on the first or the second level. */
8014 static unsigned HOST_WIDE_INT
8015 cached_nonzero_bits (rtx x
, enum machine_mode mode
, rtx known_x
,
8016 enum machine_mode known_mode
,
8017 unsigned HOST_WIDE_INT known_ret
)
8019 if (x
== known_x
&& mode
== known_mode
)
8022 /* Try to find identical subexpressions. If found call
8023 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8024 precomputed value for the subexpression as KNOWN_RET. */
8026 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8027 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8029 rtx x0
= XEXP (x
, 0);
8030 rtx x1
= XEXP (x
, 1);
8032 /* Check the first level. */
8034 return nonzero_bits1 (x
, mode
, x0
, mode
,
8035 nonzero_bits_with_known (x0
, mode
));
8037 /* Check the second level. */
8038 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8039 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8040 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8041 return nonzero_bits1 (x
, mode
, x1
, mode
,
8042 nonzero_bits_with_known (x1
, mode
));
8044 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8045 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8046 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8047 return nonzero_bits1 (x
, mode
, x0
, mode
,
8048 nonzero_bits_with_known (x0
, mode
));
8051 return nonzero_bits1 (x
, mode
, known_x
, known_mode
, known_ret
);
8054 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8055 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8056 is less useful. We can't allow both, because that results in exponential
8057 run time recursion. There is a nullstone testcase that triggered
8058 this. This macro avoids accidental uses of num_sign_bit_copies. */
8059 #define cached_num_sign_bit_copies()
8061 /* Given an expression, X, compute which bits in X can be nonzero.
8062 We don't care about bits outside of those defined in MODE.
8064 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8065 a shift, AND, or zero_extract, we can do better. */
8067 static unsigned HOST_WIDE_INT
8068 nonzero_bits1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8069 enum machine_mode known_mode
,
8070 unsigned HOST_WIDE_INT known_ret
)
8072 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
8073 unsigned HOST_WIDE_INT inner_nz
;
8075 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
8078 /* For floating-point values, assume all bits are needed. */
8079 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
8082 /* If X is wider than MODE, use its mode instead. */
8083 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
8085 mode
= GET_MODE (x
);
8086 nonzero
= GET_MODE_MASK (mode
);
8087 mode_width
= GET_MODE_BITSIZE (mode
);
8090 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
8091 /* Our only callers in this case look for single bit values. So
8092 just return the mode mask. Those tests will then be false. */
8095 #ifndef WORD_REGISTER_OPERATIONS
8096 /* If MODE is wider than X, but both are a single word for both the host
8097 and target machines, we can compute this from which bits of the
8098 object might be nonzero in its own mode, taking into account the fact
8099 that on many CISC machines, accessing an object in a wider mode
8100 causes the high-order bits to become undefined. So they are
8101 not known to be zero. */
8103 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
8104 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
8105 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
8106 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
8108 nonzero
&= nonzero_bits_with_known (x
, GET_MODE (x
));
8109 nonzero
|= GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
));
8114 code
= GET_CODE (x
);
8118 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8119 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8120 all the bits above ptr_mode are known to be zero. */
8121 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8123 nonzero
&= GET_MODE_MASK (ptr_mode
);
8126 /* Include declared information about alignment of pointers. */
8127 /* ??? We don't properly preserve REG_POINTER changes across
8128 pointer-to-integer casts, so we can't trust it except for
8129 things that we know must be pointers. See execute/960116-1.c. */
8130 if ((x
== stack_pointer_rtx
8131 || x
== frame_pointer_rtx
8132 || x
== arg_pointer_rtx
)
8133 && REGNO_POINTER_ALIGN (REGNO (x
)))
8135 unsigned HOST_WIDE_INT alignment
8136 = REGNO_POINTER_ALIGN (REGNO (x
)) / BITS_PER_UNIT
;
8138 #ifdef PUSH_ROUNDING
8139 /* If PUSH_ROUNDING is defined, it is possible for the
8140 stack to be momentarily aligned only to that amount,
8141 so we pick the least alignment. */
8142 if (x
== stack_pointer_rtx
&& PUSH_ARGS
)
8143 alignment
= MIN ((unsigned HOST_WIDE_INT
) PUSH_ROUNDING (1),
8147 nonzero
&= ~(alignment
- 1);
8150 /* If X is a register whose nonzero bits value is current, use it.
8151 Otherwise, if X is a register whose value we can find, use that
8152 value. Otherwise, use the previously-computed global nonzero bits
8153 for this register. */
8155 if (reg_last_set_value
[REGNO (x
)] != 0
8156 && (reg_last_set_mode
[REGNO (x
)] == mode
8157 || (GET_MODE_CLASS (reg_last_set_mode
[REGNO (x
)]) == MODE_INT
8158 && GET_MODE_CLASS (mode
) == MODE_INT
))
8159 && (reg_last_set_label
[REGNO (x
)] == label_tick
8160 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8161 && REG_N_SETS (REGNO (x
)) == 1
8162 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8164 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8165 return reg_last_set_nonzero_bits
[REGNO (x
)] & nonzero
;
8167 tem
= get_last_value (x
);
8171 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8172 /* If X is narrower than MODE and TEM is a non-negative
8173 constant that would appear negative in the mode of X,
8174 sign-extend it for use in reg_nonzero_bits because some
8175 machines (maybe most) will actually do the sign-extension
8176 and this is the conservative approach.
8178 ??? For 2.5, try to tighten up the MD files in this regard
8179 instead of this kludge. */
8181 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
8182 && GET_CODE (tem
) == CONST_INT
8184 && 0 != (INTVAL (tem
)
8185 & ((HOST_WIDE_INT
) 1
8186 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
8187 tem
= GEN_INT (INTVAL (tem
)
8188 | ((HOST_WIDE_INT
) (-1)
8189 << GET_MODE_BITSIZE (GET_MODE (x
))));
8191 return nonzero_bits_with_known (tem
, mode
) & nonzero
;
8193 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
8195 unsigned HOST_WIDE_INT mask
= reg_nonzero_bits
[REGNO (x
)];
8197 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
)
8198 /* We don't know anything about the upper bits. */
8199 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
8200 return nonzero
& mask
;
8206 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8207 /* If X is negative in MODE, sign-extend the value. */
8208 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
8209 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
8210 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
8216 #ifdef LOAD_EXTEND_OP
8217 /* In many, if not most, RISC machines, reading a byte from memory
8218 zeros the rest of the register. Noticing that fact saves a lot
8219 of extra zero-extends. */
8220 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
8221 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
8226 case UNEQ
: case LTGT
:
8227 case GT
: case GTU
: case UNGT
:
8228 case LT
: case LTU
: case UNLT
:
8229 case GE
: case GEU
: case UNGE
:
8230 case LE
: case LEU
: case UNLE
:
8231 case UNORDERED
: case ORDERED
:
8233 /* If this produces an integer result, we know which bits are set.
8234 Code here used to clear bits outside the mode of X, but that is
8237 if (GET_MODE_CLASS (mode
) == MODE_INT
8238 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
8239 nonzero
= STORE_FLAG_VALUE
;
8244 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8245 and num_sign_bit_copies. */
8246 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8247 == GET_MODE_BITSIZE (GET_MODE (x
)))
8251 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
8252 nonzero
|= (GET_MODE_MASK (mode
) & ~GET_MODE_MASK (GET_MODE (x
)));
8257 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8258 and num_sign_bit_copies. */
8259 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
8260 == GET_MODE_BITSIZE (GET_MODE (x
)))
8266 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8267 & GET_MODE_MASK (mode
));
8271 nonzero
&= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8272 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8273 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8277 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8278 Otherwise, show all the bits in the outer mode but not the inner
8280 inner_nz
= nonzero_bits_with_known (XEXP (x
, 0), mode
);
8281 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8283 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8285 & (((HOST_WIDE_INT
) 1
8286 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8287 inner_nz
|= (GET_MODE_MASK (mode
)
8288 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8291 nonzero
&= inner_nz
;
8295 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 0), mode
)
8296 & nonzero_bits_with_known (XEXP (x
, 1), mode
));
8300 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8302 unsigned HOST_WIDE_INT nonzero0
=
8303 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8305 /* Don't call nonzero_bits for the second time if it cannot change
8307 if ((nonzero
& nonzero0
) != nonzero
)
8308 nonzero
&= (nonzero0
8309 | nonzero_bits_with_known (XEXP (x
, 1), mode
));
8313 case PLUS
: case MINUS
:
8315 case DIV
: case UDIV
:
8316 case MOD
: case UMOD
:
8317 /* We can apply the rules of arithmetic to compute the number of
8318 high- and low-order zero bits of these operations. We start by
8319 computing the width (position of the highest-order nonzero bit)
8320 and the number of low-order zero bits for each value. */
8322 unsigned HOST_WIDE_INT nz0
=
8323 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8324 unsigned HOST_WIDE_INT nz1
=
8325 nonzero_bits_with_known (XEXP (x
, 1), mode
);
8326 int sign_index
= GET_MODE_BITSIZE (GET_MODE (x
)) - 1;
8327 int width0
= floor_log2 (nz0
) + 1;
8328 int width1
= floor_log2 (nz1
) + 1;
8329 int low0
= floor_log2 (nz0
& -nz0
);
8330 int low1
= floor_log2 (nz1
& -nz1
);
8331 HOST_WIDE_INT op0_maybe_minusp
8332 = (nz0
& ((HOST_WIDE_INT
) 1 << sign_index
));
8333 HOST_WIDE_INT op1_maybe_minusp
8334 = (nz1
& ((HOST_WIDE_INT
) 1 << sign_index
));
8335 unsigned int result_width
= mode_width
;
8341 result_width
= MAX (width0
, width1
) + 1;
8342 result_low
= MIN (low0
, low1
);
8345 result_low
= MIN (low0
, low1
);
8348 result_width
= width0
+ width1
;
8349 result_low
= low0
+ low1
;
8354 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8355 result_width
= width0
;
8360 result_width
= width0
;
8365 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8366 result_width
= MIN (width0
, width1
);
8367 result_low
= MIN (low0
, low1
);
8372 result_width
= MIN (width0
, width1
);
8373 result_low
= MIN (low0
, low1
);
8379 if (result_width
< mode_width
)
8380 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8383 nonzero
&= ~(((HOST_WIDE_INT
) 1 << result_low
) - 1);
8385 #ifdef POINTERS_EXTEND_UNSIGNED
8386 /* If pointers extend unsigned and this is an addition or subtraction
8387 to a pointer in Pmode, all the bits above ptr_mode are known to be
8389 if (POINTERS_EXTEND_UNSIGNED
> 0 && GET_MODE (x
) == Pmode
8390 && (code
== PLUS
|| code
== MINUS
)
8391 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8392 nonzero
&= GET_MODE_MASK (ptr_mode
);
8398 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8399 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8400 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8404 /* If this is a SUBREG formed for a promoted variable that has
8405 been zero-extended, we know that at least the high-order bits
8406 are zero, though others might be too. */
8408 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
) > 0)
8409 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8410 & nonzero_bits_with_known (SUBREG_REG (x
), GET_MODE (x
)));
8412 /* If the inner mode is a single word for both the host and target
8413 machines, we can compute this from which bits of the inner
8414 object might be nonzero. */
8415 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8416 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8417 <= HOST_BITS_PER_WIDE_INT
))
8419 nonzero
&= nonzero_bits_with_known (SUBREG_REG (x
), mode
);
8421 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8422 /* If this is a typical RISC machine, we only have to worry
8423 about the way loads are extended. */
8424 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8426 & (((unsigned HOST_WIDE_INT
) 1
8427 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8429 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8430 || GET_CODE (SUBREG_REG (x
)) != MEM
)
8433 /* On many CISC machines, accessing an object in a wider mode
8434 causes the high-order bits to become undefined. So they are
8435 not known to be zero. */
8436 if (GET_MODE_SIZE (GET_MODE (x
))
8437 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8438 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8439 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8448 /* The nonzero bits are in two classes: any bits within MODE
8449 that aren't in GET_MODE (x) are always significant. The rest of the
8450 nonzero bits are those that are significant in the operand of
8451 the shift when shifted the appropriate number of bits. This
8452 shows that high-order bits are cleared by the right shift and
8453 low-order bits by left shifts. */
8454 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8455 && INTVAL (XEXP (x
, 1)) >= 0
8456 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8458 enum machine_mode inner_mode
= GET_MODE (x
);
8459 unsigned int width
= GET_MODE_BITSIZE (inner_mode
);
8460 int count
= INTVAL (XEXP (x
, 1));
8461 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8462 unsigned HOST_WIDE_INT op_nonzero
=
8463 nonzero_bits_with_known (XEXP (x
, 0), mode
);
8464 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8465 unsigned HOST_WIDE_INT outer
= 0;
8467 if (mode_width
> width
)
8468 outer
= (op_nonzero
& nonzero
& ~mode_mask
);
8470 if (code
== LSHIFTRT
)
8472 else if (code
== ASHIFTRT
)
8476 /* If the sign bit may have been nonzero before the shift, we
8477 need to mark all the places it could have been copied to
8478 by the shift as possibly nonzero. */
8479 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8480 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8482 else if (code
== ASHIFT
)
8485 inner
= ((inner
<< (count
% width
)
8486 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8488 nonzero
&= (outer
| inner
);
8494 /* This is at most the number of bits in the mode. */
8495 nonzero
= ((HOST_WIDE_INT
) 2 << (floor_log2 (mode_width
))) - 1;
8499 /* If CLZ has a known value at zero, then the nonzero bits are
8500 that value, plus the number of bits in the mode minus one. */
8501 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8502 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8508 /* If CTZ has a known value at zero, then the nonzero bits are
8509 that value, plus the number of bits in the mode minus one. */
8510 if (CTZ_DEFINED_VALUE_AT_ZERO (mode
, nonzero
))
8511 nonzero
|= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
))) - 1;
8521 nonzero
&= (nonzero_bits_with_known (XEXP (x
, 1), mode
)
8522 | nonzero_bits_with_known (XEXP (x
, 2), mode
));
8532 /* See the macro definition above. */
8533 #undef cached_num_sign_bit_copies
8535 #define num_sign_bit_copies_with_known(X, M) \
8536 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8538 /* The function cached_num_sign_bit_copies is a wrapper around
8539 num_sign_bit_copies1. It avoids exponential behavior in
8540 num_sign_bit_copies1 when X has identical subexpressions on the
8541 first or the second level. */
8544 cached_num_sign_bit_copies (rtx x
, enum machine_mode mode
, rtx known_x
,
8545 enum machine_mode known_mode
,
8546 unsigned int known_ret
)
8548 if (x
== known_x
&& mode
== known_mode
)
8551 /* Try to find identical subexpressions. If found call
8552 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8553 the precomputed value for the subexpression as KNOWN_RET. */
8555 if (GET_RTX_CLASS (GET_CODE (x
)) == '2'
8556 || GET_RTX_CLASS (GET_CODE (x
)) == 'c')
8558 rtx x0
= XEXP (x
, 0);
8559 rtx x1
= XEXP (x
, 1);
8561 /* Check the first level. */
8564 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8565 num_sign_bit_copies_with_known (x0
, mode
));
8567 /* Check the second level. */
8568 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
8569 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
8570 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
8572 num_sign_bit_copies1 (x
, mode
, x1
, mode
,
8573 num_sign_bit_copies_with_known (x1
, mode
));
8575 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
8576 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
8577 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
8579 num_sign_bit_copies1 (x
, mode
, x0
, mode
,
8580 num_sign_bit_copies_with_known (x0
, mode
));
8583 return num_sign_bit_copies1 (x
, mode
, known_x
, known_mode
, known_ret
);
8586 /* Return the number of bits at the high-order end of X that are known to
8587 be equal to the sign bit. X will be used in mode MODE; if MODE is
8588 VOIDmode, X will be used in its own mode. The returned value will always
8589 be between 1 and the number of bits in MODE. */
8592 num_sign_bit_copies1 (rtx x
, enum machine_mode mode
, rtx known_x
,
8593 enum machine_mode known_mode
,
8594 unsigned int known_ret
)
8596 enum rtx_code code
= GET_CODE (x
);
8597 unsigned int bitwidth
;
8598 int num0
, num1
, result
;
8599 unsigned HOST_WIDE_INT nonzero
;
8602 /* If we weren't given a mode, use the mode of X. If the mode is still
8603 VOIDmode, we don't know anything. Likewise if one of the modes is
8606 if (mode
== VOIDmode
)
8607 mode
= GET_MODE (x
);
8609 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8612 bitwidth
= GET_MODE_BITSIZE (mode
);
8614 /* For a smaller object, just ignore the high bits. */
8615 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8617 num0
= num_sign_bit_copies_with_known (x
, GET_MODE (x
));
8619 num0
- (int) (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
));
8622 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8624 #ifndef WORD_REGISTER_OPERATIONS
8625 /* If this machine does not do all register operations on the entire
8626 register and MODE is wider than the mode of X, we can say nothing
8627 at all about the high-order bits. */
8630 /* Likewise on machines that do, if the mode of the object is smaller
8631 than a word and loads of that size don't sign extend, we can say
8632 nothing about the high order bits. */
8633 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8634 #ifdef LOAD_EXTEND_OP
8635 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8646 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8647 /* If pointers extend signed and this is a pointer in Pmode, say that
8648 all the bits above ptr_mode are known to be sign bit copies. */
8649 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8651 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8654 if (reg_last_set_value
[REGNO (x
)] != 0
8655 && reg_last_set_mode
[REGNO (x
)] == mode
8656 && (reg_last_set_label
[REGNO (x
)] == label_tick
8657 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8658 && REG_N_SETS (REGNO (x
)) == 1
8659 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
,
8661 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8662 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8664 tem
= get_last_value (x
);
8666 return num_sign_bit_copies_with_known (tem
, mode
);
8668 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0
8669 && GET_MODE_BITSIZE (GET_MODE (x
)) == bitwidth
)
8670 return reg_sign_bit_copies
[REGNO (x
)];
8674 #ifdef LOAD_EXTEND_OP
8675 /* Some RISC machines sign-extend all loads of smaller than a word. */
8676 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8677 return MAX (1, ((int) bitwidth
8678 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1));
8683 /* If the constant is negative, take its 1's complement and remask.
8684 Then see how many zero bits we have. */
8685 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8686 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8687 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8688 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8690 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8693 /* If this is a SUBREG for a promoted object that is sign-extended
8694 and we are looking at it in a wider mode, we know that at least the
8695 high-order bits are known to be sign bit copies. */
8697 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8699 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8700 return MAX ((int) bitwidth
8701 - (int) GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8705 /* For a smaller object, just ignore the high bits. */
8706 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8708 num0
= num_sign_bit_copies_with_known (SUBREG_REG (x
), VOIDmode
);
8709 return MAX (1, (num0
8710 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8714 #ifdef WORD_REGISTER_OPERATIONS
8715 #ifdef LOAD_EXTEND_OP
8716 /* For paradoxical SUBREGs on machines where all register operations
8717 affect the entire register, just look inside. Note that we are
8718 passing MODE to the recursive call, so the number of sign bit copies
8719 will remain relative to that mode, not the inner mode. */
8721 /* This works only if loads sign extend. Otherwise, if we get a
8722 reload for the inner part, it may be loaded from the stack, and
8723 then we lose all sign bit copies that existed before the store
8726 if ((GET_MODE_SIZE (GET_MODE (x
))
8727 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8728 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8729 && GET_CODE (SUBREG_REG (x
)) == MEM
)
8730 return num_sign_bit_copies_with_known (SUBREG_REG (x
), mode
);
8736 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8737 return MAX (1, (int) bitwidth
- INTVAL (XEXP (x
, 1)));
8741 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8742 + num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
));
8745 /* For a smaller object, just ignore the high bits. */
8746 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), VOIDmode
);
8747 return MAX (1, (num0
- (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8751 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8753 case ROTATE
: case ROTATERT
:
8754 /* If we are rotating left by a number of bits less than the number
8755 of sign bit copies, we can just subtract that amount from the
8757 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8758 && INTVAL (XEXP (x
, 1)) >= 0
8759 && INTVAL (XEXP (x
, 1)) < (int) bitwidth
)
8761 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8762 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8763 : (int) bitwidth
- INTVAL (XEXP (x
, 1))));
8768 /* In general, this subtracts one sign bit copy. But if the value
8769 is known to be positive, the number of sign bit copies is the
8770 same as that of the input. Finally, if the input has just one bit
8771 that might be nonzero, all the bits are copies of the sign bit. */
8772 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8773 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8774 return num0
> 1 ? num0
- 1 : 1;
8776 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8781 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8786 case IOR
: case AND
: case XOR
:
8787 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8788 /* Logical operations will preserve the number of sign-bit copies.
8789 MIN and MAX operations always return one of the operands. */
8790 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8791 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8792 return MIN (num0
, num1
);
8794 case PLUS
: case MINUS
:
8795 /* For addition and subtraction, we can have a 1-bit carry. However,
8796 if we are subtracting 1 from a positive number, there will not
8797 be such a carry. Furthermore, if the positive number is known to
8798 be 0 or 1, we know the result is either -1 or 0. */
8800 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8801 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8803 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8804 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8805 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8806 : bitwidth
- floor_log2 (nonzero
) - 1);
8809 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8810 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8811 result
= MAX (1, MIN (num0
, num1
) - 1);
8813 #ifdef POINTERS_EXTEND_UNSIGNED
8814 /* If pointers extend signed and this is an addition or subtraction
8815 to a pointer in Pmode, all the bits above ptr_mode are known to be
8817 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
8818 && (code
== PLUS
|| code
== MINUS
)
8819 && GET_CODE (XEXP (x
, 0)) == REG
&& REG_POINTER (XEXP (x
, 0)))
8820 result
= MAX ((int) (GET_MODE_BITSIZE (Pmode
)
8821 - GET_MODE_BITSIZE (ptr_mode
) + 1),
8827 /* The number of bits of the product is the sum of the number of
8828 bits of both terms. However, unless one of the terms if known
8829 to be positive, we must allow for an additional bit since negating
8830 a negative number can remove one sign bit copy. */
8832 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8833 num1
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8835 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8837 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8838 || (((nonzero_bits (XEXP (x
, 0), mode
)
8839 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8840 && ((nonzero_bits (XEXP (x
, 1), mode
)
8841 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8844 return MAX (1, result
);
8847 /* The result must be <= the first operand. If the first operand
8848 has the high bit set, we know nothing about the number of sign
8850 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8852 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8853 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8856 return num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8859 /* The result must be <= the second operand. */
8860 return num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8863 /* Similar to unsigned division, except that we have to worry about
8864 the case where the divisor is negative, in which case we have
8866 result
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8868 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8869 || (nonzero_bits (XEXP (x
, 1), mode
)
8870 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8876 result
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8878 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8879 || (nonzero_bits (XEXP (x
, 1), mode
)
8880 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8886 /* Shifts by a constant add to the number of bits equal to the
8888 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8889 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8890 && INTVAL (XEXP (x
, 1)) > 0)
8891 num0
= MIN ((int) bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8896 /* Left shifts destroy copies. */
8897 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8898 || INTVAL (XEXP (x
, 1)) < 0
8899 || INTVAL (XEXP (x
, 1)) >= (int) bitwidth
)
8902 num0
= num_sign_bit_copies_with_known (XEXP (x
, 0), mode
);
8903 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8906 num0
= num_sign_bit_copies_with_known (XEXP (x
, 1), mode
);
8907 num1
= num_sign_bit_copies_with_known (XEXP (x
, 2), mode
);
8908 return MIN (num0
, num1
);
8910 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8911 case UNEQ
: case LTGT
: case UNGE
: case UNGT
: case UNLE
: case UNLT
:
8912 case GEU
: case GTU
: case LEU
: case LTU
:
8913 case UNORDERED
: case ORDERED
:
8914 /* If the constant is negative, take its 1's complement and remask.
8915 Then see how many zero bits we have. */
8916 nonzero
= STORE_FLAG_VALUE
;
8917 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8918 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8919 nonzero
= (~nonzero
) & GET_MODE_MASK (mode
);
8921 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8928 /* If we haven't been able to figure it out by one of the above rules,
8929 see if some of the high-order bits are known to be zero. If so,
8930 count those bits and return one less than that amount. If we can't
8931 safely compute the mask for this mode, always return BITWIDTH. */
8933 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8936 nonzero
= nonzero_bits (x
, mode
);
8937 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8938 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8941 /* Return the number of "extended" bits there are in X, when interpreted
8942 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8943 unsigned quantities, this is the number of high-order zero bits.
8944 For signed quantities, this is the number of copies of the sign bit
8945 minus 1. In both case, this function returns the number of "spare"
8946 bits. For example, if two quantities for which this function returns
8947 at least 1 are added, the addition is known not to overflow.
8949 This function will always return 0 unless called during combine, which
8950 implies that it must be called from a define_split. */
8953 extended_count (rtx x
, enum machine_mode mode
, int unsignedp
)
8955 if (nonzero_sign_valid
== 0)
8959 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8960 ? (unsigned int) (GET_MODE_BITSIZE (mode
) - 1
8961 - floor_log2 (nonzero_bits (x
, mode
)))
8963 : num_sign_bit_copies (x
, mode
) - 1);
8966 /* This function is called from `simplify_shift_const' to merge two
8967 outer operations. Specifically, we have already found that we need
8968 to perform operation *POP0 with constant *PCONST0 at the outermost
8969 position. We would now like to also perform OP1 with constant CONST1
8970 (with *POP0 being done last).
8972 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8973 the resulting operation. *PCOMP_P is set to 1 if we would need to
8974 complement the innermost operand, otherwise it is unchanged.
8976 MODE is the mode in which the operation will be done. No bits outside
8977 the width of this mode matter. It is assumed that the width of this mode
8978 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8980 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8981 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8982 result is simply *PCONST0.
8984 If the resulting operation cannot be expressed as one operation, we
8985 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8988 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, enum machine_mode mode
, int *pcomp_p
)
8990 enum rtx_code op0
= *pop0
;
8991 HOST_WIDE_INT const0
= *pconst0
;
8993 const0
&= GET_MODE_MASK (mode
);
8994 const1
&= GET_MODE_MASK (mode
);
8996 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9000 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9003 if (op1
== NIL
|| op0
== SET
)
9006 else if (op0
== NIL
)
9007 op0
= op1
, const0
= const1
;
9009 else if (op0
== op1
)
9033 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9034 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
9037 /* If the two constants aren't the same, we can't do anything. The
9038 remaining six cases can all be done. */
9039 else if (const0
!= const1
)
9047 /* (a & b) | b == b */
9049 else /* op1 == XOR */
9050 /* (a ^ b) | b == a | b */
9056 /* (a & b) ^ b == (~a) & b */
9057 op0
= AND
, *pcomp_p
= 1;
9058 else /* op1 == IOR */
9059 /* (a | b) ^ b == a & ~b */
9060 op0
= AND
, const0
= ~const0
;
9065 /* (a | b) & b == b */
9067 else /* op1 == XOR */
9068 /* (a ^ b) & b) == (~a) & b */
9075 /* Check for NO-OP cases. */
9076 const0
&= GET_MODE_MASK (mode
);
9078 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
9080 else if (const0
== 0 && op0
== AND
)
9082 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
9086 /* ??? Slightly redundant with the above mask, but not entirely.
9087 Moving this above means we'd have to sign-extend the mode mask
9088 for the final test. */
9089 const0
= trunc_int_for_mode (const0
, mode
);
9097 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9098 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9099 that we started with.
9101 The shift is normally computed in the widest mode we find in VAROP, as
9102 long as it isn't a different number of words than RESULT_MODE. Exceptions
9103 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9106 simplify_shift_const (rtx x
, enum rtx_code code
,
9107 enum machine_mode result_mode
, rtx varop
,
9110 enum rtx_code orig_code
= code
;
9113 enum machine_mode mode
= result_mode
;
9114 enum machine_mode shift_mode
, tmode
;
9115 unsigned int mode_words
9116 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
9117 /* We form (outer_op (code varop count) (outer_const)). */
9118 enum rtx_code outer_op
= NIL
;
9119 HOST_WIDE_INT outer_const
= 0;
9121 int complement_p
= 0;
9124 /* Make sure and truncate the "natural" shift on the way in. We don't
9125 want to do this inside the loop as it makes it more difficult to
9127 #ifdef SHIFT_COUNT_TRUNCATED
9128 if (SHIFT_COUNT_TRUNCATED
)
9129 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
9132 /* If we were given an invalid count, don't do anything except exactly
9133 what was requested. */
9135 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_BITSIZE (mode
))
9140 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (orig_count
));
9145 /* Unless one of the branches of the `if' in this loop does a `continue',
9146 we will `break' the loop after the `if'. */
9150 /* If we have an operand of (clobber (const_int 0)), just return that
9152 if (GET_CODE (varop
) == CLOBBER
)
9155 /* If we discovered we had to complement VAROP, leave. Making a NOT
9156 here would cause an infinite loop. */
9160 /* Convert ROTATERT to ROTATE. */
9161 if (code
== ROTATERT
)
9163 unsigned int bitsize
= GET_MODE_BITSIZE (result_mode
);;
9165 if (VECTOR_MODE_P (result_mode
))
9166 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
9168 count
= bitsize
- count
;
9171 /* We need to determine what mode we will do the shift in. If the
9172 shift is a right shift or a ROTATE, we must always do it in the mode
9173 it was originally done in. Otherwise, we can do it in MODE, the
9174 widest mode encountered. */
9176 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9177 ? result_mode
: mode
);
9179 /* Handle cases where the count is greater than the size of the mode
9180 minus 1. For ASHIFT, use the size minus one as the count (this can
9181 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9182 take the count modulo the size. For other shifts, the result is
9185 Since these shifts are being produced by the compiler by combining
9186 multiple operations, each of which are defined, we know what the
9187 result is supposed to be. */
9189 if (count
> (unsigned int) (GET_MODE_BITSIZE (shift_mode
) - 1))
9191 if (code
== ASHIFTRT
)
9192 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9193 else if (code
== ROTATE
|| code
== ROTATERT
)
9194 count
%= GET_MODE_BITSIZE (shift_mode
);
9197 /* We can't simply return zero because there may be an
9205 /* An arithmetic right shift of a quantity known to be -1 or 0
9207 if (code
== ASHIFTRT
9208 && (num_sign_bit_copies (varop
, shift_mode
)
9209 == GET_MODE_BITSIZE (shift_mode
)))
9215 /* If we are doing an arithmetic right shift and discarding all but
9216 the sign bit copies, this is equivalent to doing a shift by the
9217 bitsize minus one. Convert it into that shift because it will often
9218 allow other simplifications. */
9220 if (code
== ASHIFTRT
9221 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
9222 >= GET_MODE_BITSIZE (shift_mode
)))
9223 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
9225 /* We simplify the tests below and elsewhere by converting
9226 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9227 `make_compound_operation' will convert it to an ASHIFTRT for
9228 those machines (such as VAX) that don't have an LSHIFTRT. */
9229 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9231 && ((nonzero_bits (varop
, shift_mode
)
9232 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
9236 if (code
== LSHIFTRT
9237 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9238 && !(nonzero_bits (varop
, shift_mode
) >> count
))
9241 && GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
9242 && !((nonzero_bits (varop
, shift_mode
) << count
)
9243 & GET_MODE_MASK (shift_mode
)))
9246 switch (GET_CODE (varop
))
9252 new = expand_compound_operation (varop
);
9261 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9262 minus the width of a smaller mode, we can do this with a
9263 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9264 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9265 && ! mode_dependent_address_p (XEXP (varop
, 0))
9266 && ! MEM_VOLATILE_P (varop
)
9267 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9268 MODE_INT
, 1)) != BLKmode
)
9270 new = adjust_address_nv (varop
, tmode
,
9271 BYTES_BIG_ENDIAN
? 0
9272 : count
/ BITS_PER_UNIT
);
9274 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9275 : ZERO_EXTEND
, mode
, new);
9282 /* Similar to the case above, except that we can only do this if
9283 the resulting mode is the same as that of the underlying
9284 MEM and adjust the address depending on the *bits* endianness
9285 because of the way that bit-field extract insns are defined. */
9286 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9287 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
9288 MODE_INT
, 1)) != BLKmode
9289 && tmode
== GET_MODE (XEXP (varop
, 0)))
9291 if (BITS_BIG_ENDIAN
)
9292 new = XEXP (varop
, 0);
9295 new = copy_rtx (XEXP (varop
, 0));
9296 SUBST (XEXP (new, 0),
9297 plus_constant (XEXP (new, 0),
9298 count
/ BITS_PER_UNIT
));
9301 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
9302 : ZERO_EXTEND
, mode
, new);
9309 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9310 the same number of words as what we've seen so far. Then store
9311 the widest mode in MODE. */
9312 if (subreg_lowpart_p (varop
)
9313 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9314 > GET_MODE_SIZE (GET_MODE (varop
)))
9315 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
9316 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
9319 varop
= SUBREG_REG (varop
);
9320 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
9321 mode
= GET_MODE (varop
);
9327 /* Some machines use MULT instead of ASHIFT because MULT
9328 is cheaper. But it is still better on those machines to
9329 merge two shifts into one. */
9330 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9331 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9334 = gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
9335 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9341 /* Similar, for when divides are cheaper. */
9342 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9343 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
9346 = gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
9347 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
9353 /* If we are extracting just the sign bit of an arithmetic
9354 right shift, that shift is not needed. However, the sign
9355 bit of a wider mode may be different from what would be
9356 interpreted as the sign bit in a narrower mode, so, if
9357 the result is narrower, don't discard the shift. */
9358 if (code
== LSHIFTRT
9359 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9360 && (GET_MODE_BITSIZE (result_mode
)
9361 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
9363 varop
= XEXP (varop
, 0);
9367 /* ... fall through ... */
9372 /* Here we have two nested shifts. The result is usually the
9373 AND of a new shift with a mask. We compute the result below. */
9374 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9375 && INTVAL (XEXP (varop
, 1)) >= 0
9376 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
9377 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9378 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
9380 enum rtx_code first_code
= GET_CODE (varop
);
9381 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
9382 unsigned HOST_WIDE_INT mask
;
9385 /* We have one common special case. We can't do any merging if
9386 the inner code is an ASHIFTRT of a smaller mode. However, if
9387 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9388 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9389 we can convert it to
9390 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9391 This simplifies certain SIGN_EXTEND operations. */
9392 if (code
== ASHIFT
&& first_code
== ASHIFTRT
9393 && count
== (unsigned int)
9394 (GET_MODE_BITSIZE (result_mode
)
9395 - GET_MODE_BITSIZE (GET_MODE (varop
))))
9397 /* C3 has the low-order C1 bits zero. */
9399 mask
= (GET_MODE_MASK (mode
)
9400 & ~(((HOST_WIDE_INT
) 1 << first_count
) - 1));
9402 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
9403 XEXP (varop
, 0), mask
);
9404 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
9406 count
= first_count
;
9411 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9412 than C1 high-order bits equal to the sign bit, we can convert
9413 this to either an ASHIFT or an ASHIFTRT depending on the
9416 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9418 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9419 && GET_MODE (varop
) == shift_mode
9420 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9423 varop
= XEXP (varop
, 0);
9425 signed_count
= count
- first_count
;
9426 if (signed_count
< 0)
9427 count
= -signed_count
, code
= ASHIFT
;
9429 count
= signed_count
;
9434 /* There are some cases we can't do. If CODE is ASHIFTRT,
9435 we can only do this if FIRST_CODE is also ASHIFTRT.
9437 We can't do the case when CODE is ROTATE and FIRST_CODE is
9440 If the mode of this shift is not the mode of the outer shift,
9441 we can't do this if either shift is a right shift or ROTATE.
9443 Finally, we can't do any of these if the mode is too wide
9444 unless the codes are the same.
9446 Handle the case where the shift codes are the same
9449 if (code
== first_code
)
9451 if (GET_MODE (varop
) != result_mode
9452 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9456 count
+= first_count
;
9457 varop
= XEXP (varop
, 0);
9461 if (code
== ASHIFTRT
9462 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9463 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9464 || (GET_MODE (varop
) != result_mode
9465 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9466 || first_code
== ROTATE
9467 || code
== ROTATE
)))
9470 /* To compute the mask to apply after the shift, shift the
9471 nonzero bits of the inner shift the same way the
9472 outer shift will. */
9474 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9477 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9480 /* Give up if we can't compute an outer operation to use. */
9482 || GET_CODE (mask_rtx
) != CONST_INT
9483 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9485 result_mode
, &complement_p
))
9488 /* If the shifts are in the same direction, we add the
9489 counts. Otherwise, we subtract them. */
9490 signed_count
= count
;
9491 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9492 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9493 signed_count
+= first_count
;
9495 signed_count
-= first_count
;
9497 /* If COUNT is positive, the new shift is usually CODE,
9498 except for the two exceptions below, in which case it is
9499 FIRST_CODE. If the count is negative, FIRST_CODE should
9501 if (signed_count
> 0
9502 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9503 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9504 code
= first_code
, count
= signed_count
;
9505 else if (signed_count
< 0)
9506 code
= first_code
, count
= -signed_count
;
9508 count
= signed_count
;
9510 varop
= XEXP (varop
, 0);
9514 /* If we have (A << B << C) for any shift, we can convert this to
9515 (A << C << B). This wins if A is a constant. Only try this if
9516 B is not a constant. */
9518 else if (GET_CODE (varop
) == code
9519 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9521 = simplify_binary_operation (code
, mode
,
9525 varop
= gen_rtx_fmt_ee (code
, mode
, new, XEXP (varop
, 1));
9532 /* Make this fit the case below. */
9533 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0),
9534 GEN_INT (GET_MODE_MASK (mode
)));
9540 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9541 with C the size of VAROP - 1 and the shift is logical if
9542 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9543 we have an (le X 0) operation. If we have an arithmetic shift
9544 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9545 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9547 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9548 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9549 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9550 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9551 && count
== (unsigned int)
9552 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9553 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9556 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
9559 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9560 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9565 /* If we have (shift (logical)), move the logical to the outside
9566 to allow it to possibly combine with another logical and the
9567 shift to combine with another shift. This also canonicalizes to
9568 what a ZERO_EXTRACT looks like. Also, some machines have
9569 (and (shift)) insns. */
9571 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9572 && (new = simplify_binary_operation (code
, result_mode
,
9574 GEN_INT (count
))) != 0
9575 && GET_CODE (new) == CONST_INT
9576 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9577 INTVAL (new), result_mode
, &complement_p
))
9579 varop
= XEXP (varop
, 0);
9583 /* If we can't do that, try to simplify the shift in each arm of the
9584 logical expression, make a new logical expression, and apply
9585 the inverse distributive law. */
9587 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9588 XEXP (varop
, 0), count
);
9589 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9590 XEXP (varop
, 1), count
);
9592 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9593 varop
= apply_distributive_law (varop
);
9600 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9601 says that the sign bit can be tested, FOO has mode MODE, C is
9602 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9603 that may be nonzero. */
9604 if (code
== LSHIFTRT
9605 && XEXP (varop
, 1) == const0_rtx
9606 && GET_MODE (XEXP (varop
, 0)) == result_mode
9607 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9608 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9609 && ((STORE_FLAG_VALUE
9610 & ((HOST_WIDE_INT
) 1
9611 < (GET_MODE_BITSIZE (result_mode
) - 1))))
9612 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9613 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9614 (HOST_WIDE_INT
) 1, result_mode
,
9617 varop
= XEXP (varop
, 0);
9624 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9625 than the number of bits in the mode is equivalent to A. */
9626 if (code
== LSHIFTRT
9627 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9628 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9630 varop
= XEXP (varop
, 0);
9635 /* NEG commutes with ASHIFT since it is multiplication. Move the
9636 NEG outside to allow shifts to combine. */
9638 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9639 (HOST_WIDE_INT
) 0, result_mode
,
9642 varop
= XEXP (varop
, 0);
9648 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9649 is one less than the number of bits in the mode is
9650 equivalent to (xor A 1). */
9651 if (code
== LSHIFTRT
9652 && count
== (unsigned int) (GET_MODE_BITSIZE (result_mode
) - 1)
9653 && XEXP (varop
, 1) == constm1_rtx
9654 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9655 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9656 (HOST_WIDE_INT
) 1, result_mode
,
9660 varop
= XEXP (varop
, 0);
9664 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9665 that might be nonzero in BAR are those being shifted out and those
9666 bits are known zero in FOO, we can replace the PLUS with FOO.
9667 Similarly in the other operand order. This code occurs when
9668 we are computing the size of a variable-size array. */
9670 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9671 && count
< HOST_BITS_PER_WIDE_INT
9672 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9673 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9674 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9676 varop
= XEXP (varop
, 0);
9679 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9680 && count
< HOST_BITS_PER_WIDE_INT
9681 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9682 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9684 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9685 & nonzero_bits (XEXP (varop
, 1),
9688 varop
= XEXP (varop
, 1);
9692 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9694 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9695 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9697 GEN_INT (count
))) != 0
9698 && GET_CODE (new) == CONST_INT
9699 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9700 INTVAL (new), result_mode
, &complement_p
))
9702 varop
= XEXP (varop
, 0);
9708 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9709 with C the size of VAROP - 1 and the shift is logical if
9710 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9711 we have a (gt X 0) operation. If the shift is arithmetic with
9712 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9713 we have a (neg (gt X 0)) operation. */
9715 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9716 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9717 && count
== (unsigned int)
9718 (GET_MODE_BITSIZE (GET_MODE (varop
)) - 1)
9719 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9720 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9721 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (varop
, 0), 1))
9723 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9726 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
9729 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9730 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
9737 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9738 if the truncate does not affect the value. */
9739 if (code
== LSHIFTRT
9740 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9741 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9742 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9743 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9744 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9746 rtx varop_inner
= XEXP (varop
, 0);
9749 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
9750 XEXP (varop_inner
, 0),
9752 (count
+ INTVAL (XEXP (varop_inner
, 1))));
9753 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
9766 /* We need to determine what mode to do the shift in. If the shift is
9767 a right shift or ROTATE, we must always do it in the mode it was
9768 originally done in. Otherwise, we can do it in MODE, the widest mode
9769 encountered. The code we care about is that of the shift that will
9770 actually be done, not the shift that was originally requested. */
9772 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9773 ? result_mode
: mode
);
9775 /* We have now finished analyzing the shift. The result should be
9776 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9777 OUTER_OP is non-NIL, it is an operation that needs to be applied
9778 to the result of the shift. OUTER_CONST is the relevant constant,
9779 but we must turn off all bits turned off in the shift.
9781 If we were passed a value for X, see if we can use any pieces of
9782 it. If not, make new rtx. */
9784 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9785 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9786 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == count
)
9787 const_rtx
= XEXP (x
, 1);
9789 const_rtx
= GEN_INT (count
);
9791 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9792 && GET_MODE (XEXP (x
, 0)) == shift_mode
9793 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9794 varop
= XEXP (x
, 0);
9795 else if (GET_MODE (varop
) != shift_mode
)
9796 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9798 /* If we can't make the SUBREG, try to return what we were given. */
9799 if (GET_CODE (varop
) == CLOBBER
)
9800 return x
? x
: varop
;
9802 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9806 x
= gen_rtx_fmt_ee (code
, shift_mode
, varop
, const_rtx
);
9808 /* If we have an outer operation and we just made a shift, it is
9809 possible that we could have simplified the shift were it not
9810 for the outer operation. So try to do the simplification
9813 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9814 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9815 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9816 INTVAL (XEXP (x
, 1)));
9818 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9819 turn off all the bits that the shift would have turned off. */
9820 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9821 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9822 GET_MODE_MASK (result_mode
) >> orig_count
);
9824 /* Do the remainder of the processing in RESULT_MODE. */
9825 x
= gen_lowpart_for_combine (result_mode
, x
);
9827 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9830 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
9832 if (outer_op
!= NIL
)
9834 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9835 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9837 if (outer_op
== AND
)
9838 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9839 else if (outer_op
== SET
)
9840 /* This means that we have determined that the result is
9841 equivalent to a constant. This should be rare. */
9842 x
= GEN_INT (outer_const
);
9843 else if (GET_RTX_CLASS (outer_op
) == '1')
9844 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
9846 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9852 /* Like recog, but we receive the address of a pointer to a new pattern.
9853 We try to match the rtx that the pointer points to.
9854 If that fails, we may try to modify or replace the pattern,
9855 storing the replacement into the same pointer object.
9857 Modifications include deletion or addition of CLOBBERs.
9859 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9860 the CLOBBERs are placed.
9862 The value is the final insn code from the pattern ultimately matched,
9866 recog_for_combine (rtx
*pnewpat
, rtx insn
, rtx
*pnotes
)
9869 int insn_code_number
;
9870 int num_clobbers_to_add
= 0;
9875 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9876 we use to indicate that something didn't match. If we find such a
9877 thing, force rejection. */
9878 if (GET_CODE (pat
) == PARALLEL
)
9879 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9880 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9881 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9884 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9885 instruction for pattern recognition. */
9886 dummy_insn
= shallow_copy_rtx (insn
);
9887 PATTERN (dummy_insn
) = pat
;
9888 REG_NOTES (dummy_insn
) = 0;
9890 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9892 /* If it isn't, there is the possibility that we previously had an insn
9893 that clobbered some register as a side effect, but the combined
9894 insn doesn't need to do that. So try once more without the clobbers
9895 unless this represents an ASM insn. */
9897 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9898 && GET_CODE (pat
) == PARALLEL
)
9902 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9903 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9906 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9910 SUBST_INT (XVECLEN (pat
, 0), pos
);
9913 pat
= XVECEXP (pat
, 0, 0);
9915 PATTERN (dummy_insn
) = pat
;
9916 insn_code_number
= recog (pat
, dummy_insn
, &num_clobbers_to_add
);
9919 /* Recognize all noop sets, these will be killed by followup pass. */
9920 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
9921 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
9923 /* If we had any clobbers to add, make a new pattern than contains
9924 them. Then check to make sure that all of them are dead. */
9925 if (num_clobbers_to_add
)
9927 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9928 rtvec_alloc (GET_CODE (pat
) == PARALLEL
9930 + num_clobbers_to_add
)
9931 : num_clobbers_to_add
+ 1));
9933 if (GET_CODE (pat
) == PARALLEL
)
9934 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9935 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9937 XVECEXP (newpat
, 0, 0) = pat
;
9939 add_clobbers (newpat
, insn_code_number
);
9941 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9942 i
< XVECLEN (newpat
, 0); i
++)
9944 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9945 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9947 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9948 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9956 return insn_code_number
;
9959 /* Like gen_lowpart but for use by combine. In combine it is not possible
9960 to create any new pseudoregs. However, it is safe to create
9961 invalid memory addresses, because combine will try to recognize
9962 them and all they will do is make the combine attempt fail.
9964 If for some reason this cannot do its job, an rtx
9965 (clobber (const_int 0)) is returned.
9966 An insn containing that will not be recognized. */
9971 gen_lowpart_for_combine (enum machine_mode mode
, rtx x
)
9975 if (GET_MODE (x
) == mode
)
9978 /* Return identity if this is a CONST or symbolic
9981 && (GET_CODE (x
) == CONST
9982 || GET_CODE (x
) == SYMBOL_REF
9983 || GET_CODE (x
) == LABEL_REF
))
9986 /* We can only support MODE being wider than a word if X is a
9987 constant integer or has a mode the same size. */
9989 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9990 && ! ((GET_MODE (x
) == VOIDmode
9991 && (GET_CODE (x
) == CONST_INT
9992 || GET_CODE (x
) == CONST_DOUBLE
))
9993 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9994 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9996 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9997 won't know what to do. So we will strip off the SUBREG here and
9998 process normally. */
9999 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
10001 x
= SUBREG_REG (x
);
10002 if (GET_MODE (x
) == mode
)
10006 result
= gen_lowpart_common (mode
, x
);
10007 #ifdef CANNOT_CHANGE_MODE_CLASS
10009 && GET_CODE (result
) == SUBREG
10010 && GET_CODE (SUBREG_REG (result
)) == REG
10011 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
)
10012 bitmap_set_bit (&subregs_of_mode
, REGNO (SUBREG_REG (result
))
10014 + GET_MODE (result
));
10020 if (GET_CODE (x
) == MEM
)
10024 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10026 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
10027 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10029 /* If we want to refer to something bigger than the original memref,
10030 generate a perverse subreg instead. That will force a reload
10031 of the original memref X. */
10032 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
10033 return gen_rtx_SUBREG (mode
, x
, 0);
10035 if (WORDS_BIG_ENDIAN
)
10036 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
10037 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
10039 if (BYTES_BIG_ENDIAN
)
10041 /* Adjust the address so that the address-after-the-data is
10043 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
10044 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
10047 return adjust_address_nv (x
, mode
, offset
);
10050 /* If X is a comparison operator, rewrite it in a new mode. This
10051 probably won't match, but may allow further simplifications. */
10052 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
10053 return gen_rtx_fmt_ee (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
10055 /* If we couldn't simplify X any other way, just enclose it in a
10056 SUBREG. Normally, this SUBREG won't match, but some patterns may
10057 include an explicit SUBREG or we may simplify it further in combine. */
10062 enum machine_mode sub_mode
= GET_MODE (x
);
10064 offset
= subreg_lowpart_offset (mode
, sub_mode
);
10065 if (sub_mode
== VOIDmode
)
10067 sub_mode
= int_mode_for_mode (mode
);
10068 x
= gen_lowpart_common (sub_mode
, x
);
10070 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
10072 res
= simplify_gen_subreg (mode
, x
, sub_mode
, offset
);
10075 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
10079 /* These routines make binary and unary operations by first seeing if they
10080 fold; if not, a new expression is allocated. */
10083 gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
, rtx op1
)
10088 if (GET_CODE (op0
) == CLOBBER
)
10090 else if (GET_CODE (op1
) == CLOBBER
)
10093 if (GET_RTX_CLASS (code
) == 'c'
10094 && swap_commutative_operands_p (op0
, op1
))
10095 tem
= op0
, op0
= op1
, op1
= tem
;
10097 if (GET_RTX_CLASS (code
) == '<')
10099 enum machine_mode op_mode
= GET_MODE (op0
);
10101 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10102 just (REL_OP X Y). */
10103 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
10105 op1
= XEXP (op0
, 1);
10106 op0
= XEXP (op0
, 0);
10107 op_mode
= GET_MODE (op0
);
10110 if (op_mode
== VOIDmode
)
10111 op_mode
= GET_MODE (op1
);
10112 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
10115 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
10120 /* Put complex operands first and constants second. */
10121 if (GET_RTX_CLASS (code
) == 'c'
10122 && swap_commutative_operands_p (op0
, op1
))
10123 return gen_rtx_fmt_ee (code
, mode
, op1
, op0
);
10125 /* If we are turning off bits already known off in OP0, we need not do
10127 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
10128 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
10129 && (nonzero_bits (op0
, mode
) & ~INTVAL (op1
)) == 0)
10132 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
10135 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10136 comparison code that will be tested.
10138 The result is a possibly different comparison code to use. *POP0 and
10139 *POP1 may be updated.
10141 It is possible that we might detect that a comparison is either always
10142 true or always false. However, we do not perform general constant
10143 folding in combine, so this knowledge isn't useful. Such tautologies
10144 should have been detected earlier. Hence we ignore all such cases. */
10146 static enum rtx_code
10147 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
10153 enum machine_mode mode
, tmode
;
10155 /* Try a few ways of applying the same transformation to both operands. */
10158 #ifndef WORD_REGISTER_OPERATIONS
10159 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10160 so check specially. */
10161 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
10162 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
10163 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10164 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
10165 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
10166 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
10167 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
10168 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
10169 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10170 && XEXP (op0
, 1) == XEXP (op1
, 1)
10171 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10172 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
10173 && (INTVAL (XEXP (op0
, 1))
10174 == (GET_MODE_BITSIZE (GET_MODE (op0
))
10175 - (GET_MODE_BITSIZE
10176 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
10178 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
10179 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
10183 /* If both operands are the same constant shift, see if we can ignore the
10184 shift. We can if the shift is a rotate or if the bits shifted out of
10185 this shift are known to be zero for both inputs and if the type of
10186 comparison is compatible with the shift. */
10187 if (GET_CODE (op0
) == GET_CODE (op1
)
10188 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10189 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
10190 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
10191 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
10192 || (GET_CODE (op0
) == ASHIFTRT
10193 && (code
!= GTU
&& code
!= LTU
10194 && code
!= GEU
&& code
!= LEU
)))
10195 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10196 && INTVAL (XEXP (op0
, 1)) >= 0
10197 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10198 && XEXP (op0
, 1) == XEXP (op1
, 1))
10200 enum machine_mode mode
= GET_MODE (op0
);
10201 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10202 int shift_count
= INTVAL (XEXP (op0
, 1));
10204 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
10205 mask
&= (mask
>> shift_count
) << shift_count
;
10206 else if (GET_CODE (op0
) == ASHIFT
)
10207 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
10209 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
10210 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
10211 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
10216 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10217 SUBREGs are of the same mode, and, in both cases, the AND would
10218 be redundant if the comparison was done in the narrower mode,
10219 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10220 and the operand's possibly nonzero bits are 0xffffff01; in that case
10221 if we only care about QImode, we don't need the AND). This case
10222 occurs if the output mode of an scc insn is not SImode and
10223 STORE_FLAG_VALUE == 1 (e.g., the 386).
10225 Similarly, check for a case where the AND's are ZERO_EXTEND
10226 operations from some narrower mode even though a SUBREG is not
10229 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
10230 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10231 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
10233 rtx inner_op0
= XEXP (op0
, 0);
10234 rtx inner_op1
= XEXP (op1
, 0);
10235 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
10236 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
10239 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
10240 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
10241 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
10242 && (GET_MODE (SUBREG_REG (inner_op0
))
10243 == GET_MODE (SUBREG_REG (inner_op1
)))
10244 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
10245 <= HOST_BITS_PER_WIDE_INT
)
10246 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
10247 GET_MODE (SUBREG_REG (inner_op0
)))))
10248 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
10249 GET_MODE (SUBREG_REG (inner_op1
))))))
10251 op0
= SUBREG_REG (inner_op0
);
10252 op1
= SUBREG_REG (inner_op1
);
10254 /* The resulting comparison is always unsigned since we masked
10255 off the original sign bit. */
10256 code
= unsigned_condition (code
);
10262 for (tmode
= GET_CLASS_NARROWEST_MODE
10263 (GET_MODE_CLASS (GET_MODE (op0
)));
10264 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
10265 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
10267 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
10268 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
10269 code
= unsigned_condition (code
);
10278 /* If both operands are NOT, we can strip off the outer operation
10279 and adjust the comparison code for swapped operands; similarly for
10280 NEG, except that this must be an equality comparison. */
10281 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
10282 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
10283 && (code
== EQ
|| code
== NE
)))
10284 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
10290 /* If the first operand is a constant, swap the operands and adjust the
10291 comparison code appropriately, but don't do this if the second operand
10292 is already a constant integer. */
10293 if (swap_commutative_operands_p (op0
, op1
))
10295 tem
= op0
, op0
= op1
, op1
= tem
;
10296 code
= swap_condition (code
);
10299 /* We now enter a loop during which we will try to simplify the comparison.
10300 For the most part, we only are concerned with comparisons with zero,
10301 but some things may really be comparisons with zero but not start
10302 out looking that way. */
10304 while (GET_CODE (op1
) == CONST_INT
)
10306 enum machine_mode mode
= GET_MODE (op0
);
10307 unsigned int mode_width
= GET_MODE_BITSIZE (mode
);
10308 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
10309 int equality_comparison_p
;
10310 int sign_bit_comparison_p
;
10311 int unsigned_comparison_p
;
10312 HOST_WIDE_INT const_op
;
10314 /* We only want to handle integral modes. This catches VOIDmode,
10315 CCmode, and the floating-point modes. An exception is that we
10316 can handle VOIDmode if OP0 is a COMPARE or a comparison
10319 if (GET_MODE_CLASS (mode
) != MODE_INT
10320 && ! (mode
== VOIDmode
10321 && (GET_CODE (op0
) == COMPARE
10322 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
10325 /* Get the constant we are comparing against and turn off all bits
10326 not on in our mode. */
10327 const_op
= INTVAL (op1
);
10328 if (mode
!= VOIDmode
)
10329 const_op
= trunc_int_for_mode (const_op
, mode
);
10330 op1
= GEN_INT (const_op
);
10332 /* If we are comparing against a constant power of two and the value
10333 being compared can only have that single bit nonzero (e.g., it was
10334 `and'ed with that bit), we can replace this with a comparison
10337 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10338 || code
== LT
|| code
== LTU
)
10339 && mode_width
<= HOST_BITS_PER_WIDE_INT
10340 && exact_log2 (const_op
) >= 0
10341 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10343 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10344 op1
= const0_rtx
, const_op
= 0;
10347 /* Similarly, if we are comparing a value known to be either -1 or
10348 0 with -1, change it to the opposite comparison against zero. */
10351 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10352 || code
== GEU
|| code
== LTU
)
10353 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10355 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10356 op1
= const0_rtx
, const_op
= 0;
10359 /* Do some canonicalizations based on the comparison code. We prefer
10360 comparisons against zero and then prefer equality comparisons.
10361 If we can reduce the size of a constant, we will do that too. */
10366 /* < C is equivalent to <= (C - 1) */
10370 op1
= GEN_INT (const_op
);
10372 /* ... fall through to LE case below. */
10378 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10382 op1
= GEN_INT (const_op
);
10386 /* If we are doing a <= 0 comparison on a value known to have
10387 a zero sign bit, we can replace this with == 0. */
10388 else if (const_op
== 0
10389 && mode_width
<= HOST_BITS_PER_WIDE_INT
10390 && (nonzero_bits (op0
, mode
)
10391 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10396 /* >= C is equivalent to > (C - 1). */
10400 op1
= GEN_INT (const_op
);
10402 /* ... fall through to GT below. */
10408 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10412 op1
= GEN_INT (const_op
);
10416 /* If we are doing a > 0 comparison on a value known to have
10417 a zero sign bit, we can replace this with != 0. */
10418 else if (const_op
== 0
10419 && mode_width
<= HOST_BITS_PER_WIDE_INT
10420 && (nonzero_bits (op0
, mode
)
10421 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10426 /* < C is equivalent to <= (C - 1). */
10430 op1
= GEN_INT (const_op
);
10432 /* ... fall through ... */
10435 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10436 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10437 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10439 const_op
= 0, op1
= const0_rtx
;
10447 /* unsigned <= 0 is equivalent to == 0 */
10451 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10452 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10453 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10455 const_op
= 0, op1
= const0_rtx
;
10461 /* >= C is equivalent to < (C - 1). */
10465 op1
= GEN_INT (const_op
);
10467 /* ... fall through ... */
10470 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10471 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10472 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10474 const_op
= 0, op1
= const0_rtx
;
10482 /* unsigned > 0 is equivalent to != 0 */
10486 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10487 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10488 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10490 const_op
= 0, op1
= const0_rtx
;
10499 /* Compute some predicates to simplify code below. */
10501 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10502 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10503 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10506 /* If this is a sign bit comparison and we can do arithmetic in
10507 MODE, say that we will only be needing the sign bit of OP0. */
10508 if (sign_bit_comparison_p
10509 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10510 op0
= force_to_mode (op0
, mode
,
10512 << (GET_MODE_BITSIZE (mode
) - 1)),
10515 /* Now try cases based on the opcode of OP0. If none of the cases
10516 does a "continue", we exit this loop immediately after the
10519 switch (GET_CODE (op0
))
10522 /* If we are extracting a single bit from a variable position in
10523 a constant that has only a single bit set and are comparing it
10524 with zero, we can convert this into an equality comparison
10525 between the position and the location of the single bit. */
10527 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10528 && XEXP (op0
, 1) == const1_rtx
10529 && equality_comparison_p
&& const_op
== 0
10530 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10532 if (BITS_BIG_ENDIAN
)
10534 enum machine_mode new_mode
10535 = mode_for_extraction (EP_extzv
, 1);
10536 if (new_mode
== MAX_MACHINE_MODE
)
10537 i
= BITS_PER_WORD
- 1 - i
;
10541 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10545 op0
= XEXP (op0
, 2);
10549 /* Result is nonzero iff shift count is equal to I. */
10550 code
= reverse_condition (code
);
10554 /* ... fall through ... */
10557 tem
= expand_compound_operation (op0
);
10566 /* If testing for equality, we can take the NOT of the constant. */
10567 if (equality_comparison_p
10568 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10570 op0
= XEXP (op0
, 0);
10575 /* If just looking at the sign bit, reverse the sense of the
10577 if (sign_bit_comparison_p
)
10579 op0
= XEXP (op0
, 0);
10580 code
= (code
== GE
? LT
: GE
);
10586 /* If testing for equality, we can take the NEG of the constant. */
10587 if (equality_comparison_p
10588 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10590 op0
= XEXP (op0
, 0);
10595 /* The remaining cases only apply to comparisons with zero. */
10599 /* When X is ABS or is known positive,
10600 (neg X) is < 0 if and only if X != 0. */
10602 if (sign_bit_comparison_p
10603 && (GET_CODE (XEXP (op0
, 0)) == ABS
10604 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10605 && (nonzero_bits (XEXP (op0
, 0), mode
)
10606 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10608 op0
= XEXP (op0
, 0);
10609 code
= (code
== LT
? NE
: EQ
);
10613 /* If we have NEG of something whose two high-order bits are the
10614 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10615 if (num_sign_bit_copies (op0
, mode
) >= 2)
10617 op0
= XEXP (op0
, 0);
10618 code
= swap_condition (code
);
10624 /* If we are testing equality and our count is a constant, we
10625 can perform the inverse operation on our RHS. */
10626 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10627 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10628 op1
, XEXP (op0
, 1))) != 0)
10630 op0
= XEXP (op0
, 0);
10635 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10636 a particular bit. Convert it to an AND of a constant of that
10637 bit. This will be converted into a ZERO_EXTRACT. */
10638 if (const_op
== 0 && sign_bit_comparison_p
10639 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10640 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10642 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10645 - INTVAL (XEXP (op0
, 1)))));
10646 code
= (code
== LT
? NE
: EQ
);
10650 /* Fall through. */
10653 /* ABS is ignorable inside an equality comparison with zero. */
10654 if (const_op
== 0 && equality_comparison_p
)
10656 op0
= XEXP (op0
, 0);
10662 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10663 to (compare FOO CONST) if CONST fits in FOO's mode and we
10664 are either testing inequality or have an unsigned comparison
10665 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10666 if (! unsigned_comparison_p
10667 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10668 <= HOST_BITS_PER_WIDE_INT
)
10669 && ((unsigned HOST_WIDE_INT
) const_op
10670 < (((unsigned HOST_WIDE_INT
) 1
10671 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10673 op0
= XEXP (op0
, 0);
10679 /* Check for the case where we are comparing A - C1 with C2,
10680 both constants are smaller than 1/2 the maximum positive
10681 value in MODE, and the comparison is equality or unsigned.
10682 In that case, if A is either zero-extended to MODE or has
10683 sufficient sign bits so that the high-order bit in MODE
10684 is a copy of the sign in the inner mode, we can prove that it is
10685 safe to do the operation in the wider mode. This simplifies
10686 many range checks. */
10688 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10689 && subreg_lowpart_p (op0
)
10690 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10691 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10692 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10693 && (-INTVAL (XEXP (SUBREG_REG (op0
), 1))
10694 < (HOST_WIDE_INT
) (GET_MODE_MASK (mode
) / 2))
10695 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10696 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10697 GET_MODE (SUBREG_REG (op0
)))
10698 & ~GET_MODE_MASK (mode
))
10699 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10700 GET_MODE (SUBREG_REG (op0
)))
10702 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10703 - GET_MODE_BITSIZE (mode
)))))
10705 op0
= SUBREG_REG (op0
);
10709 /* If the inner mode is narrower and we are extracting the low part,
10710 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10711 if (subreg_lowpart_p (op0
)
10712 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10713 /* Fall through */ ;
10717 /* ... fall through ... */
10720 if ((unsigned_comparison_p
|| equality_comparison_p
)
10721 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10722 <= HOST_BITS_PER_WIDE_INT
)
10723 && ((unsigned HOST_WIDE_INT
) const_op
10724 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10726 op0
= XEXP (op0
, 0);
10732 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10733 this for equality comparisons due to pathological cases involving
10735 if (equality_comparison_p
10736 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10737 op1
, XEXP (op0
, 1))))
10739 op0
= XEXP (op0
, 0);
10744 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10745 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10746 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10748 op0
= XEXP (XEXP (op0
, 0), 0);
10749 code
= (code
== LT
? EQ
: NE
);
10755 /* We used to optimize signed comparisons against zero, but that
10756 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10757 arrive here as equality comparisons, or (GEU, LTU) are
10758 optimized away. No need to special-case them. */
10760 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10761 (eq B (minus A C)), whichever simplifies. We can only do
10762 this for equality comparisons due to pathological cases involving
10764 if (equality_comparison_p
10765 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10766 XEXP (op0
, 1), op1
)))
10768 op0
= XEXP (op0
, 0);
10773 if (equality_comparison_p
10774 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10775 XEXP (op0
, 0), op1
)))
10777 op0
= XEXP (op0
, 1);
10782 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10783 of bits in X minus 1, is one iff X > 0. */
10784 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10785 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10786 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (XEXP (op0
, 0), 1))
10788 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10790 op0
= XEXP (op0
, 1);
10791 code
= (code
== GE
? LE
: GT
);
10797 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10798 if C is zero or B is a constant. */
10799 if (equality_comparison_p
10800 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10801 XEXP (op0
, 1), op1
)))
10803 op0
= XEXP (op0
, 0);
10810 case UNEQ
: case LTGT
:
10811 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
10812 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
10813 case UNORDERED
: case ORDERED
:
10814 /* We can't do anything if OP0 is a condition code value, rather
10815 than an actual data value. */
10817 || CC0_P (XEXP (op0
, 0))
10818 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10821 /* Get the two operands being compared. */
10822 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10823 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10825 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10827 /* Check for the cases where we simply want the result of the
10828 earlier test or the opposite of that result. */
10829 if (code
== NE
|| code
== EQ
10830 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10831 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10832 && (STORE_FLAG_VALUE
10833 & (((HOST_WIDE_INT
) 1
10834 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10835 && (code
== LT
|| code
== GE
)))
10837 enum rtx_code new_code
;
10838 if (code
== LT
|| code
== NE
)
10839 new_code
= GET_CODE (op0
);
10841 new_code
= combine_reversed_comparison_code (op0
);
10843 if (new_code
!= UNKNOWN
)
10854 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10856 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10857 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10858 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10860 op0
= XEXP (op0
, 1);
10861 code
= (code
== GE
? GT
: LE
);
10867 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10868 will be converted to a ZERO_EXTRACT later. */
10869 if (const_op
== 0 && equality_comparison_p
10870 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10871 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10873 op0
= simplify_and_const_int
10874 (op0
, mode
, gen_rtx_LSHIFTRT (mode
,
10876 XEXP (XEXP (op0
, 0), 1)),
10877 (HOST_WIDE_INT
) 1);
10881 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10882 zero and X is a comparison and C1 and C2 describe only bits set
10883 in STORE_FLAG_VALUE, we can compare with X. */
10884 if (const_op
== 0 && equality_comparison_p
10885 && mode_width
<= HOST_BITS_PER_WIDE_INT
10886 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10887 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10888 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10889 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10890 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10892 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10893 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10894 if ((~STORE_FLAG_VALUE
& mask
) == 0
10895 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10896 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10897 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10899 op0
= XEXP (XEXP (op0
, 0), 0);
10904 /* If we are doing an equality comparison of an AND of a bit equal
10905 to the sign bit, replace this with a LT or GE comparison of
10906 the underlying value. */
10907 if (equality_comparison_p
10909 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10910 && mode_width
<= HOST_BITS_PER_WIDE_INT
10911 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10912 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10914 op0
= XEXP (op0
, 0);
10915 code
= (code
== EQ
? GE
: LT
);
10919 /* If this AND operation is really a ZERO_EXTEND from a narrower
10920 mode, the constant fits within that mode, and this is either an
10921 equality or unsigned comparison, try to do this comparison in
10922 the narrower mode. */
10923 if ((equality_comparison_p
|| unsigned_comparison_p
)
10924 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10925 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10926 & GET_MODE_MASK (mode
))
10928 && const_op
>> i
== 0
10929 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10931 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10935 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10936 fits in both M1 and M2 and the SUBREG is either paradoxical
10937 or represents the low part, permute the SUBREG and the AND
10939 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
)
10941 unsigned HOST_WIDE_INT c1
;
10942 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
10943 /* Require an integral mode, to avoid creating something like
10945 if (SCALAR_INT_MODE_P (tmode
)
10946 /* It is unsafe to commute the AND into the SUBREG if the
10947 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10948 not defined. As originally written the upper bits
10949 have a defined value due to the AND operation.
10950 However, if we commute the AND inside the SUBREG then
10951 they no longer have defined values and the meaning of
10952 the code has been changed. */
10954 #ifdef WORD_REGISTER_OPERATIONS
10955 || (mode_width
> GET_MODE_BITSIZE (tmode
)
10956 && mode_width
<= BITS_PER_WORD
)
10958 || (mode_width
<= GET_MODE_BITSIZE (tmode
)
10959 && subreg_lowpart_p (XEXP (op0
, 0))))
10960 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10961 && mode_width
<= HOST_BITS_PER_WIDE_INT
10962 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
10963 && ((c1
= INTVAL (XEXP (op0
, 1))) & ~mask
) == 0
10964 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
10966 && c1
!= GET_MODE_MASK (tmode
))
10968 op0
= gen_binary (AND
, tmode
,
10969 SUBREG_REG (XEXP (op0
, 0)),
10970 gen_int_mode (c1
, tmode
));
10971 op0
= gen_lowpart_for_combine (mode
, op0
);
10976 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10977 if (const_op
== 0 && equality_comparison_p
10978 && XEXP (op0
, 1) == const1_rtx
10979 && GET_CODE (XEXP (op0
, 0)) == NOT
)
10981 op0
= simplify_and_const_int
10982 (NULL_RTX
, mode
, XEXP (XEXP (op0
, 0), 0), (HOST_WIDE_INT
) 1);
10983 code
= (code
== NE
? EQ
: NE
);
10987 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10988 (eq (and (lshiftrt X) 1) 0).
10989 Also handle the case where (not X) is expressed using xor. */
10990 if (const_op
== 0 && equality_comparison_p
10991 && XEXP (op0
, 1) == const1_rtx
10992 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
10994 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
10995 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
10997 if (GET_CODE (shift_op
) == NOT
10998 || (GET_CODE (shift_op
) == XOR
10999 && GET_CODE (XEXP (shift_op
, 1)) == CONST_INT
11000 && GET_CODE (shift_count
) == CONST_INT
11001 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
11002 && (INTVAL (XEXP (shift_op
, 1))
11003 == (HOST_WIDE_INT
) 1 << INTVAL (shift_count
))))
11005 op0
= simplify_and_const_int
11007 gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
),
11008 (HOST_WIDE_INT
) 1);
11009 code
= (code
== NE
? EQ
: NE
);
11016 /* If we have (compare (ashift FOO N) (const_int C)) and
11017 the high order N bits of FOO (N+1 if an inequality comparison)
11018 are known to be zero, we can do this by comparing FOO with C
11019 shifted right N bits so long as the low-order N bits of C are
11021 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11022 && INTVAL (XEXP (op0
, 1)) >= 0
11023 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
11024 < HOST_BITS_PER_WIDE_INT
)
11026 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
11027 && mode_width
<= HOST_BITS_PER_WIDE_INT
11028 && (nonzero_bits (XEXP (op0
, 0), mode
)
11029 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
11030 + ! equality_comparison_p
))) == 0)
11032 /* We must perform a logical shift, not an arithmetic one,
11033 as we want the top N bits of C to be zero. */
11034 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
11036 temp
>>= INTVAL (XEXP (op0
, 1));
11037 op1
= gen_int_mode (temp
, mode
);
11038 op0
= XEXP (op0
, 0);
11042 /* If we are doing a sign bit comparison, it means we are testing
11043 a particular bit. Convert it to the appropriate AND. */
11044 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
11045 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11047 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11050 - INTVAL (XEXP (op0
, 1)))));
11051 code
= (code
== LT
? NE
: EQ
);
11055 /* If this an equality comparison with zero and we are shifting
11056 the low bit to the sign bit, we can convert this to an AND of the
11058 if (const_op
== 0 && equality_comparison_p
11059 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11060 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11063 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11064 (HOST_WIDE_INT
) 1);
11070 /* If this is an equality comparison with zero, we can do this
11071 as a logical shift, which might be much simpler. */
11072 if (equality_comparison_p
&& const_op
== 0
11073 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
11075 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
11077 INTVAL (XEXP (op0
, 1)));
11081 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11082 do the comparison in a narrower mode. */
11083 if (! unsigned_comparison_p
11084 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11085 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11086 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11087 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11088 MODE_INT
, 1)) != BLKmode
11089 && (((unsigned HOST_WIDE_INT
) const_op
11090 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11091 <= GET_MODE_MASK (tmode
)))
11093 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
11097 /* Likewise if OP0 is a PLUS of a sign extension with a
11098 constant, which is usually represented with the PLUS
11099 between the shifts. */
11100 if (! unsigned_comparison_p
11101 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11102 && GET_CODE (XEXP (op0
, 0)) == PLUS
11103 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
11104 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
11105 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
11106 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
11107 MODE_INT
, 1)) != BLKmode
11108 && (((unsigned HOST_WIDE_INT
) const_op
11109 + (GET_MODE_MASK (tmode
) >> 1) + 1)
11110 <= GET_MODE_MASK (tmode
)))
11112 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
11113 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
11114 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
11117 op0
= gen_binary (PLUS
, tmode
,
11118 gen_lowpart_for_combine (tmode
, inner
),
11123 /* ... fall through ... */
11125 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11126 the low order N bits of FOO are known to be zero, we can do this
11127 by comparing FOO with C shifted left N bits so long as no
11128 overflow occurs. */
11129 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
11130 && INTVAL (XEXP (op0
, 1)) >= 0
11131 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11132 && mode_width
<= HOST_BITS_PER_WIDE_INT
11133 && (nonzero_bits (XEXP (op0
, 0), mode
)
11134 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
11135 && (((unsigned HOST_WIDE_INT
) const_op
11136 + (GET_CODE (op0
) != LSHIFTRT
11137 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
11140 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
11142 /* If the shift was logical, then we must make the condition
11144 if (GET_CODE (op0
) == LSHIFTRT
)
11145 code
= unsigned_condition (code
);
11147 const_op
<<= INTVAL (XEXP (op0
, 1));
11148 op1
= GEN_INT (const_op
);
11149 op0
= XEXP (op0
, 0);
11153 /* If we are using this shift to extract just the sign bit, we
11154 can replace this with an LT or GE comparison. */
11156 && (equality_comparison_p
|| sign_bit_comparison_p
)
11157 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
11158 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
11161 op0
= XEXP (op0
, 0);
11162 code
= (code
== NE
|| code
== GT
? LT
: GE
);
11174 /* Now make any compound operations involved in this comparison. Then,
11175 check for an outmost SUBREG on OP0 that is not doing anything or is
11176 paradoxical. The latter transformation must only be performed when
11177 it is known that the "extra" bits will be the same in op0 and op1 or
11178 that they don't matter. There are three cases to consider:
11180 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11181 care bits and we can assume they have any convenient value. So
11182 making the transformation is safe.
11184 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11185 In this case the upper bits of op0 are undefined. We should not make
11186 the simplification in that case as we do not know the contents of
11189 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11190 NIL. In that case we know those bits are zeros or ones. We must
11191 also be sure that they are the same as the upper bits of op1.
11193 We can never remove a SUBREG for a non-equality comparison because
11194 the sign bit is in a different place in the underlying object. */
11196 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
11197 op1
= make_compound_operation (op1
, SET
);
11199 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
11200 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
11201 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
11202 && (code
== NE
|| code
== EQ
))
11204 if (GET_MODE_SIZE (GET_MODE (op0
))
11205 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))
11207 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11209 if (GET_CODE (SUBREG_REG (op0
)) == REG
)
11211 op0
= SUBREG_REG (op0
);
11212 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
11215 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
11216 <= HOST_BITS_PER_WIDE_INT
)
11217 && (nonzero_bits (SUBREG_REG (op0
),
11218 GET_MODE (SUBREG_REG (op0
)))
11219 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11221 tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)), op1
);
11223 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
11224 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
11225 op0
= SUBREG_REG (op0
), op1
= tem
;
11229 /* We now do the opposite procedure: Some machines don't have compare
11230 insns in all modes. If OP0's mode is an integer mode smaller than a
11231 word and we can't do a compare in that mode, see if there is a larger
11232 mode for which we can do the compare. There are a number of cases in
11233 which we can use the wider mode. */
11235 mode
= GET_MODE (op0
);
11236 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
11237 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
11238 && ! have_insn_for (COMPARE
, mode
))
11239 for (tmode
= GET_MODE_WIDER_MODE (mode
);
11241 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
11242 tmode
= GET_MODE_WIDER_MODE (tmode
))
11243 if (have_insn_for (COMPARE
, tmode
))
11247 /* If the only nonzero bits in OP0 and OP1 are those in the
11248 narrower mode and this is an equality or unsigned comparison,
11249 we can use the wider mode. Similarly for sign-extended
11250 values, in which case it is true for all comparisons. */
11251 zero_extended
= ((code
== EQ
|| code
== NE
11252 || code
== GEU
|| code
== GTU
11253 || code
== LEU
|| code
== LTU
)
11254 && (nonzero_bits (op0
, tmode
)
11255 & ~GET_MODE_MASK (mode
)) == 0
11256 && ((GET_CODE (op1
) == CONST_INT
11257 || (nonzero_bits (op1
, tmode
)
11258 & ~GET_MODE_MASK (mode
)) == 0)));
11261 || ((num_sign_bit_copies (op0
, tmode
)
11262 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11263 - GET_MODE_BITSIZE (mode
)))
11264 && (num_sign_bit_copies (op1
, tmode
)
11265 > (unsigned int) (GET_MODE_BITSIZE (tmode
)
11266 - GET_MODE_BITSIZE (mode
)))))
11268 /* If OP0 is an AND and we don't have an AND in MODE either,
11269 make a new AND in the proper mode. */
11270 if (GET_CODE (op0
) == AND
11271 && !have_insn_for (AND
, mode
))
11272 op0
= gen_binary (AND
, tmode
,
11273 gen_lowpart_for_combine (tmode
,
11275 gen_lowpart_for_combine (tmode
,
11278 op0
= gen_lowpart_for_combine (tmode
, op0
);
11279 if (zero_extended
&& GET_CODE (op1
) == CONST_INT
)
11280 op1
= GEN_INT (INTVAL (op1
) & GET_MODE_MASK (mode
));
11281 op1
= gen_lowpart_for_combine (tmode
, op1
);
11285 /* If this is a test for negative, we can make an explicit
11286 test of the sign bit. */
11288 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
11289 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11291 op0
= gen_binary (AND
, tmode
,
11292 gen_lowpart_for_combine (tmode
, op0
),
11293 GEN_INT ((HOST_WIDE_INT
) 1
11294 << (GET_MODE_BITSIZE (mode
) - 1)));
11295 code
= (code
== LT
) ? NE
: EQ
;
11300 #ifdef CANONICALIZE_COMPARISON
11301 /* If this machine only supports a subset of valid comparisons, see if we
11302 can convert an unsupported one into a supported one. */
11303 CANONICALIZE_COMPARISON (code
, op0
, op1
);
11312 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11313 searching backward. */
11314 static enum rtx_code
11315 combine_reversed_comparison_code (rtx exp
)
11317 enum rtx_code code1
= reversed_comparison_code (exp
, NULL
);
11320 if (code1
!= UNKNOWN
11321 || GET_MODE_CLASS (GET_MODE (XEXP (exp
, 0))) != MODE_CC
)
11323 /* Otherwise try and find where the condition codes were last set and
11325 x
= get_last_value (XEXP (exp
, 0));
11326 if (!x
|| GET_CODE (x
) != COMPARE
)
11328 return reversed_comparison_code_parts (GET_CODE (exp
),
11329 XEXP (x
, 0), XEXP (x
, 1), NULL
);
11332 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11333 Return NULL_RTX in case we fail to do the reversal. */
11335 reversed_comparison (rtx exp
, enum machine_mode mode
, rtx op0
, rtx op1
)
11337 enum rtx_code reversed_code
= combine_reversed_comparison_code (exp
);
11338 if (reversed_code
== UNKNOWN
)
11341 return gen_binary (reversed_code
, mode
, op0
, op1
);
11344 /* Utility function for following routine. Called when X is part of a value
11345 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11346 for each register mentioned. Similar to mention_regs in cse.c */
11349 update_table_tick (rtx x
)
11351 enum rtx_code code
= GET_CODE (x
);
11352 const char *fmt
= GET_RTX_FORMAT (code
);
11357 unsigned int regno
= REGNO (x
);
11358 unsigned int endregno
11359 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11360 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11363 for (r
= regno
; r
< endregno
; r
++)
11364 reg_last_set_table_tick
[r
] = label_tick
;
11369 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11370 /* Note that we can't have an "E" in values stored; see
11371 get_last_value_validate. */
11374 /* Check for identical subexpressions. If x contains
11375 identical subexpression we only have to traverse one of
11378 && (GET_RTX_CLASS (code
) == '2'
11379 || GET_RTX_CLASS (code
) == 'c'))
11381 /* Note that at this point x1 has already been
11383 rtx x0
= XEXP (x
, 0);
11384 rtx x1
= XEXP (x
, 1);
11386 /* If x0 and x1 are identical then there is no need to
11391 /* If x0 is identical to a subexpression of x1 then while
11392 processing x1, x0 has already been processed. Thus we
11393 are done with x. */
11394 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11395 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11396 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11399 /* If x1 is identical to a subexpression of x0 then we
11400 still have to process the rest of x0. */
11401 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11402 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11403 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11405 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
11410 update_table_tick (XEXP (x
, i
));
11414 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11415 are saying that the register is clobbered and we no longer know its
11416 value. If INSN is zero, don't update reg_last_set; this is only permitted
11417 with VALUE also zero and is used to invalidate the register. */
11420 record_value_for_reg (rtx reg
, rtx insn
, rtx value
)
11422 unsigned int regno
= REGNO (reg
);
11423 unsigned int endregno
11424 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11425 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
11428 /* If VALUE contains REG and we have a previous value for REG, substitute
11429 the previous value. */
11430 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
11434 /* Set things up so get_last_value is allowed to see anything set up to
11436 subst_low_cuid
= INSN_CUID (insn
);
11437 tem
= get_last_value (reg
);
11439 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11440 it isn't going to be useful and will take a lot of time to process,
11441 so just use the CLOBBER. */
11445 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
11446 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
11447 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
11448 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11449 tem
= XEXP (tem
, 0);
11451 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11455 /* For each register modified, show we don't know its value, that
11456 we don't know about its bitwise content, that its value has been
11457 updated, and that we don't know the location of the death of the
11459 for (i
= regno
; i
< endregno
; i
++)
11462 reg_last_set
[i
] = insn
;
11464 reg_last_set_value
[i
] = 0;
11465 reg_last_set_mode
[i
] = 0;
11466 reg_last_set_nonzero_bits
[i
] = 0;
11467 reg_last_set_sign_bit_copies
[i
] = 0;
11468 reg_last_death
[i
] = 0;
11471 /* Mark registers that are being referenced in this value. */
11473 update_table_tick (value
);
11475 /* Now update the status of each register being set.
11476 If someone is using this register in this block, set this register
11477 to invalid since we will get confused between the two lives in this
11478 basic block. This makes using this register always invalid. In cse, we
11479 scan the table to invalidate all entries using this register, but this
11480 is too much work for us. */
11482 for (i
= regno
; i
< endregno
; i
++)
11484 reg_last_set_label
[i
] = label_tick
;
11485 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11486 reg_last_set_invalid
[i
] = 1;
11488 reg_last_set_invalid
[i
] = 0;
11491 /* The value being assigned might refer to X (like in "x++;"). In that
11492 case, we must replace it with (clobber (const_int 0)) to prevent
11494 if (value
&& ! get_last_value_validate (&value
, insn
,
11495 reg_last_set_label
[regno
], 0))
11497 value
= copy_rtx (value
);
11498 if (! get_last_value_validate (&value
, insn
,
11499 reg_last_set_label
[regno
], 1))
11503 /* For the main register being modified, update the value, the mode, the
11504 nonzero bits, and the number of sign bit copies. */
11506 reg_last_set_value
[regno
] = value
;
11510 enum machine_mode mode
= GET_MODE (reg
);
11511 subst_low_cuid
= INSN_CUID (insn
);
11512 reg_last_set_mode
[regno
] = mode
;
11513 if (GET_MODE_CLASS (mode
) == MODE_INT
11514 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
11515 mode
= nonzero_bits_mode
;
11516 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, mode
);
11517 reg_last_set_sign_bit_copies
[regno
]
11518 = num_sign_bit_copies (value
, GET_MODE (reg
));
11522 /* Called via note_stores from record_dead_and_set_regs to handle one
11523 SET or CLOBBER in an insn. DATA is the instruction in which the
11524 set is occurring. */
11527 record_dead_and_set_regs_1 (rtx dest
, rtx setter
, void *data
)
11529 rtx record_dead_insn
= (rtx
) data
;
11531 if (GET_CODE (dest
) == SUBREG
)
11532 dest
= SUBREG_REG (dest
);
11534 if (GET_CODE (dest
) == REG
)
11536 /* If we are setting the whole register, we know its value. Otherwise
11537 show that we don't know the value. We can handle SUBREG in
11539 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11540 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11541 else if (GET_CODE (setter
) == SET
11542 && GET_CODE (SET_DEST (setter
)) == SUBREG
11543 && SUBREG_REG (SET_DEST (setter
)) == dest
11544 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11545 && subreg_lowpart_p (SET_DEST (setter
)))
11546 record_value_for_reg (dest
, record_dead_insn
,
11547 gen_lowpart_for_combine (GET_MODE (dest
),
11548 SET_SRC (setter
)));
11550 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11552 else if (GET_CODE (dest
) == MEM
11553 /* Ignore pushes, they clobber nothing. */
11554 && ! push_operand (dest
, GET_MODE (dest
)))
11555 mem_last_set
= INSN_CUID (record_dead_insn
);
11558 /* Update the records of when each REG was most recently set or killed
11559 for the things done by INSN. This is the last thing done in processing
11560 INSN in the combiner loop.
11562 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11563 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11564 and also the similar information mem_last_set (which insn most recently
11565 modified memory) and last_call_cuid (which insn was the most recent
11566 subroutine call). */
11569 record_dead_and_set_regs (rtx insn
)
11574 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11576 if (REG_NOTE_KIND (link
) == REG_DEAD
11577 && GET_CODE (XEXP (link
, 0)) == REG
)
11579 unsigned int regno
= REGNO (XEXP (link
, 0));
11580 unsigned int endregno
11581 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11582 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11585 for (i
= regno
; i
< endregno
; i
++)
11586 reg_last_death
[i
] = insn
;
11588 else if (REG_NOTE_KIND (link
) == REG_INC
)
11589 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11592 if (GET_CODE (insn
) == CALL_INSN
)
11594 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11595 if (TEST_HARD_REG_BIT (regs_invalidated_by_call
, i
))
11597 reg_last_set_value
[i
] = 0;
11598 reg_last_set_mode
[i
] = 0;
11599 reg_last_set_nonzero_bits
[i
] = 0;
11600 reg_last_set_sign_bit_copies
[i
] = 0;
11601 reg_last_death
[i
] = 0;
11604 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11606 /* Don't bother recording what this insn does. It might set the
11607 return value register, but we can't combine into a call
11608 pattern anyway, so there's no point trying (and it may cause
11609 a crash, if e.g. we wind up asking for last_set_value of a
11610 SUBREG of the return value register). */
11614 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11617 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11618 register present in the SUBREG, so for each such SUBREG go back and
11619 adjust nonzero and sign bit information of the registers that are
11620 known to have some zero/sign bits set.
11622 This is needed because when combine blows the SUBREGs away, the
11623 information on zero/sign bits is lost and further combines can be
11624 missed because of that. */
11627 record_promoted_value (rtx insn
, rtx subreg
)
11630 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
11631 enum machine_mode mode
= GET_MODE (subreg
);
11633 if (GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
)
11636 for (links
= LOG_LINKS (insn
); links
;)
11638 insn
= XEXP (links
, 0);
11639 set
= single_set (insn
);
11641 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11642 || REGNO (SET_DEST (set
)) != regno
11643 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11645 links
= XEXP (links
, 1);
11649 if (reg_last_set
[regno
] == insn
)
11651 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
) > 0)
11652 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11655 if (GET_CODE (SET_SRC (set
)) == REG
)
11657 regno
= REGNO (SET_SRC (set
));
11658 links
= LOG_LINKS (insn
);
11665 /* Scan X for promoted SUBREGs. For each one found,
11666 note what it implies to the registers used in it. */
11669 check_promoted_subreg (rtx insn
, rtx x
)
11671 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11672 && GET_CODE (SUBREG_REG (x
)) == REG
)
11673 record_promoted_value (insn
, x
);
11676 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11679 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11683 check_promoted_subreg (insn
, XEXP (x
, i
));
11687 if (XVEC (x
, i
) != 0)
11688 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11689 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11695 /* Utility routine for the following function. Verify that all the registers
11696 mentioned in *LOC are valid when *LOC was part of a value set when
11697 label_tick == TICK. Return 0 if some are not.
11699 If REPLACE is nonzero, replace the invalid reference with
11700 (clobber (const_int 0)) and return 1. This replacement is useful because
11701 we often can get useful information about the form of a value (e.g., if
11702 it was produced by a shift that always produces -1 or 0) even though
11703 we don't know exactly what registers it was produced from. */
11706 get_last_value_validate (rtx
*loc
, rtx insn
, int tick
, int replace
)
11709 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11710 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11713 if (GET_CODE (x
) == REG
)
11715 unsigned int regno
= REGNO (x
);
11716 unsigned int endregno
11717 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11718 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11721 for (j
= regno
; j
< endregno
; j
++)
11722 if (reg_last_set_invalid
[j
]
11723 /* If this is a pseudo-register that was only set once and not
11724 live at the beginning of the function, it is always valid. */
11725 || (! (regno
>= FIRST_PSEUDO_REGISTER
11726 && REG_N_SETS (regno
) == 1
11727 && (! REGNO_REG_SET_P
11728 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))
11729 && reg_last_set_label
[j
] > tick
))
11732 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11738 /* If this is a memory reference, make sure that there were
11739 no stores after it that might have clobbered the value. We don't
11740 have alias info, so we assume any store invalidates it. */
11741 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11742 && INSN_CUID (insn
) <= mem_last_set
)
11745 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11749 for (i
= 0; i
< len
; i
++)
11753 /* Check for identical subexpressions. If x contains
11754 identical subexpression we only have to traverse one of
11757 && (GET_RTX_CLASS (GET_CODE (x
)) == '2'
11758 || GET_RTX_CLASS (GET_CODE (x
)) == 'c'))
11760 /* Note that at this point x0 has already been checked
11761 and found valid. */
11762 rtx x0
= XEXP (x
, 0);
11763 rtx x1
= XEXP (x
, 1);
11765 /* If x0 and x1 are identical then x is also valid. */
11769 /* If x1 is identical to a subexpression of x0 then
11770 while checking x0, x1 has already been checked. Thus
11771 it is valid and so as x. */
11772 if ((GET_RTX_CLASS (GET_CODE (x0
)) == '2'
11773 || GET_RTX_CLASS (GET_CODE (x0
)) == 'c')
11774 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
11777 /* If x0 is identical to a subexpression of x1 then x is
11778 valid iff the rest of x1 is valid. */
11779 if ((GET_RTX_CLASS (GET_CODE (x1
)) == '2'
11780 || GET_RTX_CLASS (GET_CODE (x1
)) == 'c')
11781 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
11783 get_last_value_validate (&XEXP (x1
,
11784 x0
== XEXP (x1
, 0) ? 1 : 0),
11785 insn
, tick
, replace
);
11788 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
11792 /* Don't bother with these. They shouldn't occur anyway. */
11793 else if (fmt
[i
] == 'E')
11797 /* If we haven't found a reason for it to be invalid, it is valid. */
11801 /* Get the last value assigned to X, if known. Some registers
11802 in the value may be replaced with (clobber (const_int 0)) if their value
11803 is known longer known reliably. */
11806 get_last_value (rtx x
)
11808 unsigned int regno
;
11811 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11812 then convert it to the desired mode. If this is a paradoxical SUBREG,
11813 we cannot predict what values the "extra" bits might have. */
11814 if (GET_CODE (x
) == SUBREG
11815 && subreg_lowpart_p (x
)
11816 && (GET_MODE_SIZE (GET_MODE (x
))
11817 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11818 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11819 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11821 if (GET_CODE (x
) != REG
)
11825 value
= reg_last_set_value
[regno
];
11827 /* If we don't have a value, or if it isn't for this basic block and
11828 it's either a hard register, set more than once, or it's a live
11829 at the beginning of the function, return 0.
11831 Because if it's not live at the beginning of the function then the reg
11832 is always set before being used (is never used without being set).
11833 And, if it's set only once, and it's always set before use, then all
11834 uses must have the same last value, even if it's not from this basic
11838 || (reg_last_set_label
[regno
] != label_tick
11839 && (regno
< FIRST_PSEUDO_REGISTER
11840 || REG_N_SETS (regno
) != 1
11841 || (REGNO_REG_SET_P
11842 (ENTRY_BLOCK_PTR
->next_bb
->global_live_at_start
, regno
)))))
11845 /* If the value was set in a later insn than the ones we are processing,
11846 we can't use it even if the register was only set once. */
11847 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11850 /* If the value has all its registers valid, return it. */
11851 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11852 reg_last_set_label
[regno
], 0))
11855 /* Otherwise, make a copy and replace any invalid register with
11856 (clobber (const_int 0)). If that fails for some reason, return 0. */
11858 value
= copy_rtx (value
);
11859 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11860 reg_last_set_label
[regno
], 1))
11866 /* Return nonzero if expression X refers to a REG or to memory
11867 that is set in an instruction more recent than FROM_CUID. */
11870 use_crosses_set_p (rtx x
, int from_cuid
)
11874 enum rtx_code code
= GET_CODE (x
);
11878 unsigned int regno
= REGNO (x
);
11879 unsigned endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11880 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11882 #ifdef PUSH_ROUNDING
11883 /* Don't allow uses of the stack pointer to be moved,
11884 because we don't know whether the move crosses a push insn. */
11885 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
11888 for (; regno
< endreg
; regno
++)
11889 if (reg_last_set
[regno
]
11890 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11895 if (code
== MEM
&& mem_last_set
> from_cuid
)
11898 fmt
= GET_RTX_FORMAT (code
);
11900 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11905 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11906 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11909 else if (fmt
[i
] == 'e'
11910 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11916 /* Define three variables used for communication between the following
11919 static unsigned int reg_dead_regno
, reg_dead_endregno
;
11920 static int reg_dead_flag
;
11922 /* Function called via note_stores from reg_dead_at_p.
11924 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11925 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11928 reg_dead_at_p_1 (rtx dest
, rtx x
, void *data ATTRIBUTE_UNUSED
)
11930 unsigned int regno
, endregno
;
11932 if (GET_CODE (dest
) != REG
)
11935 regno
= REGNO (dest
);
11936 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11937 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11939 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11940 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11943 /* Return nonzero if REG is known to be dead at INSN.
11945 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11946 referencing REG, it is dead. If we hit a SET referencing REG, it is
11947 live. Otherwise, see if it is live or dead at the start of the basic
11948 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11949 must be assumed to be always live. */
11952 reg_dead_at_p (rtx reg
, rtx insn
)
11957 /* Set variables for reg_dead_at_p_1. */
11958 reg_dead_regno
= REGNO (reg
);
11959 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11960 ? HARD_REGNO_NREGS (reg_dead_regno
,
11966 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11967 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11969 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11970 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11974 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11975 beginning of function. */
11976 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11977 insn
= prev_nonnote_insn (insn
))
11979 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11981 return reg_dead_flag
== 1 ? 1 : 0;
11983 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11987 /* Get the basic block that we were in. */
11989 block
= ENTRY_BLOCK_PTR
->next_bb
;
11992 FOR_EACH_BB (block
)
11993 if (insn
== BB_HEAD (block
))
11996 if (block
== EXIT_BLOCK_PTR
)
12000 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
12001 if (REGNO_REG_SET_P (block
->global_live_at_start
, i
))
12007 /* Note hard registers in X that are used. This code is similar to
12008 that in flow.c, but much simpler since we don't care about pseudos. */
12011 mark_used_regs_combine (rtx x
)
12013 RTX_CODE code
= GET_CODE (x
);
12014 unsigned int regno
;
12027 case ADDR_DIFF_VEC
:
12030 /* CC0 must die in the insn after it is set, so we don't need to take
12031 special note of it here. */
12037 /* If we are clobbering a MEM, mark any hard registers inside the
12038 address as used. */
12039 if (GET_CODE (XEXP (x
, 0)) == MEM
)
12040 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
12045 /* A hard reg in a wide mode may really be multiple registers.
12046 If so, mark all of them just like the first. */
12047 if (regno
< FIRST_PSEUDO_REGISTER
)
12049 unsigned int endregno
, r
;
12051 /* None of this applies to the stack, frame or arg pointers. */
12052 if (regno
== STACK_POINTER_REGNUM
12053 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12054 || regno
== HARD_FRAME_POINTER_REGNUM
12056 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12057 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
12059 || regno
== FRAME_POINTER_REGNUM
)
12062 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12063 for (r
= regno
; r
< endregno
; r
++)
12064 SET_HARD_REG_BIT (newpat_used_regs
, r
);
12070 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12072 rtx testreg
= SET_DEST (x
);
12074 while (GET_CODE (testreg
) == SUBREG
12075 || GET_CODE (testreg
) == ZERO_EXTRACT
12076 || GET_CODE (testreg
) == SIGN_EXTRACT
12077 || GET_CODE (testreg
) == STRICT_LOW_PART
)
12078 testreg
= XEXP (testreg
, 0);
12080 if (GET_CODE (testreg
) == MEM
)
12081 mark_used_regs_combine (XEXP (testreg
, 0));
12083 mark_used_regs_combine (SET_SRC (x
));
12091 /* Recursively scan the operands of this expression. */
12094 const char *fmt
= GET_RTX_FORMAT (code
);
12096 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12099 mark_used_regs_combine (XEXP (x
, i
));
12100 else if (fmt
[i
] == 'E')
12104 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12105 mark_used_regs_combine (XVECEXP (x
, i
, j
));
12111 /* Remove register number REGNO from the dead registers list of INSN.
12113 Return the note used to record the death, if there was one. */
12116 remove_death (unsigned int regno
, rtx insn
)
12118 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
12122 REG_N_DEATHS (regno
)--;
12123 remove_note (insn
, note
);
12129 /* For each register (hardware or pseudo) used within expression X, if its
12130 death is in an instruction with cuid between FROM_CUID (inclusive) and
12131 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12132 list headed by PNOTES.
12134 That said, don't move registers killed by maybe_kill_insn.
12136 This is done when X is being merged by combination into TO_INSN. These
12137 notes will then be distributed as needed. */
12140 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_cuid
, rtx to_insn
,
12145 enum rtx_code code
= GET_CODE (x
);
12149 unsigned int regno
= REGNO (x
);
12150 rtx where_dead
= reg_last_death
[regno
];
12151 rtx before_dead
, after_dead
;
12153 /* Don't move the register if it gets killed in between from and to. */
12154 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
12155 && ! reg_referenced_p (x
, maybe_kill_insn
))
12158 /* WHERE_DEAD could be a USE insn made by combine, so first we
12159 make sure that we have insns with valid INSN_CUID values. */
12160 before_dead
= where_dead
;
12161 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
12162 before_dead
= PREV_INSN (before_dead
);
12164 after_dead
= where_dead
;
12165 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
12166 after_dead
= NEXT_INSN (after_dead
);
12168 if (before_dead
&& after_dead
12169 && INSN_CUID (before_dead
) >= from_cuid
12170 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
12171 || (where_dead
!= after_dead
12172 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
12174 rtx note
= remove_death (regno
, where_dead
);
12176 /* It is possible for the call above to return 0. This can occur
12177 when reg_last_death points to I2 or I1 that we combined with.
12178 In that case make a new note.
12180 We must also check for the case where X is a hard register
12181 and NOTE is a death note for a range of hard registers
12182 including X. In that case, we must put REG_DEAD notes for
12183 the remaining registers in place of NOTE. */
12185 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
12186 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12187 > GET_MODE_SIZE (GET_MODE (x
))))
12189 unsigned int deadregno
= REGNO (XEXP (note
, 0));
12190 unsigned int deadend
12191 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
12192 GET_MODE (XEXP (note
, 0))));
12193 unsigned int ourend
12194 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12197 for (i
= deadregno
; i
< deadend
; i
++)
12198 if (i
< regno
|| i
>= ourend
)
12199 REG_NOTES (where_dead
)
12200 = gen_rtx_EXPR_LIST (REG_DEAD
,
12202 REG_NOTES (where_dead
));
12205 /* If we didn't find any note, or if we found a REG_DEAD note that
12206 covers only part of the given reg, and we have a multi-reg hard
12207 register, then to be safe we must check for REG_DEAD notes
12208 for each register other than the first. They could have
12209 their own REG_DEAD notes lying around. */
12210 else if ((note
== 0
12212 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
12213 < GET_MODE_SIZE (GET_MODE (x
)))))
12214 && regno
< FIRST_PSEUDO_REGISTER
12215 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
12217 unsigned int ourend
12218 = regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12219 unsigned int i
, offset
;
12223 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
12227 for (i
= regno
+ offset
; i
< ourend
; i
++)
12228 move_deaths (regno_reg_rtx
[i
],
12229 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
12232 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
12234 XEXP (note
, 1) = *pnotes
;
12238 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
12240 REG_N_DEATHS (regno
)++;
12246 else if (GET_CODE (x
) == SET
)
12248 rtx dest
= SET_DEST (x
);
12250 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12252 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12253 that accesses one word of a multi-word item, some
12254 piece of everything register in the expression is used by
12255 this insn, so remove any old death. */
12256 /* ??? So why do we test for equality of the sizes? */
12258 if (GET_CODE (dest
) == ZERO_EXTRACT
12259 || GET_CODE (dest
) == STRICT_LOW_PART
12260 || (GET_CODE (dest
) == SUBREG
12261 && (((GET_MODE_SIZE (GET_MODE (dest
))
12262 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
12263 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
12264 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
12266 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12270 /* If this is some other SUBREG, we know it replaces the entire
12271 value, so use that as the destination. */
12272 if (GET_CODE (dest
) == SUBREG
)
12273 dest
= SUBREG_REG (dest
);
12275 /* If this is a MEM, adjust deaths of anything used in the address.
12276 For a REG (the only other possibility), the entire value is
12277 being replaced so the old value is not used in this insn. */
12279 if (GET_CODE (dest
) == MEM
)
12280 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
12285 else if (GET_CODE (x
) == CLOBBER
)
12288 len
= GET_RTX_LENGTH (code
);
12289 fmt
= GET_RTX_FORMAT (code
);
12291 for (i
= 0; i
< len
; i
++)
12296 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
12297 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
12300 else if (fmt
[i
] == 'e')
12301 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
12305 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12306 pattern of an insn. X must be a REG. */
12309 reg_bitfield_target_p (rtx x
, rtx body
)
12313 if (GET_CODE (body
) == SET
)
12315 rtx dest
= SET_DEST (body
);
12317 unsigned int regno
, tregno
, endregno
, endtregno
;
12319 if (GET_CODE (dest
) == ZERO_EXTRACT
)
12320 target
= XEXP (dest
, 0);
12321 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
12322 target
= SUBREG_REG (XEXP (dest
, 0));
12326 if (GET_CODE (target
) == SUBREG
)
12327 target
= SUBREG_REG (target
);
12329 if (GET_CODE (target
) != REG
)
12332 tregno
= REGNO (target
), regno
= REGNO (x
);
12333 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
12334 return target
== x
;
12336 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
12337 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
12339 return endregno
> tregno
&& regno
< endtregno
;
12342 else if (GET_CODE (body
) == PARALLEL
)
12343 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
12344 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
12350 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12351 as appropriate. I3 and I2 are the insns resulting from the combination
12352 insns including FROM (I2 may be zero).
12354 Each note in the list is either ignored or placed on some insns, depending
12355 on the type of note. */
12358 distribute_notes (rtx notes
, rtx from_insn
, rtx i3
, rtx i2
)
12360 rtx note
, next_note
;
12363 for (note
= notes
; note
; note
= next_note
)
12365 rtx place
= 0, place2
= 0;
12367 /* If this NOTE references a pseudo register, ensure it references
12368 the latest copy of that register. */
12369 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
12370 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
12371 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
12373 next_note
= XEXP (note
, 1);
12374 switch (REG_NOTE_KIND (note
))
12378 /* Doesn't matter much where we put this, as long as it's somewhere.
12379 It is preferable to keep these notes on branches, which is most
12380 likely to be i3. */
12384 case REG_VALUE_PROFILE
:
12385 /* Just get rid of this note, as it is unused later anyway. */
12388 case REG_VTABLE_REF
:
12389 /* ??? Should remain with *a particular* memory load. Given the
12390 nature of vtable data, the last insn seems relatively safe. */
12394 case REG_NON_LOCAL_GOTO
:
12395 if (GET_CODE (i3
) == JUMP_INSN
)
12397 else if (i2
&& GET_CODE (i2
) == JUMP_INSN
)
12403 case REG_EH_REGION
:
12404 /* These notes must remain with the call or trapping instruction. */
12405 if (GET_CODE (i3
) == CALL_INSN
)
12407 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12409 else if (flag_non_call_exceptions
)
12411 if (may_trap_p (i3
))
12413 else if (i2
&& may_trap_p (i2
))
12415 /* ??? Otherwise assume we've combined things such that we
12416 can now prove that the instructions can't trap. Drop the
12417 note in this case. */
12423 case REG_ALWAYS_RETURN
:
12426 /* These notes must remain with the call. It should not be
12427 possible for both I2 and I3 to be a call. */
12428 if (GET_CODE (i3
) == CALL_INSN
)
12430 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
12437 /* Any clobbers for i3 may still exist, and so we must process
12438 REG_UNUSED notes from that insn.
12440 Any clobbers from i2 or i1 can only exist if they were added by
12441 recog_for_combine. In that case, recog_for_combine created the
12442 necessary REG_UNUSED notes. Trying to keep any original
12443 REG_UNUSED notes from these insns can cause incorrect output
12444 if it is for the same register as the original i3 dest.
12445 In that case, we will notice that the register is set in i3,
12446 and then add a REG_UNUSED note for the destination of i3, which
12447 is wrong. However, it is possible to have REG_UNUSED notes from
12448 i2 or i1 for register which were both used and clobbered, so
12449 we keep notes from i2 or i1 if they will turn into REG_DEAD
12452 /* If this register is set or clobbered in I3, put the note there
12453 unless there is one already. */
12454 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
12456 if (from_insn
!= i3
)
12459 if (! (GET_CODE (XEXP (note
, 0)) == REG
12460 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
12461 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
12464 /* Otherwise, if this register is used by I3, then this register
12465 now dies here, so we must put a REG_DEAD note here unless there
12467 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
12468 && ! (GET_CODE (XEXP (note
, 0)) == REG
12469 ? find_regno_note (i3
, REG_DEAD
,
12470 REGNO (XEXP (note
, 0)))
12471 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
12473 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
12481 /* These notes say something about results of an insn. We can
12482 only support them if they used to be on I3 in which case they
12483 remain on I3. Otherwise they are ignored.
12485 If the note refers to an expression that is not a constant, we
12486 must also ignore the note since we cannot tell whether the
12487 equivalence is still true. It might be possible to do
12488 slightly better than this (we only have a problem if I2DEST
12489 or I1DEST is present in the expression), but it doesn't
12490 seem worth the trouble. */
12492 if (from_insn
== i3
12493 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
12498 case REG_NO_CONFLICT
:
12499 /* These notes say something about how a register is used. They must
12500 be present on any use of the register in I2 or I3. */
12501 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
12504 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
12514 /* This can show up in several ways -- either directly in the
12515 pattern, or hidden off in the constant pool with (or without?)
12516 a REG_EQUAL note. */
12517 /* ??? Ignore the without-reg_equal-note problem for now. */
12518 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12519 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12520 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12521 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12525 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12526 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12527 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12528 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12536 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12537 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12538 if (place
&& GET_CODE (place
) == JUMP_INSN
&& JUMP_LABEL (place
))
12540 if (JUMP_LABEL (place
) != XEXP (note
, 0))
12542 if (GET_CODE (JUMP_LABEL (place
)) == CODE_LABEL
)
12543 LABEL_NUSES (JUMP_LABEL (place
))--;
12546 if (place2
&& GET_CODE (place2
) == JUMP_INSN
&& JUMP_LABEL (place2
))
12548 if (JUMP_LABEL (place2
) != XEXP (note
, 0))
12550 if (GET_CODE (JUMP_LABEL (place2
)) == CODE_LABEL
)
12551 LABEL_NUSES (JUMP_LABEL (place2
))--;
12557 /* This note says something about the value of a register prior
12558 to the execution of an insn. It is too much trouble to see
12559 if the note is still correct in all situations. It is better
12560 to simply delete it. */
12564 /* If the insn previously containing this note still exists,
12565 put it back where it was. Otherwise move it to the previous
12566 insn. Adjust the corresponding REG_LIBCALL note. */
12567 if (GET_CODE (from_insn
) != NOTE
)
12571 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12572 place
= prev_real_insn (from_insn
);
12574 XEXP (tem
, 0) = place
;
12575 /* If we're deleting the last remaining instruction of a
12576 libcall sequence, don't add the notes. */
12577 else if (XEXP (note
, 0) == from_insn
)
12583 /* This is handled similarly to REG_RETVAL. */
12584 if (GET_CODE (from_insn
) != NOTE
)
12588 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12589 place
= next_real_insn (from_insn
);
12591 XEXP (tem
, 0) = place
;
12592 /* If we're deleting the last remaining instruction of a
12593 libcall sequence, don't add the notes. */
12594 else if (XEXP (note
, 0) == from_insn
)
12600 /* If the register is used as an input in I3, it dies there.
12601 Similarly for I2, if it is nonzero and adjacent to I3.
12603 If the register is not used as an input in either I3 or I2
12604 and it is not one of the registers we were supposed to eliminate,
12605 there are two possibilities. We might have a non-adjacent I2
12606 or we might have somehow eliminated an additional register
12607 from a computation. For example, we might have had A & B where
12608 we discover that B will always be zero. In this case we will
12609 eliminate the reference to A.
12611 In both cases, we must search to see if we can find a previous
12612 use of A and put the death note there. */
12615 && GET_CODE (from_insn
) == CALL_INSN
12616 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12618 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12620 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12621 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12626 basic_block bb
= this_basic_block
;
12628 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12630 if (! INSN_P (tem
))
12632 if (tem
== BB_HEAD (bb
))
12637 /* If the register is being set at TEM, see if that is all
12638 TEM is doing. If so, delete TEM. Otherwise, make this
12639 into a REG_UNUSED note instead. */
12640 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12642 rtx set
= single_set (tem
);
12643 rtx inner_dest
= 0;
12645 rtx cc0_setter
= NULL_RTX
;
12649 for (inner_dest
= SET_DEST (set
);
12650 (GET_CODE (inner_dest
) == STRICT_LOW_PART
12651 || GET_CODE (inner_dest
) == SUBREG
12652 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
12653 inner_dest
= XEXP (inner_dest
, 0))
12656 /* Verify that it was the set, and not a clobber that
12657 modified the register.
12659 CC0 targets must be careful to maintain setter/user
12660 pairs. If we cannot delete the setter due to side
12661 effects, mark the user with an UNUSED note instead
12664 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12665 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12667 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12668 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12669 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12673 /* Move the notes and links of TEM elsewhere.
12674 This might delete other dead insns recursively.
12675 First set the pattern to something that won't use
12677 rtx old_notes
= REG_NOTES (tem
);
12679 PATTERN (tem
) = pc_rtx
;
12680 REG_NOTES (tem
) = NULL
;
12682 distribute_notes (old_notes
, tem
, tem
, NULL_RTX
);
12683 distribute_links (LOG_LINKS (tem
));
12685 PUT_CODE (tem
, NOTE
);
12686 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12687 NOTE_SOURCE_FILE (tem
) = 0;
12690 /* Delete the setter too. */
12693 PATTERN (cc0_setter
) = pc_rtx
;
12694 old_notes
= REG_NOTES (cc0_setter
);
12695 REG_NOTES (cc0_setter
) = NULL
;
12697 distribute_notes (old_notes
, cc0_setter
,
12698 cc0_setter
, NULL_RTX
);
12699 distribute_links (LOG_LINKS (cc0_setter
));
12701 PUT_CODE (cc0_setter
, NOTE
);
12702 NOTE_LINE_NUMBER (cc0_setter
)
12703 = NOTE_INSN_DELETED
;
12704 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12708 /* If the register is both set and used here, put the
12709 REG_DEAD note here, but place a REG_UNUSED note
12710 here too unless there already is one. */
12711 else if (reg_referenced_p (XEXP (note
, 0),
12716 if (! find_regno_note (tem
, REG_UNUSED
,
12717 REGNO (XEXP (note
, 0))))
12719 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12724 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12726 /* If there isn't already a REG_UNUSED note, put one
12728 if (! find_regno_note (tem
, REG_UNUSED
,
12729 REGNO (XEXP (note
, 0))))
12734 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12735 || (GET_CODE (tem
) == CALL_INSN
12736 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12740 /* If we are doing a 3->2 combination, and we have a
12741 register which formerly died in i3 and was not used
12742 by i2, which now no longer dies in i3 and is used in
12743 i2 but does not die in i2, and place is between i2
12744 and i3, then we may need to move a link from place to
12746 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12747 && INSN_CUID (place
) > INSN_CUID (i2
)
12749 && INSN_CUID (from_insn
) > INSN_CUID (i2
)
12750 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12752 rtx links
= LOG_LINKS (place
);
12753 LOG_LINKS (place
) = 0;
12754 distribute_links (links
);
12759 if (tem
== BB_HEAD (bb
))
12763 /* We haven't found an insn for the death note and it
12764 is still a REG_DEAD note, but we have hit the beginning
12765 of the block. If the existing life info says the reg
12766 was dead, there's nothing left to do. Otherwise, we'll
12767 need to do a global life update after combine. */
12768 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0
12769 && REGNO_REG_SET_P (bb
->global_live_at_start
,
12770 REGNO (XEXP (note
, 0))))
12771 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12774 /* If the register is set or already dead at PLACE, we needn't do
12775 anything with this note if it is still a REG_DEAD note.
12776 We can here if it is set at all, not if is it totally replace,
12777 which is what `dead_or_set_p' checks, so also check for it being
12780 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12782 unsigned int regno
= REGNO (XEXP (note
, 0));
12784 /* Similarly, if the instruction on which we want to place
12785 the note is a noop, we'll need do a global live update
12786 after we remove them in delete_noop_moves. */
12787 if (noop_move_p (place
))
12788 SET_BIT (refresh_blocks
, this_basic_block
->index
);
12790 if (dead_or_set_p (place
, XEXP (note
, 0))
12791 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12793 /* Unless the register previously died in PLACE, clear
12794 reg_last_death. [I no longer understand why this is
12796 if (reg_last_death
[regno
] != place
)
12797 reg_last_death
[regno
] = 0;
12801 reg_last_death
[regno
] = place
;
12803 /* If this is a death note for a hard reg that is occupying
12804 multiple registers, ensure that we are still using all
12805 parts of the object. If we find a piece of the object
12806 that is unused, we must arrange for an appropriate REG_DEAD
12807 note to be added for it. However, we can't just emit a USE
12808 and tag the note to it, since the register might actually
12809 be dead; so we recourse, and the recursive call then finds
12810 the previous insn that used this register. */
12812 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12813 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12815 unsigned int endregno
12816 = regno
+ HARD_REGNO_NREGS (regno
,
12817 GET_MODE (XEXP (note
, 0)));
12821 for (i
= regno
; i
< endregno
; i
++)
12822 if ((! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12823 && ! find_regno_fusage (place
, USE
, i
))
12824 || dead_or_set_regno_p (place
, i
))
12829 /* Put only REG_DEAD notes for pieces that are
12830 not already dead or set. */
12832 for (i
= regno
; i
< endregno
;
12833 i
+= HARD_REGNO_NREGS (i
, reg_raw_mode
[i
]))
12835 rtx piece
= regno_reg_rtx
[i
];
12836 basic_block bb
= this_basic_block
;
12838 if (! dead_or_set_p (place
, piece
)
12839 && ! reg_bitfield_target_p (piece
,
12843 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
, NULL_RTX
);
12845 distribute_notes (new_note
, place
, place
,
12848 else if (! refers_to_regno_p (i
, i
+ 1,
12849 PATTERN (place
), 0)
12850 && ! find_regno_fusage (place
, USE
, i
))
12851 for (tem
= PREV_INSN (place
); ;
12852 tem
= PREV_INSN (tem
))
12854 if (! INSN_P (tem
))
12856 if (tem
== BB_HEAD (bb
))
12858 SET_BIT (refresh_blocks
,
12859 this_basic_block
->index
);
12864 if (dead_or_set_p (tem
, piece
)
12865 || reg_bitfield_target_p (piece
,
12869 = gen_rtx_EXPR_LIST (REG_UNUSED
, piece
,
12884 /* Any other notes should not be present at this point in the
12891 XEXP (note
, 1) = REG_NOTES (place
);
12892 REG_NOTES (place
) = note
;
12894 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12895 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12896 && GET_CODE (XEXP (note
, 0)) == REG
)
12897 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12901 if ((REG_NOTE_KIND (note
) == REG_DEAD
12902 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12903 && GET_CODE (XEXP (note
, 0)) == REG
)
12904 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12906 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12907 REG_NOTE_KIND (note
),
12909 REG_NOTES (place2
));
12914 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12915 I3, I2, and I1 to new locations. This is also called to add a link
12916 pointing at I3 when I3's destination is changed. */
12919 distribute_links (rtx links
)
12921 rtx link
, next_link
;
12923 for (link
= links
; link
; link
= next_link
)
12929 next_link
= XEXP (link
, 1);
12931 /* If the insn that this link points to is a NOTE or isn't a single
12932 set, ignore it. In the latter case, it isn't clear what we
12933 can do other than ignore the link, since we can't tell which
12934 register it was for. Such links wouldn't be used by combine
12937 It is not possible for the destination of the target of the link to
12938 have been changed by combine. The only potential of this is if we
12939 replace I3, I2, and I1 by I3 and I2. But in that case the
12940 destination of I2 also remains unchanged. */
12942 if (GET_CODE (XEXP (link
, 0)) == NOTE
12943 || (set
= single_set (XEXP (link
, 0))) == 0)
12946 reg
= SET_DEST (set
);
12947 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12948 || GET_CODE (reg
) == SIGN_EXTRACT
12949 || GET_CODE (reg
) == STRICT_LOW_PART
)
12950 reg
= XEXP (reg
, 0);
12952 /* A LOG_LINK is defined as being placed on the first insn that uses
12953 a register and points to the insn that sets the register. Start
12954 searching at the next insn after the target of the link and stop
12955 when we reach a set of the register or the end of the basic block.
12957 Note that this correctly handles the link that used to point from
12958 I3 to I2. Also note that not much searching is typically done here
12959 since most links don't point very far away. */
12961 for (insn
= NEXT_INSN (XEXP (link
, 0));
12962 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR
12963 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
12964 insn
= NEXT_INSN (insn
))
12965 if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12967 if (reg_referenced_p (reg
, PATTERN (insn
)))
12971 else if (GET_CODE (insn
) == CALL_INSN
12972 && find_reg_fusage (insn
, USE
, reg
))
12977 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
12980 /* If we found a place to put the link, place it there unless there
12981 is already a link to the same insn as LINK at that point. */
12987 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12988 if (XEXP (link2
, 0) == XEXP (link
, 0))
12993 XEXP (link
, 1) = LOG_LINKS (place
);
12994 LOG_LINKS (place
) = link
;
12996 /* Set added_links_insn to the earliest insn we added a
12998 if (added_links_insn
== 0
12999 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
13000 added_links_insn
= place
;
13006 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13009 insn_cuid (rtx insn
)
13011 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
13012 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
13013 insn
= NEXT_INSN (insn
);
13015 if (INSN_UID (insn
) > max_uid_cuid
)
13018 return INSN_CUID (insn
);
13022 dump_combine_stats (FILE *file
)
13026 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13027 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
13031 dump_combine_total_stats (FILE *file
)
13035 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13036 total_attempts
, total_merges
, total_extras
, total_successes
);