| blob | 37f0f260754da77e693369e791dd76a5e3aa8b9d |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
57 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
58 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
60 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
61 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
62 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
65 /* Vector mapping INSN_UIDs to luids.
66 The luids are like uids but increase monotonically always.
67 We use them to see whether a jump comes from outside a given loop. */
71 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
72 number the insn is contained in. */
76 /* 1 + largest uid of any insn. */
80 /* 1 + luid of last insn. */
84 /* Number of loops detected in current function. Used as index to the
85 next few tables. */
89 /* Bound on pseudo register number before loop optimization.
90 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
93 /* The value to pass to the next call of reg_scan_update. */
96 #define obstack_chunk_alloc xmalloc
97 #define obstack_chunk_free free
98 \f
99 /* During the analysis of a loop, a chain of `struct movable's
100 is made to record all the movable insns found.
101 Then the entire chain can be scanned to decide which to move. */
103 struct movable
104 {
109 of any registers used within the LIBCALL. */
111 that must be moved with this one. */
114 may be adjusted when matching movables
115 that load the same value are found. */
117 including other movables that force this
118 or match this one. */
122 /* If PARTIAL is 1, GLOBAL means something different:
123 that the reg is live outside the range from where it is set
124 to the following label. */
128 In particular, moving it does not make it
129 invariant. */
131 load SRC, rather than copying INSN. */
133 first insn of a consecutive sets group. */
136 that we should avoid changing when clearing
137 the rest of the reg. */
141 };
146 /* Forward declarations. */
160 #if 0
162 #endif
191 rtx *));
269 {
270 rtx r1;
271 rtx r2;
275 {
276 rtx match;
277 rtx replacement;
278 rtx insn;
281 /* Nonzero iff INSN is between START and END, inclusive. */
282 #define INSN_IN_RANGE_P(INSN, START, END) \
283 (INSN_UID (INSN) < max_uid_for_loop \
284 && INSN_LUID (INSN) >= INSN_LUID (START) \
285 && INSN_LUID (INSN) <= INSN_LUID (END))
287 /* Indirect_jump_in_function is computed once per function. */
295 rtx));
296 \f
297 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
298 copy the value of the strength reduced giv to its original register. */
301 /* Cost of using a register, to normalize the benefits of a giv. */
304 void
306 {
312 }
313 \f
314 /* Compute the mapping from uids to luids.
315 LUIDs are numbers assigned to insns, like uids,
316 except that luids increase monotonically through the code.
317 Start at insn START and stop just before END. Assign LUIDs
318 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
319 static int
323 {
325 rtx insn;
328 {
331 /* Don't assign luids to line-number NOTEs, so that the distance in
332 luids between two insns is not affected by -g. */
336 else
337 /* Give a line number note the same luid as preceding insn. */
339 }
341 }
342 \f
343 /* Entry point of this file. Perform loop optimization
344 on the current function. F is the first insn of the function
345 and DUMPFILE is a stream for output of a trace of actions taken
346 (or 0 if none should be output). */
348 void
350 /* f is the first instruction of a chain of insns for one function */
351 rtx f;
354 {
370 /* Count the number of loops. */
374 {
377 max_loop_num++;
378 }
380 /* Don't waste time if no loops. */
386 /* Get size to use for tables indexed by uids.
387 Leave some space for labels allocated by find_and_verify_loops. */
394 /* Allocate storage for array of loops. */
398 /* Find and process each loop.
399 First, find them, and record them in order of their beginnings. */
402 /* Allocate and initialize auxiliary loop information. */
407 /* Now find all register lifetimes. This must be done after
408 find_and_verify_loops, because it might reorder the insns in the
409 function. */
412 /* This must occur after reg_scan so that registers created by gcse
413 will have entries in the register tables.
415 We could have added a call to reg_scan after gcse_main in toplev.c,
416 but moving this call to init_alias_analysis is more efficient. */
419 /* See if we went too far. Note that get_max_uid already returns
420 one more that the maximum uid of all insn. */
423 /* Now reset it to the actual size we need. See above. */
426 /* find_and_verify_loops has already called compute_luids, but it
427 might have rearranged code afterwards, so we need to recompute
428 the luids now. */
431 /* Don't leave gaps in uid_luid for insns that have been
432 deleted. It is possible that the first or last insn
433 using some register has been deleted by cross-jumping.
434 Make sure that uid_luid for that former insn's uid
435 points to the general area where that insn used to be. */
437 {
441 }
446 /* Determine if the function has indirect jump. On some systems
447 this prevents low overhead loop instructions from being used. */
450 /* Now scan the loops, last ones first, since this means inner ones are done
451 before outer ones. */
453 {
458 }
460 /* If there were lexical blocks inside the loop, they have been
461 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
462 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
463 the BLOCKs as well. */
469 /* Clean up. */
474 }
475 \f
476 /* Returns the next insn, in execution order, after INSN. START and
477 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
478 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
479 insn-stream; it is used with loops that are entered near the
480 bottom. */
482 static rtx
485 rtx insn;
486 {
490 {
492 /* Go to the top of the loop, and continue there. */
494 else
495 /* We're done. */
497 }
500 /* We're done. */
504 }
506 /* Optimize one loop described by LOOP. */
508 /* ??? Could also move memory writes out of loops if the destination address
509 is invariant, the source is invariant, the memory write is not volatile,
510 and if we can prove that no read inside the loop can read this address
511 before the write occurs. If there is a read of this address after the
512 write, then we can also mark the memory read as invariant. */
514 static void
518 {
524 rtx p;
525 /* 1 if we are scanning insns that could be executed zero times. */
527 /* 1 if we are scanning insns that might never be executed
528 due to a subroutine call which might exit before they are reached. */
530 /* Jump insn that enters the loop, or 0 if control drops in. */
532 /* Number of insns in the loop. */
536 /* The SET from an insn, if it is the only SET in the insn. */
538 /* Chain describing insns movable in current loop. */
540 /* Ratio of extra register life span we can justify
541 for saving an instruction. More if loop doesn't call subroutines
542 since in that case saving an insn makes more difference
543 and more registers are available. */
545 /* Nonzero if we are scanning instructions in a sub-loop. */
554 /* Determine whether this loop starts with a jump down to a test at
555 the end. This will occur for a small number of loops with a test
556 that is too complex to duplicate in front of the loop.
558 We search for the first insn or label in the loop, skipping NOTEs.
559 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
560 (because we might have a loop executed only once that contains a
561 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
562 (in case we have a degenerate loop).
564 Note that if we mistakenly think that a loop is entered at the top
565 when, in fact, it is entered at the exit test, the only effect will be
566 slightly poorer optimization. Making the opposite error can generate
567 incorrect code. Since very few loops now start with a jump to the
568 exit test, the code here to detect that case is very conservative. */
571 p != loop_end
577 ;
581 /* If loop end is the end of the current function, then emit a
582 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
583 note insn. This is the position we use when sinking insns out of
584 the loop. */
587 else
590 /* Set up variables describing this loop. */
594 /* If loop has a jump before the first label,
595 the true entry is the target of that jump.
596 Start scan from there.
597 But record in LOOP->TOP the place where the end-test jumps
598 back to so we can scan that after the end of the loop. */
600 {
603 /* Loop entry must be unconditional jump (and not a RETURN) */
606 /* Check to see whether the jump actually
607 jumps out of the loop (meaning it's no loop).
608 This case can happen for things like
609 do {..} while (0). If this label was generated previously
610 by loop, we can't tell anything about it and have to reject
611 the loop. */
613 {
616 }
617 }
619 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
620 as required by loop_reg_used_before_p. So skip such loops. (This
621 test may never be true, but it's best to play it safe.)
623 Also, skip loops where we do not start scanning at a label. This
624 test also rejects loops starting with a JUMP_INSN that failed the
625 test above. */
629 {
634 }
636 /* Allocate extra space for REGs that might be created by load_mems.
637 We allocate a little extra slop as well, in the hopes that we
638 won't have to reallocate the regs array. */
642 {
648 }
650 /* Scan through the loop finding insns that are safe to move.
651 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
652 this reg will be considered invariant for subsequent insns.
653 We consider whether subsequent insns use the reg
654 in deciding whether it is worth actually moving.
656 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
657 and therefore it is possible that the insns we are scanning
658 would never be executed. At such times, we must make sure
659 that it is safe to execute the insn once instead of zero times.
660 When MAYBE_NEVER is 0, all insns will be executed at least once
661 so that is not a problem. */
666 {
671 {
678 /* Figure out what to use as a source of this insn. If a REG_EQUIV
679 note is given or if a REG_EQUAL note with a constant operand is
680 specified, use it as the source and mark that we should move
681 this insn by calling emit_move_insn rather that duplicating the
682 insn.
684 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
685 is present. */
689 else
690 {
695 {
697 /* A libcall block can use regs that don't appear in
698 the equivalent expression. To move the libcall,
699 we must move those regs too. */
701 }
702 }
704 /* Don't try to optimize a register that was made
705 by loop-optimization for an inner loop.
706 We don't know its life-span, so we can't compute the benefit. */
708 ;
710 than the one where it is set (meaning that
711 something after this point in the loop might
712 depend on its value before the set). */
714 /* And the set is not guaranteed to be executed one
715 the loop starts, or the value before the set is
716 needed before the set occurs...
718 ??? Note we have quadratic behaviour here, mitigated
719 by the fact that the previous test will often fail for
720 large loops. Rather than re-scanning the entire loop
721 each time for register usage, we should build tables
722 of the register usage and use them here instead. */
723 && (maybe_never
725 /* It is unsafe to move the set.
727 This code used to consider it OK to move a set of a variable
728 which was not created by the user and not used in an exit test.
729 That behavior is incorrect and was removed. */
730 ;
735 || (tem1
736 = consec_sets_invariant_p
739 p)))
740 /* If the insn can cause a trap (such as divide by zero),
741 can't move it unless it's guaranteed to be executed
742 once loop is entered. Even a function call might
743 prevent the trap insn from being reached
744 (since it might exit!) */
747 {
751 /* A potential lossage is where we have a case where two insns
752 can be combined as long as they are both in the loop, but
753 we move one of them outside the loop. For large loops,
754 this can lose. The most common case of this is the address
755 of a function being called.
757 Therefore, if this register is marked as being used exactly
758 once if we are in a loop with calls (a "large loop"), see if
759 we can replace the usage of this register with the source
760 of this SET. If we can, delete this insn.
762 Don't do this if P has a REG_RETVAL note or if we have
763 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
774 && (! SMALL_REGISTER_CLASSES
777 /* This test is not redundant; SET_SRC (set) might be
778 a call-clobbered register and the life of REGNO
779 might span a call. */
785 {
786 /* Replace any usage in a REG_EQUAL note. Must copy the
787 new source, so that we don't get rtx sharing between the
788 SET_SOURCE and REG_NOTES of insn p. */
798 }
816 /* Set M->cond if either loop_invariant_p
817 or consec_sets_invariant_p returned 2
818 (only conditionally invariant). */
827 /* Add M to the end of the chain MOVABLES. */
831 {
832 /* It is possible for the first instruction to have a
833 REG_EQUAL note but a non-invariant SET_SRC, so we must
834 remember the status of the first instruction in case
835 the last instruction doesn't have a REG_EQUAL note. */
838 /* Skip this insn, not checking REG_LIBCALL notes. */
840 /* Skip the consecutive insns, if there are any. */
842 /* Back up to the last insn of the consecutive group. */
845 /* We must now reset m->move_insn, m->is_equiv, and possibly
846 m->set_src to correspond to the effects of all the
847 insns. */
851 else
852 {
856 else
859 }
861 }
862 }
863 /* If this register is always set within a STRICT_LOW_PART
864 or set to zero, then its high bytes are constant.
865 So clear them outside the loop and within the loop
866 just load the low bytes.
867 We must check that the machine has an instruction to do so.
868 Also, if the value loaded into the register
869 depends on the same register, this cannot be done. */
879 {
882 {
896 /* If the insn may not be executed on some cycles,
897 we can't clear the whole reg; clear just high part.
898 Not even if the reg is used only within this loop.
899 Consider this:
900 while (1)
901 while (s != t) {
902 if (foo ()) x = *s;
903 use (x);
904 }
905 Clearing x before the inner loop could clobber a value
906 being saved from the last time around the outer loop.
907 However, if the reg is not used outside this loop
908 and all uses of the register are in the same
909 basic block as the store, there is no problem.
911 If this insn was made by loop, we don't know its
912 INSN_LUID and hence must make a conservative
913 assumption. */
916 || (labels_in_range_p
920 else
928 /* Add M to the end of the chain MOVABLES. */
930 }
931 }
932 }
933 /* Past a call insn, we get to insns which might not be executed
934 because the call might exit. This matters for insns that trap.
935 Constant and pure call insns always return, so they don't count. */
938 /* Past a label or a jump, we get to insns for which we
939 can't count on whether or how many times they will be
940 executed during each iteration. Therefore, we can
941 only move out sets of trivial variables
942 (those not used after the loop). */
943 /* Similar code appears twice in strength_reduce. */
945 /* If we enter the loop in the middle, and scan around to the
946 beginning, don't set maybe_never for that. This must be an
947 unconditional jump, otherwise the code at the top of the
948 loop might never be executed. Unconditional jumps are
949 followed a by barrier then loop end. */
955 {
956 /* At the virtual top of a converted loop, insns are again known to
957 be executed: logically, the loop begins here even though the exit
958 code has been duplicated. */
962 loop_depth++;
964 loop_depth--;
965 }
966 }
968 /* If one movable subsumes another, ignore that other. */
972 /* For each movable insn, see if the reg that it loads
973 leads when it dies right into another conditionally movable insn.
974 If so, record that the second insn "forces" the first one,
975 since the second can be moved only if the first is. */
979 /* See if there are multiple movable insns that load the same value.
980 If there are, make all but the first point at the first one
981 through the `match' field, and add the priorities of them
982 all together as the priority of the first. */
986 /* Now consider each movable insn to decide whether it is worth moving.
987 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
989 Generally this increases code size, so do not move moveables when
990 optimizing for code size. */
995 /* Now candidates that still are negative are those not moved.
996 Change regs->array[I].set_in_loop to indicate that those are not actually
997 invariant. */
1002 /* Now that we've moved some things out of the loop, we might be able to
1003 hoist even more memory references. */
1006 /* Recalculate regs->array if load_mems has created new registers. */
1014 ;
1021 {
1023 /* Ensure our label doesn't go away. */
1034 }
1037 /* The movable information is required for strength reduction. */
1043 }
1044 \f
1045 /* Add elements to *OUTPUT to record all the pseudo-regs
1046 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1048 void
1052 {
1060 {
1078 }
1082 {
1086 {
1095 }
1096 }
1097 }
1098 \f
1099 /* Check what regs are referred to in the libcall block ending with INSN,
1100 aside from those mentioned in the equivalent value.
1101 If there are none, return 0.
1102 If there are one or more, return an EXPR_LIST containing all of them. */
1104 rtx
1107 {
1112 /* First, find all the regs used in the libcall block
1113 that are not mentioned as inputs to the result. */
1116 {
1121 }
1124 }
1125 \f
1126 /* Return 1 if all uses of REG
1127 are between INSN and the end of the basic block. */
1129 static int
1132 {
1134 rtx p;
1139 /* Search this basic block for the already recorded last use of the reg. */
1141 {
1143 {
1149 /* Ordinary insn: if this is the last use, we win. */
1155 /* Jump insn: if this is the last use, we win. */
1158 /* Otherwise, it's the end of the basic block, so we lose. */
1163 /* It's the end of the basic block, so we lose. */
1168 }
1169 }
1171 /* The "last use" that was recorded can't be found after the first
1172 use. This can happen when the last use was deleted while
1173 processing an inner loop, this inner loop was then completely
1174 unrolled, and the outer loop is always exited after the inner loop,
1175 so that everything after the first use becomes a single basic block. */
1177 }
1178 \f
1179 /* Compute the benefit of eliminating the insns in the block whose
1180 last insn is LAST. This may be a group of insns used to compute a
1181 value directly or can contain a library call. */
1183 static int
1185 rtx last;
1186 {
1187 rtx insn;
1192 {
1195 routine. */
1199 benefit++;
1200 }
1203 }
1204 \f
1205 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1207 static rtx
1209 rtx insn;
1211 {
1213 {
1214 rtx temp;
1216 /* If first insn of libcall sequence, skip to end. */
1217 /* Do this at start of loop, since INSN is guaranteed to
1218 be an insn here. */
1223 do
1226 }
1229 }
1231 /* Ignore any movable whose insn falls within a libcall
1232 which is part of another movable.
1233 We make use of the fact that the movable for the libcall value
1234 was made later and so appears later on the chain. */
1236 static void
1239 {
1243 {
1244 /* Is this a movable for the value of a libcall? */
1247 {
1248 rtx insn;
1249 /* Check for earlier movables inside that range,
1250 and mark them invalid. We cannot use LUIDs here because
1251 insns created by loop.c for prior loops don't have LUIDs.
1252 Rather than reject all such insns from movables, we just
1253 explicitly check each insn in the libcall (since invariant
1254 libcalls aren't that common). */
1259 }
1260 }
1261 }
1263 /* For each movable insn, see if the reg that it loads
1264 leads when it dies right into another conditionally movable insn.
1265 If so, record that the second insn "forces" the first one,
1266 since the second can be moved only if the first is. */
1268 static void
1271 {
1274 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1276 {
1279 /* ??? Could this be a bug? What if CSE caused the
1280 register of M1 to be used after this insn?
1281 Since CSE does not update regno_last_uid,
1282 this insn M->insn might not be where it dies.
1283 But very likely this doesn't matter; what matters is
1284 that M's reg is computed from M1's reg. */
1289 /* If m->consec, m->set_src isn't valid. */
1293 /* Increase the priority of the moving the first insn
1294 since it permits the second to be moved as well. */
1296 {
1300 }
1301 }
1302 }
1303 \f
1304 /* Find invariant expressions that are equal and can be combined into
1305 one register. */
1307 static void
1311 {
1316 /* Regs that are set more than once are not allowed to match
1317 or be matched. I'm no longer sure why not. */
1318 /* Perhaps testing m->consec_sets would be more appropriate here? */
1323 {
1330 /* We want later insns to match the first one. Don't make the first
1331 one match any later ones. So start this loop at m->next. */
1335 /* A reg used outside the loop mustn't be eliminated. */
1337 /* A reg used for zero-extending mustn't be eliminated. */
1340 ||
1341 (
1342 /* Can combine regs with different modes loaded from the
1343 same constant only if the modes are the same or
1344 if both are integer modes with M wider or the same
1345 width as M1. The check for integer is redundant, but
1346 safe, since the only case of differing destination
1347 modes with equal sources is when both sources are
1348 VOIDmode, i.e., CONST_INT. */
1354 /* See if the source of M1 says it matches M. */
1361 {
1367 }
1368 }
1370 /* Now combine the regs used for zero-extension.
1371 This can be done for those not marked `global'
1372 provided their lives don't overlap. */
1376 {
1379 /* Combine all the registers for extension from mode MODE.
1380 Don't combine any that are used outside this loop. */
1384 {
1390 {
1391 /* First one: don't check for overlap, just record it. */
1394 }
1396 /* Make sure they extend to the same mode.
1397 (Almost always true.) */
1401 /* We already have one: check for overlap with those
1402 already combined together. */
1409 /* No overlap: we can combine this with the others. */
1415 overlap:
1416 ;
1417 }
1418 }
1420 /* Clean up. */
1422 }
1423 \f
1424 /* Return 1 if regs X and Y will become the same if moved. */
1426 static int
1430 {
1447 }
1449 /* Return 1 if X and Y are identical-looking rtx's.
1450 This is the Lisp function EQUAL for rtx arguments.
1452 If two registers are matching movables or a movable register and an
1453 equivalent constant, consider them equal. */
1455 static int
1460 {
1474 /* If we have a register and a constant, they may sometimes be
1475 equal. */
1478 {
1483 }
1486 {
1491 }
1493 /* Otherwise, rtx's of different codes cannot be equal. */
1497 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1498 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1503 /* These three types of rtx's can be compared nonrecursively. */
1512 /* Compare the elements. If any pair of corresponding elements
1513 fail to match, return 0 for the whole things. */
1517 {
1519 {
1531 /* Two vectors must have the same length. */
1535 /* And the corresponding elements must match. */
1554 /* These are just backpointers, so they don't matter. */
1560 /* It is believed that rtx's at this level will never
1561 contain anything but integers and other rtx's,
1562 except for within LABEL_REFs and SYMBOL_REFs. */
1565 }
1566 }
1568 }
1569 \f
1570 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1571 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1572 references is incremented once for each added note. */
1574 static void
1576 rtx x;
1577 rtx insns;
1578 {
1582 rtx insn;
1585 {
1586 /* This code used to ignore labels that referred to dispatch tables to
1587 avoid flow generating (slighly) worse code.
1589 We no longer ignore such label references (see LABEL_REF handling in
1590 mark_jump_label for additional information). */
1593 {
1598 }
1599 }
1603 {
1609 }
1610 }
1611 \f
1612 /* Scan MOVABLES, and move the insns that deserve to be moved.
1613 If two matching movables are combined, replace one reg with the
1614 other throughout. */
1616 static void
1622 {
1630 /* Map of pseudo-register replacements to handle combining
1631 when we move several insns that load the same value
1632 into different pseudo-registers. */
1639 {
1640 /* Describe this movable insn. */
1643 {
1664 }
1666 /* Count movables. Value used in heuristics in strength_reduce. */
1669 /* Ignore the insn if it's already done (it matched something else).
1670 Otherwise, see if it is now safe to move. */
1682 {
1687 /* We have an insn that is safe to move.
1688 Compute its desirability. */
1699 /* An insn MUST be moved if we already moved something else
1700 which is safe only if this one is moved too: that is,
1701 if already_moved[REGNO] is nonzero. */
1703 /* An insn is desirable to move if the new lifetime of the
1704 register is no more than THRESHOLD times the old lifetime.
1705 If it's not desirable, it means the loop is so big
1706 that moving won't speed things up much,
1707 and it is liable to make register usage worse. */
1709 /* It is also desirable to move if it can be moved at no
1710 extra cost because something else was already moved. */
1713 || flag_move_all_movables
1718 {
1723 /* Now move the insns that set the reg. */
1726 {
1729 /* Find the end of this chain of matching regs.
1730 Thus, we load each reg in the chain from that one reg.
1731 And that reg is loaded with 0 directly,
1732 since it has ->match == 0. */
1738 /* Mark the moved, invariant reg as being allowed to
1739 share a hard reg with the other matching invariant. */
1743 regs_may_share
1746 regs_may_share));
1754 }
1755 /* If we are to re-generate the item being moved with a
1756 new move insn, first delete what we have and then emit
1757 the move insn before the loop. */
1759 {
1763 {
1764 /* If this is the first insn of a library call sequence,
1765 skip to the end. */
1770 /* If this is the last insn of a libcall sequence, then
1771 delete every insn in the sequence except the last.
1772 The last insn is handled in the normal manner. */
1775 {
1779 }
1784 /* simplify_giv_expr expects that it can walk the insns
1785 at m->insn forwards and see this old sequence we are
1786 tossing here. delete_insn does preserve the next
1787 pointers, but when we skip over a NOTE we must fix
1788 it up. Otherwise that code walks into the non-deleted
1789 insn stream. */
1792 }
1811 /* The more regs we move, the less we like moving them. */
1813 }
1814 else
1815 {
1817 {
1820 /* If first insn of libcall sequence, skip to end. */
1821 /* Do this at start of loop, since p is guaranteed to
1822 be an insn here. */
1827 /* If last insn of libcall sequence, move all
1828 insns except the last before the loop. The last
1829 insn is handled in the normal manner. */
1832 {
1840 {
1841 rtx body;
1842 rtx n;
1843 rtx next;
1850 /* Find the next insn after TEMP,
1851 not counting USE or NOTE insns. */
1859 /* If that is the call, this may be the insn
1860 that loads the function address.
1862 Extract the function address from the insn
1863 that loads it into a register.
1864 If this insn was cse'd, we get incorrect code.
1866 So emit a new move insn that copies the
1867 function address into the register that the
1868 call insn will use. flow.c will delete any
1869 redundant stores that we have created. */
1874 NULL_RTX)))
1875 {
1881 }
1882 /* We have the call insn.
1883 If it uses the register we suspect it might,
1884 load it with the correct address directly. */
1889 fn_address),
1890 fn_address_insn);
1893 {
1895 /* Because the USAGE information potentially
1896 contains objects other than hard registers
1897 we need to copy it. */
1901 }
1902 else
1910 }
1913 }
1915 {
1916 /* P sets REG to zero; but we should clear only
1917 the bits that are not covered by the mode
1918 m->savemode. */
1920 rtx sequence;
1921 rtx tem;
1924 tem = expand_binop
1937 }
1939 {
1941 /* Because the USAGE information potentially
1942 contains objects other than hard registers
1943 we need to copy it. */
1947 }
1949 {
1950 rtx seq;
1951 /* The SET_SRC might not be invariant, so we must
1952 use the REG_EQUAL note. */
1967 }
1968 else
1972 {
1975 /* If there is a REG_EQUAL note present whose value
1976 is not loop invariant, then delete it, since it
1977 may cause problems with later optimization passes.
1978 It is possible for cse to create such notes
1979 like this as a result of record_jump_cond. */
1984 }
1993 /* If library call, now fix the REG_NOTES that contain
1994 insn pointers, namely REG_LIBCALL on FIRST
1995 and REG_RETVAL on I1. */
1997 {
2001 }
2007 /* simplify_giv_expr expects that it can walk the insns
2008 at m->insn forwards and see this old sequence we are
2009 tossing here. delete_insn does preserve the next
2010 pointers, but when we skip over a NOTE we must fix
2011 it up. Otherwise that code walks into the non-deleted
2012 insn stream. */
2015 }
2017 /* The more regs we move, the less we like moving them. */
2019 }
2021 /* Any other movable that loads the same register
2022 MUST be moved. */
2025 /* This reg has been moved out of one loop. */
2028 /* The reg set here is now invariant. */
2034 /* Change the length-of-life info for the register
2035 to say it lives at least the full length of this loop.
2036 This will help guide optimizations in outer loops. */
2039 /* This is the old insn before all the moved insns.
2040 We can't use the moved insn because it is out of range
2041 in uid_luid. Only the old insns have luids. */
2046 /* Combine with this moved insn any other matching movables. */
2051 {
2052 rtx temp;
2054 /* Schedule the reg loaded by M1
2055 for replacement so that shares the reg of M.
2056 If the modes differ (only possible in restricted
2057 circumstances, make a SUBREG.
2059 Note this assumes that the target dependent files
2060 treat REG and SUBREG equally, including within
2061 GO_IF_LEGITIMATE_ADDRESS and in all the
2062 predicates since we never verify that replacing the
2063 original register with a SUBREG results in a
2064 recognizable insn. */
2067 else
2072 /* Get rid of the matching insn
2073 and prevent further processing of it. */
2076 /* if library call, delete all insn except last, which
2077 is deleted below */
2079 NULL_RTX)))
2080 {
2084 }
2087 /* Any other movable that loads the same register
2088 MUST be moved. */
2091 /* The reg merged here is now invariant,
2092 if the reg it matches is invariant. */
2095 }
2096 }
2099 }
2105 }
2110 /* Go through all the instructions in the loop, making
2111 all the register substitutions scheduled in REG_MAP. */
2115 {
2119 }
2121 /* Clean up. */
2124 }
2127 static void
2131 {
2134 else
2137 }
2140 static void
2143 {
2148 {
2151 }
2152 }
2153 \f
2154 #if 0
2155 /* Scan X and replace the address of any MEM in it with ADDR.
2156 REG is the address that MEM should have before the replacement. */
2158 static void
2161 {
2170 {
2182 /* Short cut for very common case. */
2187 /* Short cut for very common case. */
2192 /* If this MEM uses a reg other than the one we expected,
2193 something is wrong. */
2201 }
2205 {
2209 {
2213 }
2214 }
2215 }
2216 #endif
2217 \f
2218 /* Return the number of memory refs to addresses that vary
2219 in the rtx X. */
2221 static int
2224 rtx x;
2225 {
2236 {
2253 }
2258 {
2262 {
2266 }
2267 }
2269 }
2270 \f
2271 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2272 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2273 `unknown_address_altered', `unknown_constant_address_altered', and
2274 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2275 list `store_mems' in LOOP. */
2277 static void
2280 {
2282 rtx insn;
2286 /* The label after END. Jumping here is just like falling off the
2287 end of the loop. We use next_nonnote_insn instead of next_label
2288 as a hedge against the (pathological) case where some actual insn
2289 might end up between the two. */
2311 {
2313 {
2316 }
2317 }
2321 {
2323 {
2325 {
2327 /* Count number of loops contained in this one. */
2329 }
2331 {
2333 }
2334 }
2336 {
2338 {
2341 }
2343 }
2345 {
2365 {
2367 {
2370 }
2371 else
2372 {
2374 }
2376 do
2377 {
2379 {
2381 {
2382 /* Something tricky. */
2385 }
2388 {
2389 /* A jump outside the current loop. */
2392 }
2393 }
2397 }
2399 }
2400 }
2403 }
2405 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2407 anywhere. */
2409 /* We don't want loads for MEMs moved to a location before the
2410 one at which their stack memory becomes allocated. (Note
2411 that this is not a problem for malloc, etc., since those
2412 require actual function calls. */
2413 && ! current_function_calls_alloca
2414 /* There are ways to leave the loop other than falling off the
2415 end. */
2421 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2422 that loop_invariant_p and load_mems can use true_dependence
2423 to determine what is really clobbered. */
2425 {
2428 loop_info->store_mems
2430 }
2432 {
2436 loop_info->store_mems
2438 }
2439 }
2440 \f
2441 /* Scan the function looking for loops. Record the start and end of each loop.
2442 Also mark as invalid loops any loops that contain a setjmp or are branched
2443 to from outside the loop. */
2445 static void
2447 rtx f;
2449 {
2450 rtx insn;
2451 rtx label;
2461 /* If there are jumps to undefined labels,
2462 treat them as jumps out of any/all loops.
2463 This also avoids writing past end of tables when there are no loops. */
2466 /* Find boundaries of loops, mark which loops are contained within
2467 loops, and invalidate loops that have setjmp. */
2472 {
2475 {
2479 num_loops++;
2486 /* In this case, we must invalidate our current loop and any
2487 enclosing loop. */
2489 {
2495 }
2516 }
2518 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2519 enclosing loop, but this doesn't matter. */
2521 }
2523 /* Any loop containing a label used in an initializer must be invalidated,
2524 because it can be jumped into from anywhere. */
2527 {
2531 }
2533 /* Any loop containing a label used for an exception handler must be
2534 invalidated, because it can be jumped into from anywhere. */
2537 {
2541 }
2543 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2544 loop that it is not contained within, that loop is marked invalid.
2545 If any INSN or CALL_INSN uses a label's address, then the loop containing
2546 that label is marked invalid, because it could be jumped into from
2547 anywhere.
2549 Also look for blocks of code ending in an unconditional branch that
2550 exits the loop. If such a block is surrounded by a conditional
2551 branch around the block, move the block elsewhere (see below) and
2552 invert the jump to point to the code block. This may eliminate a
2553 label in our loop and will simplify processing by both us and a
2554 possible second cse pass. */
2558 {
2562 {
2565 {
2569 }
2570 }
2577 /* See if this is an unconditional branch outside the loop. */
2585 {
2586 rtx p;
2592 /* Go backwards until we reach the start of the loop, a label,
2593 or a JUMP_INSN. */
2600 ;
2602 /* Check for the case where we have a jump to an inner nested
2603 loop, and do not perform the optimization in that case. */
2606 {
2609 {
2614 }
2615 }
2617 /* Make sure that the target of P is within the current loop. */
2623 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2624 we have a block of code to try to move.
2626 We look backward and then forward from the target of INSN
2627 to find a BARRIER at the same loop depth as the target.
2628 If we find such a BARRIER, we make a new label for the start
2629 of the block, invert the jump in P and point it to that label,
2630 and move the block of code to the spot we found. */
2635 /* Just ignore jumps to labels that were never emitted.
2636 These always indicate compilation errors. */
2640 /* If it's not safe to move the sequence, then we
2641 mustn't try. */
2644 {
2645 rtx target
2652 /* Don't move things inside a tablejump. */
2665 /* Don't move things inside a tablejump. */
2676 {
2680 /* Ensure our label doesn't go away. */
2683 /* Verify that uid_loop is large enough and that
2684 we can invert P. */
2686 {
2689 /* If no suitable BARRIER was found, create a suitable
2690 one before TARGET. Since TARGET is a fall through
2691 path, we'll need to insert an jump around our block
2692 and a add a BARRIER before TARGET.
2694 This creates an extra unconditional jump outside
2695 the loop. However, the benefits of removing rarely
2696 executed instructions from inside the loop usually
2697 outweighs the cost of the extra unconditional jump
2698 outside the loop. */
2700 {
2701 rtx temp;
2708 }
2710 /* Include the BARRIER after INSN and copy the
2711 block after LOC. */
2713 last_insn_to_move);
2716 /* All those insns are now in TARGET_LOOP. */
2722 /* The label jumped to by INSN is no longer a loop
2723 exit. Unless INSN does not have a label (e.g.,
2724 it is a RETURN insn), search loop->exit_labels
2725 to find its label_ref, and remove it. Also turn
2726 off LABEL_OUTSIDE_LOOP_P bit. */
2728 {
2730 r;
2733 {
2737 else
2740 }
2746 /* If we didn't find it, then something is
2747 wrong. */
2750 }
2752 /* P is now a jump outside the loop, so it must be put
2753 in loop->exit_labels, and marked as such.
2754 The easiest way to do this is to just call
2755 mark_loop_jump again for P. */
2758 /* If INSN now jumps to the insn after it,
2759 delete INSN. */
2764 }
2766 /* Continue the loop after where the conditional
2767 branch used to jump, since the only branch insn
2768 in the block (if it still remains) is an inter-loop
2769 branch and hence needs no processing. */
2775 /* This loop will be continued with NEXT_INSN (insn). */
2777 }
2778 }
2779 }
2780 }
2781 }
2783 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2784 loops it is contained in, mark the target loop invalid.
2786 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2788 static void
2790 rtx x;
2792 {
2798 {
2810 /* There could be a label reference in here. */
2822 /* This may refer to a LABEL_REF or SYMBOL_REF. */
2834 /* Link together all labels that branch outside the loop. This
2835 is used by final_[bg]iv_value and the loop unrolling code. Also
2836 mark this LABEL_REF so we know that this branch should predict
2837 false. */
2839 /* A check to make sure the label is not in an inner nested loop,
2840 since this does not count as a loop exit. */
2842 {
2847 }
2848 else
2852 {
2861 }
2863 /* If this is inside a loop, but not in the current loop or one enclosed
2864 by it, it invalidates at least one loop. */
2869 /* We must invalidate every nested loop containing the target of this
2870 label, except those that also contain the jump insn. */
2873 {
2874 /* Stop when we reach a loop that also contains the jump insn. */
2879 /* If we get here, we know we need to invalidate a loop. */
2886 }
2890 /* If this is not setting pc, ignore. */
2912 /* Strictly speaking this is not a jump into the loop, only a possible
2913 jump out of the loop. However, we have no way to link the destination
2914 of this jump onto the list of exit labels. To be safe we mark this
2915 loop and any containing loops as invalid. */
2917 {
2919 {
2925 }
2926 }
2928 }
2929 }
2930 \f
2931 /* Return nonzero if there is a label in the range from
2932 insn INSN to and including the insn whose luid is END
2933 INSN must have an assigned luid (i.e., it must not have
2934 been previously created by loop.c). */
2936 static int
2938 rtx insn;
2940 {
2942 {
2946 }
2949 }
2951 /* Record that a memory reference X is being set. */
2953 static void
2955 rtx x;
2956 rtx y ATTRIBUTE_UNUSED;
2958 {
2964 /* Count number of memory writes.
2965 This affects heuristics in strength_reduce. */
2968 /* BLKmode MEM means all memory is clobbered. */
2970 {
2973 else
2977 }
2981 }
2983 /* X is a value modified by an INSN that references a biv inside a loop
2984 exit test (ie, X is somehow related to the value of the biv). If X
2985 is a pseudo that is used more than once, then the biv is (effectively)
2986 used more than once. DATA is a pointer to a loop_regs structure. */
2988 static void
2990 rtx x;
2991 rtx y ATTRIBUTE_UNUSED;
2993 {
3008 /* If we do not have usage information, or if we know the register
3009 is used more than once, note that fact for check_dbra_loop. */
3014 }
3015 \f
3016 /* Return nonzero if the rtx X is invariant over the current loop.
3018 The value is 2 if we refer to something only conditionally invariant.
3020 A memory ref is invariant if it is not volatile and does not conflict
3021 with anything stored in `loop_info->store_mems'. */
3023 int
3027 {
3034 rtx mem_list_entry;
3040 {
3048 /* A LABEL_REF is normally invariant, however, if we are unrolling
3049 loops, and this label is inside the loop, then it isn't invariant.
3050 This is because each unrolled copy of the loop body will have
3051 a copy of this label. If this was invariant, then an insn loading
3052 the address of this label into a register might get moved outside
3053 the loop, and then each loop body would end up using the same label.
3055 We don't know the loop bounds here though, so just fail for all
3056 labels. */
3059 else
3068 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3069 since the reg might be set by initialization within the loop. */
3086 /* Volatile memory references must be rejected. Do this before
3087 checking for read-only items, so that volatile read-only items
3088 will be rejected also. */
3092 /* See if there is any dependence between a store and this load. */
3095 {
3101 }
3103 /* It's not invalidated by a store in memory
3104 but we must still verify the address is invariant. */
3108 /* Don't mess with insns declared volatile. */
3115 }
3119 {
3121 {
3127 }
3129 {
3132 {
3138 }
3140 }
3141 }
3144 }
3145 \f
3146 /* Return nonzero if all the insns in the loop that set REG
3147 are INSN and the immediately following insns,
3148 and if each of those insns sets REG in an invariant way
3149 (not counting uses of REG in them).
3151 The value is 2 if some of these insns are only conditionally invariant.
3153 We assume that INSN itself is the first set of REG
3154 and that its source is invariant. */
3156 static int
3161 {
3165 rtx temp;
3166 /* Number of sets we have to insist on finding after INSN. */
3172 /* If N_SETS hit the limit, we can't rely on its value. */
3179 {
3181 rtx set;
3186 /* If library call, skip to end of it. */
3195 {
3200 {
3201 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3202 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3203 notes are OK. */
3209 }
3210 }
3212 count--;
3214 {
3217 }
3218 }
3221 /* If loop_invariant_p ever returned 2, we return 2. */
3223 }
3225 #if 0
3226 /* I don't think this condition is sufficient to allow INSN
3227 to be moved, so we no longer test it. */
3229 /* Return 1 if all insns in the basic block of INSN and following INSN
3230 that set REG are invariant according to TABLE. */
3232 static int
3236 {
3241 {
3250 {
3253 }
3254 }
3255 }
3257 \f
3258 /* Look at all uses (not sets) of registers in X. For each, if it is
3259 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3260 a different insn, set USAGE[REGNO] to const0_rtx. */
3262 static void
3265 rtx insn;
3266 rtx x;
3267 {
3279 {
3280 /* Don't count SET_DEST if it is a REG; otherwise count things
3281 in SET_DEST because if a register is partially modified, it won't
3282 show up as a potential movable so we don't care how USAGE is set
3283 for it. */
3287 }
3288 else
3290 {
3296 }
3297 }
3298 \f
3299 /* Count and record any set in X which is contained in INSN. Update
3300 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3301 in X. */
3303 static void
3308 {
3310 /* Don't move a reg that has an explicit clobber.
3311 It's not worth the pain to try to do it correctly. */
3315 {
3323 {
3325 /* If this is the first setting of this reg
3326 in current basic block, and it was set before,
3327 it must be set in two basic blocks, so it cannot
3328 be moved out of the loop. */
3332 /* If this is not first setting in current basic block,
3333 see if reg was used in between previous one and this.
3334 If so, neither one can be moved. */
3341 }
3342 }
3343 }
3344 \f
3345 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3346 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3347 contained in insn INSN is used by any insn that precedes INSN in
3348 cyclic order starting from the loop entry point.
3350 We don't want to use INSN_LUID here because if we restrict INSN to those
3351 that have a valid INSN_LUID, it means we cannot move an invariant out
3352 from an inner loop past two loops. */
3354 static int
3358 {
3360 rtx p;
3362 /* Scan forward checking for register usage. If we hit INSN, we
3363 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3365 {
3371 }
3374 }
3375 \f
3376 /* A "basic induction variable" or biv is a pseudo reg that is set
3377 (within this loop) only by incrementing or decrementing it. */
3378 /* A "general induction variable" or giv is a pseudo reg whose
3379 value is a linear function of a biv. */
3381 /* Bivs are recognized by `basic_induction_var';
3382 Givs by `general_induction_var'. */
3384 /* Communication with routines called via `note_stores'. */
3388 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
3392 /* ??? Unfinished optimizations, and possible future optimizations,
3393 for the strength reduction code. */
3395 /* ??? The interaction of biv elimination, and recognition of 'constant'
3396 bivs, may cause problems. */
3398 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
3399 performance problems.
3401 Perhaps don't eliminate things that can be combined with an addressing
3402 mode. Find all givs that have the same biv, mult_val, and add_val;
3403 then for each giv, check to see if its only use dies in a following
3404 memory address. If so, generate a new memory address and check to see
3405 if it is valid. If it is valid, then store the modified memory address,
3406 otherwise, mark the giv as not done so that it will get its own iv. */
3408 /* ??? Could try to optimize branches when it is known that a biv is always
3409 positive. */
3411 /* ??? When replace a biv in a compare insn, we should replace with closest
3412 giv so that an optimized branch can still be recognized by the combiner,
3413 e.g. the VAX acb insn. */
3415 /* ??? Many of the checks involving uid_luid could be simplified if regscan
3416 was rerun in loop_optimize whenever a register was added or moved.
3417 Also, some of the optimizations could be a little less conservative. */
3418 \f
3419 /* Scan the loop body and call FNCALL for each insn. In the addition to the
3420 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
3421 callback.
3423 NOT_EVERY_ITERATION if current insn is not executed at least once for every
3424 loop iteration except for the last one.
3426 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
3427 loop iteration.
3428 */
3429 void
3432 loop_insn_callback fncall;
3433 {
3434 /* This is 1 if current insn is not executed at least once for every loop
3435 iteration. */
3440 rtx p;
3442 /* If loop_scan_start points to the loop exit test, we have to be wary of
3443 subversive use of gotos inside expression statements. */
3447 /* Scan through loop to find all possible bivs. */
3452 {
3455 /* Past CODE_LABEL, we get to insns that may be executed multiple
3456 times. The only way we can be sure that they can't is if every
3457 jump insn between here and the end of the loop either
3458 returns, exits the loop, is a jump to a location that is still
3459 behind the label, or is a jump to the loop start. */
3462 {
3468 {
3473 {
3476 else
3480 }
3488 {
3491 }
3492 }
3493 }
3495 /* Past a jump, we get to insns for which we can't count
3496 on whether they will be executed during each iteration. */
3497 /* This code appears twice in strength_reduce. There is also similar
3498 code in scan_loop. */
3500 /* If we enter the loop in the middle, and scan around to the
3501 beginning, don't set not_every_iteration for that.
3502 This can be any kind of jump, since we want to know if insns
3503 will be executed if the loop is executed. */
3508 {
3511 /* If this is a jump outside the loop, then it also doesn't
3512 matter. Check to see if the target of this branch is on the
3513 loop->exits_labels list. */
3521 }
3524 {
3525 /* At the virtual top of a converted loop, insns are again known to
3526 be executed each iteration: logically, the loop begins here
3527 even though the exit code has been duplicated.
3529 Insns are also again known to be executed each iteration at
3530 the LOOP_CONT note. */
3536 loop_depth++;
3538 loop_depth--;
3539 }
3541 /* Note if we pass a loop latch. If we do, then we can not clear
3542 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
3543 a loop since a jump before the last CODE_LABEL may have started
3544 a new loop iteration.
3546 Note that LOOP_TOP is only set for rotated loops and we need
3547 this check for all loops, so compare against the CODE_LABEL
3548 which immediately follows LOOP_START. */
3553 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
3554 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
3555 or not an insn is known to be executed each iteration of the
3556 loop, whether or not any iterations are known to occur.
3558 Therefore, if we have just passed a label and have no more labels
3559 between here and the test insn of the loop, and we have not passed
3560 a jump to the top of the loop, then we know these insns will be
3561 executed each iteration. */
3564 && !past_loop_latch
3569 }
3570 }
3571 \f
3572 static void
3575 {
3578 /* Temporary list pointers for traversing ivs->list. */
3585 /* Scan ivs->list to remove all regs that proved not to be bivs.
3586 Make a sanity check against regs->n_times_set. */
3588 {
3590 /* Above happens if register modified by subreg, etc. */
3591 /* Make sure it is not recognized as a basic induction var: */
3593 /* If never incremented, it is invariant that we decided not to
3594 move. So leave it alone. */
3596 {
3607 }
3608 else
3609 {
3614 }
3615 }
3616 }
3619 /* Determine how BIVS are initialised by looking through pre-header
3620 extended basic block. */
3621 static void
3624 {
3626 /* Temporary list pointers for traversing ivs->list. */
3629 rtx p;
3631 /* Find initial value for each biv by searching backwards from loop_start,
3632 halting at first label. Also record any test condition. */
3636 {
3637 rtx test;
3647 /* Record any test of a biv that branches around the loop if no store
3648 between it and the start of loop. We only care about tests with
3649 constants and registers and only certain of those. */
3659 {
3660 /* If an NE test, we have an initial value! */
3662 {
3666 }
3667 else
3669 }
3670 }
3671 }
3674 /* Look at the each biv and see if we can say anything better about its
3675 initial value from any initializing insns set up above. (This is done
3676 in two passes to avoid missing SETs in a PARALLEL.) */
3677 static void
3680 {
3682 /* Temporary list pointers for traversing ivs->list. */
3687 {
3688 rtx src;
3689 rtx note;
3694 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
3695 is a constant, use the value of that. */
3701 else
3714 {
3718 {
3721 }
3722 }
3723 /* If we can't make it a giv,
3724 let biv keep initial value of "itself". */
3727 }
3728 }
3731 /* Search the loop for general induction variables. */
3733 static void
3736 {
3738 }
3741 /* For each giv for which we still don't know whether or not it is
3742 replaceable, check to see if it is replaceable because its final value
3743 can be calculated. */
3745 static void
3748 {
3753 {
3759 }
3760 }
3763 /* Return non-zero if it is possible to eliminate the biv BL provided
3764 all givs are reduced. This is possible if either the reg is not
3765 used outside the loop, or we can compute what its final value will
3766 be. */
3768 static int
3774 {
3775 /* For architectures with a decrement_and_branch_until_zero insn,
3776 don't do this if we put a REG_NONNEG note on the endtest for this
3777 biv. */
3779 #ifdef HAVE_decrement_and_branch_until_zero
3781 {
3786 }
3787 #endif
3789 /* Check that biv is used outside loop or if it has a final value.
3790 Compare against bl->init_insn rather than loop->start. We aren't
3791 concerned with any uses of the biv between init_insn and
3792 loop->start since these won't be affected by the value of the biv
3793 elsewhere in the function, so long as init_insn doesn't use the
3794 biv itself. */
3805 {
3813 }
3815 }
3818 /* Reduce each giv of BL that we have decided to reduce. */
3820 static void
3824 {
3828 {
3831 {
3834 /* If the code for derived givs immediately below has already
3835 allocated a new_reg, we must keep it. */
3839 #ifdef AUTO_INC_DEC
3840 /* If the target has auto-increment addressing modes, and
3841 this is an address giv, then try to put the increment
3842 immediately after its use, so that flow can create an
3843 auto-increment addressing mode. */
3846 /* We don't handle reversed biv's because bl->biv->insn
3847 does not have a valid INSN_LUID. */
3851 {
3852 /* If other giv's have been combined with this one, then
3853 this will work only if all uses of the other giv's occur
3854 before this giv's insn. This is difficult to check.
3856 We simplify this by looking for the common case where
3857 there is one DEST_REG giv, and this giv's insn is the
3858 last use of the dest_reg of that DEST_REG giv. If the
3859 increment occurs after the address giv, then we can
3860 perform the optimization. (Otherwise, the increment
3861 would have to go before other_giv, and we would not be
3862 able to combine it with the address giv to get an
3863 auto-inc address.) */
3865 {
3870 {
3873 else
3875 }
3882 }
3883 /* Check for case where increment is before the address
3884 giv. Do this test in "loop order". */
3893 else
3896 #ifdef HAVE_cc0
3897 {
3898 rtx prev;
3900 /* We can't put an insn immediately after one setting
3901 cc0, or immediately before one using cc0. */
3908 }
3909 #endif
3913 }
3914 #endif
3916 /* For each place where the biv is incremented, add an insn
3917 to increment the new, reduced reg for the giv. */
3919 {
3920 rtx insert_before;
3926 else
3934 /* A multiply is acceptable here
3935 since this is presumed to be seldom executed. */
3939 }
3941 /* Add code at loop start to initialize giv's reduced reg. */
3946 }
3947 }
3948 }
3951 /* Check for givs whose first use is their definition and whose
3952 last use is the definition of another giv. If so, it is likely
3953 dead and should not be used to derive another giv nor to
3954 eliminate a biv. */
3956 static void
3960 {
3964 {
3971 {
3977 }
3978 }
3979 }
3982 static void
3987 {
3991 {
3998 /* Update expression if this was combined, in case other giv was
3999 replaced. */
4004 /* See if this register is known to be a pointer to something. If
4005 so, see if we can find the alignment. First see if there is a
4006 destination register that is a pointer. If so, this shares the
4007 alignment too. Next see if we can deduce anything from the
4008 computational information. If not, and this is a DEST_ADDR
4009 giv, at least we know that it's a pointer, though we don't know
4010 the alignment. */
4018 {
4027 }
4031 {
4039 }
4044 /* Store reduced reg as the address in the memref where we found
4045 this giv. */
4048 {
4050 }
4051 else
4052 {
4053 /* Not replaceable; emit an insn to set the original giv reg from
4054 the reduced giv, same as above. */
4057 }
4059 /* When a loop is reversed, givs which depend on the reversed
4060 biv, and which are live outside the loop, must be set to their
4061 correct final value. This insn is only needed if the giv is
4062 not replaceable. The correct final value is the same as the
4063 value that the giv starts the reversed loop with. */
4073 {
4078 }
4079 }
4080 }
4083 static int
4088 rtx test_reg;
4089 {
4098 /* Reduce benefit if not replaceable, since we will insert a
4099 move-insn to replace the insn that calculates this giv. Don't do
4100 this unless the giv is a user variable, since it will often be
4101 marked non-replaceable because of the duplication of the exit
4102 code outside the loop. In such a case, the copies we insert are
4103 dead and will be deleted. So they don't have a cost. Similar
4104 situations exist. */
4105 /* ??? The new final_[bg]iv_value code does a much better job of
4106 finding replaceable giv's, and hence this code may no longer be
4107 necessary. */
4112 /* Decrease the benefit to count the add-insns that we will insert
4113 to increment the reduced reg for the giv. ??? This can
4114 overestimate the run-time cost of the additional insns, e.g. if
4115 there are multiple basic blocks that increment the biv, but only
4116 one of these blocks is executed during each iteration. There is
4117 no good way to detect cases like this with the current structure
4118 of the loop optimizer. This code is more accurate for
4119 determining code size than run-time benefits. */
4122 /* Decide whether to strength-reduce this giv or to leave the code
4123 unchanged (recompute it from the biv each time it is used). This
4124 decision can be made independently for each giv. */
4126 #ifdef AUTO_INC_DEC
4127 /* Attempt to guess whether autoincrement will handle some of the
4128 new add insns; if so, increase BENEFIT (undo the subtraction of
4129 add_cost that was done above). */
4131 /* Increasing the benefit is risky, since this is only a guess.
4132 Avoid increasing register pressure in cases where there would
4133 be no other benefit from reducing this giv. */
4136 {
4149 }
4150 #endif
4153 }
4156 /* Free IV structures for LOOP. */
4158 static void
4161 {
4168 {
4174 {
4177 }
4179 {
4182 }
4186 }
4187 }
4190 /* Perform strength reduction and induction variable elimination.
4192 Pseudo registers created during this function will be beyond the
4193 last valid index in several tables including
4194 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
4195 problem here, because the added registers cannot be givs outside of
4196 their loop, and hence will never be reconsidered. But scan_loop
4197 must check regnos to make sure they are in bounds. */
4199 static void
4204 {
4208 rtx p;
4209 /* Temporary list pointer for traversing ivs->list. */
4211 /* Ratio of extra register life span we can justify
4212 for saving an instruction. More if loop doesn't call subroutines
4213 since in that case saving an insn makes more difference
4214 and more registers are available. */
4215 /* ??? could set this to last value of threshold in move_movables */
4217 /* Map of pseudo-register replacements. */
4228 /* Find all BIVs in loop. */
4231 /* Exit if there are no bivs. */
4233 {
4234 /* Can still unroll the loop anyways, but indicate that there is no
4235 strength reduction info available. */
4241 }
4243 /* Determine how BIVS are initialised by looking through pre-header
4244 extended basic block. */
4247 /* Look at the each biv and see if we can say anything better about its
4248 initial value from any initializing insns set up above. */
4251 /* Search the loop for general induction variables. */
4254 /* Try to calculate and save the number of loop iterations. This is
4255 set to zero if the actual number can not be calculated. This must
4256 be called after all giv's have been identified, since otherwise it may
4257 fail if the iteration variable is a giv. */
4260 /* Now for each giv for which we still don't know whether or not it is
4261 replaceable, check to see if it is replaceable because its final value
4262 can be calculated. This must be done after loop_iterations is called,
4263 so that final_giv_value will work correctly. */
4266 /* Try to prove that the loop counter variable (if any) is always
4267 nonnegative; if so, record that fact with a REG_NONNEG note
4268 so that "decrement and branch until zero" insn can be used. */
4271 /* Create reg_map to hold substitutions for replaceable giv regs.
4272 Some givs might have been made from biv increments, so look at
4273 ivs->reg_iv_type for a suitable size. */
4277 /* Examine each iv class for feasibility of strength reduction/induction
4278 variable elimination. */
4281 {
4285 /* Test whether it will be possible to eliminate this biv
4286 provided all givs are reduced. */
4289 /* Check each extension dependent giv in this class to see if its
4290 root biv is safe from wrapping in the interior mode. */
4293 /* Combine all giv's for this iv_class. */
4296 /* This will be true at the end, if all givs which depend on this
4297 biv have been strength reduced.
4298 We can't (currently) eliminate the biv unless this is so. */
4302 {
4310 /* If an insn is not to be strength reduced, then set its ignore
4311 flag, and clear bl->all_reduced. */
4313 /* A giv that depends on a reversed biv must be reduced if it is
4314 used after the loop exit, otherwise, it would have the wrong
4315 value after the loop exit. To make it simple, just reduce all
4316 of such giv's whether or not we know they are used after the loop
4317 exit. */
4322 {
4330 }
4331 else
4332 {
4333 /* Check that we can increment the reduced giv without a
4334 multiply insn. If not, reject it. */
4339 {
4347 }
4348 }
4349 }
4351 /* Check for givs whose first use is their definition and whose
4352 last use is the definition of another giv. If so, it is likely
4353 dead and should not be used to derive another giv nor to
4354 eliminate a biv. */
4357 /* Reduce each giv that we decided to reduce. */
4360 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
4361 as not reduced.
4363 For each giv register that can be reduced now: if replaceable,
4364 substitute reduced reg wherever the old giv occurs;
4365 else add new move insn "giv_reg = reduced_reg". */
4368 /* All the givs based on the biv bl have been reduced if they
4369 merit it. */
4371 /* For each giv not marked as maybe dead that has been combined with a
4372 second giv, clear any "maybe dead" mark on that second giv.
4373 v->new_reg will either be or refer to the register of the giv it
4374 combined with.
4376 Doing this clearing avoids problems in biv elimination where
4377 a giv's new_reg is a complex value that can't be put in the
4378 insn but the giv combined with (with a reg as new_reg) is
4379 marked maybe_dead. Since the register will be used in either
4380 case, we'd prefer it be used from the simpler giv. */
4386 /* Try to eliminate the biv, if it is a candidate.
4387 This won't work if ! bl->all_reduced,
4388 since the givs we planned to use might not have been reduced.
4390 We have to be careful that we didn't initially think we could
4391 eliminate this biv because of a giv that we now think may be
4392 dead and shouldn't be used as a biv replacement.
4394 Also, there is the possibility that we may have a giv that looks
4395 like it can be used to eliminate a biv, but the resulting insn
4396 isn't valid. This can happen, for example, on the 88k, where a
4397 JUMP_INSN can compare a register only with zero. Attempts to
4398 replace it with a compare with a constant will fail.
4400 Note that in cases where this call fails, we may have replaced some
4401 of the occurrences of the biv with a giv, but no harm was done in
4402 doing so in the rare cases where it can occur. */
4406 {
4407 /* ?? If we created a new test to bypass the loop entirely,
4408 or otherwise drop straight in, based on this test, then
4409 we might want to rewrite it also. This way some later
4410 pass has more hope of removing the initialization of this
4411 biv entirely. */
4413 /* If final_value != 0, then the biv may be used after loop end
4414 and we must emit an insn to set it just in case.
4416 Reversed bivs already have an insn after the loop setting their
4417 value, so we don't need another one. We can't calculate the
4418 proper final value for such a biv here anyways. */
4426 }
4427 }
4429 /* Go through all the instructions in the loop, making all the
4430 register substitutions scheduled in REG_MAP. */
4435 {
4439 }
4442 {
4443 /* When we completely unroll a loop we will likely not need the increment
4444 of the loop BIV and we will not need the conditional branch at the
4445 end of the loop. */
4448 #ifdef HAVE_cc0
4449 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
4450 need the comparison before the conditional branch at the end of the
4451 loop. */
4453 #endif
4455 /* We'll need one copy for each loop iteration. */
4458 /* A little slop to account for the ability to remove initialization
4459 code, better CSE, and other secondary benefits of completely
4460 unrolling some loops. */
4463 /* Clamp the value. */
4466 }
4468 /* Unroll loops from within strength reduction so that we can use the
4469 induction variable information that strength_reduce has already
4470 collected. Always unroll loops that would be as small or smaller
4471 unrolled than when rolled. */
4477 #ifdef HAVE_doloop_end
4488 }
4489 \f
4490 /*Record all basic induction variables calculated in the insn. */
4491 static rtx
4494 rtx p;
4497 {
4499 rtx set;
4500 rtx dest_reg;
4501 rtx inc_val;
4502 rtx mult_val;
4508 {
4513 {
4518 {
4519 /* It is a possible basic induction variable.
4520 Create and initialize an induction structure for it. */
4528 }
4531 }
4532 }
4534 }
4535 \f
4536 /* Record all givs calculated in the insn.
4537 A register is a giv if: it is only set once, it is a function of a
4538 biv and a constant (or invariant), and it is not a biv. */
4539 static rtx
4542 rtx p;
4545 {
4548 rtx set;
4549 /* Look for a general induction variable in a register. */
4554 {
4555 rtx src_reg;
4556 rtx dest_reg;
4557 rtx add_val;
4558 rtx mult_val;
4559 rtx ext_val;
4562 rtx last_consec_insn;
4571 /* Equivalent expression is a giv. */
4576 /* Don't try to handle any regs made by loop optimization.
4577 We have nothing on them in regno_first_uid, etc. */
4579 /* Don't recognize a BASIC_INDUCT_VAR here. */
4581 /* This must be the only place where the register is set. */
4583 /* or all sets must be consecutive and make a giv. */
4588 {
4592 /* If this is a library call, increase benefit. */
4596 /* Skip the consecutive insns, if there are any. */
4604 }
4605 }
4607 #ifndef DONT_REDUCE_ADDR
4608 /* Look for givs which are memory addresses. */
4609 /* This resulted in worse code on a VAX 8600. I wonder if it
4610 still does. */
4613 maybe_multiple);
4614 #endif
4616 /* Update the status of whether giv can derive other givs. This can
4617 change when we pass a label or an insn that updates a biv. */
4622 }
4623 \f
4624 /* Return 1 if X is a valid source for an initial value (or as value being
4625 compared against in an initial test).
4627 X must be either a register or constant and must not be clobbered between
4628 the current insn and the start of the loop.
4630 INSN is the insn containing X. */
4632 static int
4634 rtx x;
4635 rtx insn;
4637 rtx loop_start;
4638 {
4642 /* Only consider pseudos we know about initialized in insns whose luids
4643 we know. */
4648 /* Don't use call-clobbered registers across a call which clobbers it. On
4649 some machines, don't use any hard registers at all. */
4651 && (SMALL_REGISTER_CLASSES
4655 /* Don't use registers that have been clobbered before the start of the
4656 loop. */
4661 }
4662 \f
4663 /* Scan X for memory refs and check each memory address
4664 as a possible giv. INSN is the insn whose pattern X comes from.
4665 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
4666 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
4667 more thanonce in each loop iteration. */
4669 static void
4672 rtx x;
4673 rtx insn;
4675 {
4685 {
4701 {
4702 rtx src_reg;
4703 rtx add_val;
4704 rtx mult_val;
4705 rtx ext_val;
4708 /* This code used to disable creating GIVs with mult_val == 1 and
4709 add_val == 0. However, this leads to lost optimizations when
4710 it comes time to combine a set of related DEST_ADDR GIVs, since
4711 this one would not be seen. */
4716 {
4717 /* Found one; record it. */
4726 }
4727 }
4732 }
4734 /* Recursively scan the subexpressions for other mem refs. */
4740 maybe_multiple);
4744 maybe_multiple);
4745 }
4746 \f
4747 /* Fill in the data about one biv update.
4748 V is the `struct induction' in which we record the biv. (It is
4749 allocated by the caller, with alloca.)
4750 INSN is the insn that sets it.
4751 DEST_REG is the biv's reg.
4753 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
4754 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
4755 being set to INC_VAL.
4757 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
4758 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
4759 can be executed more than once per iteration. If MAYBE_MULTIPLE
4760 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
4761 executed exactly once per iteration. */
4763 static void
4768 rtx insn;
4769 rtx dest_reg;
4770 rtx inc_val;
4771 rtx mult_val;
4775 {
4791 /* Add this to the reg's iv_class, creating a class
4792 if this is the first incrementation of the reg. */
4796 {
4797 /* Create and initialize new iv_class. */
4807 /* Set initial value to the reg itself. */
4810 /* We haven't seen the initializing insn yet */
4820 /* Add this class to ivs->list. */
4824 /* Put it in the array of biv register classes. */
4826 }
4828 /* Update IV_CLASS entry for this biv. */
4837 }
4838 \f
4839 /* Fill in the data about one giv.
4840 V is the `struct induction' in which we record the giv. (It is
4841 allocated by the caller, with alloca.)
4842 INSN is the insn that sets it.
4843 BENEFIT estimates the savings from deleting this insn.
4844 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
4845 into a register or is used as a memory address.
4847 SRC_REG is the biv reg which the giv is computed from.
4848 DEST_REG is the giv's reg (if the giv is stored in a reg).
4849 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
4850 LOCATION points to the place where this giv's value appears in INSN. */
4852 static void
4857 rtx insn;
4858 rtx src_reg;
4859 rtx dest_reg;
4865 {
4870 rtx temp;
4872 /* Attempt to prove constantness of the values. */
4900 /* The v->always_computable field is used in update_giv_derive, to
4901 determine whether a giv can be used to derive another giv. For a
4902 DEST_REG giv, INSN computes a new value for the giv, so its value
4903 isn't computable if INSN insn't executed every iteration.
4904 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
4905 it does not compute a new value. Hence the value is always computable
4906 regardless of whether INSN is executed each iteration. */
4910 else
4916 {
4919 }
4921 {
4926 /* If the lifetime is zero, it means that this register is
4927 really a dead store. So mark this as a giv that can be
4928 ignored. This will not prevent the biv from being eliminated. */
4934 }
4936 /* Add the giv to the class of givs computed from one biv. */
4940 {
4943 /* Don't count DEST_ADDR. This is supposed to count the number of
4944 insns that calculate givs. */
4948 }
4949 else
4950 /* Fatal error, biv missing for this giv? */
4955 else
4956 {
4957 /* The giv can be replaced outright by the reduced register only if all
4958 of the following conditions are true:
4959 - the insn that sets the giv is always executed on any iteration
4960 on which the giv is used at all
4961 (there are two ways to deduce this:
4962 either the insn is executed on every iteration,
4963 or all uses follow that insn in the same basic block),
4964 - the giv is not used outside the loop
4965 - no assignments to the biv occur during the giv's lifetime. */
4968 /* Previous line always fails if INSN was moved by loop opt. */
4971 && (! not_every_iteration
4973 {
4974 /* Now check that there are no assignments to the biv within the
4975 giv's lifetime. This requires two separate checks. */
4977 /* Check each biv update, and fail if any are between the first
4978 and last use of the giv.
4980 If this loop contains an inner loop that was unrolled, then
4981 the insn modifying the biv may have been emitted by the loop
4982 unrolling code, and hence does not have a valid luid. Just
4983 mark the biv as not replaceable in this case. It is not very
4984 useful as a biv, because it is used in two different loops.
4985 It is very unlikely that we would be able to optimize the giv
4986 using this biv anyways. */
4990 {
4996 {
5000 }
5001 }
5003 /* If there are any backwards branches that go from after the
5004 biv update to before it, then this giv is not replaceable. */
5008 {
5012 }
5013 }
5014 else
5015 {
5016 /* May still be replaceable, we don't have enough info here to
5017 decide. */
5020 }
5021 }
5023 /* Record whether the add_val contains a const_int, for later use by
5024 combine_givs. */
5025 {
5030 ;
5034 {
5036 {
5041 else
5043 }
5046 }
5047 }
5051 }
5053 /* All this does is determine whether a giv can be made replaceable because
5054 its final value can be calculated. This code can not be part of record_giv
5055 above, because final_giv_value requires that the number of loop iterations
5056 be known, and that can not be accurately calculated until after all givs
5057 have been identified. */
5059 static void
5063 {
5070 /* DEST_ADDR givs will never reach here, because they are always marked
5071 replaceable above in record_giv. */
5073 /* The giv can be replaced outright by the reduced register only if all
5074 of the following conditions are true:
5075 - the insn that sets the giv is always executed on any iteration
5076 on which the giv is used at all
5077 (there are two ways to deduce this:
5078 either the insn is executed on every iteration,
5079 or all uses follow that insn in the same basic block),
5080 - its final value can be calculated (this condition is different
5081 than the one above in record_giv)
5082 - it's not used before the it's set
5083 - no assignments to the biv occur during the giv's lifetime. */
5085 #if 0
5086 /* This is only called now when replaceable is known to be false. */
5087 /* Clear replaceable, so that it won't confuse final_giv_value. */
5089 #endif
5093 {
5096 rtx last_giv_use;
5100 /* When trying to determine whether or not a biv increment occurs
5101 during the lifetime of the giv, we can ignore uses of the variable
5102 outside the loop because final_value is true. Hence we can not
5103 use regno_last_uid and regno_first_uid as above in record_giv. */
5105 /* Search the loop to determine whether any assignments to the
5106 biv occur during the giv's lifetime. Start with the insn
5107 that sets the giv, and search around the loop until we come
5108 back to that insn again.
5110 Also fail if there is a jump within the giv's lifetime that jumps
5111 to somewhere outside the lifetime but still within the loop. This
5112 catches spaghetti code where the execution order is not linear, and
5113 hence the above test fails. Here we assume that the giv lifetime
5114 does not extend from one iteration of the loop to the next, so as
5115 to make the test easier. Since the lifetime isn't known yet,
5116 this requires two loops. See also record_giv above. */
5121 {
5124 {
5127 }
5133 {
5134 /* It is possible for the BIV increment to use the GIV if we
5135 have a cycle. Thus we must be sure to check each insn for
5136 both BIV and GIV uses, and we must check for BIV uses
5137 first. */
5144 {
5146 {
5150 }
5152 }
5153 }
5154 }
5156 /* Now that the lifetime of the giv is known, check for branches
5157 from within the lifetime to outside the lifetime if it is still
5158 replaceable. */
5161 {
5164 {
5177 {
5186 }
5187 }
5188 }
5190 /* If it is replaceable, then save the final value. */
5193 }
5198 }
5199 \f
5200 /* Update the status of whether a giv can derive other givs.
5202 We need to do something special if there is or may be an update to the biv
5203 between the time the giv is defined and the time it is used to derive
5204 another giv.
5206 In addition, a giv that is only conditionally set is not allowed to
5207 derive another giv once a label has been passed.
5209 The cases we look at are when a label or an update to a biv is passed. */
5211 static void
5214 rtx p;
5215 {
5219 rtx tem;
5222 /* Search all IV classes, then all bivs, and finally all givs.
5224 There are three cases we are concerned with. First we have the situation
5225 of a giv that is only updated conditionally. In that case, it may not
5226 derive any givs after a label is passed.
5228 The second case is when a biv update occurs, or may occur, after the
5229 definition of a giv. For certain biv updates (see below) that are
5230 known to occur between the giv definition and use, we can adjust the
5231 giv definition. For others, or when the biv update is conditional,
5232 we must prevent the giv from deriving any other givs. There are two
5233 sub-cases within this case.
5235 If this is a label, we are concerned with any biv update that is done
5236 conditionally, since it may be done after the giv is defined followed by
5237 a branch here (actually, we need to pass both a jump and a label, but
5238 this extra tracking doesn't seem worth it).
5240 If this is a jump, we are concerned about any biv update that may be
5241 executed multiple times. We are actually only concerned about
5242 backward jumps, but it is probably not worth performing the test
5243 on the jump again here.
5245 If this is a biv update, we must adjust the giv status to show that a
5246 subsequent biv update was performed. If this adjustment cannot be done,
5247 the giv cannot derive further givs. */
5253 {
5255 {
5256 /* If cant_derive is already true, there is no point in
5257 checking all of these conditions again. */
5261 /* If this giv is conditionally set and we have passed a label,
5262 it cannot derive anything. */
5266 /* Skip givs that have mult_val == 0, since
5267 they are really invariants. Also skip those that are
5268 replaceable, since we know their lifetime doesn't contain
5269 any biv update. */
5273 /* The only way we can allow this giv to derive another
5274 is if this is a biv increment and we can form the product
5275 of biv->add_val and giv->mult_val. In this case, we will
5276 be able to compute a compensation. */
5278 {
5279 rtx ext_val_dummy;
5290 tem = simplify_giv_expr
5297 else
5299 }
5303 }
5304 }
5305 }
5306 \f
5307 /* Check whether an insn is an increment legitimate for a basic induction var.
5308 X is the source of insn P, or a part of it.
5309 MODE is the mode in which X should be interpreted.
5311 DEST_REG is the putative biv, also the destination of the insn.
5312 We accept patterns of these forms:
5313 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
5314 REG = INVARIANT + REG
5316 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
5317 store the additive term into *INC_VAL, and store the place where
5318 we found the additive term into *LOCATION.
5320 If X is an assignment of an invariant into DEST_REG, we set
5321 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
5323 We also want to detect a BIV when it corresponds to a variable
5324 whose mode was promoted via PROMOTED_MODE. In that case, an increment
5325 of the variable may be a PLUS that adds a SUBREG of that variable to
5326 an invariant and then sign- or zero-extends the result of the PLUS
5327 into the variable.
5329 Most GIVs in such cases will be in the promoted mode, since that is the
5330 probably the natural computation mode (and almost certainly the mode
5331 used for addresses) on the machine. So we view the pseudo-reg containing
5332 the variable as the BIV, as if it were simply incremented.
5334 Note that treating the entire pseudo as a BIV will result in making
5335 simple increments to any GIVs based on it. However, if the variable
5336 overflows in its declared mode but not its promoted mode, the result will
5337 be incorrect. This is acceptable if the variable is signed, since
5338 overflows in such cases are undefined, but not if it is unsigned, since
5339 those overflows are defined. So we only check for SIGN_EXTEND and
5340 not ZERO_EXTEND.
5342 If we cannot find a biv, we return 0. */
5344 static int
5349 rtx dest_reg;
5350 rtx p;
5354 {
5362 {
5368 {
5370 }
5375 {
5377 }
5378 else
5391 /* If this is a SUBREG for a promoted variable, check the inner
5392 value. */
5400 /* If this register is assigned in a previous insn, look at its
5401 source, but don't go outside the loop or past a label. */
5403 /* If this sets a register to itself, we would repeat any previous
5404 biv increment if we applied this strategy blindly. */
5410 {
5411 rtx dest;
5412 do
5413 {
5415 }
5444 }
5445 /* Fall through. */
5447 /* Can accept constant setting of biv only when inside inner most loop.
5448 Otherwise, a biv of an inner loop may be incorrectly recognized
5449 as a biv of the outer loop,
5450 causing code to be moved INTO the inner loop. */
5457 /* convert_modes aborts if we try to convert to or from CCmode, so just
5458 exclude that case. It is very unlikely that a condition code value
5459 would be a useful iterator anyways. */
5463 {
5464 /* Possible bug here? Perhaps we don't know the mode of X. */
5468 }
5469 else
5477 /* Similar, since this can be a sign extension. */
5482 ;
5496 location);
5501 }
5502 }
5503 \f
5504 /* A general induction variable (giv) is any quantity that is a linear
5505 function of a basic induction variable,
5506 i.e. giv = biv * mult_val + add_val.
5507 The coefficients can be any loop invariant quantity.
5508 A giv need not be computed directly from the biv;
5509 it can be computed by way of other givs. */
5511 /* Determine whether X computes a giv.
5512 If it does, return a nonzero value
5513 which is the benefit from eliminating the computation of X;
5514 set *SRC_REG to the register of the biv that it is computed from;
5515 set *ADD_VAL and *MULT_VAL to the coefficients,
5516 such that the value of X is biv * mult + add; */
5518 static int
5522 rtx x;
5530 {
5534 /* If this is an invariant, forget it, it isn't a giv. */
5545 {
5548 /* Since this is now an invariant and wasn't before, it must be a giv
5549 with MULT_VAL == 0. It doesn't matter which BIV we associate this
5550 with. */
5557 /* This is equivalent to a BIV. */
5564 /* Either (plus (biv) (invar)) or
5565 (plus (mult (biv) (invar_1)) (invar_2)). */
5567 {
5570 }
5571 else
5572 {
5575 }
5580 /* ADD_VAL is zero. */
5588 }
5590 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
5591 unless they are CONST_INT). */
5599 else
5602 /* Always return true if this is a giv so it will be detected as such,
5603 even if the benefit is zero or negative. This allows elimination
5604 of bivs that might otherwise not be eliminated. */
5606 }
5607 \f
5608 /* Given an expression, X, try to form it as a linear function of a biv.
5609 We will canonicalize it to be of the form
5610 (plus (mult (BIV) (invar_1))
5611 (invar_2))
5612 with possible degeneracies.
5614 The invariant expressions must each be of a form that can be used as a
5615 machine operand. We surround then with a USE rtx (a hack, but localized
5616 and certainly unambiguous!) if not a CONST_INT for simplicity in this
5617 routine; it is the caller's responsibility to strip them.
5619 If no such canonicalization is possible (i.e., two biv's are used or an
5620 expression that is neither invariant nor a biv or giv), this routine
5621 returns 0.
5623 For a non-zero return, the result will have a code of CONST_INT, USE,
5624 REG (for a BIV), PLUS, or MULT. No other codes will occur.
5626 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
5631 static rtx
5634 rtx x;
5637 {
5642 rtx tem;
5644 /* If this is not an integer mode, or if we cannot do arithmetic in this
5645 mode, this can't be a giv. */
5652 {
5659 /* Put constant last, CONST_INT last if both constant. */
5667 /* Handle addition of zero, then addition of an invariant. */
5672 {
5675 /* Adding two invariants must result in an invariant, so enclose
5676 addition operation inside a USE and return it. */
5686 else
5695 /* biv + invar or mult + invar. Return sum. */
5699 /* (a + invar_1) + invar_2. Associate. */
5700 return
5706 arg1)),
5711 }
5713 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
5714 MULT to reduce cases. */
5720 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
5721 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
5722 Recurse to associate the second PLUS. */
5727 return
5735 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
5751 /* Handle "a - b" as "a + b * (-1)". */
5757 constm1_rtx)),
5766 /* Put constant last, CONST_INT last if both constant. */
5771 /* If second argument is not now constant, not giv. */
5775 /* Handle multiply by 0 or 1. */
5783 {
5785 /* biv * invar. Done. */
5789 /* Product of two constants. */
5793 /* invar * invar is a giv, but attempt to simplify it somehow. */
5799 {
5800 /* (invar_0 * invar_1) * invar_2. Associate. */
5807 arg1)),
5809 }
5810 /* Porpagate the MULT expressions to the intermost nodes. */
5812 {
5813 /* (invar_0 + invar_1) * invar_2. Distribute. */
5819 arg1),
5823 arg1)),
5825 }
5829 /* (a * invar_1) * invar_2. Associate. */
5835 arg1)),
5839 /* (a + invar_1) * invar_2. Distribute. */
5844 arg1),
5847 arg1)),
5852 }
5855 /* Shift by constant is multiply by power of two. */
5859 return
5868 /* "-a" is "a * (-1)" */
5874 /* "~a" is "-a - 1". Silly, but easy. */
5878 const1_rtx),
5882 /* Already in proper form for invariant. */
5888 /* Conditionally recognize extensions of simple IVs. After we've
5889 computed loop traversal counts and verified the range of the
5890 source IV, we'll reevaluate this as a GIV. */
5892 {
5895 {
5898 }
5899 }
5903 /* If this is a new register, we can't deal with it. */
5907 /* Check for biv or giv. */
5909 {
5913 {
5916 /* Form expression from giv and add benefit. Ensure this giv
5917 can derive another and subtract any needed adjustment if so. */
5919 /* Increasing the benefit here is risky. The only case in which it
5920 is arguably correct is if this is the only use of V. In other
5921 cases, this will artificially inflate the benefit of the current
5922 giv, and lead to suboptimal code. Thus, it is disabled, since
5923 potentially not reducing an only marginally beneficial giv is
5924 less harmful than reducing many givs that are not really
5925 beneficial. */
5926 {
5930 }
5943 {
5946 }
5947 else
5948 {
5951 }
5953 }
5956 do_default:
5957 /* If it isn't an induction variable, and it is invariant, we
5958 may be able to simplify things further by looking through
5959 the bits we just moved outside the loop. */
5961 {
5967 {
5968 /* Ok, we found a match. Substitute and simplify. */
5970 /* If we match another movable, we must use that, as
5971 this one is going away. */
5976 /* If consec is non-zero, this is a member of a group of
5977 instructions that were moved together. We handle this
5978 case only to the point of seeking to the last insn and
5979 looking for a REG_EQUAL. Fail if we don't find one. */
5981 {
5984 do
5985 {
5987 }
5993 }
5994 else
5995 {
5999 }
6002 {
6003 /* What we are most interested in is pointer
6004 arithmetic on invariants -- only take
6005 patterns we may be able to do something with. */
6011 {
6013 benefit);
6016 }
6021 {
6026 }
6027 }
6029 }
6030 }
6032 }
6034 /* Fall through to general case. */
6036 /* If invariant, return as USE (unless CONST_INT).
6037 Otherwise, not giv. */
6042 {
6051 }
6052 else
6054 }
6055 }
6057 /* This routine folds invariants such that there is only ever one
6058 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6060 static rtx
6063 {
6069 {
6072 }
6075 {
6078 }
6079 else
6080 {
6083 }
6084 }
6086 static rtx
6090 {
6092 {
6096 else
6099 }
6102 else
6105 }
6106 \f
6107 /* Help detect a giv that is calculated by several consecutive insns;
6108 for example,
6109 giv = biv * M
6110 giv = giv + A
6111 The caller has already identified the first insn P as having a giv as dest;
6112 we check that all other insns that set the same register follow
6113 immediately after P, that they alter nothing else,
6114 and that the result of the last is still a giv.
6116 The value is 0 if the reg set in P is not really a giv.
6117 Otherwise, the value is the amount gained by eliminating
6118 all the consecutive insns that compute the value.
6120 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6121 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6123 The coefficients of the ultimate giv value are stored in
6124 *MULT_VAL and *ADD_VAL. */
6126 static int
6131 rtx p;
6132 rtx src_reg;
6133 rtx dest_reg;
6138 {
6144 rtx temp;
6145 rtx set;
6147 /* Indicate that this is a giv so that we can update the value produced in
6148 each insn of the multi-insn sequence.
6150 This induction structure will be used only by the call to
6151 general_induction_var below, so we can allocate it on our stack.
6152 If this is a giv, our caller will replace the induct var entry with
6153 a new induction structure. */
6174 {
6178 /* If libcall, skip to end of call sequence. */
6189 /* Giv created by equivalent expression. */
6195 {
6199 count--;
6203 }
6205 {
6206 /* Allow insns that set something other than this giv to a
6207 constant. Such insns are needed on machines which cannot
6208 include long constants and should not disqualify a giv. */
6217 }
6218 }
6223 }
6224 \f
6225 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6226 represented by G1. If no such expression can be found, or it is clear that
6227 it cannot possibly be a valid address, 0 is returned.
6229 To perform the computation, we note that
6230 G1 = x * v + a and
6231 G2 = y * v + b
6232 where `v' is the biv.
6234 So G2 = (y/b) * G1 + (b - a*y/x).
6236 Note that MULT = y/x.
6238 Update: A and B are now allowed to be additive expressions such that
6239 B contains all variables in A. That is, computing B-A will not require
6240 subtracting variables. */
6242 static rtx
6245 {
6246 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
6251 /* If MULT is not 1, we cannot handle A with non-constants, since we
6252 would then be required to subtract multiples of the registers in A.
6253 This is theoretically possible, and may even apply to some Fortran
6254 constructs, but it is a lot of work and we do not attempt it here. */
6259 /* In general these structures are sorted top to bottom (down the PLUS
6260 chain), but not left to right across the PLUS. If B is a higher
6261 order giv than A, we can strip one level and recurse. If A is higher
6262 order, we'll eventually bail out, but won't know that until the end.
6263 If they are the same, we'll strip one level around this loop. */
6266 {
6278 /* We matched: remove one reg completely. */
6281 /* An alternate match. */
6284 /* An alternate match. */
6286 else
6287 {
6288 /* Indicates an extra register in B. Strip one level from B and
6289 recurse, hoping B was the higher order expression. */
6294 }
6295 }
6297 /* Here we are at the last level of A, go through the cases hoping to
6298 get rid of everything but a constant. */
6301 {
6314 }
6316 {
6318 }
6320 {
6321 return simplify_gen_binary (MINUS, GET_MODE (b) != VOIDmode ? GET_MODE (b) : GET_MODE (a), const0_rtx, a);
6322 }
6324 {
6329 else
6331 }
6336 }
6338 rtx
6341 {
6344 /* The value that G1 will be multiplied by must be a constant integer. Also,
6345 the only chance we have of getting a valid address is if b*c/a (see above
6346 for notation) is also an integer. */
6349 {
6354 }
6357 else
6358 {
6359 /* ??? Find out if the one is a multiple of the other? */
6361 }
6365 {
6366 /* Failed. If we've got a multiplication factor between G1 and G2,
6367 scale G1's addend and try again. */
6369 {
6373 {
6374 HOST_WIDE_INT m;
6378 }
6379 else
6380 {
6382 mult);
6383 }
6386 }
6387 }
6391 /* Form simplified final result. */
6396 else
6401 else
6402 {
6405 {
6409 }
6412 }
6413 }
6414 \f
6415 /* Return an rtx, if any, that expresses giv G2 as a function of the register
6416 represented by G1. This indicates that G2 should be combined with G1 and
6417 that G2 can use (either directly or via an address expression) a register
6418 used to represent G1. */
6420 static rtx
6423 {
6426 /* With the introduction of ext dependant givs, we must care for modes.
6427 G2 must not use a wider mode than G1. */
6437 /* If these givs are identical, they can be combined. We use the results
6438 of express_from because the addends are not in a canonical form, so
6439 rtx_equal_p is a weaker test. */
6440 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
6441 combination to be the other way round. */
6444 {
6446 }
6448 /* If G2 can be expressed as a function of G1 and that function is valid
6449 as an address and no more expensive than using a register for G2,
6450 the expression of G2 in terms of G1 can be used. */
6454 /* ??? Looses, especially with -fforce-addr, where *g2->location
6455 will always be a register, and so anything more complicated
6456 gets discarded. */
6457 #if 0
6458 #ifdef ADDRESS_COST
6460 #else
6462 #endif
6463 #endif
6464 )
6465 {
6467 }
6470 }
6471 \f
6472 /* Check each extension dependant giv in this class to see if its
6473 root biv is safe from wrapping in the interior mode, which would
6474 make the giv illegal. */
6476 static void
6480 {
6483 HOST_WIDE_INT start_val;
6488 /* Make sure the iteration data is available. We must have
6489 constants in order to be certain of no overflow. */
6490 /* ??? An unknown iteration count with an increment of +-1
6491 combined with friendly exit tests of against an invariant
6492 value is also ameanable to optimization. Not implemented. */
6498 /* Make sure the host can represent the arithmetic. */
6500 {
6502 HOST_WIDE_INT s_end_val;
6514 /* Check for host arithmatic overflow. */
6516 {
6518 HOST_WIDE_INT s_max;
6525 /* Check zero extension of biv ok. */
6527 /* Check for host arithmatic overflow. */
6528 && (neg_incr
6531 /* Check for target arithmetic overflow. */
6532 && (neg_incr
6535 {
6537 }
6539 /* Check sign extension of biv ok. */
6540 /* ??? While it is true that overflow with signed and pointer
6541 arithmetic is undefined, I fear too many programmers don't
6542 keep this fact in mind -- myself included on occasion.
6543 So leave alone with the signed overflow optimizations. */
6545 /* Check for host arithmatic overflow. */
6546 && (neg_incr
6549 /* Check for target arithmetic overflow. */
6550 && (neg_incr
6553 {
6555 }
6556 }
6557 }
6559 /* Invalidate givs that fail the tests. */
6562 {
6567 {
6576 /* We don't know whether this value is being used as either
6577 signed or unsigned, so to safely truncate we must satisfy
6578 both. The initial check here verifies the BIV itself;
6579 once that is successful we may check its range wrt the
6580 derived GIV. */
6582 {
6586 /* We know from the above that both endpoints are nonnegative,
6587 and that there is no wrapping. Verify that both endpoints
6588 are within the (signed) range of the outer mode. */
6591 }
6596 }
6599 {
6601 {
6605 }
6606 }
6607 else
6608 {
6610 {
6615 else
6616 {
6621 else
6623 }
6628 }
6630 }
6631 }
6632 }
6634 /* Generate a version of VALUE in a mode appropriate for initializing V. */
6636 rtx
6639 rtx value;
6640 {
6646 /* Recall that check_ext_dependant_givs verified that the known bounds
6647 of a biv did not overflow or wrap with respect to the extension for
6648 the giv. Therefore, constants need no additional adjustment. */
6652 /* Otherwise, we must adjust the value to compensate for the
6653 differing modes of the biv and the giv. */
6655 }
6656 \f
6657 struct combine_givs_stats
6658 {
6661 };
6663 static int
6667 {
6674 /* Stabilize the sort. */
6678 }
6680 /* Check all pairs of givs for iv_class BL and see if any can be combined with
6681 any other. If so, point SAME to the giv combined with and set NEW_REG to
6682 be an expression (in terms of the other giv's DEST_REG) equivalent to the
6683 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
6685 static void
6689 {
6690 /* Additional benefit to add for being combined multiple times. */
6698 /* Count givs, because bl->giv_count is incorrect here. */
6702 giv_count++;
6704 giv_array
6715 {
6717 rtx single_use;
6722 /* If a DEST_REG GIV is used only once, do not allow it to combine
6723 with anything, for in doing so we will gain nothing that cannot
6724 be had by simply letting the GIV with which we would have combined
6725 to be reduced on its own. The losage shows up in particular with
6726 DEST_ADDR targets on hosts with reg+reg addressing, though it can
6727 be seen elsewhere as well. */
6734 /* Add an additional weight for zero addends. */
6739 {
6740 rtx this_combine;
6745 {
6748 }
6749 }
6751 }
6753 /* Iterate, combining until we can't. */
6754 restart:
6758 {
6761 {
6767 }
6769 }
6772 {
6778 /* If it has already been combined, skip. */
6783 {
6786 /* If it has already been combined, skip. */
6788 {
6798 /* ??? The new final_[bg]iv_value code does a much better job
6799 of finding replaceable giv's, and hence this code may no
6800 longer be necessary. */
6804 /* To help optimize the next set of combinations, remove
6805 this giv from the benefits of other potential mates. */
6807 {
6811 }
6818 }
6819 }
6821 /* To help optimize the next set of combinations, remove
6822 this giv from the benefits of other potential mates. */
6824 {
6826 {
6830 }
6834 /* We've finished with this giv, and everything it touched.
6835 Restart the combination so that proper weights for the
6836 rest of the givs are properly taken into account. */
6837 /* ??? Ideally we would compact the arrays at this point, so
6838 as to not cover old ground. But sanely compacting
6839 can_combine is tricky. */
6841 }
6842 }
6844 /* Clean up. */
6847 }
6848 \f
6849 /* Generate sequence for REG = B * M + A. */
6851 static rtx
6857 {
6858 rtx seq;
6859 rtx result;
6862 /* Use unsigned arithmetic. */
6870 }
6873 /* Update registers created in insn sequence SEQ. */
6875 static void
6878 rtx seq;
6879 {
6880 /* Update register info for alias analysis. */
6883 {
6886 {
6890 }
6891 }
6892 else
6893 {
6897 }
6898 }
6901 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
6903 void
6910 basic_block before_bb;
6911 rtx before_insn;
6912 {
6913 rtx seq;
6916 {
6919 }
6921 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6924 /* Increase the lifetime of any invariants moved further in code. */
6931 /* It is possible that the expansion created lots of new registers.
6932 Iterate over the sequence we just created and record them all. */
6934 }
6937 /* Emit insns in loop pre-header to set REG = B * M + A. */
6939 void
6946 {
6947 rtx seq;
6949 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6952 /* Increase the lifetime of any invariants moved further in code.
6953 ???? Is this really necessary? */
6960 /* It is possible that the expansion created lots of new registers.
6961 Iterate over the sequence we just created and record them all. */
6963 }
6966 /* Emit insns after loop to set REG = B * M + A. */
6968 void
6975 {
6976 rtx seq;
6978 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
6983 /* It is possible that the expansion created lots of new registers.
6984 Iterate over the sequence we just created and record them all. */
6986 }
6990 /* Similar to gen_add_mult, but compute cost rather than generating
6991 sequence. */
6993 static int
6999 {
7009 {
7014 }
7017 }
7018 \f
7019 /* Test whether A * B can be computed without
7020 an actual multiply insn. Value is 1 if so. */
7022 static int
7024 rtx a;
7025 rtx b;
7026 {
7028 rtx tmp;
7031 /* If only one is constant, make it B. */
7035 /* If first constant, both constant, so don't need multiply. */
7039 /* If second not constant, neither is constant, so would need multiply. */
7043 /* One operand is constant, so might not need multiply insn. Generate the
7044 code for the multiply and see if a call or multiply, or long sequence
7045 of insns is generated. */
7053 {
7058 else
7060 {
7069 {
7072 }
7073 }
7074 }
7084 }
7085 \f
7086 /* Check to see if loop can be terminated by a "decrement and branch until
7087 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7088 Also try reversing an increment loop to a decrement loop
7089 to see if the optimization can be performed.
7090 Value is nonzero if optimization was performed. */
7092 /* This is useful even if the architecture doesn't have such an insn,
7093 because it might change a loops which increments from 0 to n to a loop
7094 which decrements from n to 0. A loop that decrements to zero is usually
7095 faster than one that increments from zero. */
7097 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7098 such as approx_final_value, biv_total_increment, loop_iterations, and
7099 final_[bg]iv_value. */
7101 static int
7105 {
7110 rtx reg;
7111 rtx jump_label;
7112 rtx final_value;
7113 rtx start_value;
7114 rtx new_add_val;
7115 rtx comparison;
7116 rtx before_comparison;
7117 rtx p;
7118 rtx jump;
7119 rtx first_compare;
7124 /* If last insn is a conditional branch, and the insn before tests a
7125 register value, try to optimize it. Otherwise, we can't do anything. */
7134 /* Try to compute whether the compare/branch at the loop end is one or
7135 two instructions. */
7141 else
7144 {
7145 /* If more than one condition is present to control the loop, then
7146 do not proceed, as this function does not know how to rewrite
7147 loop tests with more than one condition.
7149 Look backwards from the first insn in the last comparison
7150 sequence and see if we've got another comparison sequence. */
7152 rtx jump1;
7156 }
7158 /* Check all of the bivs to see if the compare uses one of them.
7159 Skip biv's set more than once because we can't guarantee that
7160 it will be zero on the last iteration. Also skip if the biv is
7161 used between its update and the test insn. */
7164 {
7169 first_compare))
7171 }
7176 /* Look for the case where the basic induction variable is always
7177 nonnegative, and equals zero on the last iteration.
7178 In this case, add a reg_note REG_NONNEG, which allows the
7179 m68k DBRA instruction to be used. */
7187 {
7188 /* Initial value must be greater than 0,
7189 init_val % -dec_value == 0 to ensure that it equals zero on
7190 the last iteration */
7196 {
7197 /* register always nonnegative, add REG_NOTE to branch */
7205 }
7207 /* If the decrement is 1 and the value was tested as >= 0 before
7208 the loop, then we can safely optimize. */
7210 {
7223 {
7231 }
7232 }
7233 }
7236 {
7237 /* Try to change inc to dec, so can apply above optimization. */
7238 /* Can do this if:
7239 all registers modified are induction variables or invariant,
7240 all memory references have non-overlapping addresses
7241 (obviously true if only one write)
7242 allow 2 insns for the compare/jump at the end of the loop. */
7243 /* Also, we must avoid any instructions which use both the reversed
7244 biv and another biv. Such instructions will fail if the loop is
7245 reversed. We meet this condition by requiring that either
7246 no_use_except_counting is true, or else that there is only
7247 one biv. */
7249 /* 1 if the iteration var is used only to count iterations. */
7251 /* 1 if the loop has no memory store, or it has a single memory store
7252 which is reversible. */
7256 {
7259 /* If there are no givs for this biv, and the only exit is the
7260 fall through at the end of the loop, then
7261 see if perhaps there are no uses except to count. */
7265 {
7270 /* An insn that sets the biv is okay. */
7271 ;
7275 {
7276 /* If either of these insns uses the biv and sets a pseudo
7277 that has more than one usage, then the biv has uses
7278 other than counting since it's used to derive a value
7279 that is used more than one time. */
7281 regs);
7283 {
7286 }
7287 }
7289 {
7292 }
7293 }
7294 }
7297 /* No need to worry about MEMs. */
7298 ;
7300 {
7305 /* If the loop has a single store, and the destination address is
7306 invariant, then we can't reverse the loop, because this address
7307 might then have the wrong value at loop exit.
7308 This would work if the source was invariant also, however, in that
7309 case, the insn should have been moved out of the loop. */
7312 {
7315 reversible_mem_store
7322 /* If the store depends on a register that is set after the
7323 store, it depends on the initial value, and is thus not
7324 reversible. */
7326 {
7333 }
7334 }
7335 }
7336 else
7339 /* This code only acts for innermost loops. Also it simplifies
7340 the memory address check by only reversing loops with
7341 zero or one memory access.
7342 Two memory accesses could involve parts of the same array,
7343 and that can't be reversed.
7344 If the biv is used only for counting, than we don't need to worry
7345 about all these things. */
7350 && reversible_mem_store
7355 {
7356 rtx tem;
7358 /* Loop can be reversed. */
7362 /* Now check other conditions:
7364 The increment must be a constant, as must the initial value,
7365 and the comparison code must be LT.
7367 This test can probably be improved since +/- 1 in the constant
7368 can be obtained by changing LT to LE and vice versa; this is
7369 confusing. */
7372 /* for constants, LE gets turned into LT */
7376 {
7387 comparison_const_width
7389 else
7390 comparison_const_width
7394 comparison_sign_mask
7397 /* If the comparison value is not a loop invariant, then we
7398 can not reverse this loop.
7400 ??? If the insns which initialize the comparison value as
7401 a whole compute an invariant result, then we could move
7402 them out of the loop and proceed with loop reversal. */
7410 /* Normalize the initial value if it is an integer and
7411 has no other use except as a counter. This will allow
7412 a few more loops to be reversed. */
7416 {
7418 /* The code below requires comparison_val to be a multiple
7419 of add_val in order to do the loop reversal, so
7420 round up comparison_val to a multiple of add_val.
7421 Since comparison_value is constant, we know that the
7422 current comparison code is LT. */
7424 comparison_val
7426 /* We postpone overflow checks for COMPARISON_VAL here;
7427 even if there is an overflow, we might still be able to
7428 reverse the loop, if converting the loop exit test to
7429 NE is possible. */
7431 }
7433 /* First check if we can do a vanilla loop reversal. */
7435 /* If we have a decrement_and_branch_on_count,
7436 prefer the NE test, since this will allow that
7437 instruction to be generated. Note that we must
7438 use a vanilla loop reversal if the biv is used to
7439 calculate a giv or has a non-counting use. */
7440 #if ! defined (HAVE_decrement_and_branch_until_zero) \
7441 && defined (HAVE_decrement_and_branch_on_count)
7445 #endif
7447 /* Now do postponed overflow checks on COMPARISON_VAL. */
7450 {
7451 /* Register will always be nonnegative, with value
7452 0 on last iteration */
7456 }
7460 {
7463 }
7464 else
7470 /* If the initial value is not zero, or if the comparison
7471 value is not an exact multiple of the increment, then we
7472 can not reverse this loop. */
7475 {
7478 }
7479 else
7480 {
7483 }
7487 /* Reset these in case we normalized the initial value
7488 and comparison value above. */
7491 {
7493 final_value
7495 }
7498 /* Save some info needed to produce the new insns. */
7505 /* Set start_value; if this is not a CONST_INT, we need
7506 to generate a SUB.
7507 Initialize biv to start_value before loop start.
7508 The old initializing insn will be deleted as a
7509 dead store by flow.c. */
7512 {
7515 }
7517 {
7520 enum insn_code icode
7529 start_value
7536 }
7538 {
7540 enum insn_code icode
7548 start_value
7552 initial_value)));
7553 }
7554 else
7555 /* We could handle the other cases too, but it'll be
7556 better to have a testcase first. */
7559 /* We may not have a single insn which can increment a reg, so
7560 create a sequence to hold all the insns from expand_inc. */
7569 /* Update biv info to reflect its new status. */
7574 /* Update loop info. */
7583 /* Inc LABEL_NUSES so that delete_insn will
7584 not delete the label. */
7587 /* Emit an insn after the end of the loop to set the biv's
7588 proper exit value if it is used anywhere outside the loop. */
7594 /* Delete compare/branch at end of loop. */
7599 /* Add new compare/branch insn at end of loop. */
7611 ;
7617 {
7619 {
7620 /* Increment of LABEL_NUSES done above. */
7621 /* Register is now always nonnegative,
7622 so add REG_NONNEG note to the branch. */
7625 }
7627 }
7629 /* No insn may reference both the reversed and another biv or it
7630 will fail (see comment near the top of the loop reversal
7631 code).
7632 Earlier on, we have verified that the biv has no use except
7633 counting, or it is the only biv in this function.
7634 However, the code that computes no_use_except_counting does
7635 not verify reg notes. It's possible to have an insn that
7636 references another biv, and has a REG_EQUAL note with an
7637 expression based on the reversed biv. To avoid this case,
7638 remove all REG_EQUAL notes based on the reversed biv
7639 here. */
7642 {
7645 /* If this is a set of a GIV based on the reversed biv, any
7646 REG_EQUAL notes should still be correct. */
7653 {
7658 else
7660 }
7661 }
7663 /* Mark that this biv has been reversed. Each giv which depends
7664 on this biv, and which is also live past the end of the loop
7665 will have to be fixed up. */
7670 {
7674 else
7676 }
7679 }
7680 }
7681 }
7684 }
7685 \f
7686 /* Verify whether the biv BL appears to be eliminable,
7687 based on the insns in the loop that refer to it.
7689 If ELIMINATE_P is non-zero, actually do the elimination.
7691 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
7692 determine whether invariant insns should be placed inside or at the
7693 start of the loop. */
7695 static int
7701 {
7704 rtx p;
7706 /* Scan all insns in the loop, stopping if we find one that uses the
7707 biv in a way that we cannot eliminate. */
7710 {
7715 /* If this is a libcall that sets a giv, skip ahead to its end. */
7717 {
7721 {
7726 {
7733 }
7734 }
7735 }
7740 {
7746 }
7747 }
7750 {
7755 }
7758 }
7759 \f
7760 /* INSN and REFERENCE are instructions in the same insn chain.
7761 Return non-zero if INSN is first. */
7763 int
7766 {
7770 {
7771 /* Start with test for not first so that INSN == REFERENCE yields not
7772 first. */
7778 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
7779 previous insn, hence the <= comparison below does not work if
7780 P is a note. */
7791 }
7792 }
7794 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
7795 the offset that we have to take into account due to auto-increment /
7796 div derivation is zero. */
7797 static int
7800 rtx insn;
7801 {
7802 /* If the giv V had the auto-inc address optimization applied
7803 to it, and INSN occurs between the giv insn and the biv
7804 insn, then we'd have to adjust the value used here.
7805 This is rare, so we don't bother to make this possible. */
7814 }
7816 /* If BL appears in X (part of the pattern of INSN), see if we can
7817 eliminate its use. If so, return 1. If not, return 0.
7819 If BIV does not appear in X, return 1.
7821 If ELIMINATE_P is non-zero, actually do the elimination.
7822 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
7823 Depending on how many items have been moved out of the loop, it
7824 will either be before INSN (when WHERE_INSN is non-zero) or at the
7825 start of the loop (when WHERE_INSN is zero). */
7827 static int
7833 basic_block where_bb;
7834 rtx where_insn;
7835 {
7841 #ifdef HAVE_cc0
7843 #endif
7849 {
7851 /* If we haven't already been able to do something with this BIV,
7852 we can't eliminate it. */
7858 /* If this sets the BIV, it is not a problem. */
7862 /* If this is an insn that defines a giv, it is also ok because
7863 it will go away when the giv is reduced. */
7868 #ifdef HAVE_cc0
7870 {
7871 /* Can replace with any giv that was reduced and
7872 that has (MULT_VAL != 0) and (ADD_VAL == 0).
7873 Require a constant for MULT_VAL, so we know it's nonzero.
7874 ??? We disable this optimization to avoid potential
7875 overflows. */
7883 {
7890 /* If the giv has the opposite direction of change,
7891 then reverse the comparison. */
7895 else
7898 /* We can probably test that giv's reduced reg. */
7901 }
7903 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
7904 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
7905 Require a constant for MULT_VAL, so we know it's nonzero.
7906 ??? Do this only if ADD_VAL is a pointer to avoid a potential
7907 overflow problem. */
7919 {
7926 /* If the giv has the opposite direction of change,
7927 then reverse the comparison. */
7931 else
7935 /* Replace biv with the giv's reduced register. */
7940 /* Insn doesn't support that constant or invariant. Copy it
7941 into a register (it will be a loop invariant.) */
7945 where_insn);
7947 /* Substitute the new register for its invariant value in
7948 the compare expression. */
7952 }
7953 }
7954 #endif
7961 /* See if either argument is the biv. */
7966 else
7970 {
7971 /* First try to replace with any giv that has constant positive
7972 mult_val and constant add_val. We might be able to support
7973 negative mult_val, but it seems complex to do it in general. */
7985 {
7992 /* Replace biv with the giv's reduced reg. */
7995 /* If all constants are actually constant integers and
7996 the derived constant can be directly placed in the COMPARE,
7997 do so. */
8001 {
8006 }
8007 else
8008 {
8009 /* Otherwise, load it into a register. */
8015 }
8018 }
8020 /* Look for giv with positive constant mult_val and nonconst add_val.
8021 Insert insns to calculate new compare value.
8022 ??? Turn this off due to possible overflow. */
8030 {
8031 rtx tem;
8041 /* Replace biv with giv's reduced register. */
8045 /* Compute value to compare against. */
8049 /* Use it in this insn. */
8053 }
8054 }
8056 {
8058 {
8059 /* Look for giv with constant positive mult_val and nonconst
8060 add_val. Insert insns to compute new compare value.
8061 ??? Turn this off due to possible overflow. */
8068 {
8069 rtx tem;
8079 /* Replace biv with giv's reduced register. */
8083 /* Compute value to compare against. */
8090 }
8091 }
8093 /* This code has problems. Basically, you can't know when
8094 seeing if we will eliminate BL, whether a particular giv
8095 of ARG will be reduced. If it isn't going to be reduced,
8096 we can't eliminate BL. We can try forcing it to be reduced,
8097 but that can generate poor code.
8099 The problem is that the benefit of reducing TV, below should
8100 be increased if BL can actually be eliminated, but this means
8101 we might have to do a topological sort of the order in which
8102 we try to process biv. It doesn't seem worthwhile to do
8103 this sort of thing now. */
8105 #if 0
8106 /* Otherwise the reg compared with had better be a biv. */
8111 /* Look for a pair of givs, one for each biv,
8112 with identical coefficients. */
8114 {
8126 {
8133 /* Replace biv with its giv's reduced reg. */
8135 /* Replace other operand with the other giv's
8136 reduced reg. */
8139 }
8140 }
8141 #endif
8142 }
8144 /* If we get here, the biv can't be eliminated. */
8148 /* If this address is a DEST_ADDR giv, it doesn't matter if the
8149 biv is used in it, since it will be replaced. */
8157 }
8159 /* See if any subexpression fails elimination. */
8162 {
8164 {
8177 }
8178 }
8181 }
8182 \f
8183 /* Return nonzero if the last use of REG
8184 is in an insn following INSN in the same basic block. */
8186 static int
8188 rtx reg;
8189 rtx insn;
8190 {
8191 rtx n;
8195 {
8198 }
8200 }
8201 \f
8202 /* Called via `note_stores' to record the initial value of a biv. Here we
8203 just record the location of the set and process it later. */
8205 static void
8207 rtx dest;
8208 rtx set;
8210 {
8221 /* If this is the first set found, record it. */
8223 {
8226 }
8227 }
8228 \f
8229 /* If any of the registers in X are "old" and currently have a last use earlier
8230 than INSN, update them to have a last use of INSN. Their actual last use
8231 will be the previous insn but it will not have a valid uid_luid so we can't
8232 use it. X must be a source expression only. */
8234 static void
8236 rtx x;
8237 rtx insn;
8238 {
8239 /* Check for the case where INSN does not have a valid luid. In this case,
8240 there is no need to modify the regno_last_uid, as this can only happen
8241 when code is inserted after the loop_end to set a pseudo's final value,
8242 and hence this insn will never be the last use of x.
8243 ???? This comment is not correct. See for example loop_givs_reduce.
8244 This may insert an insn before another new insn. */
8248 {
8250 }
8251 else
8252 {
8256 {
8262 }
8263 }
8264 }
8265 \f
8266 /* Given an insn INSN and condition COND, return the condition in a
8267 canonical form to simplify testing by callers. Specifically:
8269 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
8270 (2) Both operands will be machine operands; (cc0) will have been replaced.
8271 (3) If an operand is a constant, it will be the second operand.
8272 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
8273 for GE, GEU, and LEU.
8275 If the condition cannot be understood, or is an inequality floating-point
8276 comparison which needs to be reversed, 0 will be returned.
8278 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
8280 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8281 insn used in locating the condition was found. If a replacement test
8282 of the condition is desired, it should be placed in front of that
8283 insn and we will be sure that the inputs are still valid.
8285 If WANT_REG is non-zero, we wish the condition to be relative to that
8286 register, if possible. Therefore, do not canonicalize the condition
8287 further. */
8289 rtx
8291 rtx insn;
8292 rtx cond;
8295 rtx want_reg;
8296 {
8299 rtx set;
8300 rtx tem;
8312 {
8315 }
8320 /* If we are comparing a register with zero, see if the register is set
8321 in the previous insn to a COMPARE or a comparison operation. Perform
8322 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
8323 in cse.c */
8328 {
8329 /* Set non-zero when we find something of interest. */
8332 #ifdef HAVE_cc0
8333 /* If comparison with cc0, import actual comparison from compare
8334 insn. */
8336 {
8347 }
8348 #endif
8350 /* If this is a COMPARE, pick up the two things being compared. */
8352 {
8356 }
8360 /* Go back to the previous insn. Stop if it is not an INSN. We also
8361 stop if it isn't a single set or if it has a REG_INC note because
8362 we don't want to bother dealing with it. */
8370 /* If this is setting OP0, get what it sets it to if it looks
8371 relevant. */
8373 {
8376 /* ??? We may not combine comparisons done in a CCmode with
8377 comparisons not done in a CCmode. This is to aid targets
8378 like Alpha that have an IEEE compliant EQ instruction, and
8379 a non-IEEE compliant BEQ instruction. The use of CCmode is
8380 actually artificial, simply to prevent the combination, but
8381 should not affect other platforms.
8383 However, we must allow VOIDmode comparisons to match either
8384 CCmode or non-CCmode comparison, because some ports have
8385 modeless comparisons inside branch patterns.
8387 ??? This mode check should perhaps look more like the mode check
8388 in simplify_comparison in combine. */
8396 && (STORE_FLAG_VALUE
8399 #ifdef FLOAT_STORE_FLAG_VALUE
8402 && (REAL_VALUE_NEGATIVE
8404 #endif
8405 ))
8416 && (STORE_FLAG_VALUE
8419 #ifdef FLOAT_STORE_FLAG_VALUE
8422 && (REAL_VALUE_NEGATIVE
8424 #endif
8425 ))
8431 {
8432 /* We might have reversed a LT to get a GE here. But this wasn't
8433 actually the comparison of data, so we don't flag that we
8434 have had to reverse the condition. */
8438 }
8439 else
8441 }
8444 /* If this sets OP0, but not directly, we have to give up. */
8448 {
8452 {
8458 }
8463 }
8464 }
8466 /* If constant is first, put it last. */
8470 /* If OP0 is the result of a comparison, we weren't able to find what
8471 was really being compared, so fail. */
8475 /* Canonicalize any ordered comparison with integers involving equality
8476 if we can do computations in the relevant mode and we do not
8477 overflow. */
8482 {
8485 unsigned HOST_WIDE_INT max_val
8489 {
8495 /* When cross-compiling, const_val might be sign-extended from
8496 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
8516 }
8517 }
8519 /* If this was floating-point and we reversed anything other than an
8520 EQ or NE or (UN)ORDERED, return zero. */
8522 && did_reverse_condition
8524 && ! flag_fast_math
8528 #ifdef HAVE_cc0
8529 /* Never return CC0; return zero instead. */
8532 #endif
8535 }
8537 /* Given a jump insn JUMP, return the condition that will cause it to branch
8538 to its JUMP_LABEL. If the condition cannot be understood, or is an
8539 inequality floating-point comparison which needs to be reversed, 0 will
8540 be returned.
8542 If EARLIEST is non-zero, it is a pointer to a place where the earliest
8543 insn used in locating the condition was found. If a replacement test
8544 of the condition is desired, it should be placed in front of that
8545 insn and we will be sure that the inputs are still valid. */
8547 rtx
8549 rtx jump;
8551 {
8552 rtx cond;
8554 rtx set;
8556 /* If this is not a standard conditional jump, we can't parse it. */
8564 /* If this branches to JUMP_LABEL when the condition is false, reverse
8565 the condition. */
8566 reverse
8571 }
8573 /* Similar to above routine, except that we also put an invariant last
8574 unless both operands are invariants. */
8576 rtx
8579 rtx x;
8580 {
8590 }
8592 /* Scan the function and determine whether it has indirect (computed) jumps.
8594 This is taken mostly from flow.c; similar code exists elsewhere
8595 in the compiler. It may be useful to put this into rtlanal.c. */
8596 static int
8598 rtx start;
8599 {
8600 rtx insn;
8607 }
8609 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
8610 documentation for LOOP_MEMS for the definition of `appropriate'.
8611 This function is called from prescan_loop via for_each_rtx. */
8613 static int
8617 {
8626 {
8631 /* We're not interested in MEMs that are only clobbered. */
8635 /* We're not interested in the MEM associated with a
8636 CONST_DOUBLE, so there's no need to traverse into this. */
8640 /* We're not interested in any MEMs that only appear in notes. */
8644 /* This is not a MEM. */
8646 }
8648 /* See if we've already seen this MEM. */
8651 {
8653 /* The modes of the two memory accesses are different. If
8654 this happens, something tricky is going on, and we just
8655 don't optimize accesses to this MEM. */
8659 }
8661 /* Resize the array, if necessary. */
8663 {
8666 else
8672 }
8674 /* Actually insert the MEM. */
8676 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
8677 because we can't put it in a register. We still store it in the
8678 table, though, so that if we see the same address later, but in a
8679 non-BLK mode, we'll not think we can optimize it at that point. */
8685 }
8688 /* Allocate REGS->ARRAY or reallocate it if it is too small.
8690 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
8691 register that is modified by an insn between FROM and TO. If the
8692 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
8693 more, stop incrementing it, to avoid overflow.
8695 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
8696 register I is used, if it is only used once. Otherwise, it is set
8697 to 0 (for no uses) or const0_rtx for more than one use. This
8698 parameter may be zero, in which case this processing is not done.
8700 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
8701 optimize register I.
8703 Store in *COUNT_PTR the number of actual instructions
8704 in the loop. We use this to decide what is worth moving out. */
8706 static void
8711 {
8714 /* last_set[n] is nonzero iff reg n has been set in the current
8715 basic block. In that case, it is the insn that last set reg n. */
8717 rtx insn;
8724 /* Grow the regs array if not allocated or too small. */
8726 {
8732 /* Zero the new elements. */
8735 }
8737 /* Clear previously scanned fields but do not clear n_times_set. */
8739 {
8743 }
8747 /* Scan the loop, recording register usage. */
8750 {
8752 {
8755 /* Record registers that have exactly one use. */
8758 /* Include uses in REG_EQUAL notes. */
8766 {
8770 last_set);
8771 }
8772 }
8776 }
8779 {
8782 }
8784 #ifdef AVOID_CCMODE_COPIES
8785 /* Don't try to move insns which set CC registers if we should not
8786 create CCmode register copies. */
8790 #endif
8792 /* Set regs->array[I].n_times_set for the new registers. */
8798 }
8801 /* Move MEMs into registers for the duration of the loop. */
8803 static void
8806 {
8811 rtx p;
8813 rtx end_label;
8814 /* Nonzero if the next instruction may never be executed. */
8821 /* We cannot use next_label here because it skips over normal insns. */
8826 /* Check to see if it's possible that some instructions in the loop are
8827 never executed. Also check if there is a goto out of the loop other
8828 than right after the end of the loop. */
8832 {
8836 /* If we enter the loop in the middle, and scan
8837 around to the beginning, don't set maybe_never
8838 for that. This must be an unconditional jump,
8839 otherwise the code at the top of the loop might
8840 never be executed. Unconditional jumps are
8841 followed a by barrier then loop end. */
8846 {
8847 /* If this is a jump outside of the loop but not right
8848 after the end of the loop, we would have to emit new fixup
8849 sequences for each such label. */
8857 /* Something complicated. */
8859 else
8860 /* If there are any more instructions in the loop, they
8861 might not be reached. */
8863 }
8866 }
8868 /* Find start of the extended basic block that enters the loop. */
8872 ;
8876 /* Build table of mems that get set to constant values before the
8877 loop. */
8881 /* Actually move the MEMs. */
8883 {
8884 regset_head load_copies;
8885 regset_head store_copies;
8887 rtx reg;
8889 rtx mem_list_entry;
8893 /* There's no telling whether or not MEM is modified. */
8896 /* Go through the MEMs written to in the loop to see if this
8897 one is aliased by one of them. */
8900 {
8905 {
8906 /* MEM is indeed aliased by this store. */
8909 }
8911 }
8917 /* If this MEM is written to, we must be sure that there
8918 are no reads from another MEM that aliases this one. */
8920 {
8924 {
8928 VOIDmode,
8930 rtx_varies_p))
8931 {
8932 /* It's not safe to hoist loop_info->mems[i] out of
8933 the loop because writes to it might not be
8934 seen by reads from loop_info->mems[j]. */
8937 }
8938 }
8939 }
8942 /* We can't access the MEM outside the loop; it might
8943 cause a trap that wouldn't have happened otherwise. */
8947 /* We thought we were going to lift this MEM out of the
8948 loop, but later discovered that we could not. */
8954 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
8955 order to keep scan_loop from moving stores to this MEM
8956 out of the loop just because this REG is neither a
8957 user-variable nor used in the loop test. */
8962 /* Now, replace all references to the MEM with the
8963 corresponding pesudos. */
8968 {
8970 {
8971 rtx set;
8975 /* See if this copies the mem into a register that isn't
8976 modified afterwards. We'll try to do copy propagation
8977 a little further on. */
8979 /* @@@ This test is _way_ too conservative. */
8980 && ! maybe_never
8988 /* See if this copies the mem from a register that isn't
8989 modified afterwards. We'll try to remove the
8990 redundant copy later on by doing a little register
8991 renaming and copy propagation. This will help
8992 to untangle things for the BIV detection code. */
8994 && ! maybe_never
9002 /* Replace the memory reference with the shadow register. */
9005 }
9010 }
9013 /* We couldn't replace all occurrences of the MEM. */
9015 else
9016 {
9017 /* Load the memory immediately before LOOP->START, which is
9018 the NOTE_LOOP_BEG. */
9020 rtx set;
9026 {
9030 {
9034 /* Extending hard register lifetimes cuases crash
9035 on SRC targets. Doing so on non-SRC is
9036 probably also not good idea, since we most
9037 probably have pseudoregister equivalence as
9038 well. */
9041 }
9042 /* Use the constant equivalence if that is cheap enough. */
9048 {
9051 }
9053 /* If best_equiv is nonzero, we know that MEM is set to a
9054 constant or register before the loop. We will use this
9055 knowledge to initialize the shadow register with that
9056 constant or reg rather than by loading from MEM. */
9059 }
9068 {
9070 {
9073 }
9075 /* Store the memory immediately after END, which is
9076 the NOTE_LOOP_END. */
9079 }
9082 {
9087 }
9089 /* Attempt a bit of copy propagation. This helps untangle the
9090 data flow, and enables {basic,general}_induction_var to find
9091 more bivs/givs. */
9092 EXECUTE_IF_SET_IN_REG_SET
9094 {
9096 });
9099 EXECUTE_IF_SET_IN_REG_SET
9101 {
9103 });
9105 }
9106 }
9109 {
9110 /* Now, we need to replace all references to the previous exit
9111 label with the new one. */
9112 rtx_pair rr;
9117 {
9120 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
9121 field. This is not handled by for_each_rtx because it doesn't
9122 handle unprinted ('0') fields. We need to update JUMP_LABEL
9123 because the immediately following unroll pass will use it.
9124 replace_label would not work anyways, because that only handles
9125 LABEL_REFs. */
9128 }
9129 }
9132 }
9134 /* For communication between note_reg_stored and its caller. */
9135 struct note_reg_stored_arg
9136 {
9138 rtx reg;
9139 };
9141 /* Called via note_stores, record in SET_SEEN whether X, which is written,
9142 is equal to ARG. */
9143 static void
9147 {
9151 }
9153 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
9154 There must be exactly one insn that sets this pseudo; it will be
9155 deleted if all replacements succeed and we can prove that the register
9156 is not used after the loop. */
9158 static void
9161 rtx replacement;
9163 {
9164 /* This is the reg that we are copying from. */
9167 rtx insn;
9168 /* These help keep track of whether we replaced all uses of the reg. */
9175 {
9176 rtx set;
9178 /* Only substitute within one extended basic block from the initializing
9179 insn. */
9186 /* Is this the initializing insn? */
9191 {
9198 }
9200 /* Only substitute after seeing the initializing insn. */
9202 {
9209 /* Stop replacing when REPLACEMENT is modified. */
9215 }
9216 }
9220 {
9224 {
9230 }
9233 }
9234 }
9236 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
9237 loop LOOP if the order of the sets of these registers can be
9238 swapped. There must be exactly one insn within the loop that sets
9239 this pseudo followed immediately by a move insn that sets
9240 REPLACEMENT with REGNO. */
9241 static void
9244 rtx replacement;
9246 {
9247 rtx insn;
9248 rtx set;
9256 {
9257 /* Search for the insn that copies REGNO to NEW_REGNO? */
9265 }
9268 {
9269 rtx prev_insn;
9270 rtx prev_set;
9272 /* Some DEF-USE info would come in handy here to make this
9273 function more general. For now, just check the previous insn
9274 which is the most likely candidate for setting REGNO. */
9282 {
9283 /* We have:
9284 (set (reg regno) (expr))
9285 (set (reg new_regno) (reg regno))
9287 so try converting this to:
9288 (set (reg new_regno) (expr))
9289 (set (reg regno) (reg new_regno))
9291 The former construct is often generated when a global
9292 variable used for an induction variable is shadowed by a
9293 register (NEW_REGNO). The latter construct improves the
9294 chances of GIV replacement and BIV elimination. */
9304 {
9311 /* Update first use of REGNO. */
9315 /* Now perform copy propagation to hopefully
9316 remove all uses of REGNO within the loop. */
9318 }
9319 }
9320 }
9321 }
9323 /* Replace MEM with its associated pseudo register. This function is
9324 called from load_mems via for_each_rtx. DATA is actually a pointer
9325 to a structure describing the instruction currently being scanned
9326 and the MEM we are currently replacing. */
9328 static int
9332 {
9340 {
9345 /* We're not interested in the MEM associated with a
9346 CONST_DOUBLE, so there's no need to traverse into one. */
9350 /* This is not a MEM. */
9352 }
9355 /* This is not the MEM we are currently replacing. */
9358 /* Actually replace the MEM. */
9362 }
9364 static void
9366 rtx insn;
9367 rtx mem;
9368 rtx reg;
9369 {
9370 loop_replace_args args;
9377 }
9379 /* Replace one register with another. Called through for_each_rtx; PX points
9380 to the rtx being scanned. DATA is actually a pointer to
9381 a structure of arguments. */
9383 static int
9387 {
9398 }
9400 static void
9402 rtx insn;
9403 rtx reg;
9404 rtx replacement;
9405 {
9406 loop_replace_args args;
9413 }
9415 /* Replace occurrences of the old exit label for the loop with the new
9416 one. DATA is an rtx_pair containing the old and new labels,
9417 respectively. */
9419 static int
9423 {
9442 }
9443 \f
9444 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
9445 (ignored in the interim). */
9447 static rtx
9450 basic_block where_bb ATTRIBUTE_UNUSED;
9451 rtx where_insn;
9452 rtx pattern;
9453 {
9455 }
9458 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
9459 in basic block WHERE_BB (ignored in the interim) within the loop
9460 otherwise hoist PATTERN into the loop pre-header. */
9462 static rtx
9465 basic_block where_bb ATTRIBUTE_UNUSED;
9466 rtx where_insn;
9467 rtx pattern;
9468 {
9472 }
9475 /* Hoist insn for PATTERN into the loop pre-header. */
9477 rtx
9480 rtx pattern;
9481 {
9483 }
9486 /* Sink insn for PATTERN after the loop end. */
9488 rtx
9491 rtx pattern;
9492 {
9494 }
9497 /* If the loop has multiple exits, emit insn for PATTERN before the
9498 loop to ensure that it will always be executed no matter how the
9499 loop exits. Otherwise, emit the insn for PATTERN after the loop,
9500 since this is slightly more efficient. */
9502 static rtx
9505 rtx pattern;
9506 {
9509 else
9511 }
9512 \f
9513 static void
9518 {
9526 iv_num++;
9531 {
9534 }
9535 }
9538 static void
9543 {
9545 rtx incr;
9556 {
9559 }
9561 {
9564 }
9568 {
9572 }
9575 {
9579 }
9581 /* List the increments. */
9583 {
9587 }
9589 /* List the givs. */
9591 {
9596 else
9599 }
9600 }
9603 static void
9608 {
9619 {
9623 }
9626 }
9629 static void
9634 {
9641 else
9657 {
9659 {
9671 }
9672 }
9683 {
9687 }
9690 }
9693 void
9696 {
9698 }
9701 void
9704 {
9706 }
9709 void
9712 {
9714 }
9717 void
9720 {
9722 }
9725 #define LOOP_BLOCK_NUM_1(INSN) \
9726 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
9728 /* The notes do not have an assigned block, so look at the next insn. */
9729 #define LOOP_BLOCK_NUM(INSN) \
9730 ((INSN) ? (GET_CODE (INSN) == NOTE \
9731 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
9732 : LOOP_BLOCK_NUM_1 (INSN)) \
9733 : -1)
9735 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
9737 static void
9742 {
9743 rtx label;
9748 /* Print diagnostics to compare our concept of a loop with
9749 what the loop notes say. */
9764 {
9784 {
9787 {
9790 }
9791 }
9794 /* This can happen when a marked loop appears as two nested loops,
9795 say from while (a || b) {}. The inner loop won't match
9796 the loop markers but the outer one will. */
9799 }
9800 }
9802 /* Call this function from the debugger to dump LOOP. */
9804 void
9807 {
9809 }
9811 /* Call this function from the debugger to dump LOOPS. */
9813 void
9816 {
9818 }