| blob | 55c9834b2885c787c1f563f655a625d1db80d2da |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables.
27 Basic induction variables (BIVs) are a pseudo registers which are set within
28 a loop only by incrementing or decrementing its value. General induction
29 variables (GIVs) are pseudo registers with a value which is a linear function
30 of a basic induction variable. BIVs are recognized by `basic_induction_var';
31 GIVs by `general_induction_var'.
33 Once induction variables are identified, strength reduction is applied to the
34 general induction variables, and induction variable elimination is applied to
35 the basic induction variables.
37 It also finds cases where
38 a register is set within the loop by zero-extending a narrower value
39 and changes these to zero the entire register once before the loop
40 and merely copy the low part within the loop.
42 Most of the complexity is in heuristics to decide when it is worth
43 while to do these things. */
70 /* Not really meaningful values, but at least something. */
71 #ifndef SIMULTANEOUS_PREFETCHES
72 #define SIMULTANEOUS_PREFETCHES 3
73 #endif
74 #ifndef PREFETCH_BLOCK
75 #define PREFETCH_BLOCK 32
76 #endif
77 #ifndef HAVE_prefetch
78 #define HAVE_prefetch 0
79 #define CODE_FOR_prefetch 0
80 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
81 #endif
83 /* Give up the prefetch optimizations once we exceed a given threshold.
84 It is unlikely that we would be able to optimize something in a loop
85 with so many detected prefetches. */
86 #define MAX_PREFETCHES 100
87 /* The number of prefetch blocks that are beneficial to fetch at once before
88 a loop with a known (and low) iteration count. */
89 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
90 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
91 since it is likely that the data are already in the cache. */
92 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
94 /* Parameterize some prefetch heuristics so they can be turned on and off
95 easily for performance testing on new architectures. These can be
96 defined in target-dependent files. */
98 /* Prefetch is worthwhile only when loads/stores are dense. */
99 #ifndef PREFETCH_ONLY_DENSE_MEM
100 #define PREFETCH_ONLY_DENSE_MEM 1
101 #endif
103 /* Define what we mean by "dense" loads and stores; This value divided by 256
104 is the minimum percentage of memory references that worth prefetching. */
105 #ifndef PREFETCH_DENSE_MEM
106 #define PREFETCH_DENSE_MEM 220
107 #endif
109 /* Do not prefetch for a loop whose iteration count is known to be low. */
110 #ifndef PREFETCH_NO_LOW_LOOPCNT
111 #define PREFETCH_NO_LOW_LOOPCNT 1
112 #endif
114 /* Define what we mean by a "low" iteration count. */
115 #ifndef PREFETCH_LOW_LOOPCNT
116 #define PREFETCH_LOW_LOOPCNT 32
117 #endif
119 /* Do not prefetch for a loop that contains a function call; such a loop is
120 probably not an internal loop. */
121 #ifndef PREFETCH_NO_CALL
122 #define PREFETCH_NO_CALL 1
123 #endif
125 /* Do not prefetch accesses with an extreme stride. */
126 #ifndef PREFETCH_NO_EXTREME_STRIDE
127 #define PREFETCH_NO_EXTREME_STRIDE 1
128 #endif
130 /* Define what we mean by an "extreme" stride. */
131 #ifndef PREFETCH_EXTREME_STRIDE
132 #define PREFETCH_EXTREME_STRIDE 4096
133 #endif
135 /* Define a limit to how far apart indices can be and still be merged
136 into a single prefetch. */
137 #ifndef PREFETCH_EXTREME_DIFFERENCE
138 #define PREFETCH_EXTREME_DIFFERENCE 4096
139 #endif
141 /* Issue prefetch instructions before the loop to fetch data to be used
142 in the first few loop iterations. */
143 #ifndef PREFETCH_BEFORE_LOOP
144 #define PREFETCH_BEFORE_LOOP 1
145 #endif
147 /* Do not handle reversed order prefetches (negative stride). */
148 #ifndef PREFETCH_NO_REVERSE_ORDER
149 #define PREFETCH_NO_REVERSE_ORDER 1
150 #endif
152 /* Prefetch even if the GIV is in conditional code. */
153 #ifndef PREFETCH_CONDITIONAL
154 #define PREFETCH_CONDITIONAL 1
155 #endif
157 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
158 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
160 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
161 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
162 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
164 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
165 ((REGNO) < FIRST_PSEUDO_REGISTER \
166 ? (int) hard_regno_nregs[(REGNO)][GET_MODE (SET_DEST)] : 1)
169 /* Vector mapping INSN_UIDs to luids.
170 The luids are like uids but increase monotonically always.
171 We use them to see whether a jump comes from outside a given loop. */
175 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
176 number the insn is contained in. */
180 /* 1 + largest uid of any insn. */
184 /* Number of loops detected in current function. Used as index to the
185 next few tables. */
189 /* Bound on pseudo register number before loop optimization.
190 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
193 /* The value to pass to the next call of reg_scan_update. */
195 \f
196 /* During the analysis of a loop, a chain of `struct movable's
197 is made to record all the movable insns found.
198 Then the entire chain can be scanned to decide which to move. */
200 struct movable
201 {
206 of any registers used within the LIBCALL. */
208 that must be moved with this one. */
211 may be adjusted when matching movables
212 that load the same value are found. */
214 including other movables that force this
215 or match this one. */
217 a low part that we should avoid changing when
218 clearing the rest of the reg. */
222 /* If PARTIAL is 1, GLOBAL means something different:
223 that the reg is live outside the range from where it is set
224 to the following label. */
228 In particular, moving it does not make it
229 invariant. */
231 load SRC, rather than copying INSN. */
233 first insn of a consecutive sets group. */
236 the original insn with a copy from that
237 pseudo, rather than deleting it. */
241 };
246 /* Forward declarations. */
261 #if 0
263 #endif
304 rtx *);
365 {
366 rtx match;
367 rtx replacement;
368 rtx insn;
371 /* Nonzero iff INSN is between START and END, inclusive. */
372 #define INSN_IN_RANGE_P(INSN, START, END) \
373 (INSN_UID (INSN) < max_uid_for_loop \
374 && INSN_LUID (INSN) >= INSN_LUID (START) \
375 && INSN_LUID (INSN) <= INSN_LUID (END))
377 /* Indirect_jump_in_function is computed once per function. */
385 \f
386 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
387 copy the value of the strength reduced giv to its original register. */
390 /* Cost of using a register, to normalize the benefits of a giv. */
393 void
395 {
401 }
402 \f
403 /* Compute the mapping from uids to luids.
404 LUIDs are numbers assigned to insns, like uids,
405 except that luids increase monotonically through the code.
406 Start at insn START and stop just before END. Assign LUIDs
407 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
408 static int
410 {
412 rtx insn;
415 {
418 /* Don't assign luids to line-number NOTEs, so that the distance in
419 luids between two insns is not affected by -g. */
423 else
424 /* Give a line number note the same luid as preceding insn. */
426 }
428 }
429 \f
430 /* Entry point of this file. Perform loop optimization
431 on the current function. F is the first insn of the function
432 and DUMPFILE is a stream for output of a trace of actions taken
433 (or 0 if none should be output). */
435 void
437 {
438 rtx insn;
453 /* Count the number of loops. */
457 {
460 max_loop_num++;
461 }
463 /* Don't waste time if no loops. */
469 /* Get size to use for tables indexed by uids.
470 Leave some space for labels allocated by find_and_verify_loops. */
476 /* Allocate storage for array of loops. */
479 /* Find and process each loop.
480 First, find them, and record them in order of their beginnings. */
483 /* Allocate and initialize auxiliary loop information. */
488 /* Now find all register lifetimes. This must be done after
489 find_and_verify_loops, because it might reorder the insns in the
490 function. */
493 /* This must occur after reg_scan so that registers created by gcse
494 will have entries in the register tables.
496 We could have added a call to reg_scan after gcse_main in toplev.c,
497 but moving this call to init_alias_analysis is more efficient. */
500 /* See if we went too far. Note that get_max_uid already returns
501 one more that the maximum uid of all insn. */
504 /* Now reset it to the actual size we need. See above. */
507 /* find_and_verify_loops has already called compute_luids, but it
508 might have rearranged code afterwards, so we need to recompute
509 the luids now. */
512 /* Don't leave gaps in uid_luid for insns that have been
513 deleted. It is possible that the first or last insn
514 using some register has been deleted by cross-jumping.
515 Make sure that uid_luid for that former insn's uid
516 points to the general area where that insn used to be. */
518 {
522 }
527 /* Determine if the function has indirect jump. On some systems
528 this prevents low overhead loop instructions from being used. */
531 /* Now scan the loops, last ones first, since this means inner ones are done
532 before outer ones. */
534 {
538 {
541 }
542 }
546 /* Clean up. */
554 }
555 \f
556 /* Returns the next insn, in execution order, after INSN. START and
557 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
558 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
559 insn-stream; it is used with loops that are entered near the
560 bottom. */
562 static rtx
564 {
568 {
570 /* Go to the top of the loop, and continue there. */
572 else
573 /* We're done. */
575 }
578 /* We're done. */
582 }
584 /* Find any register references hidden inside X and add them to
585 the dependency list DEPS. This is used to look inside CLOBBER (MEM
586 when checking whether a PARALLEL can be pulled out of a loop. */
588 static rtx
590 {
594 else
595 {
599 {
605 }
606 }
608 }
610 /* Optimize one loop described by LOOP. */
612 /* ??? Could also move memory writes out of loops if the destination address
613 is invariant, the source is invariant, the memory write is not volatile,
614 and if we can prove that no read inside the loop can read this address
615 before the write occurs. If there is a read of this address after the
616 write, then we can also mark the memory read as invariant. */
618 static void
620 {
626 rtx p;
627 /* 1 if we are scanning insns that could be executed zero times. */
629 /* 1 if we are scanning insns that might never be executed
630 due to a subroutine call which might exit before they are reached. */
632 /* Number of insns in the loop. */
636 /* The SET from an insn, if it is the only SET in the insn. */
638 /* Chain describing insns movable in current loop. */
640 /* Ratio of extra register life span we can justify
641 for saving an instruction. More if loop doesn't call subroutines
642 since in that case saving an insn makes more difference
643 and more registers are available. */
645 /* Nonzero if we are scanning instructions in a sub-loop. */
654 /* Determine whether this loop starts with a jump down to a test at
655 the end. This will occur for a small number of loops with a test
656 that is too complex to duplicate in front of the loop.
658 We search for the first insn or label in the loop, skipping NOTEs.
659 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
660 (because we might have a loop executed only once that contains a
661 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
662 (in case we have a degenerate loop).
664 Note that if we mistakenly think that a loop is entered at the top
665 when, in fact, it is entered at the exit test, the only effect will be
666 slightly poorer optimization. Making the opposite error can generate
667 incorrect code. Since very few loops now start with a jump to the
668 exit test, the code here to detect that case is very conservative. */
671 p != loop_end
677 ;
681 /* If loop end is the end of the current function, then emit a
682 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
683 note insn. This is the position we use when sinking insns out of
684 the loop. */
687 else
690 /* Set up variables describing this loop. */
694 /* If loop has a jump before the first label,
695 the true entry is the target of that jump.
696 Start scan from there.
697 But record in LOOP->TOP the place where the end-test jumps
698 back to so we can scan that after the end of the loop. */
700 /* Loop entry must be unconditional jump (and not a RETURN) */
703 /* Check to see whether the jump actually
704 jumps out of the loop (meaning it's no loop).
705 This case can happen for things like
706 do {..} while (0). If this label was generated previously
707 by loop, we can't tell anything about it and have to reject
708 the loop. */
710 {
713 }
715 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
716 as required by loop_reg_used_before_p. So skip such loops. (This
717 test may never be true, but it's best to play it safe.)
719 Also, skip loops where we do not start scanning at a label. This
720 test also rejects loops starting with a JUMP_INSN that failed the
721 test above. */
725 {
730 }
732 /* Allocate extra space for REGs that might be created by load_mems.
733 We allocate a little extra slop as well, in the hopes that we
734 won't have to reallocate the regs array. */
739 {
745 }
747 /* Scan through the loop finding insns that are safe to move.
748 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
749 this reg will be considered invariant for subsequent insns.
750 We consider whether subsequent insns use the reg
751 in deciding whether it is worth actually moving.
753 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
754 and therefore it is possible that the insns we are scanning
755 would never be executed. At such times, we must make sure
756 that it is safe to execute the insn once instead of zero times.
757 When MAYBE_NEVER is 0, all insns will be executed at least once
758 so that is not a problem. */
763 {
765 in_libcall--;
767 {
770 in_libcall++;
774 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
776 #endif
778 {
786 /* Figure out what to use as a source of this insn. If a
787 REG_EQUIV note is given or if a REG_EQUAL note with a
788 constant operand is specified, use it as the source and
789 mark that we should move this insn by calling
790 emit_move_insn rather that duplicating the insn.
792 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
793 note is present. */
797 else
798 {
803 {
805 /* A libcall block can use regs that don't appear in
806 the equivalent expression. To move the libcall,
807 we must move those regs too. */
809 }
810 }
812 /* For parallels, add any possible uses to the dependencies, as
813 we can't move the insn without resolving them first.
814 MEMs inside CLOBBERs may also reference registers; these
815 count as implicit uses. */
817 {
819 {
822 dependencies
824 dependencies);
829 }
830 }
833 than the one where it is set (meaning that
834 something after this point in the loop might
835 depend on its value before the set). */
837 /* And the set is not guaranteed to be executed once
838 the loop starts, or the value before the set is
839 needed before the set occurs...
841 ??? Note we have quadratic behavior here, mitigated
842 by the fact that the previous test will often fail for
843 large loops. Rather than re-scanning the entire loop
844 each time for register usage, we should build tables
845 of the register usage and use them here instead. */
846 && (maybe_never
848 /* It is unsafe to move the set. However, it may be OK to
849 move the source into a new pseudo, and substitute a
850 reg-to-reg copy for the original insn.
852 This code used to consider it OK to move a set of a variable
853 which was not created by the user and not used in an exit
854 test.
855 That behavior is incorrect and was removed. */
858 /* Don't try to optimize a MODE_CC set with a constant
859 source. It probably will be combined with a conditional
860 jump. */
863 ;
864 /* Don't try to optimize a register that was made
865 by loop-optimization for an inner loop.
866 We don't know its life-span, so we can't compute
867 the benefit. */
869 ;
870 /* Don't move the source and add a reg-to-reg copy:
871 - with -Os (this certainly increases size),
872 - if the mode doesn't support copy operations (obviously),
873 - if the source is already a reg (the motion will gain nothing),
874 - if the source is a legitimate constant (likewise). */
876 && (optimize_size
881 ;
884 || (tem2
887 || (tem1
888 = consec_sets_invariant_p
891 p)))
892 /* If the insn can cause a trap (such as divide by zero),
893 can't move it unless it's guaranteed to be executed
894 once loop is entered. Even a function call might
895 prevent the trap insn from being reached
896 (since it might exit!) */
899 {
903 /* A potential lossage is where we have a case where two insns
904 can be combined as long as they are both in the loop, but
905 we move one of them outside the loop. For large loops,
906 this can lose. The most common case of this is the address
907 of a function being called.
909 Therefore, if this register is marked as being used
910 exactly once if we are in a loop with calls
911 (a "large loop"), see if we can replace the usage of
912 this register with the source of this SET. If we can,
913 delete this insn.
915 Don't do this if P has a REG_RETVAL note or if we have
916 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
928 && (! SMALL_REGISTER_CLASSES
932 /* This test is not redundant; SET_SRC (set) might be
933 a call-clobbered register and the life of REGNO
934 might span a call. */
941 {
942 /* Replace any usage in a REG_EQUAL note. Must copy
943 the new source, so that we don't get rtx sharing
944 between the SET_SOURCE and REG_NOTES of insn p. */
946 = (replace_rtx
952 i++)
955 }
964 m->consec
975 /* Set M->cond if either loop_invariant_p
976 or consec_sets_invariant_p returned 2
977 (only conditionally invariant). */
987 /* Add M to the end of the chain MOVABLES. */
991 {
992 /* It is possible for the first instruction to have a
993 REG_EQUAL note but a non-invariant SET_SRC, so we must
994 remember the status of the first instruction in case
995 the last instruction doesn't have a REG_EQUAL note. */
998 /* Skip this insn, not checking REG_LIBCALL notes. */
1000 /* Skip the consecutive insns, if there are any. */
1002 /* Back up to the last insn of the consecutive group. */
1005 /* We must now reset m->move_insn, m->is_equiv, and
1006 possibly m->set_src to correspond to the effects of
1007 all the insns. */
1011 else
1012 {
1016 else
1019 }
1020 m->is_equiv
1022 }
1023 }
1024 /* If this register is always set within a STRICT_LOW_PART
1025 or set to zero, then its high bytes are constant.
1026 So clear them outside the loop and within the loop
1027 just load the low bytes.
1028 We must check that the machine has an instruction to do so.
1029 Also, if the value loaded into the register
1030 depends on the same register, this cannot be done. */
1040 {
1043 {
1058 /* If the insn may not be executed on some cycles,
1059 we can't clear the whole reg; clear just high part.
1060 Not even if the reg is used only within this loop.
1061 Consider this:
1062 while (1)
1063 while (s != t) {
1064 if (foo ()) x = *s;
1065 use (x);
1066 }
1067 Clearing x before the inner loop could clobber a value
1068 being saved from the last time around the outer loop.
1069 However, if the reg is not used outside this loop
1070 and all uses of the register are in the same
1071 basic block as the store, there is no problem.
1073 If this insn was made by loop, we don't know its
1074 INSN_LUID and hence must make a conservative
1075 assumption. */
1078 || (labels_in_range_p
1082 else
1091 i++)
1093 /* Add M to the end of the chain MOVABLES. */
1095 }
1096 }
1097 }
1098 }
1099 /* Past a call insn, we get to insns which might not be executed
1100 because the call might exit. This matters for insns that trap.
1101 Constant and pure call insns always return, so they don't count. */
1104 /* Past a label or a jump, we get to insns for which we
1105 can't count on whether or how many times they will be
1106 executed during each iteration. Therefore, we can
1107 only move out sets of trivial variables
1108 (those not used after the loop). */
1109 /* Similar code appears twice in strength_reduce. */
1111 /* If we enter the loop in the middle, and scan around to the
1112 beginning, don't set maybe_never for that. This must be an
1113 unconditional jump, otherwise the code at the top of the
1114 loop might never be executed. Unconditional jumps are
1115 followed by a barrier then the loop_end. */
1121 {
1122 /* At the virtual top of a converted loop, insns are again known to
1123 be executed: logically, the loop begins here even though the exit
1124 code has been duplicated. */
1128 loop_depth++;
1130 loop_depth--;
1131 }
1132 }
1134 /* If one movable subsumes another, ignore that other. */
1138 /* For each movable insn, see if the reg that it loads
1139 leads when it dies right into another conditionally movable insn.
1140 If so, record that the second insn "forces" the first one,
1141 since the second can be moved only if the first is. */
1145 /* See if there are multiple movable insns that load the same value.
1146 If there are, make all but the first point at the first one
1147 through the `match' field, and add the priorities of them
1148 all together as the priority of the first. */
1152 /* Now consider each movable insn to decide whether it is worth moving.
1153 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1155 For machines with few registers this increases code size, so do not
1156 move moveables when optimizing for code size on such machines.
1157 (The 18 below is the value for i386.) */
1161 {
1164 /* Recalculate regs->array if move_movables has created new
1165 registers. */
1167 {
1173 ;
1178 }
1179 }
1181 /* Now candidates that still are negative are those not moved.
1182 Change regs->array[I].set_in_loop to indicate that those are not actually
1183 invariant. */
1188 /* Now that we've moved some things out of the loop, we might be able to
1189 hoist even more memory references. */
1192 /* Recalculate regs->array if load_mems has created new registers. */
1200 ;
1207 {
1209 /* Ensure our label doesn't go away. */
1220 }
1223 /* The movable information is required for strength reduction. */
1229 }
1230 \f
1231 /* Add elements to *OUTPUT to record all the pseudo-regs
1232 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1234 void
1236 {
1244 {
1262 }
1266 {
1270 {
1279 }
1280 }
1281 }
1282 \f
1283 /* Check what regs are referred to in the libcall block ending with INSN,
1284 aside from those mentioned in the equivalent value.
1285 If there are none, return 0.
1286 If there are one or more, return an EXPR_LIST containing all of them. */
1288 rtx
1290 {
1295 /* First, find all the regs used in the libcall block
1296 that are not mentioned as inputs to the result. */
1299 {
1304 }
1307 }
1308 \f
1309 /* Return 1 if all uses of REG
1310 are between INSN and the end of the basic block. */
1312 static int
1314 {
1316 rtx p;
1321 /* Search this basic block for the already recorded last use of the reg. */
1323 {
1325 {
1331 /* Ordinary insn: if this is the last use, we win. */
1337 /* Jump insn: if this is the last use, we win. */
1340 /* Otherwise, it's the end of the basic block, so we lose. */
1345 /* It's the end of the basic block, so we lose. */
1350 }
1351 }
1353 /* The "last use" that was recorded can't be found after the first
1354 use. This can happen when the last use was deleted while
1355 processing an inner loop, this inner loop was then completely
1356 unrolled, and the outer loop is always exited after the inner loop,
1357 so that everything after the first use becomes a single basic block. */
1359 }
1360 \f
1361 /* Compute the benefit of eliminating the insns in the block whose
1362 last insn is LAST. This may be a group of insns used to compute a
1363 value directly or can contain a library call. */
1365 static int
1367 {
1368 rtx insn;
1373 {
1376 routine. */
1380 benefit++;
1381 }
1384 }
1385 \f
1386 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1388 static rtx
1390 {
1392 {
1393 rtx temp;
1395 /* If first insn of libcall sequence, skip to end. */
1396 /* Do this at start of loop, since INSN is guaranteed to
1397 be an insn here. */
1402 do
1405 }
1408 }
1410 /* Ignore any movable whose insn falls within a libcall
1411 which is part of another movable.
1412 We make use of the fact that the movable for the libcall value
1413 was made later and so appears later on the chain. */
1415 static void
1417 {
1421 {
1422 /* Is this a movable for the value of a libcall? */
1425 {
1426 rtx insn;
1427 /* Check for earlier movables inside that range,
1428 and mark them invalid. We cannot use LUIDs here because
1429 insns created by loop.c for prior loops don't have LUIDs.
1430 Rather than reject all such insns from movables, we just
1431 explicitly check each insn in the libcall (since invariant
1432 libcalls aren't that common). */
1437 }
1438 }
1439 }
1441 /* For each movable insn, see if the reg that it loads
1442 leads when it dies right into another conditionally movable insn.
1443 If so, record that the second insn "forces" the first one,
1444 since the second can be moved only if the first is. */
1446 static void
1448 {
1452 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1454 {
1457 /* ??? Could this be a bug? What if CSE caused the
1458 register of M1 to be used after this insn?
1459 Since CSE does not update regno_last_uid,
1460 this insn M->insn might not be where it dies.
1461 But very likely this doesn't matter; what matters is
1462 that M's reg is computed from M1's reg. */
1467 /* If m->consec, m->set_src isn't valid. */
1471 /* Increase the priority of the moving the first insn
1472 since it permits the second to be moved as well. */
1474 {
1478 }
1479 }
1480 }
1481 \f
1482 /* Find invariant expressions that are equal and can be combined into
1483 one register. */
1485 static void
1487 {
1492 /* Regs that are set more than once are not allowed to match
1493 or be matched. I'm no longer sure why not. */
1494 /* Only pseudo registers are allowed to match or be matched,
1495 since move_movables does not validate the change. */
1496 /* Perhaps testing m->consec_sets would be more appropriate here? */
1503 {
1510 /* We want later insns to match the first one. Don't make the first
1511 one match any later ones. So start this loop at m->next. */
1517 /* A reg used outside the loop mustn't be eliminated. */
1519 /* A reg used for zero-extending mustn't be eliminated. */
1522 ||
1523 (
1524 /* Can combine regs with different modes loaded from the
1525 same constant only if the modes are the same or
1526 if both are integer modes with M wider or the same
1527 width as M1. The check for integer is redundant, but
1528 safe, since the only case of differing destination
1529 modes with equal sources is when both sources are
1530 VOIDmode, i.e., CONST_INT. */
1536 /* See if the source of M1 says it matches M. */
1543 {
1549 }
1550 }
1552 /* Now combine the regs used for zero-extension.
1553 This can be done for those not marked `global'
1554 provided their lives don't overlap. */
1558 {
1561 /* Combine all the registers for extension from mode MODE.
1562 Don't combine any that are used outside this loop. */
1566 {
1573 {
1574 /* First one: don't check for overlap, just record it. */
1577 }
1579 /* Make sure they extend to the same mode.
1580 (Almost always true.) */
1584 /* We already have one: check for overlap with those
1585 already combined together. */
1592 /* No overlap: we can combine this with the others. */
1598 overlap:
1599 ;
1600 }
1601 }
1603 /* Clean up. */
1605 }
1607 /* Returns the number of movable instructions in LOOP that were not
1608 moved outside the loop. */
1610 static int
1612 {
1621 }
1623 \f
1624 /* Return 1 if regs X and Y will become the same if moved. */
1626 static int
1628 {
1645 }
1647 /* Return 1 if X and Y are identical-looking rtx's.
1648 This is the Lisp function EQUAL for rtx arguments.
1650 If two registers are matching movables or a movable register and an
1651 equivalent constant, consider them equal. */
1653 static int
1656 {
1670 /* If we have a register and a constant, they may sometimes be
1671 equal. */
1674 {
1679 }
1682 {
1687 }
1689 /* Otherwise, rtx's of different codes cannot be equal. */
1693 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1694 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1699 /* These three types of rtx's can be compared nonrecursively. */
1708 /* Compare the elements. If any pair of corresponding elements
1709 fail to match, return 0 for the whole things. */
1713 {
1715 {
1727 /* Two vectors must have the same length. */
1731 /* And the corresponding elements must match. */
1750 /* These are just backpointers, so they don't matter. */
1756 /* It is believed that rtx's at this level will never
1757 contain anything but integers and other rtx's,
1758 except for within LABEL_REFs and SYMBOL_REFs. */
1761 }
1762 }
1764 }
1765 \f
1766 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1767 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1768 references is incremented once for each added note. */
1770 static void
1772 {
1776 rtx insn;
1779 {
1780 /* This code used to ignore labels that referred to dispatch tables to
1781 avoid flow generating (slightly) worse code.
1783 We no longer ignore such label references (see LABEL_REF handling in
1784 mark_jump_label for additional information). */
1787 {
1792 }
1793 }
1797 {
1803 }
1804 }
1805 \f
1806 /* Scan MOVABLES, and move the insns that deserve to be moved.
1807 If two matching movables are combined, replace one reg with the
1808 other throughout. */
1810 static void
1813 {
1818 rtx p;
1821 /* Map of pseudo-register replacements to handle combining
1822 when we move several insns that load the same value
1823 into different pseudo-registers. */
1828 {
1829 /* Describe this movable insn. */
1832 {
1853 }
1855 /* Ignore the insn if it's already done (it matched something else).
1856 Otherwise, see if it is now safe to move. */
1868 {
1870 rtx p;
1873 /* We have an insn that is safe to move.
1874 Compute its desirability. */
1885 /* An insn MUST be moved if we already moved something else
1886 which is safe only if this one is moved too: that is,
1887 if already_moved[REGNO] is nonzero. */
1889 /* An insn is desirable to move if the new lifetime of the
1890 register is no more than THRESHOLD times the old lifetime.
1891 If it's not desirable, it means the loop is so big
1892 that moving won't speed things up much,
1893 and it is liable to make register usage worse. */
1895 /* It is also desirable to move if it can be moved at no
1896 extra cost because something else was already moved. */
1899 || flag_move_all_movables
1904 {
1913 /* Now move the insns that set the reg. */
1916 {
1919 /* Find the end of this chain of matching regs.
1920 Thus, we load each reg in the chain from that one reg.
1921 And that reg is loaded with 0 directly,
1922 since it has ->match == 0. */
1928 /* Mark the moved, invariant reg as being allowed to
1929 share a hard reg with the other matching invariant. */
1933 regs_may_share
1936 regs_may_share));
1944 }
1945 /* If we are to re-generate the item being moved with a
1946 new move insn, first delete what we have and then emit
1947 the move insn before the loop. */
1949 {
1953 {
1954 /* If this is the first insn of a library call sequence,
1955 something is very wrong. */
1960 /* If this is the last insn of a libcall sequence, then
1961 delete every insn in the sequence except the last.
1962 The last insn is handled in the normal manner. */
1965 {
1969 }
1974 /* simplify_giv_expr expects that it can walk the insns
1975 at m->insn forwards and see this old sequence we are
1976 tossing here. delete_insn does preserve the next
1977 pointers, but when we skip over a NOTE we must fix
1978 it up. Otherwise that code walks into the non-deleted
1979 insn stream. */
1984 {
1985 /* Replace the original insn with a move from
1986 our newly created temp. */
1992 }
1993 }
2012 /* The more regs we move, the less we like moving them. */
2014 }
2015 else
2016 {
2018 {
2021 /* If first insn of libcall sequence, skip to end. */
2022 /* Do this at start of loop, since p is guaranteed to
2023 be an insn here. */
2028 /* If last insn of libcall sequence, move all
2029 insns except the last before the loop. The last
2030 insn is handled in the normal manner. */
2033 {
2041 {
2042 rtx body;
2043 rtx n;
2044 rtx next;
2051 /* Find the next insn after TEMP,
2052 not counting USE or NOTE insns. */
2060 /* If that is the call, this may be the insn
2061 that loads the function address.
2063 Extract the function address from the insn
2064 that loads it into a register.
2065 If this insn was cse'd, we get incorrect code.
2067 So emit a new move insn that copies the
2068 function address into the register that the
2069 call insn will use. flow.c will delete any
2070 redundant stores that we have created. */
2075 NULL_RTX)))
2076 {
2082 }
2083 /* We have the call insn.
2084 If it uses the register we suspect it might,
2085 load it with the correct address directly. */
2090 gen_move_insn
2094 {
2096 /* Because the USAGE information potentially
2097 contains objects other than hard registers
2098 we need to copy it. */
2102 }
2103 else
2112 }
2115 }
2117 {
2118 /* P sets REG to zero; but we should clear only
2119 the bits that are not covered by the mode
2120 m->savemode. */
2122 rtx sequence;
2123 rtx tem;
2126 tem = expand_simple_binop
2139 }
2141 {
2143 /* Because the USAGE information potentially
2144 contains objects other than hard registers
2145 we need to copy it. */
2149 }
2151 {
2152 rtx seq;
2153 /* The SET_SRC might not be invariant, so we must
2154 use the REG_EQUAL note. */
2167 }
2169 {
2177 }
2178 else
2182 {
2186 /* If there is a REG_EQUAL note present whose value
2187 is not loop invariant, then delete it, since it
2188 may cause problems with later optimization passes.
2189 It is possible for cse to create such notes
2190 like this as a result of record_jump_cond. */
2195 }
2204 /* If library call, now fix the REG_NOTES that contain
2205 insn pointers, namely REG_LIBCALL on FIRST
2206 and REG_RETVAL on I1. */
2208 {
2212 }
2218 /* simplify_giv_expr expects that it can walk the insns
2219 at m->insn forwards and see this old sequence we are
2220 tossing here. delete_insn does preserve the next
2221 pointers, but when we skip over a NOTE we must fix
2222 it up. Otherwise that code walks into the non-deleted
2223 insn stream. */
2228 {
2229 rtx seq;
2230 /* Replace the original insn with a move from
2231 our newly created temp. */
2237 }
2238 }
2240 /* The more regs we move, the less we like moving them. */
2242 }
2247 {
2248 /* Any other movable that loads the same register
2249 MUST be moved. */
2252 /* This reg has been moved out of one loop. */
2255 /* The reg set here is now invariant. */
2257 {
2261 }
2263 /* Change the length-of-life info for the register
2264 to say it lives at least the full length of this loop.
2265 This will help guide optimizations in outer loops. */
2268 /* This is the old insn before all the moved insns.
2269 We can't use the moved insn because it is out of range
2270 in uid_luid. Only the old insns have luids. */
2274 }
2276 /* Combine with this moved insn any other matching movables. */
2281 {
2282 rtx temp;
2284 /* Schedule the reg loaded by M1
2285 for replacement so that shares the reg of M.
2286 If the modes differ (only possible in restricted
2287 circumstances, make a SUBREG.
2289 Note this assumes that the target dependent files
2290 treat REG and SUBREG equally, including within
2291 GO_IF_LEGITIMATE_ADDRESS and in all the
2292 predicates since we never verify that replacing the
2293 original register with a SUBREG results in a
2294 recognizable insn. */
2297 else
2302 /* Get rid of the matching insn
2303 and prevent further processing of it. */
2306 /* If library call, delete all insns. */
2308 NULL_RTX)))
2310 else
2313 /* Any other movable that loads the same register
2314 MUST be moved. */
2317 /* The reg merged here is now invariant,
2318 if the reg it matches is invariant. */
2320 {
2324 i++)
2326 }
2327 }
2328 }
2331 }
2337 }
2342 /* Go through all the instructions in the loop, making
2343 all the register substitutions scheduled in REG_MAP. */
2347 {
2351 }
2353 /* Clean up. */
2356 }
2359 static void
2361 {
2364 else
2367 }
2370 static void
2372 {
2377 {
2380 }
2381 }
2382 \f
2383 #if 0
2384 /* Scan X and replace the address of any MEM in it with ADDR.
2385 REG is the address that MEM should have before the replacement. */
2387 static void
2389 {
2398 {
2410 /* Short cut for very common case. */
2415 /* Short cut for very common case. */
2420 /* If this MEM uses a reg other than the one we expected,
2421 something is wrong. */
2429 }
2433 {
2437 {
2441 }
2442 }
2443 }
2444 #endif
2445 \f
2446 /* Return the number of memory refs to addresses that vary
2447 in the rtx X. */
2449 static int
2451 {
2462 {
2479 }
2484 {
2488 {
2492 }
2493 }
2495 }
2496 \f
2497 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2498 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2499 `unknown_address_altered', `unknown_constant_address_altered', and
2500 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2501 list `store_mems' in LOOP. */
2503 static void
2505 {
2507 rtx insn;
2511 /* The label after END. Jumping here is just like falling off the
2512 end of the loop. We use next_nonnote_insn instead of next_label
2513 as a hedge against the (pathological) case where some actual insn
2514 might end up between the two. */
2533 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2538 {
2540 {
2543 }
2544 }
2548 {
2550 {
2553 {
2555 /* Count number of loops contained in this one. */
2557 }
2564 {
2567 }
2574 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2575 attached FUNCTION_USAGE expression list, not accounted for by the
2576 code above. We should note these to avoid missing dependencies in
2577 later references. */
2578 {
2579 rtx fusage_entry;
2583 {
2589 {
2594 }
2595 }
2596 }
2601 {
2605 {
2610 {
2613 }
2614 else
2615 {
2618 }
2620 do
2621 {
2623 {
2625 {
2626 /* Something tricky. */
2629 }
2632 {
2633 /* A jump outside the current loop. */
2636 }
2637 }
2641 }
2643 }
2644 else
2645 {
2646 /* A return, or something tricky. */
2648 }
2649 }
2650 /* Fall through. */
2671 }
2672 }
2674 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2676 anywhere. */
2678 /* We don't want loads for MEMs moved to a location before the
2679 one at which their stack memory becomes allocated. (Note
2680 that this is not a problem for malloc, etc., since those
2681 require actual function calls. */
2682 && ! current_function_calls_alloca
2683 /* There are ways to leave the loop other than falling off the
2684 end. */
2690 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2691 that loop_invariant_p and load_mems can use true_dependence
2692 to determine what is really clobbered. */
2694 {
2697 loop_info->store_mems
2699 }
2701 {
2705 loop_info->store_mems
2707 }
2708 }
2709 \f
2710 /* Invalidate all loops containing LABEL. */
2712 static void
2714 {
2718 }
2720 /* Scan the function looking for loops. Record the start and end of each loop.
2721 Also mark as invalid loops any loops that contain a setjmp or are branched
2722 to from outside the loop. */
2724 static void
2726 {
2727 rtx insn;
2728 rtx label;
2738 /* If there are jumps to undefined labels,
2739 treat them as jumps out of any/all loops.
2740 This also avoids writing past end of tables when there are no loops. */
2743 /* Find boundaries of loops, mark which loops are contained within
2744 loops, and invalidate loops that have setjmp. */
2749 {
2752 {
2756 num_loops++;
2780 }
2784 {
2785 /* In this case, we must invalidate our current loop and any
2786 enclosing loop. */
2788 {
2794 }
2795 }
2797 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2798 enclosing loop, but this doesn't matter. */
2800 }
2802 /* Any loop containing a label used in an initializer must be invalidated,
2803 because it can be jumped into from anywhere. */
2807 /* Any loop containing a label used for an exception handler must be
2808 invalidated, because it can be jumped into from anywhere. */
2811 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2812 loop that it is not contained within, that loop is marked invalid.
2813 If any INSN or CALL_INSN uses a label's address, then the loop containing
2814 that label is marked invalid, because it could be jumped into from
2815 anywhere.
2817 Also look for blocks of code ending in an unconditional branch that
2818 exits the loop. If such a block is surrounded by a conditional
2819 branch around the block, move the block elsewhere (see below) and
2820 invert the jump to point to the code block. This may eliminate a
2821 label in our loop and will simplify processing by both us and a
2822 possible second cse pass. */
2826 {
2830 {
2834 }
2841 /* See if this is an unconditional branch outside the loop. */
2849 {
2850 rtx p;
2856 /* Go backwards until we reach the start of the loop, a label,
2857 or a JUMP_INSN. */
2864 ;
2866 /* Check for the case where we have a jump to an inner nested
2867 loop, and do not perform the optimization in that case. */
2870 {
2873 {
2878 }
2879 }
2881 /* Make sure that the target of P is within the current loop. */
2887 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2888 we have a block of code to try to move.
2890 We look backward and then forward from the target of INSN
2891 to find a BARRIER at the same loop depth as the target.
2892 If we find such a BARRIER, we make a new label for the start
2893 of the block, invert the jump in P and point it to that label,
2894 and move the block of code to the spot we found. */
2899 /* Just ignore jumps to labels that were never emitted.
2900 These always indicate compilation errors. */
2904 /* If it's not safe to move the sequence, then we
2905 mustn't try. */
2908 {
2909 rtx target
2913 rtx tmp;
2915 /* Search for possible garbage past the conditional jumps
2916 and look for the last barrier. */
2924 /* Don't move things inside a tablejump. */
2937 /* Don't move things inside a tablejump. */
2948 {
2952 /* Ensure our label doesn't go away. */
2955 /* Verify that uid_loop is large enough and that
2956 we can invert P. */
2958 {
2961 /* If no suitable BARRIER was found, create a suitable
2962 one before TARGET. Since TARGET is a fall through
2963 path, we'll need to insert a jump around our block
2964 and add a BARRIER before TARGET.
2966 This creates an extra unconditional jump outside
2967 the loop. However, the benefits of removing rarely
2968 executed instructions from inside the loop usually
2969 outweighs the cost of the extra unconditional jump
2970 outside the loop. */
2972 {
2973 rtx temp;
2980 }
2982 /* Include the BARRIER after INSN and copy the
2983 block after LOC. */
2988 /* All those insns are now in TARGET_LOOP. */
2994 /* The label jumped to by INSN is no longer a loop
2995 exit. Unless INSN does not have a label (e.g.,
2996 it is a RETURN insn), search loop->exit_labels
2997 to find its label_ref, and remove it. Also turn
2998 off LABEL_OUTSIDE_LOOP_P bit. */
3000 {
3002 r;
3005 {
3009 else
3012 }
3018 /* If we didn't find it, then something is
3019 wrong. */
3022 }
3024 /* P is now a jump outside the loop, so it must be put
3025 in loop->exit_labels, and marked as such.
3026 The easiest way to do this is to just call
3027 mark_loop_jump again for P. */
3030 /* If INSN now jumps to the insn after it,
3031 delete INSN. */
3036 }
3038 /* Continue the loop after where the conditional
3039 branch used to jump, since the only branch insn
3040 in the block (if it still remains) is an inter-loop
3041 branch and hence needs no processing. */
3047 /* This loop will be continued with NEXT_INSN (insn). */
3049 }
3050 }
3051 }
3052 }
3053 }
3055 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3056 loops it is contained in, mark the target loop invalid.
3058 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3060 static void
3062 {
3068 {
3080 /* There could be a label reference in here. */
3092 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3104 /* Link together all labels that branch outside the loop. This
3105 is used by final_[bg]iv_value and the loop unrolling code. Also
3106 mark this LABEL_REF so we know that this branch should predict
3107 false. */
3109 /* A check to make sure the label is not in an inner nested loop,
3110 since this does not count as a loop exit. */
3112 {
3117 }
3118 else
3122 {
3131 }
3133 /* If this is inside a loop, but not in the current loop or one enclosed
3134 by it, it invalidates at least one loop. */
3139 /* We must invalidate every nested loop containing the target of this
3140 label, except those that also contain the jump insn. */
3143 {
3144 /* Stop when we reach a loop that also contains the jump insn. */
3149 /* If we get here, we know we need to invalidate a loop. */
3156 }
3160 /* If this is not setting pc, ignore. */
3182 /* Strictly speaking this is not a jump into the loop, only a possible
3183 jump out of the loop. However, we have no way to link the destination
3184 of this jump onto the list of exit labels. To be safe we mark this
3185 loop and any containing loops as invalid. */
3187 {
3189 {
3195 }
3196 }
3198 }
3199 }
3200 \f
3201 /* Return nonzero if there is a label in the range from
3202 insn INSN to and including the insn whose luid is END
3203 INSN must have an assigned luid (i.e., it must not have
3204 been previously created by loop.c). */
3206 static int
3208 {
3210 {
3214 }
3217 }
3219 /* Record that a memory reference X is being set. */
3221 static void
3224 {
3230 /* Count number of memory writes.
3231 This affects heuristics in strength_reduce. */
3234 /* BLKmode MEM means all memory is clobbered. */
3236 {
3239 else
3243 }
3247 }
3249 /* X is a value modified by an INSN that references a biv inside a loop
3250 exit test (ie, X is somehow related to the value of the biv). If X
3251 is a pseudo that is used more than once, then the biv is (effectively)
3252 used more than once. DATA is a pointer to a loop_regs structure. */
3254 static void
3256 {
3271 /* If we do not have usage information, or if we know the register
3272 is used more than once, note that fact for check_dbra_loop. */
3277 }
3278 \f
3279 /* Return nonzero if the rtx X is invariant over the current loop.
3281 The value is 2 if we refer to something only conditionally invariant.
3283 A memory ref is invariant if it is not volatile and does not conflict
3284 with anything stored in `loop_info->store_mems'. */
3286 int
3288 {
3295 rtx mem_list_entry;
3301 {
3309 /* A LABEL_REF is normally invariant, however, if we are unrolling
3310 loops, and this label is inside the loop, then it isn't invariant.
3311 This is because each unrolled copy of the loop body will have
3312 a copy of this label. If this was invariant, then an insn loading
3313 the address of this label into a register might get moved outside
3314 the loop, and then each loop body would end up using the same label.
3316 We don't know the loop bounds here though, so just fail for all
3317 labels. */
3320 else
3329 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3330 since the reg might be set by initialization within the loop. */
3341 /* Out-of-range regs can occur when we are called from unrolling.
3342 These registers created by the unroller are set in the loop,
3343 hence are never invariant.
3344 Other out-of-range regs can be generated by load_mems; those that
3345 are written to in the loop are not invariant, while those that are
3346 not written to are invariant. It would be easy for load_mems
3347 to set n_times_set correctly for these registers, however, there
3348 is no easy way to distinguish them from registers created by the
3349 unroller. */
3360 /* Volatile memory references must be rejected. Do this before
3361 checking for read-only items, so that volatile read-only items
3362 will be rejected also. */
3366 /* See if there is any dependence between a store and this load. */
3369 {
3375 }
3377 /* It's not invalidated by a store in memory
3378 but we must still verify the address is invariant. */
3382 /* Don't mess with insns declared volatile. */
3389 }
3393 {
3395 {
3401 }
3403 {
3406 {
3412 }
3414 }
3415 }
3418 }
3419 \f
3420 /* Return nonzero if all the insns in the loop that set REG
3421 are INSN and the immediately following insns,
3422 and if each of those insns sets REG in an invariant way
3423 (not counting uses of REG in them).
3425 The value is 2 if some of these insns are only conditionally invariant.
3427 We assume that INSN itself is the first set of REG
3428 and that its source is invariant. */
3430 static int
3432 rtx insn)
3433 {
3437 rtx temp;
3438 /* Number of sets we have to insist on finding after INSN. */
3444 /* If N_SETS hit the limit, we can't rely on its value. */
3451 {
3453 rtx set;
3458 /* If library call, skip to end of it. */
3467 {
3472 {
3473 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3474 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3475 notes are OK. */
3481 }
3482 }
3484 count--;
3486 {
3489 }
3490 }
3493 /* If loop_invariant_p ever returned 2, we return 2. */
3495 }
3497 #if 0
3498 /* I don't think this condition is sufficient to allow INSN
3499 to be moved, so we no longer test it. */
3501 /* Return 1 if all insns in the basic block of INSN and following INSN
3502 that set REG are invariant according to TABLE. */
3504 static int
3506 {
3511 {
3520 {
3523 }
3524 }
3525 }
3527 \f
3528 /* Look at all uses (not sets) of registers in X. For each, if it is
3529 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3530 a different insn, set USAGE[REGNO] to const0_rtx. */
3532 static void
3534 {
3546 {
3547 /* Don't count SET_DEST if it is a REG; otherwise count things
3548 in SET_DEST because if a register is partially modified, it won't
3549 show up as a potential movable so we don't care how USAGE is set
3550 for it. */
3554 }
3555 else
3557 {
3563 }
3564 }
3565 \f
3566 /* Count and record any set in X which is contained in INSN. Update
3567 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3568 in X. */
3570 static void
3572 {
3574 /* Don't move a reg that has an explicit clobber.
3575 It's not worth the pain to try to do it correctly. */
3579 {
3587 {
3591 {
3592 /* If this is the first setting of this reg
3593 in current basic block, and it was set before,
3594 it must be set in two basic blocks, so it cannot
3595 be moved out of the loop. */
3599 /* If this is not first setting in current basic block,
3600 see if reg was used in between previous one and this.
3601 If so, neither one can be moved. */
3608 }
3609 }
3610 }
3611 }
3612 \f
3613 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3614 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3615 contained in insn INSN is used by any insn that precedes INSN in
3616 cyclic order starting from the loop entry point.
3618 We don't want to use INSN_LUID here because if we restrict INSN to those
3619 that have a valid INSN_LUID, it means we cannot move an invariant out
3620 from an inner loop past two loops. */
3622 static int
3624 {
3626 rtx p;
3628 /* Scan forward checking for register usage. If we hit INSN, we
3629 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3631 {
3637 }
3640 }
3641 \f
3643 /* Information we collect about arrays that we might want to prefetch. */
3644 struct prefetch_info
3645 {
3649 index. */
3650 HOST_WIDE_INT index;
3652 iteration. */
3654 prefetch area in one iteration. */
3656 This is set only for loops with known
3657 iteration counts and is 0xffffffff
3658 otherwise. */
3662 };
3664 /* Data used by check_store function. */
3665 struct check_store_data
3666 {
3667 rtx mem_address;
3669 };
3675 /* Set mem_write when mem_address is found. Used as callback to
3676 note_stores. */
3677 static void
3679 {
3684 }
3685 \f
3686 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3687 important to get some addresses combined. Later more sophisticated
3688 transformations can be added when necessary.
3690 ??? Same trick with swapping operand is done at several other places.
3691 It can be nice to develop some common way to handle this. */
3693 static int
3695 {
3709 {
3714 }
3715 /* Compare the elements. If any pair of corresponding elements fails to
3716 match, return 0 for the whole thing. */
3720 {
3722 {
3734 /* Two vectors must have the same length. */
3738 /* And the corresponding elements must match. */
3756 /* These are just backpointers, so they don't matter. */
3762 /* It is believed that rtx's at this level will never
3763 contain anything but integers and other rtx's,
3764 except for within LABEL_REFs and SYMBOL_REFs. */
3767 }
3768 }
3770 }
3771 \f
3772 /* Remove constant addition value from the expression X (when present)
3773 and return it. */
3775 static HOST_WIDE_INT
3777 {
3781 /* Avoid clobbering a shared CONST expression. */
3783 {
3787 {
3790 }
3792 }
3795 {
3798 }
3800 /* For plus expression recurse on ourself. */
3802 {
3806 /* In case our parameter was constant, remove extra zero from the
3807 expression. */
3812 }
3815 }
3817 /* Attempt to identify accesses to arrays that are most likely to cause cache
3818 misses, and emit prefetch instructions a few prefetch blocks forward.
3820 To detect the arrays we use the GIV information that was collected by the
3821 strength reduction pass.
3823 The prefetch instructions are generated after the GIV information is done
3824 and before the strength reduction process. The new GIVs are injected into
3825 the strength reduction tables, so the prefetch addresses are optimized as
3826 well.
3828 GIVs are split into base address, stride, and constant addition values.
3829 GIVs with the same address, stride and close addition values are combined
3830 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3831 for write instructions can be used for the block we write to, on machines
3832 that support write prefetches.
3834 Several heuristics are used to determine when to prefetch. They are
3835 controlled by defined symbols that can be overridden for each target. */
3837 static void
3839 {
3855 /* Consider only loops w/o calls. When a call is done, the loop is probably
3856 slow enough to read the memory. */
3858 {
3863 }
3865 /* Don't prefetch in loops known to have few iterations. */
3869 {
3874 }
3876 /* Search all induction variables and pick those interesting for the prefetch
3877 machinery. */
3879 {
3885 /* Expect all BIVs to be executed in each iteration. This makes our
3886 analysis more conservative. */
3888 {
3889 /* Discard non-constant additions that we can't handle well yet, and
3890 BIVs that are executed multiple times; such BIVs ought to be
3891 handled in the nested loop. We accept not_every_iteration BIVs,
3892 since these only result in larger strides and make our
3893 heuristics more conservative. */
3895 {
3897 {
3903 }
3905 }
3908 {
3910 {
3916 }
3918 }
3922 }
3928 {
3929 rtx address;
3930 rtx temp;
3939 /* See whether an induction variable is interesting to us and if
3940 not, report the reason. */
3944 /* We are interested only in constant stride memory references
3945 in order to be able to compute density easily. */
3949 else
3950 {
3953 {
3956 }
3958 /* On some targets, reversed order prefetches are not
3959 worthwhile. */
3963 /* Prefetch of accesses with an extreme stride might not be
3964 worthwhile, either. */
3969 /* Ignore GIVs with varying add values; we can't predict the
3970 value for the next iteration. */
3974 /* Ignore GIVs in the nested loops; they ought to have been
3975 handled already. */
3978 }
3981 {
3987 }
3989 /* Determine the pointer to the basic array we are examining. It is
3990 the sum of the BIV's initial value and the GIV's add_val. */
4000 /* When the GIV is not always executed, we might be better off by
4001 not dirtying the cache pages. */
4004 else
4005 {
4010 }
4012 /* Attempt to find another prefetch to the same array and see if we
4013 can merge this one. */
4017 {
4018 /* In case both access same array (same location
4019 just with small difference in constant indexes), merge
4020 the prefetches. Just do the later and the earlier will
4021 get prefetched from previous iteration.
4022 The artificial threshold should not be too small,
4023 but also not bigger than small portion of memory usually
4024 traversed by single loop. */
4027 {
4036 }
4040 {
4045 }
4046 }
4048 /* Merging failed. */
4050 {
4058 num_prefetches++;
4060 {
4065 }
4066 }
4067 }
4068 }
4071 {
4074 /* Attempt to calculate the total number of bytes fetched by all
4075 iterations of the loop. Avoid overflow. */
4080 else
4085 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4090 {
4095 }
4096 else
4097 {
4103 }
4104 else
4107 /* Find how many prefetch instructions we'll use within the loop. */
4109 {
4115 }
4116 }
4118 /* Determine how many iterations ahead to prefetch within the loop, based
4119 on how many prefetches we currently expect to do within the loop. */
4121 {
4123 {
4129 }
4130 }
4131 /* We'll also use AHEAD to determine how many prefetch instructions to
4132 emit before a loop, so don't leave it zero. */
4137 {
4138 /* Update if we've decided not to prefetch anything within the loop. */
4142 /* Find how many prefetch instructions we'll use before the loop. */
4144 {
4152 }
4155 {
4175 }
4176 }
4179 {
4180 /* Record that this loop uses prefetch instructions. */
4184 {
4189 }
4190 }
4193 {
4197 {
4199 rtx insn;
4203 rtx seq;
4205 /* We can save some effort by offsetting the address on
4206 architectures with offsettable memory references. */
4209 else
4210 {
4216 }
4219 /* Make sure the address operand is valid for prefetch. */
4229 /* Check all insns emitted and record the new GIV
4230 information. */
4233 {
4238 }
4239 }
4242 {
4243 /* Emit insns before the loop to fetch the first cache lines or,
4244 if we're not prefetching within the loop, everything we expect
4245 to need. */
4247 {
4255 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4256 non-constant INIT_VAL to have the same mode as REG, which
4257 in this case we know to be Pmode. */
4259 {
4260 rtx seq;
4267 }
4273 loop_start);
4274 }
4275 }
4276 }
4279 }
4280 \f
4281 /* Communication with routines called via `note_stores'. */
4285 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4289 /* ??? Unfinished optimizations, and possible future optimizations,
4290 for the strength reduction code. */
4292 /* ??? The interaction of biv elimination, and recognition of 'constant'
4293 bivs, may cause problems. */
4295 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4296 performance problems.
4298 Perhaps don't eliminate things that can be combined with an addressing
4299 mode. Find all givs that have the same biv, mult_val, and add_val;
4300 then for each giv, check to see if its only use dies in a following
4301 memory address. If so, generate a new memory address and check to see
4302 if it is valid. If it is valid, then store the modified memory address,
4303 otherwise, mark the giv as not done so that it will get its own iv. */
4305 /* ??? Could try to optimize branches when it is known that a biv is always
4306 positive. */
4308 /* ??? When replace a biv in a compare insn, we should replace with closest
4309 giv so that an optimized branch can still be recognized by the combiner,
4310 e.g. the VAX acb insn. */
4312 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4313 was rerun in loop_optimize whenever a register was added or moved.
4314 Also, some of the optimizations could be a little less conservative. */
4315 \f
4316 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4317 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4318 callback.
4320 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4321 least once for every loop iteration except for the last one.
4323 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4324 loop iteration.
4325 */
4326 void
4328 {
4333 rtx p;
4335 /* If loop_scan_start points to the loop exit test, we have to be wary of
4336 subversive use of gotos inside expression statements. */
4340 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4344 {
4347 /* Past CODE_LABEL, we get to insns that may be executed multiple
4348 times. The only way we can be sure that they can't is if every
4349 jump insn between here and the end of the loop either
4350 returns, exits the loop, is a jump to a location that is still
4351 behind the label, or is a jump to the loop start. */
4354 {
4360 {
4365 {
4368 else
4372 }
4380 {
4383 }
4384 }
4385 }
4387 /* Past a jump, we get to insns for which we can't count
4388 on whether they will be executed during each iteration. */
4389 /* This code appears twice in strength_reduce. There is also similar
4390 code in scan_loop. */
4392 /* If we enter the loop in the middle, and scan around to the
4393 beginning, don't set not_every_iteration for that.
4394 This can be any kind of jump, since we want to know if insns
4395 will be executed if the loop is executed. */
4400 {
4403 /* If this is a jump outside the loop, then it also doesn't
4404 matter. Check to see if the target of this branch is on the
4405 loop->exits_labels list. */
4413 }
4416 {
4417 /* At the virtual top of a converted loop, insns are again known to
4418 be executed each iteration: logically, the loop begins here
4419 even though the exit code has been duplicated.
4421 Insns are also again known to be executed each iteration at
4422 the LOOP_CONT note. */
4428 loop_depth++;
4430 loop_depth--;
4431 }
4433 /* Note if we pass a loop latch. If we do, then we can not clear
4434 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4435 a loop since a jump before the last CODE_LABEL may have started
4436 a new loop iteration.
4438 Note that LOOP_TOP is only set for rotated loops and we need
4439 this check for all loops, so compare against the CODE_LABEL
4440 which immediately follows LOOP_START. */
4445 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4446 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4447 or not an insn is known to be executed each iteration of the
4448 loop, whether or not any iterations are known to occur.
4450 Therefore, if we have just passed a label and have no more labels
4451 between here and the test insn of the loop, and we have not passed
4452 a jump to the top of the loop, then we know these insns will be
4453 executed each iteration. */
4456 && !past_loop_latch
4461 }
4462 }
4463 \f
4464 static void
4466 {
4469 /* Temporary list pointers for traversing ivs->list. */
4476 /* Scan ivs->list to remove all regs that proved not to be bivs.
4477 Make a sanity check against regs->n_times_set. */
4479 {
4481 /* Above happens if register modified by subreg, etc. */
4482 /* Make sure it is not recognized as a basic induction var: */
4484 /* If never incremented, it is invariant that we decided not to
4485 move. So leave it alone. */
4487 {
4498 }
4499 else
4500 {
4505 }
4506 }
4507 }
4510 /* Determine how BIVS are initialized by looking through pre-header
4511 extended basic block. */
4512 static void
4514 {
4516 /* Temporary list pointers for traversing ivs->list. */
4519 rtx p;
4521 /* Find initial value for each biv by searching backwards from loop_start,
4522 halting at first label. Also record any test condition. */
4526 {
4527 rtx test;
4537 /* Record any test of a biv that branches around the loop if no store
4538 between it and the start of loop. We only care about tests with
4539 constants and registers and only certain of those. */
4549 {
4550 /* If an NE test, we have an initial value! */
4552 {
4556 }
4557 else
4559 }
4560 }
4561 }
4564 /* Look at the each biv and see if we can say anything better about its
4565 initial value from any initializing insns set up above. (This is done
4566 in two passes to avoid missing SETs in a PARALLEL.) */
4567 static void
4569 {
4571 /* Temporary list pointers for traversing ivs->list. */
4576 {
4577 rtx src;
4578 rtx note;
4583 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4584 is a constant, use the value of that. */
4590 else
4603 {
4607 {
4610 }
4611 }
4612 /* If we can't make it a giv,
4613 let biv keep initial value of "itself". */
4616 }
4617 }
4620 /* Search the loop for general induction variables. */
4622 static void
4624 {
4626 }
4629 /* For each giv for which we still don't know whether or not it is
4630 replaceable, check to see if it is replaceable because its final value
4631 can be calculated. */
4633 static void
4635 {
4640 {
4646 }
4647 }
4650 /* Return nonzero if it is possible to eliminate the biv BL provided
4651 all givs are reduced. This is possible if either the reg is not
4652 used outside the loop, or we can compute what its final value will
4653 be. */
4655 static int
4658 {
4659 /* For architectures with a decrement_and_branch_until_zero insn,
4660 don't do this if we put a REG_NONNEG note on the endtest for this
4661 biv. */
4663 #ifdef HAVE_decrement_and_branch_until_zero
4665 {
4670 }
4671 #endif
4673 /* Check that biv is used outside loop or if it has a final value.
4674 Compare against bl->init_insn rather than loop->start. We aren't
4675 concerned with any uses of the biv between init_insn and
4676 loop->start since these won't be affected by the value of the biv
4677 elsewhere in the function, so long as init_insn doesn't use the
4678 biv itself. */
4689 {
4697 }
4699 }
4702 /* Reduce each giv of BL that we have decided to reduce. */
4704 static void
4706 {
4710 {
4713 {
4716 /* If the code for derived givs immediately below has already
4717 allocated a new_reg, we must keep it. */
4721 #ifdef AUTO_INC_DEC
4722 /* If the target has auto-increment addressing modes, and
4723 this is an address giv, then try to put the increment
4724 immediately after its use, so that flow can create an
4725 auto-increment addressing mode. */
4728 /* We don't handle reversed biv's because bl->biv->insn
4729 does not have a valid INSN_LUID. */
4733 {
4734 /* If other giv's have been combined with this one, then
4735 this will work only if all uses of the other giv's occur
4736 before this giv's insn. This is difficult to check.
4738 We simplify this by looking for the common case where
4739 there is one DEST_REG giv, and this giv's insn is the
4740 last use of the dest_reg of that DEST_REG giv. If the
4741 increment occurs after the address giv, then we can
4742 perform the optimization. (Otherwise, the increment
4743 would have to go before other_giv, and we would not be
4744 able to combine it with the address giv to get an
4745 auto-inc address.) */
4747 {
4752 {
4755 else
4757 }
4764 }
4765 /* Check for case where increment is before the address
4766 giv. Do this test in "loop order". */
4775 else
4778 #ifdef HAVE_cc0
4779 {
4780 rtx prev;
4782 /* We can't put an insn immediately after one setting
4783 cc0, or immediately before one using cc0. */
4790 }
4791 #endif
4795 }
4796 #endif
4798 /* For each place where the biv is incremented, add an insn
4799 to increment the new, reduced reg for the giv. */
4801 {
4802 rtx insert_before;
4804 /* Skip if location is the same as a previous one. */
4811 else
4819 /* A multiply is acceptable here
4820 since this is presumed to be seldom executed. */
4824 }
4826 /* Add code at loop start to initialize giv's reduced reg. */
4831 }
4832 }
4833 }
4836 /* Check for givs whose first use is their definition and whose
4837 last use is the definition of another giv. If so, it is likely
4838 dead and should not be used to derive another giv nor to
4839 eliminate a biv. */
4841 static void
4843 {
4847 {
4854 {
4860 }
4861 }
4862 }
4865 static void
4867 {
4871 {
4878 /* Update expression if this was combined, in case other giv was
4879 replaced. */
4884 /* See if this register is known to be a pointer to something. If
4885 so, see if we can find the alignment. First see if there is a
4886 destination register that is a pointer. If so, this shares the
4887 alignment too. Next see if we can deduce anything from the
4888 computational information. If not, and this is a DEST_ADDR
4889 giv, at least we know that it's a pointer, though we don't know
4890 the alignment. */
4898 {
4907 }
4911 {
4919 }
4924 /* Store reduced reg as the address in the memref where we found
4925 this giv. */
4928 {
4930 }
4931 else
4932 {
4934 rtx note;
4936 /* Not replaceable; emit an insn to set the original giv reg from
4937 the reduced giv, same as above. */
4942 /* The original insn may have a REG_EQUAL note. This note is
4943 now incorrect and may result in invalid substitutions later.
4944 The original insn is dead, but may be part of a libcall
4945 sequence, which doesn't seem worth the bother of handling. */
4949 }
4951 /* When a loop is reversed, givs which depend on the reversed
4952 biv, and which are live outside the loop, must be set to their
4953 correct final value. This insn is only needed if the giv is
4954 not replaceable. The correct final value is the same as the
4955 value that the giv starts the reversed loop with. */
4966 {
4971 }
4972 }
4973 }
4976 static int
4979 rtx test_reg)
4980 {
4989 /* Reduce benefit if not replaceable, since we will insert a
4990 move-insn to replace the insn that calculates this giv. Don't do
4991 this unless the giv is a user variable, since it will often be
4992 marked non-replaceable because of the duplication of the exit
4993 code outside the loop. In such a case, the copies we insert are
4994 dead and will be deleted. So they don't have a cost. Similar
4995 situations exist. */
4996 /* ??? The new final_[bg]iv_value code does a much better job of
4997 finding replaceable giv's, and hence this code may no longer be
4998 necessary. */
5003 /* Decrease the benefit to count the add-insns that we will insert
5004 to increment the reduced reg for the giv. ??? This can
5005 overestimate the run-time cost of the additional insns, e.g. if
5006 there are multiple basic blocks that increment the biv, but only
5007 one of these blocks is executed during each iteration. There is
5008 no good way to detect cases like this with the current structure
5009 of the loop optimizer. This code is more accurate for
5010 determining code size than run-time benefits. */
5013 /* Decide whether to strength-reduce this giv or to leave the code
5014 unchanged (recompute it from the biv each time it is used). This
5015 decision can be made independently for each giv. */
5017 #ifdef AUTO_INC_DEC
5018 /* Attempt to guess whether autoincrement will handle some of the
5019 new add insns; if so, increase BENEFIT (undo the subtraction of
5020 add_cost that was done above). */
5022 /* Increasing the benefit is risky, since this is only a guess.
5023 Avoid increasing register pressure in cases where there would
5024 be no other benefit from reducing this giv. */
5027 {
5042 }
5043 #endif
5046 }
5049 /* Free IV structures for LOOP. */
5051 static void
5053 {
5060 {
5066 {
5069 }
5071 {
5074 }
5078 }
5079 }
5082 /* Perform strength reduction and induction variable elimination.
5084 Pseudo registers created during this function will be beyond the
5085 last valid index in several tables including
5086 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5087 problem here, because the added registers cannot be givs outside of
5088 their loop, and hence will never be reconsidered. But scan_loop
5089 must check regnos to make sure they are in bounds. */
5091 static void
5093 {
5097 rtx p;
5098 /* Temporary list pointer for traversing ivs->list. */
5100 /* Ratio of extra register life span we can justify
5101 for saving an instruction. More if loop doesn't call subroutines
5102 since in that case saving an insn makes more difference
5103 and more registers are available. */
5104 /* ??? could set this to last value of threshold in move_movables */
5106 /* Map of pseudo-register replacements. */
5118 /* Find all BIVs in loop. */
5121 /* Exit if there are no bivs. */
5123 {
5124 /* Can still unroll the loop anyways, but indicate that there is no
5125 strength reduction info available. */
5131 }
5133 /* Determine how BIVS are initialized by looking through pre-header
5134 extended basic block. */
5137 /* Look at the each biv and see if we can say anything better about its
5138 initial value from any initializing insns set up above. */
5141 /* Search the loop for general induction variables. */
5144 /* Try to calculate and save the number of loop iterations. This is
5145 set to zero if the actual number can not be calculated. This must
5146 be called after all giv's have been identified, since otherwise it may
5147 fail if the iteration variable is a giv. */
5150 #ifdef HAVE_prefetch
5153 #endif
5155 /* Now for each giv for which we still don't know whether or not it is
5156 replaceable, check to see if it is replaceable because its final value
5157 can be calculated. This must be done after loop_iterations is called,
5158 so that final_giv_value will work correctly. */
5161 /* Try to prove that the loop counter variable (if any) is always
5162 nonnegative; if so, record that fact with a REG_NONNEG note
5163 so that "decrement and branch until zero" insn can be used. */
5166 /* Create reg_map to hold substitutions for replaceable giv regs.
5167 Some givs might have been made from biv increments, so look at
5168 ivs->reg_iv_type for a suitable size. */
5172 /* Examine each iv class for feasibility of strength reduction/induction
5173 variable elimination. */
5176 {
5180 /* Test whether it will be possible to eliminate this biv
5181 provided all givs are reduced. */
5184 /* This will be true at the end, if all givs which depend on this
5185 biv have been strength reduced.
5186 We can't (currently) eliminate the biv unless this is so. */
5189 /* Check each extension dependent giv in this class to see if its
5190 root biv is safe from wrapping in the interior mode. */
5193 /* Combine all giv's for this iv_class. */
5197 {
5205 /* If an insn is not to be strength reduced, then set its ignore
5206 flag, and clear bl->all_reduced. */
5208 /* A giv that depends on a reversed biv must be reduced if it is
5209 used after the loop exit, otherwise, it would have the wrong
5210 value after the loop exit. To make it simple, just reduce all
5211 of such giv's whether or not we know they are used after the loop
5212 exit. */
5217 {
5225 }
5226 else
5227 {
5228 /* Check that we can increment the reduced giv without a
5229 multiply insn. If not, reject it. */
5234 {
5242 }
5243 }
5244 }
5246 /* Check for givs whose first use is their definition and whose
5247 last use is the definition of another giv. If so, it is likely
5248 dead and should not be used to derive another giv nor to
5249 eliminate a biv. */
5252 /* Reduce each giv that we decided to reduce. */
5255 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5256 as not reduced.
5258 For each giv register that can be reduced now: if replaceable,
5259 substitute reduced reg wherever the old giv occurs;
5260 else add new move insn "giv_reg = reduced_reg". */
5263 /* All the givs based on the biv bl have been reduced if they
5264 merit it. */
5266 /* For each giv not marked as maybe dead that has been combined with a
5267 second giv, clear any "maybe dead" mark on that second giv.
5268 v->new_reg will either be or refer to the register of the giv it
5269 combined with.
5271 Doing this clearing avoids problems in biv elimination where
5272 a giv's new_reg is a complex value that can't be put in the
5273 insn but the giv combined with (with a reg as new_reg) is
5274 marked maybe_dead. Since the register will be used in either
5275 case, we'd prefer it be used from the simpler giv. */
5281 /* Try to eliminate the biv, if it is a candidate.
5282 This won't work if ! bl->all_reduced,
5283 since the givs we planned to use might not have been reduced.
5285 We have to be careful that we didn't initially think we could
5286 eliminate this biv because of a giv that we now think may be
5287 dead and shouldn't be used as a biv replacement.
5289 Also, there is the possibility that we may have a giv that looks
5290 like it can be used to eliminate a biv, but the resulting insn
5291 isn't valid. This can happen, for example, on the 88k, where a
5292 JUMP_INSN can compare a register only with zero. Attempts to
5293 replace it with a compare with a constant will fail.
5295 Note that in cases where this call fails, we may have replaced some
5296 of the occurrences of the biv with a giv, but no harm was done in
5297 doing so in the rare cases where it can occur. */
5301 {
5302 /* ?? If we created a new test to bypass the loop entirely,
5303 or otherwise drop straight in, based on this test, then
5304 we might want to rewrite it also. This way some later
5305 pass has more hope of removing the initialization of this
5306 biv entirely. */
5308 /* If final_value != 0, then the biv may be used after loop end
5309 and we must emit an insn to set it just in case.
5311 Reversed bivs already have an insn after the loop setting their
5312 value, so we don't need another one. We can't calculate the
5313 proper final value for such a biv here anyways. */
5322 }
5323 /* See above note wrt final_value. But since we couldn't eliminate
5324 the biv, we must set the value after the loop instead of before. */
5328 }
5330 /* Go through all the instructions in the loop, making all the
5331 register substitutions scheduled in REG_MAP. */
5336 {
5340 }
5343 {
5344 /* When we completely unroll a loop we will likely not need the increment
5345 of the loop BIV and we will not need the conditional branch at the
5346 end of the loop. */
5349 #ifdef HAVE_cc0
5350 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5351 need the comparison before the conditional branch at the end of the
5352 loop. */
5354 #endif
5356 /* We'll need one copy for each loop iteration. */
5359 /* A little slop to account for the ability to remove initialization
5360 code, better CSE, and other secondary benefits of completely
5361 unrolling some loops. */
5364 /* Clamp the value. */
5367 }
5369 /* Unroll loops from within strength reduction so that we can use the
5370 induction variable information that strength_reduce has already
5371 collected. Always unroll loops that would be as small or smaller
5372 unrolled than when rolled. */
5379 #ifdef HAVE_doloop_end
5384 /* In case number of iterations is known, drop branch prediction note
5385 in the branch. Do that only in second loop pass, as loop unrolling
5386 may change the number of iterations performed. */
5388 {
5389 unsigned HOST_WIDE_INT n
5394 }
5402 }
5403 \f
5404 /*Record all basic induction variables calculated in the insn. */
5405 static rtx
5408 {
5410 rtx set;
5411 rtx dest_reg;
5412 rtx inc_val;
5413 rtx mult_val;
5419 {
5424 {
5429 {
5430 /* It is a possible basic induction variable.
5431 Create and initialize an induction structure for it. */
5438 }
5441 }
5442 }
5444 }
5445 \f
5446 /* Record all givs calculated in the insn.
5447 A register is a giv if: it is only set once, it is a function of a
5448 biv and a constant (or invariant), and it is not a biv. */
5449 static rtx
5452 {
5455 rtx set;
5456 /* Look for a general induction variable in a register. */
5461 {
5462 rtx src_reg;
5463 rtx dest_reg;
5464 rtx add_val;
5465 rtx mult_val;
5466 rtx ext_val;
5469 rtx last_consec_insn;
5478 /* Equivalent expression is a giv. */
5483 /* Don't try to handle any regs made by loop optimization.
5484 We have nothing on them in regno_first_uid, etc. */
5486 /* Don't recognize a BASIC_INDUCT_VAR here. */
5488 /* This must be the only place where the register is set. */
5490 /* or all sets must be consecutive and make a giv. */
5495 {
5498 /* If this is a library call, increase benefit. */
5502 /* Skip the consecutive insns, if there are any. */
5510 }
5511 }
5513 /* Look for givs which are memory addresses. */
5516 maybe_multiple);
5518 /* Update the status of whether giv can derive other givs. This can
5519 change when we pass a label or an insn that updates a biv. */
5524 }
5525 \f
5526 /* Return 1 if X is a valid source for an initial value (or as value being
5527 compared against in an initial test).
5529 X must be either a register or constant and must not be clobbered between
5530 the current insn and the start of the loop.
5532 INSN is the insn containing X. */
5534 static int
5536 {
5540 /* Only consider pseudos we know about initialized in insns whose luids
5541 we know. */
5546 /* Don't use call-clobbered registers across a call which clobbers it. On
5547 some machines, don't use any hard registers at all. */
5549 && (SMALL_REGISTER_CLASSES
5553 /* Don't use registers that have been clobbered before the start of the
5554 loop. */
5559 }
5560 \f
5561 /* Scan X for memory refs and check each memory address
5562 as a possible giv. INSN is the insn whose pattern X comes from.
5563 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5564 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5565 more than once in each loop iteration. */
5567 static void
5570 {
5580 {
5596 {
5597 rtx src_reg;
5598 rtx add_val;
5599 rtx mult_val;
5600 rtx ext_val;
5603 /* This code used to disable creating GIVs with mult_val == 1 and
5604 add_val == 0. However, this leads to lost optimizations when
5605 it comes time to combine a set of related DEST_ADDR GIVs, since
5606 this one would not be seen. */
5611 {
5612 /* Found one; record it. */
5620 }
5621 }
5626 }
5628 /* Recursively scan the subexpressions for other mem refs. */
5634 maybe_multiple);
5638 maybe_multiple);
5639 }
5640 \f
5641 /* Fill in the data about one biv update.
5642 V is the `struct induction' in which we record the biv. (It is
5643 allocated by the caller, with alloca.)
5644 INSN is the insn that sets it.
5645 DEST_REG is the biv's reg.
5647 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5648 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5649 being set to INC_VAL.
5651 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5652 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5653 can be executed more than once per iteration. If MAYBE_MULTIPLE
5654 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5655 executed exactly once per iteration. */
5657 static void
5661 {
5678 /* Add this to the reg's iv_class, creating a class
5679 if this is the first incrementation of the reg. */
5683 {
5684 /* Create and initialize new iv_class. */
5694 /* Set initial value to the reg itself. */
5697 /* We haven't seen the initializing insn yet. */
5707 /* Add this class to ivs->list. */
5711 /* Put it in the array of biv register classes. */
5713 }
5714 else
5715 {
5716 /* Check if location is the same as a previous one. */
5720 {
5723 }
5724 }
5726 /* Update IV_CLASS entry for this biv. */
5735 }
5736 \f
5737 /* Fill in the data about one giv.
5738 V is the `struct induction' in which we record the giv. (It is
5739 allocated by the caller, with alloca.)
5740 INSN is the insn that sets it.
5741 BENEFIT estimates the savings from deleting this insn.
5742 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5743 into a register or is used as a memory address.
5745 SRC_REG is the biv reg which the giv is computed from.
5746 DEST_REG is the giv's reg (if the giv is stored in a reg).
5747 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5748 LOCATION points to the place where this giv's value appears in INSN. */
5750 static void
5755 {
5760 rtx temp;
5762 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5763 undo the MULT canonicalization that we performed earlier. */
5793 /* The v->always_computable field is used in update_giv_derive, to
5794 determine whether a giv can be used to derive another giv. For a
5795 DEST_REG giv, INSN computes a new value for the giv, so its value
5796 isn't computable if INSN insn't executed every iteration.
5797 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5798 it does not compute a new value. Hence the value is always computable
5799 regardless of whether INSN is executed each iteration. */
5803 else
5809 {
5812 }
5814 {
5819 /* If the lifetime is zero, it means that this register is
5820 really a dead store. So mark this as a giv that can be
5821 ignored. This will not prevent the biv from being eliminated. */
5827 }
5829 /* Add the giv to the class of givs computed from one biv. */
5833 {
5836 /* Don't count DEST_ADDR. This is supposed to count the number of
5837 insns that calculate givs. */
5841 }
5842 else
5843 /* Fatal error, biv missing for this giv? */
5847 {
5850 }
5851 else
5852 {
5853 /* The giv can be replaced outright by the reduced register only if all
5854 of the following conditions are true:
5855 - the insn that sets the giv is always executed on any iteration
5856 on which the giv is used at all
5857 (there are two ways to deduce this:
5858 either the insn is executed on every iteration,
5859 or all uses follow that insn in the same basic block),
5860 - the giv is not used outside the loop
5861 - no assignments to the biv occur during the giv's lifetime. */
5864 /* Previous line always fails if INSN was moved by loop opt. */
5867 && (! not_every_iteration
5869 {
5870 /* Now check that there are no assignments to the biv within the
5871 giv's lifetime. This requires two separate checks. */
5873 /* Check each biv update, and fail if any are between the first
5874 and last use of the giv.
5876 If this loop contains an inner loop that was unrolled, then
5877 the insn modifying the biv may have been emitted by the loop
5878 unrolling code, and hence does not have a valid luid. Just
5879 mark the biv as not replaceable in this case. It is not very
5880 useful as a biv, because it is used in two different loops.
5881 It is very unlikely that we would be able to optimize the giv
5882 using this biv anyways. */
5887 {
5893 {
5897 }
5898 }
5900 /* If there are any backwards branches that go from after the
5901 biv update to before it, then this giv is not replaceable. */
5905 {
5909 }
5910 }
5911 else
5912 {
5913 /* May still be replaceable, we don't have enough info here to
5914 decide. */
5917 }
5918 }
5920 /* Record whether the add_val contains a const_int, for later use by
5921 combine_givs. */
5922 {
5927 ;
5931 {
5933 {
5938 else
5940 }
5943 }
5944 }
5948 }
5950 /* All this does is determine whether a giv can be made replaceable because
5951 its final value can be calculated. This code can not be part of record_giv
5952 above, because final_giv_value requires that the number of loop iterations
5953 be known, and that can not be accurately calculated until after all givs
5954 have been identified. */
5956 static void
5958 {
5961 /* DEST_ADDR givs will never reach here, because they are always marked
5962 replaceable above in record_giv. */
5964 /* The giv can be replaced outright by the reduced register only if all
5965 of the following conditions are true:
5966 - the insn that sets the giv is always executed on any iteration
5967 on which the giv is used at all
5968 (there are two ways to deduce this:
5969 either the insn is executed on every iteration,
5970 or all uses follow that insn in the same basic block),
5971 - its final value can be calculated (this condition is different
5972 than the one above in record_giv)
5973 - it's not used before the it's set
5974 - no assignments to the biv occur during the giv's lifetime. */
5976 #if 0
5977 /* This is only called now when replaceable is known to be false. */
5978 /* Clear replaceable, so that it won't confuse final_giv_value. */
5980 #endif
5985 {
5988 rtx last_giv_use;
5993 /* When trying to determine whether or not a biv increment occurs
5994 during the lifetime of the giv, we can ignore uses of the variable
5995 outside the loop because final_value is true. Hence we can not
5996 use regno_last_uid and regno_first_uid as above in record_giv. */
5998 /* Search the loop to determine whether any assignments to the
5999 biv occur during the giv's lifetime. Start with the insn
6000 that sets the giv, and search around the loop until we come
6001 back to that insn again.
6003 Also fail if there is a jump within the giv's lifetime that jumps
6004 to somewhere outside the lifetime but still within the loop. This
6005 catches spaghetti code where the execution order is not linear, and
6006 hence the above test fails. Here we assume that the giv lifetime
6007 does not extend from one iteration of the loop to the next, so as
6008 to make the test easier. Since the lifetime isn't known yet,
6009 this requires two loops. See also record_giv above. */
6014 {
6017 {
6020 }
6026 {
6027 /* It is possible for the BIV increment to use the GIV if we
6028 have a cycle. Thus we must be sure to check each insn for
6029 both BIV and GIV uses, and we must check for BIV uses
6030 first. */
6037 {
6039 {
6043 }
6045 }
6046 }
6047 }
6049 /* Now that the lifetime of the giv is known, check for branches
6050 from within the lifetime to outside the lifetime if it is still
6051 replaceable. */
6054 {
6057 {
6070 {
6079 }
6080 }
6081 }
6083 /* If it is replaceable, then save the final value. */
6086 }
6091 }
6092 \f
6093 /* Update the status of whether a giv can derive other givs.
6095 We need to do something special if there is or may be an update to the biv
6096 between the time the giv is defined and the time it is used to derive
6097 another giv.
6099 In addition, a giv that is only conditionally set is not allowed to
6100 derive another giv once a label has been passed.
6102 The cases we look at are when a label or an update to a biv is passed. */
6104 static void
6106 {
6110 rtx tem;
6113 /* Search all IV classes, then all bivs, and finally all givs.
6115 There are three cases we are concerned with. First we have the situation
6116 of a giv that is only updated conditionally. In that case, it may not
6117 derive any givs after a label is passed.
6119 The second case is when a biv update occurs, or may occur, after the
6120 definition of a giv. For certain biv updates (see below) that are
6121 known to occur between the giv definition and use, we can adjust the
6122 giv definition. For others, or when the biv update is conditional,
6123 we must prevent the giv from deriving any other givs. There are two
6124 sub-cases within this case.
6126 If this is a label, we are concerned with any biv update that is done
6127 conditionally, since it may be done after the giv is defined followed by
6128 a branch here (actually, we need to pass both a jump and a label, but
6129 this extra tracking doesn't seem worth it).
6131 If this is a jump, we are concerned about any biv update that may be
6132 executed multiple times. We are actually only concerned about
6133 backward jumps, but it is probably not worth performing the test
6134 on the jump again here.
6136 If this is a biv update, we must adjust the giv status to show that a
6137 subsequent biv update was performed. If this adjustment cannot be done,
6138 the giv cannot derive further givs. */
6144 {
6145 /* Skip if location is the same as a previous one. */
6150 {
6151 /* If cant_derive is already true, there is no point in
6152 checking all of these conditions again. */
6156 /* If this giv is conditionally set and we have passed a label,
6157 it cannot derive anything. */
6161 /* Skip givs that have mult_val == 0, since
6162 they are really invariants. Also skip those that are
6163 replaceable, since we know their lifetime doesn't contain
6164 any biv update. */
6168 /* The only way we can allow this giv to derive another
6169 is if this is a biv increment and we can form the product
6170 of biv->add_val and giv->mult_val. In this case, we will
6171 be able to compute a compensation. */
6173 {
6174 rtx ext_val_dummy;
6185 tem = simplify_giv_expr
6192 else
6194 }
6198 }
6199 }
6200 }
6201 \f
6202 /* Check whether an insn is an increment legitimate for a basic induction var.
6203 X is the source of insn P, or a part of it.
6204 MODE is the mode in which X should be interpreted.
6206 DEST_REG is the putative biv, also the destination of the insn.
6207 We accept patterns of these forms:
6208 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6209 REG = INVARIANT + REG
6211 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6212 store the additive term into *INC_VAL, and store the place where
6213 we found the additive term into *LOCATION.
6215 If X is an assignment of an invariant into DEST_REG, we set
6216 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6218 We also want to detect a BIV when it corresponds to a variable
6219 whose mode was promoted. In that case, an increment
6220 of the variable may be a PLUS that adds a SUBREG of that variable to
6221 an invariant and then sign- or zero-extends the result of the PLUS
6222 into the variable.
6224 Most GIVs in such cases will be in the promoted mode, since that is the
6225 probably the natural computation mode (and almost certainly the mode
6226 used for addresses) on the machine. So we view the pseudo-reg containing
6227 the variable as the BIV, as if it were simply incremented.
6229 Note that treating the entire pseudo as a BIV will result in making
6230 simple increments to any GIVs based on it. However, if the variable
6231 overflows in its declared mode but not its promoted mode, the result will
6232 be incorrect. This is acceptable if the variable is signed, since
6233 overflows in such cases are undefined, but not if it is unsigned, since
6234 those overflows are defined. So we only check for SIGN_EXTEND and
6235 not ZERO_EXTEND.
6237 If we cannot find a biv, we return 0. */
6239 static int
6243 {
6251 {
6257 {
6259 }
6264 {
6266 }
6267 else
6274 /* convert_modes can emit new instructions, e.g. when arg is a loop
6275 invariant MEM and dest_reg has a different mode.
6276 These instructions would be emitted after the end of the function
6277 and then *inc_val would be an uninitialized pseudo.
6278 Detect this and bail in this case.
6279 Other alternatives to solve this can be introducing a convert_modes
6280 variant which is allowed to fail but not allowed to emit new
6281 instructions, emit these instructions before loop start and let
6282 it be garbage collected if *inc_val is never used or saving the
6283 *inc_val initialization sequence generated here and when *inc_val
6284 is going to be actually used, emit it at some suitable place. */
6288 {
6291 }
6299 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6300 handle addition of promoted variables.
6301 ??? The comment at the start of this function is wrong: promoted
6302 variable increments don't look like it says they do. */
6308 /* If this register is assigned in a previous insn, look at its
6309 source, but don't go outside the loop or past a label. */
6311 /* If this sets a register to itself, we would repeat any previous
6312 biv increment if we applied this strategy blindly. */
6318 {
6319 rtx dest;
6320 do
6321 {
6323 }
6352 }
6353 /* Fall through. */
6355 /* Can accept constant setting of biv only when inside inner most loop.
6356 Otherwise, a biv of an inner loop may be incorrectly recognized
6357 as a biv of the outer loop,
6358 causing code to be moved INTO the inner loop. */
6365 /* convert_modes aborts if we try to convert to or from CCmode, so just
6366 exclude that case. It is very unlikely that a condition code value
6367 would be a useful iterator anyways. convert_modes aborts if we try to
6368 convert a float mode to non-float or vice versa too. */
6372 {
6373 /* Possible bug here? Perhaps we don't know the mode of X. */
6377 {
6380 }
6385 }
6386 else
6390 /* Ignore this BIV if signed arithmetic overflow is defined. */
6397 /* Similar, since this can be a sign extension. */
6402 ;
6416 location);
6421 }
6422 }
6423 \f
6424 /* A general induction variable (giv) is any quantity that is a linear
6425 function of a basic induction variable,
6426 i.e. giv = biv * mult_val + add_val.
6427 The coefficients can be any loop invariant quantity.
6428 A giv need not be computed directly from the biv;
6429 it can be computed by way of other givs. */
6431 /* Determine whether X computes a giv.
6432 If it does, return a nonzero value
6433 which is the benefit from eliminating the computation of X;
6434 set *SRC_REG to the register of the biv that it is computed from;
6435 set *ADD_VAL and *MULT_VAL to the coefficients,
6436 such that the value of X is biv * mult + add; */
6438 static int
6443 {
6447 /* If this is an invariant, forget it, it isn't a giv. */
6458 {
6461 /* Since this is now an invariant and wasn't before, it must be a giv
6462 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6463 with. */
6470 /* This is equivalent to a BIV. */
6477 /* Either (plus (biv) (invar)) or
6478 (plus (mult (biv) (invar_1)) (invar_2)). */
6480 {
6483 }
6484 else
6485 {
6488 }
6493 /* ADD_VAL is zero. */
6501 }
6503 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6504 unless they are CONST_INT). */
6512 else
6515 /* Always return true if this is a giv so it will be detected as such,
6516 even if the benefit is zero or negative. This allows elimination
6517 of bivs that might otherwise not be eliminated. */
6519 }
6520 \f
6521 /* Given an expression, X, try to form it as a linear function of a biv.
6522 We will canonicalize it to be of the form
6523 (plus (mult (BIV) (invar_1))
6524 (invar_2))
6525 with possible degeneracies.
6527 The invariant expressions must each be of a form that can be used as a
6528 machine operand. We surround then with a USE rtx (a hack, but localized
6529 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6530 routine; it is the caller's responsibility to strip them.
6532 If no such canonicalization is possible (i.e., two biv's are used or an
6533 expression that is neither invariant nor a biv or giv), this routine
6534 returns 0.
6536 For a nonzero return, the result will have a code of CONST_INT, USE,
6537 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6539 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6544 static rtx
6546 {
6551 rtx tem;
6553 /* If this is not an integer mode, or if we cannot do arithmetic in this
6554 mode, this can't be a giv. */
6561 {
6568 /* Put constant last, CONST_INT last if both constant. */
6576 /* Handle addition of zero, then addition of an invariant. */
6581 {
6584 /* Adding two invariants must result in an invariant, so enclose
6585 addition operation inside a USE and return it. */
6595 else
6604 /* biv + invar or mult + invar. Return sum. */
6608 /* (a + invar_1) + invar_2. Associate. */
6609 return
6615 arg1)),
6620 }
6622 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6623 MULT to reduce cases. */
6629 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6630 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6631 Recurse to associate the second PLUS. */
6636 return
6644 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6660 /* Handle "a - b" as "a + b * (-1)". */
6666 constm1_rtx)),
6675 /* Put constant last, CONST_INT last if both constant. */
6680 /* If second argument is not now constant, not giv. */
6684 /* Handle multiply by 0 or 1. */
6692 {
6694 /* biv * invar. Done. */
6698 /* Product of two constants. */
6702 /* invar * invar is a giv, but attempt to simplify it somehow. */
6708 {
6709 /* (invar_0 * invar_1) * invar_2. Associate. */
6716 arg1)),
6718 }
6719 /* Propagate the MULT expressions to the innermost nodes. */
6721 {
6722 /* (invar_0 + invar_1) * invar_2. Distribute. */
6728 arg1),
6732 arg1)),
6734 }
6738 /* (a * invar_1) * invar_2. Associate. */
6744 arg1)),
6748 /* (a + invar_1) * invar_2. Distribute. */
6753 arg1),
6756 arg1)),
6761 }
6764 /* Shift by constant is multiply by power of two. */
6768 return
6777 /* "-a" is "a * (-1)" */
6783 /* "~a" is "-a - 1". Silly, but easy. */
6787 const1_rtx),
6791 /* Already in proper form for invariant. */
6797 /* Conditionally recognize extensions of simple IVs. After we've
6798 computed loop traversal counts and verified the range of the
6799 source IV, we'll reevaluate this as a GIV. */
6801 {
6804 {
6807 }
6808 }
6812 /* If this is a new register, we can't deal with it. */
6816 /* Check for biv or giv. */
6818 {
6822 {
6825 /* Form expression from giv and add benefit. Ensure this giv
6826 can derive another and subtract any needed adjustment if so. */
6828 /* Increasing the benefit here is risky. The only case in which it
6829 is arguably correct is if this is the only use of V. In other
6830 cases, this will artificially inflate the benefit of the current
6831 giv, and lead to suboptimal code. Thus, it is disabled, since
6832 potentially not reducing an only marginally beneficial giv is
6833 less harmful than reducing many givs that are not really
6834 beneficial. */
6835 {
6839 }
6852 {
6855 }
6856 else
6857 {
6860 }
6862 }
6865 do_default:
6866 /* If it isn't an induction variable, and it is invariant, we
6867 may be able to simplify things further by looking through
6868 the bits we just moved outside the loop. */
6870 {
6876 {
6877 /* Ok, we found a match. Substitute and simplify. */
6879 /* If we match another movable, we must use that, as
6880 this one is going away. */
6885 /* If consec is nonzero, this is a member of a group of
6886 instructions that were moved together. We handle this
6887 case only to the point of seeking to the last insn and
6888 looking for a REG_EQUAL. Fail if we don't find one. */
6890 {
6893 do
6894 {
6896 }
6902 }
6903 else
6904 {
6908 }
6911 {
6912 /* What we are most interested in is pointer
6913 arithmetic on invariants -- only take
6914 patterns we may be able to do something with. */
6920 {
6922 benefit);
6925 }
6930 {
6935 }
6936 }
6938 }
6939 }
6941 }
6943 /* Fall through to general case. */
6945 /* If invariant, return as USE (unless CONST_INT).
6946 Otherwise, not giv. */
6951 {
6960 }
6961 else
6963 }
6964 }
6966 /* This routine folds invariants such that there is only ever one
6967 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6969 static rtx
6971 {
6977 {
6980 }
6983 {
6986 }
6987 else
6988 {
6991 }
6992 }
6994 static rtx
6996 {
6998 {
7002 else
7005 }
7008 else
7011 }
7012 \f
7013 /* Help detect a giv that is calculated by several consecutive insns;
7014 for example,
7015 giv = biv * M
7016 giv = giv + A
7017 The caller has already identified the first insn P as having a giv as dest;
7018 we check that all other insns that set the same register follow
7019 immediately after P, that they alter nothing else,
7020 and that the result of the last is still a giv.
7022 The value is 0 if the reg set in P is not really a giv.
7023 Otherwise, the value is the amount gained by eliminating
7024 all the consecutive insns that compute the value.
7026 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
7027 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
7029 The coefficients of the ultimate giv value are stored in
7030 *MULT_VAL and *ADD_VAL. */
7032 static int
7036 {
7042 rtx temp;
7043 rtx set;
7045 /* Indicate that this is a giv so that we can update the value produced in
7046 each insn of the multi-insn sequence.
7048 This induction structure will be used only by the call to
7049 general_induction_var below, so we can allocate it on our stack.
7050 If this is a giv, our caller will replace the induct var entry with
7051 a new induction structure. */
7072 {
7076 /* If libcall, skip to end of call sequence. */
7087 /* Giv created by equivalent expression. */
7093 {
7097 count--;
7101 }
7103 {
7104 /* Allow insns that set something other than this giv to a
7105 constant. Such insns are needed on machines which cannot
7106 include long constants and should not disqualify a giv. */
7115 }
7116 }
7121 }
7122 \f
7123 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7124 represented by G1. If no such expression can be found, or it is clear that
7125 it cannot possibly be a valid address, 0 is returned.
7127 To perform the computation, we note that
7128 G1 = x * v + a and
7129 G2 = y * v + b
7130 where `v' is the biv.
7132 So G2 = (y/b) * G1 + (b - a*y/x).
7134 Note that MULT = y/x.
7136 Update: A and B are now allowed to be additive expressions such that
7137 B contains all variables in A. That is, computing B-A will not require
7138 subtracting variables. */
7140 static rtx
7142 {
7143 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7148 /* If MULT is not 1, we cannot handle A with non-constants, since we
7149 would then be required to subtract multiples of the registers in A.
7150 This is theoretically possible, and may even apply to some Fortran
7151 constructs, but it is a lot of work and we do not attempt it here. */
7156 /* In general these structures are sorted top to bottom (down the PLUS
7157 chain), but not left to right across the PLUS. If B is a higher
7158 order giv than A, we can strip one level and recurse. If A is higher
7159 order, we'll eventually bail out, but won't know that until the end.
7160 If they are the same, we'll strip one level around this loop. */
7163 {
7175 /* We matched: remove one reg completely. */
7178 /* An alternate match. */
7181 /* An alternate match. */
7183 else
7184 {
7185 /* Indicates an extra register in B. Strip one level from B and
7186 recurse, hoping B was the higher order expression. */
7191 }
7192 }
7194 /* Here we are at the last level of A, go through the cases hoping to
7195 get rid of everything but a constant. */
7198 {
7211 }
7213 {
7215 }
7217 {
7222 }
7224 {
7229 else
7231 }
7236 }
7238 rtx
7240 {
7243 /* The value that G1 will be multiplied by must be a constant integer. Also,
7244 the only chance we have of getting a valid address is if b*c/a (see above
7245 for notation) is also an integer. */
7248 {
7256 }
7259 else
7260 {
7261 /* ??? Find out if the one is a multiple of the other? */
7263 }
7267 {
7268 /* Failed. If we've got a multiplication factor between G1 and G2,
7269 scale G1's addend and try again. */
7271 {
7275 {
7276 HOST_WIDE_INT m;
7280 }
7281 else
7282 {
7284 mult);
7285 }
7288 }
7289 }
7293 /* Form simplified final result. */
7298 else
7303 else
7304 {
7307 {
7311 }
7314 }
7315 }
7316 \f
7317 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7318 represented by G1. This indicates that G2 should be combined with G1 and
7319 that G2 can use (either directly or via an address expression) a register
7320 used to represent G1. */
7322 static rtx
7324 {
7327 /* With the introduction of ext dependent givs, we must care for modes.
7328 G2 must not use a wider mode than G1. */
7338 /* If these givs are identical, they can be combined. We use the results
7339 of express_from because the addends are not in a canonical form, so
7340 rtx_equal_p is a weaker test. */
7341 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7342 combination to be the other way round. */
7345 {
7347 }
7349 /* If G2 can be expressed as a function of G1 and that function is valid
7350 as an address and no more expensive than using a register for G2,
7351 the expression of G2 in terms of G1 can be used. */
7358 }
7359 \f
7360 /* Check each extension dependent giv in this class to see if its
7361 root biv is safe from wrapping in the interior mode, which would
7362 make the giv illegal. */
7364 static void
7366 {
7370 HOST_WIDE_INT start_val;
7376 /* Make sure the iteration data is available. We must have
7377 constants in order to be certain of no overflow. */
7383 /* Make sure the host can represent the arithmetic. */
7385 {
7387 HOST_WIDE_INT s_end_val;
7399 /* Check for host arithmetic overflow. */
7401 {
7403 HOST_WIDE_INT s_max;
7410 /* Check zero extension of biv ok. */
7412 /* Check for host arithmetic overflow. */
7413 && (neg_incr
7416 /* Check for target arithmetic overflow. */
7417 && (neg_incr
7420 {
7422 }
7424 /* Check sign extension of biv ok. */
7425 /* ??? While it is true that overflow with signed and pointer
7426 arithmetic is undefined, I fear too many programmers don't
7427 keep this fact in mind -- myself included on occasion.
7428 So leave alone with the signed overflow optimizations. */
7430 /* Check for host arithmetic overflow. */
7431 && (neg_incr
7434 /* Check for target arithmetic overflow. */
7435 && (neg_incr
7438 {
7440 }
7441 }
7442 }
7444 /* If we know the BIV is compared at run-time against an
7445 invariant value, and the increment is +/- 1, we may also
7446 be able to prove that the BIV cannot overflow. */
7452 {
7453 /* If the increment is +1, and the exit test is a <,
7454 the BIV cannot overflow. (For <=, we have the
7455 problematic case that the comparison value might
7456 be the maximum value of the range.) */
7458 {
7463 }
7465 /* Likewise for increment -1 and exit test >. */
7467 {
7472 }
7473 }
7475 /* Invalidate givs that fail the tests. */
7478 {
7483 {
7492 /* We don't know whether this value is being used as either
7493 signed or unsigned, so to safely truncate we must satisfy
7494 both. The initial check here verifies the BIV itself;
7495 once that is successful we may check its range wrt the
7496 derived GIV. This works only if we were able to determine
7497 constant start and end values above. */
7499 {
7503 /* We know from the above that both endpoints are nonnegative,
7504 and that there is no wrapping. Verify that both endpoints
7505 are within the (signed) range of the outer mode. */
7508 }
7513 }
7516 {
7518 {
7522 }
7523 }
7524 else
7525 {
7527 {
7532 else
7533 {
7538 else
7540 }
7545 }
7548 }
7549 }
7550 }
7552 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7554 rtx
7556 {
7562 /* Recall that check_ext_dependent_givs verified that the known bounds
7563 of a biv did not overflow or wrap with respect to the extension for
7564 the giv. Therefore, constants need no additional adjustment. */
7568 /* Otherwise, we must adjust the value to compensate for the
7569 differing modes of the biv and the giv. */
7571 }
7572 \f
7573 struct combine_givs_stats
7574 {
7577 };
7579 static int
7581 {
7588 /* Stabilize the sort. */
7592 }
7594 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7595 any other. If so, point SAME to the giv combined with and set NEW_REG to
7596 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7597 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7599 static void
7601 {
7602 /* Additional benefit to add for being combined multiple times. */
7610 /* Count givs, because bl->giv_count is incorrect here. */
7614 giv_count++;
7626 {
7628 rtx single_use;
7633 /* If a DEST_REG GIV is used only once, do not allow it to combine
7634 with anything, for in doing so we will gain nothing that cannot
7635 be had by simply letting the GIV with which we would have combined
7636 to be reduced on its own. The losage shows up in particular with
7637 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7638 be seen elsewhere as well. */
7645 /* Add an additional weight for zero addends. */
7650 {
7651 rtx this_combine;
7656 {
7659 }
7660 }
7662 }
7664 /* Iterate, combining until we can't. */
7665 restart:
7669 {
7672 {
7678 }
7680 }
7683 {
7689 /* If it has already been combined, skip. */
7694 {
7697 /* If it has already been combined, skip. */
7699 {
7704 /* For destination, we now may replace by mem expression instead
7705 of register. This changes the costs considerably, so add the
7706 compensation. */
7716 /* ??? The new final_[bg]iv_value code does a much better job
7717 of finding replaceable giv's, and hence this code may no
7718 longer be necessary. */
7722 /* To help optimize the next set of combinations, remove
7723 this giv from the benefits of other potential mates. */
7725 {
7729 }
7736 }
7737 }
7739 /* To help optimize the next set of combinations, remove
7740 this giv from the benefits of other potential mates. */
7742 {
7744 {
7748 }
7752 /* We've finished with this giv, and everything it touched.
7753 Restart the combination so that proper weights for the
7754 rest of the givs are properly taken into account. */
7755 /* ??? Ideally we would compact the arrays at this point, so
7756 as to not cover old ground. But sanely compacting
7757 can_combine is tricky. */
7759 }
7760 }
7762 /* Clean up. */
7765 }
7766 \f
7767 /* Generate sequence for REG = B * M + A. B is the initial value of
7768 the basic induction variable, M a multiplicative constant, A an
7769 additive constant and REG the destination register. */
7771 static rtx
7773 {
7774 rtx seq;
7775 rtx result;
7778 /* Use unsigned arithmetic. */
7786 }
7789 /* Update registers created in insn sequence SEQ. */
7791 static void
7793 {
7794 rtx insn;
7796 /* Update register info for alias analysis. */
7800 {
7807 }
7808 }
7811 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7812 is the initial value of the basic induction variable, M a
7813 multiplicative constant, A an additive constant and REG the
7814 destination register. */
7816 void
7819 {
7820 rtx seq;
7823 {
7826 }
7828 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7831 /* Increase the lifetime of any invariants moved further in code. */
7836 /* It is possible that the expansion created lots of new registers.
7837 Iterate over the sequence we just created and record them all. We
7838 must do this before inserting the sequence. */
7842 }
7845 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7846 initial value of the basic induction variable, M a multiplicative
7847 constant, A an additive constant and REG the destination
7848 register. */
7850 void
7852 {
7853 rtx seq;
7855 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7858 /* Increase the lifetime of any invariants moved further in code.
7859 ???? Is this really necessary? */
7864 /* It is possible that the expansion created lots of new registers.
7865 Iterate over the sequence we just created and record them all. We
7866 must do this before inserting the sequence. */
7870 }
7873 /* Emit insns after loop to set REG = B * M + A. B is the initial
7874 value of the basic induction variable, M a multiplicative constant,
7875 A an additive constant and REG the destination register. */
7877 void
7879 {
7880 rtx seq;
7882 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7885 /* It is possible that the expansion created lots of new registers.
7886 Iterate over the sequence we just created and record them all. We
7887 must do this before inserting the sequence. */
7891 }
7895 /* Similar to gen_add_mult, but compute cost rather than generating
7896 sequence. */
7898 static int
7900 {
7910 {
7915 }
7918 }
7919 \f
7920 /* Test whether A * B can be computed without
7921 an actual multiply insn. Value is 1 if so.
7923 ??? This function stinks because it generates a ton of wasted RTL
7924 ??? and as a result fragments GC memory to no end. There are other
7925 ??? places in the compiler which are invoked a lot and do the same
7926 ??? thing, generate wasted RTL just to see if something is possible. */
7928 static int
7930 {
7931 rtx tmp;
7934 /* If only one is constant, make it B. */
7938 /* If first constant, both constant, so don't need multiply. */
7942 /* If second not constant, neither is constant, so would need multiply. */
7946 /* One operand is constant, so might not need multiply insn. Generate the
7947 code for the multiply and see if a call or multiply, or long sequence
7948 of insns is generated. */
7957 {
7960 {
7970 {
7973 }
7976 }
7977 }
7987 }
7988 \f
7989 /* Check to see if loop can be terminated by a "decrement and branch until
7990 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7991 Also try reversing an increment loop to a decrement loop
7992 to see if the optimization can be performed.
7993 Value is nonzero if optimization was performed. */
7995 /* This is useful even if the architecture doesn't have such an insn,
7996 because it might change a loops which increments from 0 to n to a loop
7997 which decrements from n to 0. A loop that decrements to zero is usually
7998 faster than one that increments from zero. */
8000 /* ??? This could be rewritten to use some of the loop unrolling procedures,
8001 such as approx_final_value, biv_total_increment, loop_iterations, and
8002 final_[bg]iv_value. */
8004 static int
8006 {
8011 rtx reg;
8012 rtx jump_label;
8013 rtx final_value;
8014 rtx start_value;
8015 rtx new_add_val;
8016 rtx comparison;
8017 rtx before_comparison;
8018 rtx p;
8019 rtx jump;
8020 rtx first_compare;
8025 /* If last insn is a conditional branch, and the insn before tests a
8026 register value, try to optimize it. Otherwise, we can't do anything. */
8035 /* Try to compute whether the compare/branch at the loop end is one or
8036 two instructions. */
8042 else
8045 {
8046 /* If more than one condition is present to control the loop, then
8047 do not proceed, as this function does not know how to rewrite
8048 loop tests with more than one condition.
8050 Look backwards from the first insn in the last comparison
8051 sequence and see if we've got another comparison sequence. */
8053 rtx jump1;
8057 }
8059 /* Check all of the bivs to see if the compare uses one of them.
8060 Skip biv's set more than once because we can't guarantee that
8061 it will be zero on the last iteration. Also skip if the biv is
8062 used between its update and the test insn. */
8065 {
8070 first_compare))
8072 }
8074 /* Try swapping the comparison to identify a suitable biv. */
8081 first_compare))
8082 {
8084 VOIDmode,
8088 }
8093 /* Look for the case where the basic induction variable is always
8094 nonnegative, and equals zero on the last iteration.
8095 In this case, add a reg_note REG_NONNEG, which allows the
8096 m68k DBRA instruction to be used. */
8102 {
8103 /* Initial value must be greater than 0,
8104 init_val % -dec_value == 0 to ensure that it equals zero on
8105 the last iteration */
8111 {
8112 /* Register always nonnegative, add REG_NOTE to branch. */
8120 }
8122 /* If the decrement is 1 and the value was tested as >= 0 before
8123 the loop, then we can safely optimize. */
8125 {
8139 {
8147 }
8148 }
8149 }
8152 {
8153 /* Try to change inc to dec, so can apply above optimization. */
8154 /* Can do this if:
8155 all registers modified are induction variables or invariant,
8156 all memory references have non-overlapping addresses
8157 (obviously true if only one write)
8158 allow 2 insns for the compare/jump at the end of the loop. */
8159 /* Also, we must avoid any instructions which use both the reversed
8160 biv and another biv. Such instructions will fail if the loop is
8161 reversed. We meet this condition by requiring that either
8162 no_use_except_counting is true, or else that there is only
8163 one biv. */
8165 /* 1 if the iteration var is used only to count iterations. */
8167 /* 1 if the loop has no memory store, or it has a single memory store
8168 which is reversible. */
8174 {
8178 /* If there are no givs for this biv, and the only exit is the
8179 fall through at the end of the loop, then
8180 see if perhaps there are no uses except to count. */
8184 {
8189 /* An insn that sets the biv is okay. */
8190 ;
8192 /* An insn that doesn't mention the biv is okay. */
8193 ;
8196 {
8197 /* If either of these insns uses the biv and sets a pseudo
8198 that has more than one usage, then the biv has uses
8199 other than counting since it's used to derive a value
8200 that is used more than one time. */
8202 regs);
8204 {
8207 }
8208 }
8209 else
8210 {
8213 }
8214 }
8216 /* A biv has uses besides counting if it is used to set
8217 another biv. */
8221 {
8224 }
8225 }
8228 /* No need to worry about MEMs. */
8229 ;
8231 {
8236 /* If the loop has a single store, and the destination address is
8237 invariant, then we can't reverse the loop, because this address
8238 might then have the wrong value at loop exit.
8239 This would work if the source was invariant also, however, in that
8240 case, the insn should have been moved out of the loop. */
8243 {
8246 /* If we could prove that each of the memory locations
8247 written to was different, then we could reverse the
8248 store -- but we don't presently have any way of
8249 knowing that. */
8252 /* If the store depends on a register that is set after the
8253 store, it depends on the initial value, and is thus not
8254 reversible. */
8256 {
8263 }
8264 }
8265 }
8266 else
8269 /* This code only acts for innermost loops. Also it simplifies
8270 the memory address check by only reversing loops with
8271 zero or one memory access.
8272 Two memory accesses could involve parts of the same array,
8273 and that can't be reversed.
8274 If the biv is used only for counting, than we don't need to worry
8275 about all these things. */
8281 && reversible_mem_store
8286 {
8287 rtx tem;
8289 /* Loop can be reversed. */
8293 /* Now check other conditions:
8295 The increment must be a constant, as must the initial value,
8296 and the comparison code must be LT.
8298 This test can probably be improved since +/- 1 in the constant
8299 can be obtained by changing LT to LE and vice versa; this is
8300 confusing. */
8303 /* for constants, LE gets turned into LT */
8308 {
8319 comparison_const_width
8321 else
8322 comparison_const_width
8326 comparison_sign_mask
8329 /* If the comparison value is not a loop invariant, then we
8330 can not reverse this loop.
8332 ??? If the insns which initialize the comparison value as
8333 a whole compute an invariant result, then we could move
8334 them out of the loop and proceed with loop reversal. */
8342 /* Normalize the initial value if it is an integer and
8343 has no other use except as a counter. This will allow
8344 a few more loops to be reversed. */
8348 {
8350 /* The code below requires comparison_val to be a multiple
8351 of add_val in order to do the loop reversal, so
8352 round up comparison_val to a multiple of add_val.
8353 Since comparison_value is constant, we know that the
8354 current comparison code is LT. */
8356 comparison_val
8358 /* We postpone overflow checks for COMPARISON_VAL here;
8359 even if there is an overflow, we might still be able to
8360 reverse the loop, if converting the loop exit test to
8361 NE is possible. */
8363 }
8365 /* First check if we can do a vanilla loop reversal. */
8367 /* If we have a decrement_and_branch_on_count,
8368 prefer the NE test, since this will allow that
8369 instruction to be generated. Note that we must
8370 use a vanilla loop reversal if the biv is used to
8371 calculate a giv or has a non-counting use. */
8372 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8373 && defined (HAVE_decrement_and_branch_on_count)
8377 #endif
8379 /* Now do postponed overflow checks on COMPARISON_VAL. */
8382 {
8383 /* Register will always be nonnegative, with value
8384 0 on last iteration */
8388 }
8392 {
8395 }
8396 else
8402 /* If the initial value is not zero, or if the comparison
8403 value is not an exact multiple of the increment, then we
8404 can not reverse this loop. */
8407 {
8410 }
8411 else
8412 {
8415 }
8419 /* Reset these in case we normalized the initial value
8420 and comparison value above. */
8423 {
8425 final_value
8427 }
8430 /* Save some info needed to produce the new insns. */
8435 /* Set start_value; if this is not a CONST_INT, we need
8436 to generate a SUB.
8437 Initialize biv to start_value before loop start.
8438 The old initializing insn will be deleted as a
8439 dead store by flow.c. */
8442 {
8445 }
8447 {
8455 start_value
8461 }
8463 {
8466 initial_value);
8470 start_value
8473 }
8474 else
8475 /* We could handle the other cases too, but it'll be
8476 better to have a testcase first. */
8479 /* We may not have a single insn which can increment a reg, so
8480 create a sequence to hold all the insns from expand_inc. */
8489 /* Update biv info to reflect its new status. */
8494 /* Update loop info. */
8503 /* Inc LABEL_NUSES so that delete_insn will
8504 not delete the label. */
8507 /* Emit an insn after the end of the loop to set the biv's
8508 proper exit value if it is used anywhere outside the loop. */
8514 /* Delete compare/branch at end of loop. */
8519 /* Add new compare/branch insn at end of loop. */
8531 ;
8537 {
8539 {
8540 /* Increment of LABEL_NUSES done above. */
8541 /* Register is now always nonnegative,
8542 so add REG_NONNEG note to the branch. */
8545 }
8547 }
8549 /* No insn may reference both the reversed and another biv or it
8550 will fail (see comment near the top of the loop reversal
8551 code).
8552 Earlier on, we have verified that the biv has no use except
8553 counting, or it is the only biv in this function.
8554 However, the code that computes no_use_except_counting does
8555 not verify reg notes. It's possible to have an insn that
8556 references another biv, and has a REG_EQUAL note with an
8557 expression based on the reversed biv. To avoid this case,
8558 remove all REG_EQUAL notes based on the reversed biv
8559 here. */
8562 {
8565 /* If this is a set of a GIV based on the reversed biv, any
8566 REG_EQUAL notes should still be correct. */
8573 {
8578 else
8580 }
8581 }
8583 /* Mark that this biv has been reversed. Each giv which depends
8584 on this biv, and which is also live past the end of the loop
8585 will have to be fixed up. */
8590 {
8594 else
8596 }
8599 }
8600 }
8601 }
8604 }
8605 \f
8606 /* Verify whether the biv BL appears to be eliminable,
8607 based on the insns in the loop that refer to it.
8609 If ELIMINATE_P is nonzero, actually do the elimination.
8611 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8612 determine whether invariant insns should be placed inside or at the
8613 start of the loop. */
8615 static int
8618 {
8621 rtx p;
8623 /* Scan all insns in the loop, stopping if we find one that uses the
8624 biv in a way that we cannot eliminate. */
8627 {
8631 rtx note;
8633 /* If this is a libcall that sets a giv, skip ahead to its end. */
8635 {
8639 {
8644 {
8651 }
8652 }
8653 }
8655 /* Closely examine the insn if the biv is mentioned. */
8660 {
8666 }
8668 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8673 }
8676 {
8681 }
8684 }
8685 \f
8686 /* INSN and REFERENCE are instructions in the same insn chain.
8687 Return nonzero if INSN is first. */
8689 int
8691 {
8695 {
8696 /* Start with test for not first so that INSN == REFERENCE yields not
8697 first. */
8703 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8704 previous insn, hence the <= comparison below does not work if
8705 P is a note. */
8716 }
8717 }
8719 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8720 the offset that we have to take into account due to auto-increment /
8721 div derivation is zero. */
8722 static int
8725 {
8726 /* If the giv V had the auto-inc address optimization applied
8727 to it, and INSN occurs between the giv insn and the biv
8728 insn, then we'd have to adjust the value used here.
8729 This is rare, so we don't bother to make this possible. */
8738 }
8740 /* If BL appears in X (part of the pattern of INSN), see if we can
8741 eliminate its use. If so, return 1. If not, return 0.
8743 If BIV does not appear in X, return 1.
8745 If ELIMINATE_P is nonzero, actually do the elimination.
8746 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8747 Depending on how many items have been moved out of the loop, it
8748 will either be before INSN (when WHERE_INSN is nonzero) or at the
8749 start of the loop (when WHERE_INSN is zero). */
8751 static int
8755 {
8761 #ifdef HAVE_cc0
8763 #endif
8769 {
8771 /* If we haven't already been able to do something with this BIV,
8772 we can't eliminate it. */
8778 /* If this sets the BIV, it is not a problem. */
8782 /* If this is an insn that defines a giv, it is also ok because
8783 it will go away when the giv is reduced. */
8788 #ifdef HAVE_cc0
8790 {
8791 /* Can replace with any giv that was reduced and
8792 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8793 Require a constant for MULT_VAL, so we know it's nonzero.
8794 ??? We disable this optimization to avoid potential
8795 overflows. */
8803 {
8810 /* If the giv has the opposite direction of change,
8811 then reverse the comparison. */
8815 else
8818 /* We can probably test that giv's reduced reg. */
8821 }
8823 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8824 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8825 Require a constant for MULT_VAL, so we know it's nonzero.
8826 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8827 overflow problem. */
8839 {
8846 /* If the giv has the opposite direction of change,
8847 then reverse the comparison. */
8851 else
8855 /* Replace biv with the giv's reduced register. */
8860 /* Insn doesn't support that constant or invariant. Copy it
8861 into a register (it will be a loop invariant.) */
8868 /* Substitute the new register for its invariant value in
8869 the compare expression. */
8873 }
8874 }
8875 #endif
8882 /* See if either argument is the biv. */
8887 else
8891 {
8892 /* First try to replace with any giv that has constant positive
8893 mult_val and constant add_val. We might be able to support
8894 negative mult_val, but it seems complex to do it in general. */
8906 {
8910 /* Don't eliminate if the linear combination that makes up
8911 the giv overflows when it is applied to ARG. */
8913 {
8914 rtx add_val;
8918 else
8924 }
8929 /* Replace biv with the giv's reduced reg. */
8932 /* If all constants are actually constant integers and
8933 the derived constant can be directly placed in the COMPARE,
8934 do so. */
8937 {
8940 }
8941 else
8942 {
8943 /* Otherwise, load it into a register. */
8948 }
8954 }
8956 /* Look for giv with positive constant mult_val and nonconst add_val.
8957 Insert insns to calculate new compare value.
8958 ??? Turn this off due to possible overflow. */
8966 {
8967 rtx tem;
8977 /* Replace biv with giv's reduced register. */
8981 /* Compute value to compare against. */
8985 /* Use it in this insn. */
8989 }
8990 }
8992 {
8994 {
8995 /* Look for giv with constant positive mult_val and nonconst
8996 add_val. Insert insns to compute new compare value.
8997 ??? Turn this off due to possible overflow. */
9004 {
9005 rtx tem;
9015 /* Replace biv with giv's reduced register. */
9019 /* Compute value to compare against. */
9026 }
9027 }
9029 /* This code has problems. Basically, you can't know when
9030 seeing if we will eliminate BL, whether a particular giv
9031 of ARG will be reduced. If it isn't going to be reduced,
9032 we can't eliminate BL. We can try forcing it to be reduced,
9033 but that can generate poor code.
9035 The problem is that the benefit of reducing TV, below should
9036 be increased if BL can actually be eliminated, but this means
9037 we might have to do a topological sort of the order in which
9038 we try to process biv. It doesn't seem worthwhile to do
9039 this sort of thing now. */
9041 #if 0
9042 /* Otherwise the reg compared with had better be a biv. */
9047 /* Look for a pair of givs, one for each biv,
9048 with identical coefficients. */
9050 {
9062 {
9069 /* Replace biv with its giv's reduced reg. */
9071 /* Replace other operand with the other giv's
9072 reduced reg. */
9075 }
9076 }
9077 #endif
9078 }
9080 /* If we get here, the biv can't be eliminated. */
9084 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9085 biv is used in it, since it will be replaced. */
9093 }
9095 /* See if any subexpression fails elimination. */
9098 {
9100 {
9113 }
9114 }
9117 }
9118 \f
9119 /* Return nonzero if the last use of REG
9120 is in an insn following INSN in the same basic block. */
9122 static int
9124 {
9125 rtx n;
9129 {
9132 }
9134 }
9135 \f
9136 /* Called via `note_stores' to record the initial value of a biv. Here we
9137 just record the location of the set and process it later. */
9139 static void
9141 {
9152 /* If this is the first set found, record it. */
9154 {
9157 }
9158 }
9159 \f
9160 /* If any of the registers in X are "old" and currently have a last use earlier
9161 than INSN, update them to have a last use of INSN. Their actual last use
9162 will be the previous insn but it will not have a valid uid_luid so we can't
9163 use it. X must be a source expression only. */
9165 static void
9167 {
9168 /* Check for the case where INSN does not have a valid luid. In this case,
9169 there is no need to modify the regno_last_uid, as this can only happen
9170 when code is inserted after the loop_end to set a pseudo's final value,
9171 and hence this insn will never be the last use of x.
9172 ???? This comment is not correct. See for example loop_givs_reduce.
9173 This may insert an insn before another new insn. */
9177 {
9179 }
9180 else
9181 {
9185 {
9191 }
9192 }
9193 }
9194 \f
9195 /* Given an insn INSN and condition COND, return the condition in a
9196 canonical form to simplify testing by callers. Specifically:
9198 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9199 (2) Both operands will be machine operands; (cc0) will have been replaced.
9200 (3) If an operand is a constant, it will be the second operand.
9201 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9202 for GE, GEU, and LEU.
9204 If the condition cannot be understood, or is an inequality floating-point
9205 comparison which needs to be reversed, 0 will be returned.
9207 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9209 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9210 insn used in locating the condition was found. If a replacement test
9211 of the condition is desired, it should be placed in front of that
9212 insn and we will be sure that the inputs are still valid.
9214 If WANT_REG is nonzero, we wish the condition to be relative to that
9215 register, if possible. Therefore, do not canonicalize the condition
9216 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
9217 to be a compare to a CC mode register. */
9219 rtx
9222 {
9225 rtx set;
9226 rtx tem;
9244 /* If we are comparing a register with zero, see if the register is set
9245 in the previous insn to a COMPARE or a comparison operation. Perform
9246 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9247 in cse.c */
9252 {
9253 /* Set nonzero when we find something of interest. */
9256 #ifdef HAVE_cc0
9257 /* If comparison with cc0, import actual comparison from compare
9258 insn. */
9260 {
9271 }
9272 #endif
9274 /* If this is a COMPARE, pick up the two things being compared. */
9276 {
9280 }
9284 /* Go back to the previous insn. Stop if it is not an INSN. We also
9285 stop if it isn't a single set or if it has a REG_INC note because
9286 we don't want to bother dealing with it. */
9300 /* If this is setting OP0, get what it sets it to if it looks
9301 relevant. */
9303 {
9305 #ifdef FLOAT_STORE_FLAG_VALUE
9306 REAL_VALUE_TYPE fsfv;
9307 #endif
9309 /* ??? We may not combine comparisons done in a CCmode with
9310 comparisons not done in a CCmode. This is to aid targets
9311 like Alpha that have an IEEE compliant EQ instruction, and
9312 a non-IEEE compliant BEQ instruction. The use of CCmode is
9313 actually artificial, simply to prevent the combination, but
9314 should not affect other platforms.
9316 However, we must allow VOIDmode comparisons to match either
9317 CCmode or non-CCmode comparison, because some ports have
9318 modeless comparisons inside branch patterns.
9320 ??? This mode check should perhaps look more like the mode check
9321 in simplify_comparison in combine. */
9329 && (STORE_FLAG_VALUE
9332 #ifdef FLOAT_STORE_FLAG_VALUE
9337 #endif
9338 ))
9349 && (STORE_FLAG_VALUE
9352 #ifdef FLOAT_STORE_FLAG_VALUE
9357 #endif
9358 ))
9364 {
9367 }
9368 else
9370 }
9373 /* If this sets OP0, but not directly, we have to give up. */
9377 {
9381 {
9386 }
9391 }
9392 }
9394 /* If constant is first, put it last. */
9398 /* If OP0 is the result of a comparison, we weren't able to find what
9399 was really being compared, so fail. */
9404 /* Canonicalize any ordered comparison with integers involving equality
9405 if we can do computations in the relevant mode and we do not
9406 overflow. */
9412 {
9415 unsigned HOST_WIDE_INT max_val
9419 {
9425 /* When cross-compiling, const_val might be sign-extended from
9426 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9446 }
9447 }
9449 /* Never return CC0; return zero instead. */
9454 }
9456 /* Given a jump insn JUMP, return the condition that will cause it to branch
9457 to its JUMP_LABEL. If the condition cannot be understood, or is an
9458 inequality floating-point comparison which needs to be reversed, 0 will
9459 be returned.
9461 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9462 insn used in locating the condition was found. If a replacement test
9463 of the condition is desired, it should be placed in front of that
9464 insn and we will be sure that the inputs are still valid.
9466 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
9467 compare CC mode register. */
9469 rtx
9471 {
9472 rtx cond;
9474 rtx set;
9476 /* If this is not a standard conditional jump, we can't parse it. */
9484 /* If this branches to JUMP_LABEL when the condition is false, reverse
9485 the condition. */
9486 reverse
9491 allow_cc_mode);
9492 }
9494 /* Similar to above routine, except that we also put an invariant last
9495 unless both operands are invariants. */
9497 rtx
9499 {
9509 }
9511 /* Scan the function and determine whether it has indirect (computed) jumps.
9513 This is taken mostly from flow.c; similar code exists elsewhere
9514 in the compiler. It may be useful to put this into rtlanal.c. */
9515 static int
9517 {
9518 rtx insn;
9525 }
9527 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9528 documentation for LOOP_MEMS for the definition of `appropriate'.
9529 This function is called from prescan_loop via for_each_rtx. */
9531 static int
9533 {
9542 {
9547 /* We're not interested in MEMs that are only clobbered. */
9551 /* We're not interested in the MEM associated with a
9552 CONST_DOUBLE, so there's no need to traverse into this. */
9556 /* We're not interested in any MEMs that only appear in notes. */
9560 /* This is not a MEM. */
9562 }
9564 /* See if we've already seen this MEM. */
9567 {
9571 /* The modes of the two memory accesses are different. If
9572 this happens, something tricky is going on, and we just
9573 don't optimize accesses to this MEM. */
9577 }
9579 /* Resize the array, if necessary. */
9581 {
9584 else
9589 }
9591 /* Actually insert the MEM. */
9593 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9594 because we can't put it in a register. We still store it in the
9595 table, though, so that if we see the same address later, but in a
9596 non-BLK mode, we'll not think we can optimize it at that point. */
9602 }
9605 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9607 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9608 register that is modified by an insn between FROM and TO. If the
9609 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9610 more, stop incrementing it, to avoid overflow.
9612 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9613 register I is used, if it is only used once. Otherwise, it is set
9614 to 0 (for no uses) or const0_rtx for more than one use. This
9615 parameter may be zero, in which case this processing is not done.
9617 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9618 optimize register I. */
9620 static void
9622 {
9625 /* last_set[n] is nonzero iff reg n has been set in the current
9626 basic block. In that case, it is the insn that last set reg n. */
9628 rtx insn;
9634 /* Grow the regs array if not allocated or too small. */
9636 {
9641 /* Zero the new elements. */
9644 }
9646 /* Clear previously scanned fields but do not clear n_times_set. */
9648 {
9652 }
9656 /* Scan the loop, recording register usage. */
9659 {
9661 {
9662 /* Record registers that have exactly one use. */
9665 /* Include uses in REG_EQUAL notes. */
9673 {
9677 last_set);
9678 }
9679 }
9684 /* Invalidate all registers used for function argument passing.
9685 We check rtx_varies_p for the same reason as below, to allow
9686 optimizing PIC calculations. */
9688 {
9689 rtx link;
9691 link;
9693 {
9700 }
9701 }
9702 }
9704 /* Invalidate all hard registers clobbered by calls. With one exception:
9705 a call-clobbered PIC register is still function-invariant for our
9706 purposes, since we can hoist any PIC calculations out of the loop.
9707 Thus the call to rtx_varies_p. */
9712 {
9715 }
9717 #ifdef AVOID_CCMODE_COPIES
9718 /* Don't try to move insns which set CC registers if we should not
9719 create CCmode register copies. */
9723 #endif
9725 /* Set regs->array[I].n_times_set for the new registers. */
9730 }
9732 /* Returns the number of real INSNs in the LOOP. */
9734 static int
9736 {
9738 rtx insn;
9746 }
9748 /* Move MEMs into registers for the duration of the loop. */
9750 static void
9752 {
9759 rtx end_label;
9760 /* Nonzero if the next instruction may never be executed. */
9767 /* We cannot use next_label here because it skips over normal insns. */
9772 /* Check to see if it's possible that some instructions in the loop are
9773 never executed. Also check if there is a goto out of the loop other
9774 than right after the end of the loop. */
9778 {
9782 /* If we enter the loop in the middle, and scan
9783 around to the beginning, don't set maybe_never
9784 for that. This must be an unconditional jump,
9785 otherwise the code at the top of the loop might
9786 never be executed. Unconditional jumps are
9787 followed a by barrier then loop end. */
9792 {
9793 /* If this is a jump outside of the loop but not right
9794 after the end of the loop, we would have to emit new fixup
9795 sequences for each such label. */
9797 JUMP_INSN is executed, we must be conservative. */
9806 /* Something complicated. */
9808 else
9809 /* If there are any more instructions in the loop, they
9810 might not be reached. */
9812 }
9815 }
9817 /* Find start of the extended basic block that enters the loop. */
9821 ;
9826 /* Build table of mems that get set to constant values before the
9827 loop. */
9831 /* Actually move the MEMs. */
9833 {
9834 regset_head load_copies;
9835 regset_head store_copies;
9837 rtx reg;
9839 rtx mem_list_entry;
9843 /* There's no telling whether or not MEM is modified. */
9846 /* Go through the MEMs written to in the loop to see if this
9847 one is aliased by one of them. */
9850 {
9855 {
9856 /* MEM is indeed aliased by this store. */
9859 }
9861 }
9867 /* If this MEM is written to, we must be sure that there
9868 are no reads from another MEM that aliases this one. */
9870 {
9874 {
9878 VOIDmode,
9880 rtx_varies_p))
9881 {
9882 /* It's not safe to hoist loop_info->mems[i] out of
9883 the loop because writes to it might not be
9884 seen by reads from loop_info->mems[j]. */
9887 }
9888 }
9889 }
9892 /* We can't access the MEM outside the loop; it might
9893 cause a trap that wouldn't have happened otherwise. */
9897 /* We thought we were going to lift this MEM out of the
9898 loop, but later discovered that we could not. */
9904 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9905 order to keep scan_loop from moving stores to this MEM
9906 out of the loop just because this REG is neither a
9907 user-variable nor used in the loop test. */
9912 /* Now, replace all references to the MEM with the
9913 corresponding pseudos. */
9918 {
9920 {
9921 rtx set;
9925 /* See if this copies the mem into a register that isn't
9926 modified afterwards. We'll try to do copy propagation
9927 a little further on. */
9929 /* @@@ This test is _way_ too conservative. */
9930 && ! maybe_never
9938 /* See if this copies the mem from a register that isn't
9939 modified afterwards. We'll try to remove the
9940 redundant copy later on by doing a little register
9941 renaming and copy propagation. This will help
9942 to untangle things for the BIV detection code. */
9944 && ! maybe_never
9952 /* If this is a call which uses / clobbers this memory
9953 location, we must not change the interface here. */
9957 {
9961 }
9962 else
9963 /* Replace the memory reference with the shadow register. */
9966 }
9971 }
9976 /* We couldn't replace all occurrences of the MEM. */
9978 else
9979 {
9980 /* Load the memory immediately before LOOP->START, which is
9981 the NOTE_LOOP_BEG. */
9983 rtx set;
9989 {
9993 {
9997 /* Extending hard register lifetimes causes crash
9998 on SRC targets. Doing so on non-SRC is
9999 probably also not good idea, since we most
10000 probably have pseudoregister equivalence as
10001 well. */
10004 }
10005 /* Use the constant equivalence if that is cheap enough. */
10011 {
10014 }
10016 /* If best_equiv is nonzero, we know that MEM is set to a
10017 constant or register before the loop. We will use this
10018 knowledge to initialize the shadow register with that
10019 constant or reg rather than by loading from MEM. */
10022 }
10027 {
10030 {
10033 }
10034 }
10040 {
10042 {
10045 }
10047 /* Store the memory immediately after END, which is
10048 the NOTE_LOOP_END. */
10051 }
10054 {
10059 }
10061 /* Attempt a bit of copy propagation. This helps untangle the
10062 data flow, and enables {basic,general}_induction_var to find
10063 more bivs/givs. */
10064 EXECUTE_IF_SET_IN_REG_SET
10066 {
10068 });
10071 EXECUTE_IF_SET_IN_REG_SET
10073 {
10075 });
10077 }
10078 }
10080 /* Now, we need to replace all references to the previous exit
10081 label with the new one. */
10088 }
10090 /* For communication between note_reg_stored and its caller. */
10091 struct note_reg_stored_arg
10092 {
10094 rtx reg;
10095 };
10097 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10098 is equal to ARG. */
10099 static void
10101 {
10105 }
10107 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10108 There must be exactly one insn that sets this pseudo; it will be
10109 deleted if all replacements succeed and we can prove that the register
10110 is not used after the loop. */
10112 static void
10114 {
10115 /* This is the reg that we are copying from. */
10118 rtx insn;
10119 /* These help keep track of whether we replaced all uses of the reg. */
10126 {
10127 rtx set;
10129 /* Only substitute within one extended basic block from the initializing
10130 insn. */
10137 /* Is this the initializing insn? */
10142 {
10149 }
10151 /* Only substitute after seeing the initializing insn. */
10153 {
10160 /* Stop replacing when REPLACEMENT is modified. */
10165 {
10168 /* It is possible that we've turned previously valid REG_EQUAL to
10169 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10170 REPLACEMENT is modified, we get different meaning. */
10174 }
10175 }
10176 }
10180 {
10184 {
10185 rtx first;
10186 rtx retval_note;
10188 /* Assume we're just deleting INIT_INSN. */
10190 /* Look for REG_RETVAL note. If we're deleting the end of
10191 the libcall sequence, the whole sequence can go. */
10193 /* If we found a REG_RETVAL note, find the first instruction
10194 in the sequence. */
10198 /* Delete the instructions. */
10200 }
10203 }
10204 }
10206 /* Replace all the instructions from FIRST up to and including LAST
10207 with NOTE_INSN_DELETED notes. */
10209 static void
10211 {
10213 {
10219 /* If this was the LAST instructions we're supposed to delete,
10220 we're done. */
10225 }
10226 }
10228 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10229 loop LOOP if the order of the sets of these registers can be
10230 swapped. There must be exactly one insn within the loop that sets
10231 this pseudo followed immediately by a move insn that sets
10232 REPLACEMENT with REGNO. */
10233 static void
10236 {
10237 rtx insn;
10246 {
10247 /* Search for the insn that copies REGNO to NEW_REGNO? */
10255 }
10258 {
10259 rtx prev_insn;
10260 rtx prev_set;
10262 /* Some DEF-USE info would come in handy here to make this
10263 function more general. For now, just check the previous insn
10264 which is the most likely candidate for setting REGNO. */
10272 {
10273 /* We have:
10274 (set (reg regno) (expr))
10275 (set (reg new_regno) (reg regno))
10277 so try converting this to:
10278 (set (reg new_regno) (expr))
10279 (set (reg regno) (reg new_regno))
10281 The former construct is often generated when a global
10282 variable used for an induction variable is shadowed by a
10283 register (NEW_REGNO). The latter construct improves the
10284 chances of GIV replacement and BIV elimination. */
10294 {
10301 /* Update first use of REGNO. */
10305 /* Now perform copy propagation to hopefully
10306 remove all uses of REGNO within the loop. */
10308 }
10309 }
10310 }
10311 }
10313 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10315 static int
10317 {
10319 {
10323 }
10325 }
10327 /* Returns the first MEM found in NOTE by depth-first search. */
10329 static rtx
10331 {
10335 }
10337 /* Replace MEM with its associated pseudo register. This function is
10338 called from load_mems via for_each_rtx. DATA is actually a pointer
10339 to a structure describing the instruction currently being scanned
10340 and the MEM we are currently replacing. */
10342 static int
10344 {
10352 {
10357 /* We're not interested in the MEM associated with a
10358 CONST_DOUBLE, so there's no need to traverse into one. */
10362 /* This is not a MEM. */
10364 }
10367 /* This is not the MEM we are currently replacing. */
10370 /* Actually replace the MEM. */
10374 }
10376 static void
10378 {
10379 loop_replace_args args;
10387 /* If we hoist a mem write out of the loop, then REG_EQUAL
10388 notes referring to the mem are no longer valid. */
10390 {
10395 {
10399 {
10400 /* Remove the note. */
10403 }
10404 }
10405 }
10406 }
10408 /* Replace one register with another. Called through for_each_rtx; PX points
10409 to the rtx being scanned. DATA is actually a pointer to
10410 a structure of arguments. */
10412 static int
10414 {
10425 }
10427 static void
10429 {
10430 loop_replace_args args;
10437 }
10438 \f
10439 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10440 (ignored in the interim). */
10442 static rtx
10445 rtx pattern)
10446 {
10448 }
10451 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10452 in basic block WHERE_BB (ignored in the interim) within the loop
10453 otherwise hoist PATTERN into the loop pre-header. */
10455 rtx
10457 basic_block where_bb ATTRIBUTE_UNUSED,
10459 {
10463 }
10466 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10467 WHERE_BB (ignored in the interim) within the loop. */
10469 static rtx
10471 basic_block where_bb ATTRIBUTE_UNUSED,
10473 {
10475 }
10478 /* Hoist insn for PATTERN into the loop pre-header. */
10480 rtx
10482 {
10484 }
10487 /* Hoist call insn for PATTERN into the loop pre-header. */
10489 static rtx
10491 {
10493 }
10496 /* Sink insn for PATTERN after the loop end. */
10498 rtx
10500 {
10502 }
10504 /* bl->final_value can be either general_operand or PLUS of general_operand
10505 and constant. Emit sequence of instructions to load it into REG. */
10506 static rtx
10508 {
10509 rtx seq;
10517 }
10519 /* If the loop has multiple exits, emit insn for PATTERN before the
10520 loop to ensure that it will always be executed no matter how the
10521 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10522 since this is slightly more efficient. */
10524 static rtx
10526 {
10529 else
10531 }
10532 \f
10533 static void
10535 {
10543 iv_num++;
10548 {
10551 }
10552 }
10555 static void
10558 {
10560 rtx incr;
10571 {
10574 }
10576 {
10579 }
10583 {
10587 }
10590 {
10594 }
10596 /* List the increments. */
10598 {
10602 }
10604 /* List the givs. */
10606 {
10611 else
10614 }
10615 }
10618 static void
10620 {
10631 {
10635 }
10638 }
10641 static void
10643 {
10650 else
10666 {
10668 {
10680 }
10681 }
10692 {
10696 }
10699 }
10702 void
10704 {
10706 }
10709 void
10711 {
10713 }
10716 void
10718 {
10720 }
10723 void
10725 {
10727 }
10730 #define LOOP_BLOCK_NUM_1(INSN) \
10731 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10733 /* The notes do not have an assigned block, so look at the next insn. */
10734 #define LOOP_BLOCK_NUM(INSN) \
10735 ((INSN) ? (GET_CODE (INSN) == NOTE \
10736 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10737 : LOOP_BLOCK_NUM_1 (INSN)) \
10738 : -1)
10740 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10742 static void
10745 {
10746 rtx label;
10751 /* Print diagnostics to compare our concept of a loop with
10752 what the loop notes say. */
10767 {
10787 {
10790 {
10793 }
10794 }
10797 /* This can happen when a marked loop appears as two nested loops,
10798 say from while (a || b) {}. The inner loop won't match
10799 the loop markers but the outer one will. */
10802 }
10803 }
10805 /* Call this function from the debugger to dump LOOP. */
10807 void
10809 {
10811 }
10813 /* Call this function from the debugger to dump LOOPS. */
10815 void
10817 {
10819 }