1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2014 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; Return true if OP is a non-fp register_operand.
31 (define_predicate "register_and_not_any_fp_reg_operand"
32 (and (match_code "reg")
33 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
35 ;; True if the operand is a GENERAL class register.
36 (define_predicate "general_reg_operand"
37 (and (match_code "reg")
38 (match_test "GENERAL_REG_P (op)")))
40 ;; Return true if OP is a register operand other than an i387 fp register.
41 (define_predicate "register_and_not_fp_reg_operand"
42 (and (match_code "reg")
43 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
45 ;; True if the operand is an MMX register.
46 (define_predicate "mmx_reg_operand"
47 (and (match_code "reg")
48 (match_test "MMX_REGNO_P (REGNO (op))")))
50 ;; True if the operand is an SSE register.
51 (define_predicate "sse_reg_operand"
52 (and (match_code "reg")
53 (match_test "SSE_REGNO_P (REGNO (op))")))
55 ;; True if the operand is an AVX-512 new register.
56 (define_predicate "ext_sse_reg_operand"
57 (and (match_code "reg")
58 (match_test "EXT_REX_SSE_REGNO_P (REGNO (op))")))
60 ;; True if the operand is an AVX-512 mask register.
61 (define_predicate "mask_reg_operand"
62 (and (match_code "reg")
63 (match_test "MASK_REGNO_P (REGNO (op))")))
65 ;; True if the operand is a Q_REGS class register.
66 (define_predicate "q_regs_operand"
67 (match_operand 0 "register_operand")
69 if (GET_CODE (op) == SUBREG)
71 return ANY_QI_REG_P (op);
74 ;; Match an SI or HImode register for a zero_extract.
75 (define_special_predicate "ext_register_operand"
76 (match_operand 0 "register_operand")
78 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
79 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
81 if (GET_CODE (op) == SUBREG)
84 /* Be careful to accept only registers having upper parts. */
86 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
89 ;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
90 (define_predicate "nonimmediate_x64nomem_operand"
91 (if_then_else (match_test "TARGET_64BIT")
92 (match_operand 0 "register_operand")
93 (match_operand 0 "nonimmediate_operand")))
95 ;; Match general operands, but exclude memory operands on 64bit targets.
96 (define_predicate "general_x64nomem_operand"
97 (if_then_else (match_test "TARGET_64BIT")
98 (match_operand 0 "nonmemory_operand")
99 (match_operand 0 "general_operand")))
101 ;; Return true if op is the AX register.
102 (define_predicate "ax_reg_operand"
103 (and (match_code "reg")
104 (match_test "REGNO (op) == AX_REG")))
106 ;; Return true if op is the flags register.
107 (define_predicate "flags_reg_operand"
108 (and (match_code "reg")
109 (match_test "REGNO (op) == FLAGS_REG")))
111 ;; Return true if op is one of QImode registers: %[abcd][hl].
112 (define_predicate "QIreg_operand"
113 (match_test "QI_REG_P (op)"))
115 ;; Return true if op is a QImode register operand other than
117 (define_predicate "ext_QIreg_operand"
118 (and (match_code "reg")
119 (match_test "TARGET_64BIT")
120 (match_test "REGNO (op) > BX_REG")))
122 ;; Return true if VALUE is symbol reference
123 (define_predicate "symbol_operand"
124 (match_code "symbol_ref"))
126 ;; Return true if VALUE can be stored in a sign extended immediate field.
127 (define_predicate "x86_64_immediate_operand"
128 (match_code "const_int,symbol_ref,label_ref,const")
131 return immediate_operand (op, mode);
133 switch (GET_CODE (op))
136 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
137 to be at least 32 and this all acceptable constants are
138 represented as CONST_INT. */
139 if (HOST_BITS_PER_WIDE_INT == 32)
143 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
144 return trunc_int_for_mode (val, SImode) == val;
149 /* For certain code models, the symbolic references are known to fit.
150 in CM_SMALL_PIC model we know it fits if it is local to the shared
151 library. Don't count TLS SYMBOL_REFs here, since they should fit
152 only if inside of UNSPEC handled below. */
153 /* TLS symbols are not constant. */
154 if (SYMBOL_REF_TLS_MODEL (op))
156 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
157 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
160 /* For certain code models, the code is near as well. */
161 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
162 || ix86_cmodel == CM_KERNEL);
165 /* We also may accept the offsetted memory references in certain
167 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
168 switch (XINT (XEXP (op, 0), 1))
170 case UNSPEC_GOTPCREL:
172 case UNSPEC_GOTNTPOFF:
179 if (GET_CODE (XEXP (op, 0)) == PLUS)
181 rtx op1 = XEXP (XEXP (op, 0), 0);
182 rtx op2 = XEXP (XEXP (op, 0), 1);
183 HOST_WIDE_INT offset;
185 if (ix86_cmodel == CM_LARGE)
187 if (!CONST_INT_P (op2))
189 offset = trunc_int_for_mode (INTVAL (op2), DImode);
190 switch (GET_CODE (op1))
193 /* TLS symbols are not constant. */
194 if (SYMBOL_REF_TLS_MODEL (op1))
196 /* For CM_SMALL assume that latest object is 16MB before
197 end of 31bits boundary. We may also accept pretty
198 large negative constants knowing that all objects are
199 in the positive half of address space. */
200 if ((ix86_cmodel == CM_SMALL
201 || (ix86_cmodel == CM_MEDIUM
202 && !SYMBOL_REF_FAR_ADDR_P (op1)))
203 && offset < 16*1024*1024
204 && trunc_int_for_mode (offset, SImode) == offset)
206 /* For CM_KERNEL we know that all object resist in the
207 negative half of 32bits address space. We may not
208 accept negative offsets, since they may be just off
209 and we may accept pretty large positive ones. */
210 if (ix86_cmodel == CM_KERNEL
212 && trunc_int_for_mode (offset, SImode) == offset)
217 /* These conditions are similar to SYMBOL_REF ones, just the
218 constraints for code models differ. */
219 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
220 && offset < 16*1024*1024
221 && trunc_int_for_mode (offset, SImode) == offset)
223 if (ix86_cmodel == CM_KERNEL
225 && trunc_int_for_mode (offset, SImode) == offset)
230 switch (XINT (op1, 1))
234 if (trunc_int_for_mode (offset, SImode) == offset)
252 ;; Return true if VALUE can be stored in the zero extended immediate field.
253 (define_predicate "x86_64_zext_immediate_operand"
254 (match_code "const_double,const_int,symbol_ref,label_ref,const")
256 switch (GET_CODE (op))
259 if (HOST_BITS_PER_WIDE_INT == 32)
260 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
265 if (HOST_BITS_PER_WIDE_INT == 32)
266 return INTVAL (op) >= 0;
268 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
271 /* For certain code models, the symbolic references are known to fit. */
272 /* TLS symbols are not constant. */
273 if (SYMBOL_REF_TLS_MODEL (op))
275 return (ix86_cmodel == CM_SMALL
276 || (ix86_cmodel == CM_MEDIUM
277 && !SYMBOL_REF_FAR_ADDR_P (op)));
280 /* For certain code models, the code is near as well. */
281 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
284 /* We also may accept the offsetted memory references in certain
286 if (GET_CODE (XEXP (op, 0)) == PLUS)
288 rtx op1 = XEXP (XEXP (op, 0), 0);
289 rtx op2 = XEXP (XEXP (op, 0), 1);
291 if (ix86_cmodel == CM_LARGE)
293 switch (GET_CODE (op1))
296 /* TLS symbols are not constant. */
297 if (SYMBOL_REF_TLS_MODEL (op1))
299 /* For small code model we may accept pretty large positive
300 offsets, since one bit is available for free. Negative
301 offsets are limited by the size of NULL pointer area
302 specified by the ABI. */
303 if ((ix86_cmodel == CM_SMALL
304 || (ix86_cmodel == CM_MEDIUM
305 && !SYMBOL_REF_FAR_ADDR_P (op1)))
307 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
308 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
310 /* ??? For the kernel, we may accept adjustment of
311 -0x10000000, since we know that it will just convert
312 negative address space to positive, but perhaps this
313 is not worthwhile. */
317 /* These conditions are similar to SYMBOL_REF ones, just the
318 constraints for code models differ. */
319 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
321 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
322 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
338 ;; Return true if OP is general operand representable on x86_64.
339 (define_predicate "x86_64_general_operand"
340 (if_then_else (match_test "TARGET_64BIT")
341 (ior (match_operand 0 "nonimmediate_operand")
342 (match_operand 0 "x86_64_immediate_operand"))
343 (match_operand 0 "general_operand")))
345 ;; Return true if OP is non-VOIDmode general operand representable
346 ;; on x86_64. This predicate is used in sign-extending conversion
347 ;; operations that require non-VOIDmode immediate operands.
348 (define_predicate "x86_64_sext_operand"
349 (and (match_test "GET_MODE (op) != VOIDmode")
350 (match_operand 0 "x86_64_general_operand")))
352 ;; Return true if OP is non-VOIDmode general operand. This predicate
353 ;; is used in sign-extending conversion operations that require
354 ;; non-VOIDmode immediate operands.
355 (define_predicate "sext_operand"
356 (and (match_test "GET_MODE (op) != VOIDmode")
357 (match_operand 0 "general_operand")))
359 ;; Return true if OP is representable on x86_64 as zero-extended operand.
360 ;; This predicate is used in zero-extending conversion operations that
361 ;; require non-VOIDmode immediate operands.
362 (define_predicate "x86_64_zext_operand"
363 (if_then_else (match_test "TARGET_64BIT")
364 (ior (match_operand 0 "nonimmediate_operand")
365 (and (match_operand 0 "x86_64_zext_immediate_operand")
366 (match_test "GET_MODE (op) != VOIDmode")))
367 (match_operand 0 "nonimmediate_operand")))
369 ;; Return true if OP is general operand representable on x86_64
370 ;; as either sign extended or zero extended constant.
371 (define_predicate "x86_64_szext_general_operand"
372 (if_then_else (match_test "TARGET_64BIT")
373 (ior (match_operand 0 "nonimmediate_operand")
374 (match_operand 0 "x86_64_immediate_operand")
375 (match_operand 0 "x86_64_zext_immediate_operand"))
376 (match_operand 0 "general_operand")))
378 ;; Return true if OP is nonmemory operand representable on x86_64.
379 (define_predicate "x86_64_nonmemory_operand"
380 (if_then_else (match_test "TARGET_64BIT")
381 (ior (match_operand 0 "register_operand")
382 (match_operand 0 "x86_64_immediate_operand"))
383 (match_operand 0 "nonmemory_operand")))
385 ;; Return true if OP is nonmemory operand representable on x86_64.
386 (define_predicate "x86_64_szext_nonmemory_operand"
387 (if_then_else (match_test "TARGET_64BIT")
388 (ior (match_operand 0 "register_operand")
389 (match_operand 0 "x86_64_immediate_operand")
390 (match_operand 0 "x86_64_zext_immediate_operand"))
391 (match_operand 0 "nonmemory_operand")))
393 ;; Return true when operand is PIC expression that can be computed by lea
395 (define_predicate "pic_32bit_operand"
396 (match_code "const,symbol_ref,label_ref")
401 /* Rule out relocations that translate into 64bit constants. */
402 if (TARGET_64BIT && GET_CODE (op) == CONST)
405 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
407 if (GET_CODE (op) == UNSPEC
408 && (XINT (op, 1) == UNSPEC_GOTOFF
409 || XINT (op, 1) == UNSPEC_GOT))
413 return symbolic_operand (op, mode);
416 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
417 (define_predicate "x86_64_movabs_operand"
418 (and (match_operand 0 "nonmemory_operand")
419 (not (match_operand 0 "pic_32bit_operand"))))
421 ;; Return true if OP is either a symbol reference or a sum of a symbol
422 ;; reference and a constant.
423 (define_predicate "symbolic_operand"
424 (match_code "symbol_ref,label_ref,const")
426 switch (GET_CODE (op))
434 if (GET_CODE (op) == SYMBOL_REF
435 || GET_CODE (op) == LABEL_REF
436 || (GET_CODE (op) == UNSPEC
437 && (XINT (op, 1) == UNSPEC_GOT
438 || XINT (op, 1) == UNSPEC_GOTOFF
439 || XINT (op, 1) == UNSPEC_PCREL
440 || XINT (op, 1) == UNSPEC_GOTPCREL)))
442 if (GET_CODE (op) != PLUS
443 || !CONST_INT_P (XEXP (op, 1)))
447 if (GET_CODE (op) == SYMBOL_REF
448 || GET_CODE (op) == LABEL_REF)
450 /* Only @GOTOFF gets offsets. */
451 if (GET_CODE (op) != UNSPEC
452 || XINT (op, 1) != UNSPEC_GOTOFF)
455 op = XVECEXP (op, 0, 0);
456 if (GET_CODE (op) == SYMBOL_REF
457 || GET_CODE (op) == LABEL_REF)
466 ;; Return true if OP is a symbolic operand that resolves locally.
467 (define_predicate "local_symbolic_operand"
468 (match_code "const,label_ref,symbol_ref")
470 if (GET_CODE (op) == CONST
471 && GET_CODE (XEXP (op, 0)) == PLUS
472 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
473 op = XEXP (XEXP (op, 0), 0);
475 if (GET_CODE (op) == LABEL_REF)
478 if (GET_CODE (op) != SYMBOL_REF)
481 if (SYMBOL_REF_TLS_MODEL (op))
484 /* Dll-imported symbols are always external. */
485 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
487 if (SYMBOL_REF_LOCAL_P (op))
490 /* There is, however, a not insubstantial body of code in the rest of
491 the compiler that assumes it can just stick the results of
492 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
493 /* ??? This is a hack. Should update the body of the compiler to
494 always create a DECL an invoke targetm.encode_section_info. */
495 if (strncmp (XSTR (op, 0), internal_label_prefix,
496 internal_label_prefix_len) == 0)
502 ;; Test for a legitimate @GOTOFF operand.
504 ;; VxWorks does not impose a fixed gap between segments; the run-time
505 ;; gap can be different from the object-file gap. We therefore can't
506 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
507 ;; same segment as the GOT. Unfortunately, the flexibility of linker
508 ;; scripts means that we can't be sure of that in general, so assume
509 ;; that @GOTOFF is never valid on VxWorks.
510 (define_predicate "gotoff_operand"
511 (and (not (match_test "TARGET_VXWORKS_RTP"))
512 (match_operand 0 "local_symbolic_operand")))
514 ;; Test for various thread-local symbols.
515 (define_special_predicate "tls_symbolic_operand"
516 (and (match_code "symbol_ref")
517 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
519 (define_special_predicate "tls_modbase_operand"
520 (and (match_code "symbol_ref")
521 (match_test "op == ix86_tls_module_base ()")))
523 ;; Test for a pc-relative call operand
524 (define_predicate "constant_call_address_operand"
525 (match_code "symbol_ref")
527 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
529 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
534 ;; P6 processors will jump to the address after the decrement when %esp
535 ;; is used as a call operand, so they will execute return address as a code.
536 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
538 (define_predicate "call_register_no_elim_operand"
539 (match_operand 0 "register_operand")
541 if (GET_CODE (op) == SUBREG)
542 op = SUBREG_REG (op);
544 if (!TARGET_64BIT && op == stack_pointer_rtx)
547 return register_no_elim_operand (op, mode);
550 ;; True for any non-virtual or eliminable register. Used in places where
551 ;; instantiation of such a register may cause the pattern to not be recognized.
552 (define_predicate "register_no_elim_operand"
553 (match_operand 0 "register_operand")
555 if (GET_CODE (op) == SUBREG)
556 op = SUBREG_REG (op);
557 return !(op == arg_pointer_rtx
558 || op == frame_pointer_rtx
559 || IN_RANGE (REGNO (op),
560 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
563 ;; Similarly, but include the stack pointer. This is used to prevent esp
564 ;; from being used as an index reg.
565 (define_predicate "index_register_operand"
566 (match_operand 0 "register_operand")
568 if (GET_CODE (op) == SUBREG)
569 op = SUBREG_REG (op);
570 if (reload_in_progress || reload_completed)
571 return REG_OK_FOR_INDEX_STRICT_P (op);
573 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
576 ;; Return false if this is any eliminable register. Otherwise general_operand.
577 (define_predicate "general_no_elim_operand"
578 (if_then_else (match_code "reg,subreg")
579 (match_operand 0 "register_no_elim_operand")
580 (match_operand 0 "general_operand")))
582 ;; Return false if this is any eliminable register. Otherwise
583 ;; register_operand or a constant.
584 (define_predicate "nonmemory_no_elim_operand"
585 (ior (match_operand 0 "register_no_elim_operand")
586 (match_operand 0 "immediate_operand")))
588 ;; Test for a valid operand for indirect branch.
589 (define_predicate "indirect_branch_operand"
590 (ior (match_operand 0 "register_operand")
591 (and (not (match_test "TARGET_X32"))
592 (match_operand 0 "memory_operand"))))
594 ;; Test for a valid operand for a call instruction.
595 ;; Allow constant call address operands in Pmode only.
596 (define_special_predicate "call_insn_operand"
597 (ior (match_test "constant_call_address_operand
598 (op, mode == VOIDmode ? mode : Pmode)")
599 (match_operand 0 "call_register_no_elim_operand")
600 (and (not (match_test "TARGET_X32"))
601 (match_operand 0 "memory_operand"))))
603 ;; Similarly, but for tail calls, in which we cannot allow memory references.
604 (define_special_predicate "sibcall_insn_operand"
605 (ior (match_test "constant_call_address_operand
606 (op, mode == VOIDmode ? mode : Pmode)")
607 (match_operand 0 "register_no_elim_operand")))
609 ;; Return true if OP is a call from MS ABI to SYSV ABI function.
610 (define_predicate "call_rex64_ms_sysv_operation"
611 (match_code "parallel")
613 unsigned creg_size = ARRAY_SIZE (x86_64_ms_sysv_extra_clobbered_registers);
614 unsigned adop = GET_CODE (XVECEXP (op, 0, 0)) == SET
619 if ((unsigned) XVECLEN (op, 0) != creg_size + adop)
622 for (i = 0; i < creg_size; i++)
624 rtx elt = XVECEXP (op, 0, i+adop);
625 enum machine_mode mode;
628 if (GET_CODE (elt) != CLOBBER
629 || GET_CODE (SET_DEST (elt)) != REG)
632 regno = x86_64_ms_sysv_extra_clobbered_registers[i];
633 mode = SSE_REGNO_P (regno) ? TImode : DImode;
635 if (GET_MODE (SET_DEST (elt)) != mode
636 || REGNO (SET_DEST (elt)) != regno)
642 ;; Match exactly zero.
643 (define_predicate "const0_operand"
644 (match_code "const_int,const_double,const_vector")
646 if (mode == VOIDmode)
647 mode = GET_MODE (op);
648 return op == CONST0_RTX (mode);
651 ;; Match one or vector filled with ones.
652 (define_predicate "const1_operand"
653 (match_code "const_int,const_double,const_vector")
655 if (mode == VOIDmode)
656 mode = GET_MODE (op);
657 return op == CONST1_RTX (mode);
660 ;; Match exactly eight.
661 (define_predicate "const8_operand"
662 (and (match_code "const_int")
663 (match_test "INTVAL (op) == 8")))
665 ;; Match exactly 128.
666 (define_predicate "const128_operand"
667 (and (match_code "const_int")
668 (match_test "INTVAL (op) == 128")))
670 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
671 (define_predicate "const_32bit_mask"
672 (and (match_code "const_int")
673 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
674 == (HOST_WIDE_INT) 0xffffffff")))
676 ;; Match 2, 4, or 8. Used for leal multiplicands.
677 (define_predicate "const248_operand"
678 (match_code "const_int")
680 HOST_WIDE_INT i = INTVAL (op);
681 return i == 2 || i == 4 || i == 8;
684 ;; Match 2, 3, 6, or 7
685 (define_predicate "const2367_operand"
686 (match_code "const_int")
688 HOST_WIDE_INT i = INTVAL (op);
689 return i == 2 || i == 3 || i == 6 || i == 7;
692 ;; Match 1, 2, 4, or 8
693 (define_predicate "const1248_operand"
694 (match_code "const_int")
696 HOST_WIDE_INT i = INTVAL (op);
697 return i == 1 || i == 2 || i == 4 || i == 8;
700 ;; Match 3, 5, or 9. Used for leal multiplicands.
701 (define_predicate "const359_operand"
702 (match_code "const_int")
704 HOST_WIDE_INT i = INTVAL (op);
705 return i == 3 || i == 5 || i == 9;
708 ;; Match 4 or 8 to 11. Used for embeded rounding.
709 (define_predicate "const_4_or_8_to_11_operand"
710 (match_code "const_int")
712 HOST_WIDE_INT i = INTVAL (op);
713 return i == 4 || (i >= 8 && i <= 11);
716 ;; Match 4 or 8. Used for SAE.
717 (define_predicate "const48_operand"
718 (match_code "const_int")
720 HOST_WIDE_INT i = INTVAL (op);
721 return i == 4 || i == 8;
725 (define_predicate "const_0_to_1_operand"
726 (and (match_code "const_int")
727 (ior (match_test "op == const0_rtx")
728 (match_test "op == const1_rtx"))))
731 (define_predicate "const_0_to_3_operand"
732 (and (match_code "const_int")
733 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
736 (define_predicate "const_0_to_4_operand"
737 (and (match_code "const_int")
738 (match_test "IN_RANGE (INTVAL (op), 0, 4)")))
741 (define_predicate "const_0_to_5_operand"
742 (and (match_code "const_int")
743 (match_test "IN_RANGE (INTVAL (op), 0, 5)")))
746 (define_predicate "const_0_to_7_operand"
747 (and (match_code "const_int")
748 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
751 (define_predicate "const_0_to_15_operand"
752 (and (match_code "const_int")
753 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
756 (define_predicate "const_0_to_31_operand"
757 (and (match_code "const_int")
758 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
761 (define_predicate "const_0_to_63_operand"
762 (and (match_code "const_int")
763 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
766 (define_predicate "const_0_to_255_operand"
767 (and (match_code "const_int")
768 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
770 ;; Match (0 to 255) * 8
771 (define_predicate "const_0_to_255_mul_8_operand"
772 (match_code "const_int")
774 unsigned HOST_WIDE_INT val = INTVAL (op);
775 return val <= 255*8 && val % 8 == 0;
778 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
779 ;; for shift & compare patterns, as shifting by 0 does not change flags).
780 (define_predicate "const_1_to_31_operand"
781 (and (match_code "const_int")
782 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
784 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
785 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
786 (define_predicate "const_1_to_63_operand"
787 (and (match_code "const_int")
788 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
791 (define_predicate "const_2_to_3_operand"
792 (and (match_code "const_int")
793 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
796 (define_predicate "const_4_to_5_operand"
797 (and (match_code "const_int")
798 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
801 (define_predicate "const_4_to_7_operand"
802 (and (match_code "const_int")
803 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
806 (define_predicate "const_6_to_7_operand"
807 (and (match_code "const_int")
808 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
811 (define_predicate "const_8_to_9_operand"
812 (and (match_code "const_int")
813 (match_test "IN_RANGE (INTVAL (op), 8, 9)")))
816 (define_predicate "const_8_to_11_operand"
817 (and (match_code "const_int")
818 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
821 (define_predicate "const_8_to_15_operand"
822 (and (match_code "const_int")
823 (match_test "IN_RANGE (INTVAL (op), 8, 15)")))
826 (define_predicate "const_10_to_11_operand"
827 (and (match_code "const_int")
828 (match_test "IN_RANGE (INTVAL (op), 10, 11)")))
831 (define_predicate "const_12_to_13_operand"
832 (and (match_code "const_int")
833 (match_test "IN_RANGE (INTVAL (op), 12, 13)")))
836 (define_predicate "const_12_to_15_operand"
837 (and (match_code "const_int")
838 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
841 (define_predicate "const_14_to_15_operand"
842 (and (match_code "const_int")
843 (match_test "IN_RANGE (INTVAL (op), 14, 15)")))
846 (define_predicate "const_16_to_19_operand"
847 (and (match_code "const_int")
848 (match_test "IN_RANGE (INTVAL (op), 16, 19)")))
851 (define_predicate "const_16_to_31_operand"
852 (and (match_code "const_int")
853 (match_test "IN_RANGE (INTVAL (op), 16, 31)")))
856 (define_predicate "const_20_to_23_operand"
857 (and (match_code "const_int")
858 (match_test "IN_RANGE (INTVAL (op), 20, 23)")))
861 (define_predicate "const_24_to_27_operand"
862 (and (match_code "const_int")
863 (match_test "IN_RANGE (INTVAL (op), 24, 27)")))
866 (define_predicate "const_28_to_31_operand"
867 (and (match_code "const_int")
868 (match_test "IN_RANGE (INTVAL (op), 28, 31)")))
870 ;; True if this is a constant appropriate for an increment or decrement.
871 (define_predicate "incdec_operand"
872 (match_code "const_int")
874 /* On Pentium4, the inc and dec operations causes extra dependency on flag
875 registers, since carry flag is not set. */
876 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
878 return op == const1_rtx || op == constm1_rtx;
881 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
882 (define_predicate "reg_or_pm1_operand"
883 (ior (match_operand 0 "register_operand")
884 (and (match_code "const_int")
885 (ior (match_test "op == const1_rtx")
886 (match_test "op == constm1_rtx")))))
888 ;; True if OP is acceptable as operand of DImode shift expander.
889 (define_predicate "shiftdi_operand"
890 (if_then_else (match_test "TARGET_64BIT")
891 (match_operand 0 "nonimmediate_operand")
892 (match_operand 0 "register_operand")))
894 (define_predicate "ashldi_input_operand"
895 (if_then_else (match_test "TARGET_64BIT")
896 (match_operand 0 "nonimmediate_operand")
897 (match_operand 0 "reg_or_pm1_operand")))
899 ;; Return true if OP is a vector load from the constant pool with just
900 ;; the first element nonzero.
901 (define_predicate "zero_extended_scalar_load_operand"
905 op = maybe_get_pool_constant (op);
907 if (!(op && GET_CODE (op) == CONST_VECTOR))
910 n_elts = CONST_VECTOR_NUNITS (op);
912 for (n_elts--; n_elts > 0; n_elts--)
914 rtx elt = CONST_VECTOR_ELT (op, n_elts);
915 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
921 /* Return true if operand is a vector constant that is all ones. */
922 (define_predicate "vector_all_ones_operand"
923 (match_code "const_vector")
925 int nunits = GET_MODE_NUNITS (mode);
927 if (GET_CODE (op) == CONST_VECTOR
928 && CONST_VECTOR_NUNITS (op) == nunits)
931 for (i = 0; i < nunits; ++i)
933 rtx x = CONST_VECTOR_ELT (op, i);
934 if (x != constm1_rtx)
943 ; Return true when OP is operand acceptable for standard SSE move.
944 (define_predicate "vector_move_operand"
945 (ior (match_operand 0 "nonimmediate_operand")
946 (match_operand 0 "const0_operand")))
948 ;; Return true when OP is either nonimmediate operand, or any
950 (define_predicate "nonimmediate_or_const_vector_operand"
951 (ior (match_operand 0 "nonimmediate_operand")
952 (match_code "const_vector")))
954 ;; Return true when OP is nonimmediate or standard SSE constant.
955 (define_predicate "nonimmediate_or_sse_const_operand"
956 (match_operand 0 "general_operand")
958 if (nonimmediate_operand (op, mode))
960 if (standard_sse_constant_p (op) > 0)
965 ;; Return true if OP is a register or a zero.
966 (define_predicate "reg_or_0_operand"
967 (ior (match_operand 0 "register_operand")
968 (match_operand 0 "const0_operand")))
970 ;; Return true for RTX codes that force SImode address.
971 (define_predicate "SImode_address_operand"
972 (match_code "subreg,zero_extend,and"))
974 ;; Return true if op if a valid address for LEA, and does not contain
975 ;; a segment override. Defined as a special predicate to allow
976 ;; mode-less const_int operands pass to address_operand.
977 (define_special_predicate "address_no_seg_operand"
978 (match_operand 0 "address_operand")
980 struct ix86_address parts;
983 ok = ix86_decompose_address (op, &parts);
985 return parts.seg == SEG_DEFAULT;
988 ;; Return true if op if a valid base register, displacement or
989 ;; sum of base register and displacement for VSIB addressing.
990 (define_predicate "vsib_address_operand"
991 (match_operand 0 "address_operand")
993 struct ix86_address parts;
997 ok = ix86_decompose_address (op, &parts);
999 if (parts.index || parts.seg != SEG_DEFAULT)
1002 /* VSIB addressing doesn't support (%rip). */
1006 if (GET_CODE (disp) == CONST)
1008 disp = XEXP (disp, 0);
1009 if (GET_CODE (disp) == PLUS)
1010 disp = XEXP (disp, 0);
1011 if (GET_CODE (disp) == UNSPEC)
1012 switch (XINT (disp, 1))
1014 case UNSPEC_GOTPCREL:
1016 case UNSPEC_GOTNTPOFF:
1022 && (GET_CODE (disp) == SYMBOL_REF
1023 || GET_CODE (disp) == LABEL_REF))
1030 ;; Return true if op is valid MPX address operand without base
1031 (define_predicate "address_mpx_no_base_operand"
1032 (match_operand 0 "address_operand")
1034 struct ix86_address parts;
1037 ok = ix86_decompose_address (op, &parts);
1040 if (parts.index && parts.base)
1043 if (parts.seg != SEG_DEFAULT)
1046 /* Do not support (%rip). */
1047 if (parts.disp && flag_pic && TARGET_64BIT
1048 && SYMBOLIC_CONST (parts.disp))
1050 if (GET_CODE (parts.disp) != CONST
1051 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1052 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1053 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1054 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1055 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF))
1062 ;; Return true if op is valid MPX address operand without index
1063 (define_predicate "address_mpx_no_index_operand"
1064 (match_operand 0 "address_operand")
1066 struct ix86_address parts;
1069 ok = ix86_decompose_address (op, &parts);
1075 if (parts.seg != SEG_DEFAULT)
1078 /* Do not support (%rip). */
1079 if (parts.disp && flag_pic && TARGET_64BIT
1080 && SYMBOLIC_CONST (parts.disp)
1081 && (GET_CODE (parts.disp) != CONST
1082 || GET_CODE (XEXP (parts.disp, 0)) != PLUS
1083 || GET_CODE (XEXP (XEXP (parts.disp, 0), 0)) != UNSPEC
1084 || !CONST_INT_P (XEXP (XEXP (parts.disp, 0), 1))
1085 || (XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_DTPOFF
1086 && XINT (XEXP (XEXP (parts.disp, 0), 0), 1) != UNSPEC_NTPOFF)))
1092 (define_predicate "vsib_mem_operator"
1095 (define_predicate "bnd_mem_operator"
1098 ;; Return true if the rtx is known to be at least 32 bits aligned.
1099 (define_predicate "aligned_operand"
1100 (match_operand 0 "general_operand")
1102 struct ix86_address parts;
1105 /* Registers and immediate operands are always "aligned". */
1109 /* All patterns using aligned_operand on memory operands ends up
1110 in promoting memory operand to 64bit and thus causing memory mismatch. */
1111 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
1114 /* Don't even try to do any aligned optimizations with volatiles. */
1115 if (MEM_VOLATILE_P (op))
1118 if (MEM_ALIGN (op) >= 32)
1123 /* Pushes and pops are only valid on the stack pointer. */
1124 if (GET_CODE (op) == PRE_DEC
1125 || GET_CODE (op) == POST_INC)
1128 /* Decode the address. */
1129 ok = ix86_decompose_address (op, &parts);
1132 if (parts.base && GET_CODE (parts.base) == SUBREG)
1133 parts.base = SUBREG_REG (parts.base);
1134 if (parts.index && GET_CODE (parts.index) == SUBREG)
1135 parts.index = SUBREG_REG (parts.index);
1137 /* Look for some component that isn't known to be aligned. */
1140 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
1145 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
1150 if (!CONST_INT_P (parts.disp)
1151 || (INTVAL (parts.disp) & 3))
1155 /* Didn't find one -- this must be an aligned address. */
1159 ;; Return true if OP is memory operand with a displacement.
1160 (define_predicate "memory_displacement_operand"
1161 (match_operand 0 "memory_operand")
1163 struct ix86_address parts;
1166 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1168 return parts.disp != NULL_RTX;
1171 ;; Return true if OP is memory operand with a displacement only.
1172 (define_predicate "memory_displacement_only_operand"
1173 (match_operand 0 "memory_operand")
1175 struct ix86_address parts;
1181 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1184 if (parts.base || parts.index)
1187 return parts.disp != NULL_RTX;
1190 ;; Return true if OP is memory operand which will need zero or
1191 ;; one register at most, not counting stack pointer or frame pointer.
1192 (define_predicate "cmpxchg8b_pic_memory_operand"
1193 (match_operand 0 "memory_operand")
1195 struct ix86_address parts;
1198 if (TARGET_64BIT || !flag_pic)
1201 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1204 if (parts.base && GET_CODE (parts.base) == SUBREG)
1205 parts.base = SUBREG_REG (parts.base);
1206 if (parts.index && GET_CODE (parts.index) == SUBREG)
1207 parts.index = SUBREG_REG (parts.index);
1209 if (parts.base == NULL_RTX
1210 || parts.base == arg_pointer_rtx
1211 || parts.base == frame_pointer_rtx
1212 || parts.base == hard_frame_pointer_rtx
1213 || parts.base == stack_pointer_rtx)
1216 if (parts.index == NULL_RTX
1217 || parts.index == arg_pointer_rtx
1218 || parts.index == frame_pointer_rtx
1219 || parts.index == hard_frame_pointer_rtx
1220 || parts.index == stack_pointer_rtx)
1227 ;; Return true if OP is memory operand that cannot be represented
1228 ;; by the modRM array.
1229 (define_predicate "long_memory_operand"
1230 (and (match_operand 0 "memory_operand")
1231 (match_test "memory_address_length (op, false)")))
1233 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1234 (define_predicate "fcmov_comparison_operator"
1235 (match_operand 0 "comparison_operator")
1237 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1238 enum rtx_code code = GET_CODE (op);
1240 if (inmode == CCFPmode || inmode == CCFPUmode)
1242 if (!ix86_trivial_fp_comparison_operator (op, mode))
1244 code = ix86_fp_compare_code_to_integer (code);
1246 /* i387 supports just limited amount of conditional codes. */
1249 case LTU: case GTU: case LEU: case GEU:
1250 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1251 || inmode == CCCmode)
1254 case ORDERED: case UNORDERED:
1262 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1263 ;; The first set are supported directly; the second set can't be done with
1264 ;; full IEEE support, i.e. NaNs.
1266 (define_predicate "sse_comparison_operator"
1267 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1268 (and (match_test "TARGET_AVX")
1269 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1271 (define_predicate "ix86_comparison_int_operator"
1272 (match_code "ne,eq,ge,gt,le,lt"))
1274 (define_predicate "ix86_comparison_uns_operator"
1275 (match_code "ne,eq,geu,gtu,leu,ltu"))
1277 (define_predicate "bt_comparison_operator"
1278 (match_code "ne,eq"))
1280 ;; Return true if OP is a valid comparison operator in valid mode.
1281 (define_predicate "ix86_comparison_operator"
1282 (match_operand 0 "comparison_operator")
1284 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1285 enum rtx_code code = GET_CODE (op);
1287 if (inmode == CCFPmode || inmode == CCFPUmode)
1288 return ix86_trivial_fp_comparison_operator (op, mode);
1295 if (inmode == CCmode || inmode == CCGCmode
1296 || inmode == CCGOCmode || inmode == CCNOmode)
1299 case LTU: case GTU: case LEU: case GEU:
1300 if (inmode == CCmode || inmode == CCCmode)
1303 case ORDERED: case UNORDERED:
1304 if (inmode == CCmode)
1308 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1316 ;; Return true if OP is a valid comparison operator
1317 ;; testing carry flag to be set.
1318 (define_predicate "ix86_carry_flag_operator"
1319 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1321 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1322 enum rtx_code code = GET_CODE (op);
1324 if (inmode == CCFPmode || inmode == CCFPUmode)
1326 if (!ix86_trivial_fp_comparison_operator (op, mode))
1328 code = ix86_fp_compare_code_to_integer (code);
1330 else if (inmode == CCCmode)
1331 return code == LTU || code == GTU;
1332 else if (inmode != CCmode)
1338 ;; Return true if this comparison only requires testing one flag bit.
1339 (define_predicate "ix86_trivial_fp_comparison_operator"
1340 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1342 ;; Return true if we know how to do this comparison. Others require
1343 ;; testing more than one flag bit, and we let the generic middle-end
1345 (define_predicate "ix86_fp_comparison_operator"
1346 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1347 == IX86_FPCMP_ARITH")
1348 (match_operand 0 "comparison_operator")
1349 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1351 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1352 (define_predicate "ix86_swapped_fp_comparison_operator"
1353 (match_operand 0 "comparison_operator")
1355 enum rtx_code code = GET_CODE (op);
1358 PUT_CODE (op, swap_condition (code));
1359 ret = ix86_fp_comparison_operator (op, mode);
1360 PUT_CODE (op, code);
1364 ;; Nearly general operand, but accept any const_double, since we wish
1365 ;; to be able to drop them into memory rather than have them get pulled
1367 (define_predicate "cmp_fp_expander_operand"
1368 (ior (match_code "const_double")
1369 (match_operand 0 "general_operand")))
1371 ;; Return true if this is a valid binary floating-point operation.
1372 (define_predicate "binary_fp_operator"
1373 (match_code "plus,minus,mult,div"))
1375 ;; Return true if this is a multiply operation.
1376 (define_predicate "mult_operator"
1377 (match_code "mult"))
1379 ;; Return true if this is a division operation.
1380 (define_predicate "div_operator"
1383 ;; Return true if this is a plus, minus, and, ior or xor operation.
1384 (define_predicate "plusminuslogic_operator"
1385 (match_code "plus,minus,and,ior,xor"))
1387 ;; Return true if this is a float extend operation.
1388 (define_predicate "float_operator"
1389 (match_code "float"))
1391 ;; Return true for ARITHMETIC_P.
1392 (define_predicate "arith_or_logical_operator"
1393 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1394 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1396 ;; Return true for COMMUTATIVE_P.
1397 (define_predicate "commutative_operator"
1398 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1400 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1401 (define_predicate "promotable_binary_operator"
1402 (ior (match_code "plus,minus,and,ior,xor,ashift")
1403 (and (match_code "mult")
1404 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1406 (define_predicate "compare_operator"
1407 (match_code "compare"))
1409 (define_predicate "absneg_operator"
1410 (match_code "abs,neg"))
1412 ;; Return true if OP is misaligned memory operand
1413 (define_predicate "misaligned_operand"
1414 (and (match_code "mem")
1415 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1417 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1418 (define_predicate "emms_operation"
1419 (match_code "parallel")
1423 if (XVECLEN (op, 0) != 17)
1426 for (i = 0; i < 8; i++)
1428 rtx elt = XVECEXP (op, 0, i+1);
1430 if (GET_CODE (elt) != CLOBBER
1431 || GET_CODE (SET_DEST (elt)) != REG
1432 || GET_MODE (SET_DEST (elt)) != XFmode
1433 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1436 elt = XVECEXP (op, 0, i+9);
1438 if (GET_CODE (elt) != CLOBBER
1439 || GET_CODE (SET_DEST (elt)) != REG
1440 || GET_MODE (SET_DEST (elt)) != DImode
1441 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1447 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1448 (define_predicate "vzeroall_operation"
1449 (match_code "parallel")
1451 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1453 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1456 for (i = 0; i < nregs; i++)
1458 rtx elt = XVECEXP (op, 0, i+1);
1460 if (GET_CODE (elt) != SET
1461 || GET_CODE (SET_DEST (elt)) != REG
1462 || GET_MODE (SET_DEST (elt)) != V8SImode
1463 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1464 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1470 ;; return true if OP is a vzeroupper operation.
1471 (define_predicate "vzeroupper_operation"
1472 (and (match_code "unspec_volatile")
1473 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1475 ;; Return true if OP is a parallel for a vbroadcast permute.
1477 (define_predicate "avx_vbroadcast_operand"
1478 (and (match_code "parallel")
1479 (match_code "const_int" "a"))
1481 rtx elt = XVECEXP (op, 0, 0);
1482 int i, nelt = XVECLEN (op, 0);
1484 /* Don't bother checking there are the right number of operands,
1485 merely that they're all identical. */
1486 for (i = 1; i < nelt; ++i)
1487 if (XVECEXP (op, 0, i) != elt)
1492 ;; Return true if OP is a proper third operand to vpblendw256.
1493 (define_predicate "avx2_pblendw_operand"
1494 (match_code "const_int")
1496 HOST_WIDE_INT val = INTVAL (op);
1497 HOST_WIDE_INT low = val & 0xff;
1498 return val == ((low << 8) | low);
1501 ;; Return true if OP is nonimmediate_operand or CONST_VECTOR.
1502 (define_predicate "general_vector_operand"
1503 (ior (match_operand 0 "nonimmediate_operand")
1504 (match_code "const_vector")))
1506 ;; Return true if OP is either -1 constant or stored in register.
1507 (define_predicate "register_or_constm1_operand"
1508 (ior (match_operand 0 "register_operand")
1509 (and (match_code "const_int")
1510 (match_test "op == constm1_rtx"))))