| blob | c520f26c89146c81e1e2ad0d05b798b9682e21ac |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
92 #ifndef CHECK_STACK_LIMIT
93 #define CHECK_STACK_LIMIT (-1)
94 #endif
96 /* Return index of given mode in mult and division cost tables. */
97 #define MODE_INDEX(mode) \
98 ((mode) == QImode ? 0 \
99 : (mode) == HImode ? 1 \
100 : (mode) == SImode ? 2 \
101 : (mode) == DImode ? 3 \
102 : 4)
104 /* Processor costs (relative to an add) */
105 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
106 #define COSTS_N_BYTES(N) ((N) * 2)
108 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
117 const
140 in QImode, HImode and SImode.
141 Relative to reg-reg move (2). */
145 in SFmode, DFmode and XFmode */
147 in SFmode, DFmode and XFmode */
150 in SImode and DImode */
152 in SImode and DImode */
155 in SImode, DImode and TImode */
157 in SImode, DImode and TImode */
170 ix86_size_memcpy,
171 ix86_size_memset,
183 };
185 /* Processor costs (relative to an add) */
188 DUMMY_STRINGOP_ALGS};
191 DUMMY_STRINGOP_ALGS};
193 static const
216 in QImode, HImode and SImode.
217 Relative to reg-reg move (2). */
221 in SFmode, DFmode and XFmode */
223 in SFmode, DFmode and XFmode */
226 in SImode and DImode */
228 in SImode and DImode */
231 in SImode, DImode and TImode */
233 in SImode, DImode and TImode */
246 i386_memcpy,
247 i386_memset,
259 };
263 DUMMY_STRINGOP_ALGS};
266 DUMMY_STRINGOP_ALGS};
268 static const
291 in QImode, HImode and SImode.
292 Relative to reg-reg move (2). */
296 in SFmode, DFmode and XFmode */
298 in SFmode, DFmode and XFmode */
301 in SImode and DImode */
303 in SImode and DImode */
306 in SImode, DImode and TImode */
308 in SImode, DImode and TImode */
311 shared for code and data, so 4kB is
312 not really precise. */
323 i486_memcpy,
324 i486_memset,
336 };
340 DUMMY_STRINGOP_ALGS};
343 DUMMY_STRINGOP_ALGS};
345 static const
368 in QImode, HImode and SImode.
369 Relative to reg-reg move (2). */
373 in SFmode, DFmode and XFmode */
375 in SFmode, DFmode and XFmode */
378 in SImode and DImode */
380 in SImode and DImode */
383 in SImode, DImode and TImode */
385 in SImode, DImode and TImode */
398 pentium_memcpy,
399 pentium_memset,
411 };
413 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
414 (we ensure the alignment). For small blocks inline loop is still a
415 noticeable win, for bigger blocks either rep movsl or rep movsb is
416 way to go. Rep movsb has apparently more expensive startup time in CPU,
417 but after 4K the difference is down in the noise. */
422 DUMMY_STRINGOP_ALGS};
427 DUMMY_STRINGOP_ALGS};
428 static const
451 in QImode, HImode and SImode.
452 Relative to reg-reg move (2). */
456 in SFmode, DFmode and XFmode */
458 in SFmode, DFmode and XFmode */
461 in SImode and DImode */
463 in SImode and DImode */
466 in SImode, DImode and TImode */
468 in SImode, DImode and TImode */
481 pentiumpro_memcpy,
482 pentiumpro_memset,
494 };
498 DUMMY_STRINGOP_ALGS};
501 DUMMY_STRINGOP_ALGS};
502 static const
525 in QImode, HImode and SImode.
526 Relative to reg-reg move (2). */
530 in SFmode, DFmode and XFmode */
532 in SFmode, DFmode and XFmode */
536 in SImode and DImode */
538 in SImode and DImode */
541 in SImode, DImode and TImode */
543 in SImode, DImode and TImode */
556 geode_memcpy,
557 geode_memset,
569 };
573 DUMMY_STRINGOP_ALGS};
576 DUMMY_STRINGOP_ALGS};
577 static const
600 in QImode, HImode and SImode.
601 Relative to reg-reg move (2). */
605 in SFmode, DFmode and XFmode */
607 in SFmode, DFmode and XFmode */
610 in SImode and DImode */
612 in SImode and DImode */
615 in SImode, DImode and TImode */
617 in SImode, DImode and TImode */
621 have integrated l2 cache, but
622 optimizing for k6 is not important
623 enough to worry about that. */
633 k6_memcpy,
634 k6_memset,
646 };
648 /* For some reason, Athlon deals better with REP prefix (relative to loops)
649 compared to K8. Alignment becomes important after 8 bytes for memcpy and
650 128 bytes for memset. */
653 DUMMY_STRINGOP_ALGS};
656 DUMMY_STRINGOP_ALGS};
657 static const
680 in QImode, HImode and SImode.
681 Relative to reg-reg move (2). */
685 in SFmode, DFmode and XFmode */
687 in SFmode, DFmode and XFmode */
690 in SImode and DImode */
692 in SImode and DImode */
695 in SImode, DImode and TImode */
697 in SImode, DImode and TImode */
710 athlon_memcpy,
711 athlon_memset,
723 };
725 /* K8 has optimized REP instruction for medium sized blocks, but for very
726 small blocks it is better to use loop. For large blocks, libcall can
727 do nontemporary accesses and beat inline considerably. */
738 static const
761 in QImode, HImode and SImode.
762 Relative to reg-reg move (2). */
766 in SFmode, DFmode and XFmode */
768 in SFmode, DFmode and XFmode */
771 in SImode and DImode */
773 in SImode and DImode */
776 in SImode, DImode and TImode */
778 in SImode, DImode and TImode */
783 /* New AMD processors never drop prefetches; if they cannot be performed
784 immediately, they are queued. We set number of simultaneous prefetches
785 to a large constant to reflect this (it probably is not a good idea not
786 to limit number of prefetches at all, as their execution also takes some
787 time). */
797 k8_memcpy,
798 k8_memset,
810 };
812 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
813 very small blocks it is better to use loop. For large blocks, libcall can
814 do nontemporary accesses and beat inline considerably. */
847 in QImode, HImode and SImode.
848 Relative to reg-reg move (2). */
852 in SFmode, DFmode and XFmode */
854 in SFmode, DFmode and XFmode */
857 in SImode and DImode */
859 in SImode and DImode */
862 in SImode, DImode and TImode */
864 in SImode, DImode and TImode */
866 /* On K8:
867 MOVD reg64, xmmreg Double FSTORE 4
868 MOVD reg32, xmmreg Double FSTORE 4
869 On AMDFAM10:
870 MOVD reg64, xmmreg Double FADD 3
871 1/1 1/1
872 MOVD reg32, xmmreg Double FADD 3
873 1/1 1/1 */
877 /* New AMD processors never drop prefetches; if they cannot be performed
878 immediately, they are queued. We set number of simultaneous prefetches
879 to a large constant to reflect this (it probably is not a good idea not
880 to limit number of prefetches at all, as their execution also takes some
881 time). */
891 amdfam10_memcpy,
892 amdfam10_memset,
904 };
906 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
907 very small blocks it is better to use loop. For large blocks, libcall
908 can do nontemporary accesses and beat inline considerably. */
942 in QImode, HImode and SImode.
943 Relative to reg-reg move (2). */
947 in SFmode, DFmode and XFmode */
949 in SFmode, DFmode and XFmode */
952 in SImode and DImode */
954 in SImode and DImode */
957 in SImode, DImode and TImode */
959 in SImode, DImode and TImode */
961 /* On K8:
962 MOVD reg64, xmmreg Double FSTORE 4
963 MOVD reg32, xmmreg Double FSTORE 4
964 On AMDFAM10:
965 MOVD reg64, xmmreg Double FADD 3
966 1/1 1/1
967 MOVD reg32, xmmreg Double FADD 3
968 1/1 1/1 */
972 /* New AMD processors never drop prefetches; if they cannot be performed
973 immediately, they are queued. We set number of simultaneous prefetches
974 to a large constant to reflect this (it probably is not a good idea not
975 to limit number of prefetches at all, as their execution also takes some
976 time). */
986 bdver1_memcpy,
987 bdver1_memset,
999 };
1001 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1002 very small blocks it is better to use loop. For large blocks, libcall
1003 can do nontemporary accesses and beat inline considerably. */
1038 in QImode, HImode and SImode.
1039 Relative to reg-reg move (2). */
1043 in SFmode, DFmode and XFmode */
1045 in SFmode, DFmode and XFmode */
1048 in SImode and DImode */
1050 in SImode and DImode */
1053 in SImode, DImode and TImode */
1055 in SImode, DImode and TImode */
1057 /* On K8:
1058 MOVD reg64, xmmreg Double FSTORE 4
1059 MOVD reg32, xmmreg Double FSTORE 4
1060 On AMDFAM10:
1061 MOVD reg64, xmmreg Double FADD 3
1062 1/1 1/1
1063 MOVD reg32, xmmreg Double FADD 3
1064 1/1 1/1 */
1068 /* New AMD processors never drop prefetches; if they cannot be performed
1069 immediately, they are queued. We set number of simultaneous prefetches
1070 to a large constant to reflect this (it probably is not a good idea not
1071 to limit number of prefetches at all, as their execution also takes some
1072 time). */
1082 bdver2_memcpy,
1083 bdver2_memset,
1095 };
1098 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1099 very small blocks it is better to use loop. For large blocks, libcall
1100 can do nontemporary accesses and beat inline considerably. */
1133 in QImode, HImode and SImode.
1134 Relative to reg-reg move (2). */
1138 in SFmode, DFmode and XFmode */
1140 in SFmode, DFmode and XFmode */
1143 in SImode and DImode */
1145 in SImode and DImode */
1148 in SImode, DImode and TImode */
1150 in SImode, DImode and TImode */
1155 /* New AMD processors never drop prefetches; if they cannot be performed
1156 immediately, they are queued. We set number of simultaneous prefetches
1157 to a large constant to reflect this (it probably is not a good idea not
1158 to limit number of prefetches at all, as their execution also takes some
1159 time). */
1169 bdver3_memcpy,
1170 bdver3_memset,
1182 };
1184 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1185 very small blocks it is better to use loop. For large blocks, libcall
1186 can do nontemporary accesses and beat inline considerably. */
1219 in QImode, HImode and SImode.
1220 Relative to reg-reg move (2). */
1224 in SFmode, DFmode and XFmode */
1226 in SFmode, DFmode and XFmode */
1229 in SImode and DImode */
1231 in SImode and DImode */
1234 in SImode, DImode and TImode */
1236 in SImode, DImode and TImode */
1241 /* New AMD processors never drop prefetches; if they cannot be performed
1242 immediately, they are queued. We set number of simultaneous prefetches
1243 to a large constant to reflect this (it probably is not a good idea not
1244 to limit number of prefetches at all, as their execution also takes some
1245 time). */
1255 bdver4_memcpy,
1256 bdver4_memset,
1268 };
1270 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1271 very small blocks it is better to use loop. For large blocks, libcall can
1272 do nontemporary accesses and beat inline considerably. */
1305 in QImode, HImode and SImode.
1306 Relative to reg-reg move (2). */
1310 in SFmode, DFmode and XFmode */
1312 in SFmode, DFmode and XFmode */
1315 in SImode and DImode */
1317 in SImode and DImode */
1320 in SImode, DImode and TImode */
1322 in SImode, DImode and TImode */
1324 /* On K8:
1325 MOVD reg64, xmmreg Double FSTORE 4
1326 MOVD reg32, xmmreg Double FSTORE 4
1327 On AMDFAM10:
1328 MOVD reg64, xmmreg Double FADD 3
1329 1/1 1/1
1330 MOVD reg32, xmmreg Double FADD 3
1331 1/1 1/1 */
1344 btver1_memcpy,
1345 btver1_memset,
1357 };
1391 in QImode, HImode and SImode.
1392 Relative to reg-reg move (2). */
1396 in SFmode, DFmode and XFmode */
1398 in SFmode, DFmode and XFmode */
1401 in SImode and DImode */
1403 in SImode and DImode */
1406 in SImode, DImode and TImode */
1408 in SImode, DImode and TImode */
1410 /* On K8:
1411 MOVD reg64, xmmreg Double FSTORE 4
1412 MOVD reg32, xmmreg Double FSTORE 4
1413 On AMDFAM10:
1414 MOVD reg64, xmmreg Double FADD 3
1415 1/1 1/1
1416 MOVD reg32, xmmreg Double FADD 3
1417 1/1 1/1 */
1429 btver2_memcpy,
1430 btver2_memset,
1442 };
1446 DUMMY_STRINGOP_ALGS};
1450 DUMMY_STRINGOP_ALGS};
1452 static const
1475 in QImode, HImode and SImode.
1476 Relative to reg-reg move (2). */
1480 in SFmode, DFmode and XFmode */
1482 in SFmode, DFmode and XFmode */
1485 in SImode and DImode */
1487 in SImode and DImode */
1490 in SImode, DImode and TImode */
1492 in SImode, DImode and TImode */
1505 pentium4_memcpy,
1506 pentium4_memset,
1518 };
1531 static const
1554 in QImode, HImode and SImode.
1555 Relative to reg-reg move (2). */
1559 in SFmode, DFmode and XFmode */
1561 in SFmode, DFmode and XFmode */
1564 in SImode and DImode */
1566 in SImode and DImode */
1569 in SImode, DImode and TImode */
1571 in SImode, DImode and TImode */
1584 nocona_memcpy,
1585 nocona_memset,
1597 };
1608 static const
1631 in QImode, HImode and SImode.
1632 Relative to reg-reg move (2). */
1636 in SFmode, DFmode and XFmode */
1638 in SFmode, DFmode and XFmode */
1641 in SImode and DImode */
1643 in SImode and DImode */
1646 in SImode, DImode and TImode */
1648 in SImode, DImode and TImode */
1661 atom_memcpy,
1662 atom_memset,
1674 };
1685 static const
1708 in QImode, HImode and SImode.
1709 Relative to reg-reg move (2). */
1713 in SFmode, DFmode and XFmode */
1715 in SFmode, DFmode and XFmode */
1718 in SImode and DImode */
1720 in SImode and DImode */
1723 in SImode, DImode and TImode */
1725 in SImode, DImode and TImode */
1738 slm_memcpy,
1739 slm_memset,
1751 };
1762 static const
1785 in QImode, HImode and SImode.
1786 Relative to reg-reg move (2). */
1790 in SFmode, DFmode and XFmode */
1792 in SFmode, DFmode and XFmode */
1795 in SImode and DImode */
1797 in SImode and DImode */
1800 in SImode, DImode and TImode */
1802 in SImode, DImode and TImode */
1815 intel_memcpy,
1816 intel_memset,
1828 };
1830 /* Generic should produce code tuned for Core-i7 (and newer chips)
1831 and btver1 (and newer chips). */
1843 static const
1846 /* On all chips taken into consideration lea is 2 cycles and more. With
1847 this cost however our current implementation of synth_mult results in
1848 use of unnecessary temporary registers causing regression on several
1849 SPECfp benchmarks. */
1870 in QImode, HImode and SImode.
1871 Relative to reg-reg move (2). */
1875 in SFmode, DFmode and XFmode */
1877 in SFmode, DFmode and XFmode */
1880 in SImode and DImode */
1882 in SImode and DImode */
1885 in SImode, DImode and TImode */
1887 in SImode, DImode and TImode */
1893 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1894 value is increased to perhaps more appropriate value of 5. */
1902 generic_memcpy,
1903 generic_memset,
1915 };
1917 /* core_cost should produce code tuned for Core familly of CPUs. */
1930 static const
1933 /* On all chips taken into consideration lea is 2 cycles and more. With
1934 this cost however our current implementation of synth_mult results in
1935 use of unnecessary temporary registers causing regression on several
1936 SPECfp benchmarks. */
1957 in QImode, HImode and SImode.
1958 Relative to reg-reg move (2). */
1962 in SFmode, DFmode and XFmode */
1964 in SFmode, DFmode and XFmode */
1967 in SImode and DImode */
1969 in SImode and DImode */
1972 in SImode, DImode and TImode */
1974 in SImode, DImode and TImode */
1980 /* FIXME perhaps more appropriate value is 5. */
1988 core_memcpy,
1989 core_memset,
2001 };
2004 /* Set by -mtune. */
2007 /* Set by -mtune or -Os. */
2010 /* Processor feature/optimization bitmasks. */
2011 #define m_386 (1<<PROCESSOR_I386)
2012 #define m_486 (1<<PROCESSOR_I486)
2013 #define m_PENT (1<<PROCESSOR_PENTIUM)
2014 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2015 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2016 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2017 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2018 #define m_CORE2 (1<<PROCESSOR_CORE2)
2019 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2020 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2021 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2022 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2023 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2024 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2025 #define m_INTEL (1<<PROCESSOR_INTEL)
2027 #define m_GEODE (1<<PROCESSOR_GEODE)
2028 #define m_K6 (1<<PROCESSOR_K6)
2029 #define m_K6_GEODE (m_K6 | m_GEODE)
2030 #define m_K8 (1<<PROCESSOR_K8)
2031 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2032 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2033 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2034 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2035 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2036 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2037 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2038 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2039 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2040 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2041 #define m_BTVER (m_BTVER1 | m_BTVER2)
2042 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2044 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2047 #undef DEF_TUNE
2048 #define DEF_TUNE(tune, name, selector) name,
2050 #undef DEF_TUNE
2051 };
2053 /* Feature tests against the various tunings. */
2056 /* Feature tests against the various tunings used to create ix86_tune_features
2057 based on the processor mask. */
2059 #undef DEF_TUNE
2060 #define DEF_TUNE(tune, name, selector) selector,
2062 #undef DEF_TUNE
2063 };
2065 /* Feature tests against the various architecture variations. */
2068 /* Feature tests against the various architecture variations, used to create
2069 ix86_arch_features based on the processor mask. */
2071 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2074 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2077 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2080 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2083 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2085 };
2087 /* In case the average insn count for single function invocation is
2088 lower than this constant, emit fast (but longer) prologue and
2089 epilogue code. */
2090 #define FAST_PROLOGUE_INSN_COUNT 20
2092 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2097 /* Array of the smallest class containing reg number REGNO, indexed by
2098 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2101 {
2102 /* ax, dx, cx, bx */
2104 /* si, di, bp, sp */
2106 /* FP registers */
2109 /* arg pointer */
2110 NON_Q_REGS,
2111 /* flags, fpsr, fpcr, frame */
2113 /* SSE registers */
2116 /* MMX registers */
2119 /* REX registers */
2122 /* SSE REX registers */
2125 /* AVX-512 SSE registers */
2130 /* Mask registers. */
2133 /* MPX bound registers */
2135 };
2137 /* The "default" register map used in 32bit mode. */
2140 {
2152 };
2154 /* The "default" register map used in 64bit mode. */
2157 {
2169 };
2171 /* Define the register numbers to be used in Dwarf debugging information.
2172 The SVR4 reference port C compiler uses the following register numbers
2173 in its Dwarf output code:
2174 0 for %eax (gcc regno = 0)
2175 1 for %ecx (gcc regno = 2)
2176 2 for %edx (gcc regno = 1)
2177 3 for %ebx (gcc regno = 3)
2178 4 for %esp (gcc regno = 7)
2179 5 for %ebp (gcc regno = 6)
2180 6 for %esi (gcc regno = 4)
2181 7 for %edi (gcc regno = 5)
2182 The following three DWARF register numbers are never generated by
2183 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2184 believes these numbers have these meanings.
2185 8 for %eip (no gcc equivalent)
2186 9 for %eflags (gcc regno = 17)
2187 10 for %trapno (no gcc equivalent)
2188 It is not at all clear how we should number the FP stack registers
2189 for the x86 architecture. If the version of SDB on x86/svr4 were
2190 a bit less brain dead with respect to floating-point then we would
2191 have a precedent to follow with respect to DWARF register numbers
2192 for x86 FP registers, but the SDB on x86/svr4 is so completely
2193 broken with respect to FP registers that it is hardly worth thinking
2194 of it as something to strive for compatibility with.
2195 The version of x86/svr4 SDB I have at the moment does (partially)
2196 seem to believe that DWARF register number 11 is associated with
2197 the x86 register %st(0), but that's about all. Higher DWARF
2198 register numbers don't seem to be associated with anything in
2199 particular, and even for DWARF regno 11, SDB only seems to under-
2200 stand that it should say that a variable lives in %st(0) (when
2201 asked via an `=' command) if we said it was in DWARF regno 11,
2202 but SDB still prints garbage when asked for the value of the
2203 variable in question (via a `/' command).
2204 (Also note that the labels SDB prints for various FP stack regs
2205 when doing an `x' command are all wrong.)
2206 Note that these problems generally don't affect the native SVR4
2207 C compiler because it doesn't allow the use of -O with -g and
2208 because when it is *not* optimizing, it allocates a memory
2209 location for each floating-point variable, and the memory
2210 location is what gets described in the DWARF AT_location
2211 attribute for the variable in question.
2212 Regardless of the severe mental illness of the x86/svr4 SDB, we
2213 do something sensible here and we use the following DWARF
2214 register numbers. Note that these are all stack-top-relative
2215 numbers.
2216 11 for %st(0) (gcc regno = 8)
2217 12 for %st(1) (gcc regno = 9)
2218 13 for %st(2) (gcc regno = 10)
2219 14 for %st(3) (gcc regno = 11)
2220 15 for %st(4) (gcc regno = 12)
2221 16 for %st(5) (gcc regno = 13)
2222 17 for %st(6) (gcc regno = 14)
2223 18 for %st(7) (gcc regno = 15)
2224 */
2226 {
2238 };
2240 /* Define parameter passing and return registers. */
2243 {
2245 };
2248 {
2250 };
2253 {
2255 };
2257 /* Additional registers that are clobbered by SYSV calls. */
2260 {
2265 };
2267 /* Define the structure for the machine field in struct function. */
2272 rtx rtl;
2274 };
2276 /* Structure describing stack frame layout.
2277 Stack grows downward:
2279 [arguments]
2280 <- ARG_POINTER
2281 saved pc
2283 saved static chain if ix86_static_chain_on_stack
2285 saved frame pointer if frame_pointer_needed
2286 <- HARD_FRAME_POINTER
2287 [saved regs]
2288 <- regs_save_offset
2289 [padding0]
2291 [saved SSE regs]
2292 <- sse_regs_save_offset
2293 [padding1] |
2294 | <- FRAME_POINTER
2295 [va_arg registers] |
2296 |
2297 [frame] |
2298 |
2299 [padding2] | = to_allocate
2300 <- STACK_POINTER
2301 */
2302 struct ix86_frame
2303 {
2310 /* The offsets relative to ARG_POINTER. */
2311 HOST_WIDE_INT frame_pointer_offset;
2312 HOST_WIDE_INT hard_frame_pointer_offset;
2313 HOST_WIDE_INT stack_pointer_offset;
2314 HOST_WIDE_INT hfp_save_offset;
2315 HOST_WIDE_INT reg_save_offset;
2316 HOST_WIDE_INT sse_reg_save_offset;
2318 /* When save_regs_using_mov is set, emit prologue using
2319 move instead of push instructions. */
2321 };
2323 /* Which cpu are we scheduling for. */
2326 /* Which cpu are we optimizing for. */
2329 /* Which instruction set architecture to use. */
2332 /* True if processor has SSE prefetch instruction. */
2335 /* -mstackrealign option */
2352 /* Preferred alignment for stack boundary in bits. */
2355 /* Alignment for incoming stack boundary in bits specified at
2356 command line. */
2359 /* Default alignment for incoming stack boundary in bits. */
2362 /* Alignment for incoming stack boundary in bits. */
2365 /* Calling abi specific va_list type nodes. */
2369 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2373 /* Fence to use after loop using movnt. */
2374 tree x86_mfence;
2376 /* Register class used for passing given 64bit part of the argument.
2377 These represent classes as documented by the PS ABI, with the exception
2378 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2379 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2381 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2382 whenever possible (upper half does contain padding). */
2383 enum x86_64_reg_class
2384 {
2385 X86_64_NO_CLASS,
2386 X86_64_INTEGER_CLASS,
2387 X86_64_INTEGERSI_CLASS,
2388 X86_64_SSE_CLASS,
2389 X86_64_SSESF_CLASS,
2390 X86_64_SSEDF_CLASS,
2391 X86_64_SSEUP_CLASS,
2392 X86_64_X87_CLASS,
2393 X86_64_X87UP_CLASS,
2394 X86_64_COMPLEX_X87_CLASS,
2395 X86_64_MEMORY_CLASS
2396 };
2398 #define MAX_CLASSES 8
2400 /* Table of constants used by fldpi, fldln2, etc.... */
2404 \f
2409 const_tree);
2421 enum ix86_function_specific_strings
2422 {
2423 IX86_FUNCTION_SPECIFIC_ARCH,
2424 IX86_FUNCTION_SPECIFIC_TUNE,
2425 IX86_FUNCTION_SPECIFIC_MAX
2426 };
2447 \f
2448 #ifndef SUBTARGET32_DEFAULT_CPU
2450 #endif
2452 /* Whether -mtune= or -march= were specified */
2456 /* Vectorization library interface and handlers. */
2462 /* Processor target table, indexed by processor number */
2463 struct ptt
2464 {
2472 };
2474 /* This table must be in sync with enum processor_type in i386.h. */
2476 {
2502 };
2503 \f
2504 static bool
2506 {
2508 }
2510 static unsigned int
2512 {
2515 /* vzeroupper instructions are inserted immediately after reload to
2516 account for possible spills from 256bit registers. The pass
2517 reuses mode switching infrastructure by re-running mode insertion
2518 pass, so disable entities that have already been processed. */
2524 /* Call optimize_mode_switching. */
2527 }
2532 {
2544 };
2547 {
2551 {}
2553 /* opt_pass methods: */
2561 rtl_opt_pass *
2563 {
2565 }
2567 /* Return true if a red-zone is in use. */
2571 {
2573 }
2574 \f
2575 /* Return a string that documents the current -m options. The caller is
2576 responsible for freeing the string. */
2582 {
2583 struct ix86_target_opts
2584 {
2587 };
2589 /* This table is ordered so that options like -msse4.2 that imply
2590 preceding options while match those first. */
2592 {
2635 };
2637 /* Flag options. */
2639 {
2668 };
2685 /* Add -march= option. */
2687 {
2690 }
2692 /* Add -mtune= option. */
2694 {
2697 }
2699 /* Add -m32/-m64/-mx32. */
2701 {
2704 else
2706 isa &= ~ (OPTION_MASK_ISA_64BIT
2707 | OPTION_MASK_ABI_64
2709 }
2710 else
2714 /* Pick out the options in isa options. */
2716 {
2718 {
2721 }
2722 }
2725 {
2728 isa);
2729 }
2731 /* Add flag options. */
2733 {
2735 {
2738 }
2739 }
2742 {
2745 }
2747 /* Add -fpmath= option. */
2749 {
2752 {
2767 }
2768 }
2770 /* Any options? */
2776 /* Size the string. */
2780 {
2785 }
2787 /* Build the string. */
2792 {
2799 {
2801 line_len++;
2804 {
2808 }
2809 }
2813 {
2817 }
2818 }
2824 }
2826 /* Return true, if profiling code should be emitted before
2827 prologue. Otherwise it returns false.
2828 Note: For x86 with "hotfix" it is sorried. */
2829 static bool
2831 {
2833 }
2835 /* Function that is callable from the debugger to print the current
2836 options. */
2837 void ATTRIBUTE_UNUSED
2839 {
2845 {
2848 }
2849 else
2853 }
2856 #define DEF_ENUM
2857 #define DEF_ALG(alg, name) #name,
2859 #undef DEF_ENUM
2860 #undef DEF_ALG
2861 };
2863 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2864 The string is of the following form (or comma separated list of it):
2866 strategy_alg:max_size:[align|noalign]
2868 where the full size range for the strategy is either [0, max_size] or
2869 [min_size, max_size], in which min_size is the max_size + 1 of the
2870 preceding range. The last size range must have max_size == -1.
2872 Examples:
2874 1.
2875 -mmemcpy-strategy=libcall:-1:noalign
2877 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2880 2.
2881 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2883 This is to tell the compiler to use the following strategy for memset
2884 1) when the expected size is between [1, 16], use rep_8byte strategy;
2885 2) when the size is between [17, 2048], use vector_loop;
2886 3) when the size is > 2048, use libcall. */
2888 struct stringop_size_range
2889 {
2891 stringop_alg alg;
2893 };
2895 static void
2897 {
2905 else
2910 do
2911 {
2921 {
2925 }
2928 {
2932 }
2939 {
2941 alg_name,
2944 }
2952 else
2953 {
2957 }
2958 n++;
2960 }
2964 {
2969 }
2972 {
2976 }
2978 /* Now override the default algs array. */
2980 {
2986 }
2987 }
2989 \f
2990 /* parse -mtune-ctrl= option. When DUMP is true,
2991 print the features that are explicitly set. */
2993 static void
2995 {
3003 do
3004 {
3011 {
3012 curr_feature_string++;
3014 }
3016 {
3018 {
3024 }
3025 }
3030 }
3033 }
3035 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3036 processor type. */
3038 static void
3040 {
3045 {
3048 else
3050 }
3053 {
3058 }
3061 }
3064 /* Override various settings based on options. If MAIN_ARGS_P, the
3065 options are from the command line, otherwise they are from
3066 attributes. */
3068 static void
3072 {
3080 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3081 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3082 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3083 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3084 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3085 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3086 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3087 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3088 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3089 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3090 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3091 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3092 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3093 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3094 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3095 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3096 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3097 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3098 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3099 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3100 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3101 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3102 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3103 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3104 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3105 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3106 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3107 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3108 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3109 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3110 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3111 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3112 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3113 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3114 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3115 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3116 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3117 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3118 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3119 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3120 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3121 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3122 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3123 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3124 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3125 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3126 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3128 #define PTA_CORE2 \
3129 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3130 | PTA_CX16 | PTA_FXSR)
3131 #define PTA_NEHALEM \
3132 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3133 #define PTA_WESTMERE \
3134 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3135 #define PTA_SANDYBRIDGE \
3136 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3137 #define PTA_IVYBRIDGE \
3138 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3139 #define PTA_HASWELL \
3140 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3141 | PTA_FMA | PTA_MOVBE | PTA_RTM | PTA_HLE)
3142 #define PTA_BROADWELL \
3143 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3144 #define PTA_BONNELL \
3145 (PTA_CORE2 | PTA_MOVBE)
3146 #define PTA_SILVERMONT \
3147 (PTA_WESTMERE | PTA_MOVBE)
3149 /* if this reaches 64, need to widen struct pta flags below */
3151 static struct pta
3152 {
3157 }
3159 {
3193 PTA_SANDYBRIDGE},
3195 PTA_SANDYBRIDGE},
3197 PTA_IVYBRIDGE},
3199 PTA_IVYBRIDGE},
3289 PTA_64BIT
3291 };
3293 /* -mrecip options. */
3294 static struct
3295 {
3298 }
3300 {
3307 };
3311 /* Set up prefix/suffix so the error messages refer to either the command
3312 line argument, or the attribute(target). */
3314 {
3318 }
3319 else
3320 {
3324 }
3326 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3327 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3330 #ifdef TARGET_BI_ARCH
3331 else
3332 {
3333 #if TARGET_BI_ARCH == 1
3334 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3335 is on and OPTION_MASK_ABI_X32 is off. We turn off
3336 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3337 -mx32. */
3340 #else
3341 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3342 on and OPTION_MASK_ABI_64 is off. We turn off
3343 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3344 -m64. */
3347 #endif
3348 }
3349 #endif
3352 {
3353 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3354 OPTION_MASK_ABI_64 for TARGET_X32. */
3357 }
3360 | OPTION_MASK_ABI_X32
3363 {
3364 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3365 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3368 }
3370 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3371 SUBTARGET_OVERRIDE_OPTIONS;
3372 #endif
3374 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3375 SUBSUBTARGET_OVERRIDE_OPTIONS;
3376 #endif
3378 /* -fPIC is the default for x86_64. */
3382 /* Need to check -mtune=generic first. */
3384 {
3385 /* As special support for cross compilers we read -mtune=native
3386 as -mtune=generic. With native compilers we won't see the
3387 -mtune=native, as it was changed by the driver. */
3389 {
3391 }
3396 }
3397 else
3398 {
3402 {
3403 opts->x_ix86_tune_string
3406 }
3408 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3409 or defaulted. We need to use a sensible tune option. */
3411 {
3413 }
3414 }
3418 {
3419 /* rep; movq isn't available in 32-bit code. */
3422 }
3425 opts->x_ix86_arch_string
3428 else
3432 {
3440 }
3441 else
3448 /* For targets using ms ABI enable ms-extensions, if not
3449 explicit turned off. For non-ms ABI we turn off this
3450 option. */
3455 {
3457 {
3501 {
3504 }
3512 }
3513 }
3514 else
3515 {
3516 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3517 use of rip-relative addressing. This eliminates fixups that
3518 would otherwise be needed if this object is to be placed in a
3519 DLL, and is essentially just as efficient as direct addressing. */
3525 else
3527 }
3529 {
3532 }
3540 {
3543 /* Default cpu tuning to the architecture. */
3691 }
3715 {
3719 {
3721 {
3723 {
3731 }
3732 else
3735 }
3736 }
3737 /* Intel CPUs have always interpreted SSE prefetch instructions as
3738 NOPs; so, we can enable SSE prefetch instructions even when
3739 -mtune (rather than -march) points us to a processor that has them.
3740 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3741 higher processors. */
3746 }
3754 #ifndef USE_IX86_FRAME_POINTER
3755 #define USE_IX86_FRAME_POINTER 0
3756 #endif
3758 #ifndef USE_X86_64_FRAME_POINTER
3759 #define USE_X86_64_FRAME_POINTER 0
3760 #endif
3762 /* Set the default values for switches whose default depends on TARGET_64BIT
3763 in case they weren't overwritten by command line options. */
3765 {
3773 opts->x_flag_unwind_tables
3777 }
3778 else
3779 {
3781 opts->x_flag_omit_frame_pointer
3787 }
3792 else
3795 /* Arrange to set up i386_stack_locals for all functions. */
3798 /* Validate -mregparm= value. */
3800 {
3804 {
3808 }
3809 }
3813 /* Default align_* from the processor table. */
3815 {
3818 }
3820 {
3823 }
3825 {
3827 }
3829 /* Provide default for -mbranch-cost= value. */
3834 {
3835 opts->x_target_flags
3838 /* Enable by default the SSE and MMX builtins. Do allow the user to
3839 explicitly disable any of these. In particular, disabling SSE and
3840 MMX for kernel code is extremely useful. */
3842 opts->x_ix86_isa_flags
3849 }
3850 else
3851 {
3852 opts->x_target_flags
3856 opts->x_ix86_isa_flags
3859 /* i386 ABI does not specify red zone. It still makes sense to use it
3860 when programmer takes care to stack from being destroyed. */
3863 }
3865 /* Keep nonleaf frame pointers. */
3871 /* If we're doing fast math, we don't care about comparison order
3872 wrt NaNs. This lets us use a shorter comparison sequence. */
3876 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3877 since the insns won't need emulation. */
3881 /* Likewise, if the target doesn't have a 387, or we've specified
3882 software floating point, don't use 387 inline intrinsics. */
3886 /* Turn on MMX builtins for -msse. */
3888 opts->x_ix86_isa_flags
3891 /* Enable SSE prefetch. */
3896 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
3899 opts->x_ix86_isa_flags
3902 /* Enable popcnt instruction for -msse4.2 or -mabm. */
3905 opts->x_ix86_isa_flags
3908 /* Enable lzcnt instruction for -mabm. */
3910 opts->x_ix86_isa_flags
3913 /* Validate -mpreferred-stack-boundary= value or default it to
3914 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3917 {
3924 {
3928 else
3931 }
3932 else
3933 ix86_preferred_stack_boundary
3935 }
3937 /* Set the default value for -mstackrealign. */
3943 /* Validate -mincoming-stack-boundary= value or default it to
3944 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3947 {
3954 else
3955 {
3956 ix86_user_incoming_stack_boundary
3958 ix86_incoming_stack_boundary
3960 }
3961 }
3963 /* Accept -msseregparm only if at least SSE support is enabled. */
3969 {
3971 {
3973 {
3976 }
3979 {
3982 }
3983 }
3984 }
3985 /* For all chips supporting SSE2, -mfpmath=sse performs better than
3986 fpmath=387. The second is however default at many targets since the
3987 extra 80bit precision of temporaries is considered to be part of ABI.
3988 Overwrite the default at least for -ffast-math.
3989 TODO: -mfpmath=both seems to produce same performing code with bit
3990 smaller binaries. It is however not clear if register allocation is
3991 ready for this setting.
3992 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
3993 codegen. We may switch to 387 with -ffast-math for size optimized
3994 functions. */
3998 else
4001 /* If the i387 is disabled, then do not return values in it. */
4005 /* Use external vectorized library in vectorizing intrinsics. */
4008 {
4019 }
4026 /* If stack probes are required, the space used for large function
4027 arguments on the stack must also be probed, so enable
4028 -maccumulate-outgoing-args so this happens in the prologue. */
4031 {
4036 }
4038 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4039 {
4045 }
4047 /* When scheduling description is not available, disable scheduler pass
4048 so it won't slow down the compilation and make x87 code slower. */
4069 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4071 && HAVE_prefetch
4076 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4077 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4082 {
4085 {
4087 ix86_gen_tls_local_dynamic_base_64
4089 }
4090 else
4091 {
4093 ix86_gen_tls_local_dynamic_base_64
4095 }
4096 }
4097 else
4101 {
4111 }
4112 else
4113 {
4123 }
4125 #ifdef USE_IX86_CLD
4126 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4129 #endif
4132 {
4137 }
4139 {
4143 }
4145 {
4146 #if defined(PROFILE_BEFORE_PROLOGUE)
4148 #else
4150 #endif
4151 }
4153 /* When not opts->x_optimize for size, enable vzeroupper optimization for
4154 TARGET_AVX with -fexpensive-optimizations and split 32-byte
4155 AVX unaligned load/store. */
4157 {
4167 /* Enable 128-bit AVX instruction generation
4168 for the auto-vectorizer. */
4172 }
4175 {
4182 {
4185 {
4187 q++;
4188 }
4189 else
4194 else
4195 {
4198 {
4201 }
4204 {
4208 }
4209 }
4214 else
4216 }
4217 }
4224 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4225 for 64-bit Bionic. */
4230 ? MASK_LONG_DOUBLE_128
4233 /* Only one of them can be active. */
4237 /* Save the initial options in case the user does function specific
4238 options. */
4240 target_option_default_node = target_option_current_node
4243 /* Handle stack protector */
4245 opts->x_ix86_stack_protector_guard
4248 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4250 {
4254 }
4257 {
4261 }
4262 }
4264 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4266 static void
4268 {
4270 static struct register_pass_info insert_vzeroupper_info
4273 };
4278 /* This needs to be done at start up. It's convenient to do it here. */
4280 }
4282 /* Update register usage after having seen the compiler flags. */
4284 static void
4286 {
4290 /* The PIC register, if it exists, is fixed. */
4295 /* For 32-bit targets, squash the REX registers. */
4297 {
4304 }
4306 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4314 {
4315 /* Set/reset conditionally defined registers from
4316 CALL_USED_REGISTERS initializer. */
4320 /* Calculate registers of CLOBBERED_REGS register set
4321 as call used registers from GENERAL_REGS register set. */
4325 }
4327 /* If MMX is disabled, squash the registers. */
4333 /* If SSE is disabled, squash the registers. */
4339 /* If the FPU is disabled, squash the registers. */
4345 /* If AVX512F is disabled, squash the registers. */
4347 {
4353 }
4355 /* If MPX is disabled, squash the registers. */
4359 }
4361 \f
4362 /* Save the current options */
4364 static void
4367 {
4402 /* The fields are char but the variables are not; make sure the
4403 values fit in the fields. */
4408 }
4410 /* Restore the current options */
4412 static void
4415 {
4421 /* We don't change -fPIC. */
4458 /* Recreate the arch feature tests if the arch changed */
4460 {
4465 }
4467 /* Recreate the tune optimization tests */
4470 }
4472 /* Print the current options */
4474 static void
4477 {
4495 {
4498 }
4499 }
4501 \f
4502 /* Inner function to process the attribute((target(...))), take an argument and
4503 set the current options from the argument. If we have a list, recursively go
4504 over the list. */
4506 static bool
4511 {
4515 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4516 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4517 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4518 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4519 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4521 enum ix86_opt_type
4522 {
4523 ix86_opt_unknown,
4524 ix86_opt_yes,
4525 ix86_opt_no,
4526 ix86_opt_str,
4527 ix86_opt_enum,
4528 ix86_opt_isa
4529 };
4531 static const struct
4532 {
4539 /* isa options */
4582 /* enum options */
4585 /* string options */
4589 /* flag options */
4591 OPT_mcld,
4592 MASK_CLD),
4595 OPT_mfancy_math_387,
4596 MASK_NO_FANCY_MATH_387),
4599 OPT_mieee_fp,
4600 MASK_IEEE_FP),
4603 OPT_minline_all_stringops,
4604 MASK_INLINE_ALL_STRINGOPS),
4607 OPT_minline_stringops_dynamically,
4608 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4611 OPT_mno_align_stringops,
4612 MASK_NO_ALIGN_STRINGOPS),
4615 OPT_mrecip,
4616 MASK_RECIP),
4618 };
4620 /* If this is a list, recurse to get the options. */
4622 {
4629 enum_opts_set))
4633 }
4636 {
4639 }
4641 /* Handle multiple arguments separated by commas. */
4645 {
4659 {
4663 }
4664 else
4665 {
4668 }
4670 /* Recognize no-xxx. */
4672 {
4676 }
4677 else
4680 /* Find the option. */
4684 {
4692 {
4697 }
4698 }
4700 /* Process the option. */
4702 {
4705 }
4708 {
4714 }
4717 {
4723 else
4725 }
4728 {
4730 {
4733 }
4734 else
4736 }
4739 {
4747 global_dc);
4748 else
4749 {
4752 }
4753 }
4755 else
4757 }
4760 }
4762 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4764 tree
4768 {
4783 /* Process each of the options on the chain. */
4788 /* If the changed options are different from the default, rerun
4789 ix86_option_override_internal, and then save the options away.
4790 The string options are are attribute options, and will be undone
4791 when we copy the save structure. */
4797 {
4798 /* If we are using the default tune= or arch=, undo the string assigned,
4799 and use the default. */
4810 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4815 {
4818 }
4820 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4823 /* Add any builtin functions with the new isa if any. */
4826 /* Save the current options unless we are validating options for
4827 #pragma. */
4834 /* Free up memory allocated to hold the strings */
4837 }
4840 }
4842 /* Hook to validate attribute((target("string"))). */
4844 static bool
4847 tree args,
4849 {
4854 /* attribute((target("default"))) does nothing, beyond
4855 affecting multi-versioning. */
4864 /* Get the optimization options of the current function. */
4870 /* Init func_options. */
4878 /* Initialize func_options to the default before its target options can
4879 be set. */
4892 {
4897 }
4900 }
4902 \f
4903 /* Hook to determine if one function can safely inline another. */
4905 static bool
4907 {
4912 /* If callee has no option attributes, then it is ok to inline. */
4916 /* If caller has no option attributes, but callee does then it is not ok to
4917 inline. */
4921 else
4922 {
4926 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4927 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4928 function. */
4933 /* See if we have the same non-isa options. */
4937 /* See if arch, tune, etc. are the same. */
4950 else
4952 }
4955 }
4957 \f
4958 /* Remember the last target of ix86_set_current_function. */
4961 /* Invalidate ix86_previous_fndecl cache. */
4962 void
4964 {
4966 }
4968 /* Establish appropriate back-end context for processing the function
4969 FNDECL. The argument might be NULL to indicate processing at top
4970 level, outside of any function scope. */
4971 static void
4973 {
4974 /* Only change the context if the function changes. This hook is called
4975 several times in the course of compiling a function, and we don't want to
4976 slow things down too much or call target_reinit when it isn't safe. */
4978 {
4979 tree old_tree = (ix86_previous_fndecl
4983 tree new_tree = (fndecl
4989 ;
4992 {
4997 else
5000 }
5003 {
5011 else
5014 }
5015 }
5016 }
5018 \f
5019 /* Return true if this goes in large data/bss. */
5021 static bool
5023 {
5027 /* Functions are never large data. */
5032 {
5038 }
5039 else
5040 {
5043 /* If this is an incomplete type with size 0, then we can't put it
5044 in data because it might be too big when completed. */
5047 }
5050 }
5052 /* Switch to the appropriate section for output of DECL.
5053 DECL is either a `VAR_DECL' node or a constant of some sort.
5054 RELOC indicates whether forming the initial value of DECL requires
5055 link-time relocations. */
5060 {
5063 {
5067 {
5101 /* We don't split these for medium model. Place them into
5102 default sections and hope for best. */
5104 }
5106 {
5107 /* We might get called with string constants, but get_named_section
5108 doesn't like them as they are not DECLs. Also, we need to set
5109 flags in that case. */
5113 }
5114 }
5116 }
5118 /* Select a set of attributes for section NAME based on the properties
5119 of DECL and whether or not RELOC indicates that DECL's initializer
5120 might contain runtime relocations. */
5122 static unsigned int ATTRIBUTE_UNUSED
5124 {
5138 }
5140 /* Build up a unique section name, expressed as a
5141 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5142 RELOC indicates whether the initial value of EXP requires
5143 link-time relocations. */
5145 static void ATTRIBUTE_UNUSED
5147 {
5150 {
5152 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5156 {
5180 /* We don't split these for medium model. Place them into
5181 default sections and hope for best. */
5183 }
5185 {
5192 /* If we're using one_only, then there needs to be a .gnu.linkonce
5193 prefix to the section name. */
5200 }
5201 }
5203 }
5205 #ifdef COMMON_ASM_OP
5206 /* This says how to output assembler code to declare an
5207 uninitialized external linkage data object.
5209 For medium model x86-64 we need to use .largecomm opcode for
5210 large objects. */
5211 void
5215 {
5219 else
5224 }
5225 #endif
5227 /* Utility function for targets to use in implementing
5228 ASM_OUTPUT_ALIGNED_BSS. */
5230 void
5234 {
5238 else
5241 #ifdef ASM_DECLARE_OBJECT_NAME
5244 #else
5245 /* Standard thing is just output label for the object. */
5249 }
5250 \f
5251 /* Decide whether we must probe the stack before any space allocation
5252 on this target. It's essentially TARGET_STACK_PROBE except when
5253 -fstack-check causes the stack to be already probed differently. */
5255 bool
5257 {
5258 /* Do not probe the stack twice if static stack checking is enabled. */
5263 }
5264 \f
5265 /* Decide whether we can make a sibling call to a function. DECL is the
5266 declaration of the function being targeted by the call and EXP is the
5267 CALL_EXPR representing the call. */
5269 static bool
5271 {
5275 /* If we are generating position-independent code, we cannot sibcall
5276 optimize any indirect call, or a direct call to a global function,
5277 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
5279 && !TARGET_64BIT
5280 && flag_pic
5284 /* If we need to align the outgoing stack, then sibcalling would
5285 unalign the stack, which may break the called function. */
5291 {
5294 }
5295 else
5296 {
5297 /* We're looking at the CALL_EXPR, we need the type of the function. */
5302 }
5304 /* Check that the return value locations are the same. Like
5305 if we are returning floats on the 80387 register stack, we cannot
5306 make a sibcall from a function that doesn't return a float to a
5307 function that does or, conversely, from a function that does return
5308 a float to a function that doesn't; the necessary stack adjustment
5309 would not be executed. This is also the place we notice
5310 differences in the return value ABI. Note that it is ok for one
5311 of the functions to have void return type as long as the return
5312 value of the other is passed in a register. */
5317 {
5320 }
5322 ;
5327 {
5328 /* The SYSV ABI has more call-clobbered registers;
5329 disallow sibcalls from MS to SYSV. */
5333 }
5334 else
5335 {
5336 /* If this call is indirect, we'll need to be able to use a
5337 call-clobbered register for the address of the target function.
5338 Make sure that all such registers are not used for passing
5339 parameters. Note that DLLIMPORT functions are indirect. */
5342 {
5344 {
5345 /* ??? Need to count the actual number of registers to be used,
5346 not the possible number of registers. Fix later. */
5348 }
5349 }
5350 }
5352 /* Otherwise okay. That also includes certain types of indirect calls. */
5354 }
5356 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5357 and "sseregparm" calling convention attributes;
5358 arguments as in struct attribute_spec.handler. */
5360 static tree
5362 tree args,
5365 {
5370 {
5372 name);
5375 }
5377 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5379 {
5380 tree cst;
5383 {
5385 }
5388 {
5390 }
5394 {
5397 name);
5399 }
5401 {
5405 }
5408 }
5411 {
5412 /* Do not warn when emulating the MS ABI. */
5417 name);
5420 }
5422 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5424 {
5426 {
5428 }
5430 {
5432 }
5434 {
5436 }
5438 {
5440 }
5441 }
5443 /* Can combine stdcall with fastcall (redundant), regparm and
5444 sseregparm. */
5446 {
5448 {
5450 }
5452 {
5454 }
5456 {
5458 }
5459 }
5461 /* Can combine cdecl with regparm and sseregparm. */
5463 {
5465 {
5467 }
5469 {
5471 }
5473 {
5475 }
5476 }
5478 {
5481 name);
5483 {
5485 }
5487 {
5489 }
5491 {
5493 }
5494 }
5496 /* Can combine sseregparm with all attributes. */
5499 }
5501 /* The transactional memory builtins are implicitly regparm or fastcall
5502 depending on the ABI. Override the generic do-nothing attribute that
5503 these builtins were declared with, and replace it with one of the two
5504 attributes that we expect elsewhere. */
5506 static tree
5508 tree args ATTRIBUTE_UNUSED,
5510 {
5511 tree alt;
5513 /* In no case do we want to add the placeholder attribute. */
5516 /* The 64-bit ABI is unchanged for transactional memory. */
5520 /* ??? Is there a better way to validate 32-bit windows? We have
5521 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5524 else
5525 {
5528 }
5532 }
5534 /* This function determines from TYPE the calling-convention. */
5536 unsigned int
5538 {
5541 tree attrs;
5548 {
5558 /* Regparam isn't allowed for thiscall and fastcall. */
5560 {
5565 }
5569 }
5576 || is_stdarg
5582 }
5584 /* Return 0 if the attributes for two types are incompatible, 1 if they
5585 are compatible, and 2 if they are nearly compatible (which causes a
5586 warning to be generated). */
5588 static int
5590 {
5606 }
5607 \f
5608 /* Return the regparm value for a function with the indicated TYPE and DECL.
5609 DECL may be NULL when calling function indirectly
5610 or considering a libcall. */
5612 static int
5614 {
5615 tree attr;
5626 {
5629 {
5632 }
5633 }
5639 /* Use register calling convention for local functions when possible. */
5642 /* Caller and callee must agree on the calling convention, so
5643 checking here just optimize means that with
5644 __attribute__((optimize (...))) caller could use regparm convention
5645 and callee not, or vice versa. Instead look at whether the callee
5646 is optimized or not. */
5649 {
5650 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5653 {
5656 /* Make sure no regparm register is taken by a
5657 fixed register variable. */
5662 /* We don't want to use regparm(3) for nested functions as
5663 these use a static chain pointer in the third argument. */
5667 /* In 32-bit mode save a register for the split stack. */
5671 /* Each fixed register usage increases register pressure,
5672 so less registers should be used for argument passing.
5673 This functionality can be overriden by an explicit
5674 regparm value. */
5677 globals++;
5679 local_regparm
5684 }
5685 }
5688 }
5690 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5691 DFmode (2) arguments in SSE registers for a function with the
5692 indicated TYPE and DECL. DECL may be NULL when calling function
5693 indirectly or considering a libcall. Otherwise return 0. */
5695 static int
5697 {
5700 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5701 by the sseregparm attribute. */
5704 {
5706 {
5708 {
5712 else
5715 }
5717 }
5720 }
5722 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5723 (and DFmode for SSE2) arguments in SSE registers. */
5726 {
5727 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5731 }
5734 }
5736 /* Return true if EAX is live at the start of the function. Used by
5737 ix86_expand_prologue to determine if we need special help before
5738 calling allocate_stack_worker. */
5740 static bool
5742 {
5743 /* Cheat. Don't bother working forward from ix86_function_regparm
5744 to the function type to whether an actual argument is located in
5745 eax. Instead just look at cfg info, which is still close enough
5746 to correct at this point. This gives false positives for broken
5747 functions that might use uninitialized data that happens to be
5748 allocated in eax, but who cares? */
5750 }
5752 static bool
5754 {
5755 tree attr;
5758 {
5764 /* For 32-bit MS-ABI the default is to keep aggregate
5765 return pointer. */
5768 }
5770 }
5772 /* Value is the number of bytes of arguments automatically
5773 popped when returning from a subroutine call.
5774 FUNDECL is the declaration node of the function (as a tree),
5775 FUNTYPE is the data type of the function (as a tree),
5776 or for a library call it is an identifier node for the subroutine name.
5777 SIZE is the number of bytes of arguments passed on the stack.
5779 On the 80386, the RTD insn may be used to pop them if the number
5780 of args is fixed, but if the number is variable then the caller
5781 must pop them all. RTD can't be used for library calls now
5782 because the library is compiled with the Unix compiler.
5783 Use of RTD is a selectable option, since it is incompatible with
5784 standard Unix calling sequences. If the option is not selected,
5785 the caller must always pop the args.
5787 The attribute stdcall is equivalent to RTD on a per module basis. */
5789 static int
5791 {
5794 /* None of the 64-bit ABIs pop arguments. */
5805 /* Lose any fake structure return argument if it is passed on the stack. */
5808 {
5812 }
5815 }
5817 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5819 static bool
5821 {
5822 /* Check operand constraints in case hard registers were propagated
5823 into insn pattern. This check prevents combine pass from
5824 generating insn patterns with invalid hard register operands.
5825 These invalid insns can eventually confuse reload to error out
5826 with a spill failure. See also PRs 46829 and 46843. */
5828 {
5835 {
5843 /* For pre-AVX disallow unaligned loads/stores where the
5844 instructions don't support it. */
5848 {
5852 }
5854 /* A unary operator may be accepted by the predicate, but it
5855 is irrelevant for matching constraints. */
5860 {
5868 }
5875 /* Operand has no constraints, anything is OK. */
5879 {
5882 && operands_match_p
5886 {
5889 }
5890 }
5894 }
5895 }
5898 }
5899 \f
5900 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5902 static unsigned HOST_WIDE_INT
5904 {
5908 }
5909 \f
5910 /* Argument support functions. */
5912 /* Return true when register may be used to pass function parameters. */
5913 bool
5915 {
5920 {
5924 else
5930 }
5936 /* TODO: The function should depend on current function ABI but
5937 builtins.c would need updating then. Therefore we use the
5938 default ABI. */
5940 /* RAX is used as hidden argument to va_arg functions. */
5946 else
5953 }
5955 /* Return if we do not know how to pass TYPE solely in registers. */
5957 static bool
5959 {
5963 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5964 The layout_type routine is crafty and tries to trick us into passing
5965 currently unsupported vector types on the stack by using TImode. */
5968 }
5970 /* It returns the size, in bytes, of the area reserved for arguments passed
5971 in registers for the function represented by fndecl dependent to the used
5972 abi format. */
5973 int
5975 {
5979 else
5984 }
5986 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5987 call abi used. */
5988 enum calling_abi
5990 {
5992 {
5995 {
5998 }
6002 }
6004 }
6006 /* We add this as a workaround in order to use libc_has_function
6007 hook in i386.md. */
6008 bool
6010 {
6012 }
6014 static bool
6016 {
6018 {
6022 else
6024 }
6026 }
6028 static enum calling_abi
6030 {
6034 }
6036 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6037 call abi used. */
6038 enum calling_abi
6040 {
6044 }
6046 /* Write the extra assembler code needed to declare a function properly. */
6048 void
6050 tree decl)
6051 {
6055 {
6061 }
6063 #ifdef SUBTARGET_ASM_UNWIND_INIT
6065 #endif
6069 /* Output magic byte marker, if hot-patch attribute is set. */
6071 {
6073 {
6074 /* leaq [%rsp + 0], %rsp */
6077 }
6078 else
6079 {
6080 /* movl.s %edi, %edi
6081 push %ebp
6082 movl.s %esp, %ebp */
6085 }
6086 }
6087 }
6089 /* regclass.c */
6092 /* Implementation of call abi switching target hook. Specific to FNDECL
6093 the specific call register sets are set. See also
6094 ix86_conditional_register_usage for more details. */
6095 void
6097 {
6100 else
6102 }
6104 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6105 expensive re-initialization of init_regs each time we switch function context
6106 since this is needed only during RTL expansion. */
6107 static void
6109 {
6113 }
6115 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6116 for a call to a function whose data type is FNTYPE.
6117 For a library call, FNTYPE is 0. */
6119 void
6123 tree fndecl,
6125 {
6131 {
6134 }
6135 else
6136 {
6139 }
6143 /* Set up the number of registers to use for passing arguments. */
6146 {
6148 ? X86_64_REGPARM_MAX
6150 }
6152 {
6155 {
6157 ? X86_64_SSE_REGPARM_MAX
6159 }
6160 }
6168 /* Because type might mismatch in between caller and callee, we need to
6169 use actual type of function for local calls.
6170 FIXME: cgraph_analyze can be told to actually record if function uses
6171 va_start so for local functions maybe_vaarg can be made aggressive
6172 helping K&R code.
6173 FIXME: once typesytem is fixed, we won't need this code anymore. */
6186 {
6187 /* If there are variable arguments, then we won't pass anything
6188 in registers in 32-bit mode. */
6190 {
6199 }
6201 /* Use ecx and edx registers if function has fastcall attribute,
6202 else look for regparm information. */
6204 {
6207 {
6210 }
6212 {
6215 }
6216 else
6218 }
6220 /* Set up the number of SSE registers used for passing SFmode
6221 and DFmode arguments. Warn for mismatching ABI. */
6223 }
6224 }
6226 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6227 But in the case of vector types, it is some vector mode.
6229 When we have only some of our vector isa extensions enabled, then there
6230 are some modes for which vector_mode_supported_p is false. For these
6231 modes, the generic vector support in gcc will choose some non-vector mode
6232 in order to implement the type. By computing the natural mode, we'll
6233 select the proper ABI location for the operand and not depend on whatever
6234 the middle-end decides to do with these vector types.
6236 The midde-end can't deal with the vector types > 16 bytes. In this
6237 case, we return the original mode and warn ABI change if CUM isn't
6238 NULL.
6240 If INT_RETURN is true, warn ABI change if the vector mode isn't
6241 available for function return value. */
6243 static enum machine_mode
6246 {
6250 {
6253 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6255 {
6260 else
6263 /* Get the mode which has this inner mode and number of units. */
6267 {
6269 {
6274 {
6278 }
6280 {
6284 }
6287 }
6289 {
6294 {
6298 }
6300 {
6304 }
6307 }
6310 {
6315 {
6319 }
6321 {
6325 }
6326 }
6328 {
6333 {
6337 }
6339 {
6343 }
6344 }
6346 }
6349 }
6350 }
6353 }
6355 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6356 this may not agree with the mode that the type system has chosen for the
6357 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6358 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6360 static rtx
6363 {
6364 rtx tmp;
6368 else
6369 {
6373 }
6376 }
6378 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6379 of this code is to classify each 8bytes of incoming argument by the register
6380 class and assign registers accordingly. */
6382 /* Return the union class of CLASS1 and CLASS2.
6383 See the x86-64 PS ABI for details. */
6385 static enum x86_64_reg_class
6387 {
6388 /* Rule #1: If both classes are equal, this is the resulting class. */
6392 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6393 the other class. */
6399 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6403 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6411 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6412 MEMORY is used. */
6421 /* Rule #6: Otherwise class SSE is used. */
6423 }
6425 /* Classify the argument of type TYPE and mode MODE.
6426 CLASSES will be filled by the register class used to pass each word
6427 of the operand. The number of words is returned. In case the parameter
6428 should be passed in memory, 0 is returned. As a special case for zero
6429 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6431 BIT_OFFSET is used internally for handling records and specifies offset
6432 of the offset in bits modulo 512 to avoid overflow cases.
6434 See the x86-64 PS ABI for details.
6435 */
6437 static int
6440 {
6441 HOST_WIDE_INT bytes =
6443 int words
6446 /* Variable sized entities are always passed/returned in memory. */
6455 {
6457 tree field;
6460 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6467 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6468 signalize memory class, so handle it as special case. */
6470 {
6473 }
6475 /* Classify each field of record and merge classes. */
6477 {
6479 /* And now merge the fields of structure. */
6481 {
6483 {
6489 /* Bitfields are always classified as integer. Handle them
6490 early, since later code would consider them to be
6491 misaligned integers. */
6493 {
6502 }
6503 else
6504 {
6509 /* Flexible array member is ignored. */
6516 {
6520 {
6523 "the ABI of passing struct with"
6524 " a flexible array member has"
6526 }
6528 }
6530 subclasses,
6540 }
6541 }
6542 }
6546 /* Arrays are handled as small records. */
6547 {
6554 /* The partial classes are now full classes. */
6565 }
6568 /* Unions are similar to RECORD_TYPE but offset is always 0.
6569 */
6571 {
6573 {
6581 bit_offset);
6586 }
6587 }
6592 }
6595 {
6596 /* When size > 16 bytes, if the first one isn't
6597 X86_64_SSE_CLASS or any other ones aren't
6598 X86_64_SSEUP_CLASS, everything should be passed in
6599 memory. */
6606 }
6608 /* Final merger cleanup. */
6610 {
6611 /* If one class is MEMORY, everything should be passed in
6612 memory. */
6616 /* The X86_64_SSEUP_CLASS should be always preceded by
6617 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6621 {
6622 /* The first one should never be X86_64_SSEUP_CLASS. */
6625 }
6627 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6628 everything should be passed in memory. */
6631 {
6634 /* The first one should never be X86_64_X87UP_CLASS. */
6637 {
6640 "the ABI of passing union with long double"
6642 }
6644 }
6645 }
6647 }
6649 /* Compute alignment needed. We align all types to natural boundaries with
6650 exception of XFmode that is aligned to 64bits. */
6652 {
6661 /* Misaligned fields are always returned in memory. */
6664 }
6666 /* for V1xx modes, just use the base mode */
6671 /* Classification of atomic types. */
6673 {
6689 {
6692 /* Analyze last 128 bits only. */
6696 {
6699 }
6701 {
6704 }
6706 {
6710 }
6712 {
6715 }
6716 else
6718 }
6725 /* OImode shouldn't be used directly. */
6732 else
6750 else
6751 {
6755 {
6758 "the ABI of passing structure with complex float"
6760 }
6763 }
6772 /* This modes is larger than 16 bytes. */
6830 else
6834 }
6835 }
6837 /* Examine the argument and return set number of register required in each
6838 class. Return 0 iff parameter should be passed in memory. */
6839 static int
6842 {
6852 {
6874 }
6876 }
6878 /* Construct container for the argument used by GCC interface. See
6879 FUNCTION_ARG for the detailed description. */
6881 static rtx
6885 {
6886 /* The following variables hold the static issued_error state. */
6900 rtx ret;
6911 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6912 some less clueful developer tries to use floating-point anyway. */
6914 {
6916 {
6918 {
6921 }
6922 }
6924 {
6927 }
6929 }
6931 /* Likewise, error if the ABI requires us to return values in the
6932 x87 registers and the user specified -mno-80387. */
6938 {
6940 {
6943 }
6945 }
6947 /* First construct simple cases. Avoid SCmode, since we want to use
6948 single register to pass this type. */
6951 {
6966 /* Zero sized array, struct or class. */
6970 }
7009 /* Otherwise figure out the entries of the PARALLEL. */
7011 {
7015 {
7020 /* Merge TImodes on aligned occasions here too. */
7022 tmpmode
7026 else
7028 /* We've requested 24 bytes we
7029 don't have mode for. Use DImode. */
7036 intreg++;
7044 sse_regno++;
7052 sse_regno++;
7057 {
7063 {
7065 i++;
7066 }
7067 else
7092 }
7098 sse_regno++;
7102 }
7103 }
7105 /* Empty aligned struct, union or class. */
7113 }
7115 /* Update the data in CUM to advance over an argument of mode MODE
7116 and data type TYPE. (TYPE is null for libcalls where that information
7117 may not be available.) */
7119 static int
7122 HOST_WIDE_INT words)
7123 {
7127 {
7134 /* FALLTHRU */
7146 {
7149 }
7153 /* OImode shouldn't be used directly. */
7162 /* FALLTHRU */
7184 {
7189 {
7192 }
7193 }
7203 {
7208 {
7211 }
7212 }
7214 }
7217 }
7219 static int
7222 {
7225 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7234 {
7240 }
7241 else
7242 {
7247 }
7248 }
7250 static int
7252 HOST_WIDE_INT words)
7253 {
7254 /* Otherwise, this should be passed indirect. */
7259 {
7263 }
7265 }
7267 /* Update the data in CUM to advance over an argument of mode MODE and
7268 data type TYPE. (TYPE is null for libcalls where that information
7269 may not be available.) */
7271 static void
7274 {
7281 else
7290 {
7291 /* If we pass bounds in BT then just update remained bounds count. */
7293 {
7296 }
7298 /* Update remained number of bounds to force. */
7305 }
7307 /* The first arg not going to Bounds Tables resets this counter. */
7309 /* For unnamed args we always pass bounds to avoid bounds mess when
7310 passed and received types do not match. If bounds do not follow
7311 unnamed arg, still pretend required number of bounds were passed. */
7313 {
7316 }
7322 else
7325 /* For stdarg we expect bounds to be passed for each value passed
7326 in register. */
7329 /* For pointers passed in memory we expect bounds passed in Bounds
7330 Table. */
7333 }
7335 /* Define where to put the arguments to a function.
7336 Value is zero to push the argument on the stack,
7337 or a hard register in which to store the argument.
7339 MODE is the argument's machine mode.
7340 TYPE is the data type of the argument (as a tree).
7341 This is null for libcalls where that information may
7342 not be available.
7343 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7344 the preceding args and about the function being called.
7345 NAMED is nonzero if this argument is a named parameter
7346 (otherwise it is an extra parameter matching an ellipsis). */
7348 static rtx
7352 {
7353 /* Avoid the AL settings for the Unix64 ABI. */
7358 {
7365 /* FALLTHRU */
7371 {
7374 /* Fastcall allocates the first two DWORD (SImode) or
7375 smaller arguments to ECX and EDX if it isn't an
7376 aggregate type . */
7378 {
7384 /* ECX not EAX is the first allocated register. */
7387 }
7389 }
7398 /* FALLTHRU */
7400 /* In 32bit, we pass TImode in xmm registers. */
7408 {
7412 }
7417 /* OImode and XImode shouldn't be used directly. */
7433 {
7437 }
7447 {
7451 }
7453 }
7456 }
7458 static rtx
7461 {
7462 /* Handle a hidden AL argument containing number of registers
7463 for varargs x86-64 functions. */
7467 ? X86_64_SSE_REGPARM_MAX
7472 {
7488 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7492 }
7498 }
7500 static rtx
7503 HOST_WIDE_INT bytes)
7504 {
7507 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7508 We use value of -2 to specify that current function call is MSABI. */
7512 /* If we've run out of registers, it goes on the stack. */
7518 /* Only floating point modes are passed in anything but integer regs. */
7520 {
7523 else
7524 {
7527 /* Unnamed floating parameters are passed in both the
7528 SSE and integer registers. */
7534 }
7535 }
7536 /* Handle aggregated types passed in register. */
7538 {
7543 }
7546 }
7548 /* Return where to put the arguments to a function.
7549 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7551 MODE is the argument's machine mode. TYPE is the data type of the
7552 argument. It is null for libcalls where that information may not be
7553 available. CUM gives information about the preceding args and about
7554 the function being called. NAMED is nonzero if this argument is a
7555 named parameter (otherwise it is an extra parameter matching an
7556 ellipsis). */
7558 static rtx
7561 {
7565 rtx arg;
7569 else
7576 {
7581 else
7583 }
7584 else
7585 {
7586 /* To simplify the code below, represent vector types with a vector mode
7587 even if MMX/SSE are not active. */
7595 else
7597 }
7600 }
7602 /* A C expression that indicates when an argument must be passed by
7603 reference. If nonzero for an argument, a copy of that argument is
7604 made in memory and a pointer to the argument is passed instead of
7605 the argument itself. The pointer is passed in whatever way is
7606 appropriate for passing a pointer to that type. */
7608 static bool
7611 {
7614 /* See Windows x64 Software Convention. */
7616 {
7619 {
7620 /* Arrays are passed by reference. */
7625 {
7626 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7627 are passed by reference. */
7629 }
7630 }
7632 /* __m128 is passed by reference. */
7638 }
7639 }
7644 }
7646 /* Return true when TYPE should be 128bit aligned for 32bit argument
7647 passing ABI. XXX: This function is obsolete and is only used for
7648 checking psABI compatibility with previous versions of GCC. */
7650 static bool
7652 {
7664 {
7665 /* Walk the aggregates recursively. */
7667 {
7671 {
7672 tree field;
7674 /* Walk all the structure fields. */
7676 {
7680 }
7682 }
7685 /* Just for use if some languages passes arrays by value. */
7692 }
7693 }
7695 }
7697 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7698 XXX: This function is obsolete and is only used for checking psABI
7699 compatibility with previous versions of GCC. */
7701 static unsigned int
7704 {
7705 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7706 natural boundaries. */
7708 {
7709 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7710 make an exception for SSE modes since these require 128bit
7711 alignment.
7713 The handling here differs from field_alignment. ICC aligns MMX
7714 arguments to 4 byte boundaries, while structure fields are aligned
7715 to 8 byte boundaries. */
7717 {
7720 }
7721 else
7722 {
7725 }
7726 }
7730 }
7732 /* Return true when TYPE should be 128bit aligned for 32bit argument
7733 passing ABI. */
7735 static bool
7737 {
7747 {
7748 /* Walk the aggregates recursively. */
7750 {
7754 {
7755 tree field;
7757 /* Walk all the structure fields. */
7759 field;
7761 {
7765 }
7767 }
7770 /* Just for use if some languages passes arrays by value. */
7777 }
7778 }
7779 else
7783 }
7785 /* Gives the alignment boundary, in bits, of an argument with the
7786 specified mode and type. */
7788 static unsigned int
7790 {
7793 {
7794 /* Since the main variant type is used for call, we convert it to
7795 the main variant type. */
7798 }
7799 else
7803 else
7804 {
7809 {
7810 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7812 {
7815 }
7821 }
7824 && !warned
7826 saved_align))
7827 {
7830 "The ABI for passing parameters with %d-byte"
7833 }
7834 }
7837 }
7839 /* Return true if N is a possible register number of function value. */
7841 static bool
7843 {
7845 {
7856 /* Complex values are returned in %st(0)/%st(1) pair. */
7859 /* TODO: The function should depend on current function ABI but
7860 builtins.c would need updating then. Therefore we use the
7861 default ABI. */
7866 /* Complex values are returned in %xmm0/%xmm1 pair. */
7875 }
7878 }
7880 /* Define how to find the value returned by a function.
7881 VALTYPE is the data type of the value (as a tree).
7882 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7883 otherwise, FUNC is 0. */
7885 static rtx
7888 {
7891 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7892 we normally prevent this case when mmx is not available. However
7893 some ABIs may require the result to be returned like DImode. */
7897 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7898 we prevent this case when sse is not available. However some ABIs
7899 may require the result to be returned like integer TImode. */
7904 /* 32-byte vector modes in %ymm0. */
7908 /* 64-byte vector modes in %zmm0. */
7912 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7915 else
7916 /* Most things go in %eax. */
7919 /* Override FP return register with %xmm0 for local functions when
7920 SSE math is enabled or for functions with sseregparm attribute. */
7922 {
7927 }
7929 /* OImode shouldn't be used directly. */
7933 }
7935 static rtx
7937 const_tree valtype)
7938 {
7939 rtx ret;
7941 /* Handle libcalls, which don't provide a type node. */
7943 {
7947 {
7966 }
7969 }
7971 {
7972 /* Pointers are always returned in word_mode. */
7974 }
7980 /* For zero sized structures, construct_container returns NULL, but we
7981 need to keep rest of compiler happy by returning meaningful value. */
7986 }
7988 static rtx
7990 const_tree valtype)
7991 {
7995 {
7997 {
8016 }
8017 }
8019 }
8021 static rtx
8024 {
8039 else
8041 }
8043 static rtx
8046 {
8052 }
8054 static rtx
8056 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8058 {
8064 {
8067 bitmap_iterator bi;
8071 {
8076 }
8080 }
8081 else
8085 }
8087 /* Pointer function arguments and return values are promoted to
8088 word_mode. */
8090 static enum machine_mode
8094 {
8096 {
8099 }
8101 for_return);
8102 }
8104 /* Return true if a structure, union or array with MODE containing FIELD
8105 should be accessed using BLKmode. */
8107 static bool
8109 {
8110 /* Union with XFmode must be in BLKmode. */
8114 }
8116 rtx
8118 {
8120 }
8122 /* Return true iff type is returned in memory. */
8124 static bool ATTRIBUTE_UNUSED
8126 {
8127 HOST_WIDE_INT size;
8138 {
8139 /* User-created vectors small enough to fit in EAX. */
8143 /* MMX/3dNow values are returned in MM0,
8144 except when it doesn't exits or the ABI prescribes otherwise. */
8148 /* SSE values are returned in XMM0, except when it doesn't exist. */
8152 /* AVX values are returned in YMM0, except when it doesn't exist. */
8156 /* AVX512F values are returned in ZMM0, except when it doesn't exist. */
8159 }
8167 /* OImode shouldn't be used directly. */
8171 }
8173 static bool ATTRIBUTE_UNUSED
8175 {
8178 }
8180 static bool ATTRIBUTE_UNUSED
8182 {
8185 /* __m128 is returned in xmm0. */
8192 /* Otherwise, the size must be exactly in [1248]. */
8194 }
8196 static bool
8198 {
8199 #ifdef SUBTARGET_RETURN_IN_MEMORY
8201 #else
8208 {
8211 else
8213 }
8214 else
8216 #endif
8217 }
8219 \f
8220 /* Create the va_list data type. */
8222 /* Returns the calling convention specific va_list date type.
8223 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8225 static tree
8227 {
8230 /* For i386 we use plain pointer to argument area. */
8240 unsigned_type_node);
8243 unsigned_type_node);
8246 ptr_type_node);
8249 ptr_type_node);
8268 /* The correct type is an array type of one element. */
8270 }
8272 /* Setup the builtin va_list data type and for 64-bit the additional
8273 calling convention specific va_list data types. */
8275 static tree
8277 {
8280 /* Initialize abi specific va_list builtin types. */
8282 {
8283 tree t;
8285 {
8290 }
8291 else
8292 {
8297 }
8299 {
8304 }
8305 else
8306 {
8311 }
8312 }
8315 }
8317 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8319 static void
8321 {
8323 alias_set_type set;
8326 /* GPR size of varargs save area. */
8329 else
8332 /* FPR size of varargs save area. We don't need it if we don't pass
8333 anything in SSE registers. */
8336 else
8350 {
8358 }
8361 {
8365 /* Now emit code to save SSE registers. The AX parameter contains number
8366 of SSE parameter registers used to call this function, though all we
8367 actually check here is the zero/non-zero status. */
8372 label));
8374 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8375 we used movdqa (i.e. TImode) instead? Perhaps even better would
8376 be if we could determine the real mode of the data, via a hook
8377 into pass_stdarg. Ignore all that for now. */
8387 {
8396 }
8399 }
8400 }
8402 static void
8404 {
8408 /* Reset to zero, as there might be a sysv vaarg used
8409 before. */
8414 {
8425 }
8426 }
8428 static void
8432 {
8434 CUMULATIVE_ARGS next_cum;
8435 tree fntype;
8437 /* This argument doesn't appear to be used anymore. Which is good,
8438 because the old code here didn't suppress rtl generation. */
8446 /* For varargs, we do not want to skip the dummy va_dcl argument.
8447 For stdargs, we do want to skip the last named argument. */
8455 else
8457 }
8459 static void
8462 tree type,
8465 {
8467 CUMULATIVE_ARGS next_cum;
8468 tree fntype;
8469 rtx save_area;
8479 /* For varargs, we do not want to skip the dummy va_dcl argument.
8480 For stdargs, we do want to skip the last named argument. */
8497 {
8502 rtx bounds;
8506 else
8507 {
8514 }
8520 bnd_reg++;
8521 }
8522 }
8525 /* Checks if TYPE is of kind va_list char *. */
8527 static bool
8529 {
8530 tree canonic;
8532 /* For 32-bit it is always true. */
8538 }
8540 /* Implement va_start. */
8542 static void
8544 {
8548 tree type;
8549 rtx ovf_rtx;
8553 {
8556 /* When we are splitting the stack, we can't refer to the stack
8557 arguments using internal_arg_pointer, because they may be on
8558 the old stack. The split stack prologue will arrange to
8559 leave a pointer to the old stack arguments in a scratch
8560 register, which we here copy to a pseudo-register. The split
8561 stack prologue can't set the pseudo-register directly because
8562 it (the prologue) runs before any registers have been saved. */
8566 {
8580 }
8581 }
8583 /* Only 64bit target needs something special. */
8585 {
8588 else
8589 {
8599 /* Store zero bounds for va_list. */
8603 next));
8605 }
8607 }
8616 /* The following should be folded into the MEM_REF offset. */
8626 /* Count number of gp and fp argument registers used. */
8632 {
8638 }
8641 {
8647 }
8649 /* Find the overflow area. */
8653 else
8663 /* Store zero bounds for overflow area pointer. */
8668 {
8669 /* Find the register save area.
8670 Prologue of the function save it right above stack frame. */
8680 /* Store zero bounds for save area pointer. */
8683 }
8684 }
8686 /* Implement va_arg. */
8688 static tree
8691 {
8698 rtx container;
8700 tree ptrtype;
8704 /* Only 64bit target needs something special. */
8728 {
8741 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
8743 {
8746 }
8754 }
8756 /* Pull the value out of the saved registers. */
8761 {
8775 /* In case we are passing structure, verify that it is consecutive block
8776 on the register save area. If not we need to do moves. */
8778 {
8779 /* Verify that all registers are strictly consecutive */
8781 {
8785 {
8790 }
8791 }
8792 else
8793 {
8797 {
8802 }
8803 }
8804 }
8806 {
8809 }
8810 else
8811 {
8814 }
8816 /* First ensure that we fit completely in registers. */
8818 {
8825 }
8827 {
8835 }
8837 /* Compute index to start of area used for integer regs. */
8839 {
8840 /* int_addr = gpr + sav; */
8843 }
8845 {
8846 /* sse_addr = fpr + sav; */
8849 }
8851 {
8855 /* addr = &temp; */
8860 {
8864 tree piece_type;
8865 tree addr_type;
8866 tree daddr_type;
8875 {
8880 }
8884 else
8891 {
8894 }
8895 else
8896 {
8899 }
8906 {
8911 }
8912 else
8913 {
8914 tree copy
8919 }
8921 }
8922 }
8925 {
8929 }
8932 {
8936 }
8941 }
8943 /* ... otherwise out of the overflow area. */
8945 /* When we align parameter on stack for caller, if the parameter
8946 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8947 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8948 here with caller. */
8953 /* Care for on-stack alignment if needed. */
8956 else
8957 {
8962 }
8979 }
8980 \f
8981 /* Return true if OPNUM's MEM should be matched
8982 in movabs* patterns. */
8984 bool
8986 {
8998 }
8999 \f
9000 /* Initialize the table of extra 80387 mathematical constants. */
9002 static void
9004 {
9006 {
9012 };
9016 {
9018 /* Ensure each constant is rounded to XFmode precision. */
9021 }
9024 }
9026 /* Return non-zero if the constant is something that
9027 can be loaded with a special instruction. */
9029 int
9031 {
9034 REAL_VALUE_TYPE r;
9046 /* For XFmode constants, try to find a special 80387 instruction when
9047 optimizing for size or on those CPUs that benefit from them. */
9050 {
9059 }
9061 /* Load of the constant -0.0 or -1.0 will be split as
9062 fldz;fchs or fld1;fchs sequence. */
9069 }
9071 /* Return the opcode of the special instruction to be used to load
9072 the constant X. */
9076 {
9078 {
9098 }
9099 }
9101 /* Return the CONST_DOUBLE representing the 80387 constant that is
9102 loaded by the specified special instruction. The argument IDX
9103 matches the return value from standard_80387_constant_p. */
9105 rtx
9107 {
9114 {
9125 }
9128 XFmode);
9129 }
9131 /* Return 1 if X is all 0s and 2 if x is all 1s
9132 in supported SSE/AVX vector mode. */
9134 int
9136 {
9143 {
9164 }
9167 }
9169 /* Return the opcode of the special instruction to be used to load
9170 the constant X. */
9174 {
9176 {
9179 {
9201 }
9210 else
9215 }
9217 }
9219 /* Returns true if OP contains a symbol reference */
9221 bool
9223 {
9232 {
9234 {
9240 }
9244 }
9247 }
9249 /* Return true if it is appropriate to emit `ret' instructions in the
9250 body of a function. Do this only if the epilogue is simple, needing a
9251 couple of insns. Prior to reloading, we can't tell how many registers
9252 must be saved, so return false then. Return false if there is no frame
9253 marker to de-allocate. */
9255 bool
9257 {
9263 /* Don't allow more than 32k pop, since that's all we can do
9264 with one instruction. */
9271 }
9272 \f
9273 /* Value should be nonzero if functions must have frame pointers.
9274 Zero means the frame pointer need not be set up (and parms may
9275 be accessed via the stack pointer) in functions that seem suitable. */
9277 static bool
9279 {
9280 /* If we accessed previous frames, then the generated code expects
9281 to be able to access the saved ebp value in our frame. */
9285 /* Several x86 os'es need a frame pointer for other reasons,
9286 usually pertaining to setjmp. */
9290 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9294 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9295 allocation is 4GB. */
9299 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9300 turns off the frame pointer by default. Turn it back on now if
9301 we've not got a leaf function. */
9311 }
9313 /* Record that the current function accesses previous call frames. */
9315 void
9317 {
9319 }
9320 \f
9321 #ifndef USE_HIDDEN_LINKONCE
9322 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9323 # define USE_HIDDEN_LINKONCE 1
9324 # else
9325 # define USE_HIDDEN_LINKONCE 0
9326 # endif
9327 #endif
9331 /* Fills in the label name that should be used for a pc thunk for
9332 the given register. */
9334 static void
9336 {
9341 else
9343 }
9346 /* This function generates code for -fpic that loads %ebx with
9347 the return address of the caller and then returns. */
9349 static void
9351 {
9356 {
9358 tree decl;
9374 #if TARGET_MACHO
9376 {
9385 }
9386 else
9387 #endif
9389 {
9400 }
9401 else
9402 {
9405 }
9411 /* Make sure unwind info is emitted for the thunk if needed. */
9414 /* Pad stack IP move with 4 instructions (two NOPs count
9415 as one instruction). */
9417 {
9422 }
9433 }
9437 }
9439 /* Emit code for the SET_GOT patterns. */
9443 {
9449 {
9450 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9455 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9456 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9457 an unadorned address. */
9462 }
9467 {
9469 /* We don't need a pic base, we're not producing pic. */
9476 }
9477 else
9478 {
9487 #if TARGET_MACHO
9488 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9489 This is what will be referenced by the Mach-O PIC subsystem. */
9493 /* When we are restoring the pic base at the site of a nonlocal label,
9494 and we decided to emit the pic base above, we will still output a
9495 local label used for calculating the correction offset (even though
9496 the offset will be 0 in that case). */
9500 #endif
9501 }
9507 }
9509 /* Generate an "push" pattern for input ARG. */
9511 static rtx
9513 {
9526 stack_pointer_rtx)),
9527 arg);
9528 }
9530 /* Generate an "pop" pattern for input ARG. */
9532 static rtx
9534 {
9539 arg,
9542 stack_pointer_rtx)));
9543 }
9545 /* Return >= 0 if there is an unused call-clobbered register available
9546 for the entire function. */
9548 static unsigned int
9550 {
9554 {
9556 /* Can't use the same register for both PIC and DRAP. */
9559 else
9564 }
9567 }
9569 /* Return TRUE if we need to save REGNO. */
9571 static bool
9573 {
9584 {
9587 {
9593 }
9594 }
9605 }
9607 /* Return number of saved general prupose registers. */
9609 static int
9611 {
9617 nregs ++;
9619 }
9621 /* Return number of saved SSE registrers. */
9623 static int
9625 {
9633 nregs ++;
9635 }
9637 /* Given FROM and TO register numbers, say whether this elimination is
9638 allowed. If stack alignment is needed, we can only replace argument
9639 pointer with hard frame pointer, or replace frame pointer with stack
9640 pointer. Otherwise, frame pointer elimination is automatically
9641 handled and all other eliminations are valid. */
9643 static bool
9645 {
9651 else
9653 }
9655 /* Return the offset between two registers, one to be eliminated, and the other
9656 its replacement, at the start of a routine. */
9658 HOST_WIDE_INT
9660 {
9669 else
9670 {
9678 }
9679 }
9681 /* In a dynamically-aligned function, we can't know the offset from
9682 stack pointer to frame pointer, so we must ensure that setjmp
9683 eliminates fp against the hard fp (%ebp) rather than trying to
9684 index from %esp up to the top of the frame across a gap that is
9685 of unknown (at compile-time) size. */
9686 static rtx
9688 {
9690 }
9692 /* When using -fsplit-stack, the allocation routines set a field in
9693 the TCB to the bottom of the stack plus this much space, measured
9694 in bytes. */
9696 #define SPLIT_STACK_AVAILABLE 256
9698 /* Fill structure ix86_frame about frame of currently computed function. */
9700 static void
9702 {
9704 HOST_WIDE_INT offset;
9707 HOST_WIDE_INT to_allocate;
9715 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
9716 function prologues and leaf. */
9720 {
9725 }
9731 /* For SEH we have to limit the amount of code movement into the prologue.
9732 At present we do this via a BLOCKAGE, at which point there's very little
9733 scheduling that can be done, which means that there's very little point
9734 in doing anything except PUSHs. */
9738 /* During reload iteration the amount of registers saved can change.
9739 Recompute the value as needed. Do not recompute when amount of registers
9740 didn't change as reload does multiple calls to the function and does not
9741 expect the decision to change within single iteration. */
9744 {
9750 /* The fast prologue uses move instead of push to save registers. This
9751 is significantly longer, but also executes faster as modern hardware
9752 can execute the moves in parallel, but can't do that for push/pop.
9754 Be careful about choosing what prologue to emit: When function takes
9755 many instructions to execute we may use slow version as well as in
9756 case function is known to be outside hot spot (this is known with
9757 feedback only). Weight the size of function by number of registers
9758 to save as it is cheap to use one or two push instructions but very
9759 slow to use many of them. */
9763 || (flag_branch_probabilities
9766 else
9769 }
9771 frame->save_regs_using_mov
9773 /* If static stack checking is enabled and done with probes,
9774 the registers need to be saved before allocating the frame. */
9777 /* Skip return address. */
9780 /* Skip pushed static chain. */
9784 /* Skip saved base pointer. */
9789 /* The traditional frame pointer location is at the top of the frame. */
9792 /* Register save area */
9796 /* On SEH target, registers are pushed just before the frame pointer
9797 location. */
9801 /* Align and set SSE register save area. */
9803 {
9804 /* The only ABI that has saved SSE registers (Win64) also has a
9805 16-byte aligned default stack, and thus we don't need to be
9806 within the re-aligned local stack frame to save them. */
9810 }
9813 /* The re-aligned stack starts here. Values before this point are not
9814 directly comparable with values below this point. In order to make
9815 sure that no value happens to be the same before and after, force
9816 the alignment computation below to add a non-zero value. */
9820 /* Va-arg area */
9824 /* Align start of frame for local function. */
9833 /* Frame pointer points here. */
9838 /* Add outgoing arguments area. Can be skipped if we eliminated
9839 all the function calls as dead code.
9840 Skipping is however impossible when function calls alloca. Alloca
9841 expander assumes that last crtl->outgoing_args_size
9842 of stack frame are unused. */
9846 {
9849 }
9850 else
9853 /* Align stack boundary. Only needed if we're calling another function
9854 or using alloca. */
9859 /* We've reached end of stack frame. */
9862 /* Size prologue needs to allocate. */
9873 {
9879 }
9880 else
9884 /* The SEH frame pointer location is near the bottom of the frame.
9885 This is enforced by the fact that the difference between the
9886 stack pointer and the frame pointer is limited to 240 bytes in
9887 the unwind data structure. */
9889 {
9890 HOST_WIDE_INT diff;
9892 /* If we can leave the frame pointer where it is, do so. Also, returns
9893 the establisher frame for __builtin_frame_address (0). */
9898 {
9899 /* Ideally we'd determine what portion of the local stack frame
9900 (within the constraint of the lowest 240) is most heavily used.
9901 But without that complication, simply bias the frame pointer
9902 by 128 bytes so as to maximize the amount of the local stack
9903 frame that is addressable with 8-bit offsets. */
9905 }
9906 }
9907 }
9909 /* This is semi-inlined memory_address_length, but simplified
9910 since we know that we're always dealing with reg+offset, and
9911 to avoid having to create and discard all that rtl. */
9915 {
9919 {
9920 /* EBP and R13 cannot be encoded without an offset. */
9922 }
9926 /* ESP and R12 must be encoded with a SIB byte. */
9928 len++;
9931 }
9933 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9934 The valid base registers are taken from CFUN->MACHINE->FS. */
9936 static rtx
9938 {
9944 {
9945 /* Choose the base register most likely to allow the most scheduling
9946 opportunities. Generally FP is valid throughout the function,
9947 while DRAP must be reloaded within the epilogue. But choose either
9948 over the SP due to increased encoding size. */
9951 {
9954 }
9956 {
9959 }
9961 {
9964 }
9965 }
9966 else
9967 {
9968 HOST_WIDE_INT toffset;
9971 /* Choose the base register with the smallest address encoding.
9972 With a tie, choose FP > DRAP > SP. */
9974 {
9978 }
9980 {
9984 {
9988 }
9989 }
9991 {
9995 {
9999 }
10000 }
10001 }
10005 }
10007 /* Emit code to save registers in the prologue. */
10009 static void
10011 {
10013 rtx insn;
10017 {
10020 }
10021 }
10023 /* Emit a single register save at CFA - CFA_OFFSET. */
10025 static void
10027 HOST_WIDE_INT cfa_offset)
10028 {
10036 /* For SSE saves, we need to indicate the 128-bit alignment. */
10047 /* When saving registers into a re-aligned local stack frame, avoid
10048 any tricky guessing by dwarf2out. */
10050 {
10054 {
10055 /* A bit of a hack. We force the DRAP register to be saved in
10056 the re-aligned stack frame, which provides us with a copy
10057 of the CFA that will last past the prologue. Install it. */
10063 }
10064 else
10065 {
10066 /* The frame pointer is a stable reference within the
10067 aligned frame. Use it. */
10074 }
10075 }
10077 /* The memory may not be relative to the current CFA register,
10078 which means that we may need to generate a new pattern for
10079 use by the unwind info. */
10081 {
10086 }
10087 }
10089 /* Emit code to save registers using MOV insns.
10090 First register is stored at CFA - CFA_OFFSET. */
10091 static void
10093 {
10098 {
10101 }
10102 }
10104 /* Emit code to save SSE registers using MOV insns.
10105 First register is stored at CFA - CFA_OFFSET. */
10106 static void
10108 {
10113 {
10116 }
10117 }
10121 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10122 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10123 Don't add the note if the previously saved value will be left untouched
10124 within stack red-zone till return, as unwinders can find the same value
10125 in the register and on the stack. */
10127 static void
10129 {
10135 {
10138 }
10139 else
10140 queued_cfa_restores
10142 }
10144 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10146 static void
10148 {
10149 rtx last;
10153 ;
10158 }
10160 /* Expand prologue or epilogue stack adjustment.
10161 The pattern exist to put a dependency on all ebp-based memory accesses.
10162 STYLE should be negative if instructions should be marked as frame related,
10163 zero if %r11 register is live and cannot be freely used and positive
10164 otherwise. */
10166 static void
10169 {
10171 rtx insn;
10178 else
10179 {
10180 rtx tmp;
10181 /* r11 is used by indirect sibcall return as well, set before the
10182 epilogue and used after the epilogue. */
10185 else
10186 {
10190 }
10196 }
10203 {
10204 rtx r;
10214 }
10216 {
10219 {
10223 }
10224 }
10227 {
10232 {
10235 }
10237 {
10240 }
10241 else
10242 {
10243 /* Else there are two possibilities: SP itself, which we set
10244 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10245 taken care of this by hand along the eh_return path. */
10248 }
10252 }
10253 }
10255 /* Find an available register to be used as dynamic realign argument
10256 pointer regsiter. Such a register will be written in prologue and
10257 used in begin of body, so it must not be
10258 1. parameter passing register.
10259 2. GOT pointer.
10260 We reuse static-chain register if it is available. Otherwise, we
10261 use DI for i386 and R13 for x86-64. We chose R13 since it has
10262 shorter encoding.
10264 Return: the regno of chosen register. */
10266 static unsigned int
10268 {
10272 {
10273 /* Use R13 for nested function or function need static chain.
10274 Since function with tail call may use any caller-saved
10275 registers in epilogue, DRAP must not use caller-saved
10276 register in such case. */
10281 }
10282 else
10283 {
10284 /* Use DI for nested function or function need static chain.
10285 Since function with tail call may use any caller-saved
10286 registers in epilogue, DRAP must not use caller-saved
10287 register in such case. */
10291 /* Reuse static chain register if it isn't used for parameter
10292 passing. */
10294 {
10298 }
10300 }
10301 }
10303 /* Return minimum incoming stack alignment. */
10305 static unsigned int
10307 {
10310 /* Prefer the one specified at command line. */
10313 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10314 if -mstackrealign is used, it isn't used for sibcall check and
10315 estimated stack alignment is 128bit. */
10317 && !TARGET_64BIT
10318 && ix86_force_align_arg_pointer
10321 else
10324 /* Incoming stack alignment can be changed on individual functions
10325 via force_align_arg_pointer attribute. We use the smallest
10326 incoming stack boundary. */
10332 /* The incoming stack frame has to be aligned at least at
10333 parm_stack_boundary. */
10337 /* Stack at entrance of main is aligned by runtime. We use the
10338 smallest incoming stack boundary. */
10346 }
10348 /* Update incoming stack boundary and estimated stack alignment. */
10350 static void
10352 {
10353 ix86_incoming_stack_boundary
10356 /* x86_64 vararg needs 16byte stack alignment for register save
10357 area. */
10362 }
10364 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10365 needed or an rtx for DRAP otherwise. */
10367 static rtx
10369 {
10374 {
10375 /* Assign DRAP to vDRAP and returns vDRAP */
10377 rtx drap_vreg;
10378 rtx arg_ptr;
10391 {
10394 }
10396 }
10397 else
10399 }
10401 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10403 static rtx
10405 {
10407 }
10410 rtx reg;
10412 };
10414 /* Return a short-lived scratch register for use on function entry.
10415 In 32-bit mode, it is valid only after the registers are saved
10416 in the prologue. This register must be released by means of
10417 release_scratch_register_on_entry once it is dead. */
10419 static void
10421 {
10427 {
10428 /* We always use R11 in 64-bit mode. */
10430 }
10431 else
10432 {
10434 bool fastcall_p
10436 bool thiscall_p
10440 int drap_regno
10443 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10444 for the static chain register. */
10448 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10449 for the static chain register. */
10454 /* ecx is the static chain register. */
10456 && !static_chain_p
10461 /* esi is the static chain register. */
10467 else
10468 {
10471 }
10472 }
10476 {
10479 }
10480 }
10482 /* Release a scratch register obtained from the preceding function. */
10484 static void
10486 {
10488 {
10492 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10498 }
10499 }
10501 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10503 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10505 static void
10507 {
10508 /* We skip the probe for the first interval + a small dope of 4 words and
10509 probe that many bytes past the specified size to maintain a protection
10510 area at the botton of the stack. */
10514 /* See if we have a constant small number of probes to generate. If so,
10515 that's the easy case. The run-time loop is made up of 11 insns in the
10516 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10517 for n # of intervals. */
10519 {
10523 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10524 values of N from 1 until it exceeds SIZE. If only one probe is
10525 needed, this will not generate any code. Then adjust and probe
10526 to PROBE_INTERVAL + SIZE. */
10528 {
10530 {
10533 }
10534 else
10541 }
10545 else
10553 /* Adjust back to account for the additional first interval. */
10557 }
10559 /* Otherwise, do the same as above, but in a loop. Note that we must be
10560 extra careful with variables wrapping around because we might be at
10561 the very top (or the very bottom) of the address space and we have
10562 to be able to handle this case properly; in particular, we use an
10563 equality test for the loop condition. */
10564 else
10565 {
10566 HOST_WIDE_INT rounded_size;
10572 /* Step 1: round SIZE to the previous multiple of the interval. */
10577 /* Step 2: compute initial and final value of the loop counter. */
10579 /* SP = SP_0 + PROBE_INTERVAL. */
10584 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
10588 stack_pointer_rtx)));
10591 /* Step 3: the loop
10593 while (SP != LAST_ADDR)
10594 {
10595 SP = SP + PROBE_INTERVAL
10596 probe at SP
10597 }
10599 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
10600 values of N from 1 until it is equal to ROUNDED_SIZE. */
10605 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
10606 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
10609 {
10614 }
10616 /* Adjust back to account for the additional first interval. */
10622 }
10626 /* Even if the stack pointer isn't the CFA register, we need to correctly
10627 describe the adjustments made to it, in particular differentiate the
10628 frame-related ones from the frame-unrelated ones. */
10630 {
10643 }
10645 /* Make sure nothing is scheduled before we are done. */
10647 }
10649 /* Adjust the stack pointer up to REG while probing it. */
10653 {
10663 /* Jump to END_LAB if SP == LAST_ADDR. */
10671 /* SP = SP + PROBE_INTERVAL. */
10675 /* Probe at SP. */
10686 }
10688 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10689 inclusive. These are offsets from the current stack pointer. */
10691 static void
10693 {
10694 /* See if we have a constant small number of probes to generate. If so,
10695 that's the easy case. The run-time loop is made up of 7 insns in the
10696 generic case while the compile-time loop is made up of n insns for n #
10697 of intervals. */
10699 {
10700 HOST_WIDE_INT i;
10702 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10703 it exceeds SIZE. If only one probe is needed, this will not
10704 generate any code. Then probe at FIRST + SIZE. */
10711 }
10713 /* Otherwise, do the same as above, but in a loop. Note that we must be
10714 extra careful with variables wrapping around because we might be at
10715 the very top (or the very bottom) of the address space and we have
10716 to be able to handle this case properly; in particular, we use an
10717 equality test for the loop condition. */
10718 else
10719 {
10726 /* Step 1: round SIZE to the previous multiple of the interval. */
10731 /* Step 2: compute initial and final value of the loop counter. */
10733 /* TEST_OFFSET = FIRST. */
10736 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10740 /* Step 3: the loop
10742 while (TEST_ADDR != LAST_ADDR)
10743 {
10744 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10745 probe at TEST_ADDR
10746 }
10748 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10749 until it is equal to ROUNDED_SIZE. */
10754 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10755 that SIZE is equal to ROUNDED_SIZE. */
10760 stack_pointer_rtx,
10765 }
10767 /* Make sure nothing is scheduled before we are done. */
10769 }
10771 /* Probe a range of stack addresses from REG to END, inclusive. These are
10772 offsets from the current stack pointer. */
10776 {
10786 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10794 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10798 /* Probe at TEST_ADDR. */
10811 }
10813 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10814 to be generated in correct form. */
10815 static void
10817 {
10818 /* Check if stack realign is really needed after reload, and
10819 stores result in cfun */
10820 unsigned int incoming_stack_boundary
10829 {
10830 /* After stack_realign_needed is finalized, we can't no longer
10831 change it. */
10834 }
10836 /* If the only reason for frame_pointer_needed is that we conservatively
10837 assumed stack realignment might be needed, but in the end nothing that
10838 needed the stack alignment had been spilled, clear frame_pointer_needed
10839 and say we don't need stack realignment. */
10841 && frame_pointer_needed
10843 && flag_omit_frame_pointer
10845 && !ix86_current_function_calls_tls_descriptor
10854 {
10856 basic_block bb;
10863 HARD_FRAME_POINTER_REGNUM);
10865 {
10866 rtx insn;
10870 set_up_by_prologue))
10871 {
10875 }
10876 }
10878 /* If drap has been set, but it actually isn't live at the start
10879 of the function, there is no reason to set it up. */
10881 {
10884 {
10887 }
10888 }
10889 else
10904 }
10908 }
10910 /* Expand the prologue into a bunch of separate insns. */
10912 void
10914 {
10919 HOST_WIDE_INT allocate;
10925 /* DRAP should not coexist with stack_realign_fp */
10930 /* Initialize CFA state for before the prologue. */
10934 /* Track SP offset to the CFA. We continue tracking this after we've
10935 swapped the CFA register away from SP. In the case of re-alignment
10936 this is fudged; we're interested to offsets within the local frame. */
10943 {
10944 /* We should have already generated an error for any use of
10945 ms_hook on a nested function. */
10948 /* Check if profiling is active and we shall use profiling before
10949 prologue variant. If so sorry. */
10954 /* In ix86_asm_output_function_label we emitted:
10955 8b ff movl.s %edi,%edi
10956 55 push %ebp
10957 8b ec movl.s %esp,%ebp
10959 This matches the hookable function prologue in Win32 API
10960 functions in Microsoft Windows XP Service Pack 2 and newer.
10961 Wine uses this to enable Windows apps to hook the Win32 API
10962 functions provided by Wine.
10964 What that means is that we've already set up the frame pointer. */
10968 {
10971 /* We've decided to use the frame pointer already set up.
10972 Describe this to the unwinder by pretending that both
10973 push and mov insns happen right here.
10975 Putting the unwind info here at the end of the ms_hook
10976 is done so that we can make absolutely certain we get
10977 the required byte sequence at the start of the function,
10978 rather than relying on an assembler that can produce
10979 the exact encoding required.
10981 However it does mean (in the unpatched case) that we have
10982 a 1 insn window where the asynchronous unwind info is
10983 incorrect. However, if we placed the unwind info at
10984 its correct location we would have incorrect unwind info
10985 in the patched case. Which is probably all moot since
10986 I don't expect Wine generates dwarf2 unwind info for the
10987 system libraries that use this feature. */
10993 stack_pointer_rtx);
11001 /* Note that gen_push incremented m->fs.cfa_offset, even
11002 though we didn't emit the push insn here. */
11006 }
11007 else
11008 {
11009 /* The frame pointer is not needed so pop %ebp again.
11010 This leaves us with a pristine state. */
11012 }
11013 }
11015 /* The first insn of a function that accepts its static chain on the
11016 stack is to push the register that would be filled in by a direct
11017 call. This insn will be skipped by the trampoline. */
11019 {
11023 /* We don't want to interpret this push insn as a register save,
11024 only as a stack adjustment. The real copy of the register as
11025 a save will be done later, if needed. */
11030 }
11032 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11033 of DRAP is needed and stack realignment is really needed after reload */
11035 {
11038 /* Only need to push parameter pointer reg if it is caller saved. */
11040 {
11041 /* Push arg pointer reg */
11044 }
11046 /* Grab the argument pointer. */
11053 /* Align the stack. */
11055 stack_pointer_rtx,
11059 /* Replicate the return address on the stack so that return
11060 address can be reached via (argp - 1) slot. This is needed
11061 to implement macro RETURN_ADDR_RTX and intrinsic function
11062 expand_builtin_return_addr etc. */
11068 /* For the purposes of frame and register save area addressing,
11069 we've started over with a new frame. */
11072 }
11078 {
11079 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11080 slower on all targets. Also sdb doesn't like it. */
11084 /* Push registers now, before setting the frame pointer
11085 on SEH target. */
11087 && TARGET_SEH
11089 {
11093 }
11096 {
11104 }
11105 }
11108 {
11109 /* If saving registers via PUSH, do so now. */
11111 {
11115 }
11117 /* When using red zone we may start register saving before allocating
11118 the stack frame saving one cycle of the prologue. However, avoid
11119 doing this if we have to probe the stack; at least on x86_64 the
11120 stack probe can turn into a call that clobbers a red zone location. */
11122 && (! TARGET_STACK_PROBE
11124 {
11127 }
11128 }
11131 {
11135 /* The computation of the size of the re-aligned stack frame means
11136 that we must allocate the size of the register save area before
11137 performing the actual alignment. Otherwise we cannot guarantee
11138 that there's enough storage above the realignment point. */
11145 /* Align the stack. */
11147 stack_pointer_rtx,
11150 /* For the purposes of register save area addressing, the stack
11151 pointer is no longer valid. As for the value of sp_offset,
11152 see ix86_compute_frame_layout, which we need to match in order
11153 to pass verification of stack_pointer_offset at the end. */
11156 }
11161 {
11162 /* We start to count from ARG_POINTER. */
11165 /* If it was realigned, take into account the fake frame. */
11167 {
11174 /* This over-estimates by 1 minimal-stack-alignment-unit but
11175 mitigates that by counting in the new return address slot. */
11176 current_function_dynamic_stack_size
11178 }
11181 }
11183 /* On SEH target with very large frame size, allocate an area to save
11184 SSE registers (as the very large allocation won't be described). */
11188 {
11189 HOST_WIDE_INT sse_size =
11194 /* No need to do stack checking as the area will be immediately
11195 written. */
11202 }
11204 /* The stack has already been decremented by the instruction calling us
11205 so probe if the size is non-negative to preserve the protection area. */
11207 {
11208 /* We expect the registers to be saved when probes are used. */
11212 {
11215 {
11218 }
11219 }
11220 else
11221 {
11228 {
11230 {
11233 }
11234 else
11236 }
11237 else
11238 {
11240 {
11244 }
11245 else
11247 }
11248 }
11249 }
11252 ;
11255 {
11259 }
11260 else
11261 {
11273 {
11276 /* Note that SEH directives need to continue tracking the stack
11277 pointer even after the frame pointer has been set up. */
11279 {
11283 }
11284 }
11287 {
11292 {
11296 }
11297 }
11302 /* Use the fact that AX still contains ALLOCATE. */
11304 ? gen_pro_epilogue_adjust_stack_di_sub
11311 {
11319 }
11322 /* Use stack_pointer_rtx for relative addressing so that code
11323 works for realigned stack, too. */
11325 {
11332 }
11334 {
11339 }
11340 }
11343 /* If we havn't already set up the frame pointer, do so now. */
11345 {
11357 }
11365 /* We don't use pic-register for pe-coff target. */
11367 && !TARGET_PECOFF
11370 {
11377 }
11380 {
11382 {
11384 {
11394 label));
11398 }
11399 else
11401 }
11402 else
11403 {
11407 }
11408 }
11410 /* In the pic_reg_used case, make sure that the got load isn't deleted
11411 when mcount needs it. Blockage to avoid call movement across mcount
11412 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
11413 note. */
11418 {
11419 /* vDRAP is setup but after reload it turns out stack realign
11420 isn't necessary, here we will emit prologue to setup DRAP
11421 without stack realign adjustment */
11424 }
11426 /* Prevent instructions from being scheduled into register save push
11427 sequence when access to the redzone area is done through frame pointer.
11428 The offset between the frame pointer and the stack pointer is calculated
11429 relative to the value of the stack pointer at the end of the function
11430 prologue, and moving instructions that access redzone area via frame
11431 pointer inside push sequence violates this assumption. */
11435 /* Emit cld instruction if stringops are used in the function. */
11439 /* SEH requires that the prologue end within 256 bytes of the start of
11440 the function. Prevent instruction schedules that would extend that.
11441 Further, prevent alloca modifications to the stack pointer from being
11442 combined with prologue modifications. */
11445 }
11447 /* Emit code to restore REG using a POP insn. */
11449 static void
11451 {
11460 {
11461 /* Previously we'd represented the CFA as an expression
11462 like *(%ebp - 8). We've just popped that value from
11463 the stack, which means we need to reset the CFA to
11464 the drap register. This will remain until we restore
11465 the stack pointer. */
11469 /* This means that the DRAP register is valid for addressing too. */
11472 }
11475 {
11482 }
11484 /* When the frame pointer is the CFA, and we pop it, we are
11485 swapping back to the stack pointer as the CFA. This happens
11486 for stack frames that don't allocate other data, so we assume
11487 the stack pointer is now pointing at the return address, i.e.
11488 the function entry state, which makes the offset be 1 word. */
11490 {
11493 {
11501 }
11502 }
11503 }
11505 /* Emit code to restore saved registers using POP insns. */
11507 static void
11509 {
11515 }
11517 /* Emit code and notes for the LEAVE instruction. */
11519 static void
11521 {
11533 {
11541 }
11544 }
11546 /* Emit code to restore saved registers using MOV insns.
11547 First register is restored from CFA - CFA_OFFSET. */
11548 static void
11551 {
11557 {
11566 {
11567 /* Previously we'd represented the CFA as an expression
11568 like *(%ebp - 8). We've just popped that value from
11569 the stack, which means we need to reset the CFA to
11570 the drap register. This will remain until we restore
11571 the stack pointer. */
11575 /* This means that the DRAP register is valid for addressing. */
11577 }
11578 else
11582 }
11583 }
11585 /* Emit code to restore saved registers using MOV insns.
11586 First register is restored from CFA - CFA_OFFSET. */
11587 static void
11590 {
11595 {
11597 rtx mem;
11607 }
11608 }
11610 /* Restore function stack, frame, and registers. */
11612 void
11614 {
11630 /* The FP must be valid if the frame pointer is present. */
11635 /* We must have *some* valid pointer to the stack frame. */
11638 /* The DRAP is never valid at this point. */
11641 /* See the comment about red zone and frame
11642 pointer usage in ix86_expand_prologue. */
11649 /* Determine the CFA offset of the end of the red-zone. */
11652 {
11653 /* The red-zone begins below the return address. */
11656 /* When the register save area is in the aligned portion of
11657 the stack, determine the maximum runtime displacement that
11658 matches up with the aligned frame. */
11662 }
11664 /* Special care must be taken for the normal return case of a function
11665 using eh_return: the eax and edx registers are marked as saved, but
11666 not restored along this path. Adjust the save location to match. */
11670 /* EH_RETURN requires the use of moves to function properly. */
11673 /* SEH requires the use of pops to identify the epilogue. */
11676 /* If we're only restoring one register and sp is not valid then
11677 using a move instruction to restore the register since it's
11678 less work than reloading sp and popping the register. */
11691 && TARGET_USE_LEAVE
11695 else
11699 {
11700 /* Ensure that the entire register save area is addressable via
11701 the stack pointer, if we will restore via sp. */
11706 {
11710 style,
11712 }
11713 }
11715 /* If there are any SSE registers to restore, then we have to do it
11716 via moves, since there's obviously no pop for SSE regs. */
11722 {
11723 rtx t;
11728 /* eh_return epilogues need %ecx added to the stack pointer. */
11730 {
11733 /* Stack align doesn't work with eh_return. */
11735 /* Neither does regparm nested functions. */
11739 {
11747 /* Note that we use SA as a temporary CFA, as the return
11748 address is at the proper place relative to it. We
11749 pretend this happens at the FP restore insn because
11750 prior to this insn the FP would be stored at the wrong
11751 offset relative to SA, and after this insn we have no
11752 other reasonable register to use for the CFA. We don't
11753 bother resetting the CFA to the SP for the duration of
11754 the return insn. */
11767 }
11768 else
11769 {
11777 {
11781 UNITS_PER_WORD));
11783 }
11784 }
11787 }
11788 }
11789 else
11790 {
11791 /* SEH requires that the function end with (1) a stack adjustment
11792 if necessary, (2) a sequence of pops, and (3) a return or
11793 jump instruction. Prevent insns from the function body from
11794 being scheduled into this sequence. */
11796 {
11797 /* Prevent a catch region from being adjacent to the standard
11798 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11799 several other flags that would be interesting to test are
11800 not yet set up. */
11803 else
11805 }
11807 /* First step is to deallocate the stack frame so that we can
11808 pop the registers. Also do it on SEH target for very large
11809 frame as the emitted instructions aren't allowed by the ABI in
11810 epilogues. */
11812 || (TARGET_SEH
11815 {
11820 }
11822 {
11826 style,
11828 }
11831 }
11833 /* If we used a stack pointer and haven't already got rid of it,
11834 then do so now. */
11836 {
11837 /* If the stack pointer is valid and pointing at the frame
11838 pointer store address, then we only need a pop. */
11841 /* Leave results in shorter dependency chains on CPUs that are
11842 able to grok it fast. */
11847 else
11848 {
11850 hard_frame_pointer_rtx,
11853 }
11854 }
11857 {
11859 rtx insn;
11885 }
11887 /* At this point the stack pointer must be valid, and we must have
11888 restored all of the registers. We may not have deallocated the
11889 entire stack frame. We've delayed this until now because it may
11890 be possible to merge the local stack deallocation with the
11891 deallocation forced by ix86_static_chain_on_stack. */
11896 {
11900 }
11901 else
11904 /* Sibcall epilogues don't want a return instruction. */
11906 {
11909 }
11912 {
11915 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11916 address, do explicit add, and jump indirectly to the caller. */
11919 {
11921 rtx insn;
11923 /* There is no "pascal" calling convention in any 64bit ABI. */
11940 }
11941 else
11943 }
11944 else
11947 /* Restore the state back to the state from the prologue,
11948 so that it's correct for the next epilogue. */
11950 }
11952 /* Reset from the function's potential modifications. */
11954 static void
11956 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11957 {
11960 #if TARGET_MACHO
11961 /* Mach-O doesn't support labels at the end of objects, so if
11962 it looks like we might want one, insert a NOP. */
11963 {
11969 {
11970 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11971 notes only, instead set their CODE_LABEL_NUMBER to -1,
11972 otherwise there would be code generation differences
11973 in between -g and -g0. */
11977 }
11987 }
11988 #endif
11990 }
11992 /* Return a scratch register to use in the split stack prologue. The
11993 split stack prologue is used for -fsplit-stack. It is the first
11994 instructions in the function, even before the regular prologue.
11995 The scratch register can be any caller-saved register which is not
11996 used for parameters or for the static chain. */
11998 static unsigned int
12000 {
12003 else
12004 {
12017 {
12019 {
12023 }
12025 }
12027 {
12031 }
12033 {
12036 else
12037 {
12039 {
12043 }
12045 }
12046 }
12047 else
12048 {
12049 /* FIXME: We could make this work by pushing a register
12050 around the addition and comparison. */
12053 }
12054 }
12055 }
12057 /* A SYMBOL_REF for the function which allocates new stackspace for
12058 -fsplit-stack. */
12062 /* A SYMBOL_REF for the more stack function when using the large
12063 model. */
12067 /* Handle -fsplit-stack. These are the first instructions in the
12068 function, even before the regular prologue. */
12070 void
12072 {
12074 HOST_WIDE_INT allocate;
12079 rtx fn;
12087 /* This is the label we will branch to if we have enough stack
12088 space. We expect the basic block reordering pass to reverse this
12089 branch if optimizing, so that we branch in the unlikely case. */
12092 /* We need to compare the stack pointer minus the frame size with
12093 the stack boundary in the TCB. The stack boundary always gives
12094 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12095 can compare directly. Otherwise we need to do an addition. */
12098 UNSPEC_STACK_CHECK);
12103 else
12104 {
12106 rtx offset;
12108 /* We need a scratch register to hold the stack pointer minus
12109 the required frame size. Since this is the very start of the
12110 function, the scratch register can be any caller-saved
12111 register which is not used for parameters. */
12118 {
12119 /* We don't use ix86_gen_add3 in this case because it will
12120 want to split to lea, but when not optimizing the insn
12121 will not be split after this point. */
12124 offset)));
12125 }
12126 else
12127 {
12130 stack_pointer_rtx));
12131 }
12133 }
12139 /* Mark the jump as very likely to be taken. */
12147 /* Get more stack space. We pass in the desired stack space and the
12148 size of the arguments to copy to the new stack. In 32-bit mode
12149 we push the parameters; __morestack will return on a new stack
12150 anyhow. In 64-bit mode we pass the parameters in r10 and
12151 r11. */
12156 {
12162 /* If this function uses a static chain, it will be in %r10.
12163 Preserve it across the call to __morestack. */
12165 {
12166 rtx rax;
12171 }
12175 {
12176 HOST_WIDE_INT argval;
12179 /* When using the large model we need to load the address
12180 into a register, and we've run out of registers. So we
12181 switch to a different calling convention, and we call a
12182 different function: __morestack_large. We pass the
12183 argument size in the upper 32 bits of r10 and pass the
12184 frame size in the lower 32 bits. */
12189 split_stack_fn_large =
12193 {
12203 UNSPEC_GOT);
12209 }
12210 else
12217 }
12218 else
12219 {
12223 }
12226 }
12227 else
12228 {
12231 }
12237 /* In order to make call/return prediction work right, we now need
12238 to execute a return instruction. See
12239 libgcc/config/i386/morestack.S for the details on how this works.
12241 For flow purposes gcc must not see this as a return
12242 instruction--we need control flow to continue at the subsequent
12243 label. Therefore, we use an unspec. */
12247 /* If we are in 64-bit mode and this function uses a static chain,
12248 we saved %r10 in %rax before calling _morestack. */
12253 /* If this function calls va_start, we need to store a pointer to
12254 the arguments on the old stack, because they may not have been
12255 all copied to the new stack. At this point the old stack can be
12256 found at the frame pointer value used by __morestack, because
12257 __morestack has set that up before calling back to us. Here we
12258 store that pointer in a scratch register, and in
12259 ix86_expand_prologue we store the scratch register in a stack
12260 slot. */
12262 {
12264 rtx frame_reg;
12271 /* 64-bit:
12272 fp -> old fp value
12273 return address within this function
12274 return address of caller of this function
12275 stack arguments
12276 So we add three words to get to the stack arguments.
12278 32-bit:
12279 fp -> old fp value
12280 return address within this function
12281 first argument to __morestack
12282 second argument to __morestack
12283 return address of caller of this function
12284 stack arguments
12285 So we add five words to get to the stack arguments.
12286 */
12297 }
12302 /* If this function calls va_start, we now have to set the scratch
12303 register for the case where we do not call __morestack. In this
12304 case we need to set it based on the stack pointer. */
12306 {
12313 }
12314 }
12316 /* We may have to tell the dataflow pass that the split stack prologue
12317 is initializing a scratch register. */
12319 static void
12321 {
12323 {
12326 }
12327 }
12328 \f
12329 /* Extract the parts of an RTL expression that is a valid memory address
12330 for an instruction. Return 0 if the structure of the address is
12331 grossly off. Return -1 if the address contains ASHIFT, so it is not
12332 strictly valid, but still used for computing length of lea instruction. */
12334 int
12336 {
12341 rtx tmp;
12345 /* Allow zero-extended SImode addresses,
12346 they will be emitted with addr32 prefix. */
12348 {
12351 {
12355 }
12358 {
12365 }
12366 }
12368 /* Allow SImode subregs of DImode addresses,
12369 they will be emitted with addr32 prefix. */
12371 {
12374 {
12378 }
12379 }
12384 {
12387 else
12389 }
12391 {
12396 do
12397 {
12402 }
12409 {
12412 {
12437 /* FALLTHRU */
12441 && TARGET_TLS_DIRECT_SEG_REFS
12444 else
12451 /* FALLTHRU */
12458 else
12473 }
12474 }
12475 }
12477 {
12480 }
12482 {
12483 /* We're called for lea too, which implements ashift on occasion. */
12493 }
12494 else
12498 {
12500 ;
12503 ;
12504 else
12506 }
12508 /* Extract the integral value of scale. */
12510 {
12514 }
12519 /* Avoid useless 0 displacement. */
12523 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12528 {
12529 rtx tmp;
12532 }
12534 /* Special case: %ebp cannot be encoded as a base without a displacement.
12535 Similarly %r13. */
12537 && base_reg
12546 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12547 Avoid this by transforming to [%esi+0].
12548 Reload calls address legitimization without cfun defined, so we need
12549 to test cfun for being non-NULL. */
12555 /* Special case: encode reg+reg instead of reg*2. */
12559 /* Special case: scaling cannot be encoded without base or displacement. */
12570 }
12571 \f
12572 /* Return cost of the memory address x.
12573 For i386, it is better to use a complex address than let gcc copy
12574 the address into a reg and make a new pseudo. But not if the address
12575 requires to two regs - that would mean more pseudos with longer
12576 lifetimes. */
12577 static int
12579 addr_space_t as ATTRIBUTE_UNUSED,
12581 {
12593 /* Attempt to minimize number of registers in the address. */
12599 cost++;
12606 cost++;
12608 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
12609 since it's predecode logic can't detect the length of instructions
12610 and it degenerates to vector decoded. Increase cost of such
12611 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
12612 to split such addresses or even refuse such addresses at all.
12614 Following addressing modes are affected:
12615 [base+scale*index]
12616 [scale*index+disp]
12617 [base+index]
12619 The first and last case may be avoidable by explicitly coding the zero in
12620 memory address, but I don't have AMD-K6 machine handy to check this
12621 theory. */
12630 }
12631 \f
12632 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
12633 this is used for to form addresses to local data when -fPIC is in
12634 use. */
12636 static bool
12638 {
12641 }
12643 /* Determine if a given RTX is a valid constant. We already know this
12644 satisfies CONSTANT_P. */
12646 static bool
12648 {
12649 /* Pointer bounds constants are not valid. */
12654 {
12659 {
12663 }
12668 /* Only some unspecs are valid as "constants". */
12671 {
12687 }
12689 /* We must have drilled down to a symbol. */
12694 /* FALLTHRU */
12697 /* TLS symbols are never valid. */
12701 /* DLLIMPORT symbols are never valid. */
12706 #if TARGET_MACHO
12707 /* mdynamic-no-pic */
12710 #endif
12726 }
12728 /* Otherwise we handle everything else in the move patterns. */
12730 }
12732 /* Determine if it's legal to put X into the constant pool. This
12733 is not possible for the address of thread-local symbols, which
12734 is checked above. */
12736 static bool
12738 {
12739 /* We can always put integral constants and vectors in memory. */
12741 {
12749 }
12751 }
12753 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12754 otherwise zero. */
12756 static bool
12758 {
12764 }
12767 /* Nonzero if the constant value X is a legitimate general operand
12768 when generating PIC code. It is given that flag_pic is on and
12769 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12771 bool
12773 {
12774 rtx inner;
12777 {
12784 /* Only some unspecs are valid as "constants". */
12787 {
12800 }
12801 /* FALLTHRU */
12809 }
12810 }
12812 /* Determine if a given CONST RTX is a valid memory displacement
12813 in PIC mode. */
12815 bool
12817 {
12820 /* In 64bit mode we can allow direct addresses of symbols and labels
12821 when they are not dynamic symbols. */
12823 {
12827 {
12851 /* FALLTHRU */
12854 /* TLS references should always be enclosed in UNSPEC.
12855 The dllimported symbol needs always to be resolved. */
12861 {
12869 /* Function-symbols need to be resolved only for
12870 large-model.
12871 For the small-model we don't need to resolve anything
12872 here. */
12877 /* Non-external symbols don't need to be resolved for
12878 large, and medium-model. */
12883 }
12892 }
12893 }
12899 {
12900 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12901 of GOT tables. We should not need these anyway. */
12913 }
12917 {
12922 }
12931 {
12935 /* We need to check for both symbols and labels because VxWorks loads
12936 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12937 details. */
12941 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12942 While ABI specify also 32bit relocation but we don't produce it in
12943 small PIC model at all. */
12965 }
12968 }
12970 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12971 replace the input X, or the original X if no replacement is called for.
12972 The output parameter *WIN is 1 if the calling macro should goto WIN,
12973 0 if it should not. */
12975 bool
12980 {
12981 /* Reload can generate:
12983 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12984 (reg:DI 97))
12985 (reg:DI 2 cx))
12987 This RTX is rejected from ix86_legitimate_address_p due to
12988 non-strictness of base register 97. Following this rejection,
12989 reload pushes all three components into separate registers,
12990 creating invalid memory address RTX.
12992 Following code reloads only the invalid part of the
12993 memory address RTX. */
12999 {
13005 {
13010 }
13014 {
13019 }
13023 }
13026 }
13028 /* Determine if op is suitable RTX for an address register.
13029 Return naked register if a register or a register subreg is
13030 found, otherwise return NULL_RTX. */
13032 static rtx
13034 {
13037 /* Only SImode or DImode registers can form the address. */
13044 {
13052 /* Don't allow SUBREGs that span more than a word. It can
13053 lead to spill failures when the register is one word out
13054 of a two word structure. */
13058 /* Allow only SUBREGs of non-eliminable hard registers. */
13061 }
13063 /* Op is not a register. */
13065 }
13067 /* Recognizes RTL expressions that are valid memory addresses for an
13068 instruction. The MODE argument is the machine mode for the MEM
13069 expression that wants to use this address.
13071 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13072 convert common non-canonical forms to canonical form so that they will
13073 be recognized. */
13075 static bool
13078 {
13081 HOST_WIDE_INT scale;
13085 /* Decomposition failed. */
13094 /* Validate base register. */
13096 {
13104 /* Base is not valid. */
13106 }
13108 /* Validate index register. */
13110 {
13118 /* Index is not valid. */
13120 }
13122 /* Index and base should have the same mode. */
13127 /* Address override works only on the (%reg) part of %fs:(%reg). */
13133 /* Validate scale factor. */
13135 {
13137 /* Scale without index. */
13141 /* Scale is not a valid multiplier. */
13143 }
13145 /* Validate displacement. */
13147 {
13152 {
13153 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13154 used. While ABI specify also 32bit relocations, we don't produce
13155 them at all and use IP relative instead. */
13162 /* 64bit address unspec. */
13182 /* Invalid address unspec. */
13184 }
13187 && (flag_pic
13188 || (TARGET_MACHO
13189 #if TARGET_MACHO
13190 && MACHOPIC_INDIRECT
13192 #endif
13193 )))
13194 {
13196 is_legitimate_pic:
13198 {
13199 /* foo@dtpoff(%rX) is ok. */
13206 /* Non-constant pic memory reference. */
13208 }
13211 /* Displacement is an invalid pic construct. */
13213 #if TARGET_MACHO
13216 /* displacment must be referenced via non_lazy_pointer */
13218 #endif
13220 /* This code used to verify that a symbolic pic displacement
13221 includes the pic_offset_table_rtx register.
13223 While this is good idea, unfortunately these constructs may
13224 be created by "adds using lea" optimization for incorrect
13225 code like:
13227 int a;
13228 int foo(int i)
13229 {
13230 return *(&a+i);
13231 }
13233 This code is nonsensical, but results in addressing
13234 GOT table with pic_offset_table_rtx base. We can't
13235 just refuse it easily, since it gets matched by
13236 "addsi3" pattern, that later gets split to lea in the
13237 case output register differs from input. While this
13238 can be handled by separate addsi pattern for this case
13239 that never results in lea, this seems to be easier and
13240 correct fix for crash to disable this test. */
13241 }
13248 /* Displacement is not constant. */
13252 /* Displacement is out of range. */
13254 /* In x32 mode, constant addresses are sign extended to 64bit, so
13255 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13260 }
13262 /* Everything looks valid. */
13264 }
13266 /* Determine if a given RTX is a valid constant address. */
13268 bool
13270 {
13272 }
13273 \f
13274 /* Return a unique alias set for the GOT. */
13276 static alias_set_type
13278 {
13283 }
13285 /* Return a legitimate reference for ORIG (an address) using the
13286 register REG. If REG is 0, a new pseudo is generated.
13288 There are two types of references that must be handled:
13290 1. Global data references must load the address from the GOT, via
13291 the PIC reg. An insn is emitted to do this load, and the reg is
13292 returned.
13294 2. Static data references, constant pool addresses, and code labels
13295 compute the address as an offset from the GOT, whose base is in
13296 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13297 differentiate them from global data objects. The returned
13298 address is the PIC reg + an unspec constant.
13300 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13301 reg also appears in the address. */
13303 static rtx
13305 {
13309 #if TARGET_MACHO
13311 {
13314 /* Use the generic Mach-O PIC machinery. */
13316 }
13317 #endif
13320 {
13324 }
13330 {
13331 rtx tmpreg;
13332 /* This symbol may be referenced via a displacement from the PIC
13333 base address (@GOTOFF). */
13340 {
13342 UNSPEC_GOTOFF);
13344 }
13345 else
13350 else
13355 {
13359 }
13360 else
13362 }
13364 {
13365 /* This symbol may be referenced via a displacement from the PIC
13366 base address (@GOTOFF). */
13373 {
13375 UNSPEC_GOTOFF);
13377 }
13378 else
13384 {
13387 }
13388 }
13390 /* We can't use @GOTOFF for text labels on VxWorks;
13391 see gotoff_operand. */
13393 {
13398 /* For x64 PE-COFF there is no GOT table. So we use address
13399 directly. */
13401 {
13409 }
13411 {
13419 /* Use directly gen_movsi, otherwise the address is loaded
13420 into register for CSE. We don't want to CSE this addresses,
13421 instead we CSE addresses from the GOT table, so skip this. */
13424 }
13425 else
13426 {
13427 /* This symbol must be referenced via a load from the
13428 Global Offset Table (@GOT). */
13444 }
13445 }
13446 else
13447 {
13450 {
13452 {
13455 }
13456 else
13458 }
13460 {
13463 /* We must match stuff we generate before. Assume the only
13464 unspecs that can get here are ours. Not that we could do
13465 anything with them anyway.... */
13471 }
13473 {
13476 /* Check first to see if this is a constant offset from a @GOTOFF
13477 symbol reference. */
13480 {
13482 {
13486 UNSPEC_GOTOFF);
13492 {
13495 }
13496 }
13497 else
13498 {
13501 {
13505 }
13506 }
13507 }
13508 else
13509 {
13512 new_rtx
13516 {
13519 {
13522 new_rtx
13524 }
13525 else
13527 }
13528 else
13529 {
13532 {
13535 }
13537 }
13538 }
13539 }
13540 }
13542 }
13543 \f
13544 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13546 static rtx
13548 {
13552 {
13557 }
13563 }
13565 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13569 static rtx
13571 {
13573 {
13579 }
13582 {
13584 UNSPEC_PLTOFF);
13587 }
13590 }
13592 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13596 rtx
13598 {
13600 {
13601 ix86_tls_module_base_symbol
13606 }
13609 }
13611 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13612 false if we expect this to be used for a memory address and true if
13613 we expect to load the address into a register. */
13615 static rtx
13617 {
13623 /* Fall back to global dynamic model if tool chain cannot support local
13624 dynamic. */
13631 {
13636 {
13639 else
13640 {
13643 }
13644 }
13647 {
13650 else
13660 }
13661 else
13662 {
13666 {
13668 rtx insns;
13671 emit_call_insn
13681 }
13682 else
13684 }
13691 {
13694 else
13695 {
13698 }
13699 }
13702 {
13707 else
13713 }
13714 else
13715 {
13719 {
13724 emit_call_insn
13729 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
13730 share the LD_BASE result with other LD model accesses. */
13732 UNSPEC_TLS_LD_BASE);
13736 }
13737 else
13739 }
13747 {
13754 }
13759 {
13761 {
13762 /* The Sun linker took the AMD64 TLS spec literally
13763 and can only handle %rax as destination of the
13764 initial executable code sequence. */
13769 }
13771 /* Generate DImode references to avoid %fs:(%reg32)
13772 problems and linker IE->LE relaxation bug. */
13776 }
13778 {
13783 }
13785 {
13789 }
13790 else
13791 {
13794 }
13804 {
13809 }
13810 else
13811 {
13815 }
13825 {
13829 }
13830 else
13831 {
13835 }
13840 }
13843 }
13845 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13846 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13847 unique refptr-DECL symbol corresponding to symbol DECL. */
13850 htab_t dllimport_map;
13852 static tree
13854 {
13861 tree to;
13862 rtx rtl;
13889 else
13902 {
13904 #ifdef SUB_TARGET_RECORD_STUB
13906 #endif
13907 }
13916 }
13918 /* Expand SYMBOL into its corresponding far-addresse symbol.
13919 WANT_REG is true if we require the result be a register. */
13921 static rtx
13923 {
13924 tree imp_decl;
13925 rtx x;
13934 }
13936 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13937 true if we require the result be a register. */
13939 static rtx
13941 {
13942 tree imp_decl;
13943 rtx x;
13952 }
13954 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13955 is true if we require the result be a register. */
13957 static rtx
13959 {
13964 {
13971 {
13974 }
13975 }
13991 {
13994 }
13996 }
13998 /* Try machine-dependent ways of modifying an illegitimate address
13999 to be legitimate. If we find one, return the new, valid address.
14000 This macro is used in only one place: `memory_address' in explow.c.
14002 OLDX is the address as it was before break_out_memory_refs was called.
14003 In some cases it is useful to look at this to decide what needs to be done.
14005 It is always safe for this macro to do nothing. It exists to recognize
14006 opportunities to optimize the output.
14008 For the 80386, we handle X+REG by loading X into a register R and
14009 using R+REG. R will go in a general reg and indexing will be used.
14010 However, if REG is a broken-out memory address or multiplication,
14011 nothing needs to be done because REG can certainly go in a general reg.
14013 When -fpic is used, special handling is needed for symbolic references.
14014 See comments by legitimize_pic_address in i386.c for details. */
14016 static rtx
14019 {
14030 {
14034 }
14037 {
14041 }
14046 #if TARGET_MACHO
14049 #endif
14051 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14055 {
14060 }
14063 {
14064 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14069 {
14075 }
14080 {
14086 }
14088 /* Put multiply first if it isn't already. */
14090 {
14095 }
14097 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14098 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14099 created by virtual register instantiation, register elimination, and
14100 similar optimizations. */
14102 {
14108 }
14110 /* Canonicalize
14111 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14112 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14117 {
14118 rtx constant;
14122 {
14125 }
14127 {
14130 }
14131 else
14135 {
14142 }
14143 }
14149 {
14152 }
14155 {
14158 }
14166 {
14169 }
14175 {
14179 {
14182 }
14186 }
14189 {
14193 {
14196 }
14200 }
14201 }
14204 }
14205 \f
14206 /* Print an integer constant expression in assembler syntax. Addition
14207 and subtraction are the only arithmetic that may appear in these
14208 expressions. FILE is the stdio stream to write to, X is the rtx, and
14209 CODE is the operand print code from the output string. */
14211 static void
14213 {
14217 {
14226 else
14227 {
14230 /* Mark the decl as referenced so that cgraph will
14231 output the function. */
14235 #if TARGET_MACHO
14239 #endif
14241 }
14249 /* FALLTHRU */
14260 /* This used to output parentheses around the expression,
14261 but that does not work on the 386 (either ATT or BSD assembler). */
14267 {
14268 /* We can use %d if the number is <32 bits and positive. */
14273 else
14275 }
14276 else
14277 /* We can't handle floating point constants;
14278 TARGET_PRINT_OPERAND must handle them. */
14283 /* Some assemblers need integer constants to appear first. */
14285 {
14289 }
14290 else
14291 {
14296 }
14311 {
14315 }
14320 {
14339 /* FIXME: This might be @TPOFF in Sun ld too. */
14348 else
14358 else
14364 #if TARGET_MACHO
14369 #endif
14373 }
14378 }
14379 }
14381 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14382 We need to emit DTP-relative relocations. */
14384 static void ATTRIBUTE_UNUSED
14386 {
14391 {
14399 }
14400 }
14402 /* Return true if X is a representation of the PIC register. This copes
14403 with calls from ix86_find_base_term, where the register might have
14404 been replaced by a cselib value. */
14406 static bool
14408 {
14412 else
14414 }
14416 /* Helper function for ix86_delegitimize_address.
14417 Attempt to delegitimize TLS local-exec accesses. */
14419 static rtx
14421 {
14446 {
14451 }
14457 }
14459 /* In the name of slightly smaller debug output, and to cater to
14460 general assembler lossage, recognize PIC+GOTOFF and turn it back
14461 into a direct symbol reference.
14463 On Darwin, this is necessary to avoid a crash, because Darwin
14464 has a different PIC label for each routine but the DWARF debugging
14465 information is not associated with any particular routine, so it's
14466 necessary to remove references to the PIC label from RTL stored by
14467 the DWARF output code. */
14469 static rtx
14471 {
14473 /* addend is NULL or some rtx if x is something+GOTOFF where
14474 something doesn't include the PIC register. */
14476 /* reg_addend is NULL or a multiple of some register. */
14478 /* const_addend is NULL or a const_int. */
14480 /* This is the result, or NULL. */
14489 {
14496 {
14502 }
14509 {
14512 {
14517 }
14519 }
14524 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14525 and -mcmodel=medium -fpic. */
14526 }
14533 /* %ebx + GOT/GOTOFF */
14534 ;
14536 {
14537 /* %ebx + %reg * scale + GOT/GOTOFF */
14543 else
14544 {
14547 }
14548 }
14549 else
14555 {
14558 }
14579 {
14580 /* If the rest of original X doesn't involve the PIC register, add
14581 addend and subtract pic_offset_table_rtx. This can happen e.g.
14582 for code like:
14583 leal (%ebx, %ecx, 4), %ecx
14584 ...
14585 movl foo@GOTOFF(%ecx), %edx
14586 in which case we return (%ecx - %ebx) + foo. */
14589 pic_offset_table_rtx),
14590 result);
14591 else
14593 }
14595 {
14599 }
14601 }
14603 /* If X is a machine specific address (i.e. a symbol or label being
14604 referenced as a displacement from the GOT implemented using an
14605 UNSPEC), then return the base term. Otherwise return X. */
14607 rtx
14609 {
14610 rtx term;
14613 {
14627 }
14630 }
14631 \f
14632 static void
14635 {
14639 {
14642 }
14647 {
14650 {
14669 }
14673 {
14692 }
14699 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
14700 Those same assemblers have the same but opposite lossage on cmov. */
14703 else
14708 {
14721 }
14728 else
14733 {
14746 }
14753 else
14763 else
14774 }
14776 }
14778 /* Print the name of register X to FILE based on its machine mode and number.
14779 If CODE is 'w', pretend the mode is HImode.
14780 If CODE is 'b', pretend the mode is QImode.
14781 If CODE is 'k', pretend the mode is SImode.
14782 If CODE is 'q', pretend the mode is DImode.
14783 If CODE is 'x', pretend the mode is V4SFmode.
14784 If CODE is 't', pretend the mode is V8SFmode.
14785 If CODE is 'g', pretend the mode is V16SFmode.
14786 If CODE is 'h', pretend the reg is the 'high' byte register.
14787 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
14788 If CODE is 'd', duplicate the operand for AVX instruction.
14789 */
14791 void
14793 {
14802 {
14806 }
14833 else
14836 /* Irritatingly, AMD extended registers use different naming convention
14837 from the normal registers: "r%d[bwd]" */
14839 {
14844 {
14858 /* no suffix */
14863 }
14865 }
14869 {
14872 {
14875 }
14876 /* FALLTHRU */
14882 /* FALLTHRU */
14885 normal:
14900 {
14905 }
14908 {
14913 }
14917 }
14921 {
14924 else
14926 }
14927 }
14929 /* Locate some local-dynamic symbol still in use by this function
14930 so that we can print its name in some tls_local_dynamic_base
14931 pattern. */
14933 static int
14935 {
14940 {
14943 }
14946 }
14950 {
14951 rtx insn;
14962 }
14964 /* Meaning of CODE:
14965 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14966 C -- print opcode suffix for set/cmov insn.
14967 c -- like C, but print reversed condition
14968 F,f -- likewise, but for floating-point.
14969 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14970 otherwise nothing
14971 R -- print embeded rounding and sae.
14972 r -- print only sae.
14973 z -- print the opcode suffix for the size of the current operand.
14974 Z -- likewise, with special suffixes for x87 instructions.
14975 * -- print a star (in certain assembler syntax)
14976 A -- print an absolute memory reference.
14977 E -- print address with DImode register names if TARGET_64BIT.
14978 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14979 s -- print a shift double count, followed by the assemblers argument
14980 delimiter.
14981 b -- print the QImode name of the register for the indicated operand.
14982 %b0 would print %al if operands[0] is reg 0.
14983 w -- likewise, print the HImode name of the register.
14984 k -- likewise, print the SImode name of the register.
14985 q -- likewise, print the DImode name of the register.
14986 x -- likewise, print the V4SFmode name of the register.
14987 t -- likewise, print the V8SFmode name of the register.
14988 g -- likewise, print the V16SFmode name of the register.
14989 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14990 y -- print "st(0)" instead of "st" as a register.
14991 d -- print duplicated register operand for AVX instruction.
14992 D -- print condition for SSE cmp instruction.
14993 P -- if PIC, print an @PLT suffix.
14994 p -- print raw symbol name.
14995 X -- don't print any sort of PIC '@' suffix for a symbol.
14996 & -- print some in-use local-dynamic symbol name.
14997 H -- print a memory address offset by 8; used for sse high-parts
14998 Y -- print condition for XOP pcom* instruction.
14999 + -- print a branch hint as 'cs' or 'ds' prefix
15000 ; -- print a semicolon (after prefixes due to bug in older gas).
15001 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15002 @ -- print a segment register of thread base pointer load
15003 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15004 ! -- print MPX prefix for jxx/call/ret instructions if required.
15005 */
15007 void
15009 {
15011 {
15013 {
15016 {
15022 /* Intel syntax. For absolute addresses, registers should not
15023 be surrounded by braces. */
15025 {
15030 }
15035 }
15041 /* Wrap address in an UNSPEC to declare special handling. */
15079 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15084 {
15098 output_operand_lossage
15101 }
15104 #endif
15109 {
15110 /* Opcodes don't get size suffixes if using Intel opcodes. */
15115 {
15133 output_operand_lossage
15136 }
15137 }
15140 warning
15142 /* FALLTHRU */
15145 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15150 {
15152 {
15154 #ifdef HAVE_AS_IX86_FILDS
15156 #endif
15164 #ifdef HAVE_AS_IX86_FILDQ
15166 #else
15168 #endif
15173 }
15174 }
15176 {
15177 /* 387 opcodes don't get size suffixes
15178 if the operands are registers. */
15183 {
15199 }
15200 }
15201 else
15202 {
15203 output_operand_lossage
15206 }
15208 output_operand_lossage
15229 {
15232 }
15237 {
15288 }
15292 /* Little bit of braindamage here. The SSE compare instructions
15293 does use completely different names for the comparisons that the
15294 fp conditional moves. */
15296 {
15299 {
15302 }
15308 {
15311 }
15317 {
15320 }
15329 {
15332 }
15338 {
15341 }
15347 {
15350 }
15361 }
15366 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15369 #endif
15374 {
15378 }
15382 file);
15387 {
15391 }
15392 /* It doesn't actually matter what mode we use here, as we're
15393 only going to use this for printing. */
15395 /* Output 'qword ptr' for intel assembler dialect. */
15404 #ifdef HAVE_AS_IX86_HLE
15406 #else
15408 #endif
15410 #ifdef HAVE_AS_IX86_HLE
15412 #else
15414 #endif
15415 /* We do not want to print value of the operand. */
15444 {
15459 }
15472 {
15477 else
15480 }
15483 {
15484 rtx x;
15493 {
15498 {
15500 bool cputaken
15503 /* Emit hints only in the case default branch prediction
15504 heuristics would fail. */
15506 {
15507 /* We use 3e (DS) prefix for taken branches and
15508 2e (CS) prefix for not taken branches. */
15511 else
15513 }
15514 }
15515 }
15517 }
15520 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15522 #endif
15529 /* The kernel uses a different segment register for performance
15530 reasons; a system call would not have to trash the userspace
15531 segment register, which would be expensive. */
15534 else
15554 }
15555 }
15561 {
15562 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15565 {
15568 {
15577 else
15584 }
15586 /* Check for explicit size override (codes 'b', 'w', 'k',
15587 'q' and 'x') */
15601 }
15604 /* Avoid (%rip) for call operands. */
15610 else
15612 }
15615 {
15616 REAL_VALUE_TYPE r;
15624 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15628 else
15630 }
15633 {
15634 REAL_VALUE_TYPE r;
15643 }
15645 /* These float cases don't actually occur as immediate operands. */
15647 {
15652 }
15654 else
15655 {
15656 /* We have patterns that allow zero sets of memory, for instance.
15657 In 64-bit mode, we should probably support all 8-byte vectors,
15658 since we can in fact encode that into an immediate. */
15660 {
15663 }
15666 {
15668 {
15671 }
15674 {
15677 else
15679 }
15680 }
15685 else
15687 }
15688 }
15690 static bool
15692 {
15695 }
15696 \f
15697 /* Print a memory operand whose address is ADDR. */
15699 static void
15701 {
15710 {
15717 }
15719 {
15723 }
15725 {
15729 {
15732 }
15735 }
15737 {
15742 }
15743 else
15754 {
15765 }
15767 /* Use one byte shorter RIP relative addressing for 64bit mode. */
15769 {
15781 }
15783 {
15784 /* Displacement only requires special attention. */
15787 {
15791 }
15794 else
15796 }
15797 else
15798 {
15799 /* Print SImode register names to force addr32 prefix. */
15801 {
15802 #ifdef ENABLE_CHECKING
15805 {
15816 }
15817 #endif
15820 }
15822 && TARGET_X32
15823 && disp
15826 {
15827 /* X32 runs in 64-bit mode, where displacement, DISP, in
15828 address DISP(%r64), is encoded as 32-bit immediate sign-
15829 extended from 32-bit to 64-bit. For -0x40000300(%r64),
15830 address is %r64 + 0xffffffffbffffd00. When %r64 <
15831 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
15832 which is invalid for x32. The correct address is %r64
15833 - 0x40000300 == 0xf7ffdd64. To properly encode
15834 -0x40000300(%r64) for x32, we zero-extend negative
15835 displacement by forcing addr32 prefix which truncates
15836 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
15837 zero-extend all negative displacements, including -1(%rsp).
15838 However, for small negative displacements, sign-extension
15839 won't cause overflow. We only zero-extend negative
15840 displacements if they < -16*1024*1024, which is also used
15841 to check legitimate address displacements for PIC. */
15843 }
15846 {
15848 {
15853 else
15855 }
15861 {
15866 }
15868 }
15869 else
15870 {
15874 {
15875 /* Pull out the offset of a symbol; print any symbol itself. */
15879 {
15883 }
15891 else
15893 }
15897 {
15900 {
15904 }
15905 }
15908 else
15912 {
15917 }
15919 }
15920 }
15921 }
15923 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15925 static bool
15927 {
15928 rtx op;
15935 {
15938 /* FIXME: This might be @TPOFF in Sun ld. */
15949 else
15961 else
15968 #if TARGET_MACHO
15974 #endif
15977 {
15982 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15984 #else
15986 #endif
15989 }
15994 }
15997 }
15998 \f
15999 /* Split one or more double-mode RTL references into pairs of half-mode
16000 references. The RTL can be REG, offsettable MEM, integer constant, or
16001 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16002 split and "num" is its length. lo_half and hi_half are output arrays
16003 that parallel "operands". */
16005 void
16008 {
16013 {
16022 }
16027 {
16030 /* simplify_subreg refuse to split volatile memory addresses,
16031 but we still have to handle it. */
16033 {
16036 }
16037 else
16038 {
16045 }
16046 }
16047 }
16048 \f
16049 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16050 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16051 is the expression of the binary operation. The output may either be
16052 emitted here, or returned to the caller, like all output_* functions.
16054 There is no guarantee that the operands are the same mode, as they
16055 might be within FLOAT or FLOAT_EXTEND expressions. */
16057 #ifndef SYSV386_COMPAT
16058 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16059 wants to fix the assemblers because that causes incompatibility
16060 with gcc. No-one wants to fix gcc because that causes
16061 incompatibility with assemblers... You can use the option of
16062 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16063 #define SYSV386_COMPAT 1
16064 #endif
16068 {
16074 #ifdef ENABLE_CHECKING
16075 /* Even if we do not want to check the inputs, this documents input
16076 constraints. Which helps in understanding the following code. */
16086 else
16088 #endif
16091 {
16096 else
16105 else
16114 else
16123 else
16130 }
16133 {
16135 {
16139 else
16141 }
16142 else
16143 {
16147 else
16149 }
16151 }
16155 {
16159 {
16163 }
16165 /* know operands[0] == operands[1]. */
16168 {
16171 }
16174 {
16176 /* How is it that we are storing to a dead operand[2]?
16177 Well, presumably operands[1] is dead too. We can't
16178 store the result to st(0) as st(0) gets popped on this
16179 instruction. Instead store to operands[2] (which I
16180 think has to be st(1)). st(1) will be popped later.
16181 gcc <= 2.8.1 didn't have this check and generated
16182 assembly code that the Unixware assembler rejected. */
16184 else
16187 }
16191 else
16198 {
16201 }
16204 {
16207 }
16210 {
16211 #if SYSV386_COMPAT
16212 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16213 derived assemblers, confusingly reverse the direction of
16214 the operation for fsub{r} and fdiv{r} when the
16215 destination register is not st(0). The Intel assembler
16216 doesn't have this brain damage. Read !SYSV386_COMPAT to
16217 figure out what the hardware really does. */
16220 else
16222 #else
16224 /* As above for fmul/fadd, we can't store to st(0). */
16226 else
16228 #endif
16230 }
16233 {
16234 #if SYSV386_COMPAT
16237 else
16239 #else
16242 else
16244 #endif
16246 }
16249 {
16252 else
16255 }
16257 {
16258 #if SYSV386_COMPAT
16260 #else
16262 #endif
16263 }
16264 else
16265 {
16266 #if SYSV386_COMPAT
16268 #else
16270 #endif
16271 }
16276 }
16280 }
16282 /* Check if a 256bit AVX register is referenced inside of EXP. */
16284 static int
16286 {
16297 }
16299 /* Return needed mode for entity in optimize_mode_switching pass. */
16301 static int
16303 {
16305 {
16306 rtx link;
16308 /* Needed mode is set to AVX_U128_CLEAN if there are
16309 no 256bit modes used in function arguments. */
16311 link;
16313 {
16315 {
16320 }
16321 }
16324 }
16326 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16327 changes state only when a 256bit register is written to, but we need
16328 to prevent the compiler from moving optimal insertion point above
16329 eventual read from 256bit register. */
16334 }
16336 /* Return mode that i387 must be switched into
16337 prior to the execution of insn. */
16339 static int
16341 {
16344 /* The mode UNINITIALIZED is used to store control word after a
16345 function call or ASM pattern. The mode ANY specify that function
16346 has no requirements on the control word and make no changes in the
16347 bits we are interested in. */
16361 {
16384 }
16387 }
16389 /* Return mode that entity must be switched into
16390 prior to the execution of insn. */
16392 int
16394 {
16396 {
16406 }
16408 }
16410 /* Check if a 256bit AVX register is referenced in stores. */
16412 static void
16414 {
16416 {
16419 }
16420 }
16422 /* Calculate mode of upper 128bit AVX registers after the insn. */
16424 static int
16426 {
16433 /* We know that state is clean after CALL insn if there are no
16434 256bit registers used in the function return register. */
16436 {
16441 }
16443 /* Otherwise, return current mode. Remember that if insn
16444 references AVX 256bit registers, the mode was already changed
16445 to DIRTY from MODE_NEEDED. */
16447 }
16449 /* Return the mode that an insn results in. */
16451 int
16453 {
16455 {
16465 }
16466 }
16468 static int
16470 {
16471 tree arg;
16473 /* Entry mode is set to AVX_U128_DIRTY if there are
16474 256bit modes used in function arguments. */
16477 {
16482 }
16485 }
16487 /* Return a mode that ENTITY is assumed to be
16488 switched to at function entry. */
16490 int
16492 {
16494 {
16504 }
16505 }
16507 static int
16509 {
16512 /* Exit mode is set to AVX_U128_DIRTY if there are
16513 256bit modes used in the function return register. */
16518 }
16520 /* Return a mode that ENTITY is assumed to be
16521 switched to at function exit. */
16523 int
16525 {
16527 {
16537 }
16538 }
16540 /* Output code to initialize control word copies used by trunc?f?i and
16541 rounding patterns. CURRENT_MODE is set to current control word,
16542 while NEW_MODE is set to new control word. */
16544 static void
16546 {
16548 rtx new_mode;
16559 {
16561 {
16563 /* round toward zero (truncate) */
16569 /* round down toward -oo */
16576 /* round up toward +oo */
16583 /* mask precision exception for nearbyint() */
16590 }
16591 }
16592 else
16593 {
16595 {
16597 /* round toward zero (truncate) */
16603 /* round down toward -oo */
16609 /* round up toward +oo */
16615 /* mask precision exception for nearbyint() */
16622 }
16623 }
16629 }
16631 /* Emit vzeroupper. */
16633 void
16635 {
16638 /* Cancel automatic vzeroupper insertion if there are
16639 live call-saved SSE registers at the insertion point. */
16651 }
16653 /* Generate one or more insns to set ENTITY to MODE. */
16655 void
16657 {
16659 {
16674 }
16675 }
16677 /* Output code for INSN to convert a float to a signed int. OPERANDS
16678 are the insn operands. The output may be [HSD]Imode and the input
16679 operand may be [SDX]Fmode. */
16683 {
16688 /* Jump through a hoop or two for DImode, since the hardware has no
16689 non-popping instruction. We used to do this a different way, but
16690 that was somewhat fragile and broke with post-reload splitters. */
16700 else
16701 {
16706 else
16710 }
16713 }
16715 /* Output code for x87 ffreep insn. The OPNO argument, which may only
16716 have the values zero or one, indicates the ffreep insn's operand
16717 from the OPERANDS array. */
16721 {
16723 #ifdef HAVE_AS_IX86_FFREEP
16725 #else
16726 {
16736 }
16737 #endif
16740 }
16743 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
16744 should be used. UNORDERED_P is true when fucom should be used. */
16748 {
16754 {
16757 }
16758 else
16759 {
16762 }
16765 {
16769 else
16771 else
16774 else
16776 }
16783 {
16785 {
16788 }
16789 else
16791 }
16794 && stack_top_dies
16797 {
16798 /* If both the top of the 387 stack dies, and the other operand
16799 is also a stack register that dies, then this must be a
16800 `fcompp' float compare */
16803 {
16804 /* There is no double popping fcomi variant. Fortunately,
16805 eflags is immune from the fstp's cc clobbering. */
16808 else
16811 }
16812 else
16813 {
16816 else
16818 }
16819 }
16820 else
16821 {
16822 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
16825 {
16833 NULL,
16834 NULL,
16841 NULL,
16842 NULL,
16843 NULL,
16844 NULL
16845 };
16860 }
16861 }
16863 void
16865 {
16868 #ifdef ASM_QUAD
16871 #else
16873 #endif
16876 }
16878 void
16880 {
16883 #ifdef ASM_QUAD
16886 #else
16888 #endif
16889 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16895 #if TARGET_MACHO
16897 {
16901 }
16902 #endif
16903 else
16906 }
16907 \f
16908 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16909 for the target. */
16911 void
16913 {
16914 rtx tmp;
16916 /* We play register width games, which are only valid after reload. */
16919 /* Avoid HImode and its attendant prefix byte. */
16924 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16926 {
16929 }
16932 }
16934 /* X is an unchanging MEM. If it is a constant pool reference, return
16935 the constant pool rtx, else NULL. */
16937 rtx
16939 {
16946 }
16948 void
16950 {
16958 {
16959 rtx tmp;
16963 {
16969 }
16972 }
16976 {
16979 rtx tmp;
16984 else
16988 {
16995 }
16996 }
17000 {
17002 {
17003 #if TARGET_MACHO
17004 /* dynamic-no-pic */
17006 {
17007 rtx temp = ((reload_in_progress
17015 }
17017 {
17021 }
17024 else
17025 {
17033 }
17034 /* dynamic-no-pic */
17035 #endif
17036 }
17037 else
17038 {
17042 {
17048 }
17049 }
17050 }
17051 else
17052 {
17063 /* Force large constants in 64bit compilation into register
17064 to get them CSEed. */
17076 {
17077 /* If we are loading a floating point constant to a register,
17078 force the value to memory now, since we'll get better code
17079 out the back end. */
17083 {
17088 }
17089 }
17090 }
17093 }
17095 void
17097 {
17104 /* Force constants other than zero into memory. We do not know how
17105 the instructions used to build constants modify the upper 64 bits
17106 of the register, once we have that information we may be able
17107 to handle some of them more efficiently. */
17116 /* We need to check memory alignment for SSE mode since attribute
17117 can make operands unaligned. */
17122 {
17125 /* ix86_expand_vector_move_misalign() does not like constants ... */
17131 /* ... nor both arguments in memory. */
17139 }
17141 /* Make operand1 a register if it isn't already. */
17145 {
17148 }
17151 }
17153 /* Split 32-byte AVX unaligned load and store if needed. */
17155 static void
17157 {
17158 rtx m;
17165 {
17186 }
17189 {
17191 {
17198 }
17199 /* Normal *mov<mode>_internal pattern will handle
17200 unaligned loads just fine if misaligned_operand
17201 is true, and without the UNSPEC it can be combined
17202 with arithmetic instructions. */
17205 else
17207 }
17209 {
17211 {
17216 }
17217 else
17219 }
17220 else
17222 }
17224 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17225 straight to ix86_expand_vector_move. */
17226 /* Code generation for scalar reg-reg moves of single and double precision data:
17227 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17228 movaps reg, reg
17229 else
17230 movss reg, reg
17231 if (x86_sse_partial_reg_dependency == true)
17232 movapd reg, reg
17233 else
17234 movsd reg, reg
17236 Code generation for scalar loads of double precision data:
17237 if (x86_sse_split_regs == true)
17238 movlpd mem, reg (gas syntax)
17239 else
17240 movsd mem, reg
17242 Code generation for unaligned packed loads of single precision data
17243 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17244 if (x86_sse_unaligned_move_optimal)
17245 movups mem, reg
17247 if (x86_sse_partial_reg_dependency == true)
17248 {
17249 xorps reg, reg
17250 movlps mem, reg
17251 movhps mem+8, reg
17252 }
17253 else
17254 {
17255 movlps mem, reg
17256 movhps mem+8, reg
17257 }
17259 Code generation for unaligned packed loads of double precision data
17260 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17261 if (x86_sse_unaligned_move_optimal)
17262 movupd mem, reg
17264 if (x86_sse_split_regs == true)
17265 {
17266 movlpd mem, reg
17267 movhpd mem+8, reg
17268 }
17269 else
17270 {
17271 movsd mem, reg
17272 movhpd mem+8, reg
17273 }
17274 */
17276 void
17278 {
17287 {
17289 {
17293 {
17295 {
17298 }
17299 else
17301 }
17303 /* FALLTHRU */
17307 {
17322 }
17328 else
17336 }
17339 }
17343 {
17345 {
17349 {
17351 {
17354 }
17355 else
17357 }
17359 /* FALLTHRU */
17369 }
17372 }
17375 {
17376 /* Normal *mov<mode>_internal pattern will handle
17377 unaligned loads just fine if misaligned_operand
17378 is true, and without the UNSPEC it can be combined
17379 with arithmetic instructions. */
17385 /* ??? If we have typed data, then it would appear that using
17386 movdqu is the only way to get unaligned data loaded with
17387 integer type. */
17389 {
17391 {
17394 }
17396 /* We will eventually emit movups based on insn attributes. */
17400 }
17402 {
17403 rtx zero;
17406 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17407 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17409 {
17410 /* We will eventually emit movups based on insn attributes. */
17413 }
17415 /* When SSE registers are split into halves, we can avoid
17416 writing to the top half twice. */
17418 {
17421 }
17422 else
17423 {
17424 /* ??? Not sure about the best option for the Intel chips.
17425 The following would seem to satisfy; the register is
17426 entirely cleared, breaking the dependency chain. We
17427 then store to the upper half, with a dependency depth
17428 of one. A rumor has it that Intel recommends two movsd
17429 followed by an unpacklpd, but this is unconfirmed. And
17430 given that the dependency depth of the unpacklpd would
17431 still be one, I'm not sure why this would be better. */
17433 }
17439 }
17440 else
17441 {
17442 rtx t;
17445 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17446 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17448 {
17450 {
17453 }
17460 }
17464 else
17469 else
17478 }
17479 }
17481 {
17483 {
17486 /* We will eventually emit movups based on insn attributes. */
17488 }
17490 {
17492 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17493 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17495 /* We will eventually emit movups based on insn attributes. */
17497 else
17498 {
17503 }
17504 }
17505 else
17506 {
17511 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17512 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17514 {
17517 }
17518 else
17519 {
17524 }
17525 }
17526 }
17527 else
17529 }
17531 /* Helper function of ix86_fixup_binary_operands to canonicalize
17532 operand order. Returns true if the operands should be swapped. */
17534 static bool
17536 rtx operands[])
17537 {
17542 /* If the operation is not commutative, we can't do anything. */
17546 /* Highest priority is that src1 should match dst. */
17552 /* Next highest priority is that immediate constants come second. */
17558 /* Lowest priority is that memory references should come second. */
17565 }
17568 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17569 destination to use for the operation. If different from the true
17570 destination in operands[0], a copy operation will be required. */
17572 rtx
17574 rtx operands[])
17575 {
17580 /* Canonicalize operand order. */
17582 {
17583 rtx temp;
17585 /* It is invalid to swap operands of different modes. */
17591 }
17593 /* Both source operands cannot be in memory. */
17595 {
17596 /* Optimization: Only read from memory once. */
17598 {
17601 }
17604 else
17606 }
17608 /* If the destination is memory, and we do not have matching source
17609 operands, do things in registers. */
17613 /* Source 1 cannot be a constant. */
17617 /* Source 1 cannot be a non-matching memory. */
17621 /* Improve address combine. */
17630 }
17632 /* Similarly, but assume that the destination has already been
17633 set up properly. */
17635 void
17638 {
17641 }
17643 /* Attempt to expand a binary operator. Make the expansion closer to the
17644 actual machine, then just general_operand, which will allow 3 separate
17645 memory references (one output, two input) in a single insn. */
17647 void
17649 rtx operands[])
17650 {
17657 /* Emit the instruction. */
17661 {
17662 /* Reload doesn't know about the flags register, and doesn't know that
17663 it doesn't want to clobber it. We can only do this with PLUS. */
17666 }
17670 {
17671 /* This is going to be an LEA; avoid splitting it later. */
17673 }
17674 else
17675 {
17678 }
17680 /* Fix up the destination if needed. */
17683 }
17685 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
17686 the given OPERANDS. */
17688 void
17690 rtx operands[])
17691 {
17694 {
17697 }
17699 {
17702 }
17703 /* Optimize (__m128i) d | (__m128i) e and similar code
17704 when d and e are float vectors into float vector logical
17705 insn. In C/C++ without using intrinsics there is no other way
17706 to express vector logical operation on float vectors than
17707 to cast them temporarily to integer vectors. */
17709 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17718 {
17719 rtx dst;
17721 {
17728 {
17731 }
17732 else
17733 {
17738 }
17749 }
17750 }
17759 }
17761 /* Return TRUE or FALSE depending on whether the binary operator meets the
17762 appropriate constraints. */
17764 bool
17767 {
17772 /* Both source operands cannot be in memory. */
17776 /* Canonicalize operand order for commutative operators. */
17778 {
17782 }
17784 /* If the destination is memory, we must have a matching source operand. */
17788 /* Source 1 cannot be a constant. */
17792 /* Source 1 cannot be a non-matching memory. */
17794 /* Support "andhi/andsi/anddi" as a zero-extending move. */
17802 }
17804 /* Attempt to expand a unary operator. Make the expansion closer to the
17805 actual machine, then just general_operand, which will allow 2 separate
17806 memory references (one output, one input) in a single insn. */
17808 void
17810 rtx operands[])
17811 {
17818 /* If the destination is memory, and we do not have matching source
17819 operands, do things in registers. */
17822 {
17825 else
17827 }
17829 /* When source operand is memory, destination must match. */
17833 /* Emit the instruction. */
17837 {
17838 /* Reload doesn't know about the flags register, and doesn't know that
17839 it doesn't want to clobber it. */
17842 }
17843 else
17844 {
17847 }
17849 /* Fix up the destination if needed. */
17852 }
17854 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
17855 divisor are within the range [0-255]. */
17857 void
17860 {
17869 {
17882 }
17889 /* Use 8bit unsigned divimod if dividend and divisor are within
17890 the range [0-255]. */
17899 pc_rtx);
17904 /* Generate original signed/unsigned divimod. */
17909 /* Branch to the end. */
17913 /* Generate 8bit unsigned divide. */
17915 /* Don't use operands[0] for result of 8bit divide since not all
17916 registers support QImode ZERO_EXTRACT. */
17923 {
17926 }
17927 else
17928 {
17931 }
17933 /* Extract remainder from AH. */
17937 else
17938 {
17939 /* Need a new scratch register since the old one has result
17940 of 8bit divide. */
17944 }
17947 /* Zero extend quotient from AL. */
17953 }
17955 /* Whether it is OK to emit CFI directives when emitting asm code. */
17957 bool
17959 {
17961 }
17963 #define LEA_MAX_STALL (3)
17964 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
17966 /* Increase given DISTANCE in half-cycles according to
17967 dependencies between PREV and NEXT instructions.
17968 Add 1 half-cycle if there is no dependency and
17969 go to next cycle if there is some dependecy. */
17971 static unsigned int
17973 {
17990 }
17992 /* Function checks if instruction INSN defines register number
17993 REGNO1 or REGNO2. */
17995 static bool
17997 rtx insn)
17998 {
18006 {
18008 }
18011 }
18013 /* Function checks if instruction INSN uses register number
18014 REGNO as a part of address expression. */
18016 static bool
18018 {
18026 }
18028 /* Search backward for non-agu definition of register number REGNO1
18029 or register number REGNO2 in basic block starting from instruction
18030 START up to head of basic block or instruction INSN.
18032 Function puts true value into *FOUND var if definition was found
18033 and false otherwise.
18035 Distance in half-cycles between START and found instruction or head
18036 of BB is added to DISTANCE and returned. */
18038 static int
18042 {
18052 {
18054 {
18057 {
18060 {
18063 }
18064 }
18067 }
18072 }
18075 }
18077 /* Search backward for non-agu definition of register number REGNO1
18078 or register number REGNO2 in INSN's basic block until
18079 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18080 2. Reach neighbour BBs boundary, or
18081 3. Reach agu definition.
18082 Returns the distance between the non-agu definition point and INSN.
18083 If no definition point, returns -1. */
18085 static int
18087 rtx insn)
18088 {
18099 {
18100 edge e;
18101 edge_iterator ei;
18106 {
18109 }
18115 else
18116 {
18121 {
18122 int bb_dist
18128 {
18135 }
18136 }
18139 }
18140 }
18142 /* get_attr_type may modify recog data. We want to make sure
18143 that recog data is valid for instruction INSN, on which
18144 distance_non_agu_define is called. INSN is unchanged here. */
18151 }
18153 /* Return the distance in half-cycles between INSN and the next
18154 insn that uses register number REGNO in memory address added
18155 to DISTANCE. Return -1 if REGNO0 is set.
18157 Put true value into *FOUND if register usage was found and
18158 false otherwise.
18159 Put true value into *REDEFINED if register redefinition was
18160 found and false otherwise. */
18162 static int
18166 {
18175 {
18178 /* If insn and start belong to the same bb, set prev to insn,
18179 so the call to increase_distance will increase the distance
18180 between insns by 1. */
18182 }
18187 {
18189 {
18192 {
18193 /* Return DISTANCE if OP0 is used in memory
18194 address in NEXT. */
18197 }
18200 {
18201 /* Return -1 if OP0 is set in NEXT. */
18204 }
18207 }
18213 }
18216 }
18218 /* Return the distance between INSN and the next insn that uses
18219 register number REGNO0 in memory address. Return -1 if no such
18220 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18222 static int
18224 {
18236 {
18237 edge e;
18238 edge_iterator ei;
18243 {
18246 }
18252 else
18253 {
18259 {
18260 int bb_dist
18265 {
18272 }
18273 }
18276 }
18277 }
18283 }
18285 /* Define this macro to tune LEA priority vs ADD, it take effect when
18286 there is a dilemma of choicing LEA or ADD
18287 Negative value: ADD is more preferred than LEA
18288 Zero: Netrual
18289 Positive value: LEA is more preferred than ADD*/
18290 #define IX86_LEA_PRIORITY 0
18292 /* Return true if usage of lea INSN has performance advantage
18293 over a sequence of instructions. Instructions sequence has
18294 SPLIT_COST cycles higher latency than lea latency. */
18296 static bool
18299 {
18302 /* For Silvermont if using a 2-source or 3-source LEA for
18303 non-destructive destination purposes, or due to wanting
18304 ability to use SCALE, the use of LEA is justified. */
18306 {
18314 }
18320 {
18321 /* If there is no non AGU operand definition, no AGU
18322 operand usage and split cost is 0 then both lea
18323 and non lea variants have same priority. Currently
18324 we prefer lea for 64 bit code and non lea on 32 bit
18325 code. */
18328 else
18330 }
18332 /* With longer definitions distance lea is more preferable.
18333 Here we change it to take into account splitting cost and
18334 lea priority. */
18337 /* If there is no use in memory addess then we just check
18338 that split cost exceeds AGU stall. */
18342 /* If this insn has both backward non-agu dependence and forward
18343 agu dependence, the one with short distance takes effect. */
18345 }
18347 /* Return true if it is legal to clobber flags by INSN and
18348 false otherwise. */
18350 static bool
18352 {
18355 bitmap live;
18358 {
18360 {
18367 }
18373 }
18377 }
18379 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18380 move and add to avoid AGU stalls. */
18382 bool
18384 {
18387 /* Check if we need to optimize. */
18391 /* Check it is correct to split here. */
18399 /* We need to split only adds with non destructive
18400 destination operand. */
18403 else
18405 }
18407 /* Return true if we should emit lea instruction instead of mov
18408 instruction. */
18410 bool
18412 {
18415 /* Check if we need to optimize. */
18419 /* Use lea for reg to reg moves only. */
18427 }
18429 /* Return true if we need to split lea into a sequence of
18430 instructions to avoid AGU stalls. */
18432 bool
18434 {
18440 /* Check we need to optimize. */
18444 /* The "at least two components" test below might not catch simple
18445 move or zero extension insns if parts.base is non-NULL and parts.disp
18446 is const0_rtx as the only components in the address, e.g. if the
18447 register is %rbp or %r13. As this test is much cheaper and moves or
18448 zero extensions are the common case, do this check first. */
18454 /* Check if it is OK to split here. */
18461 /* There should be at least two components in the address. */
18466 /* We should not split into add if non legitimate pic
18467 operand is used as displacement. */
18482 /* Compute how many cycles we will add to execution time
18483 if split lea into a sequence of instructions. */
18485 {
18486 /* Have to use mov instruction if non desctructive
18487 destination form is used. */
18491 /* Have to add index to base if both exist. */
18495 /* Have to use shift and adds if scale is 2 or greater. */
18497 {
18502 else
18504 }
18506 /* Have to use add instruction with immediate if
18507 disp is non zero. */
18511 /* Subtract the price of lea. */
18513 }
18517 }
18519 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18520 matches destination. RTX includes clobber of FLAGS_REG. */
18522 static void
18525 {
18532 }
18534 /* Return true if regno1 def is nearest to the insn. */
18536 static bool
18538 {
18545 {
18547 {
18550 }
18556 }
18558 /* None of the regs is defined in the bb. */
18560 }
18562 /* Split lea instructions into a sequence of instructions
18563 which are executed on ALU to avoid AGU stalls.
18564 It is assumed that it is allowed to clobber flags register
18565 at lea position. */
18567 void
18569 {
18585 {
18588 }
18591 {
18594 }
18600 {
18601 /* Case r1 = r1 + ... */
18603 {
18604 /* If we have a case r1 = r1 + C * r2 then we
18605 should use multiplication which is very
18606 expensive. Assume cost model is wrong if we
18607 have such case here. */
18612 }
18613 else
18614 {
18615 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18619 /* Use shift for scaling. */
18628 }
18629 }
18631 {
18634 }
18635 else
18636 {
18638 {
18641 }
18643 {
18646 }
18647 else
18648 {
18653 else
18654 {
18655 rtx tmp1;
18657 /* Find better operand for SET instruction, depending
18658 on which definition is farther from the insn. */
18661 else
18671 }
18674 }
18678 }
18679 }
18681 /* Return true if it is ok to optimize an ADD operation to LEA
18682 operation to avoid flag register consumation. For most processors,
18683 ADD is faster than LEA. For the processors like BONNELL, if the
18684 destination register of LEA holds an actual address which will be
18685 used soon, LEA is better and otherwise ADD is better. */
18687 bool
18689 {
18694 /* If a = b + c, (a!=b && a!=c), must use lea form. */
18702 }
18704 /* Return true if destination reg of SET_BODY is shift count of
18705 USE_BODY. */
18707 static bool
18709 {
18710 rtx set_dest;
18711 rtx shift_rtx;
18714 /* Retrieve destination of SET_BODY. */
18716 {
18725 use_body))
18730 }
18732 /* Retrieve shift count of USE_BODY. */
18734 {
18746 }
18754 {
18757 /* Return true if shift count is dest of SET_BODY. */
18759 {
18760 /* Add check since it can be invoked before register
18761 allocation in pre-reload schedule. */
18767 }
18768 }
18771 }
18773 /* Return true if destination reg of SET_INSN is shift count of
18774 USE_INSN. */
18776 bool
18778 {
18781 }
18783 /* Return TRUE or FALSE depending on whether the unary operator meets the
18784 appropriate constraints. */
18786 bool
18790 {
18791 /* If one of operands is memory, source and destination must match. */
18797 }
18799 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
18800 are ok, keeping in mind the possible movddup alternative. */
18802 bool
18804 {
18810 }
18812 /* Post-reload splitter for converting an SF or DFmode value in an
18813 SSE register into an unsigned SImode. */
18815 void
18817 {
18828 /* Load up the value into the low element. We must ensure that the other
18829 elements are valid floats -- zero is the easiest such value. */
18831 {
18834 else
18836 }
18837 else
18838 {
18843 else
18845 }
18865 else
18870 }
18872 /* Convert an unsigned DImode value into a DFmode, using only SSE.
18873 Expects the 64-bit DImode to be supplied in a pair of integral
18874 registers. Requires SSE2; will use SSE3 if available. For x86_32,
18875 -mfpmath=sse, !optimize_size only. */
18877 void
18879 {
18883 rtx x;
18889 {
18892 }
18893 else
18894 {
18898 }
18906 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
18909 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
18910 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
18911 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
18912 (0x1.0p84 + double(fp_value_hi_xmm)).
18913 Note these exponents differ by 32. */
18917 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
18918 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
18927 /* Add the upper and lower DFmode values together. */
18930 else
18931 {
18935 }
18938 }
18940 /* Not used, but eases macroization of patterns. */
18941 void
18943 rtx input ATTRIBUTE_UNUSED)
18944 {
18946 }
18948 /* Convert an unsigned SImode value into a DFmode. Only currently used
18949 for SSE, but applicable anywhere. */
18951 void
18953 {
18954 REAL_VALUE_TYPE TWO31r;
18969 }
18971 /* Convert a signed DImode value into a DFmode. Only used for SSE in
18972 32-bit mode; otherwise we have a direct convert instruction. */
18974 void
18976 {
18977 REAL_VALUE_TYPE TWO32r;
18995 }
18997 /* Convert an unsigned SImode value into a SFmode, using only SSE.
18998 For x86_32, -mfpmath=sse, !optimize_size only. */
18999 void
19001 {
19002 REAL_VALUE_TYPE ONE16r;
19021 }
19023 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19024 a vector of unsigned ints VAL to vector of floats TARGET. */
19026 void
19028 {
19030 REAL_VALUE_TYPE TWO16r;
19037 else
19042 OPTAB_DIRECT);
19053 OPTAB_DIRECT);
19055 OPTAB_DIRECT);
19058 }
19060 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19061 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19062 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19063 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19065 rtx
19067 {
19068 REAL_VALUE_TYPE TWO31r;
19083 {
19089 }
19098 OPTAB_DIRECT);
19099 else
19100 {
19106 OPTAB_DIRECT);
19107 }
19110 }
19112 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19113 then replicate the value for all elements of the vector
19114 register. */
19116 rtx
19118 {
19120 rtvec v;
19124 {
19157 }
19158 }
19160 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19161 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19162 for an SSE register. If VECT is true, then replicate the mask for
19163 all elements of the vector register. If INVERT is true, then create
19164 a mask excluding the sign bit. */
19166 rtx
19168 {
19172 rtx v;
19173 rtx mask;
19175 /* Find the sign bit, sign extended to 2*HWI. */
19177 {
19201 else
19209 {
19212 }
19213 else
19214 {
19215 rtvec vec;
19221 {
19224 }
19225 else
19235 }
19240 }
19245 /* Force this value into the low part of a fp vector constant. */
19254 }
19256 /* Generate code for floating point ABS or NEG. */
19258 void
19260 rtx operands[])
19261 {
19272 {
19278 }
19280 /* NEG and ABS performed with SSE use bitwise mask operations.
19281 Create the appropriate mask now. */
19284 else
19294 {
19296 rtvec par;
19301 else
19302 {
19305 }
19307 }
19308 else
19310 }
19312 /* Expand a copysign operation. Special case operand 0 being a constant. */
19314 void
19316 {
19330 else
19334 {
19341 {
19344 else
19345 {
19349 }
19350 }
19360 else
19364 }
19365 else
19366 {
19376 else
19380 }
19381 }
19383 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19384 be a constant, and so has already been expanded into a vector constant. */
19386 void
19388 {
19404 {
19407 }
19408 }
19410 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19411 so we have to do two masks. */
19413 void
19415 {
19430 {
19431 /* Shouldn't happen often (it's useless, obviously), but when it does
19432 we'd generate incorrect code if we continue below. */
19435 }
19438 {
19449 }
19450 else
19451 {
19453 {
19455 }
19457 {
19461 }
19465 {
19468 }
19470 {
19475 }
19477 }
19481 }
19483 /* Return TRUE or FALSE depending on whether the first SET in INSN
19484 has source and destination with matching CC modes, and that the
19485 CC mode is at least as constrained as REQ_MODE. */
19487 bool
19489 {
19490 rtx set;
19501 {
19511 /* FALLTHRU */
19515 /* FALLTHRU */
19519 /* FALLTHRU */
19533 }
19536 }
19538 /* Generate insn patterns to do an integer compare of OPERANDS. */
19540 static rtx
19542 {
19549 /* This is very simple, but making the interface the same as in the
19550 FP case makes the rest of the code easier. */
19554 /* Return the test that should be put into the flags user, i.e.
19555 the bcc, scc, or cmov instruction. */
19557 }
19559 /* Figure out whether to use ordered or unordered fp comparisons.
19560 Return the appropriate mode to use. */
19562 enum machine_mode
19564 {
19565 /* ??? In order to make all comparisons reversible, we do all comparisons
19566 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19567 all forms trapping and nontrapping comparisons, we can make inequality
19568 comparisons trapping again, since it results in better code when using
19569 FCOM based compares. */
19571 }
19573 enum machine_mode
19575 {
19579 {
19582 }
19585 {
19586 /* Only zero flag is needed. */
19590 /* Codes needing carry flag. */
19593 /* Detect overflow checks. They need just the carry flag. */
19597 else
19602 /* Codes possibly doable only with sign flag when
19603 comparing against zero. */
19608 else
19609 /* For other cases Carry flag is not required. */
19611 /* Codes doable only with sign flag when comparing
19612 against zero, but we miss jump instruction for it
19613 so we need to use relational tests against overflow
19614 that thus needs to be zero. */
19619 else
19621 /* strcmp pattern do (use flags) and combine may ask us for proper
19622 mode. */
19627 }
19628 }
19630 /* Return the fixed registers used for condition codes. */
19632 static bool
19634 {
19638 }
19640 /* If two condition code modes are compatible, return a condition code
19641 mode which is compatible with both. Otherwise, return
19642 VOIDmode. */
19644 static enum machine_mode
19646 {
19663 {
19677 {
19691 }
19695 /* These are only compatible with themselves, which we already
19696 checked above. */
19698 }
19699 }
19702 /* Return a comparison we can do and that it is equivalent to
19703 swap_condition (code) apart possibly from orderedness.
19704 But, never change orderedness if TARGET_IEEE_FP, returning
19705 UNKNOWN in that case if necessary. */
19707 static enum rtx_code
19709 {
19711 {
19722 }
19723 }
19725 /* Return cost of comparison CODE using the best strategy for performance.
19726 All following functions do use number of instructions as a cost metrics.
19727 In future this should be tweaked to compute bytes for optimize_size and
19728 take into account performance of various instructions on various CPUs. */
19730 static int
19732 {
19735 /* The cost of code using bit-twiddling on %ah. */
19737 {
19760 }
19763 {
19770 }
19771 }
19773 /* Return strategy to use for floating-point. We assume that fcomi is always
19774 preferrable where available, since that is also true when looking at size
19775 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
19777 enum ix86_fpcmp_strategy
19779 {
19780 /* Do fcomi/sahf based test when profitable. */
19789 }
19791 /* Swap, force into registers, or otherwise massage the two operands
19792 to a fp comparison. The operands are updated in place; the new
19793 comparison code is returned. */
19795 static enum rtx_code
19797 {
19803 /* All of the unordered compare instructions only work on registers.
19804 The same is true of the fcomi compare instructions. The XFmode
19805 compare instructions require registers except when comparing
19806 against zero or when converting operand 1 from fixed point to
19807 floating point. */
19816 {
19819 }
19820 else
19821 {
19822 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
19823 things around if they appear profitable, otherwise force op0
19824 into a register. */
19830 {
19833 {
19834 rtx tmp;
19837 }
19838 }
19844 {
19849 {
19852 }
19853 else
19855 }
19856 }
19858 /* Try to rearrange the comparison to make it cheaper. */
19862 {
19863 rtx tmp;
19868 }
19873 }
19875 /* Convert comparison codes we use to represent FP comparison to integer
19876 code that will result in proper branch. Return UNKNOWN if no such code
19877 is available. */
19879 enum rtx_code
19881 {
19883 {
19906 }
19907 }
19909 /* Generate insn patterns to do a floating point compare of OPERANDS. */
19911 static rtx
19913 {
19920 /* Do fcomi/sahf based test when profitable. */
19922 {
19927 tmp);
19935 tmp);
19944 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
19951 /* In the unordered case, we have to check C2 for NaN's, which
19952 doesn't happen to work out to anything nice combination-wise.
19953 So do some bit twiddling on the value we've got in AH to come
19954 up with an appropriate set of condition codes. */
19958 {
19962 {
19965 }
19966 else
19967 {
19973 }
19978 {
19983 }
19984 else
19985 {
19988 }
19993 {
19996 }
19997 else
19998 {
20002 }
20007 {
20013 }
20014 else
20015 {
20018 }
20023 {
20028 }
20029 else
20030 {
20033 }
20038 {
20043 }
20044 else
20045 {
20048 }
20062 }
20067 }
20069 /* Return the test that should be put into the flags user, i.e.
20070 the bcc, scc, or cmov instruction. */
20073 const0_rtx);
20074 }
20076 static rtx
20078 {
20079 rtx ret;
20085 {
20088 }
20089 else
20093 }
20095 void
20097 {
20099 rtx tmp;
20102 {
20109 simple:
20113 pc_rtx);
20121 /* Expand DImode branch into multiple compare+branch. */
20122 {
20128 {
20131 }
20138 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20139 avoid two branches. This costs one extra insn, so disable when
20140 optimizing for size. */
20145 {
20163 }
20165 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20166 op1 is a constant and the low word is zero, then we can just
20167 examine the high word. Similarly for low word -1 and
20168 less-or-equal-than or greater-than. */
20172 {
20175 {
20178 }
20182 {
20185 }
20189 }
20191 /* Otherwise, we need two or three jumps. */
20200 {
20214 }
20216 /*
20217 * a < b =>
20218 * if (hi(a) < hi(b)) goto true;
20219 * if (hi(a) > hi(b)) goto false;
20220 * if (lo(a) < lo(b)) goto true;
20221 * false:
20222 */
20234 }
20239 }
20240 }
20242 /* Split branch based on floating point condition. */
20243 void
20246 {
20247 rtx condition;
20248 rtx i;
20251 {
20256 }
20259 tmp);
20267 }
20269 void
20271 {
20272 rtx ret;
20279 }
20281 /* Expand comparison setting or clearing carry flag. Return true when
20282 successful and set pop for the operation. */
20283 static bool
20285 {
20289 /* Do not handle double-mode compares that go through special path. */
20294 {
20299 /* Shortcut: following common codes never translate
20300 into carry flag compares. */
20305 /* These comparisons require zero flag; swap operands so they won't. */
20308 {
20313 }
20315 /* Try to expand the comparison and verify that we end up with
20316 carry flag based comparison. This fails to be true only when
20317 we decide to expand comparison using arithmetic that is not
20318 too common scenario. */
20327 else
20336 }
20342 {
20347 /* Convert a==0 into (unsigned)a<1. */
20356 /* Convert a>b into b<a or a>=b-1. */
20360 {
20362 /* Bail out on overflow. We still can swap operands but that
20363 would force loading of the constant into register. */
20368 }
20369 else
20370 {
20375 }
20378 /* Convert a>=0 into (unsigned)a<0x80000000. */
20396 }
20397 /* Swapping operands may cause constant to appear as first operand. */
20399 {
20403 }
20407 }
20409 bool
20411 {
20435 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20436 HImode insns, we'd be swallowed in word prefix ops. */
20442 {
20446 HOST_WIDE_INT diff;
20449 /* Sign bit compares are better done using shifts than we do by using
20450 sbb. */
20453 {
20454 /* Detect overlap between destination and compare sources. */
20458 {
20459 rtx flags;
20468 {
20470 compare_code
20472 }
20474 /* To simplify rest of code, restrict to the GEU case. */
20476 {
20482 }
20483 else
20484 {
20487 reverse_condition_maybe_unordered
20489 else
20492 }
20501 else
20504 }
20505 else
20506 {
20509 else
20510 {
20515 }
20517 }
20520 {
20521 /*
20522 * cmpl op0,op1
20523 * sbbl dest,dest
20524 * [addl dest, ct]
20525 *
20526 * Size 5 - 8.
20527 */
20532 }
20534 {
20535 /*
20536 * cmpl op0,op1
20537 * sbbl dest,dest
20538 * orl $ct, dest
20539 *
20540 * Size 8.
20541 */
20545 }
20547 {
20548 /*
20549 * cmpl op0,op1
20550 * sbbl dest,dest
20551 * notl dest
20552 * [addl dest, cf]
20553 *
20554 * Size 8 - 11.
20555 */
20561 }
20562 else
20563 {
20564 /*
20565 * cmpl op0,op1
20566 * sbbl dest,dest
20567 * [notl dest]
20568 * andl cf - ct, dest
20569 * [addl dest, ct]
20570 *
20571 * Size 8 - 11.
20572 */
20575 {
20579 }
20589 }
20595 }
20598 {
20601 HOST_WIDE_INT tmp;
20606 {
20609 /* We may be reversing unordered compare to normal compare, that
20610 is not valid in general (we may convert non-trapping condition
20611 to trapping one), however on i386 we currently emit all
20612 comparisons unordered. */
20615 }
20616 else
20617 {
20620 }
20621 }
20626 {
20631 {
20636 }
20637 }
20639 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20643 {
20644 /* If lea code below could be used, only optimize
20645 if it results in a 2 insn sequence. */
20651 {
20652 /*
20653 * notl op1 (if necessary)
20654 * sarl $31, op1
20655 * orl cf, op1
20656 */
20658 {
20662 }
20673 }
20674 }
20682 {
20683 /*
20684 * xorl dest,dest
20685 * cmpl op1,op2
20686 * setcc dest
20687 * lea cf(dest*(ct-cf)),dest
20688 *
20689 * Size 14.
20690 *
20691 * This also catches the degenerate setcc-only case.
20692 */
20694 rtx tmp;
20700 /* On x86_64 the lea instruction operates on Pmode, so we need
20701 to get arithmetics done in proper mode to match. */
20704 else
20705 {
20706 rtx out1;
20709 nops++;
20711 {
20713 nops++;
20714 }
20715 }
20717 {
20719 nops++;
20720 }
20722 {
20725 else
20727 }
20732 }
20734 /*
20735 * General case: Jumpful:
20736 * xorl dest,dest cmpl op1, op2
20737 * cmpl op1, op2 movl ct, dest
20738 * setcc dest jcc 1f
20739 * decl dest movl cf, dest
20740 * andl (cf-ct),dest 1:
20741 * addl ct,dest
20742 *
20743 * Size 20. Size 14.
20744 *
20745 * This is reasonably steep, but branch mispredict costs are
20746 * high on modern cpus, so consider failing only if optimizing
20747 * for space.
20748 */
20753 {
20755 {
20762 {
20765 /* We may be reversing unordered compare to normal compare,
20766 that is not valid in general (we may convert non-trapping
20767 condition to trapping one), however on i386 we currently
20768 emit all comparisons unordered. */
20770 }
20771 else
20772 {
20776 }
20777 }
20780 {
20781 /* notl op1 (if needed)
20782 sarl $31, op1
20783 andl (cf-ct), op1
20784 addl ct, op1
20786 For x < 0 (resp. x <= -1) there will be no notl,
20787 so if possible swap the constants to get rid of the
20788 complement.
20789 True/false will be -1/0 while code below (store flag
20790 followed by decrement) is 0/-1, so the constants need
20791 to be exchanged once more. */
20794 {
20797 }
20798 else
20799 {
20803 }
20806 }
20807 else
20808 {
20812 constm1_rtx,
20814 }
20826 }
20827 }
20830 {
20831 /* Try a few things more with specific constants and a variable. */
20833 optab op;
20839 /* If one of the two operands is an interesting constant, load a
20840 constant with the above and mask it in with a logical operation. */
20843 {
20849 else
20851 }
20853 {
20859 else
20861 }
20862 else
20869 /* Recurse to get the constant loaded. */
20873 /* Mask in the interesting variable. */
20875 OPTAB_WIDEN);
20880 }
20882 /*
20883 * For comparison with above,
20884 *
20885 * movl cf,dest
20886 * movl ct,tmp
20887 * cmpl op1,op2
20888 * cmovcc tmp,dest
20889 *
20890 * Size 15.
20891 */
20913 }
20915 /* Swap, force into registers, or otherwise massage the two operands
20916 to an sse comparison with a mask result. Thus we differ a bit from
20917 ix86_prepare_fp_compare_args which expects to produce a flags result.
20919 The DEST operand exists to help determine whether to commute commutative
20920 operators. The POP0/POP1 operands are updated in place. The new
20921 comparison code is returned, or UNKNOWN if not implementable. */
20923 static enum rtx_code
20926 {
20927 rtx tmp;
20930 {
20933 /* AVX supports all the needed comparisons. */
20936 /* We have no LTGT as an operator. We could implement it with
20937 NE & ORDERED, but this requires an extra temporary. It's
20938 not clear that it's worth it. */
20945 /* These are supported directly. */
20952 /* AVX has 3 operand comparisons, no need to swap anything. */
20955 /* For commutative operators, try to canonicalize the destination
20956 operand to be first in the comparison - this helps reload to
20957 avoid extra moves. */
20960 /* FALLTHRU */
20966 /* These are not supported directly before AVX, and furthermore
20967 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
20968 comparison operands to transform into something that is
20969 supported. */
20978 }
20981 }
20983 /* Detect conditional moves that exactly match min/max operational
20984 semantics. Note that this is IEEE safe, as long as we don't
20985 interchange the operands.
20987 Returns FALSE if this conditional move doesn't match a MIN/MAX,
20988 and TRUE if the operation is successful and instructions are emitted. */
20990 static bool
20993 {
20996 rtx tmp;
20999 ;
21001 {
21005 }
21006 else
21013 else
21018 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21019 but MODE may be a vector mode and thus not appropriate. */
21021 {
21023 rtvec v;
21028 }
21029 else
21030 {
21033 }
21037 }
21039 /* Expand an sse vector comparison. Return the register with the result. */
21041 static rtx
21044 {
21048 /* In general case result of comparison can differ from operands' type. */
21051 /* In AVX512F the result of comparison is an integer mask. */
21053 rtx x;
21056 {
21061 }
21062 else
21075 /* Compare patterns for int modes are unspec in AVX512F only. */
21077 {
21081 {
21090 }
21093 {
21096 }
21097 }
21101 {
21104 }
21105 else
21109 }
21111 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21112 operations. This is used for both scalar and vector conditional moves. */
21114 static void
21116 {
21120 /* In AVX512F the result of comparison is an integer mask. */
21128 {
21130 }
21133 {
21137 }
21140 {
21145 }
21148 {
21152 }
21155 {
21163 op_true,
21164 op_false)));
21165 }
21166 else
21167 {
21177 {
21191 {
21198 }
21213 {
21220 }
21238 }
21241 {
21245 }
21246 else
21247 {
21253 else
21265 }
21266 }
21267 }
21269 /* Expand a floating-point conditional move. Return true if successful. */
21271 bool
21273 {
21281 {
21284 /* Since we've no cmove for sse registers, don't force bad register
21285 allocation just to gain access to it. Deny movcc when the
21286 comparison mode doesn't match the move mode. */
21305 }
21312 /* The floating point conditional move instructions don't directly
21313 support conditions resulting from a signed integer comparison. */
21317 {
21322 }
21329 }
21331 /* Expand a floating-point vector conditional move; a vcond operation
21332 rather than a movcc operation. */
21334 bool
21336 {
21338 rtx cmp;
21343 {
21344 rtx temp;
21346 {
21363 }
21365 OPTAB_DIRECT);
21368 }
21378 }
21380 /* Expand a signed/unsigned integral vector conditional move. */
21382 bool
21384 {
21394 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21395 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21404 {
21408 {
21414 }
21417 {
21423 }
21424 }
21433 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21437 ;
21438 else
21439 {
21440 /* Canonicalize the comparison to EQ, GT, GTU. */
21442 {
21459 /* FALLTHRU */
21469 }
21471 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21473 {
21475 {
21477 /* SSE4.1 supports EQ. */
21484 /* SSE4.2 supports GT/GTU. */
21491 }
21492 }
21494 /* Unsigned parallel compare is not supported by the hardware.
21495 Play some tricks to turn this into a signed comparison
21496 against 0. */
21498 {
21502 {
21509 {
21514 {
21523 }
21524 /* Subtract (-(INT MAX) - 1) from both operands to make
21525 them signed. */
21536 }
21543 /* Perform a parallel unsigned saturating subtraction. */
21556 }
21557 }
21558 }
21560 /* Allow the comparison to be done in one mode, but the movcc to
21561 happen in another mode. */
21563 {
21566 }
21567 else
21568 {
21574 }
21579 }
21581 static bool
21583 {
21586 {
21590 op1));
21595 op1));
21607 }
21608 }
21610 /* Expand a variable vector permutation. */
21612 void
21614 {
21625 /* Number of elements in the vector. */
21634 {
21636 {
21637 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
21638 an constant shuffle operand. With a tiny bit of effort we can
21639 use VPERMD instead. A re-interpretation stall for V4DFmode is
21640 unfortunate but there's no avoiding it.
21641 Similarly for V16HImode we don't have instructions for variable
21642 shuffling, while for V32QImode we can use after preparing suitable
21643 masks vpshufb; vpshufb; vpermq; vpor. */
21646 {
21650 }
21651 else
21652 {
21656 }
21659 /* Replicate the low bits of the V4DImode mask into V8SImode:
21660 mask = { A B C D }
21661 t1 = { A A B B C C D D }. */
21669 else
21672 /* Multiply the shuffle indicies by two. */
21674 OPTAB_DIRECT);
21676 /* Add one to the odd shuffle indicies:
21677 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
21679 {
21682 }
21686 OPTAB_DIRECT);
21688 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
21693 }
21696 {
21698 /* The VPERMD and VPERMPS instructions already properly ignore
21699 the high bits of the shuffle elements. No need for us to
21700 perform an AND ourselves. */
21702 {
21707 }
21708 else
21709 {
21715 }
21722 else
21723 {
21729 }
21733 /* By combining the two 128-bit input vectors into one 256-bit
21734 input vector, we can use VPERMD and VPERMPS for the full
21735 two-operand shuffle. */
21767 /* From mask create two adjusted masks, which contain the same
21768 bits as mask in the low 7 bits of each vector element.
21769 The first mask will have the most significant bit clear
21770 if it requests element from the same 128-bit lane
21771 and MSB set if it requests element from the other 128-bit lane.
21772 The second mask will have the opposite values of the MSB,
21773 and additionally will have its 128-bit lanes swapped.
21774 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
21775 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
21776 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
21777 stands for other 12 bytes. */
21778 /* The bit whether element is from the same lane or the other
21779 lane is bit 4, so shift it up by 3 to the MSB position. */
21783 /* Clear MSB bits from the mask just in case it had them set. */
21785 /* After this t1 will have MSB set for elements from other lane. */
21787 /* Clear bits other than MSB. */
21789 /* Or in the lower bits from mask into t3. */
21791 /* And invert MSB bits in t1, so MSB is set for elements from the same
21792 lane. */
21794 /* Swap 128-bit lanes in t3. */
21799 /* And or in the lower bits from mask into t1. */
21802 {
21803 /* Each of these shuffles will put 0s in places where
21804 element from the other 128-bit lane is needed, otherwise
21805 will shuffle in the requested value. */
21809 /* For t3 the 128-bit lanes are swapped again. */
21814 /* And oring both together leads to the result. */
21821 }
21824 /* Similarly to the above one_operand_shuffle code,
21825 just for repeated twice for each operand. merge_two:
21826 code will merge the two results together. */
21850 }
21851 }
21854 {
21855 /* The XOP VPPERM insn supports three inputs. By ignoring the
21856 one_operand_shuffle special case, we avoid creating another
21857 set of constant vectors in memory. */
21860 /* mask = mask & {2*w-1, ...} */
21862 }
21863 else
21864 {
21865 /* mask = mask & {w-1, ...} */
21867 }
21875 /* For non-QImode operations, convert the word permutation control
21876 into a byte permutation control. */
21878 {
21883 /* Convert mask to vector of chars. */
21886 /* Replicate each of the input bytes into byte positions:
21887 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
21888 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
21889 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
21896 else
21899 /* Convert it into the byte positions by doing
21900 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
21906 }
21908 /* The actual shuffle operations all operate on V16QImode. */
21913 {
21920 }
21922 {
21929 }
21930 else
21931 {
21935 /* Shuffle the two input vectors independently. */
21941 merge_two:
21942 /* Then merge them together. The key is whether any given control
21943 element contained a bit set that indicates the second word. */
21947 {
21948 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
21949 more shuffle to convert the V2DI input mask into a V4SI
21950 input mask. At which point the masking that expand_int_vcond
21951 will work as desired. */
21959 }
21981 }
21982 }
21984 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
21985 true if we should do zero extension, else sign extension. HIGH_P is
21986 true if we want the N/2 high elements, else the low elements. */
21988 void
21990 {
21992 rtx tmp;
21995 {
22001 {
22005 else
22008 extract
22014 else
22017 extract
22023 else
22026 extract
22032 else
22035 extract
22041 else
22044 extract
22050 else
22056 else
22062 else
22067 }
22070 {
22073 }
22075 {
22076 /* Shift higher 8 bytes to lower 8 bytes. */
22081 }
22082 else
22086 }
22087 else
22088 {
22092 {
22096 else
22102 else
22108 else
22113 }
22117 else
22124 }
22125 }
22127 /* Expand conditional increment or decrement using adb/sbb instructions.
22128 The default case using setcc followed by the conditional move can be
22129 done by generic code. */
22130 bool
22132 {
22134 rtx flags;
22136 rtx compare_op;
22154 {
22157 }
22160 {
22164 reverse_condition_maybe_unordered
22166 else
22168 }
22172 /* Construct either adc or sbb insn. */
22174 {
22176 {
22191 }
22192 }
22193 else
22194 {
22196 {
22211 }
22212 }
22216 }
22219 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22220 but works for floating pointer parameters and nonoffsetable memories.
22221 For pushes, it returns just stack offsets; the values will be saved
22222 in the right order. Maximally three parts are generated. */
22224 static int
22226 {
22231 else
22237 /* Optimize constant pool reference to immediates. This is used by fp
22238 moves, that force all constants to memory to allow combining. */
22240 {
22244 }
22247 {
22248 /* The only non-offsetable memories we handle are pushes. */
22257 }
22260 {
22262 /* Caution: if we looked through a constant pool memory above,
22263 the operand may actually have a different mode now. That's
22264 ok, since we want to pun this all the way back to an integer. */
22268 }
22271 {
22274 else
22275 {
22279 {
22283 }
22285 {
22290 }
22292 {
22293 REAL_VALUE_TYPE r;
22298 {
22305 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22306 long double may not be 80-bit. */
22315 }
22318 }
22319 else
22321 }
22322 }
22323 else
22324 {
22328 {
22331 {
22335 }
22337 {
22341 }
22343 {
22344 REAL_VALUE_TYPE r;
22350 /* Do not use shift by 32 to avoid warning on 32bit systems. */
22353 = gen_int_mode
22356 DImode);
22357 else
22364 = gen_int_mode
22367 DImode);
22368 else
22370 }
22371 else
22373 }
22374 }
22377 }
22379 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22380 Return false when normal moves are needed; true when all required
22381 insns have been emitted. Operands 2-4 contain the input values
22382 int the correct order; operands 5-7 contain the output values. */
22384 void
22386 {
22394 /* The DFmode expanders may ask us to move double.
22395 For 64bit target this is single move. By hiding the fact
22396 here we simplify i386.md splitters. */
22398 {
22399 /* Optimize constant pool reference to immediates. This is used by
22400 fp moves, that force all constants to memory to allow combining. */
22407 {
22410 }
22411 else
22416 }
22418 /* The only non-offsettable memory we handle is push. */
22421 else
22428 /* When emitting push, take care for source operands on the stack. */
22431 {
22434 /* Compensate for the stack decrement by 4. */
22439 /* src_base refers to the stack pointer and is
22440 automatically decreased by emitted push. */
22444 }
22446 /* We need to do copy in the right order in case an address register
22447 of the source overlaps the destination. */
22449 {
22450 rtx tmp;
22453 {
22457 collisions++;
22458 }
22460 /* Collision in the middle part can be handled by reordering. */
22462 {
22465 }
22469 {
22471 {
22474 }
22475 else
22476 {
22479 }
22480 }
22482 /* If there are more collisions, we can't handle it by reordering.
22483 Do an lea to the last part and use only one colliding move. */
22485 {
22486 rtx base;
22492 /* Handle the case when the last part isn't valid for lea.
22493 Happens in 64-bit mode storing the 12-byte XFmode. */
22500 {
22503 }
22504 }
22505 }
22508 {
22510 {
22512 {
22517 }
22519 {
22522 }
22523 }
22524 else
22525 {
22526 /* In 64bit mode we don't have 32bit push available. In case this is
22527 register, it is OK - we will just use larger counterpart. We also
22528 retype memory - these comes from attempt to avoid REX prefix on
22529 moving of second half of TFmode value. */
22531 {
22533 {
22544 }
22548 }
22549 }
22553 }
22555 /* Choose correct order to not overwrite the source before it is copied. */
22565 {
22567 {
22570 }
22571 }
22572 else
22573 {
22575 {
22578 }
22579 }
22581 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
22583 {
22592 }
22598 }
22600 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
22601 left shift by a constant, either using a single shift or
22602 a sequence of add instructions. */
22604 static void
22606 {
22612 {
22616 }
22617 else
22618 {
22621 }
22622 }
22624 void
22626 {
22635 {
22640 {
22646 }
22647 else
22648 {
22656 }
22658 }
22665 {
22666 /* Assuming we've chosen a QImode capable registers, then 1 << N
22667 can be done with two 32/64-bit shifts, no branches, no cmoves. */
22669 {
22685 }
22687 /* Otherwise, we can get the same results by manually performing
22688 a bit extract operation on bit 5/6, and then performing the two
22689 shifts. The two methods of getting 0/1 into low/high are exactly
22690 the same size. Avoiding the shift in the bit extract case helps
22691 pentium4 a bit; no one else seems to care much either way. */
22692 else
22693 {
22698 HOST_WIDE_INT bits;
22699 rtx x;
22702 {
22708 }
22709 else
22710 {
22716 }
22720 else
22728 }
22733 }
22736 {
22737 /* For -1 << N, we can avoid the shld instruction, because we
22738 know that we're shifting 0...31/63 ones into a -1. */
22742 else
22744 }
22745 else
22746 {
22754 }
22759 {
22765 }
22766 else
22767 {
22772 }
22773 }
22775 void
22777 {
22787 {
22792 {
22798 }
22800 {
22809 }
22810 else
22811 {
22819 }
22820 }
22821 else
22822 {
22834 {
22842 scratch));
22843 }
22844 else
22845 {
22850 }
22851 }
22852 }
22854 void
22856 {
22866 {
22871 {
22878 }
22879 else
22880 {
22888 }
22889 }
22890 else
22891 {
22903 {
22909 scratch));
22910 }
22911 else
22912 {
22917 }
22918 }
22919 }
22921 /* Predict just emitted jump instruction to be taken with probability PROB. */
22922 static void
22924 {
22928 }
22930 /* Helper function for the string operations below. Dest VARIABLE whether
22931 it is aligned to VALUE bytes. If true, jump to the label. */
22932 static rtx
22934 {
22939 else
22945 else
22948 }
22950 /* Adjust COUNTER by the VALUE. */
22951 static void
22953 {
22958 }
22960 /* Zero extend possibly SImode EXP to Pmode register. */
22961 rtx
22963 {
22965 }
22967 /* Divide COUNTREG by SCALE. */
22968 static rtx
22970 {
22971 rtx sc;
22983 }
22985 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
22986 DImode for constant loop counts. */
22988 static enum machine_mode
22990 {
22998 }
23000 /* Copy the address to a Pmode register. This is used for x32 to
23001 truncate DImode TLS address to a SImode register. */
23003 static rtx
23005 {
23008 else
23009 {
23012 }
23013 }
23015 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23016 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23017 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23018 memory by VALUE (supposed to be in MODE).
23020 The size is rounded down to whole number of chunk size moved at once.
23021 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23024 static void
23029 {
23035 rtx size;
23044 /* Those two should combine. */
23046 {
23050 }
23057 /* This assert could be relaxed - in this case we'll need to compute
23058 smallest power of two, containing in PIECE_SIZE_N and pass it to
23059 offset_address. */
23065 {
23069 /* When unrolling for chips that reorder memory reads and writes,
23070 we can save registers by using single temporary.
23071 Also using 4 temporaries is overkill in 32bit mode. */
23073 {
23075 {
23077 {
23078 destmem =
23080 srcmem =
23082 }
23084 }
23085 }
23086 else
23087 {
23091 {
23094 {
23095 srcmem =
23097 }
23099 }
23101 {
23103 {
23104 destmem =
23106 }
23108 }
23109 }
23110 }
23111 else
23113 {
23115 destmem =
23118 }
23128 {
23134 else
23136 }
23137 else
23145 {
23150 }
23152 }
23154 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23155 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23156 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23157 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23158 ORIG_VALUE is the original value passed to memset to fill the memory with.
23159 Other arguments have same meaning as for previous function. */
23161 static void
23164 rtx count,
23166 {
23167 rtx destexp;
23168 rtx srcexp;
23169 rtx countreg;
23170 HOST_WIDE_INT rounded_count;
23172 /* If possible, it is shorter to use rep movs.
23173 TODO: Maybe it is better to move this logic to decide_alg. */
23184 {
23188 }
23189 else
23192 {
23197 }
23202 {
23205 }
23206 else
23207 {
23211 {
23215 }
23216 else
23219 {
23224 }
23225 else
23226 {
23229 }
23232 }
23233 }
23235 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23236 DESTMEM.
23237 SRC is passed by pointer to be updated on return.
23238 Return value is updated DST. */
23239 static rtx
23241 HOST_WIDE_INT size_to_move)
23242 {
23248 /* Find the widest mode in which we could perform moves.
23249 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23250 it until move of such size is supported. */
23255 {
23259 }
23261 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23262 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23264 {
23269 {
23273 }
23274 }
23280 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23284 {
23285 /* We move from memory to memory, so we'll need to do it via
23286 a temporary register. */
23297 piece_size);
23299 piece_size);
23300 }
23302 /* Update DST and SRC rtx. */
23305 }
23307 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23308 static void
23311 {
23314 {
23319 /* For now MAX_SIZE should be a power of 2. This assert could be
23320 relaxed, but it'll require a bit more complicated epilogue
23321 expanding. */
23324 {
23327 }
23329 }
23331 {
23337 }
23339 /* When there are stringops, we can cheaply increase dest and src pointers.
23340 Otherwise we save code size by maintaining offset (zero is readily
23341 available from preceding rep operation) and using x86 addressing modes.
23342 */
23344 {
23346 {
23353 }
23355 {
23362 }
23364 {
23371 }
23372 }
23373 else
23374 {
23376 rtx tmp;
23379 {
23390 }
23392 {
23405 }
23407 {
23416 }
23417 }
23418 }
23420 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23421 with value PROMOTED_VAL.
23422 SRC is passed by pointer to be updated on return.
23423 Return value is updated DST. */
23424 static rtx
23426 HOST_WIDE_INT size_to_move)
23427 {
23433 /* Find the widest mode in which we could perform moves.
23434 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23435 it until move of such size is supported. */
23440 {
23443 }
23450 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23454 {
23456 {
23459 piece_size);
23461 }
23469 piece_size);
23470 }
23472 /* Update DST rtx. */
23474 }
23475 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23476 static void
23479 {
23480 count =
23486 }
23488 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23489 static void
23492 {
23493 rtx dest;
23496 {
23501 /* For now MAX_SIZE should be a power of 2. This assert could be
23502 relaxed, but it'll require a bit more complicated epilogue
23503 expanding. */
23506 {
23508 {
23511 else
23513 }
23514 }
23516 }
23518 {
23521 }
23523 {
23526 {
23531 }
23532 else
23533 {
23542 }
23545 }
23547 {
23550 {
23553 }
23554 else
23555 {
23560 }
23563 }
23565 {
23571 }
23573 {
23579 }
23581 {
23587 }
23588 }
23590 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
23591 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
23592 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
23593 ignored.
23594 Return value is updated DESTMEM. */
23595 static rtx
23600 {
23603 {
23605 {
23608 {
23611 else
23613 }
23614 else
23620 }
23621 }
23623 }
23625 /* Test if COUNT&SIZE is nonzero and if so, expand movme
23626 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
23627 and jump to DONE_LABEL. */
23628 static void
23634 {
23637 rtx modesize;
23640 /* If we do not have vector value to copy, we must reduce size. */
23642 {
23644 {
23649 }
23650 else
23652 }
23653 else
23654 {
23655 /* Choose appropriate vector mode. */
23661 }
23666 {
23669 else
23670 {
23673 }
23675 }
23681 {
23685 }
23687 {
23690 else
23691 {
23694 }
23696 }
23702 }
23704 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
23705 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
23706 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
23707 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
23708 DONE_LABEL is a label after the whole copying sequence. The label is created
23709 on demand if *DONE_LABEL is NULL.
23710 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
23711 bounds after the initial copies.
23713 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
23714 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
23715 we will dispatch to a library call for large blocks.
23717 In pseudocode we do:
23719 if (COUNT < SIZE)
23720 {
23721 Assume that SIZE is 4. Bigger sizes are handled analogously
23722 if (COUNT & 4)
23723 {
23724 copy 4 bytes from SRCPTR to DESTPTR
23725 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
23726 goto done_label
23727 }
23728 if (!COUNT)
23729 goto done_label;
23730 copy 1 byte from SRCPTR to DESTPTR
23731 if (COUNT & 2)
23732 {
23733 copy 2 bytes from SRCPTR to DESTPTR
23734 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
23735 }
23736 }
23737 else
23738 {
23739 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
23740 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
23742 OLD_DESPTR = DESTPTR;
23743 Align DESTPTR up to DESIRED_ALIGN
23744 SRCPTR += DESTPTR - OLD_DESTPTR
23745 COUNT -= DEST_PTR - OLD_DESTPTR
23746 if (DYNAMIC_CHECK)
23747 Round COUNT down to multiple of SIZE
23748 << optional caller supplied zero size guard is here >>
23749 << optional caller suppplied dynamic check is here >>
23750 << caller supplied main copy loop is here >>
23751 }
23752 done_label:
23753 */
23754 static void
23767 {
23770 rtx modesize;
23772 rtx mode_value;
23774 /* Chose proper value to copy. */
23777 else
23781 /* See if block is big or small, handle small blocks. */
23783 {
23794 /* Handle sizes > 3. */
23801 /* Nothing to copy? Jump to DONE_LABEL if so */
23805 /* Do a byte copy. */
23809 else
23810 {
23813 }
23815 /* Handle sizes 2 and 3. */
23822 else
23823 {
23828 }
23834 }
23835 else
23839 /* Start memcpy for COUNT >= SIZE. */
23841 {
23844 }
23846 /* Copy first desired_align bytes. */
23852 {
23855 else
23856 {
23859 }
23862 }
23865 /* Copy last SIZE bytes. */
23872 else
23873 {
23879 }
23881 {
23885 else
23886 {
23889 }
23890 }
23892 /* Align destination. */
23894 {
23898 /* Align destptr up, place it to new register. */
23905 /* See how many bytes we skipped. */
23909 /* Adjust srcptr and count. */
23915 /* We copied at most size + prolog_size. */
23918 else
23921 /* Our loops always round down the bock size, but for dispatch to library
23922 we need precise value. */
23926 }
23927 else
23928 {
23930 /* Decrease count, so we won't end up copying last word twice. */
23934 else
23938 }
23939 }
23942 /* This function is like the previous one, except here we know how many bytes
23943 need to be copied. That allows us to update alignment not only of DST, which
23944 is returned, but also of SRC, which is passed as a pointer for that
23945 reason. */
23946 static rtx
23951 {
23959 {
23963 }
23968 {
23970 {
23972 {
23975 else
23977 }
23978 else
23981 }
23982 }
23989 {
23995 {
23998 {
24002 }
24007 }
24011 }
24014 }
24016 /* Return true if ALG can be used in current context.
24017 Assume we expand memset if MEMSET is true. */
24018 static bool
24020 {
24025 /* Algorithms using the rep prefix want at least edi and ecx;
24026 additionally, memset wants eax and memcpy wants esi. Don't
24027 consider such algorithms if the user has appropriated those
24028 registers for their own purposes. */
24035 }
24037 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24038 static enum stringop_alg
24042 {
24053 /* Even if the string operation call is cold, we still might spend a lot
24054 of time processing large blocks. */
24060 else
24066 else
24069 /* See maximal size for user defined algorithm. */
24071 {
24078 }
24080 /* If expected size is not known but max size is small enough
24081 so inline version is a win, set expected size into
24082 the range. */
24087 /* If user specified the algorithm, honnor it if possible. */
24091 /* rep; movq or rep; movl is the smallest variant. */
24093 {
24098 else
24101 }
24102 /* Very tiny blocks are best handled via the loop, REP is expensive to
24103 setup. */
24107 {
24111 {
24112 /* We get here if the algorithms that were not libcall-based
24113 were rep-prefix based and we are unable to use rep prefixes
24114 based on global register usage. Break out of the loop and
24115 use the heuristic below. */
24119 {
24123 {
24126 }
24127 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24128 last non-libcall inline algorithm. */
24130 {
24131 /* When the current size is best to be copied by a libcall,
24132 but we are still forced to inline, run the heuristic below
24133 that will pick code for medium sized blocks. */
24135 {
24138 }
24140 }
24142 {
24145 }
24146 }
24147 }
24148 }
24149 /* When asked to inline the call anyway, try to pick meaningful choice.
24150 We look for maximal size of block that is faster to copy by hand and
24151 take blocks of at most of that size guessing that average size will
24152 be roughly half of the block.
24154 If this turns out to be bad, we might simply specify the preferred
24155 choice in ix86_costs. */
24159 {
24162 /* If there aren't any usable algorithms, then recursing on
24163 smaller sizes isn't going to find anything. Just return the
24164 simple byte-at-a-time copy loop. */
24166 {
24167 /* Pick something reasonable. */
24171 }
24181 }
24184 }
24186 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24187 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24188 static int
24193 {
24204 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24205 copying whole cacheline at once. */
24218 }
24221 /* Helper function for memcpy. For QImode value 0xXY produce
24222 0xXYXYXYXY of wide specified by MODE. This is essentially
24223 a * 0x10101010, but we can do slightly better than
24224 synth_mult by unwinding the sequence by hand on CPUs with
24225 slow multiply. */
24226 static rtx
24228 {
24230 rtx tmp;
24237 {
24245 }
24254 nops--;
24259 {
24263 OPTAB_DIRECT);
24264 }
24265 else
24266 {
24272 else
24274 else
24275 {
24278 reg =
24280 }
24290 }
24291 }
24293 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24294 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24295 alignment from ALIGN to DESIRED_ALIGN. */
24296 static rtx
24299 {
24300 rtx promoted_val;
24309 else
24313 }
24315 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24316 operations when profitable. The code depends upon architecture, block size
24317 and alignment, but always has one of the following overall structures:
24319 Aligned move sequence:
24321 1) Prologue guard: Conditional that jumps up to epilogues for small
24322 blocks that can be handled by epilogue alone. This is faster
24323 but also needed for correctness, since prologue assume the block
24324 is larger than the desired alignment.
24326 Optional dynamic check for size and libcall for large
24327 blocks is emitted here too, with -minline-stringops-dynamically.
24329 2) Prologue: copy first few bytes in order to get destination
24330 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24331 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24332 copied. We emit either a jump tree on power of two sized
24333 blocks, or a byte loop.
24335 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24336 with specified algorithm.
24338 4) Epilogue: code copying tail of the block that is too small to be
24339 handled by main body (or up to size guarded by prologue guard).
24341 Misaligned move sequence
24343 1) missaligned move prologue/epilogue containing:
24344 a) Prologue handling small memory blocks and jumping to done_label
24345 (skipped if blocks are known to be large enough)
24346 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24347 needed by single possibly misaligned move
24348 (skipped if alignment is not needed)
24349 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24351 2) Zero size guard dispatching to done_label, if needed
24353 3) dispatch to library call, if needed,
24355 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24356 with specified algorithm. */
24357 bool
24363 {
24364 rtx destreg;
24367 rtx tmp;
24383 /* TODO: Once value ranges are available, fill in proper data. */
24391 /* i386 can do misaligned access on reasonably increased cost. */
24395 /* ALIGN is the minimum of destination and source alignment, but we care here
24396 just about destination alignment. */
24404 else
24405 {
24414 }
24416 /* Make sure we don't need to care about overflow later on. */
24420 /* Step 0: Decide on preferred algorithm, desired alignment and
24421 size of chunks to be copied by main loop. */
24423 issetmem,
24430 /* For now vector-version of memset is generated only for memory zeroing, as
24431 creating of promoted vector value is very cheap in this case. */
24444 {
24463 /* Find the widest supported mode. */
24469 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24470 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24472 {
24477 }
24489 }
24497 /* Step 1: Prologue guard. */
24499 /* Alignment code needs count to be in register. */
24501 {
24504 {
24505 align_bytes
24509 else
24511 }
24514 }
24517 /* Misaligned move sequences handle both prologue and epilogue at once.
24518 Default code generation results in a smaller code for large alignments
24519 and also avoids redundant job when sizes are known precisely. */
24520 misaligned_prologue_used
24521 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24527 /* Do the cheap promotion to allow better CSE across the
24528 main loop and epilogue (ie one load of the big constant in the
24529 front of all code.
24530 For now the misaligned move sequences do not have fast path
24531 without broadcasting. */
24533 {
24535 {
24541 }
24542 else
24543 {
24546 }
24547 }
24548 /* Misaligned move sequences handles both prologues and epilogues at once.
24549 Default code generation results in smaller code for large alignments and
24550 also avoids redundant job when sizes are known precisely. */
24552 {
24553 /* Misaligned move prologue handled small blocks by itself. */
24554 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
24559 desired_align < align
24568 {
24569 /* It is possible that we copied enough so the main loop will not
24570 execute. */
24580 else
24582 }
24583 }
24584 /* Ensure that alignment prologue won't copy past end of block. */
24586 {
24588 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
24589 Make sure it is power of 2. */
24592 /* To improve performance of small blocks, we jump around the VAL
24593 promoting mode. This mean that if the promoted VAL is not constant,
24594 we might not use it in the epilogue and have to use byte
24595 loop variant. */
24600 {
24601 /* If main algorithm works on QImode, no epilogue is needed.
24602 For small sizes just don't align anything. */
24605 else
24607 }
24610 {
24617 else
24619 }
24620 }
24622 /* Emit code to decide on runtime whether library call or inline should be
24623 used. */
24625 {
24627 {
24629 {
24633 }
24634 }
24635 else
24636 {
24645 else
24649 }
24650 }
24652 /* Step 2: Alignment prologue. */
24653 /* Do the expensive promotion once we branched off the small blocks. */
24659 {
24661 {
24662 /* Except for the first move in prologue, we no longer know
24663 constant offset in aliasing info. It don't seems to worth
24664 the pain to maintain it for the first move, so throw away
24665 the info early. */
24672 issetmem);
24673 /* At most desired_align - align bytes are copied. */
24676 else
24678 }
24679 else
24680 {
24681 /* If we know how many bytes need to be stored before dst is
24682 sufficiently aligned, maintain aliasing info accurately. */
24684 srcreg,
24685 promoted_val,
24686 vec_promoted_val,
24687 desired_align,
24688 align_bytes,
24689 issetmem);
24696 }
24698 && !min_size
24703 {
24704 /* It is possible that we copied enough so the main loop will not
24705 execute. */
24715 else
24717 }
24718 }
24720 {
24727 }
24731 /* Step 3: Main loop. */
24734 {
24757 }
24758 /* Adjust properly the offset of src and dest memory for aliasing. */
24760 {
24766 }
24767 else
24768 {
24772 }
24774 /* Step 4: Epilogue to copy the remaining bytes. */
24775 epilogue:
24777 {
24778 /* When the main loop is done, COUNT_EXP might hold original count,
24779 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
24780 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
24781 bytes. Compensate if needed. */
24784 {
24785 tmp =
24788 OPTAB_DIRECT);
24791 }
24794 }
24797 {
24800 epilogue_size_needed);
24801 else
24802 {
24806 epilogue_size_needed);
24807 else
24809 epilogue_size_needed);
24810 }
24811 }
24815 }
24818 /* Expand the appropriate insns for doing strlen if not just doing
24819 repnz; scasb
24821 out = result, initialized with the start address
24822 align_rtx = alignment of the address.
24823 scratch = scratch register, initialized with the startaddress when
24824 not aligned, otherwise undefined
24826 This is just the body. It needs the initializations mentioned above and
24827 some address computing at the end. These things are done in i386.md. */
24829 static void
24831 {
24833 rtx tmp;
24838 rtx mem;
24841 rtx cmp;
24847 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
24849 /* Is there a known alignment and is it less than 4? */
24851 {
24854 /* Is there a known alignment and is it not 2? */
24856 {
24860 /* Leave just the 3 lower bits. */
24870 }
24871 else
24872 {
24873 /* Since the alignment is 2, we have to check 2 or 0 bytes;
24874 check if is aligned to 4 - byte. */
24881 }
24885 /* Now compare the bytes. */
24887 /* Compare the first n unaligned byte on a byte per byte basis. */
24891 /* Increment the address. */
24894 /* Not needed with an alignment of 2 */
24896 {
24900 end_0_label);
24905 }
24908 end_0_label);
24911 }
24913 /* Generate loop to check 4 bytes at a time. It is not a good idea to
24914 align this loop. It gives only huge programs, but does not help to
24915 speed up. */
24922 /* This formula yields a nonzero result iff one of the bytes is zero.
24923 This saves three branches inside loop and many cycles. */
24931 align_4_label);
24934 {
24940 /* If zero is not in the first two bytes, move two bytes forward. */
24946 reg,
24947 tmpreg)));
24948 /* Emit lea manually to avoid clobbering of flags. */
24956 reg2,
24957 out)));
24958 }
24959 else
24960 {
24962 /* Is zero in the first two bytes? */
24969 pc_rtx);
24973 /* Not in the first two. Move two bytes forward. */
24979 }
24981 /* Avoid branch in fixing the byte. */
24989 }
24991 /* Expand strlen. */
24993 bool
24995 {
24998 /* The generic case of strlen expander is long. Avoid it's
24999 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25002 && !TARGET_INLINE_ALL_STRINGOPS
25012 {
25013 /* Well it seems that some optimizer does not combine a call like
25014 foo(strlen(bar), strlen(bar));
25015 when the move and the subtraction is done here. It does calculate
25016 the length just once when these instructions are done inside of
25017 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25018 often used and I use one fewer register for the lifetime of
25019 output_strlen_unroll() this is better. */
25025 /* strlensi_unroll_1 returns the address of the zero at the end of
25026 the string, like memchr(), so compute the length by subtracting
25027 the start address. */
25029 }
25030 else
25031 {
25032 rtx unspec;
25034 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25047 /* If .md starts supporting :P, this can be done in .md. */
25053 }
25055 }
25057 /* For given symbol (function) construct code to compute address of it's PLT
25058 entry in large x86-64 PIC model. */
25059 static rtx
25061 {
25074 }
25076 rtx
25078 rtx callarg2,
25080 {
25081 unsigned int const cregs_size
25092 {
25093 #if TARGET_MACHO
25096 #endif
25097 }
25098 else
25099 {
25100 /* Static functions and indirect calls don't need the pic register. */
25102 && (!TARGET_64BIT
25108 }
25111 {
25115 }
25118 && !TARGET_PECOFF
25126 {
25129 }
25134 {
25135 /* For instrumented code we may have GPR + BR in parallel but
25136 it will confuse DF and we need to put each reg
25137 under EXPR_LIST. */
25142 }
25145 /* b0 and b1 registers hold bounds for returned value. */
25147 {
25156 }
25159 {
25163 }
25167 {
25171 UNSPEC_MS_TO_SYSV_CALL);
25174 {
25180 }
25181 }
25190 }
25192 /* Output the assembly for a call instruction. */
25196 {
25202 {
25205 /* SEH epilogue detection requires the indirect branch case
25206 to include REX.W. */
25209 else
25214 }
25216 /* SEH unwinding can require an extra nop to be emitted in several
25217 circumstances. Determine if we have one of those. */
25219 {
25220 rtx i;
25223 {
25224 /* If we get to another real insn, we don't need the nop. */
25228 /* If we get to the epilogue note, prevent a catch region from
25229 being adjacent to the standard epilogue sequence. If non-
25230 call-exceptions, we'll have done this during epilogue emission. */
25232 && !flag_non_call_exceptions
25234 {
25237 }
25238 }
25240 /* If we didn't find a real insn following the call, prevent the
25241 unwinder from looking into the next function. */
25244 }
25248 else
25257 }
25258 \f
25259 /* Clear stack slot assignments remembered from previous functions.
25260 This is called from INIT_EXPANDERS once before RTL is emitted for each
25261 function. */
25265 {
25273 }
25275 /* Return a MEM corresponding to a stack slot with mode MODE.
25276 Allocate a new slot if necessary.
25278 The RTL for a function can have several slots available: N is
25279 which slot to use. */
25281 rtx
25283 {
25300 }
25302 static void
25304 {
25310 }
25311 \f
25312 /* Check whether x86 address PARTS is a pc-relative address. */
25314 static bool
25316 {
25324 {
25326 {
25343 }
25344 }
25346 }
25348 /* Calculate the length of the memory address in the instruction encoding.
25349 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25350 or other prefixes. We never generate addr32 prefix for LEA insn. */
25352 int
25354 {
25371 /* If this is not LEA instruction, add the length of addr32 prefix. */
25376 len++;
25390 /* Rule of thumb:
25391 - esp as the base always wants an index,
25392 - ebp as the base always wants a displacement,
25393 - r12 as the base always wants an index,
25394 - r13 as the base always wants a displacement. */
25396 /* Register Indirect. */
25398 {
25399 /* esp (for its index) and ebp (for its displacement) need
25400 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25401 code. */
25408 len++;
25409 }
25411 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25412 is not disp32, but disp32(%rip), so for disp32
25413 SIB byte is needed, unless print_operand_address
25414 optimizes it into disp32(%rip) or (%rip) is implied
25415 by UNSPEC. */
25417 {
25420 len++;
25421 }
25422 else
25423 {
25424 /* Find the length of the displacement constant. */
25426 {
25429 else
25431 }
25432 /* ebp always wants a displacement. Similarly r13. */
25434 len++;
25436 /* An index requires the two-byte modrm form.... */
25438 /* ...like esp (or r12), which always wants an index. */
25442 len++;
25443 }
25446 }
25448 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25449 is set, expect that insn have 8bit immediate alternative. */
25450 int
25452 {
25458 {
25463 {
25466 {
25478 }
25480 {
25483 }
25484 }
25486 {
25496 /* Immediates for DImode instructions are encoded
25497 as 32bit sign extended values. */
25503 }
25504 }
25506 }
25508 /* Compute default value for "length_address" attribute. */
25509 int
25511 {
25515 {
25526 }
25531 {
25534 {
25539 constraints++;
25542 ;
25543 /* Skip ignored operands. */
25546 }
25548 }
25550 }
25552 /* Compute default value for "length_vex" attribute. It includes
25553 2 or 3 byte VEX prefix and 1 opcode byte. */
25555 int
25557 {
25560 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
25561 byte VEX prefix. */
25565 /* We can always use 2 byte VEX prefix in 32bit. */
25573 {
25574 /* REX.W bit uses 3 byte VEX prefix. */
25578 }
25579 else
25580 {
25581 /* REX.X or REX.B bits use 3 byte VEX prefix. */
25585 }
25588 }
25589 \f
25590 /* Return the maximum number of instructions a cpu can issue. */
25592 static int
25594 {
25596 {
25627 }
25628 }
25630 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
25631 by DEP_INSN and nothing set by DEP_INSN. */
25633 static bool
25635 {
25638 /* Simplify the test for uninteresting insns. */
25646 {
25649 }
25654 {
25657 }
25658 else
25664 /* This test is true if the dependent insn reads the flags but
25665 not any other potentially set register. */
25673 }
25675 /* Return true iff USE_INSN has a memory address with operands set by
25676 SET_INSN. */
25678 bool
25680 {
25685 {
25688 }
25690 }
25692 /* Helper function for exact_store_load_dependency.
25693 Return true if addr is found in insn. */
25694 static bool
25696 {
25703 {
25709 CASE_CONST_ANY:
25718 }
25722 {
25724 {
25734 }
25735 }
25737 }
25739 /* Return true if there exists exact dependency for store & load, i.e.
25740 the same memory address is used in them. */
25741 static bool
25743 {
25757 }
25759 static int
25761 {
25767 /* Anti and output dependencies have zero cost on all CPUs. */
25773 /* If we can't recognize the insns, we can't really do anything. */
25781 {
25783 /* Address Generation Interlock adds a cycle of latency. */
25785 {
25796 }
25800 /* ??? Compares pair with jump/setcc. */
25804 /* Floating point stores require value to be ready one cycle earlier. */
25812 /* INT->FP conversion is expensive. */
25816 /* There is one cycle extra latency between an FP op and a store. */
25826 /* Show ability of reorder buffer to hide latency of load by executing
25827 in parallel with previous instruction in case
25828 previous instruction is not needed to compute the address. */
25831 {
25832 /* Claim moves to take one cycle, as core can issue one load
25833 at time and the next load can start cycle later. */
25838 cost--;
25839 }
25843 /* The esp dependency is resolved before
25844 the instruction is really finished. */
25849 /* INT->FP conversion is expensive. */
25855 /* Show ability of reorder buffer to hide latency of load by executing
25856 in parallel with previous instruction in case
25857 previous instruction is not needed to compute the address. */
25860 {
25861 /* Claim moves to take one cycle, as core can issue one load
25862 at time and the next load can start cycle later. */
25868 else
25870 }
25881 /* Stack engine allows to execute push&pop instructions in parall. */
25885 /* FALLTHRU */
25891 /* Show ability of reorder buffer to hide latency of load by executing
25892 in parallel with previous instruction in case
25893 previous instruction is not needed to compute the address. */
25896 {
25900 /* Because of the difference between the length of integer and
25901 floating unit pipeline preparation stages, the memory operands
25902 for floating point are cheaper.
25904 ??? For Athlon it the difference is most probably 2. */
25907 else
25912 else
25914 }
25921 /* Stack engine allows to execute push&pop instructions in parall. */
25928 /* Show ability of reorder buffer to hide latency of load by executing
25929 in parallel with previous instruction in case
25930 previous instruction is not needed to compute the address. */
25933 {
25936 else
25938 }
25946 /* Increase cost of integer loads. */
25949 {
25952 {
25955 else
25956 {
25957 /* Increase cost of ld/st for short int types only
25958 because of store forwarding issue. */
25962 {
25963 /* Increase cost of store/load insn if exact
25964 dependence exists and it is load insn. */
25969 }
25970 }
25971 }
25972 }
25976 }
25979 }
25981 /* How many alternative schedules to try. This should be as wide as the
25982 scheduling freedom in the DFA, but no wider. Making this value too
25983 large results extra work for the scheduler. */
25985 static int
25987 {
25989 {
26001 /* We use lookahead value 4 for BD both before and after reload
26002 schedules. Plan is to have value 8 included for O3. */
26012 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26013 as many instructions can be executed on a cycle, i.e.,
26014 issue_rate. I wonder why tuning for many CPUs does not do this. */
26017 /* Don't use lookahead for pre-reload schedule to save compile time. */
26022 }
26023 }
26025 /* Return true if target platform supports macro-fusion. */
26027 static bool
26029 {
26031 }
26033 /* Check whether current microarchitecture support macro fusion
26034 for insn pair "CONDGEN + CONDJMP". Refer to
26035 "Intel Architectures Optimization Reference Manual". */
26037 static bool
26039 {
26058 else
26059 {
26064 {
26068 else
26070 }
26071 }
26078 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26079 supported. */
26086 /* No fusion for RIP-relative address. */
26093 ix86_address parts;
26099 }
26104 /* Check whether conditional jump use Sign or Overflow Flags. */
26112 /* Return true for TYPE_TEST and TYPE_ICMP. */
26117 /* The following is the case that macro-fusion for alu + jmp. */
26121 /* No fusion for alu op with memory destination operand. */
26126 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26127 supported. */
26136 }
26138 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26139 execution. It is applied if
26140 (1) IMUL instruction is on the top of list;
26141 (2) There exists the only producer of independent IMUL instruction in
26142 ready list.
26143 Return index of IMUL producer if it was found and -1 otherwise. */
26144 static int
26146 {
26148 sd_iterator_def sd_it;
26149 dep_t dep;
26156 /* Check that IMUL instruction is on the top of ready list. */
26165 /* Search for producer of independent IMUL instruction. */
26167 {
26171 /* Skip IMUL instruction. */
26181 {
26182 rtx con;
26193 {
26194 sd_iterator_def sd_it1;
26195 dep_t dep1;
26196 /* Check if there is no other dependee for IMUL. */
26199 {
26200 rtx pro;
26206 }
26209 }
26210 }
26213 }
26215 }
26217 /* Try to find the best candidate on the top of ready list if two insns
26218 have the same priority - candidate is best if its dependees were
26219 scheduled earlier. Applied for Silvermont only.
26220 Return true if top 2 insns must be interchanged. */
26221 static bool
26223 {
26226 rtx set;
26227 sd_iterator_def sd_it;
26228 dep_t dep;
26231 #define INSN_TICK(INSN) (HID (INSN)->tick)
26252 {
26255 /* Determine winner more precise. */
26257 {
26258 rtx pro;
26264 }
26266 {
26267 rtx pro;
26273 }
26276 {
26277 /* Determine winner - load must win. */
26283 }
26285 }
26287 #undef INSN_TICK
26288 }
26290 /* Perform possible reodering of ready list for Atom/Silvermont only.
26291 Return issue rate. */
26292 static int
26295 {
26299 rtx insn;
26302 /* Set up issue rate. */
26305 /* Do reodering for BONNELL/SILVERMONT only. */
26309 /* Nothing to do if ready list contains only 1 instruction. */
26313 /* Do reodering for post-reload scheduler only. */
26318 {
26323 /* Put IMUL producer (ready[index]) at the top of ready list. */
26329 }
26331 {
26335 /* Swap 2 top elements of ready list. */
26339 }
26341 }
26343 static bool
26346 /* Returns true if lhs of insn is HW function argument register and set up
26347 is_spilled to true if it is likely spilled HW register. */
26348 static bool
26350 {
26351 rtx dst;
26355 /* Call instructions are not movable, ignore it. */
26366 {
26367 /* Is it likely spilled HW register? */
26372 }
26374 }
26376 /* Add output dependencies for chain of function adjacent arguments if only
26377 there is a move to likely spilled HW register. Return first argument
26378 if at least one dependence was added or NULL otherwise. */
26379 static rtx
26381 {
26382 rtx insn;
26389 /* Find nearest to call argument passing instruction. */
26391 {
26400 }
26404 {
26411 {
26414 }
26416 {
26417 /* Add output depdendence between two function arguments if chain
26418 of output arguments contains likely spilled HW registers. */
26422 }
26423 else
26425 }
26429 }
26431 /* Add output or anti dependency from insn to first_arg to restrict its code
26432 motion. */
26433 static void
26435 {
26436 rtx set;
26437 rtx tmp;
26444 {
26445 /* Add output dependency to the first function argument. */
26448 }
26449 /* Add anti dependency. */
26451 }
26453 /* Avoid cross block motion of function argument through adding dependency
26454 from the first non-jump instruction in bb. */
26455 static void
26457 {
26461 {
26463 {
26466 {
26469 }
26470 }
26474 }
26475 }
26477 /* Hook for pre-reload schedule - avoid motion of function arguments
26478 passed in likely spilled HW registers. */
26479 static void
26481 {
26482 rtx insn;
26490 {
26493 {
26494 /* Add dependee for first argument to predecessors if only
26495 region contains more than one block. */
26499 /* Skip trivial regions and region head blocks that can have
26500 predecessors outside of region. */
26502 {
26503 edge e;
26504 edge_iterator ei;
26505 /* Assume that region is SCC, i.e. all immediate predecessors
26506 of non-head block are in the same region. */
26508 {
26509 /* Avoid creating of loop-carried dependencies through
26510 using topological odering in region. */
26513 }
26514 }
26518 }
26519 }
26522 }
26524 /* Hook for pre-reload schedule - set priority of moves from likely spilled
26525 HW registers to maximum, to schedule them at soon as possible. These are
26526 moves from function argument registers at the top of the function entry
26527 and moves from function return value registers after call. */
26528 static int
26530 {
26531 rtx set;
26541 {
26548 }
26551 }
26553 /* Model decoder of Core 2/i7.
26554 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
26555 track the instruction fetch block boundaries and make sure that long
26556 (9+ bytes) instructions are assigned to D0. */
26558 /* Maximum length of an insn that can be handled by
26559 a secondary decoder unit. '8' for Core 2/i7. */
26562 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
26563 '16' for Core 2/i7. */
26566 /* Maximum number of instructions decoder can handle per cycle.
26567 '6' for Core 2/i7. */
26571 ix86_first_cycle_multipass_data_t;
26573 const_ix86_first_cycle_multipass_data_t;
26575 /* A variable to store target state across calls to max_issue within
26576 one cycle. */
26580 /* Initialize DATA. */
26581 static void
26583 {
26584 ix86_first_cycle_multipass_data_t data
26591 }
26593 /* Advancing the cycle; reset ifetch block counts. */
26594 static void
26596 {
26603 }
26607 /* Filter out insns from ready_try that the core will not be able to issue
26608 on current cycle due to decoder. */
26609 static void
26610 core2i7_first_cycle_multipass_filter_ready_try
26613 {
26615 {
26616 rtx insn;
26626 (!first_cycle_insn_p
26628 /* ... or it would not fit into the ifetch block ... */
26630 /* ... or the decoder is full already ... */
26632 /* ... mask the insn out. */
26633 {
26638 }
26639 }
26640 }
26642 /* Prepare for a new round of multipass lookahead scheduling. */
26643 static void
26646 {
26647 ix86_first_cycle_multipass_data_t data
26649 const_ix86_first_cycle_multipass_data_t prev_data
26652 /* Restore the state from the end of the previous round. */
26656 /* Filter instructions that cannot be issued on current cycle due to
26657 decoder restrictions. */
26659 first_cycle_insn_p);
26660 }
26662 /* INSN is being issued in current solution. Account for its impact on
26663 the decoder model. */
26664 static void
26667 {
26668 ix86_first_cycle_multipass_data_t data
26670 const_ix86_first_cycle_multipass_data_t prev_data
26680 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
26682 {
26685 }
26687 {
26691 }
26694 /* Filter out insns from ready_try that the core will not be able to issue
26695 on current cycle due to decoder. */
26698 }
26700 /* Revert the effect on ready_try. */
26701 static void
26705 {
26706 const_ix86_first_cycle_multipass_data_t data
26709 sbitmap_iterator sbi;
26713 {
26715 }
26716 }
26718 /* Save the result of multipass lookahead scheduling for the next round. */
26719 static void
26721 {
26722 const_ix86_first_cycle_multipass_data_t data
26724 ix86_first_cycle_multipass_data_t next_data
26728 {
26731 }
26732 }
26734 /* Deallocate target data. */
26735 static void
26737 {
26738 ix86_first_cycle_multipass_data_t data
26742 {
26746 }
26747 }
26749 /* Prepare for scheduling pass. */
26750 static void
26754 {
26755 /* Install scheduling hooks for current CPU. Some of these hooks are used
26756 in time-critical parts of the scheduler, so we only set them up when
26757 they are actually used. */
26759 {
26764 /* Do not perform multipass scheduling for pre-reload schedule
26765 to save compile time. */
26767 {
26783 /* Set decoder parameters. */
26788 }
26789 /* ... Fall through ... */
26799 }
26800 }
26802 \f
26803 /* Compute the alignment given to a constant that is being placed in memory.
26804 EXP is the constant and ALIGN is the alignment that the object would
26805 ordinarily have.
26806 The value of this function is used instead of that alignment to align
26807 the object. */
26809 int
26811 {
26814 {
26819 }
26825 }
26827 /* Compute the alignment for a static variable.
26828 TYPE is the data type, and ALIGN is the alignment that
26829 the object would ordinarily have. The value of this function is used
26830 instead of that alignment to align the object. */
26832 int
26834 {
26835 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
26836 for symbols from other compilation units or symbols that don't need
26837 to bind locally. In order to preserve some ABI compatibility with
26838 those compilers, ensure we don't decrease alignment from what we
26839 used to assume. */
26841 int max_align_compat
26844 /* A data structure, equal or greater than the size of a cache line
26845 (64 bytes in the Pentium 4 and other recent Intel processors, including
26846 processors based on Intel Core microarchitecture) should be aligned
26847 so that its base address is a multiple of a cache line size. */
26849 int max_align
26859 {
26868 }
26870 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26871 to 16byte boundary. */
26873 {
26880 }
26886 {
26891 }
26893 {
26900 }
26905 {
26910 }
26913 {
26918 }
26921 }
26923 /* Compute the alignment for a local variable or a stack slot. EXP is
26924 the data type or decl itself, MODE is the widest mode available and
26925 ALIGN is the alignment that the object would ordinarily have. The
26926 value of this macro is used instead of that alignment to align the
26927 object. */
26929 unsigned int
26932 {
26936 {
26939 }
26940 else
26941 {
26944 }
26946 /* Don't do dynamic stack realignment for long long objects with
26947 -mpreferred-stack-boundary=2. */
26956 /* If TYPE is NULL, we are allocating a stack slot for caller-save
26957 register in MODE. We will return the largest alignment of XF
26958 and DF. */
26960 {
26964 }
26966 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
26967 to 16byte boundary. Exact wording is:
26969 An array uses the same alignment as its elements, except that a local or
26970 global array variable of length at least 16 bytes or
26971 a C99 variable-length array variable always has alignment of at least 16 bytes.
26973 This was added to allow use of aligned SSE instructions at arrays. This
26974 rule is meant for static storage (where compiler can not do the analysis
26975 by itself). We follow it for automatic variables only when convenient.
26976 We fully control everything in the function compiled and functions from
26977 other unit can not rely on the alignment.
26979 Exclude va_list type. It is the common case of local array where
26980 we can not benefit from the alignment.
26982 TODO: Probably one should optimize for size only when var is not escaping. */
26985 {
26995 }
26997 {
27002 }
27004 {
27010 }
27015 {
27020 }
27023 {
27029 }
27031 }
27033 /* Compute the minimum required alignment for dynamic stack realignment
27034 purposes for a local variable, parameter or a stack slot. EXP is
27035 the data type or decl itself, MODE is its mode and ALIGN is the
27036 alignment that the object would ordinarily have. */
27038 unsigned int
27041 {
27045 {
27048 }
27049 else
27050 {
27053 }
27058 /* Don't do dynamic stack realignment for long long objects with
27059 -mpreferred-stack-boundary=2. */
27066 }
27067 \f
27068 /* Find a location for the static chain incoming to a nested function.
27069 This is a register, unless all free registers are used by arguments. */
27071 static rtx
27073 {
27080 {
27081 /* We always use R10 in 64-bit mode. */
27083 }
27084 else
27085 {
27086 tree fntype;
27089 /* By default in 32-bit mode we use ECX to pass the static chain. */
27095 {
27096 /* Fastcall functions use ecx/edx for arguments, which leaves
27097 us with EAX for the static chain.
27098 Thiscall functions use ecx for arguments, which also
27099 leaves us with EAX for the static chain. */
27101 }
27103 {
27104 /* Thiscall functions use ecx for arguments, which leaves
27105 us with EAX and EDX for the static chain.
27106 We are using for abi-compatibility EAX. */
27108 }
27110 {
27111 /* For regparm 3, we have no free call-clobbered registers in
27112 which to store the static chain. In order to implement this,
27113 we have the trampoline push the static chain to the stack.
27114 However, we can't push a value below the return address when
27115 we call the nested function directly, so we have to use an
27116 alternate entry point. For this we use ESI, and have the
27117 alternate entry point push ESI, so that things appear the
27118 same once we're executing the nested function. */
27120 {
27126 }
27128 }
27129 }
27132 }
27134 /* Emit RTL insns to initialize the variable parts of a trampoline.
27135 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27136 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27137 to be passed to the target function. */
27139 static void
27141 {
27149 {
27152 /* Load the function address to r11. Try to load address using
27153 the shorter movl instead of movabs. We may want to support
27154 movq for kernel mode, but kernel does not use trampolines at
27155 the moment. FNADDR is a 32bit address and may not be in
27156 DImode when ptr_mode == SImode. Always use movl in this
27157 case. */
27160 {
27169 }
27170 else
27171 {
27178 }
27180 /* Load static chain using movabs to r10. Use the shorter movl
27181 instead of movabs when ptr_mode == SImode. */
27183 {
27186 }
27187 else
27188 {
27191 }
27200 /* Jump to r11; the last (unused) byte is a nop, only there to
27201 pad the write out to a single 32-bit store. */
27205 }
27206 else
27207 {
27210 /* Depending on the static chain location, either load a register
27211 with a constant, or push the constant to the stack. All of the
27212 instructions are the same size. */
27215 {
27217 {
27224 }
27225 }
27226 else
27241 /* Compute offset from the end of the jmp to the target function.
27242 In the case in which the trampoline stores the static chain on
27243 the stack, we need to skip the first insn which pushes the
27244 (call-saved) register static chain; this push is 1 byte. */
27251 }
27255 #ifdef HAVE_ENABLE_EXECUTE_STACK
27256 #ifdef CHECK_EXECUTE_STACK_ENABLED
27258 #endif
27261 #endif
27262 }
27263 \f
27264 /* The following file contains several enumerations and data structures
27265 built from the definitions in i386-builtin-types.def. */
27269 /* Table for the ix86 builtin non-function types. */
27272 /* Retrieve an element from the above table, building some of
27273 the types lazily. */
27275 static tree
27277 {
27289 {
27297 }
27298 else
27299 {
27305 else
27313 }
27317 }
27319 /* Table for the ix86 builtin function types. */
27322 /* Retrieve an element from the above table, building some of
27323 the types lazily. */
27325 static tree
27327 {
27328 tree type;
27337 {
27345 {
27348 }
27351 }
27352 else
27353 {
27359 }
27363 }
27366 /* Codes for all the SSE/MMX builtins. */
27367 enum ix86_builtins
27368 {
27369 IX86_BUILTIN_ADDPS,
27370 IX86_BUILTIN_ADDSS,
27371 IX86_BUILTIN_DIVPS,
27372 IX86_BUILTIN_DIVSS,
27373 IX86_BUILTIN_MULPS,
27374 IX86_BUILTIN_MULSS,
27375 IX86_BUILTIN_SUBPS,
27376 IX86_BUILTIN_SUBSS,
27378 IX86_BUILTIN_CMPEQPS,
27379 IX86_BUILTIN_CMPLTPS,
27380 IX86_BUILTIN_CMPLEPS,
27381 IX86_BUILTIN_CMPGTPS,
27382 IX86_BUILTIN_CMPGEPS,
27383 IX86_BUILTIN_CMPNEQPS,
27384 IX86_BUILTIN_CMPNLTPS,
27385 IX86_BUILTIN_CMPNLEPS,
27386 IX86_BUILTIN_CMPNGTPS,
27387 IX86_BUILTIN_CMPNGEPS,
27388 IX86_BUILTIN_CMPORDPS,
27389 IX86_BUILTIN_CMPUNORDPS,
27390 IX86_BUILTIN_CMPEQSS,
27391 IX86_BUILTIN_CMPLTSS,
27392 IX86_BUILTIN_CMPLESS,
27393 IX86_BUILTIN_CMPNEQSS,
27394 IX86_BUILTIN_CMPNLTSS,
27395 IX86_BUILTIN_CMPNLESS,
27396 IX86_BUILTIN_CMPORDSS,
27397 IX86_BUILTIN_CMPUNORDSS,
27399 IX86_BUILTIN_COMIEQSS,
27400 IX86_BUILTIN_COMILTSS,
27401 IX86_BUILTIN_COMILESS,
27402 IX86_BUILTIN_COMIGTSS,
27403 IX86_BUILTIN_COMIGESS,
27404 IX86_BUILTIN_COMINEQSS,
27405 IX86_BUILTIN_UCOMIEQSS,
27406 IX86_BUILTIN_UCOMILTSS,
27407 IX86_BUILTIN_UCOMILESS,
27408 IX86_BUILTIN_UCOMIGTSS,
27409 IX86_BUILTIN_UCOMIGESS,
27410 IX86_BUILTIN_UCOMINEQSS,
27412 IX86_BUILTIN_CVTPI2PS,
27413 IX86_BUILTIN_CVTPS2PI,
27414 IX86_BUILTIN_CVTSI2SS,
27415 IX86_BUILTIN_CVTSI642SS,
27416 IX86_BUILTIN_CVTSS2SI,
27417 IX86_BUILTIN_CVTSS2SI64,
27418 IX86_BUILTIN_CVTTPS2PI,
27419 IX86_BUILTIN_CVTTSS2SI,
27420 IX86_BUILTIN_CVTTSS2SI64,
27422 IX86_BUILTIN_MAXPS,
27423 IX86_BUILTIN_MAXSS,
27424 IX86_BUILTIN_MINPS,
27425 IX86_BUILTIN_MINSS,
27427 IX86_BUILTIN_LOADUPS,
27428 IX86_BUILTIN_STOREUPS,
27429 IX86_BUILTIN_MOVSS,
27431 IX86_BUILTIN_MOVHLPS,
27432 IX86_BUILTIN_MOVLHPS,
27433 IX86_BUILTIN_LOADHPS,
27434 IX86_BUILTIN_LOADLPS,
27435 IX86_BUILTIN_STOREHPS,
27436 IX86_BUILTIN_STORELPS,
27438 IX86_BUILTIN_MASKMOVQ,
27439 IX86_BUILTIN_MOVMSKPS,
27440 IX86_BUILTIN_PMOVMSKB,
27442 IX86_BUILTIN_MOVNTPS,
27443 IX86_BUILTIN_MOVNTQ,
27445 IX86_BUILTIN_LOADDQU,
27446 IX86_BUILTIN_STOREDQU,
27448 IX86_BUILTIN_PACKSSWB,
27449 IX86_BUILTIN_PACKSSDW,
27450 IX86_BUILTIN_PACKUSWB,
27452 IX86_BUILTIN_PADDB,
27453 IX86_BUILTIN_PADDW,
27454 IX86_BUILTIN_PADDD,
27455 IX86_BUILTIN_PADDQ,
27456 IX86_BUILTIN_PADDSB,
27457 IX86_BUILTIN_PADDSW,
27458 IX86_BUILTIN_PADDUSB,
27459 IX86_BUILTIN_PADDUSW,
27460 IX86_BUILTIN_PSUBB,
27461 IX86_BUILTIN_PSUBW,
27462 IX86_BUILTIN_PSUBD,
27463 IX86_BUILTIN_PSUBQ,
27464 IX86_BUILTIN_PSUBSB,
27465 IX86_BUILTIN_PSUBSW,
27466 IX86_BUILTIN_PSUBUSB,
27467 IX86_BUILTIN_PSUBUSW,
27469 IX86_BUILTIN_PAND,
27470 IX86_BUILTIN_PANDN,
27471 IX86_BUILTIN_POR,
27472 IX86_BUILTIN_PXOR,
27474 IX86_BUILTIN_PAVGB,
27475 IX86_BUILTIN_PAVGW,
27477 IX86_BUILTIN_PCMPEQB,
27478 IX86_BUILTIN_PCMPEQW,
27479 IX86_BUILTIN_PCMPEQD,
27480 IX86_BUILTIN_PCMPGTB,
27481 IX86_BUILTIN_PCMPGTW,
27482 IX86_BUILTIN_PCMPGTD,
27484 IX86_BUILTIN_PMADDWD,
27486 IX86_BUILTIN_PMAXSW,
27487 IX86_BUILTIN_PMAXUB,
27488 IX86_BUILTIN_PMINSW,
27489 IX86_BUILTIN_PMINUB,
27491 IX86_BUILTIN_PMULHUW,
27492 IX86_BUILTIN_PMULHW,
27493 IX86_BUILTIN_PMULLW,
27495 IX86_BUILTIN_PSADBW,
27496 IX86_BUILTIN_PSHUFW,
27498 IX86_BUILTIN_PSLLW,
27499 IX86_BUILTIN_PSLLD,
27500 IX86_BUILTIN_PSLLQ,
27501 IX86_BUILTIN_PSRAW,
27502 IX86_BUILTIN_PSRAD,
27503 IX86_BUILTIN_PSRLW,
27504 IX86_BUILTIN_PSRLD,
27505 IX86_BUILTIN_PSRLQ,
27506 IX86_BUILTIN_PSLLWI,
27507 IX86_BUILTIN_PSLLDI,
27508 IX86_BUILTIN_PSLLQI,
27509 IX86_BUILTIN_PSRAWI,
27510 IX86_BUILTIN_PSRADI,
27511 IX86_BUILTIN_PSRLWI,
27512 IX86_BUILTIN_PSRLDI,
27513 IX86_BUILTIN_PSRLQI,
27515 IX86_BUILTIN_PUNPCKHBW,
27516 IX86_BUILTIN_PUNPCKHWD,
27517 IX86_BUILTIN_PUNPCKHDQ,
27518 IX86_BUILTIN_PUNPCKLBW,
27519 IX86_BUILTIN_PUNPCKLWD,
27520 IX86_BUILTIN_PUNPCKLDQ,
27522 IX86_BUILTIN_SHUFPS,
27524 IX86_BUILTIN_RCPPS,
27525 IX86_BUILTIN_RCPSS,
27526 IX86_BUILTIN_RSQRTPS,
27527 IX86_BUILTIN_RSQRTPS_NR,
27528 IX86_BUILTIN_RSQRTSS,
27529 IX86_BUILTIN_RSQRTF,
27530 IX86_BUILTIN_SQRTPS,
27531 IX86_BUILTIN_SQRTPS_NR,
27532 IX86_BUILTIN_SQRTSS,
27534 IX86_BUILTIN_UNPCKHPS,
27535 IX86_BUILTIN_UNPCKLPS,
27537 IX86_BUILTIN_ANDPS,
27538 IX86_BUILTIN_ANDNPS,
27539 IX86_BUILTIN_ORPS,
27540 IX86_BUILTIN_XORPS,
27542 IX86_BUILTIN_EMMS,
27543 IX86_BUILTIN_LDMXCSR,
27544 IX86_BUILTIN_STMXCSR,
27545 IX86_BUILTIN_SFENCE,
27547 IX86_BUILTIN_FXSAVE,
27548 IX86_BUILTIN_FXRSTOR,
27549 IX86_BUILTIN_FXSAVE64,
27550 IX86_BUILTIN_FXRSTOR64,
27552 IX86_BUILTIN_XSAVE,
27553 IX86_BUILTIN_XRSTOR,
27554 IX86_BUILTIN_XSAVE64,
27555 IX86_BUILTIN_XRSTOR64,
27557 IX86_BUILTIN_XSAVEOPT,
27558 IX86_BUILTIN_XSAVEOPT64,
27560 /* 3DNow! Original */
27561 IX86_BUILTIN_FEMMS,
27562 IX86_BUILTIN_PAVGUSB,
27563 IX86_BUILTIN_PF2ID,
27564 IX86_BUILTIN_PFACC,
27565 IX86_BUILTIN_PFADD,
27566 IX86_BUILTIN_PFCMPEQ,
27567 IX86_BUILTIN_PFCMPGE,
27568 IX86_BUILTIN_PFCMPGT,
27569 IX86_BUILTIN_PFMAX,
27570 IX86_BUILTIN_PFMIN,
27571 IX86_BUILTIN_PFMUL,
27572 IX86_BUILTIN_PFRCP,
27573 IX86_BUILTIN_PFRCPIT1,
27574 IX86_BUILTIN_PFRCPIT2,
27575 IX86_BUILTIN_PFRSQIT1,
27576 IX86_BUILTIN_PFRSQRT,
27577 IX86_BUILTIN_PFSUB,
27578 IX86_BUILTIN_PFSUBR,
27579 IX86_BUILTIN_PI2FD,
27580 IX86_BUILTIN_PMULHRW,
27582 /* 3DNow! Athlon Extensions */
27583 IX86_BUILTIN_PF2IW,
27584 IX86_BUILTIN_PFNACC,
27585 IX86_BUILTIN_PFPNACC,
27586 IX86_BUILTIN_PI2FW,
27587 IX86_BUILTIN_PSWAPDSI,
27588 IX86_BUILTIN_PSWAPDSF,
27590 /* SSE2 */
27591 IX86_BUILTIN_ADDPD,
27592 IX86_BUILTIN_ADDSD,
27593 IX86_BUILTIN_DIVPD,
27594 IX86_BUILTIN_DIVSD,
27595 IX86_BUILTIN_MULPD,
27596 IX86_BUILTIN_MULSD,
27597 IX86_BUILTIN_SUBPD,
27598 IX86_BUILTIN_SUBSD,
27600 IX86_BUILTIN_CMPEQPD,
27601 IX86_BUILTIN_CMPLTPD,
27602 IX86_BUILTIN_CMPLEPD,
27603 IX86_BUILTIN_CMPGTPD,
27604 IX86_BUILTIN_CMPGEPD,
27605 IX86_BUILTIN_CMPNEQPD,
27606 IX86_BUILTIN_CMPNLTPD,
27607 IX86_BUILTIN_CMPNLEPD,
27608 IX86_BUILTIN_CMPNGTPD,
27609 IX86_BUILTIN_CMPNGEPD,
27610 IX86_BUILTIN_CMPORDPD,
27611 IX86_BUILTIN_CMPUNORDPD,
27612 IX86_BUILTIN_CMPEQSD,
27613 IX86_BUILTIN_CMPLTSD,
27614 IX86_BUILTIN_CMPLESD,
27615 IX86_BUILTIN_CMPNEQSD,
27616 IX86_BUILTIN_CMPNLTSD,
27617 IX86_BUILTIN_CMPNLESD,
27618 IX86_BUILTIN_CMPORDSD,
27619 IX86_BUILTIN_CMPUNORDSD,
27621 IX86_BUILTIN_COMIEQSD,
27622 IX86_BUILTIN_COMILTSD,
27623 IX86_BUILTIN_COMILESD,
27624 IX86_BUILTIN_COMIGTSD,
27625 IX86_BUILTIN_COMIGESD,
27626 IX86_BUILTIN_COMINEQSD,
27627 IX86_BUILTIN_UCOMIEQSD,
27628 IX86_BUILTIN_UCOMILTSD,
27629 IX86_BUILTIN_UCOMILESD,
27630 IX86_BUILTIN_UCOMIGTSD,
27631 IX86_BUILTIN_UCOMIGESD,
27632 IX86_BUILTIN_UCOMINEQSD,
27634 IX86_BUILTIN_MAXPD,
27635 IX86_BUILTIN_MAXSD,
27636 IX86_BUILTIN_MINPD,
27637 IX86_BUILTIN_MINSD,
27639 IX86_BUILTIN_ANDPD,
27640 IX86_BUILTIN_ANDNPD,
27641 IX86_BUILTIN_ORPD,
27642 IX86_BUILTIN_XORPD,
27644 IX86_BUILTIN_SQRTPD,
27645 IX86_BUILTIN_SQRTSD,
27647 IX86_BUILTIN_UNPCKHPD,
27648 IX86_BUILTIN_UNPCKLPD,
27650 IX86_BUILTIN_SHUFPD,
27652 IX86_BUILTIN_LOADUPD,
27653 IX86_BUILTIN_STOREUPD,
27654 IX86_BUILTIN_MOVSD,
27656 IX86_BUILTIN_LOADHPD,
27657 IX86_BUILTIN_LOADLPD,
27659 IX86_BUILTIN_CVTDQ2PD,
27660 IX86_BUILTIN_CVTDQ2PS,
27662 IX86_BUILTIN_CVTPD2DQ,
27663 IX86_BUILTIN_CVTPD2PI,
27664 IX86_BUILTIN_CVTPD2PS,
27665 IX86_BUILTIN_CVTTPD2DQ,
27666 IX86_BUILTIN_CVTTPD2PI,
27668 IX86_BUILTIN_CVTPI2PD,
27669 IX86_BUILTIN_CVTSI2SD,
27670 IX86_BUILTIN_CVTSI642SD,
27672 IX86_BUILTIN_CVTSD2SI,
27673 IX86_BUILTIN_CVTSD2SI64,
27674 IX86_BUILTIN_CVTSD2SS,
27675 IX86_BUILTIN_CVTSS2SD,
27676 IX86_BUILTIN_CVTTSD2SI,
27677 IX86_BUILTIN_CVTTSD2SI64,
27679 IX86_BUILTIN_CVTPS2DQ,
27680 IX86_BUILTIN_CVTPS2PD,
27681 IX86_BUILTIN_CVTTPS2DQ,
27683 IX86_BUILTIN_MOVNTI,
27684 IX86_BUILTIN_MOVNTI64,
27685 IX86_BUILTIN_MOVNTPD,
27686 IX86_BUILTIN_MOVNTDQ,
27688 IX86_BUILTIN_MOVQ128,
27690 /* SSE2 MMX */
27691 IX86_BUILTIN_MASKMOVDQU,
27692 IX86_BUILTIN_MOVMSKPD,
27693 IX86_BUILTIN_PMOVMSKB128,
27695 IX86_BUILTIN_PACKSSWB128,
27696 IX86_BUILTIN_PACKSSDW128,
27697 IX86_BUILTIN_PACKUSWB128,
27699 IX86_BUILTIN_PADDB128,
27700 IX86_BUILTIN_PADDW128,
27701 IX86_BUILTIN_PADDD128,
27702 IX86_BUILTIN_PADDQ128,
27703 IX86_BUILTIN_PADDSB128,
27704 IX86_BUILTIN_PADDSW128,
27705 IX86_BUILTIN_PADDUSB128,
27706 IX86_BUILTIN_PADDUSW128,
27707 IX86_BUILTIN_PSUBB128,
27708 IX86_BUILTIN_PSUBW128,
27709 IX86_BUILTIN_PSUBD128,
27710 IX86_BUILTIN_PSUBQ128,
27711 IX86_BUILTIN_PSUBSB128,
27712 IX86_BUILTIN_PSUBSW128,
27713 IX86_BUILTIN_PSUBUSB128,
27714 IX86_BUILTIN_PSUBUSW128,
27716 IX86_BUILTIN_PAND128,
27717 IX86_BUILTIN_PANDN128,
27718 IX86_BUILTIN_POR128,
27719 IX86_BUILTIN_PXOR128,
27721 IX86_BUILTIN_PAVGB128,
27722 IX86_BUILTIN_PAVGW128,
27724 IX86_BUILTIN_PCMPEQB128,
27725 IX86_BUILTIN_PCMPEQW128,
27726 IX86_BUILTIN_PCMPEQD128,
27727 IX86_BUILTIN_PCMPGTB128,
27728 IX86_BUILTIN_PCMPGTW128,
27729 IX86_BUILTIN_PCMPGTD128,
27731 IX86_BUILTIN_PMADDWD128,
27733 IX86_BUILTIN_PMAXSW128,
27734 IX86_BUILTIN_PMAXUB128,
27735 IX86_BUILTIN_PMINSW128,
27736 IX86_BUILTIN_PMINUB128,
27738 IX86_BUILTIN_PMULUDQ,
27739 IX86_BUILTIN_PMULUDQ128,
27740 IX86_BUILTIN_PMULHUW128,
27741 IX86_BUILTIN_PMULHW128,
27742 IX86_BUILTIN_PMULLW128,
27744 IX86_BUILTIN_PSADBW128,
27745 IX86_BUILTIN_PSHUFHW,
27746 IX86_BUILTIN_PSHUFLW,
27747 IX86_BUILTIN_PSHUFD,
27749 IX86_BUILTIN_PSLLDQI128,
27750 IX86_BUILTIN_PSLLWI128,
27751 IX86_BUILTIN_PSLLDI128,
27752 IX86_BUILTIN_PSLLQI128,
27753 IX86_BUILTIN_PSRAWI128,
27754 IX86_BUILTIN_PSRADI128,
27755 IX86_BUILTIN_PSRLDQI128,
27756 IX86_BUILTIN_PSRLWI128,
27757 IX86_BUILTIN_PSRLDI128,
27758 IX86_BUILTIN_PSRLQI128,
27760 IX86_BUILTIN_PSLLDQ128,
27761 IX86_BUILTIN_PSLLW128,
27762 IX86_BUILTIN_PSLLD128,
27763 IX86_BUILTIN_PSLLQ128,
27764 IX86_BUILTIN_PSRAW128,
27765 IX86_BUILTIN_PSRAD128,
27766 IX86_BUILTIN_PSRLW128,
27767 IX86_BUILTIN_PSRLD128,
27768 IX86_BUILTIN_PSRLQ128,
27770 IX86_BUILTIN_PUNPCKHBW128,
27771 IX86_BUILTIN_PUNPCKHWD128,
27772 IX86_BUILTIN_PUNPCKHDQ128,
27773 IX86_BUILTIN_PUNPCKHQDQ128,
27774 IX86_BUILTIN_PUNPCKLBW128,
27775 IX86_BUILTIN_PUNPCKLWD128,
27776 IX86_BUILTIN_PUNPCKLDQ128,
27777 IX86_BUILTIN_PUNPCKLQDQ128,
27779 IX86_BUILTIN_CLFLUSH,
27780 IX86_BUILTIN_MFENCE,
27781 IX86_BUILTIN_LFENCE,
27782 IX86_BUILTIN_PAUSE,
27784 IX86_BUILTIN_FNSTENV,
27785 IX86_BUILTIN_FLDENV,
27786 IX86_BUILTIN_FNSTSW,
27787 IX86_BUILTIN_FNCLEX,
27789 IX86_BUILTIN_BSRSI,
27790 IX86_BUILTIN_BSRDI,
27791 IX86_BUILTIN_RDPMC,
27792 IX86_BUILTIN_RDTSC,
27793 IX86_BUILTIN_RDTSCP,
27794 IX86_BUILTIN_ROLQI,
27795 IX86_BUILTIN_ROLHI,
27796 IX86_BUILTIN_RORQI,
27797 IX86_BUILTIN_RORHI,
27799 /* SSE3. */
27800 IX86_BUILTIN_ADDSUBPS,
27801 IX86_BUILTIN_HADDPS,
27802 IX86_BUILTIN_HSUBPS,
27803 IX86_BUILTIN_MOVSHDUP,
27804 IX86_BUILTIN_MOVSLDUP,
27805 IX86_BUILTIN_ADDSUBPD,
27806 IX86_BUILTIN_HADDPD,
27807 IX86_BUILTIN_HSUBPD,
27808 IX86_BUILTIN_LDDQU,
27810 IX86_BUILTIN_MONITOR,
27811 IX86_BUILTIN_MWAIT,
27813 /* SSSE3. */
27814 IX86_BUILTIN_PHADDW,
27815 IX86_BUILTIN_PHADDD,
27816 IX86_BUILTIN_PHADDSW,
27817 IX86_BUILTIN_PHSUBW,
27818 IX86_BUILTIN_PHSUBD,
27819 IX86_BUILTIN_PHSUBSW,
27820 IX86_BUILTIN_PMADDUBSW,
27821 IX86_BUILTIN_PMULHRSW,
27822 IX86_BUILTIN_PSHUFB,
27823 IX86_BUILTIN_PSIGNB,
27824 IX86_BUILTIN_PSIGNW,
27825 IX86_BUILTIN_PSIGND,
27826 IX86_BUILTIN_PALIGNR,
27827 IX86_BUILTIN_PABSB,
27828 IX86_BUILTIN_PABSW,
27829 IX86_BUILTIN_PABSD,
27831 IX86_BUILTIN_PHADDW128,
27832 IX86_BUILTIN_PHADDD128,
27833 IX86_BUILTIN_PHADDSW128,
27834 IX86_BUILTIN_PHSUBW128,
27835 IX86_BUILTIN_PHSUBD128,
27836 IX86_BUILTIN_PHSUBSW128,
27837 IX86_BUILTIN_PMADDUBSW128,
27838 IX86_BUILTIN_PMULHRSW128,
27839 IX86_BUILTIN_PSHUFB128,
27840 IX86_BUILTIN_PSIGNB128,
27841 IX86_BUILTIN_PSIGNW128,
27842 IX86_BUILTIN_PSIGND128,
27843 IX86_BUILTIN_PALIGNR128,
27844 IX86_BUILTIN_PABSB128,
27845 IX86_BUILTIN_PABSW128,
27846 IX86_BUILTIN_PABSD128,
27848 /* AMDFAM10 - SSE4A New Instructions. */
27849 IX86_BUILTIN_MOVNTSD,
27850 IX86_BUILTIN_MOVNTSS,
27851 IX86_BUILTIN_EXTRQI,
27852 IX86_BUILTIN_EXTRQ,
27853 IX86_BUILTIN_INSERTQI,
27854 IX86_BUILTIN_INSERTQ,
27856 /* SSE4.1. */
27857 IX86_BUILTIN_BLENDPD,
27858 IX86_BUILTIN_BLENDPS,
27859 IX86_BUILTIN_BLENDVPD,
27860 IX86_BUILTIN_BLENDVPS,
27861 IX86_BUILTIN_PBLENDVB128,
27862 IX86_BUILTIN_PBLENDW128,
27864 IX86_BUILTIN_DPPD,
27865 IX86_BUILTIN_DPPS,
27867 IX86_BUILTIN_INSERTPS128,
27869 IX86_BUILTIN_MOVNTDQA,
27870 IX86_BUILTIN_MPSADBW128,
27871 IX86_BUILTIN_PACKUSDW128,
27872 IX86_BUILTIN_PCMPEQQ,
27873 IX86_BUILTIN_PHMINPOSUW128,
27875 IX86_BUILTIN_PMAXSB128,
27876 IX86_BUILTIN_PMAXSD128,
27877 IX86_BUILTIN_PMAXUD128,
27878 IX86_BUILTIN_PMAXUW128,
27880 IX86_BUILTIN_PMINSB128,
27881 IX86_BUILTIN_PMINSD128,
27882 IX86_BUILTIN_PMINUD128,
27883 IX86_BUILTIN_PMINUW128,
27885 IX86_BUILTIN_PMOVSXBW128,
27886 IX86_BUILTIN_PMOVSXBD128,
27887 IX86_BUILTIN_PMOVSXBQ128,
27888 IX86_BUILTIN_PMOVSXWD128,
27889 IX86_BUILTIN_PMOVSXWQ128,
27890 IX86_BUILTIN_PMOVSXDQ128,
27892 IX86_BUILTIN_PMOVZXBW128,
27893 IX86_BUILTIN_PMOVZXBD128,
27894 IX86_BUILTIN_PMOVZXBQ128,
27895 IX86_BUILTIN_PMOVZXWD128,
27896 IX86_BUILTIN_PMOVZXWQ128,
27897 IX86_BUILTIN_PMOVZXDQ128,
27899 IX86_BUILTIN_PMULDQ128,
27900 IX86_BUILTIN_PMULLD128,
27902 IX86_BUILTIN_ROUNDSD,
27903 IX86_BUILTIN_ROUNDSS,
27905 IX86_BUILTIN_ROUNDPD,
27906 IX86_BUILTIN_ROUNDPS,
27908 IX86_BUILTIN_FLOORPD,
27909 IX86_BUILTIN_CEILPD,
27910 IX86_BUILTIN_TRUNCPD,
27911 IX86_BUILTIN_RINTPD,
27912 IX86_BUILTIN_ROUNDPD_AZ,
27914 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
27915 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
27916 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
27918 IX86_BUILTIN_FLOORPS,
27919 IX86_BUILTIN_CEILPS,
27920 IX86_BUILTIN_TRUNCPS,
27921 IX86_BUILTIN_RINTPS,
27922 IX86_BUILTIN_ROUNDPS_AZ,
27924 IX86_BUILTIN_FLOORPS_SFIX,
27925 IX86_BUILTIN_CEILPS_SFIX,
27926 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
27928 IX86_BUILTIN_PTESTZ,
27929 IX86_BUILTIN_PTESTC,
27930 IX86_BUILTIN_PTESTNZC,
27932 IX86_BUILTIN_VEC_INIT_V2SI,
27933 IX86_BUILTIN_VEC_INIT_V4HI,
27934 IX86_BUILTIN_VEC_INIT_V8QI,
27935 IX86_BUILTIN_VEC_EXT_V2DF,
27936 IX86_BUILTIN_VEC_EXT_V2DI,
27937 IX86_BUILTIN_VEC_EXT_V4SF,
27938 IX86_BUILTIN_VEC_EXT_V4SI,
27939 IX86_BUILTIN_VEC_EXT_V8HI,
27940 IX86_BUILTIN_VEC_EXT_V2SI,
27941 IX86_BUILTIN_VEC_EXT_V4HI,
27942 IX86_BUILTIN_VEC_EXT_V16QI,
27943 IX86_BUILTIN_VEC_SET_V2DI,
27944 IX86_BUILTIN_VEC_SET_V4SF,
27945 IX86_BUILTIN_VEC_SET_V4SI,
27946 IX86_BUILTIN_VEC_SET_V8HI,
27947 IX86_BUILTIN_VEC_SET_V4HI,
27948 IX86_BUILTIN_VEC_SET_V16QI,
27950 IX86_BUILTIN_VEC_PACK_SFIX,
27951 IX86_BUILTIN_VEC_PACK_SFIX256,
27953 /* SSE4.2. */
27954 IX86_BUILTIN_CRC32QI,
27955 IX86_BUILTIN_CRC32HI,
27956 IX86_BUILTIN_CRC32SI,
27957 IX86_BUILTIN_CRC32DI,
27959 IX86_BUILTIN_PCMPESTRI128,
27960 IX86_BUILTIN_PCMPESTRM128,
27961 IX86_BUILTIN_PCMPESTRA128,
27962 IX86_BUILTIN_PCMPESTRC128,
27963 IX86_BUILTIN_PCMPESTRO128,
27964 IX86_BUILTIN_PCMPESTRS128,
27965 IX86_BUILTIN_PCMPESTRZ128,
27966 IX86_BUILTIN_PCMPISTRI128,
27967 IX86_BUILTIN_PCMPISTRM128,
27968 IX86_BUILTIN_PCMPISTRA128,
27969 IX86_BUILTIN_PCMPISTRC128,
27970 IX86_BUILTIN_PCMPISTRO128,
27971 IX86_BUILTIN_PCMPISTRS128,
27972 IX86_BUILTIN_PCMPISTRZ128,
27974 IX86_BUILTIN_PCMPGTQ,
27976 /* AES instructions */
27977 IX86_BUILTIN_AESENC128,
27978 IX86_BUILTIN_AESENCLAST128,
27979 IX86_BUILTIN_AESDEC128,
27980 IX86_BUILTIN_AESDECLAST128,
27981 IX86_BUILTIN_AESIMC128,
27982 IX86_BUILTIN_AESKEYGENASSIST128,
27984 /* PCLMUL instruction */
27985 IX86_BUILTIN_PCLMULQDQ128,
27987 /* AVX */
27988 IX86_BUILTIN_ADDPD256,
27989 IX86_BUILTIN_ADDPS256,
27990 IX86_BUILTIN_ADDSUBPD256,
27991 IX86_BUILTIN_ADDSUBPS256,
27992 IX86_BUILTIN_ANDPD256,
27993 IX86_BUILTIN_ANDPS256,
27994 IX86_BUILTIN_ANDNPD256,
27995 IX86_BUILTIN_ANDNPS256,
27996 IX86_BUILTIN_BLENDPD256,
27997 IX86_BUILTIN_BLENDPS256,
27998 IX86_BUILTIN_BLENDVPD256,
27999 IX86_BUILTIN_BLENDVPS256,
28000 IX86_BUILTIN_DIVPD256,
28001 IX86_BUILTIN_DIVPS256,
28002 IX86_BUILTIN_DPPS256,
28003 IX86_BUILTIN_HADDPD256,
28004 IX86_BUILTIN_HADDPS256,
28005 IX86_BUILTIN_HSUBPD256,
28006 IX86_BUILTIN_HSUBPS256,
28007 IX86_BUILTIN_MAXPD256,
28008 IX86_BUILTIN_MAXPS256,
28009 IX86_BUILTIN_MINPD256,
28010 IX86_BUILTIN_MINPS256,
28011 IX86_BUILTIN_MULPD256,
28012 IX86_BUILTIN_MULPS256,
28013 IX86_BUILTIN_ORPD256,
28014 IX86_BUILTIN_ORPS256,
28015 IX86_BUILTIN_SHUFPD256,
28016 IX86_BUILTIN_SHUFPS256,
28017 IX86_BUILTIN_SUBPD256,
28018 IX86_BUILTIN_SUBPS256,
28019 IX86_BUILTIN_XORPD256,
28020 IX86_BUILTIN_XORPS256,
28021 IX86_BUILTIN_CMPSD,
28022 IX86_BUILTIN_CMPSS,
28023 IX86_BUILTIN_CMPPD,
28024 IX86_BUILTIN_CMPPS,
28025 IX86_BUILTIN_CMPPD256,
28026 IX86_BUILTIN_CMPPS256,
28027 IX86_BUILTIN_CVTDQ2PD256,
28028 IX86_BUILTIN_CVTDQ2PS256,
28029 IX86_BUILTIN_CVTPD2PS256,
28030 IX86_BUILTIN_CVTPS2DQ256,
28031 IX86_BUILTIN_CVTPS2PD256,
28032 IX86_BUILTIN_CVTTPD2DQ256,
28033 IX86_BUILTIN_CVTPD2DQ256,
28034 IX86_BUILTIN_CVTTPS2DQ256,
28035 IX86_BUILTIN_EXTRACTF128PD256,
28036 IX86_BUILTIN_EXTRACTF128PS256,
28037 IX86_BUILTIN_EXTRACTF128SI256,
28038 IX86_BUILTIN_VZEROALL,
28039 IX86_BUILTIN_VZEROUPPER,
28040 IX86_BUILTIN_VPERMILVARPD,
28041 IX86_BUILTIN_VPERMILVARPS,
28042 IX86_BUILTIN_VPERMILVARPD256,
28043 IX86_BUILTIN_VPERMILVARPS256,
28044 IX86_BUILTIN_VPERMILPD,
28045 IX86_BUILTIN_VPERMILPS,
28046 IX86_BUILTIN_VPERMILPD256,
28047 IX86_BUILTIN_VPERMILPS256,
28048 IX86_BUILTIN_VPERMIL2PD,
28049 IX86_BUILTIN_VPERMIL2PS,
28050 IX86_BUILTIN_VPERMIL2PD256,
28051 IX86_BUILTIN_VPERMIL2PS256,
28052 IX86_BUILTIN_VPERM2F128PD256,
28053 IX86_BUILTIN_VPERM2F128PS256,
28054 IX86_BUILTIN_VPERM2F128SI256,
28055 IX86_BUILTIN_VBROADCASTSS,
28056 IX86_BUILTIN_VBROADCASTSD256,
28057 IX86_BUILTIN_VBROADCASTSS256,
28058 IX86_BUILTIN_VBROADCASTPD256,
28059 IX86_BUILTIN_VBROADCASTPS256,
28060 IX86_BUILTIN_VINSERTF128PD256,
28061 IX86_BUILTIN_VINSERTF128PS256,
28062 IX86_BUILTIN_VINSERTF128SI256,
28063 IX86_BUILTIN_LOADUPD256,
28064 IX86_BUILTIN_LOADUPS256,
28065 IX86_BUILTIN_STOREUPD256,
28066 IX86_BUILTIN_STOREUPS256,
28067 IX86_BUILTIN_LDDQU256,
28068 IX86_BUILTIN_MOVNTDQ256,
28069 IX86_BUILTIN_MOVNTPD256,
28070 IX86_BUILTIN_MOVNTPS256,
28071 IX86_BUILTIN_LOADDQU256,
28072 IX86_BUILTIN_STOREDQU256,
28073 IX86_BUILTIN_MASKLOADPD,
28074 IX86_BUILTIN_MASKLOADPS,
28075 IX86_BUILTIN_MASKSTOREPD,
28076 IX86_BUILTIN_MASKSTOREPS,
28077 IX86_BUILTIN_MASKLOADPD256,
28078 IX86_BUILTIN_MASKLOADPS256,
28079 IX86_BUILTIN_MASKSTOREPD256,
28080 IX86_BUILTIN_MASKSTOREPS256,
28081 IX86_BUILTIN_MOVSHDUP256,
28082 IX86_BUILTIN_MOVSLDUP256,
28083 IX86_BUILTIN_MOVDDUP256,
28085 IX86_BUILTIN_SQRTPD256,
28086 IX86_BUILTIN_SQRTPS256,
28087 IX86_BUILTIN_SQRTPS_NR256,
28088 IX86_BUILTIN_RSQRTPS256,
28089 IX86_BUILTIN_RSQRTPS_NR256,
28091 IX86_BUILTIN_RCPPS256,
28093 IX86_BUILTIN_ROUNDPD256,
28094 IX86_BUILTIN_ROUNDPS256,
28096 IX86_BUILTIN_FLOORPD256,
28097 IX86_BUILTIN_CEILPD256,
28098 IX86_BUILTIN_TRUNCPD256,
28099 IX86_BUILTIN_RINTPD256,
28100 IX86_BUILTIN_ROUNDPD_AZ256,
28102 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28103 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28104 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28106 IX86_BUILTIN_FLOORPS256,
28107 IX86_BUILTIN_CEILPS256,
28108 IX86_BUILTIN_TRUNCPS256,
28109 IX86_BUILTIN_RINTPS256,
28110 IX86_BUILTIN_ROUNDPS_AZ256,
28112 IX86_BUILTIN_FLOORPS_SFIX256,
28113 IX86_BUILTIN_CEILPS_SFIX256,
28114 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28116 IX86_BUILTIN_UNPCKHPD256,
28117 IX86_BUILTIN_UNPCKLPD256,
28118 IX86_BUILTIN_UNPCKHPS256,
28119 IX86_BUILTIN_UNPCKLPS256,
28121 IX86_BUILTIN_SI256_SI,
28122 IX86_BUILTIN_PS256_PS,
28123 IX86_BUILTIN_PD256_PD,
28124 IX86_BUILTIN_SI_SI256,
28125 IX86_BUILTIN_PS_PS256,
28126 IX86_BUILTIN_PD_PD256,
28128 IX86_BUILTIN_VTESTZPD,
28129 IX86_BUILTIN_VTESTCPD,
28130 IX86_BUILTIN_VTESTNZCPD,
28131 IX86_BUILTIN_VTESTZPS,
28132 IX86_BUILTIN_VTESTCPS,
28133 IX86_BUILTIN_VTESTNZCPS,
28134 IX86_BUILTIN_VTESTZPD256,
28135 IX86_BUILTIN_VTESTCPD256,
28136 IX86_BUILTIN_VTESTNZCPD256,
28137 IX86_BUILTIN_VTESTZPS256,
28138 IX86_BUILTIN_VTESTCPS256,
28139 IX86_BUILTIN_VTESTNZCPS256,
28140 IX86_BUILTIN_PTESTZ256,
28141 IX86_BUILTIN_PTESTC256,
28142 IX86_BUILTIN_PTESTNZC256,
28144 IX86_BUILTIN_MOVMSKPD256,
28145 IX86_BUILTIN_MOVMSKPS256,
28147 /* AVX2 */
28148 IX86_BUILTIN_MPSADBW256,
28149 IX86_BUILTIN_PABSB256,
28150 IX86_BUILTIN_PABSW256,
28151 IX86_BUILTIN_PABSD256,
28152 IX86_BUILTIN_PACKSSDW256,
28153 IX86_BUILTIN_PACKSSWB256,
28154 IX86_BUILTIN_PACKUSDW256,
28155 IX86_BUILTIN_PACKUSWB256,
28156 IX86_BUILTIN_PADDB256,
28157 IX86_BUILTIN_PADDW256,
28158 IX86_BUILTIN_PADDD256,
28159 IX86_BUILTIN_PADDQ256,
28160 IX86_BUILTIN_PADDSB256,
28161 IX86_BUILTIN_PADDSW256,
28162 IX86_BUILTIN_PADDUSB256,
28163 IX86_BUILTIN_PADDUSW256,
28164 IX86_BUILTIN_PALIGNR256,
28165 IX86_BUILTIN_AND256I,
28166 IX86_BUILTIN_ANDNOT256I,
28167 IX86_BUILTIN_PAVGB256,
28168 IX86_BUILTIN_PAVGW256,
28169 IX86_BUILTIN_PBLENDVB256,
28170 IX86_BUILTIN_PBLENDVW256,
28171 IX86_BUILTIN_PCMPEQB256,
28172 IX86_BUILTIN_PCMPEQW256,
28173 IX86_BUILTIN_PCMPEQD256,
28174 IX86_BUILTIN_PCMPEQQ256,
28175 IX86_BUILTIN_PCMPGTB256,
28176 IX86_BUILTIN_PCMPGTW256,
28177 IX86_BUILTIN_PCMPGTD256,
28178 IX86_BUILTIN_PCMPGTQ256,
28179 IX86_BUILTIN_PHADDW256,
28180 IX86_BUILTIN_PHADDD256,
28181 IX86_BUILTIN_PHADDSW256,
28182 IX86_BUILTIN_PHSUBW256,
28183 IX86_BUILTIN_PHSUBD256,
28184 IX86_BUILTIN_PHSUBSW256,
28185 IX86_BUILTIN_PMADDUBSW256,
28186 IX86_BUILTIN_PMADDWD256,
28187 IX86_BUILTIN_PMAXSB256,
28188 IX86_BUILTIN_PMAXSW256,
28189 IX86_BUILTIN_PMAXSD256,
28190 IX86_BUILTIN_PMAXUB256,
28191 IX86_BUILTIN_PMAXUW256,
28192 IX86_BUILTIN_PMAXUD256,
28193 IX86_BUILTIN_PMINSB256,
28194 IX86_BUILTIN_PMINSW256,
28195 IX86_BUILTIN_PMINSD256,
28196 IX86_BUILTIN_PMINUB256,
28197 IX86_BUILTIN_PMINUW256,
28198 IX86_BUILTIN_PMINUD256,
28199 IX86_BUILTIN_PMOVMSKB256,
28200 IX86_BUILTIN_PMOVSXBW256,
28201 IX86_BUILTIN_PMOVSXBD256,
28202 IX86_BUILTIN_PMOVSXBQ256,
28203 IX86_BUILTIN_PMOVSXWD256,
28204 IX86_BUILTIN_PMOVSXWQ256,
28205 IX86_BUILTIN_PMOVSXDQ256,
28206 IX86_BUILTIN_PMOVZXBW256,
28207 IX86_BUILTIN_PMOVZXBD256,
28208 IX86_BUILTIN_PMOVZXBQ256,
28209 IX86_BUILTIN_PMOVZXWD256,
28210 IX86_BUILTIN_PMOVZXWQ256,
28211 IX86_BUILTIN_PMOVZXDQ256,
28212 IX86_BUILTIN_PMULDQ256,
28213 IX86_BUILTIN_PMULHRSW256,
28214 IX86_BUILTIN_PMULHUW256,
28215 IX86_BUILTIN_PMULHW256,
28216 IX86_BUILTIN_PMULLW256,
28217 IX86_BUILTIN_PMULLD256,
28218 IX86_BUILTIN_PMULUDQ256,
28219 IX86_BUILTIN_POR256,
28220 IX86_BUILTIN_PSADBW256,
28221 IX86_BUILTIN_PSHUFB256,
28222 IX86_BUILTIN_PSHUFD256,
28223 IX86_BUILTIN_PSHUFHW256,
28224 IX86_BUILTIN_PSHUFLW256,
28225 IX86_BUILTIN_PSIGNB256,
28226 IX86_BUILTIN_PSIGNW256,
28227 IX86_BUILTIN_PSIGND256,
28228 IX86_BUILTIN_PSLLDQI256,
28229 IX86_BUILTIN_PSLLWI256,
28230 IX86_BUILTIN_PSLLW256,
28231 IX86_BUILTIN_PSLLDI256,
28232 IX86_BUILTIN_PSLLD256,
28233 IX86_BUILTIN_PSLLQI256,
28234 IX86_BUILTIN_PSLLQ256,
28235 IX86_BUILTIN_PSRAWI256,
28236 IX86_BUILTIN_PSRAW256,
28237 IX86_BUILTIN_PSRADI256,
28238 IX86_BUILTIN_PSRAD256,
28239 IX86_BUILTIN_PSRLDQI256,
28240 IX86_BUILTIN_PSRLWI256,
28241 IX86_BUILTIN_PSRLW256,
28242 IX86_BUILTIN_PSRLDI256,
28243 IX86_BUILTIN_PSRLD256,
28244 IX86_BUILTIN_PSRLQI256,
28245 IX86_BUILTIN_PSRLQ256,
28246 IX86_BUILTIN_PSUBB256,
28247 IX86_BUILTIN_PSUBW256,
28248 IX86_BUILTIN_PSUBD256,
28249 IX86_BUILTIN_PSUBQ256,
28250 IX86_BUILTIN_PSUBSB256,
28251 IX86_BUILTIN_PSUBSW256,
28252 IX86_BUILTIN_PSUBUSB256,
28253 IX86_BUILTIN_PSUBUSW256,
28254 IX86_BUILTIN_PUNPCKHBW256,
28255 IX86_BUILTIN_PUNPCKHWD256,
28256 IX86_BUILTIN_PUNPCKHDQ256,
28257 IX86_BUILTIN_PUNPCKHQDQ256,
28258 IX86_BUILTIN_PUNPCKLBW256,
28259 IX86_BUILTIN_PUNPCKLWD256,
28260 IX86_BUILTIN_PUNPCKLDQ256,
28261 IX86_BUILTIN_PUNPCKLQDQ256,
28262 IX86_BUILTIN_PXOR256,
28263 IX86_BUILTIN_MOVNTDQA256,
28264 IX86_BUILTIN_VBROADCASTSS_PS,
28265 IX86_BUILTIN_VBROADCASTSS_PS256,
28266 IX86_BUILTIN_VBROADCASTSD_PD256,
28267 IX86_BUILTIN_VBROADCASTSI256,
28268 IX86_BUILTIN_PBLENDD256,
28269 IX86_BUILTIN_PBLENDD128,
28270 IX86_BUILTIN_PBROADCASTB256,
28271 IX86_BUILTIN_PBROADCASTW256,
28272 IX86_BUILTIN_PBROADCASTD256,
28273 IX86_BUILTIN_PBROADCASTQ256,
28274 IX86_BUILTIN_PBROADCASTB128,
28275 IX86_BUILTIN_PBROADCASTW128,
28276 IX86_BUILTIN_PBROADCASTD128,
28277 IX86_BUILTIN_PBROADCASTQ128,
28278 IX86_BUILTIN_VPERMVARSI256,
28279 IX86_BUILTIN_VPERMDF256,
28280 IX86_BUILTIN_VPERMVARSF256,
28281 IX86_BUILTIN_VPERMDI256,
28282 IX86_BUILTIN_VPERMTI256,
28283 IX86_BUILTIN_VEXTRACT128I256,
28284 IX86_BUILTIN_VINSERT128I256,
28285 IX86_BUILTIN_MASKLOADD,
28286 IX86_BUILTIN_MASKLOADQ,
28287 IX86_BUILTIN_MASKLOADD256,
28288 IX86_BUILTIN_MASKLOADQ256,
28289 IX86_BUILTIN_MASKSTORED,
28290 IX86_BUILTIN_MASKSTOREQ,
28291 IX86_BUILTIN_MASKSTORED256,
28292 IX86_BUILTIN_MASKSTOREQ256,
28293 IX86_BUILTIN_PSLLVV4DI,
28294 IX86_BUILTIN_PSLLVV2DI,
28295 IX86_BUILTIN_PSLLVV8SI,
28296 IX86_BUILTIN_PSLLVV4SI,
28297 IX86_BUILTIN_PSRAVV8SI,
28298 IX86_BUILTIN_PSRAVV4SI,
28299 IX86_BUILTIN_PSRLVV4DI,
28300 IX86_BUILTIN_PSRLVV2DI,
28301 IX86_BUILTIN_PSRLVV8SI,
28302 IX86_BUILTIN_PSRLVV4SI,
28304 IX86_BUILTIN_GATHERSIV2DF,
28305 IX86_BUILTIN_GATHERSIV4DF,
28306 IX86_BUILTIN_GATHERDIV2DF,
28307 IX86_BUILTIN_GATHERDIV4DF,
28308 IX86_BUILTIN_GATHERSIV4SF,
28309 IX86_BUILTIN_GATHERSIV8SF,
28310 IX86_BUILTIN_GATHERDIV4SF,
28311 IX86_BUILTIN_GATHERDIV8SF,
28312 IX86_BUILTIN_GATHERSIV2DI,
28313 IX86_BUILTIN_GATHERSIV4DI,
28314 IX86_BUILTIN_GATHERDIV2DI,
28315 IX86_BUILTIN_GATHERDIV4DI,
28316 IX86_BUILTIN_GATHERSIV4SI,
28317 IX86_BUILTIN_GATHERSIV8SI,
28318 IX86_BUILTIN_GATHERDIV4SI,
28319 IX86_BUILTIN_GATHERDIV8SI,
28321 /* AVX512F */
28322 IX86_BUILTIN_ADDPD512,
28323 IX86_BUILTIN_ADDPS512,
28324 IX86_BUILTIN_ADDSD_ROUND,
28325 IX86_BUILTIN_ADDSS_ROUND,
28326 IX86_BUILTIN_ALIGND512,
28327 IX86_BUILTIN_ALIGNQ512,
28328 IX86_BUILTIN_BLENDMD512,
28329 IX86_BUILTIN_BLENDMPD512,
28330 IX86_BUILTIN_BLENDMPS512,
28331 IX86_BUILTIN_BLENDMQ512,
28332 IX86_BUILTIN_BROADCASTF32X4_512,
28333 IX86_BUILTIN_BROADCASTF64X4_512,
28334 IX86_BUILTIN_BROADCASTI32X4_512,
28335 IX86_BUILTIN_BROADCASTI64X4_512,
28336 IX86_BUILTIN_BROADCASTSD512,
28337 IX86_BUILTIN_BROADCASTSS512,
28338 IX86_BUILTIN_CMPD512,
28339 IX86_BUILTIN_CMPPD512,
28340 IX86_BUILTIN_CMPPS512,
28341 IX86_BUILTIN_CMPQ512,
28342 IX86_BUILTIN_CMPSD_MASK,
28343 IX86_BUILTIN_CMPSS_MASK,
28344 IX86_BUILTIN_COMIDF,
28345 IX86_BUILTIN_COMISF,
28346 IX86_BUILTIN_COMPRESSPD512,
28347 IX86_BUILTIN_COMPRESSPDSTORE512,
28348 IX86_BUILTIN_COMPRESSPS512,
28349 IX86_BUILTIN_COMPRESSPSSTORE512,
28350 IX86_BUILTIN_CVTDQ2PD512,
28351 IX86_BUILTIN_CVTDQ2PS512,
28352 IX86_BUILTIN_CVTPD2DQ512,
28353 IX86_BUILTIN_CVTPD2PS512,
28354 IX86_BUILTIN_CVTPD2UDQ512,
28355 IX86_BUILTIN_CVTPH2PS512,
28356 IX86_BUILTIN_CVTPS2DQ512,
28357 IX86_BUILTIN_CVTPS2PD512,
28358 IX86_BUILTIN_CVTPS2PH512,
28359 IX86_BUILTIN_CVTPS2UDQ512,
28360 IX86_BUILTIN_CVTSD2SS_ROUND,
28361 IX86_BUILTIN_CVTSI2SD64,
28362 IX86_BUILTIN_CVTSI2SS32,
28363 IX86_BUILTIN_CVTSI2SS64,
28364 IX86_BUILTIN_CVTSS2SD_ROUND,
28365 IX86_BUILTIN_CVTTPD2DQ512,
28366 IX86_BUILTIN_CVTTPD2UDQ512,
28367 IX86_BUILTIN_CVTTPS2DQ512,
28368 IX86_BUILTIN_CVTTPS2UDQ512,
28369 IX86_BUILTIN_CVTUDQ2PD512,
28370 IX86_BUILTIN_CVTUDQ2PS512,
28371 IX86_BUILTIN_CVTUSI2SD32,
28372 IX86_BUILTIN_CVTUSI2SD64,
28373 IX86_BUILTIN_CVTUSI2SS32,
28374 IX86_BUILTIN_CVTUSI2SS64,
28375 IX86_BUILTIN_DIVPD512,
28376 IX86_BUILTIN_DIVPS512,
28377 IX86_BUILTIN_DIVSD_ROUND,
28378 IX86_BUILTIN_DIVSS_ROUND,
28379 IX86_BUILTIN_EXPANDPD512,
28380 IX86_BUILTIN_EXPANDPD512Z,
28381 IX86_BUILTIN_EXPANDPDLOAD512,
28382 IX86_BUILTIN_EXPANDPDLOAD512Z,
28383 IX86_BUILTIN_EXPANDPS512,
28384 IX86_BUILTIN_EXPANDPS512Z,
28385 IX86_BUILTIN_EXPANDPSLOAD512,
28386 IX86_BUILTIN_EXPANDPSLOAD512Z,
28387 IX86_BUILTIN_EXTRACTF32X4,
28388 IX86_BUILTIN_EXTRACTF64X4,
28389 IX86_BUILTIN_EXTRACTI32X4,
28390 IX86_BUILTIN_EXTRACTI64X4,
28391 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28392 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28393 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28394 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28395 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28396 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28397 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28398 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28399 IX86_BUILTIN_GETEXPPD512,
28400 IX86_BUILTIN_GETEXPPS512,
28401 IX86_BUILTIN_GETEXPSD128,
28402 IX86_BUILTIN_GETEXPSS128,
28403 IX86_BUILTIN_GETMANTPD512,
28404 IX86_BUILTIN_GETMANTPS512,
28405 IX86_BUILTIN_GETMANTSD128,
28406 IX86_BUILTIN_GETMANTSS128,
28407 IX86_BUILTIN_INSERTF32X4,
28408 IX86_BUILTIN_INSERTF64X4,
28409 IX86_BUILTIN_INSERTI32X4,
28410 IX86_BUILTIN_INSERTI64X4,
28411 IX86_BUILTIN_LOADAPD512,
28412 IX86_BUILTIN_LOADAPS512,
28413 IX86_BUILTIN_LOADDQUDI512,
28414 IX86_BUILTIN_LOADDQUSI512,
28415 IX86_BUILTIN_LOADUPD512,
28416 IX86_BUILTIN_LOADUPS512,
28417 IX86_BUILTIN_MAXPD512,
28418 IX86_BUILTIN_MAXPS512,
28419 IX86_BUILTIN_MAXSD_ROUND,
28420 IX86_BUILTIN_MAXSS_ROUND,
28421 IX86_BUILTIN_MINPD512,
28422 IX86_BUILTIN_MINPS512,
28423 IX86_BUILTIN_MINSD_ROUND,
28424 IX86_BUILTIN_MINSS_ROUND,
28425 IX86_BUILTIN_MOVAPD512,
28426 IX86_BUILTIN_MOVAPS512,
28427 IX86_BUILTIN_MOVDDUP512,
28428 IX86_BUILTIN_MOVDQA32LOAD512,
28429 IX86_BUILTIN_MOVDQA32STORE512,
28430 IX86_BUILTIN_MOVDQA32_512,
28431 IX86_BUILTIN_MOVDQA64LOAD512,
28432 IX86_BUILTIN_MOVDQA64STORE512,
28433 IX86_BUILTIN_MOVDQA64_512,
28434 IX86_BUILTIN_MOVNTDQ512,
28435 IX86_BUILTIN_MOVNTDQA512,
28436 IX86_BUILTIN_MOVNTPD512,
28437 IX86_BUILTIN_MOVNTPS512,
28438 IX86_BUILTIN_MOVSHDUP512,
28439 IX86_BUILTIN_MOVSLDUP512,
28440 IX86_BUILTIN_MULPD512,
28441 IX86_BUILTIN_MULPS512,
28442 IX86_BUILTIN_MULSD_ROUND,
28443 IX86_BUILTIN_MULSS_ROUND,
28444 IX86_BUILTIN_PABSD512,
28445 IX86_BUILTIN_PABSQ512,
28446 IX86_BUILTIN_PADDD512,
28447 IX86_BUILTIN_PADDQ512,
28448 IX86_BUILTIN_PANDD512,
28449 IX86_BUILTIN_PANDND512,
28450 IX86_BUILTIN_PANDNQ512,
28451 IX86_BUILTIN_PANDQ512,
28452 IX86_BUILTIN_PBROADCASTD512,
28453 IX86_BUILTIN_PBROADCASTD512_GPR,
28454 IX86_BUILTIN_PBROADCASTMB512,
28455 IX86_BUILTIN_PBROADCASTMW512,
28456 IX86_BUILTIN_PBROADCASTQ512,
28457 IX86_BUILTIN_PBROADCASTQ512_GPR,
28458 IX86_BUILTIN_PBROADCASTQ512_MEM,
28459 IX86_BUILTIN_PCMPEQD512_MASK,
28460 IX86_BUILTIN_PCMPEQQ512_MASK,
28461 IX86_BUILTIN_PCMPGTD512_MASK,
28462 IX86_BUILTIN_PCMPGTQ512_MASK,
28463 IX86_BUILTIN_PCOMPRESSD512,
28464 IX86_BUILTIN_PCOMPRESSDSTORE512,
28465 IX86_BUILTIN_PCOMPRESSQ512,
28466 IX86_BUILTIN_PCOMPRESSQSTORE512,
28467 IX86_BUILTIN_PEXPANDD512,
28468 IX86_BUILTIN_PEXPANDD512Z,
28469 IX86_BUILTIN_PEXPANDDLOAD512,
28470 IX86_BUILTIN_PEXPANDDLOAD512Z,
28471 IX86_BUILTIN_PEXPANDQ512,
28472 IX86_BUILTIN_PEXPANDQ512Z,
28473 IX86_BUILTIN_PEXPANDQLOAD512,
28474 IX86_BUILTIN_PEXPANDQLOAD512Z,
28475 IX86_BUILTIN_PMAXSD512,
28476 IX86_BUILTIN_PMAXSQ512,
28477 IX86_BUILTIN_PMAXUD512,
28478 IX86_BUILTIN_PMAXUQ512,
28479 IX86_BUILTIN_PMINSD512,
28480 IX86_BUILTIN_PMINSQ512,
28481 IX86_BUILTIN_PMINUD512,
28482 IX86_BUILTIN_PMINUQ512,
28483 IX86_BUILTIN_PMOVDB512,
28484 IX86_BUILTIN_PMOVDB512_MEM,
28485 IX86_BUILTIN_PMOVDW512,
28486 IX86_BUILTIN_PMOVDW512_MEM,
28487 IX86_BUILTIN_PMOVQB512,
28488 IX86_BUILTIN_PMOVQB512_MEM,
28489 IX86_BUILTIN_PMOVQD512,
28490 IX86_BUILTIN_PMOVQD512_MEM,
28491 IX86_BUILTIN_PMOVQW512,
28492 IX86_BUILTIN_PMOVQW512_MEM,
28493 IX86_BUILTIN_PMOVSDB512,
28494 IX86_BUILTIN_PMOVSDB512_MEM,
28495 IX86_BUILTIN_PMOVSDW512,
28496 IX86_BUILTIN_PMOVSDW512_MEM,
28497 IX86_BUILTIN_PMOVSQB512,
28498 IX86_BUILTIN_PMOVSQB512_MEM,
28499 IX86_BUILTIN_PMOVSQD512,
28500 IX86_BUILTIN_PMOVSQD512_MEM,
28501 IX86_BUILTIN_PMOVSQW512,
28502 IX86_BUILTIN_PMOVSQW512_MEM,
28503 IX86_BUILTIN_PMOVSXBD512,
28504 IX86_BUILTIN_PMOVSXBQ512,
28505 IX86_BUILTIN_PMOVSXDQ512,
28506 IX86_BUILTIN_PMOVSXWD512,
28507 IX86_BUILTIN_PMOVSXWQ512,
28508 IX86_BUILTIN_PMOVUSDB512,
28509 IX86_BUILTIN_PMOVUSDB512_MEM,
28510 IX86_BUILTIN_PMOVUSDW512,
28511 IX86_BUILTIN_PMOVUSDW512_MEM,
28512 IX86_BUILTIN_PMOVUSQB512,
28513 IX86_BUILTIN_PMOVUSQB512_MEM,
28514 IX86_BUILTIN_PMOVUSQD512,
28515 IX86_BUILTIN_PMOVUSQD512_MEM,
28516 IX86_BUILTIN_PMOVUSQW512,
28517 IX86_BUILTIN_PMOVUSQW512_MEM,
28518 IX86_BUILTIN_PMOVZXBD512,
28519 IX86_BUILTIN_PMOVZXBQ512,
28520 IX86_BUILTIN_PMOVZXDQ512,
28521 IX86_BUILTIN_PMOVZXWD512,
28522 IX86_BUILTIN_PMOVZXWQ512,
28523 IX86_BUILTIN_PMULDQ512,
28524 IX86_BUILTIN_PMULLD512,
28525 IX86_BUILTIN_PMULUDQ512,
28526 IX86_BUILTIN_PORD512,
28527 IX86_BUILTIN_PORQ512,
28528 IX86_BUILTIN_PROLD512,
28529 IX86_BUILTIN_PROLQ512,
28530 IX86_BUILTIN_PROLVD512,
28531 IX86_BUILTIN_PROLVQ512,
28532 IX86_BUILTIN_PRORD512,
28533 IX86_BUILTIN_PRORQ512,
28534 IX86_BUILTIN_PRORVD512,
28535 IX86_BUILTIN_PRORVQ512,
28536 IX86_BUILTIN_PSHUFD512,
28537 IX86_BUILTIN_PSLLD512,
28538 IX86_BUILTIN_PSLLDI512,
28539 IX86_BUILTIN_PSLLQ512,
28540 IX86_BUILTIN_PSLLQI512,
28541 IX86_BUILTIN_PSLLVV16SI,
28542 IX86_BUILTIN_PSLLVV8DI,
28543 IX86_BUILTIN_PSRAD512,
28544 IX86_BUILTIN_PSRADI512,
28545 IX86_BUILTIN_PSRAQ512,
28546 IX86_BUILTIN_PSRAQI512,
28547 IX86_BUILTIN_PSRAVV16SI,
28548 IX86_BUILTIN_PSRAVV8DI,
28549 IX86_BUILTIN_PSRLD512,
28550 IX86_BUILTIN_PSRLDI512,
28551 IX86_BUILTIN_PSRLQ512,
28552 IX86_BUILTIN_PSRLQI512,
28553 IX86_BUILTIN_PSRLVV16SI,
28554 IX86_BUILTIN_PSRLVV8DI,
28555 IX86_BUILTIN_PSUBD512,
28556 IX86_BUILTIN_PSUBQ512,
28557 IX86_BUILTIN_PTESTMD512,
28558 IX86_BUILTIN_PTESTMQ512,
28559 IX86_BUILTIN_PTESTNMD512,
28560 IX86_BUILTIN_PTESTNMQ512,
28561 IX86_BUILTIN_PUNPCKHDQ512,
28562 IX86_BUILTIN_PUNPCKHQDQ512,
28563 IX86_BUILTIN_PUNPCKLDQ512,
28564 IX86_BUILTIN_PUNPCKLQDQ512,
28565 IX86_BUILTIN_PXORD512,
28566 IX86_BUILTIN_PXORQ512,
28567 IX86_BUILTIN_RCP14PD512,
28568 IX86_BUILTIN_RCP14PS512,
28569 IX86_BUILTIN_RCP14SD,
28570 IX86_BUILTIN_RCP14SS,
28571 IX86_BUILTIN_RNDSCALEPD,
28572 IX86_BUILTIN_RNDSCALEPS,
28573 IX86_BUILTIN_RNDSCALESD,
28574 IX86_BUILTIN_RNDSCALESS,
28575 IX86_BUILTIN_RSQRT14PD512,
28576 IX86_BUILTIN_RSQRT14PS512,
28577 IX86_BUILTIN_RSQRT14SD,
28578 IX86_BUILTIN_RSQRT14SS,
28579 IX86_BUILTIN_SCALEFPD512,
28580 IX86_BUILTIN_SCALEFPS512,
28581 IX86_BUILTIN_SCALEFSD,
28582 IX86_BUILTIN_SCALEFSS,
28583 IX86_BUILTIN_SHUFPD512,
28584 IX86_BUILTIN_SHUFPS512,
28585 IX86_BUILTIN_SHUF_F32x4,
28586 IX86_BUILTIN_SHUF_F64x2,
28587 IX86_BUILTIN_SHUF_I32x4,
28588 IX86_BUILTIN_SHUF_I64x2,
28589 IX86_BUILTIN_SQRTPD512,
28590 IX86_BUILTIN_SQRTPD512_MASK,
28591 IX86_BUILTIN_SQRTPS512_MASK,
28592 IX86_BUILTIN_SQRTPS_NR512,
28593 IX86_BUILTIN_SQRTSD_ROUND,
28594 IX86_BUILTIN_SQRTSS_ROUND,
28595 IX86_BUILTIN_STOREAPD512,
28596 IX86_BUILTIN_STOREAPS512,
28597 IX86_BUILTIN_STOREDQUDI512,
28598 IX86_BUILTIN_STOREDQUSI512,
28599 IX86_BUILTIN_STOREUPD512,
28600 IX86_BUILTIN_STOREUPS512,
28601 IX86_BUILTIN_SUBPD512,
28602 IX86_BUILTIN_SUBPS512,
28603 IX86_BUILTIN_SUBSD_ROUND,
28604 IX86_BUILTIN_SUBSS_ROUND,
28605 IX86_BUILTIN_UCMPD512,
28606 IX86_BUILTIN_UCMPQ512,
28607 IX86_BUILTIN_UNPCKHPD512,
28608 IX86_BUILTIN_UNPCKHPS512,
28609 IX86_BUILTIN_UNPCKLPD512,
28610 IX86_BUILTIN_UNPCKLPS512,
28611 IX86_BUILTIN_VCVTSD2SI32,
28612 IX86_BUILTIN_VCVTSD2SI64,
28613 IX86_BUILTIN_VCVTSD2USI32,
28614 IX86_BUILTIN_VCVTSD2USI64,
28615 IX86_BUILTIN_VCVTSS2SI32,
28616 IX86_BUILTIN_VCVTSS2SI64,
28617 IX86_BUILTIN_VCVTSS2USI32,
28618 IX86_BUILTIN_VCVTSS2USI64,
28619 IX86_BUILTIN_VCVTTSD2SI32,
28620 IX86_BUILTIN_VCVTTSD2SI64,
28621 IX86_BUILTIN_VCVTTSD2USI32,
28622 IX86_BUILTIN_VCVTTSD2USI64,
28623 IX86_BUILTIN_VCVTTSS2SI32,
28624 IX86_BUILTIN_VCVTTSS2SI64,
28625 IX86_BUILTIN_VCVTTSS2USI32,
28626 IX86_BUILTIN_VCVTTSS2USI64,
28627 IX86_BUILTIN_VFMADDPD512_MASK,
28628 IX86_BUILTIN_VFMADDPD512_MASK3,
28629 IX86_BUILTIN_VFMADDPD512_MASKZ,
28630 IX86_BUILTIN_VFMADDPS512_MASK,
28631 IX86_BUILTIN_VFMADDPS512_MASK3,
28632 IX86_BUILTIN_VFMADDPS512_MASKZ,
28633 IX86_BUILTIN_VFMADDSD3_ROUND,
28634 IX86_BUILTIN_VFMADDSS3_ROUND,
28635 IX86_BUILTIN_VFMADDSUBPD512_MASK,
28636 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
28637 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
28638 IX86_BUILTIN_VFMADDSUBPS512_MASK,
28639 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
28640 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
28641 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
28642 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
28643 IX86_BUILTIN_VFMSUBPD512_MASK3,
28644 IX86_BUILTIN_VFMSUBPS512_MASK3,
28645 IX86_BUILTIN_VFMSUBSD3_MASK3,
28646 IX86_BUILTIN_VFMSUBSS3_MASK3,
28647 IX86_BUILTIN_VFNMADDPD512_MASK,
28648 IX86_BUILTIN_VFNMADDPS512_MASK,
28649 IX86_BUILTIN_VFNMSUBPD512_MASK,
28650 IX86_BUILTIN_VFNMSUBPD512_MASK3,
28651 IX86_BUILTIN_VFNMSUBPS512_MASK,
28652 IX86_BUILTIN_VFNMSUBPS512_MASK3,
28653 IX86_BUILTIN_VPCLZCNTD512,
28654 IX86_BUILTIN_VPCLZCNTQ512,
28655 IX86_BUILTIN_VPCONFLICTD512,
28656 IX86_BUILTIN_VPCONFLICTQ512,
28657 IX86_BUILTIN_VPERMDF512,
28658 IX86_BUILTIN_VPERMDI512,
28659 IX86_BUILTIN_VPERMI2VARD512,
28660 IX86_BUILTIN_VPERMI2VARPD512,
28661 IX86_BUILTIN_VPERMI2VARPS512,
28662 IX86_BUILTIN_VPERMI2VARQ512,
28663 IX86_BUILTIN_VPERMILPD512,
28664 IX86_BUILTIN_VPERMILPS512,
28665 IX86_BUILTIN_VPERMILVARPD512,
28666 IX86_BUILTIN_VPERMILVARPS512,
28667 IX86_BUILTIN_VPERMT2VARD512,
28668 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
28669 IX86_BUILTIN_VPERMT2VARPD512,
28670 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
28671 IX86_BUILTIN_VPERMT2VARPS512,
28672 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
28673 IX86_BUILTIN_VPERMT2VARQ512,
28674 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
28675 IX86_BUILTIN_VPERMVARDF512,
28676 IX86_BUILTIN_VPERMVARDI512,
28677 IX86_BUILTIN_VPERMVARSF512,
28678 IX86_BUILTIN_VPERMVARSI512,
28679 IX86_BUILTIN_VTERNLOGD512_MASK,
28680 IX86_BUILTIN_VTERNLOGD512_MASKZ,
28681 IX86_BUILTIN_VTERNLOGQ512_MASK,
28682 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
28684 /* Mask arithmetic operations */
28685 IX86_BUILTIN_KAND16,
28686 IX86_BUILTIN_KANDN16,
28687 IX86_BUILTIN_KNOT16,
28688 IX86_BUILTIN_KOR16,
28689 IX86_BUILTIN_KORTESTC16,
28690 IX86_BUILTIN_KORTESTZ16,
28691 IX86_BUILTIN_KUNPCKBW,
28692 IX86_BUILTIN_KXNOR16,
28693 IX86_BUILTIN_KXOR16,
28694 IX86_BUILTIN_KMOV16,
28696 /* Alternate 4 and 8 element gather/scatter for the vectorizer
28697 where all operands are 32-byte or 64-byte wide respectively. */
28698 IX86_BUILTIN_GATHERALTSIV4DF,
28699 IX86_BUILTIN_GATHERALTDIV8SF,
28700 IX86_BUILTIN_GATHERALTSIV4DI,
28701 IX86_BUILTIN_GATHERALTDIV8SI,
28702 IX86_BUILTIN_GATHER3ALTDIV16SF,
28703 IX86_BUILTIN_GATHER3ALTDIV16SI,
28704 IX86_BUILTIN_GATHER3ALTSIV8DF,
28705 IX86_BUILTIN_GATHER3ALTSIV8DI,
28706 IX86_BUILTIN_GATHER3DIV16SF,
28707 IX86_BUILTIN_GATHER3DIV16SI,
28708 IX86_BUILTIN_GATHER3DIV8DF,
28709 IX86_BUILTIN_GATHER3DIV8DI,
28710 IX86_BUILTIN_GATHER3SIV16SF,
28711 IX86_BUILTIN_GATHER3SIV16SI,
28712 IX86_BUILTIN_GATHER3SIV8DF,
28713 IX86_BUILTIN_GATHER3SIV8DI,
28714 IX86_BUILTIN_SCATTERDIV16SF,
28715 IX86_BUILTIN_SCATTERDIV16SI,
28716 IX86_BUILTIN_SCATTERDIV8DF,
28717 IX86_BUILTIN_SCATTERDIV8DI,
28718 IX86_BUILTIN_SCATTERSIV16SF,
28719 IX86_BUILTIN_SCATTERSIV16SI,
28720 IX86_BUILTIN_SCATTERSIV8DF,
28721 IX86_BUILTIN_SCATTERSIV8DI,
28723 /* AVX512PF */
28724 IX86_BUILTIN_GATHERPFQPD,
28725 IX86_BUILTIN_GATHERPFDPS,
28726 IX86_BUILTIN_GATHERPFDPD,
28727 IX86_BUILTIN_GATHERPFQPS,
28728 IX86_BUILTIN_SCATTERPFDPD,
28729 IX86_BUILTIN_SCATTERPFDPS,
28730 IX86_BUILTIN_SCATTERPFQPD,
28731 IX86_BUILTIN_SCATTERPFQPS,
28733 /* AVX-512ER */
28734 IX86_BUILTIN_EXP2PD_MASK,
28735 IX86_BUILTIN_EXP2PS_MASK,
28736 IX86_BUILTIN_EXP2PS,
28737 IX86_BUILTIN_RCP28PD,
28738 IX86_BUILTIN_RCP28PS,
28739 IX86_BUILTIN_RCP28SD,
28740 IX86_BUILTIN_RCP28SS,
28741 IX86_BUILTIN_RSQRT28PD,
28742 IX86_BUILTIN_RSQRT28PS,
28743 IX86_BUILTIN_RSQRT28SD,
28744 IX86_BUILTIN_RSQRT28SS,
28746 /* SHA builtins. */
28747 IX86_BUILTIN_SHA1MSG1,
28748 IX86_BUILTIN_SHA1MSG2,
28749 IX86_BUILTIN_SHA1NEXTE,
28750 IX86_BUILTIN_SHA1RNDS4,
28751 IX86_BUILTIN_SHA256MSG1,
28752 IX86_BUILTIN_SHA256MSG2,
28753 IX86_BUILTIN_SHA256RNDS2,
28755 /* TFmode support builtins. */
28756 IX86_BUILTIN_INFQ,
28757 IX86_BUILTIN_HUGE_VALQ,
28758 IX86_BUILTIN_FABSQ,
28759 IX86_BUILTIN_COPYSIGNQ,
28761 /* Vectorizer support builtins. */
28762 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
28763 IX86_BUILTIN_CPYSGNPS,
28764 IX86_BUILTIN_CPYSGNPD,
28765 IX86_BUILTIN_CPYSGNPS256,
28766 IX86_BUILTIN_CPYSGNPS512,
28767 IX86_BUILTIN_CPYSGNPD256,
28768 IX86_BUILTIN_CPYSGNPD512,
28769 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
28770 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
28773 /* FMA4 instructions. */
28774 IX86_BUILTIN_VFMADDSS,
28775 IX86_BUILTIN_VFMADDSD,
28776 IX86_BUILTIN_VFMADDPS,
28777 IX86_BUILTIN_VFMADDPD,
28778 IX86_BUILTIN_VFMADDPS256,
28779 IX86_BUILTIN_VFMADDPD256,
28780 IX86_BUILTIN_VFMADDSUBPS,
28781 IX86_BUILTIN_VFMADDSUBPD,
28782 IX86_BUILTIN_VFMADDSUBPS256,
28783 IX86_BUILTIN_VFMADDSUBPD256,
28785 /* FMA3 instructions. */
28786 IX86_BUILTIN_VFMADDSS3,
28787 IX86_BUILTIN_VFMADDSD3,
28789 /* XOP instructions. */
28790 IX86_BUILTIN_VPCMOV,
28791 IX86_BUILTIN_VPCMOV_V2DI,
28792 IX86_BUILTIN_VPCMOV_V4SI,
28793 IX86_BUILTIN_VPCMOV_V8HI,
28794 IX86_BUILTIN_VPCMOV_V16QI,
28795 IX86_BUILTIN_VPCMOV_V4SF,
28796 IX86_BUILTIN_VPCMOV_V2DF,
28797 IX86_BUILTIN_VPCMOV256,
28798 IX86_BUILTIN_VPCMOV_V4DI256,
28799 IX86_BUILTIN_VPCMOV_V8SI256,
28800 IX86_BUILTIN_VPCMOV_V16HI256,
28801 IX86_BUILTIN_VPCMOV_V32QI256,
28802 IX86_BUILTIN_VPCMOV_V8SF256,
28803 IX86_BUILTIN_VPCMOV_V4DF256,
28805 IX86_BUILTIN_VPPERM,
28807 IX86_BUILTIN_VPMACSSWW,
28808 IX86_BUILTIN_VPMACSWW,
28809 IX86_BUILTIN_VPMACSSWD,
28810 IX86_BUILTIN_VPMACSWD,
28811 IX86_BUILTIN_VPMACSSDD,
28812 IX86_BUILTIN_VPMACSDD,
28813 IX86_BUILTIN_VPMACSSDQL,
28814 IX86_BUILTIN_VPMACSSDQH,
28815 IX86_BUILTIN_VPMACSDQL,
28816 IX86_BUILTIN_VPMACSDQH,
28817 IX86_BUILTIN_VPMADCSSWD,
28818 IX86_BUILTIN_VPMADCSWD,
28820 IX86_BUILTIN_VPHADDBW,
28821 IX86_BUILTIN_VPHADDBD,
28822 IX86_BUILTIN_VPHADDBQ,
28823 IX86_BUILTIN_VPHADDWD,
28824 IX86_BUILTIN_VPHADDWQ,
28825 IX86_BUILTIN_VPHADDDQ,
28826 IX86_BUILTIN_VPHADDUBW,
28827 IX86_BUILTIN_VPHADDUBD,
28828 IX86_BUILTIN_VPHADDUBQ,
28829 IX86_BUILTIN_VPHADDUWD,
28830 IX86_BUILTIN_VPHADDUWQ,
28831 IX86_BUILTIN_VPHADDUDQ,
28832 IX86_BUILTIN_VPHSUBBW,
28833 IX86_BUILTIN_VPHSUBWD,
28834 IX86_BUILTIN_VPHSUBDQ,
28836 IX86_BUILTIN_VPROTB,
28837 IX86_BUILTIN_VPROTW,
28838 IX86_BUILTIN_VPROTD,
28839 IX86_BUILTIN_VPROTQ,
28840 IX86_BUILTIN_VPROTB_IMM,
28841 IX86_BUILTIN_VPROTW_IMM,
28842 IX86_BUILTIN_VPROTD_IMM,
28843 IX86_BUILTIN_VPROTQ_IMM,
28845 IX86_BUILTIN_VPSHLB,
28846 IX86_BUILTIN_VPSHLW,
28847 IX86_BUILTIN_VPSHLD,
28848 IX86_BUILTIN_VPSHLQ,
28849 IX86_BUILTIN_VPSHAB,
28850 IX86_BUILTIN_VPSHAW,
28851 IX86_BUILTIN_VPSHAD,
28852 IX86_BUILTIN_VPSHAQ,
28854 IX86_BUILTIN_VFRCZSS,
28855 IX86_BUILTIN_VFRCZSD,
28856 IX86_BUILTIN_VFRCZPS,
28857 IX86_BUILTIN_VFRCZPD,
28858 IX86_BUILTIN_VFRCZPS256,
28859 IX86_BUILTIN_VFRCZPD256,
28861 IX86_BUILTIN_VPCOMEQUB,
28862 IX86_BUILTIN_VPCOMNEUB,
28863 IX86_BUILTIN_VPCOMLTUB,
28864 IX86_BUILTIN_VPCOMLEUB,
28865 IX86_BUILTIN_VPCOMGTUB,
28866 IX86_BUILTIN_VPCOMGEUB,
28867 IX86_BUILTIN_VPCOMFALSEUB,
28868 IX86_BUILTIN_VPCOMTRUEUB,
28870 IX86_BUILTIN_VPCOMEQUW,
28871 IX86_BUILTIN_VPCOMNEUW,
28872 IX86_BUILTIN_VPCOMLTUW,
28873 IX86_BUILTIN_VPCOMLEUW,
28874 IX86_BUILTIN_VPCOMGTUW,
28875 IX86_BUILTIN_VPCOMGEUW,
28876 IX86_BUILTIN_VPCOMFALSEUW,
28877 IX86_BUILTIN_VPCOMTRUEUW,
28879 IX86_BUILTIN_VPCOMEQUD,
28880 IX86_BUILTIN_VPCOMNEUD,
28881 IX86_BUILTIN_VPCOMLTUD,
28882 IX86_BUILTIN_VPCOMLEUD,
28883 IX86_BUILTIN_VPCOMGTUD,
28884 IX86_BUILTIN_VPCOMGEUD,
28885 IX86_BUILTIN_VPCOMFALSEUD,
28886 IX86_BUILTIN_VPCOMTRUEUD,
28888 IX86_BUILTIN_VPCOMEQUQ,
28889 IX86_BUILTIN_VPCOMNEUQ,
28890 IX86_BUILTIN_VPCOMLTUQ,
28891 IX86_BUILTIN_VPCOMLEUQ,
28892 IX86_BUILTIN_VPCOMGTUQ,
28893 IX86_BUILTIN_VPCOMGEUQ,
28894 IX86_BUILTIN_VPCOMFALSEUQ,
28895 IX86_BUILTIN_VPCOMTRUEUQ,
28897 IX86_BUILTIN_VPCOMEQB,
28898 IX86_BUILTIN_VPCOMNEB,
28899 IX86_BUILTIN_VPCOMLTB,
28900 IX86_BUILTIN_VPCOMLEB,
28901 IX86_BUILTIN_VPCOMGTB,
28902 IX86_BUILTIN_VPCOMGEB,
28903 IX86_BUILTIN_VPCOMFALSEB,
28904 IX86_BUILTIN_VPCOMTRUEB,
28906 IX86_BUILTIN_VPCOMEQW,
28907 IX86_BUILTIN_VPCOMNEW,
28908 IX86_BUILTIN_VPCOMLTW,
28909 IX86_BUILTIN_VPCOMLEW,
28910 IX86_BUILTIN_VPCOMGTW,
28911 IX86_BUILTIN_VPCOMGEW,
28912 IX86_BUILTIN_VPCOMFALSEW,
28913 IX86_BUILTIN_VPCOMTRUEW,
28915 IX86_BUILTIN_VPCOMEQD,
28916 IX86_BUILTIN_VPCOMNED,
28917 IX86_BUILTIN_VPCOMLTD,
28918 IX86_BUILTIN_VPCOMLED,
28919 IX86_BUILTIN_VPCOMGTD,
28920 IX86_BUILTIN_VPCOMGED,
28921 IX86_BUILTIN_VPCOMFALSED,
28922 IX86_BUILTIN_VPCOMTRUED,
28924 IX86_BUILTIN_VPCOMEQQ,
28925 IX86_BUILTIN_VPCOMNEQ,
28926 IX86_BUILTIN_VPCOMLTQ,
28927 IX86_BUILTIN_VPCOMLEQ,
28928 IX86_BUILTIN_VPCOMGTQ,
28929 IX86_BUILTIN_VPCOMGEQ,
28930 IX86_BUILTIN_VPCOMFALSEQ,
28931 IX86_BUILTIN_VPCOMTRUEQ,
28933 /* LWP instructions. */
28934 IX86_BUILTIN_LLWPCB,
28935 IX86_BUILTIN_SLWPCB,
28936 IX86_BUILTIN_LWPVAL32,
28937 IX86_BUILTIN_LWPVAL64,
28938 IX86_BUILTIN_LWPINS32,
28939 IX86_BUILTIN_LWPINS64,
28941 IX86_BUILTIN_CLZS,
28943 /* RTM */
28944 IX86_BUILTIN_XBEGIN,
28945 IX86_BUILTIN_XEND,
28946 IX86_BUILTIN_XABORT,
28947 IX86_BUILTIN_XTEST,
28949 /* MPX */
28950 IX86_BUILTIN_BNDMK,
28951 IX86_BUILTIN_BNDSTX,
28952 IX86_BUILTIN_BNDLDX,
28953 IX86_BUILTIN_BNDCL,
28954 IX86_BUILTIN_BNDCU,
28955 IX86_BUILTIN_BNDRET,
28956 IX86_BUILTIN_BNDNARROW,
28957 IX86_BUILTIN_BNDINT,
28958 IX86_BUILTIN_SIZEOF,
28959 IX86_BUILTIN_BNDLOWER,
28960 IX86_BUILTIN_BNDUPPER,
28962 /* BMI instructions. */
28963 IX86_BUILTIN_BEXTR32,
28964 IX86_BUILTIN_BEXTR64,
28965 IX86_BUILTIN_CTZS,
28967 /* TBM instructions. */
28968 IX86_BUILTIN_BEXTRI32,
28969 IX86_BUILTIN_BEXTRI64,
28971 /* BMI2 instructions. */
28972 IX86_BUILTIN_BZHI32,
28973 IX86_BUILTIN_BZHI64,
28974 IX86_BUILTIN_PDEP32,
28975 IX86_BUILTIN_PDEP64,
28976 IX86_BUILTIN_PEXT32,
28977 IX86_BUILTIN_PEXT64,
28979 /* ADX instructions. */
28980 IX86_BUILTIN_ADDCARRYX32,
28981 IX86_BUILTIN_ADDCARRYX64,
28983 /* FSGSBASE instructions. */
28984 IX86_BUILTIN_RDFSBASE32,
28985 IX86_BUILTIN_RDFSBASE64,
28986 IX86_BUILTIN_RDGSBASE32,
28987 IX86_BUILTIN_RDGSBASE64,
28988 IX86_BUILTIN_WRFSBASE32,
28989 IX86_BUILTIN_WRFSBASE64,
28990 IX86_BUILTIN_WRGSBASE32,
28991 IX86_BUILTIN_WRGSBASE64,
28993 /* RDRND instructions. */
28994 IX86_BUILTIN_RDRAND16_STEP,
28995 IX86_BUILTIN_RDRAND32_STEP,
28996 IX86_BUILTIN_RDRAND64_STEP,
28998 /* RDSEED instructions. */
28999 IX86_BUILTIN_RDSEED16_STEP,
29000 IX86_BUILTIN_RDSEED32_STEP,
29001 IX86_BUILTIN_RDSEED64_STEP,
29003 /* F16C instructions. */
29004 IX86_BUILTIN_CVTPH2PS,
29005 IX86_BUILTIN_CVTPH2PS256,
29006 IX86_BUILTIN_CVTPS2PH,
29007 IX86_BUILTIN_CVTPS2PH256,
29009 /* CFString built-in for darwin */
29010 IX86_BUILTIN_CFSTRING,
29012 /* Builtins to get CPU type and supported features. */
29013 IX86_BUILTIN_CPU_INIT,
29014 IX86_BUILTIN_CPU_IS,
29015 IX86_BUILTIN_CPU_SUPPORTS,
29017 /* Read/write FLAGS register built-ins. */
29018 IX86_BUILTIN_READ_FLAGS,
29019 IX86_BUILTIN_WRITE_FLAGS,
29021 IX86_BUILTIN_MAX
29022 };
29024 /* Table for the ix86 builtin decls. */
29027 /* Table of all of the builtin functions that are possible with different ISA's
29028 but are waiting to be built until a function is declared to use that
29029 ISA. */
29038 };
29043 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
29044 of which isa_flags to use in the ix86_builtins_isa array. Stores the
29045 function decl in the ix86_builtins array. Returns the function decl or
29046 NULL_TREE, if the builtin was not added.
29048 If the front end has a special hook for builtin functions, delay adding
29049 builtin functions that aren't in the current ISA until the ISA is changed
29050 with function specific optimization. Doing so, can save about 300K for the
29051 default compiler. When the builtin is expanded, check at that time whether
29052 it is valid.
29054 If the front end doesn't have a special hook, record all builtins, even if
29055 it isn't an instruction set in the current ISA in case the user uses
29056 function specific options for a different ISA, so that we don't get scope
29057 errors if a builtin is added in the middle of a function scope. */
29063 {
29067 {
29076 {
29082 }
29083 else
29084 {
29092 }
29093 }
29096 }
29098 /* Like def_builtin, but also marks the function decl "const". */
29103 {
29107 else
29111 }
29113 /* Add any new builtin functions for a given ISA that may not have been
29114 declared. This saves a bit of space compared to adding all of the
29115 declarations to the tree, even if we didn't use them. */
29117 static void
29119 {
29123 {
29126 {
29129 /* Don't define the builtin again. */
29135 NULL_TREE);
29142 NULL_TREE);
29145 }
29146 }
29147 }
29149 /* Bits for builtin_description.flag. */
29151 /* Set when we don't support the comparison natively, and should
29152 swap_comparison in order to support it. */
29153 #define BUILTIN_DESC_SWAP_OPERANDS 1
29155 struct builtin_description
29156 {
29163 };
29166 {
29167 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
29168 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
29169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
29170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
29171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
29172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
29173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
29174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
29175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
29176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
29177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
29178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
29179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
29180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
29181 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
29182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
29183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
29184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
29185 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
29186 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
29187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
29188 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
29189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
29190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
29191 };
29194 {
29195 /* SSE4.2 */
29196 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
29197 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
29198 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
29199 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
29200 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
29201 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
29202 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
29203 };
29206 {
29207 /* SSE4.2 */
29208 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
29209 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
29210 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
29211 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
29212 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
29213 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
29214 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
29215 };
29217 /* Special builtins with variable number of arguments. */
29219 {
29220 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
29221 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
29222 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
29224 /* 80387 (for use internally for atomic compound assignment). */
29225 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
29226 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
29227 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) VOID_FTYPE_PUSHORT },
29228 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
29230 /* MMX */
29231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29233 /* 3DNow! */
29234 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
29236 /* FXSR, XSAVE and XSAVEOPT */
29237 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
29238 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
29239 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29240 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29241 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29243 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29244 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
29245 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29246 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29247 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
29249 /* SSE */
29250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
29256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
29259 /* SSE or 3DNow!A */
29260 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29261 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
29263 /* SSE2 */
29264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
29266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
29268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
29270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
29271 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
29272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
29273 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29275 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
29278 /* SSE3 */
29279 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
29281 /* SSE4.1 */
29282 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
29284 /* SSE4A */
29285 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
29286 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
29288 /* AVX */
29289 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
29290 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
29292 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
29293 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29294 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29295 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
29296 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
29298 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
29299 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
29300 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29301 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29302 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29303 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
29304 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
29306 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
29307 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
29308 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
29310 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
29311 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
29312 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
29313 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
29314 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
29315 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
29316 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
29317 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
29319 /* AVX2 */
29320 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
29321 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
29322 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
29323 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
29324 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
29325 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
29326 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
29327 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
29328 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
29330 /* AVX512F */
29331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
29348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
29349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
29350 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
29351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
29352 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
29353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
29354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
29355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
29361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
29364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
29367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
29370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
29373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
29375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
29376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
29377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
29379 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
29380 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
29381 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
29382 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
29383 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
29384 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
29386 /* FSGSBASE */
29387 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29388 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29389 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29390 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
29391 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29392 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29393 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
29394 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
29396 /* RTM */
29397 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
29398 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
29399 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
29400 };
29402 /* Builtins with variable number of arguments. */
29404 {
29405 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
29406 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
29407 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
29408 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29409 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29410 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
29411 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
29413 /* MMX */
29414 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29415 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29416 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29417 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29418 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29419 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29421 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29422 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29423 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29424 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29425 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29426 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29427 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29428 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29430 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29431 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29433 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29434 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29435 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29436 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29438 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29439 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29440 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29441 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29442 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29443 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29445 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29446 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29447 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29448 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29449 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
29450 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
29452 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29453 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
29454 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
29456 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
29458 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29459 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29460 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29461 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29462 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29463 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29465 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29466 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29467 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
29468 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29469 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29470 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
29472 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
29473 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
29474 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
29475 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
29477 /* 3DNow! */
29478 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29479 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29480 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29481 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29483 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29484 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29485 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29486 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29487 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29488 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
29489 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29490 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29491 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29492 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29493 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29494 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29495 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29496 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29497 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29499 /* 3DNow!A */
29500 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
29501 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
29502 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29503 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
29504 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29505 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
29507 /* SSE */
29508 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
29509 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29510 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29511 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29512 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29513 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29514 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29515 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29516 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29517 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
29518 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
29519 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
29521 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29523 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29524 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29525 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29526 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29527 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29528 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29529 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29530 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29532 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29533 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29534 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29535 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29536 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29537 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29538 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29539 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29540 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29541 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
29542 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
29543 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29544 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
29545 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
29546 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
29547 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29548 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
29549 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
29550 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
29551 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
29553 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29554 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29555 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29558 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29559 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29560 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29561 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29563 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29565 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29566 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29567 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29568 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29569 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29571 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
29572 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
29573 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
29575 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
29577 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29578 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29579 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
29581 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
29582 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
29584 /* SSE MMX or 3Dnow!A */
29585 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29586 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29587 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29589 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29590 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29591 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29592 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29594 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
29595 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
29597 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
29599 /* SSE2 */
29600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29602 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
29603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
29604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29605 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
29606 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
29608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29610 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
29611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
29612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
29614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
29616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
29618 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29619 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
29621 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29622 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
29623 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29625 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29626 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29627 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29628 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29629 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29630 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29631 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29632 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29634 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29635 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29636 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29637 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29638 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
29639 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29640 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29641 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29642 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29643 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29644 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
29645 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29646 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
29647 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
29648 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
29649 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29650 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
29651 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
29652 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
29653 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
29655 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29656 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29657 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29658 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29660 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29661 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29662 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29663 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29665 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29667 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29668 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29669 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29671 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29673 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29674 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29675 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29676 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29677 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29678 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29679 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29680 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29682 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29683 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29684 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29685 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29686 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29687 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29688 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29689 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29691 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29692 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
29694 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29696 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29697 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29700 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29706 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29709 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29710 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29711 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29712 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29714 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29715 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29716 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29717 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29718 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29719 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29720 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29721 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
29727 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
29730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
29731 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
29735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
29736 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
29737 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
29738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
29740 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29741 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29742 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29743 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29744 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29745 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29746 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
29749 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29750 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29751 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
29752 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29753 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29754 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
29756 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
29757 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
29758 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
29759 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
29761 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
29762 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29763 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
29765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
29767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29769 /* SSE2 MMX */
29770 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29771 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
29773 /* SSE3 */
29774 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
29775 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29777 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29778 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29779 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29780 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29781 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
29782 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
29784 /* SSSE3 */
29785 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
29786 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
29787 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29788 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
29789 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
29790 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
29792 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29793 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29794 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29795 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29796 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29797 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29798 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29799 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29800 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29801 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29802 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29803 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29804 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
29805 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
29806 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29807 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29808 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29809 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29810 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29811 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
29812 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29813 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
29814 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29815 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
29817 /* SSSE3. */
29818 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
29819 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
29821 /* SSE4.1 */
29822 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29823 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29824 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
29825 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
29826 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29827 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29828 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29829 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
29830 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
29831 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
29833 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29834 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29835 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29836 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29837 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29838 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29839 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
29840 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
29841 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
29842 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
29843 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
29844 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
29845 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
29847 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
29848 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29849 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29850 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29851 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29852 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29853 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
29854 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29855 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29856 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
29857 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
29858 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
29860 /* SSE4.1 */
29861 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29862 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29863 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29864 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29866 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
29867 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
29868 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
29869 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
29871 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29872 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
29874 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
29875 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
29877 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
29878 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
29879 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
29880 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
29882 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
29883 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
29885 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
29886 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
29888 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29889 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29890 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
29892 /* SSE4.2 */
29893 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29894 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
29895 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
29896 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
29897 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
29899 /* SSE4A */
29900 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
29901 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
29902 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
29903 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29905 /* AES */
29906 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
29907 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
29909 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29910 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29911 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29912 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
29914 /* PCLMUL */
29915 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
29917 /* AVX */
29918 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29919 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29920 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29922 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29923 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29924 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29925 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29926 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29927 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29928 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29929 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29930 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29931 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29932 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29933 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29934 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29935 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29936 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29937 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29938 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29939 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29940 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29941 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29942 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
29943 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
29945 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
29946 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
29947 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
29948 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
29950 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29951 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29952 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
29953 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
29954 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29955 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29956 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29957 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29958 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29959 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
29960 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
29961 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29962 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29963 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
29964 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
29965 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
29966 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
29967 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
29968 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
29969 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29970 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
29971 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29972 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
29973 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
29974 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
29975 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
29976 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
29977 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
29978 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
29979 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29980 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
29981 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
29982 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
29983 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
29985 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29986 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29987 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29989 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
29990 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29991 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29992 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29993 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29995 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
29997 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
29998 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
30000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
30001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
30002 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
30003 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
30005 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
30006 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
30008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
30009 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
30011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
30012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
30013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
30014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
30016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
30017 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
30019 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
30020 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
30022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30023 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30025 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
30028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
30029 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
30030 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
30031 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
30032 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
30034 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
30037 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30038 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
30040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
30043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
30046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
30050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
30051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
30053 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
30054 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
30056 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
30058 /* AVX2 */
30059 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
30060 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
30061 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
30062 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
30063 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
30064 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
30065 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
30066 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
30067 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30068 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30069 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30070 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30071 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30072 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30073 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30074 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30075 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
30076 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30077 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30078 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30079 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30080 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
30081 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
30082 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30083 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30084 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30085 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30086 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30087 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30088 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30089 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30090 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30091 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30092 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30093 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30094 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30095 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30096 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
30097 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
30098 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30099 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30100 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30101 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30102 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30103 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30104 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30105 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30106 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30107 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30108 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30109 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30110 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
30111 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
30112 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
30113 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
30114 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
30115 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
30116 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
30117 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
30118 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
30119 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
30120 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
30121 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
30122 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
30123 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
30124 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30125 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30126 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30127 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30128 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30129 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
30130 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30131 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
30132 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30133 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
30134 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
30135 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
30136 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30137 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30138 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30139 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
30140 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30141 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30142 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30143 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30144 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
30145 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
30146 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30147 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30148 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30149 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30150 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
30151 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
30152 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
30153 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
30154 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
30155 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
30156 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
30157 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30158 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30159 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30160 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30161 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30162 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30163 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30164 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30165 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30166 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30167 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30168 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30169 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
30170 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
30171 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30172 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30173 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30174 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
30175 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
30176 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
30177 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
30178 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30179 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
30180 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
30181 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
30182 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
30183 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
30184 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
30185 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
30186 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
30187 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
30188 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30189 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
30190 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
30191 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
30192 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
30193 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
30194 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
30195 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30196 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30197 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30198 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30199 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30200 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30201 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
30202 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
30203 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
30204 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30206 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30208 /* BMI */
30209 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30210 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30211 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
30213 /* TBM */
30214 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30215 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30217 /* F16C */
30218 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
30219 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
30220 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
30221 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
30223 /* BMI2 */
30224 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30225 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30226 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30227 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30228 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
30229 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
30231 /* AVX512F */
30232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
30240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
30242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
30243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
30244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
30250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
30251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
30252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
30257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
30258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
30259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
30260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
30261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
30262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
30263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
30264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
30280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
30281 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
30282 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
30283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
30284 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30285 { OPTION_MASK_ISA_AVX512F & ~OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vec_dup_memv8di_mask, "__builtin_ia32_pbroadcastq512_mem_mask", IX86_BUILTIN_PBROADCASTQ512_MEM, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
30286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
30320 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
30321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
30322 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
30323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
30324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
30325 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
30326 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
30327 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
30328 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
30329 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30330 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30331 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
30332 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30333 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30334 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30335 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30336 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30337 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30338 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30339 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30340 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30341 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30342 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30343 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30344 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30345 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30346 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30347 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30348 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30349 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30350 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30351 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30352 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30353 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30354 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30355 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
30356 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
30357 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
30358 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30359 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30360 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30361 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30362 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30363 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30364 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30365 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
30366 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
30367 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30368 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30369 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30370 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30371 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30372 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30373 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30374 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30375 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30376 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30377 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
30378 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
30379 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
30380 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
30381 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30382 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30383 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
30384 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
30385 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
30386 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
30387 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
30388 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
30389 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30390 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30391 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
30392 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
30393 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30394 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30395 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
30396 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
30397 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30398 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
30399 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30400 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30401 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30402 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30403 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
30404 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
30405 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30406 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30407 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30408 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30409 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30410 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
30411 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30412 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
30413 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30414 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30415 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
30416 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
30417 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
30418 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
30419 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30420 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
30421 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30422 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
30424 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
30425 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
30426 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
30427 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30428 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
30429 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
30430 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30431 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
30433 /* Mask arithmetic operations */
30434 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30435 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30436 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
30437 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30438 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30439 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30440 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
30441 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30442 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
30443 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
30445 /* SHA */
30446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30449 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
30450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30451 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
30452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
30453 };
30455 /* Builtins with rounding support. */
30457 {
30458 /* AVX512F */
30459 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30460 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30461 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30462 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30463 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
30464 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
30465 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
30466 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
30467 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
30468 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
30469 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30470 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30471 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
30472 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30473 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
30474 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30475 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
30476 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30477 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
30478 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
30479 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
30480 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
30481 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
30482 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30483 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
30484 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30485 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
30486 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
30487 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
30488 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
30489 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
30490 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30491 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30492 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30493 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30494 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30495 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
30496 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30497 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
30498 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30499 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
30500 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30501 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
30502 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30503 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30504 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30505 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30506 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30507 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30508 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30509 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30510 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30511 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30512 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30513 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30514 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30515 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30516 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30517 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30518 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30519 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30520 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30521 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30522 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
30523 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
30524 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
30525 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
30526 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30527 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30528 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30529 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30530 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30531 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30532 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30533 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30534 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30535 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30536 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30537 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30538 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30539 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30540 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30541 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30542 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30543 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30544 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30545 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30546 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
30547 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
30548 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
30549 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
30550 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
30551 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
30552 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
30553 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
30554 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30555 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30556 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30557 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30558 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30559 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30560 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
30561 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
30562 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30563 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30564 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30565 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30566 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30567 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30568 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30569 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30570 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30571 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30572 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30573 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30574 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30575 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
30576 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30577 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
30579 /* AVX512ER */
30580 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30581 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30582 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30583 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30584 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30585 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30586 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
30587 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
30588 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
30589 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
30590 };
30592 /* Bultins for MPX. */
30594 {
30595 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
30596 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
30597 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
30598 };
30600 /* Const builtins for MPX. */
30602 {
30603 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
30604 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
30605 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
30606 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
30607 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
30608 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
30609 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
30610 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
30611 };
30613 /* FMA4 and XOP. */
30614 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
30615 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
30616 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
30617 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
30618 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
30619 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
30620 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
30621 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
30622 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
30623 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
30624 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
30625 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
30626 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
30627 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
30628 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
30629 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
30630 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
30631 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
30632 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
30633 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
30634 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
30635 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
30636 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
30637 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
30638 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
30639 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
30640 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
30641 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
30642 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
30643 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
30644 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
30645 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
30646 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
30647 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
30648 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
30649 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
30650 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
30651 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
30652 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
30653 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
30654 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
30655 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
30656 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
30657 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
30658 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
30659 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
30660 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
30661 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
30662 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
30663 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
30664 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
30665 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
30668 {
30709 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
30710 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
30711 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
30712 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
30713 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
30714 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
30715 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
30717 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30718 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
30719 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
30720 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
30721 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
30722 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
30723 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
30725 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
30727 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30728 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
30729 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30730 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30731 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30732 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
30733 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30734 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30735 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30736 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
30737 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30738 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
30740 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30741 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
30742 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
30743 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
30744 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
30745 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
30746 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
30747 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
30748 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30749 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
30750 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
30751 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
30752 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
30753 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
30754 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
30755 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
30757 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
30758 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
30759 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
30760 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
30761 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
30762 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
30764 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30765 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30766 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30767 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30768 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30769 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30770 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30771 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
30772 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
30773 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30774 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
30775 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30776 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
30777 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
30778 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
30780 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
30781 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30782 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
30783 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
30784 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
30785 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
30786 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
30788 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
30789 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30790 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
30791 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
30792 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
30793 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
30794 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
30796 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
30797 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30798 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
30799 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
30800 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
30801 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
30802 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
30804 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30805 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30806 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
30807 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
30808 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
30809 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
30810 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
30812 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
30813 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30814 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
30815 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
30816 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
30817 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
30818 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
30820 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
30821 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30822 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
30823 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
30824 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
30825 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
30826 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
30828 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
30829 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30830 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
30831 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
30832 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
30833 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
30834 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
30836 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
30837 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30838 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
30839 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
30840 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
30841 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
30842 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
30844 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30845 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30846 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30847 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30848 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
30849 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
30850 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
30851 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
30853 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30854 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30855 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30856 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30857 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
30858 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
30859 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
30860 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
30862 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
30863 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
30864 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
30865 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
30867 };
30868 \f
30869 /* TM vector builtins. */
30871 /* Reuse the existing x86-specific `struct builtin_description' cause
30872 we're lazy. Add casts to make them fit. */
30874 {
30875 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30876 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30877 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
30878 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30879 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30880 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30881 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
30883 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30884 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30885 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
30886 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30887 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30888 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30889 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
30891 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30892 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30893 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
30894 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30895 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30896 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30897 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
30899 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
30900 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
30901 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
30902 };
30904 /* TM callbacks. */
30906 /* Return the builtin decl needed to load a vector of TYPE. */
30908 static tree
30910 {
30912 {
30914 {
30921 }
30922 }
30924 }
30926 /* Return the builtin decl needed to store a vector of TYPE. */
30928 static tree
30930 {
30932 {
30934 {
30941 }
30942 }
30944 }
30945 \f
30946 /* Initialize the transactional memory vector load/store builtins. */
30948 static void
30950 {
30954 tree decl;
30961 /* If there are no builtins defined, we must be compiling in a
30962 language without trans-mem support. */
30966 /* Use whatever attributes a normal TM load has. */
30970 /* Use whatever attributes a normal TM store has. */
30974 /* Use whatever attributes a normal TM log has. */
30982 {
30986 {
30994 {
30997 }
30999 {
31002 }
31003 else
31004 {
31007 }
31009 /* The builtin without the prefix for
31010 calling it directly. */
31012 attrs);
31013 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
31014 set the TYPE_ATTRIBUTES. */
31018 }
31019 }
31020 }
31022 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
31023 in the current target ISA to allow the user to compile particular modules
31024 with different target specific options that differ from the command line
31025 options. */
31026 static void
31028 {
31033 /* Add all special builtins with variable number of operands. */
31037 {
31043 }
31045 /* Add all builtins with variable number of operands. */
31049 {
31055 }
31057 /* Add all builtins with rounding. */
31061 {
31067 }
31069 /* pcmpestr[im] insns. */
31073 {
31076 else
31079 }
31081 /* pcmpistr[im] insns. */
31085 {
31088 else
31091 }
31093 /* comi/ucomi insns. */
31095 {
31098 else
31101 }
31103 /* SSE */
31109 /* SSE or 3DNow!A */
31112 IX86_BUILTIN_MASKMOVQ);
31114 /* SSE2 */
31123 /* SSE3. */
31129 /* AES */
31143 /* PCLMUL */
31147 /* RDRND */
31154 IX86_BUILTIN_RDRAND64_STEP);
31156 /* AVX2 */
31158 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
31159 IX86_BUILTIN_GATHERSIV2DF);
31162 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
31163 IX86_BUILTIN_GATHERSIV4DF);
31166 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
31167 IX86_BUILTIN_GATHERDIV2DF);
31170 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
31171 IX86_BUILTIN_GATHERDIV4DF);
31174 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
31175 IX86_BUILTIN_GATHERSIV4SF);
31178 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
31179 IX86_BUILTIN_GATHERSIV8SF);
31182 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
31183 IX86_BUILTIN_GATHERDIV4SF);
31186 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
31187 IX86_BUILTIN_GATHERDIV8SF);
31190 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
31191 IX86_BUILTIN_GATHERSIV2DI);
31194 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
31195 IX86_BUILTIN_GATHERSIV4DI);
31198 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
31199 IX86_BUILTIN_GATHERDIV2DI);
31202 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
31203 IX86_BUILTIN_GATHERDIV4DI);
31206 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
31207 IX86_BUILTIN_GATHERSIV4SI);
31210 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
31211 IX86_BUILTIN_GATHERSIV8SI);
31214 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
31215 IX86_BUILTIN_GATHERDIV4SI);
31218 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
31219 IX86_BUILTIN_GATHERDIV8SI);
31222 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
31223 IX86_BUILTIN_GATHERALTSIV4DF);
31226 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
31227 IX86_BUILTIN_GATHERALTDIV8SF);
31230 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
31231 IX86_BUILTIN_GATHERALTSIV4DI);
31234 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
31235 IX86_BUILTIN_GATHERALTDIV8SI);
31237 /* AVX512F */
31239 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
31240 IX86_BUILTIN_GATHER3SIV16SF);
31243 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
31244 IX86_BUILTIN_GATHER3SIV8DF);
31247 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
31248 IX86_BUILTIN_GATHER3DIV16SF);
31251 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
31252 IX86_BUILTIN_GATHER3DIV8DF);
31255 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
31256 IX86_BUILTIN_GATHER3SIV16SI);
31259 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
31260 IX86_BUILTIN_GATHER3SIV8DI);
31263 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
31264 IX86_BUILTIN_GATHER3DIV16SI);
31267 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
31268 IX86_BUILTIN_GATHER3DIV8DI);
31271 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
31272 IX86_BUILTIN_GATHER3ALTSIV8DF);
31275 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
31276 IX86_BUILTIN_GATHER3ALTDIV16SF);
31279 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
31280 IX86_BUILTIN_GATHER3ALTSIV8DI);
31283 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
31284 IX86_BUILTIN_GATHER3ALTDIV16SI);
31287 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
31288 IX86_BUILTIN_SCATTERSIV16SF);
31291 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
31292 IX86_BUILTIN_SCATTERSIV8DF);
31295 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
31296 IX86_BUILTIN_SCATTERDIV16SF);
31299 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
31300 IX86_BUILTIN_SCATTERDIV8DF);
31303 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
31304 IX86_BUILTIN_SCATTERSIV16SI);
31307 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
31308 IX86_BUILTIN_SCATTERSIV8DI);
31311 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
31312 IX86_BUILTIN_SCATTERDIV16SI);
31315 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
31316 IX86_BUILTIN_SCATTERDIV8DI);
31318 /* AVX512PF */
31320 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31321 IX86_BUILTIN_GATHERPFDPD);
31323 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31324 IX86_BUILTIN_GATHERPFDPS);
31326 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31327 IX86_BUILTIN_GATHERPFQPD);
31329 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31330 IX86_BUILTIN_GATHERPFQPS);
31332 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
31333 IX86_BUILTIN_SCATTERPFDPD);
31335 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
31336 IX86_BUILTIN_SCATTERPFDPS);
31338 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
31339 IX86_BUILTIN_SCATTERPFQPD);
31341 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
31342 IX86_BUILTIN_SCATTERPFQPS);
31344 /* SHA */
31360 /* RTM. */
31364 /* MMX access to the vec_init patterns. */
31369 V4HI_FTYPE_HI_HI_HI_HI,
31370 IX86_BUILTIN_VEC_INIT_V4HI);
31373 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
31374 IX86_BUILTIN_VEC_INIT_V8QI);
31376 /* Access to the vec_extract patterns. */
31398 /* Access to the vec_set patterns. */
31419 /* RDSEED */
31428 /* ADCX */
31433 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
31434 IX86_BUILTIN_ADDCARRYX64);
31436 /* Read/write FLAGS. */
31447 /* Add FMA4 multi-arg argument instructions */
31449 {
31455 }
31456 }
31458 static void
31460 {
31463 tree decl;
31469 {
31476 /* With no leaf and nothrow flags for MPX builtins
31477 abnormal edges may follow its call when setjmp
31478 presents in the function. Since we may have a lot
31479 of MPX builtins calls it causes lots of useless
31480 edges and enormous PHI nodes. To avoid this we mark
31481 MPX builtins as leaf and nothrow. */
31483 {
31485 NULL_TREE);
31487 }
31488 else
31489 {
31492 }
31493 }
31498 {
31506 {
31508 NULL_TREE);
31510 }
31511 else
31512 {
31515 }
31516 }
31517 }
31519 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
31520 to return a pointer to VERSION_DECL if the outcome of the expression
31521 formed by PREDICATE_CHAIN is true. This function will be called during
31522 version dispatch to decide which function version to execute. It returns
31523 the basic block at the end, to which more conditions can be added. */
31525 static basic_block
31528 {
31529 gimple return_stmt;
31531 gimple convert_stmt;
31532 gimple call_cond_stmt;
31533 gimple if_else_stmt;
31539 gimple_seq gseq;
31556 {
31564 }
31567 {
31582 else
31583 {
31584 gimple assign_stmt;
31585 /* Use MIN_EXPR to check if any integer is zero?.
31586 and_expr_var = min_expr <cond_var, and_expr_var> */
31594 }
31595 }
31598 integer_zero_node,
31628 }
31630 /* This parses the attribute arguments to target in DECL and determines
31631 the right builtin to use to match the platform specification.
31632 It returns the priority value for this version decl. If PREDICATE_LIST
31633 is not NULL, it stores the list of cpu features that need to be checked
31634 before dispatching this function. */
31636 static unsigned int
31638 {
31639 tree attrs;
31641 tree target_node;
31648 /* Priority of i386 features, greater value is higher priority. This is
31649 used to decide the order in which function dispatch must happen. For
31650 instance, a version specialized for SSE4.2 should be checked for dispatch
31651 before a version for SSE3, as SSE4.2 implies SSE3. */
31652 enum feature_priority
31653 {
31655 P_MMX,
31656 P_SSE,
31657 P_SSE2,
31658 P_SSE3,
31659 P_SSSE3,
31660 P_PROC_SSSE3,
31661 P_SSE4_A,
31662 P_PROC_SSE4_A,
31663 P_SSE4_1,
31664 P_SSE4_2,
31665 P_PROC_SSE4_2,
31666 P_POPCNT,
31667 P_AVX,
31668 P_PROC_AVX,
31669 P_FMA4,
31670 P_XOP,
31671 P_PROC_XOP,
31672 P_FMA,
31673 P_PROC_FMA,
31674 P_AVX2,
31675 P_PROC_AVX2
31676 };
31680 /* These are the target attribute strings for which a dispatcher is
31681 available, from fold_builtin_cpu. */
31683 static struct _feature_list
31684 {
31687 }
31689 {
31704 };
31707 static unsigned int NUM_FEATURES
31723 /* Return priority zero for default function. */
31727 /* Handle arch= if specified. For priority, set it to be 1 more than
31728 the best instruction set the processor can handle. For instance, if
31729 there is a version for atom and a version for ssse3 (the highest ISA
31730 priority for atom), the atom version must be checked for dispatch
31731 before the ssse3 version. */
31733 {
31743 {
31745 {
31753 else
31754 /* We translate "arch=corei7" and "arch=nehalem" to
31755 "corei7" so that it will be mapped to M_INTEL_COREI7
31756 as cpu type to cover all M_INTEL_COREI7_XXXs. */
31763 else
31770 else
31810 }
31811 }
31816 {
31820 }
31823 {
31825 /* For a C string literal the length includes the trailing NULL. */
31828 predicate_chain);
31829 }
31830 }
31832 /* Process feature name. */
31839 {
31840 /* Do not process "arch=" */
31842 {
31845 }
31847 {
31849 {
31851 {
31856 predicate_chain);
31857 }
31858 /* Find the maximum priority feature. */
31863 }
31864 }
31866 {
31870 }
31872 }
31876 {
31879 attrs_str);
31881 }
31883 {
31886 }
31889 }
31891 /* This compares the priority of target features in function DECL1
31892 and DECL2. It returns positive value if DECL1 is higher priority,
31893 negative value if DECL2 is higher priority and 0 if they are the
31894 same. */
31896 static int
31898 {
31903 }
31905 /* V1 and V2 point to function versions with different priorities
31906 based on the target ISA. This function compares their priorities. */
31908 static int
31910 {
31912 {
31913 tree version_decl;
31914 tree predicate_chain;
31921 }
31923 /* This function generates the dispatch function for
31924 multi-versioned functions. DISPATCH_DECL is the function which will
31925 contain the dispatch logic. FNDECLS are the function choices for
31926 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
31927 in DISPATCH_DECL in which the dispatch code is generated. */
31929 static int
31933 {
31934 tree default_decl;
31935 gimple ifunc_cpu_init_stmt;
31936 gimple_seq gseq;
31938 tree ele;
31944 struct _function_version_info
31945 {
31946 tree version_decl;
31947 tree predicate_chain;
31955 /*fndecls_p is actually a vector. */
31958 /* At least one more version other than the default. */
31965 /* The first version in the vector is the default decl. */
31971 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
31972 constructors, so explicity call __builtin_cpu_init here. */
31983 {
31987 /* Get attribute string, parse it and find the right predicate decl.
31988 The predicate function could be a lengthy combination of many
31989 features, like arch-type and various isa-variants. */
32000 actual_versions++;
32001 }
32003 /* Sort the versions according to descending order of dispatch priority. The
32004 priority is based on the ISA. This is not a perfect solution. There
32005 could still be ambiguity. If more than one function version is suitable
32006 to execute, which one should be dispatched? In future, allow the user
32007 to specify a dispatch priority next to the version. */
32017 /* dispatch default version at the end. */
32023 }
32025 /* Comparator function to be used in qsort routine to sort attribute
32026 specification strings to "target". */
32028 static int
32030 {
32034 }
32036 /* ARGLIST is the argument to target attribute. This function tokenizes
32037 the comma separated arguments, sorts them and returns a string which
32038 is a unique identifier for the comma separated arguments. It also
32039 replaces non-identifier characters "=,-" with "_". */
32043 {
32044 tree arg;
32053 {
32058 argnum++;
32061 argnum++;
32062 }
32067 {
32073 }
32075 /* Replace "=,-" with "_". */
32088 {
32090 i++;
32092 }
32099 {
32104 }
32109 }
32111 /* This function changes the assembler name for functions that are
32112 versions. If DECL is a function version and has a "target"
32113 attribute, it appends the attribute string to its assembler name. */
32115 static tree
32117 {
32118 tree version_attr;
32126 "Function versions cannot be marked as gnu_inline,"
32135 /* target attribute string cannot be NULL. */
32139 version_string
32150 /* Allow assembler name to be modified if already set. */
32158 }
32160 /* This function returns true if FN1 and FN2 are versions of the same function,
32161 that is, the target strings of the function decls are different. This assumes
32162 that FN1 and FN2 have the same signature. */
32164 static bool
32166 {
32178 /* At least one function decl should have the target attribute specified. */
32182 /* Diagnose missing target attribute if one of the decls is already
32183 multi-versioned. */
32185 {
32187 {
32189 {
32194 }
32197 fn2);
32200 /* Prevent diagnosing of the same error multiple times. */
32205 }
32207 }
32212 /* The sorted target strings must be different for fn1 and fn2
32213 to be versions. */
32216 else
32223 }
32225 static tree
32227 {
32228 /* For function version, add the target suffix to the assembler name. */
32232 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
32234 #endif
32237 }
32239 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
32240 is true, append the full path name of the source file. */
32244 {
32252 /* Get a unique name that can be used globally without any chances
32253 of collision at link time. */
32263 /* Use '.' to concatenate names as it is demangler friendly. */
32266 suffix);
32267 else
32271 }
32273 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32275 /* Make a dispatcher declaration for the multi-versioned function DECL.
32276 Calls to DECL function will be replaced with calls to the dispatcher
32277 by the front-end. Return the decl created. */
32279 static tree
32281 {
32282 tree func_decl;
32302 /* Mark this func as external, the resolver will flip it again if
32303 it gets generated. */
32305 /* This will be of type IFUNCs have to be externally visible. */
32309 }
32311 #endif
32313 /* Returns true if decl is multi-versioned and DECL is the default function,
32314 that is it is not tagged with target specific optimization. */
32316 static bool
32318 {
32327 }
32329 /* Make a dispatcher declaration for the multi-versioned function DECL.
32330 Calls to DECL function will be replaced with calls to the dispatcher
32331 by the front-end. Returns the decl of the dispatcher function. */
32333 static tree
32335 {
32357 /* Find the default version and make it the first node. */
32359 /* Go to the beginning of the chain. */
32364 {
32369 }
32371 /* If there is no default node, just return NULL. */
32375 /* Make default info the first node. */
32377 {
32384 }
32388 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
32390 {
32395 /* Right now, the dispatching is done via ifunc. */
32401 dispatcher_version_info
32406 /* Set the dispatcher for all the versions. */
32409 {
32412 }
32413 }
32414 else
32415 #endif
32416 {
32418 "multiversioning needs ifunc which is not supported "
32420 }
32423 }
32425 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
32426 it to CHAIN. */
32428 static tree
32430 {
32431 tree attr_name;
32432 tree attr_arg_name;
32433 tree attr_args;
32434 tree attr;
32441 }
32443 /* Make the resolver function decl to dispatch the versions of
32444 a multi-versioned function, DEFAULT_DECL. Create an
32445 empty basic block in the resolver and store the pointer in
32446 EMPTY_BB. Return the decl of the resolver function. */
32448 static tree
32452 {
32457 /* IFUNC's have to be globally visible. So, if the default_decl is
32458 not, then the name of the IFUNC should be made unique. */
32462 /* Append the filename to the resolver function if the versions are
32463 not externally visible. This is because the resolver function has
32464 to be externally visible for the loader to find it. So, appending
32465 the filename will prevent conflicts with a resolver function from
32466 another module which is based on the same version name. */
32469 /* The resolver function should return a (void *). */
32480 /* IFUNC resolvers have to be externally visible. */
32484 /* Resolver is not external, body is generated. */
32494 {
32495 /* In this case, each translation unit with a call to this
32496 versioned function will put out a resolver. Ensure it
32497 is comdat to keep just one copy. */
32500 }
32501 /* Build result decl and add to function_decl. */
32517 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
32521 /* Create the alias for dispatch to resolver here. */
32522 /*cgraph_create_function_alias (dispatch_decl, decl);*/
32526 }
32528 /* Generate the dispatching code body to dispatch multi-versioned function
32529 DECL. The target hook is called to process the "target" attributes and
32530 provide the code to dispatch the right function at run-time. NODE points
32531 to the dispatcher decl whose body will be created. */
32533 static tree
32535 {
32536 tree resolver_decl;
32537 basic_block empty_bb;
32538 tree default_ver_decl;
32554 /* The first version in the chain corresponds to the default version. */
32557 /* node is going to be an alias, so remove the finalized bit. */
32571 {
32573 /* Check for virtual functions here again, as by this time it should
32574 have been determined if this function needs a vtable index or
32575 not. This happens for methods in derived classes that override
32576 virtual methods in base classes but are not explicitly marked as
32577 virtual. */
32582 }
32588 }
32589 /* This builds the processor_model struct type defined in
32590 libgcc/config/i386/cpuinfo.c */
32592 static tree
32594 {
32601 /* The first 3 fields are unsigned int. */
32603 {
32609 }
32611 /* The last field is an array of unsigned integers of size one. */
32622 }
32624 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
32626 static tree
32628 {
32629 tree new_decl;
32632 VAR_DECL,
32634 type);
32647 }
32649 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
32650 into an integer defined in libgcc/config/i386/cpuinfo.c */
32652 static tree
32654 {
32660 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
32661 enum processor_features
32662 {
32664 F_MMX,
32665 F_POPCNT,
32666 F_SSE,
32667 F_SSE2,
32668 F_SSE3,
32669 F_SSSE3,
32670 F_SSE4_1,
32671 F_SSE4_2,
32672 F_AVX,
32673 F_AVX2,
32674 F_SSE4_A,
32675 F_FMA4,
32676 F_XOP,
32677 F_FMA,
32678 F_MAX
32679 };
32681 /* These are the values for vendor types and cpu types and subtypes
32682 in cpuinfo.c. Cpu types and subtypes should be subtracted by
32683 the corresponding start value. */
32684 enum processor_model
32685 {
32687 M_AMD,
32688 M_CPU_TYPE_START,
32689 M_INTEL_BONNELL,
32690 M_INTEL_CORE2,
32691 M_INTEL_COREI7,
32692 M_AMDFAM10H,
32693 M_AMDFAM15H,
32694 M_INTEL_SILVERMONT,
32695 M_AMD_BTVER1,
32696 M_AMD_BTVER2,
32697 M_CPU_SUBTYPE_START,
32698 M_INTEL_COREI7_NEHALEM,
32699 M_INTEL_COREI7_WESTMERE,
32700 M_INTEL_COREI7_SANDYBRIDGE,
32701 M_AMDFAM10H_BARCELONA,
32702 M_AMDFAM10H_SHANGHAI,
32703 M_AMDFAM10H_ISTANBUL,
32704 M_AMDFAM15H_BDVER1,
32705 M_AMDFAM15H_BDVER2,
32706 M_AMDFAM15H_BDVER3,
32707 M_AMDFAM15H_BDVER4,
32708 M_INTEL_COREI7_IVYBRIDGE,
32709 M_INTEL_COREI7_HASWELL
32710 };
32712 static struct _arch_names_table
32713 {
32716 }
32718 {
32743 };
32745 static struct _isa_names_table
32746 {
32749 }
32751 {
32767 };
32781 {
32782 /* *args must be a expr that can contain other EXPRS leading to a
32783 STRING_CST. */
32785 {
32788 }
32790 }
32795 {
32796 tree ref;
32797 tree field;
32798 tree final;
32801 unsigned int NUM_ARCH_NAMES
32810 {
32814 }
32819 /* CPU types are stored in the next field. */
32822 {
32825 }
32827 /* CPU subtypes are stored in the next field. */
32829 {
32832 }
32834 /* Get the appropriate field in __cpu_model. */
32838 /* Check the value. */
32842 }
32844 {
32845 tree ref;
32846 tree array_elt;
32847 tree field;
32848 tree final;
32851 unsigned int NUM_ISA_NAMES
32860 {
32864 }
32867 /* Get the last field, which is __cpu_features. */
32871 /* Get the appropriate field: __cpu_model.__cpu_features */
32875 /* Access the 0th element of __cpu_features array. */
32880 /* Return __cpu_model.__cpu_features[0] & field_val */
32884 }
32886 }
32888 static tree
32891 {
32893 {
32898 {
32901 }
32902 }
32904 #ifdef SUBTARGET_FOLD_BUILTIN
32906 #endif
32909 }
32911 /* Make builtins to detect cpu type and features supported. NAME is
32912 the builtin name, CODE is the builtin code, and FTYPE is the function
32913 type of the builtin. */
32915 static void
32918 {
32919 tree decl;
32920 tree type;
32928 }
32930 /* Make builtins to get CPU type and features supported. The created
32931 builtins are :
32933 __builtin_cpu_init (), to detect cpu type and features,
32934 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
32935 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
32936 */
32938 static void
32940 {
32947 }
32949 /* Internal method for ix86_init_builtins. */
32951 static void
32953 {
32965 sysv_va_ref =
32968 fnvoid_va_end_ms =
32970 fnvoid_va_start_ms =
32972 fnvoid_va_end_sysv =
32974 fnvoid_va_start_sysv =
32976 NULL_TREE);
32977 fnvoid_va_copy_ms =
32979 NULL_TREE);
32980 fnvoid_va_copy_sysv =
32996 }
32998 static void
33000 {
33003 /* The __float80 type. */
33006 {
33007 /* The __float80 type. */
33012 }
33015 /* The __float128 type. */
33021 /* This macro is built by i386-builtin-types.awk. */
33022 DEFINE_BUILTIN_PRIMITIVE_TYPES;
33023 }
33025 static void
33027 {
33028 tree t;
33032 /* Builtins to get CPU type and features. */
33035 /* TFmode support builtins. */
33041 /* We will expand them to normal call if SSE isn't available since
33042 they are used by libgcc. */
33062 #ifdef SUBTARGET_INIT_BUILTINS
33063 SUBTARGET_INIT_BUILTINS;
33064 #endif
33065 }
33067 /* Return the ix86 builtin for CODE. */
33069 static tree
33071 {
33076 }
33078 /* Errors in the source file can cause expand_expr to return const0_rtx
33079 where we expect a vector. To avoid crashing, use one of the vector
33080 clear instructions. */
33081 static rtx
33083 {
33087 }
33089 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
33091 static rtx
33093 {
33094 rtx pat;
33114 {
33118 }
33132 }
33134 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
33136 static rtx
33140 {
33141 rtx pat;
33149 rtx op;
33156 {
33236 }
33246 {
33253 {
33255 {
33258 {
33276 xop_rotl:
33278 {
33281 gcc_checking_assert
33283 }
33284 else
33285 {
33286 gcc_checking_assert
33297 }
33301 }
33302 }
33303 }
33304 else
33305 {
33306 non_constant:
33310 /* If we aren't optimizing, only allow one memory operand to be
33311 generated. */
33313 num_memory++;
33321 }
33325 }
33328 {
33339 else
33340 {
33346 }
33359 }
33366 }
33368 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
33369 insns with vec_merge. */
33371 static rtx
33373 rtx target)
33374 {
33375 rtx pat;
33402 }
33404 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
33406 static rtx
33409 {
33410 rtx pat;
33415 rtx op2;
33426 /* Swap operands if we have a comparison that isn't available in
33427 hardware. */
33429 {
33434 }
33454 }
33456 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
33458 static rtx
33460 rtx target)
33461 {
33462 rtx pat;
33476 /* Swap operands if we have a comparison that isn't available in
33477 hardware. */
33479 {
33483 }
33504 const0_rtx)));
33507 }
33509 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
33511 static rtx
33513 rtx target)
33514 {
33515 rtx pat;
33540 }
33542 static rtx
33545 {
33546 rtx pat;
33551 rtx op2;
33578 }
33580 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
33582 static rtx
33584 rtx target)
33585 {
33586 rtx pat;
33619 const0_rtx)));
33622 }
33624 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
33626 static rtx
33629 {
33630 rtx pat;
33668 {
33671 }
33674 {
33683 }
33685 {
33694 }
33695 else
33696 {
33703 }
33711 {
33716 emit_insn
33720 FLAGS_REG),
33721 const0_rtx)));
33723 }
33724 else
33726 }
33729 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
33731 static rtx
33734 {
33735 rtx pat;
33763 {
33766 }
33769 {
33778 }
33780 {
33789 }
33790 else
33791 {
33798 }
33806 {
33811 emit_insn
33815 FLAGS_REG),
33816 const0_rtx)));
33818 }
33819 else
33821 }
33823 /* Subroutine of ix86_expand_builtin to take care of insns with
33824 variable number of operands. */
33826 static rtx
33829 {
33835 struct
33836 {
33837 rtx op;
33849 {
34297 }
34302 {
34305 }
34308 {
34315 }
34316 else
34317 {
34320 }
34323 {
34330 {
34331 /* SIMD shift insns take either an 8-bit immediate or
34332 register as count. But builtin functions take int as
34333 count. If count doesn't match, we put it in register. */
34335 {
34339 }
34340 }
34343 {
34346 {
34422 {
34426 {
34429 }
34435 }
34437 }
34438 }
34439 else
34440 {
34444 /* If we aren't optimizing, only allow one memory operand to
34445 be generated. */
34447 num_memory++;
34450 {
34453 }
34454 else
34455 {
34458 }
34459 }
34463 }
34466 {
34491 }
34498 }
34500 /* Transform pattern of following layout:
34501 (parallel [
34502 set (A B)
34503 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
34504 ])
34505 into:
34506 (set (A B))
34508 Or:
34509 (parallel [ A B
34510 ...
34511 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
34512 ...
34513 ])
34514 into:
34515 (parallel [ A B ... ]) */
34517 static rtx
34519 {
34526 {
34535 }
34536 else
34537 {
34543 {
34548 }
34550 /* No more than 1 occurence was removed. */
34554 }
34555 }
34557 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
34558 with rounding. */
34559 static rtx
34562 {
34579 /* See avxintrin.h for values. */
34581 {
34585 };
34587 {
34592 };
34595 {
34598 }
34600 {
34603 }
34606 {
34609 }
34632 ? CODE_FOR_sse_ucomi_round
34639 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
34641 {
34647 }
34648 else
34649 {
34652 }
34658 set_dst,
34659 const0_rtx)));
34662 }
34664 static rtx
34667 {
34668 rtx pat;
34670 struct
34671 {
34672 rtx op;
34682 {
34759 }
34769 {
34776 {
34778 {
34780 {
34796 }
34797 }
34798 }
34800 {
34802 {
34805 }
34807 /* If there is no rounding use normal version of the pattern. */
34810 }
34811 else
34812 {
34817 {
34820 }
34821 else
34822 {
34825 }
34826 }
34830 }
34833 {
34858 }
34868 }
34870 /* Subroutine of ix86_expand_builtin to take care of special insns
34871 with variable number of operands. */
34873 static rtx
34876 {
34877 tree arg;
34881 struct
34882 {
34883 rtx op;
34893 {
34932 {
34940 }
34959 /* Reserve memory operand for target. */
34962 {
34963 /* These builtins and instructions require the memory
34964 to be properly aligned. */
34983 }
35008 {
35009 /* These builtins and instructions require the memory
35010 to be properly aligned. */
35019 }
35020 /* FALLTHRU */
35038 /* Reserve memory operand for target. */
35051 {
35052 /* These builtins and instructions require the memory
35053 to be properly aligned. */
35062 }
35075 }
35080 {
35085 {
35088 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
35089 on it. Try to improve it using get_pointer_alignment,
35090 and if the special builtin is one that requires strict
35091 mode alignment, also from it's GET_MODE_ALIGNMENT.
35092 Failure to do so could lead to ix86_legitimate_combined_insn
35093 rejecting all changes to such insns. */
35099 }
35100 else
35103 }
35104 else
35105 {
35112 }
35115 {
35124 {
35126 {
35132 else
35135 }
35136 }
35137 else
35138 {
35140 {
35141 /* This must be the memory operand. */
35144 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
35145 on it. Try to improve it using get_pointer_alignment,
35146 and if the special builtin is one that requires strict
35147 mode alignment, also from it's GET_MODE_ALIGNMENT.
35148 Failure to do so could lead to ix86_legitimate_combined_insn
35149 rejecting all changes to such insns. */
35155 }
35156 else
35157 {
35158 /* This must be register. */
35164 else
35165 {
35168 }
35169 }
35170 }
35174 }
35177 {
35192 }
35198 }
35200 /* Return the integer constant in ARG. Constrain it to be in the range
35201 of the subparts of VEC_TYPE; issue an error if not. */
35203 static int
35205 {
35210 {
35213 }
35216 }
35218 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35219 ix86_expand_vector_init. We DO have language-level syntax for this, in
35220 the form of (type){ init-list }. Except that since we can't place emms
35221 instructions from inside the compiler, we can't allow the use of MMX
35222 registers unless the user explicitly asks for it. So we do *not* define
35223 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
35224 we have builtins invoked by mmintrin.h that gives us license to emit
35225 these sorts of instructions. */
35227 static rtx
35229 {
35239 {
35242 }
35249 }
35251 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35252 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
35253 had a language-level syntax for referencing vector elements. */
35255 static rtx
35257 {
35261 rtx op0;
35281 }
35283 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
35284 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
35285 a language-level syntax for referencing vector elements. */
35287 static rtx
35289 {
35313 /* OP0 is the source of these builtin functions and shouldn't be
35314 modified. Create a copy, use it and return it as target. */
35320 }
35322 /* Choose max of DST and SRC and put it to DST. */
35323 static void
35325 {
35326 rtx t;
35329 {
35334 }
35335 else
35336 {
35342 }
35343 }
35345 /* Expand an expression EXP that calls a built-in function,
35346 with result going to TARGET if that's convenient
35347 (and in mode MODE if that's convenient).
35348 SUBTARGET may be used as the target for computing one of EXP's operands.
35349 IGNORE is nonzero if the value is to be ignored. */
35351 static rtx
35354 {
35364 /* For CPU builtins that can be folded, fold first and expand the fold. */
35366 {
35368 {
35369 /* Make it call __cpu_indicator_init in libgcc. */
35375 }
35378 {
35383 }
35384 }
35386 /* Determine whether the builtin function is available under the current ISA.
35387 Originally the builtin was not created if it wasn't applicable to the
35388 current ISA based on the command line switches. With function specific
35389 options, we need to check in the context of the function making the call
35390 whether it is supported. */
35393 {
35399 else
35400 {
35404 }
35406 }
35409 {
35414 /* Builtin arg1 is size of block but instruction op1 should
35415 be (size - 1). */
35455 /* Avoid registers which connot be used as index. */
35457 {
35461 }
35463 /* If op1 was a register originally then it may have
35464 mode other than Pmode. We need to extend in such
35465 case because bndldx may work only with Pmode regs. */
35473 else
35474 {
35480 }
35517 /* If no bounds were specified for returned value,
35518 then use INIT bounds. It usually happens when
35519 some built-in function is expanded. */
35521 {
35530 }
35535 {
35538 /* Return value and lb. */
35540 /* Bounds. */
35542 /* Size. */
35545 /* Size was passed but we need to use (size - 1) as for bndmk. */
35547 integer_minus_one_node);
35549 /* Add LB to size and inverse to get UB. */
35560 /* We need to move bounds to memory before any computations. */
35562 {
35565 }
35566 else
35569 /* Generate mem expression to be used for access to LB and UB. */
35576 /* Compute LB. */
35582 /* Compute UB. UB are stored in 1's complement form. Therefore
35583 we also use max here. */
35592 }
35595 {
35607 /* We need to move bounds to memory before any computations. */
35609 {
35612 }
35613 else
35617 {
35620 }
35621 else
35624 /* Generate mem expression to be used for access to LB and UB. */
35632 /* Allocate temporaries. */
35636 /* Compute LB. */
35642 /* Compute UB. UB are stored in 1's complement form. Therefore
35643 we also use max here. */
35650 }
35653 {
35668 }
35671 {
35677 /* We need to move bounds to memory first. */
35679 {
35682 }
35683 else
35686 /* Generate mem expression to access LB and load it. */
35692 }
35695 {
35701 /* We need to move bounds to memory first. */
35703 {
35706 }
35707 else
35710 /* Generate mem expression to access UB and load it. */
35717 /* We need to inverse all bits of UB. */
35721 }
35726 ? CODE_FOR_mmx_maskmovq
35728 /* Note the arg order is different from the operand order. */
35829 {
35830 REAL_VALUE_TYPE inf;
35831 rtx tmp;
35843 }
35853 {
35859 insn = (TARGET_64BIT
35863 }
35865 {
35866 insn = (TARGET_64BIT
35870 }
35871 else
35872 {
35875 insn = (TARGET_64BIT
35883 {
35886 }
35888 }
35891 {
35892 /* mode is VOIDmode if __builtin_rd* has been called
35893 without lhs. */
35897 }
35900 {
35905 }
35919 {
35944 }
35950 {
35953 }
35973 {
35976 }
35982 {
35986 {
36007 }
36012 }
36013 else
36014 {
36016 {
36028 }
36030 }
36060 ? CODE_FOR_tbm_bextri_si
36063 {
36066 }
36067 else
36068 {
36077 }
36093 rdrand_step:
36100 {
36103 }
36109 /* Emit SImode conditional move. */
36111 {
36114 }
36117 else
36124 const0_rtx);
36143 rdseed_step:
36150 {
36153 }
36159 const0_rtx);
36177 addcarryx:
36185 /* Generate CF from input operand. */
36190 /* Gen ADCX instruction to compute X+Y+CF. */
36205 /* Store the result. */
36208 {
36211 }
36214 /* Return current CF value. */
36256 kortest:
36270 /* Emit kortest. */
36272 /* And use setcc to return result from flags. */
36423 gather_gen:
36424 rtx half;
36437 /* Note the arg order is different from the operand order. */
36448 else
36452 {
36474 else
36481 {
36486 }
36493 else
36500 {
36505 }
36509 }
36511 /* Force memory operand only with base register here. But we
36512 don't want to do it on memory operand for other builtin
36513 functions. */
36523 {
36526 }
36527 else
36528 {
36531 }
36533 {
36536 }
36538 /* Optimize. If mask is known to have all high bits set,
36539 replace op0 with pc_rtx to signal that the instruction
36540 overwrites the whole destination and doesn't use its
36541 previous contents. */
36543 {
36545 {
36548 }
36550 {
36553 {
36557 negative++;
36560 negative++;
36561 }
36564 }
36567 {
36568 /* Recognize also when mask is like:
36569 __v2df src = _mm_setzero_pd ();
36570 __v2df mask = _mm_cmpeq_pd (src, src);
36571 or
36572 __v8sf src = _mm256_setzero_ps ();
36573 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
36574 as that is a cheaper way to load all ones into
36575 a register than having to load a constant from
36576 memory. */
36579 {
36584 {
36591 /* FALLTHRU */
36601 }
36602 }
36603 }
36604 }
36612 {
36636 }
36639 scatter_gen:
36655 /* Force memory operand only with base register here. But we
36656 don't want to do it on memory operand for other builtin
36657 functions. */
36664 {
36667 }
36668 else
36669 {
36672 }
36681 {
36684 }
36693 vec_prefetch_gen:
36711 {
36714 }
36716 {
36719 }
36724 /* Force memory operand only with base register here. But we
36725 don't want to do it on memory operand for other builtin
36726 functions. */
36733 {
36736 }
36739 {
36742 }
36758 {
36761 }
36767 }
36780 {
36784 /* Emit a normal call if SSE isn't available. */
36788 }
36817 }
36819 /* This returns the target-specific builtin with code CODE if
36820 current_function_decl has visibility on this builtin, which is checked
36821 using isa flags. Returns NULL_TREE otherwise. */
36824 {
36828 /* Determine the isa flags of current_function_decl. */
36840 else
36842 }
36844 /* Return function decl for target specific builtin
36845 for given MPX builtin passed i FCODE. */
36846 static tree
36848 {
36850 {
36886 }
36889 }
36891 /* Load bounds PTR pointer value loaded from SLOT.
36892 if SLOT is a register then load bounds associated
36893 with special address identified by BND.
36895 Return loaded bounds. */
36896 static rtx
36898 {
36900 rtx reg;
36903 {
36906 }
36909 {
36915 /* Here we have the case when more than four pointers are
36916 passed in registers. In this case we are out of bound
36917 registers and have to use bndldx to load bound. RA,
36918 RA - 8, etc. are used for address translation in bndldx. */
36920 }
36922 {
36925 }
36926 else
36930 /* If ptr was a register originally then it may have
36931 mode other than Pmode. We need to extend in such
36932 case because bndldx may work only with Pmode regs. */
36934 {
36938 }
36946 }
36948 /* Store bounds BOUNDS for PTR pointer value stored in
36949 specified ADDR. If ADDR is a register then TO identifies
36950 which special address to use for bounds store. */
36951 static void
36953 {
36955 {
36958 }
36961 {
36964 }
36967 else
36970 /* Should we also ignore integer modes of incorrect size?. */
36974 /* Avoid registers which connot be used as index. */
36976 {
36980 }
36988 }
36990 /* Load and return bounds returned by function in SLOT. */
36991 static rtx
36993 {
36994 rtx res;
37001 }
37003 /* Store BOUNDS returned by function into SLOT. */
37004 static void
37006 {
37009 }
37011 /* Returns a function decl for a vectorized version of the builtin function
37012 with builtin function code FN and the result vector type TYPE, or NULL_TREE
37013 if it is not available. */
37015 static tree
37017 tree type_in)
37018 {
37034 {
37037 {
37044 }
37049 {
37052 }
37057 {
37064 }
37070 /* The round insn does not trap on denormals. */
37075 {
37082 }
37088 /* The round insn does not trap on denormals. */
37093 {
37098 }
37104 /* The round insn does not trap on denormals. */
37109 {
37116 }
37122 /* The round insn does not trap on denormals. */
37127 {
37132 }
37139 {
37144 }
37151 {
37156 }
37162 /* The round insn does not trap on denormals. */
37167 {
37174 }
37180 /* The round insn does not trap on denormals. */
37185 {
37190 }
37195 {
37202 }
37207 {
37214 }
37218 /* The round insn does not trap on denormals. */
37223 {
37228 }
37232 /* The round insn does not trap on denormals. */
37237 {
37242 }
37246 /* The round insn does not trap on denormals. */
37251 {
37256 }
37260 /* The round insn does not trap on denormals. */
37265 {
37270 }
37274 /* The round insn does not trap on denormals. */
37279 {
37284 }
37288 /* The round insn does not trap on denormals. */
37293 {
37298 }
37302 /* The round insn does not trap on denormals. */
37307 {
37312 }
37316 /* The round insn does not trap on denormals. */
37321 {
37326 }
37330 /* The round insn does not trap on denormals. */
37335 {
37340 }
37344 /* The round insn does not trap on denormals. */
37349 {
37354 }
37359 {
37364 }
37369 {
37374 }
37379 }
37381 /* Dispatch to a handler for a vectorization library. */
37384 type_in);
37387 }
37389 /* Handler for an SVML-style interface to
37390 a library with vectorized intrinsics. */
37392 static tree
37394 {
37402 /* The SVML is suitable for unsafe math only. */
37415 {
37462 }
37471 {
37474 }
37475 else
37478 /* Convert to uppercase. */
37483 args;
37485 arity++;
37489 else
37492 /* Build a function declaration for the vectorized function. */
37501 }
37503 /* Handler for an ACML-style interface to
37504 a library with vectorized intrinsics. */
37506 static tree
37508 {
37516 /* The ACML is 64bits only and suitable for unsafe math only as
37517 it does not correctly support parts of IEEE with the required
37518 precision such as denormals. */
37532 {
37562 }
37569 args;
37571 arity++;
37575 else
37578 /* Build a function declaration for the vectorized function. */
37587 }
37589 /* Returns a decl of a function that implements gather load with
37590 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
37591 Return NULL_TREE if it is not available. */
37593 static tree
37596 {
37612 /* v*gather* insn sign extends index to pointer mode. */
37624 {
37652 else
37658 else
37664 else
37670 else
37675 }
37678 }
37680 /* Returns a code for a target-specific builtin that implements
37681 reciprocal of the function, or NULL_TREE if not available. */
37683 static tree
37686 {
37693 /* Machine dependent builtins. */
37695 {
37696 /* Vectorized version of sqrt to rsqrt conversion. */
37705 }
37706 else
37707 /* Normal builtins. */
37709 {
37710 /* Sqrt to rsqrt conversion. */
37716 }
37717 }
37718 \f
37719 /* Helper for avx_vpermilps256_operand et al. This is also used by
37720 the expansion functions to turn the parallel back into a mask.
37721 The return value is 0 for no match and the imm8+1 for a match. */
37723 int
37725 {
37733 /* Validate that all of the elements are constants, and not totally
37734 out of range. Copy the data into an integral array to make the
37735 subsequent checks easier. */
37737 {
37747 }
37750 {
37752 /* In the 512-bit DFmode case, we can only move elements within
37753 a 128-bit lane. First fill the second part of the mask,
37754 then fallthru. */
37756 {
37760 }
37762 {
37766 }
37767 /* FALLTHRU */
37770 /* In the 256-bit DFmode case, we can only move elements within
37771 a 128-bit lane. */
37773 {
37777 }
37779 {
37783 }
37787 /* In 512 bit SFmode case, permutation in the upper 256 bits
37788 must mirror the permutation in the lower 256-bits. */
37792 /* FALLTHRU */
37795 /* In 256 bit SFmode case, we have full freedom of
37796 movement within the low 128-bit lane, but the high 128-bit
37797 lane must mirror the exact same pattern. */
37802 /* FALLTHRU */
37806 /* In the 128-bit case, we've full freedom in the placement of
37807 the elements from the source operand. */
37814 }
37816 /* Make sure success has a non-zero value by adding one. */
37818 }
37820 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
37821 the expansion functions to turn the parallel back into a mask.
37822 The return value is 0 for no match and the imm8+1 for a match. */
37824 int
37826 {
37834 /* Validate that all of the elements are constants, and not totally
37835 out of range. Copy the data into an integral array to make the
37836 subsequent checks easier. */
37838 {
37848 }
37850 /* Validate that the halves of the permute are halves. */
37858 /* Reconstruct the mask. */
37860 {
37866 }
37868 /* Make sure success has a non-zero value by adding one. */
37870 }
37871 \f
37872 /* Return a register priority for hard reg REGNO. */
37873 static int
37875 {
37876 /* ebp and r13 as the base always wants a displacement, r12 as the
37877 base always wants an index. So discourage their usage in an
37878 address. */
37883 /* New x86-64 int registers result in bigger code size. Discourage
37884 them. */
37887 /* New x86-64 SSE registers result in bigger code size. Discourage
37888 them. */
37891 /* Usage of AX register results in smaller code. Prefer it. */
37895 }
37897 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
37899 Put float CONST_DOUBLE in the constant pool instead of fp regs.
37900 QImode must go into class Q_REGS.
37901 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
37902 movdf to do mem-to-mem moves through integer regs. */
37904 static reg_class_t
37906 {
37909 /* We're only allowed to return a subclass of CLASS. Many of the
37910 following checks fail for NO_REGS, so eliminate that early. */
37914 /* All classes can load zeros. */
37918 /* Force constants into memory if we are loading a (nonzero) constant into
37919 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
37920 instructions to load from a constant. */
37927 /* Prefer SSE regs only, if we can use them for math. */
37931 /* Floating-point constants need more complex checks. */
37933 {
37934 /* General regs can load everything. */
37938 /* Floats can load 0 and 1 plus some others. Note that we eliminated
37939 zero above. We only want to wind up preferring 80387 registers if
37940 we plan on doing computation with them. */
37943 {
37944 /* Limit class to non-sse. */
37953 }
37956 }
37958 /* Generally when we see PLUS here, it's the function invariant
37959 (plus soft-fp const_int). Which can only be computed into general
37960 regs. */
37964 /* QImode constants are easy to load, but non-constant QImode data
37965 must go into Q_REGS. */
37967 {
37973 }
37976 }
37978 /* Discourage putting floating-point values in SSE registers unless
37979 SSE math is being used, and likewise for the 387 registers. */
37980 static reg_class_t
37982 {
37985 /* Restrict the output reload class to the register bank that we are doing
37986 math on. If we would like not to return a subset of CLASS, reject this
37987 alternative: if reload cannot do this, it will still use its choice. */
37993 {
37998 else
38000 }
38003 }
38005 static reg_class_t
38008 {
38009 /* Double-word spills from general registers to non-offsettable memory
38010 references (zero-extended addresses) require special handling. */
38016 {
38018 ? CODE_FOR_reload_noff_load
38020 /* Add the cost of moving address to a temporary. */
38024 }
38026 /* QImode spills from non-QI registers require
38027 intermediate register on 32bit targets. */
38033 {
38038 else
38044 /* Return Q_REGS if the operand is in memory. */
38047 }
38049 /* This condition handles corner case where an expression involving
38050 pointers gets vectorized. We're trying to use the address of a
38051 stack slot as a vector initializer.
38053 (set (reg:V2DI 74 [ vect_cst_.2 ])
38054 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
38056 Eventually frame gets turned into sp+offset like this:
38058 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
38059 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
38060 (const_int 392 [0x188]))))
38062 That later gets turned into:
38064 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
38065 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
38066 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
38068 We'll have the following reload recorded:
38070 Reload 0: reload_in (DI) =
38071 (plus:DI (reg/f:DI 7 sp)
38072 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
38073 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
38074 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
38075 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
38076 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
38077 reload_reg_rtx: (reg:V2DI 22 xmm1)
38079 Which isn't going to work since SSE instructions can't handle scalar
38080 additions. Returning GENERAL_REGS forces the addition into integer
38081 register and reload can handle subsequent reloads without problems. */
38089 }
38091 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
38093 static bool
38095 {
38097 {
38113 }
38116 }
38118 /* If we are copying between general and FP registers, we need a memory
38119 location. The same is true for SSE and MMX registers.
38121 To optimize register_move_cost performance, allow inline variant.
38123 The macro can't work reliably when one of the CLASSES is class containing
38124 registers from multiple units (SSE, MMX, integer). We avoid this by never
38125 combining those units in single alternative in the machine description.
38126 Ensure that this constraint holds to avoid unexpected surprises.
38128 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
38129 enforce these sanity checks. */
38134 {
38143 {
38146 }
38151 /* ??? This is a lie. We do have moves between mmx/general, and for
38152 mmx/sse2. But by saying we need secondary memory we discourage the
38153 register allocator from using the mmx registers unless needed. */
38158 {
38159 /* SSE1 doesn't have any direct moves from other classes. */
38163 /* If the target says that inter-unit moves are more expensive
38164 than moving through memory, then don't generate them. */
38169 /* Between SSE and general, we have moves no larger than word size. */
38172 }
38175 }
38177 bool
38180 {
38182 }
38184 /* Implement the TARGET_CLASS_MAX_NREGS hook.
38186 On the 80386, this is the size of MODE in words,
38187 except in the FP regs, where a single reg is always enough. */
38189 static unsigned char
38191 {
38193 {
38198 else
38200 }
38201 else
38202 {
38205 else
38207 }
38208 }
38210 /* Return true if the registers in CLASS cannot represent the change from
38211 modes FROM to TO. */
38213 bool
38216 {
38220 /* x87 registers can't do subreg at all, as all values are reformatted
38221 to extended precision. */
38226 {
38227 /* Vector registers do not support QI or HImode loads. If we don't
38228 disallow a change to these modes, reload will assume it's ok to
38229 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
38230 the vec_dupv4hi pattern. */
38234 /* Vector registers do not support subreg with nonzero offsets, which
38235 are otherwise valid for integer registers. Since we can't see
38236 whether we have a nonzero offset from here, prohibit all
38237 nonparadoxical subregs changing size. */
38240 }
38243 }
38245 /* Return the cost of moving data of mode M between a
38246 register and memory. A value of 2 is the default; this cost is
38247 relative to those in `REGISTER_MOVE_COST'.
38249 This function is used extensively by register_move_cost that is used to
38250 build tables at startup. Make it inline in this case.
38251 When IN is 2, return maximum of in and out move cost.
38253 If moving between registers and memory is more expensive than
38254 between two registers, you should define this macro to express the
38255 relative cost.
38257 Model also increased moving costs of QImode registers in non
38258 Q_REGS classes.
38259 */
38263 {
38266 {
38269 {
38281 }
38285 }
38287 {
38290 {
38302 }
38306 }
38308 {
38311 {
38320 }
38324 }
38326 {
38329 {
38335 else
38340 }
38341 else
38342 {
38347 else
38349 }
38356 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
38363 else
38367 }
38368 }
38370 static int
38373 {
38375 }
38378 /* Return the cost of moving data from a register in class CLASS1 to
38379 one in class CLASS2.
38381 It is not required that the cost always equal 2 when FROM is the same as TO;
38382 on some machines it is expensive to move between registers if they are not
38383 general registers. */
38385 static int
38387 reg_class_t class2_i)
38388 {
38392 /* In case we require secondary memory, compute cost of the store followed
38393 by load. In order to avoid bad register allocation choices, we need
38394 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
38397 {
38403 /* In case of copying from general_purpose_register we may emit multiple
38404 stores followed by single load causing memory size mismatch stall.
38405 Count this as arbitrarily high cost of 20. */
38410 /* In the case of FP/MMX moves, the registers actually overlap, and we
38411 have to switch modes in order to treat them differently. */
38417 }
38419 /* Moves between SSE/MMX and integer unit are expensive. */
38423 /* ??? By keeping returned value relatively high, we limit the number
38424 of moves between integer and MMX/SSE registers for all targets.
38425 Additionally, high value prevents problem with x86_modes_tieable_p(),
38426 where integer modes in MMX/SSE registers are not tieable
38427 because of missing QImode and HImode moves to, from or between
38428 MMX/SSE registers. */
38438 }
38440 /* Return TRUE if hard register REGNO can hold a value of machine-mode
38441 MODE. */
38443 bool
38445 {
38446 /* Flags and only flags can only hold CCmode values. */
38460 {
38461 /* We implement the move patterns for all vector modes into and
38462 out of SSE registers, even when no operation instructions
38463 are available. */
38465 /* For AVX-512 we allow, regardless of regno:
38466 - XI mode
38467 - any of 512-bit wide vector mode
38468 - any scalar mode. */
38475 /* xmm16-xmm31 are only available for AVX-512. */
38479 /* OImode and AVX modes are available only when AVX is enabled. */
38486 }
38488 {
38489 /* We implement the move patterns for 3DNOW modes even in MMX mode,
38490 so if the register is available at all, then we can move data of
38491 the given mode into or out of it. */
38494 }
38497 {
38498 /* Take care for QImode values - they can be in non-QI regs,
38499 but then they do cause partial register stalls. */
38504 /* LRA checks if the hard register is OK for the given mode.
38505 QImode values can live in non-QI regs, so we allow all
38506 registers here. */
38510 }
38511 /* We handle both integer and floats in the general purpose registers. */
38518 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
38519 on to use that value in smaller contexts, this can easily force a
38520 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
38521 supporting DImode, allow it. */
38526 }
38528 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
38529 tieable integer mode. */
38531 static bool
38533 {
38535 {
38548 }
38549 }
38551 /* Return true if MODE1 is accessible in a register that can hold MODE2
38552 without copying. That is, all register classes that can hold MODE2
38553 can also hold MODE1. */
38555 bool
38557 {
38565 /* MODE2 being XFmode implies fp stack or general regs, which means we
38566 can tie any smaller floating point modes to it. Note that we do not
38567 tie this with TFmode. */
38571 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
38572 that we can tie it with SFmode. */
38576 /* If MODE2 is only appropriate for an SSE register, then tie with
38577 any other mode acceptable to SSE registers. */
38587 /* If MODE2 is appropriate for an MMX register, then tie
38588 with any other mode acceptable to MMX registers. */
38595 }
38597 /* Return the cost of moving between two registers of mode MODE. */
38599 static int
38601 {
38605 {
38637 }
38639 /* Return the cost of moving between two registers of mode MODE,
38640 assuming that the move will be in pieces of at most UNITS bytes. */
38642 }
38644 /* Compute a (partial) cost for rtx X. Return true if the complete
38645 cost has been computed, and false if subexpressions should be
38646 scanned. In either case, *TOTAL contains the cost result. */
38648 static bool
38651 {
38652 rtx mask;
38659 {
38663 {
38666 }
38678 && (!TARGET_64BIT
38683 else
38689 {
38692 }
38694 {
38704 }
38706 {
38709 {
38718 }
38719 }
38720 /* Fall back to (MEM (SYMBOL_REF)), since that's where
38721 it'll probably end up. Add a penalty for size. */
38728 /* The zero extensions is often completely free on x86_64, so make
38729 it as cheap as possible. */
38735 else
38747 {
38750 {
38753 }
38756 {
38759 }
38760 }
38761 /* FALLTHRU */
38768 {
38769 /* ??? Should be SSE vector operation cost. */
38770 /* At least for published AMD latencies, this really is the same
38771 as the latency for a simple fpu operation like fabs. */
38772 /* V*QImode is emulated with 1-11 insns. */
38774 {
38777 {
38778 /* For XOP we use vpshab, which requires a broadcast of the
38779 value to the variable shift insn. For constants this
38780 means a V16Q const in mem; even when we can perform the
38781 shift with one insn set the cost to prefer paddb. */
38783 {
38788 }
38790 }
38794 }
38795 else
38797 }
38799 {
38801 {
38804 else
38806 }
38807 else
38808 {
38811 else
38813 }
38814 }
38815 else
38816 {
38821 {
38822 /* Return the cost after shift-and truncation. */
38825 }
38826 else
38828 }
38832 {
38833 rtx sub;
38838 /* ??? SSE scalar/vector cost should be used here. */
38839 /* ??? Bald assumption that fma has the same cost as fmul. */
38843 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
38854 }
38858 {
38859 /* ??? SSE scalar cost should be used here. */
38862 }
38864 {
38867 }
38869 {
38870 /* ??? SSE vector cost should be used here. */
38873 }
38875 {
38876 /* V*QImode is emulated with 7-13 insns. */
38878 {
38885 }
38886 /* V*DImode is emulated with 5-8 insns. */
38888 {
38891 else
38893 }
38894 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
38895 insns, including two PMULUDQ. */
38898 else
38901 }
38902 else
38903 {
38908 {
38911 nbits++;
38912 }
38913 else
38914 /* This is arbitrary. */
38917 /* Compute costs correctly for widening multiplication. */
38921 {
38928 {
38932 else
38934 }
38938 }
38946 }
38953 /* ??? SSE cost should be used here. */
38958 /* ??? SSE vector cost should be used here. */
38960 else
38967 {
38972 {
38975 {
38983 }
38984 }
38987 {
38990 {
38996 }
38997 }
38999 {
39007 }
39008 }
39009 /* FALLTHRU */
39013 {
39014 /* ??? SSE cost should be used here. */
39017 }
39019 {
39022 }
39024 {
39025 /* ??? SSE vector cost should be used here. */
39028 }
39029 /* FALLTHRU */
39036 {
39043 }
39044 /* FALLTHRU */
39048 {
39049 /* ??? SSE cost should be used here. */
39052 }
39054 {
39057 }
39059 {
39060 /* ??? SSE vector cost should be used here. */
39063 }
39064 /* FALLTHRU */
39068 {
39069 /* ??? Should be SSE vector operation cost. */
39070 /* At least for published AMD latencies, this really is the same
39071 as the latency for a simple fpu operation like fabs. */
39073 }
39076 else
39085 {
39086 /* This kind of construct is implemented using test[bwl].
39087 Treat it as if we had an AND. */
39092 }
39102 /* ??? SSE cost should be used here. */
39107 /* ??? SSE vector cost should be used here. */
39113 /* ??? SSE cost should be used here. */
39118 /* ??? SSE vector cost should be used here. */
39130 /* ??? Assume all of these vector manipulation patterns are
39131 recognizable. In which case they all pretty much have the
39132 same cost. */
39137 /* This is masked instruction, assume the same cost,
39138 as nonmasked variant. */
39141 else
39147 }
39148 }
39150 #if TARGET_MACHO
39154 /* Given a symbol name and its associated stub, write out the
39155 definition of the stub. */
39157 void
39159 {
39164 /* For 64-bit we shouldn't get here. */
39167 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
39184 else
39191 {
39193 }
39195 {
39196 /* PIC stub. */
39197 /* 25-byte PIC stub using "CALL get_pc_thunk". */
39203 }
39204 else
39207 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
39208 it needs no stub-binding-helper. */
39215 {
39218 }
39219 else
39224 /* N.B. Keep the correspondence of these
39225 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
39226 old-pic/new-pic/non-pic stubs; altering this will break
39227 compatibility with existing dylibs. */
39229 {
39230 /* 25-byte PIC stub using "CALL get_pc_thunk". */
39232 }
39233 else
39234 /* 16-byte -mdynamic-no-pic stub. */
39240 }
39243 /* Order the registers for register allocator. */
39245 void
39247 {
39251 /* First allocate the local general purpose registers. */
39256 /* Global general purpose registers. */
39261 /* x87 registers come first in case we are doing FP math
39262 using them. */
39267 /* SSE registers. */
39273 /* Extended REX SSE registers. */
39277 /* Mask register. */
39281 /* MPX bound registers. */
39285 /* x87 registers. */
39293 /* Initialize the rest of array as we do not allocate some registers
39294 at all. */
39297 }
39299 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
39300 in struct attribute_spec handler. */
39301 static tree
39303 tree args,
39306 {
39311 {
39313 name);
39316 }
39318 {
39320 name);
39323 }
39325 {
39326 tree cst;
39330 {
39333 name);
39335 }
39338 {
39341 name);
39343 }
39346 }
39349 }
39351 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
39352 struct attribute_spec.handler. */
39353 static tree
39355 tree args ATTRIBUTE_UNUSED,
39357 {
39362 {
39364 name);
39367 }
39369 /* Can combine regparm with all attributes but fastcall. */
39371 {
39373 {
39375 }
39378 }
39380 {
39382 {
39384 }
39387 }
39390 }
39392 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
39393 struct attribute_spec.handler. */
39394 static tree
39396 tree args ATTRIBUTE_UNUSED,
39398 {
39401 {
39404 }
39405 else
39409 {
39411 name);
39413 }
39419 {
39421 name);
39423 }
39426 }
39428 static tree
39430 tree args ATTRIBUTE_UNUSED,
39432 {
39434 {
39436 name);
39438 }
39440 }
39442 static bool
39444 {
39448 }
39450 /* Returns an expression indicating where the this parameter is
39451 located on entry to the FUNCTION. */
39453 static rtx
39455 {
39461 {
39466 else
39469 }
39474 {
39481 {
39486 }
39487 else
39488 {
39491 {
39497 }
39498 }
39500 }
39504 }
39506 /* Determine whether x86_output_mi_thunk can succeed. */
39508 static bool
39510 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
39512 {
39513 /* 64-bit can handle anything. */
39517 /* For 32-bit, everything's fine if we have one free register. */
39521 /* Need a free register for vcall_offset. */
39525 /* Need a free register for GOT references. */
39529 /* Otherwise ok. */
39531 }
39533 /* Output the assembler code for a thunk function. THUNK_DECL is the
39534 declaration for the thunk function itself, FUNCTION is the decl for
39535 the target function. DELTA is an immediate constant offset to be
39536 added to THIS. If VCALL_OFFSET is nonzero, the word at
39537 *(*this + vcall_offset) should be added to THIS. */
39539 static void
39543 {
39550 else
39551 {
39557 else
39559 }
39563 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
39564 pull it in now and let DELTA benefit. */
39568 {
39569 /* Put the this parameter into %eax. */
39572 }
39573 else
39576 /* Adjust the this parameter by a fixed constant. */
39578 {
39583 {
39585 {
39589 }
39590 }
39593 }
39595 /* Adjust the this parameter by a value stored in the vtable. */
39597 {
39607 /* Adjust the this parameter. */
39611 {
39615 }
39622 vcall_mem));
39623 else
39625 }
39627 /* If necessary, drop THIS back to its stack slot. */
39633 {
39636 ;
39637 else
39638 {
39642 }
39643 }
39644 else
39645 {
39647 ;
39648 #if TARGET_MACHO
39650 {
39653 }
39655 else
39656 {
39664 }
39665 }
39667 /* Our sibling call patterns do not allow memories, because we have no
39668 predicate that can distinguish between frame and non-frame memory.
39669 For our purposes here, we can get away with (ab)using a jump pattern,
39670 because we're going to do no optimization. */
39673 else
39674 {
39680 {
39686 }
39692 }
39695 /* Emit just enough of rest_of_compilation to get the insns emitted.
39696 Note that use_thunk calls assemble_start_function et al. */
39702 }
39704 static void
39706 {
39710 #if TARGET_MACHO
39712 #endif
39719 }
39721 int
39723 {
39735 }
39737 /* Output assembler code to FILE to increment profiler label # LABELNO
39738 for profiling a function entry. */
39739 void
39741 {
39746 {
39747 #ifndef NO_PROFILE_COUNTERS
39749 #endif
39753 else
39755 }
39757 {
39758 #ifndef NO_PROFILE_COUNTERS
39761 #endif
39763 }
39764 else
39765 {
39766 #ifndef NO_PROFILE_COUNTERS
39769 #endif
39771 }
39772 }
39774 /* We don't have exact information about the insn sizes, but we may assume
39775 quite safely that we are informed about all 1 byte insns and memory
39776 address sizes. This is enough to eliminate unnecessary padding in
39777 99% of cases. */
39779 static int
39781 {
39787 /* Discard alignments we've emit and jump instructions. */
39792 /* Important case - calls are always 5 bytes.
39793 It is common to have many calls in the row. */
39802 /* For normal instructions we rely on get_attr_length being exact,
39803 with a few exceptions. */
39805 {
39809 {
39819 /* Otherwise trust get_attr_length. */
39821 }
39826 }
39829 else
39831 }
39833 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
39835 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
39836 window. */
39838 static void
39840 {
39845 /* Look for all minimal intervals of instructions containing 4 jumps.
39846 The intervals are bounded by START and INSN. NBYTES is the total
39847 size of instructions in the interval including INSN and not including
39848 START. When the NBYTES is smaller than 16 bytes, it is possible
39849 that the end of START and INSN ends up in the same 16byte page.
39851 The smallest offset in the page INSN can start is the case where START
39852 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
39853 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
39855 Don't consider asm goto as jump, while it can contain a jump, it doesn't
39856 have to, control transfer to label(s) can be performed through other
39857 means, and also we estimate minimum length of all asm stmts as 0. */
39859 {
39863 {
39869 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
39870 already in the current 16 byte page, because otherwise
39871 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
39872 bytes to reach 16 byte boundary. */
39880 {
39882 {
39887 else
39890 }
39891 }
39893 }
39902 njumps++;
39903 else
39907 {
39912 else
39915 }
39922 {
39929 }
39930 }
39931 }
39932 #endif
39934 /* AMD Athlon works faster
39935 when RET is not destination of conditional jump or directly preceded
39936 by other jump instruction. We avoid the penalty by inserting NOP just
39937 before the RET instructions in such cases. */
39938 static void
39940 {
39941 edge e;
39942 edge_iterator ei;
39945 {
39948 rtx prev;
39958 {
39959 edge e;
39960 edge_iterator ei;
39965 {
39968 }
39969 }
39971 {
39977 /* Empty functions get branch mispredict even when
39978 the jump destination is not visible to us. */
39981 }
39983 {
39986 }
39987 }
39988 }
39990 /* Count the minimum number of instructions in BB. Return 4 if the
39991 number of instructions >= 4. */
39993 static int
39995 {
39996 rtx insn;
39999 /* Count number of instructions in this block. Return 4 if the number
40000 of instructions >= 4. */
40002 {
40003 /* Only happen in exit blocks. */
40011 {
40012 insn_count++;
40015 }
40016 }
40019 }
40022 /* Count the minimum number of instructions in code path in BB.
40023 Return 4 if the number of instructions >= 4. */
40025 static int
40027 {
40028 edge e;
40029 edge_iterator ei;
40032 /* Only bother counting instructions along paths with no
40033 more than 2 basic blocks between entry and exit. Given
40034 that BB has an edge to exit, determine if a predecessor
40035 of BB has an edge from entry. If so, compute the number
40036 of instructions in the predecessor block. If there
40037 happen to be multiple such blocks, compute the minimum. */
40040 {
40041 edge prev_e;
40042 edge_iterator prev_ei;
40045 {
40048 }
40050 {
40052 {
40057 }
40058 }
40059 }
40065 }
40067 /* Pad short function to 4 instructions. */
40069 static void
40071 {
40072 edge e;
40073 edge_iterator ei;
40076 {
40079 {
40082 /* Pad short function. */
40084 {
40087 /* Find epilogue. */
40096 /* Two NOPs count as one instruction. */
40099 }
40100 }
40101 }
40102 }
40104 /* Fix up a Windows system unwinder issue. If an EH region falls through into
40105 the epilogue, the Windows system unwinder will apply epilogue logic and
40106 produce incorrect offsets. This can be avoided by adding a nop between
40107 the last insn that can throw and the first insn of the epilogue. */
40109 static void
40111 {
40112 edge e;
40113 edge_iterator ei;
40116 {
40119 /* Find the beginning of the epilogue. */
40126 /* We only care about preceding insns that can throw. */
40131 /* Do not separate calls from their debug information. */
40137 else
40141 }
40142 }
40144 /* Implement machine specific optimizations. We implement padding of returns
40145 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
40146 static void
40148 {
40149 /* We are freeing block_for_insn in the toplev to keep compatibility
40150 with old MDEP_REORGS that are not CFG based. Recompute it now. */
40157 {
40162 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
40165 #endif
40166 }
40167 }
40169 /* Return nonzero when QImode register that must be represented via REX prefix
40170 is used. */
40171 bool
40173 {
40181 }
40183 /* Return nonzero when P points to register encoded via REX prefix.
40184 Called via for_each_rtx. */
40185 static int
40187 {
40193 }
40195 /* Return true when INSN mentions register that must be encoded using REX
40196 prefix. */
40197 bool
40199 {
40202 }
40204 /* If profitable, negate (without causing overflow) integer constant
40205 of mode MODE at location LOC. Return true in this case. */
40206 bool
40208 {
40209 HOST_WIDE_INT val;
40215 {
40217 /* DImode x86_64 constants must fit in 32 bits. */
40230 }
40232 /* Avoid overflows. */
40238 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
40239 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
40242 {
40245 }
40248 }
40250 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
40251 optabs would emit if we didn't have TFmode patterns. */
40253 void
40255 {
40289 }
40290 \f
40291 /* AVX512F does support 64-byte integer vector operations,
40292 thus the longest vector we are faced with is V64QImode. */
40293 #define MAX_VECT_LEN 64
40295 struct expand_vec_perm_d
40296 {
40303 };
40309 /* Get a vector mode of the same size as the original but with elements
40310 twice as wide. This is only guaranteed to apply to integral vectors. */
40314 {
40315 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
40320 }
40322 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
40323 fill target with val via vec_duplicate. */
40325 static bool
40327 {
40331 /* First attempt to recognize VAL as-is. */
40335 {
40336 rtx seq;
40337 /* If that fails, force VAL into a register. */
40348 }
40350 }
40352 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
40353 with all elements equal to VAR. Return true if successful. */
40355 static bool
40358 {
40362 {
40367 /* FALLTHRU */
40387 {
40388 rtx x;
40395 }
40405 {
40409 permute:
40417 /* Extend to SImode using a paradoxical SUBREG. */
40421 /* Insert the SImode value as low element of a V4SImode vector. */
40430 }
40438 widen:
40439 /* Replicate the value once into the next wider mode and recurse. */
40440 {
40442 rtx x;
40459 }
40463 {
40472 }
40477 }
40478 }
40480 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
40481 whose ONE_VAR element is VAR, and other elements are zero. Return true
40482 if successful. */
40484 static bool
40487 {
40489 rtx new_target;
40494 {
40496 /* For SSE4.1, we normally use vector set. But if the second
40497 element is zero and inter-unit moves are OK, we use movq
40498 instead. */
40500 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
40522 /* Use ix86_expand_vector_set in 64bit mode only. */
40527 }
40530 {
40535 }
40538 {
40543 /* FALLTHRU */
40558 else
40565 {
40566 /* We need to shuffle the value to the correct position, so
40567 create a new pseudo to store the intermediate result. */
40569 /* With SSE2, we can use the integer shuffle insns. */
40571 {
40573 const1_rtx,
40580 }
40582 /* Otherwise convert the intermediate result to V4SFmode and
40583 use the SSE1 shuffle instructions. */
40585 {
40588 }
40589 else
40593 const1_rtx,
40602 }
40617 widen:
40621 /* Zero extend the variable element to SImode and recurse. */
40634 }
40635 }
40637 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
40638 consisting of the values in VALS. It is known that all elements
40639 except ONE_VAR are constants. Return true if successful. */
40641 static bool
40644 {
40654 {
40659 /* For the two element vectors, it's just as easy to use
40660 the general case. */
40664 /* Use ix86_expand_vector_set in 64bit mode only. */
40686 widen:
40687 /* There's no way to set one QImode entry easily. Combine
40688 the variable value with its adjacent constant value, and
40689 promote to an HImode set. */
40692 {
40697 }
40698 else
40699 {
40702 }
40716 }
40721 }
40723 /* A subroutine of ix86_expand_vector_init_general. Use vector
40724 concatenate to handle the most general case: all values variable,
40725 and none identical. */
40727 static void
40730 {
40733 rtvec v;
40737 {
40740 {
40785 }
40798 {
40813 }
40818 {
40837 }
40842 {
40855 }
40858 half:
40859 /* FIXME: We process inputs backward to help RA. PR 36222. */
40863 {
40868 }
40872 {
40876 {
40880 }
40883 {
40887 }
40890 }
40892 {
40895 {
40899 }
40902 }
40903 else
40909 }
40910 }
40912 /* A subroutine of ix86_expand_vector_init_general. Use vector
40913 interleave to handle the most general case: all values variable,
40914 and none identical. */
40916 static void
40919 {
40928 {
40949 }
40952 {
40953 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
40957 /* Insert the SImode value as low element of V4SImode vector. */
40961 op0),
40963 const1_rtx);
40966 /* Cast the V4SImode vector back to a vector in orignal mode. */
40970 /* Load even elements into the second position. */
40974 const1_rtx));
40976 /* Cast vector to FIRST_IMODE vector. */
40979 }
40981 /* Interleave low FIRST_IMODE vectors. */
40983 {
40987 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
40990 }
40992 /* Interleave low SECOND_IMODE vectors. */
40994 {
40997 {
41002 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
41003 vector. */
41006 }
41009 /* FALLTHRU */
41016 /* Cast the SECOND_IMODE vector back to a vector on original
41017 mode. */
41024 }
41025 }
41027 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
41028 all values variable, and none identical. */
41030 static void
41033 {
41039 {
41044 /* FALLTHRU */
41072 half:
41089 /* FALLTHRU */
41095 /* Don't use ix86_expand_vector_init_interleave if we can't
41096 move from GPR to SSE register directly. */
41112 }
41114 {
41126 {
41130 {
41136 else
41137 {
41142 }
41143 }
41146 }
41151 {
41157 }
41159 {
41165 }
41166 else
41168 }
41169 }
41171 /* Initialize vector TARGET via VALS. Suppress the use of MMX
41172 instructions unless MMX_OK is true. */
41174 void
41176 {
41183 rtx x;
41186 {
41196 }
41198 /* Constants are best loaded from the constant pool. */
41200 {
41203 }
41205 /* If all values are identical, broadcast the value. */
41211 /* Values where only one field is non-constant are best loaded from
41212 the pool and overwritten via move later. */
41214 {
41218 one_var))
41223 }
41226 }
41228 void
41230 {
41235 rtx tmp;
41237 = {
41244 };
41246 = {
41253 };
41257 {
41261 {
41266 else
41270 }
41282 else
41288 {
41291 /* For the two element vectors, we implement a VEC_CONCAT with
41292 the extraction of the other element. */
41299 else
41304 }
41313 {
41319 /* tmp = target = A B C D */
41321 /* target = A A B B */
41323 /* target = X A B B */
41325 /* target = A X C D */
41332 /* tmp = target = A B C D */
41334 /* tmp = X B C D */
41336 /* target = A B X D */
41343 /* tmp = target = A B C D */
41345 /* tmp = X B C D */
41347 /* target = A B X D */
41355 }
41363 /* Element 0 handled by vec_merge below. */
41365 {
41368 }
41371 {
41372 /* With SSE2, use integer shuffles to swap element 0 and ELT,
41373 store into element 0, then shuffle them back. */
41390 }
41391 else
41392 {
41393 /* For SSE1, we have to reuse the V4SF code. */
41397 }
41450 half:
41451 /* Compute offset. */
41457 /* Extract the half. */
41461 /* Put val in tmp at elt. */
41464 /* Put it back. */
41470 }
41473 {
41477 }
41478 else
41479 {
41488 }
41489 }
41491 void
41493 {
41497 rtx tmp;
41500 {
41505 /* FALLTHRU */
41518 {
41538 }
41550 {
41552 {
41572 }
41576 }
41577 else
41578 {
41579 /* For SSE1, we have to reuse the V4SF code. */
41583 }
41599 {
41603 else
41607 }
41612 {
41616 else
41620 }
41625 {
41629 else
41633 }
41638 {
41642 else
41646 }
41651 {
41655 else
41659 }
41664 {
41668 else
41672 }
41679 else
41688 else
41697 else
41706 else
41712 /* ??? Could extract the appropriate HImode element and shift. */
41715 }
41718 {
41722 /* Let the rtl optimizers know about the zero extension performed. */
41724 {
41727 }
41730 }
41731 else
41732 {
41739 }
41740 }
41742 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
41743 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
41744 The upper bits of DEST are undefined, though they shouldn't cause
41745 exceptions (some bits from src or all zeros are ok). */
41747 static void
41749 {
41752 {
41756 else
41774 else
41781 else
41789 {
41794 const1_rtx);
41795 }
41796 else
41797 {
41801 }
41821 else
41843 }
41847 }
41849 /* Expand a vector reduction. FN is the binary pattern to reduce;
41850 DEST is the destination; IN is the input vector. */
41852 void
41854 {
41859 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
41863 {
41866 }
41871 {
41876 else
41880 }
41881 }
41882 \f
41883 /* Target hook for scalar_mode_supported_p. */
41884 static bool
41886 {
41891 else
41893 }
41895 /* Implements target hook vector_mode_supported_p. */
41896 static bool
41898 {
41912 }
41914 /* Target hook for c_mode_for_suffix. */
41915 static enum machine_mode
41917 {
41924 }
41926 /* Worker function for TARGET_MD_ASM_CLOBBERS.
41928 We do this in the new i386 backend to maintain source compatibility
41929 with the old cc0-based compiler. */
41931 static tree
41933 tree inputs ATTRIBUTE_UNUSED,
41934 tree clobbers)
41935 {
41937 clobbers);
41939 clobbers);
41941 }
41943 /* Implements target vector targetm.asm.encode_section_info. */
41945 static void ATTRIBUTE_UNUSED
41947 {
41954 }
41956 /* Worker function for REVERSE_CONDITION. */
41958 enum rtx_code
41960 {
41964 }
41966 /* Output code to perform an x87 FP register move, from OPERANDS[1]
41967 to OPERANDS[0]. */
41971 {
41973 {
41976 {
41980 }
41984 }
41986 {
41990 else
41991 {
41992 /* There is no non-popping store to memory for XFmode.
41993 So if we need one, follow the store with a load. */
41996 else
41998 }
41999 }
42000 else
42002 }
42004 /* Output code to perform a conditional jump to LABEL, if C2 flag in
42005 FP status register is set. */
42007 void
42009 {
42011 rtx temp;
42016 {
42021 }
42022 else
42023 {
42028 }
42032 pc_rtx);
42037 }
42039 /* Output code to perform a log1p XFmode calculation. */
42042 {
42048 rtx test;
42054 XFmode));
42068 }
42070 /* Emit code for round calculation. */
42072 {
42079 rtx insn;
42084 {
42096 }
42099 {
42120 }
42128 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
42130 /* scratch = fxam(op1) */
42133 UNSPEC_FXAM)));
42134 /* e1 = fabs(op1) */
42137 /* e2 = e1 + 0.5 */
42142 /* res = floor(e2) */
42144 {
42149 }
42150 else
42154 {
42157 {
42164 UNSPEC_TRUNC_NOOP)));
42165 }
42181 }
42183 /* flags = signbit(a) */
42186 /* if (flags) then res = -res */
42190 pc_rtx);
42201 }
42203 /* Output code to perform a Newton-Rhapson approximation of a single precision
42204 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
42207 {
42215 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
42219 /* x0 = rcp(b) estimate */
42223 UNSPEC_RCP14)));
42224 else
42227 UNSPEC_RCP)));
42229 /* e0 = x0 * b */
42233 /* e0 = x0 * e0 */
42237 /* e1 = x0 + x0 */
42241 /* x1 = e1 - e0 */
42245 /* res = a * x1 */
42248 }
42250 /* Output code to perform a Newton-Rhapson approximation of a
42251 single precision floating point [reciprocal] square root. */
42255 {
42257 REAL_VALUE_TYPE r;
42274 {
42277 /* There is no 512-bit rsqrt. There is however rsqrt14. */
42280 }
42282 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
42283 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
42287 /* x0 = rsqrt(a) estimate */
42290 unspec)));
42292 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
42294 {
42302 /* Handle masked compare. */
42304 {
42306 /* Imm value 0x4 corresponds to not-equal comparison. */
42309 }
42310 else
42311 {
42317 }
42318 }
42320 /* e0 = x0 * a */
42323 /* e1 = e0 * x0 */
42327 /* e2 = e1 - 3. */
42334 /* e3 = -.5 * x0 */
42337 else
42338 /* e3 = -.5 * e0 */
42341 /* ret = e2 * e3 */
42344 }
42346 #ifdef TARGET_SOLARIS
42347 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
42349 static void
42351 tree decl)
42352 {
42353 /* With Binutils 2.15, the "@unwind" marker must be specified on
42354 every occurrence of the ".eh_frame" section, not just the first
42355 one. */
42358 {
42362 }
42364 #ifndef USE_GAS
42366 {
42369 }
42370 #endif
42373 }
42376 /* Return the mangling of TYPE if it is an extended fundamental type. */
42380 {
42388 {
42390 /* __float128 is "g". */
42393 /* "long double" or __float80 is "e". */
42397 }
42398 }
42400 /* For 32-bit code we can save PIC register setup by using
42401 __stack_chk_fail_local hidden function instead of calling
42402 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
42403 register, so it is better to call __stack_chk_fail directly. */
42405 static tree ATTRIBUTE_UNUSED
42407 {
42408 return TARGET_64BIT
42411 }
42413 /* Select a format to encode pointers in exception handling data. CODE
42414 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
42415 true if the symbol may be affected by dynamic relocations.
42417 ??? All x86 object file formats are capable of representing this.
42418 After all, the relocation needed is the same as for the call insn.
42419 Whether or not a particular assembler allows us to enter such, I
42420 guess we'll have to see. */
42421 int
42423 {
42425 {
42432 }
42437 }
42438 \f
42439 /* Expand copysign from SIGN to the positive value ABS_VALUE
42440 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
42441 the sign-bit. */
42442 static void
42444 {
42448 {
42455 else
42460 {
42461 /* We need to generate a scalar mode mask in this case. */
42466 }
42467 }
42468 else
42474 }
42476 /* Expand fabs (OP0) and return a new rtx that holds the result. The
42477 mask for masking out the sign-bit is stored in *SMASK, if that is
42478 non-null. */
42479 static rtx
42481 {
42490 else
42494 {
42495 /* We need to generate a scalar mode mask in this case. */
42500 }
42508 }
42510 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
42511 swapping the operands if SWAP_OPERANDS is true. The expanded
42512 code is a forward jump to a newly created label in case the
42513 comparison is true. The generated label rtx is returned. */
42514 static rtx
42517 {
42522 {
42526 }
42539 }
42541 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
42542 using comparison code CODE. Operands are swapped for the comparison if
42543 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
42544 static rtx
42547 {
42553 {
42557 }
42564 }
42566 /* Generate and return a rtx of mode MODE for 2**n where n is the number
42567 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
42568 static rtx
42570 {
42571 REAL_VALUE_TYPE TWO52r;
42572 rtx TWO52;
42579 }
42581 /* Expand SSE sequence for computing lround from OP1 storing
42582 into OP0. */
42583 void
42585 {
42586 /* C code for the stuff we're doing below:
42587 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
42588 return (long)tmp;
42589 */
42593 rtx adj;
42595 /* load nextafter (0.5, 0.0) */
42600 /* adj = copysign (0.5, op1) */
42604 /* adj = op1 + adj */
42607 /* op0 = (imode)adj */
42609 }
42611 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
42612 into OPERAND0. */
42613 void
42615 {
42616 /* C code for the stuff we're doing below (for do_floor):
42617 xi = (long)op1;
42618 xi -= (double)xi > op1 ? 1 : 0;
42619 return xi;
42620 */
42625 /* reg = (long)op1 */
42629 /* freg = (double)reg */
42633 /* ireg = (freg > op1) ? ireg - 1 : ireg */
42644 }
42646 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
42647 result in OPERAND0. */
42648 void
42650 {
42651 /* C code for the stuff we're doing below:
42652 xa = fabs (operand1);
42653 if (!isless (xa, 2**52))
42654 return operand1;
42655 xa = xa + 2**52 - 2**52;
42656 return copysign (xa, operand1);
42657 */
42664 /* xa = abs (operand1) */
42667 /* if (!isless (xa, TWO52)) goto label; */
42680 }
42682 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42683 into OPERAND0. */
42684 void
42686 {
42687 /* C code for the stuff we expand below.
42688 double xa = fabs (x), x2;
42689 if (!isless (xa, TWO52))
42690 return x;
42691 xa = xa + TWO52 - TWO52;
42692 x2 = copysign (xa, x);
42693 Compensate. Floor:
42694 if (x2 > x)
42695 x2 -= 1;
42696 Compensate. Ceil:
42697 if (x2 < x)
42698 x2 -= -1;
42699 return x2;
42700 */
42706 /* Temporary for holding the result, initialized to the input
42707 operand to ease control flow. */
42711 /* xa = abs (operand1) */
42714 /* if (!isless (xa, TWO52)) goto label; */
42717 /* xa = xa + TWO52 - TWO52; */
42721 /* xa = copysign (xa, operand1) */
42724 /* generate 1.0 or -1.0 */
42729 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42733 /* We always need to subtract here to preserve signed zero. */
42742 }
42744 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
42745 into OPERAND0. */
42746 void
42748 {
42749 /* C code for the stuff we expand below.
42750 double xa = fabs (x), x2;
42751 if (!isless (xa, TWO52))
42752 return x;
42753 x2 = (double)(long)x;
42754 Compensate. Floor:
42755 if (x2 > x)
42756 x2 -= 1;
42757 Compensate. Ceil:
42758 if (x2 < x)
42759 x2 += 1;
42760 if (HONOR_SIGNED_ZEROS (mode))
42761 return copysign (x2, x);
42762 return x2;
42763 */
42769 /* Temporary for holding the result, initialized to the input
42770 operand to ease control flow. */
42774 /* xa = abs (operand1) */
42777 /* if (!isless (xa, TWO52)) goto label; */
42780 /* xa = (double)(long)x */
42785 /* generate 1.0 */
42788 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
42803 }
42805 /* Expand SSE sequence for computing round from OPERAND1 storing
42806 into OPERAND0. Sequence that works without relying on DImode truncation
42807 via cvttsd2siq that is only available on 64bit targets. */
42808 void
42810 {
42811 /* C code for the stuff we expand below.
42812 double xa = fabs (x), xa2, x2;
42813 if (!isless (xa, TWO52))
42814 return x;
42815 Using the absolute value and copying back sign makes
42816 -0.0 -> -0.0 correct.
42817 xa2 = xa + TWO52 - TWO52;
42818 Compensate.
42819 dxa = xa2 - xa;
42820 if (dxa <= -0.5)
42821 xa2 += 1;
42822 else if (dxa > 0.5)
42823 xa2 -= 1;
42824 x2 = copysign (xa2, x);
42825 return x2;
42826 */
42832 /* Temporary for holding the result, initialized to the input
42833 operand to ease control flow. */
42837 /* xa = abs (operand1) */
42840 /* if (!isless (xa, TWO52)) goto label; */
42843 /* xa2 = xa + TWO52 - TWO52; */
42847 /* dxa = xa2 - xa; */
42850 /* generate 0.5, 1.0 and -0.5 */
42856 /* Compensate. */
42858 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
42863 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
42869 /* res = copysign (xa2, operand1) */
42876 }
42878 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42879 into OPERAND0. */
42880 void
42882 {
42883 /* C code for SSE variant we expand below.
42884 double xa = fabs (x), x2;
42885 if (!isless (xa, TWO52))
42886 return x;
42887 x2 = (double)(long)x;
42888 if (HONOR_SIGNED_ZEROS (mode))
42889 return copysign (x2, x);
42890 return x2;
42891 */
42897 /* Temporary for holding the result, initialized to the input
42898 operand to ease control flow. */
42902 /* xa = abs (operand1) */
42905 /* if (!isless (xa, TWO52)) goto label; */
42908 /* x = (double)(long)x */
42920 }
42922 /* Expand SSE sequence for computing trunc from OPERAND1 storing
42923 into OPERAND0. */
42924 void
42926 {
42930 /* C code for SSE variant we expand below.
42931 double xa = fabs (x), x2;
42932 if (!isless (xa, TWO52))
42933 return x;
42934 xa2 = xa + TWO52 - TWO52;
42935 Compensate:
42936 if (xa2 > xa)
42937 xa2 -= 1.0;
42938 x2 = copysign (xa2, x);
42939 return x2;
42940 */
42944 /* Temporary for holding the result, initialized to the input
42945 operand to ease control flow. */
42949 /* xa = abs (operand1) */
42952 /* if (!isless (xa, TWO52)) goto label; */
42955 /* res = xa + TWO52 - TWO52; */
42960 /* generate 1.0 */
42963 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
42971 /* res = copysign (res, operand1) */
42978 }
42980 /* Expand SSE sequence for computing round from OPERAND1 storing
42981 into OPERAND0. */
42982 void
42984 {
42985 /* C code for the stuff we're doing below:
42986 double xa = fabs (x);
42987 if (!isless (xa, TWO52))
42988 return x;
42989 xa = (double)(long)(xa + nextafter (0.5, 0.0));
42990 return copysign (xa, x);
42991 */
42997 /* Temporary for holding the result, initialized to the input
42998 operand to ease control flow. */
43006 /* load nextafter (0.5, 0.0) */
43011 /* xa = xa + 0.5 */
43015 /* xa = (double)(int64_t)xa */
43020 /* res = copysign (xa, operand1) */
43027 }
43029 /* Expand SSE sequence for computing round
43030 from OP1 storing into OP0 using sse4 round insn. */
43031 void
43033 {
43042 {
43053 }
43055 /* round (a) = trunc (a + copysign (0.5, a)) */
43057 /* load nextafter (0.5, 0.0) */
43063 /* e1 = copysign (0.5, op1) */
43067 /* e2 = op1 + e1 */
43070 /* res = trunc (e2) */
43075 }
43076 \f
43078 /* Table of valid machine attributes. */
43080 {
43081 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
43082 affects_type_identity } */
43083 /* Stdcall attribute says callee is responsible for popping arguments
43084 if they are not variable. */
43087 /* Fastcall attribute says callee is responsible for popping arguments
43088 if they are not variable. */
43091 /* Thiscall attribute says callee is responsible for popping arguments
43092 if they are not variable. */
43095 /* Cdecl attribute says the callee is a normal C declaration */
43098 /* Regparm attribute specifies how many integer arguments are to be
43099 passed in registers. */
43102 /* Sseregparm attribute says we are using x86_64 calling conventions
43103 for FP arguments. */
43106 /* The transactional memory builtins are implicitly regparm or fastcall
43107 depending on the ABI. Override the generic do-nothing attribute that
43108 these builtins were declared with. */
43111 /* force_align_arg_pointer says this function realigns the stack at entry. */
43114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
43119 #endif
43124 #ifdef SUBTARGET_ATTRIBUTE_TABLE
43125 SUBTARGET_ATTRIBUTE_TABLE,
43126 #endif
43127 /* ms_abi and sysv_abi calling convention function attributes. */
43134 /* End element. */
43136 };
43138 /* Implement targetm.vectorize.builtin_vectorization_cost. */
43139 static int
43141 tree vectype,
43143 {
43147 {
43192 }
43193 }
43195 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
43196 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
43197 insn every time. */
43201 /* Initialize vselect_insn. */
43203 static void
43205 {
43207 rtx x;
43218 }
43220 /* Construct (set target (vec_select op0 (parallel perm))) and
43221 return true if that's a valid instruction in the active ISA. */
43223 static bool
43226 {
43252 }
43254 /* Similar, but generate a vec_concat from op0 and op1 as well. */
43256 static bool
43260 {
43262 rtx x;
43277 }
43279 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43280 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
43282 static bool
43284 {
43293 ;
43295 ;
43297 ;
43298 else
43301 /* This is a blend, not a permute. Elements must stay in their
43302 respective lanes. */
43304 {
43308 }
43313 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
43314 decision should be extracted elsewhere, so that we only try that
43315 sequence once all budget==3 options have been tried. */
43322 {
43346 /* See if bytes move in pairs so we can use pblendw with
43347 an immediate argument, rather than pblendvb with a vector
43348 argument. */
43351 {
43352 use_pblendvb:
43356 finish_pblendvb:
43362 else
43367 }
43372 /* FALLTHRU */
43374 do_subreg:
43381 /* See if bytes move in pairs. If not, vpblendvb must be used. */
43385 /* See if bytes move in quadruplets. If yes, vpblendd
43386 with immediate can be used. */
43391 {
43392 /* See if bytes move the same in both lanes. If yes,
43393 vpblendw with immediate can be used. */
43398 /* Use vpblendw. */
43403 }
43405 /* Use vpblendd. */
43412 /* See if words move in pairs. If yes, vpblendd can be used. */
43417 {
43418 /* See if words move the same in both lanes. If not,
43419 vpblendvb must be used. */
43422 {
43423 /* Use vpblendvb. */
43433 }
43435 /* Use vpblendw. */
43439 }
43441 /* Use vpblendd. */
43448 /* Use vpblendd. */
43456 }
43458 /* This matches five different patterns with the different modes. */
43466 }
43468 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43469 in terms of the variable form of vpermilps.
43471 Note that we will have already failed the immediate input vpermilps,
43472 which requires that the high and low part shuffle be identical; the
43473 variable form doesn't require that. */
43475 static bool
43477 {
43484 /* We can only permute within the 128-bit lane. */
43486 {
43490 }
43496 {
43499 /* Within each 128-bit lane, the elements of op0 are numbered
43500 from 0 and the elements of op1 are numbered from 4. */
43507 }
43514 }
43516 /* Return true if permutation D can be performed as VMODE permutation
43517 instead. */
43519 static bool
43521 {
43536 else
43542 }
43544 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43545 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
43547 static bool
43549 {
43558 {
43560 {
43563 {
43567 /* Use vperm2i128 insn. The pattern uses
43568 V4DImode instead of V2TImode. */
43581 }
43583 }
43584 }
43585 else
43586 {
43588 {
43591 }
43593 {
43597 /* V4DImode should be already handled through
43598 expand_vselect by vpermq instruction. */
43605 {
43606 /* First see if vpermq can be used for
43607 V8SImode/V16HImode/V32QImode. */
43609 {
43617 {
43621 }
43623 }
43625 /* Next see if vpermd can be used. */
43628 }
43629 /* Or if vpermps can be used. */
43634 {
43635 /* vpshufb only works intra lanes, it is not
43636 possible to shuffle bytes in between the lanes. */
43640 }
43641 }
43642 else
43644 }
43652 else
43653 {
43659 else
43663 {
43667 }
43668 }
43679 {
43686 else
43688 }
43689 else
43690 {
43693 }
43698 }
43700 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
43701 in a single instruction. */
43703 static bool
43705 {
43709 /* Check plain VEC_SELECT first, because AVX has instructions that could
43710 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
43711 input where SEL+CONCAT may not. */
43713 {
43719 {
43725 }
43728 {
43732 }
43734 {
43735 /* Use vpbroadcast{b,w,d}. */
43738 {
43757 /* For other modes prefer other shuffles this function creates. */
43759 }
43761 {
43765 }
43766 }
43771 /* There are plenty of patterns in sse.md that are written for
43772 SEL+CONCAT and are not replicated for a single op. Perhaps
43773 that should be changed, to avoid the nastiness here. */
43775 /* Recognize interleave style patterns, which means incrementing
43776 every other permutation operand. */
43778 {
43781 }
43786 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
43788 {
43790 {
43795 }
43800 }
43801 }
43803 /* Finally, try the fully general two operand permute. */
43808 /* Recognize interleave style patterns with reversed operands. */
43810 {
43812 {
43816 else
43819 }
43824 }
43826 /* Try the SSE4.1 blend variable merge instructions. */
43830 /* Try one of the AVX vpermil variable permutations. */
43834 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
43835 vpshufb, vpermd, vpermps or vpermq variable permutation. */
43839 /* Try the AVX512F vpermi2 instructions. */
43853 }
43855 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
43856 in terms of a pair of pshuflw + pshufhw instructions. */
43858 static bool
43860 {
43868 /* The two permutations only operate in 64-bit lanes. */
43879 /* Emit the pshuflw. */
43886 /* Emit the pshufhw. */
43894 }
43896 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43897 the permutation using the SSSE3 palignr instruction. This succeeds
43898 when all of the elements in PERM fit within one vector and we merely
43899 need to shift them down so that a single vector permutation has a
43900 chance to succeed. */
43902 static bool
43904 {
43911 /* Even with AVX, palignr only operates on 128-bit vectors. */
43917 {
43923 }
43927 /* Given that we have SSSE3, we know we'll be able to implement the
43928 single operand permutation after the palignr with pshufb. */
43943 {
43948 }
43950 /* Test for the degenerate case where the alignment by itself
43951 produces the desired permutation. */
43953 {
43956 }
43962 }
43966 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
43967 a two vector permutation into a single vector permutation by using
43968 an interleave operation to merge the vectors. */
43970 static bool
43972 {
43977 rtx seq;
43981 {
43984 }
43986 {
43989 /* For 32-byte modes allow even d->one_operand_p.
43990 The lack of cross-lane shuffling in some instructions
43991 might prevent a single insn shuffle. */
43994 /* If expand_vec_perm_interleave3 can expand this into
43995 a 3 insn sequence, give up and let it be expanded as
43996 3 insn sequence. While that is one insn longer,
43997 it doesn't need a memory operand and in the common
43998 case that both interleave low and high permutations
43999 with the same operands are adjacent needs 4 insns
44000 for both after CSE. */
44003 }
44004 else
44007 /* Examine from whence the elements come. */
44016 {
44019 /* Split the two input vectors into 4 halves. */
44025 /* If the elements from the low halves use interleave low, and similarly
44026 for interleave high. If the elements are from mis-matched halves, we
44027 can use shufps for V4SF/V4SI or do a DImode shuffle. */
44029 {
44030 /* punpckl* */
44032 {
44037 }
44040 }
44042 {
44043 /* punpckh* */
44045 {
44050 }
44053 }
44055 {
44056 /* shufps */
44058 {
44063 }
44065 {
44066 /* shufpd */
44071 }
44072 }
44074 {
44075 /* shufps */
44077 {
44082 }
44084 {
44085 /* shufpd */
44090 }
44091 }
44092 else
44094 }
44095 else
44096 {
44101 /* Split the two input vectors into 8 quarters. */
44107 {
44110 }
44113 {
44117 }
44119 {
44122 }
44125 {
44127 {
44128 /* Attempt to increase the likelihood that dfinal
44129 shuffle will be intra-lane. */
44133 }
44135 /* vperm2f128 or vperm2i128. */
44137 {
44142 }
44147 {
44151 {
44154 }
44155 }
44156 }
44161 {
44162 /* vpunpckl* */
44164 {
44173 }
44174 }
44177 {
44178 /* vpunpckh* */
44180 {
44189 }
44190 }
44191 else
44193 }
44195 /* Use the remapping array set up above to move the elements from their
44196 swizzled locations into their final destinations. */
44199 {
44202 /* If same_halves is true, both halves of the remapped vector are the
44203 same. Avoid cross-lane accesses if possible. */
44205 {
44208 }
44209 else
44211 }
44213 {
44216 }
44220 /* Test if the final remap can be done with a single insn. For V4SFmode or
44221 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
44234 {
44237 }
44244 }
44246 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
44247 a single vector cross-lane permutation into vpermq followed
44248 by any of the single insn permutations. */
44250 static bool
44252 {
44266 {
44269 }
44272 {
44277 }
44290 {
44297 }
44304 {
44309 ;
44312 else
44314 }
44323 }
44325 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
44326 a vector permutation using two instructions, vperm2f128 resp.
44327 vperm2i128 followed by any single in-lane permutation. */
44329 static bool
44331 {
44345 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
44346 immediate. For perm < 16 the second permutation uses
44347 d->op0 as first operand, for perm >= 16 it uses d->op1
44348 as first operand. The second operand is the result of
44349 vperm2[fi]128. */
44351 {
44352 /* Ignore permutations which do not move anything cross-lane. */
44354 {
44355 /* The second shuffle for e.g. V4DFmode has
44356 0123 and ABCD operands.
44357 Ignore AB23, as 23 is already in the second lane
44358 of the first operand. */
44360 /* And 01CD, as 01 is in the first lane of the first
44361 operand. */
44363 /* And 4567, as then the vperm2[fi]128 doesn't change
44364 anything on the original 4567 second operand. */
44366 }
44367 else
44368 {
44369 /* The second shuffle for e.g. V4DFmode has
44370 4567 and ABCD operands.
44371 Ignore AB67, as 67 is already in the second lane
44372 of the first operand. */
44374 /* And 45CD, as 45 is in the first lane of the first
44375 operand. */
44377 /* And 0123, as then the vperm2[fi]128 doesn't change
44378 anything on the original 0123 first operand. */
44380 }
44383 {
44389 else
44391 }
44394 {
44398 }
44399 else
44403 {
44407 /* Found a usable second shuffle. dfirst will be
44408 vperm2f128 on d->op0 and d->op1. */
44419 /* And dsecond is some single insn shuffle, taking
44420 d->op0 and result of vperm2f128 (if perm < 16) or
44421 d->op1 and result of vperm2f128 (otherwise). */
44430 }
44432 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
44435 }
44438 }
44440 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
44441 a two vector permutation using 2 intra-lane interleave insns
44442 and cross-lane shuffle for 32-byte vectors. */
44444 static bool
44446 {
44453 ;
44455 ;
44456 else
44471 {
44475 else
44481 else
44487 else
44493 else
44499 else
44505 else
44510 }
44514 }
44516 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
44517 a single vector permutation using a single intra-lane vector
44518 permutation, vperm2f128 swapping the lanes and vblend* insn blending
44519 the non-swapped and swapped vectors together. */
44521 static bool
44523 {
44526 rtx seq;
44531 || TARGET_AVX2
44540 {
44547 }
44582 }
44584 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
44585 permutation using two vperm2f128, followed by a vshufpd insn blending
44586 the two vectors together. */
44588 static bool
44590 {
44633 }
44635 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
44636 permutation with two pshufb insns and an ior. We should have already
44637 failed all two instruction sequences. */
44639 static bool
44641 {
44655 /* Generate two permutation masks. If the required element is within
44656 the given vector it is shuffled into the proper lane. If the required
44657 element is in the other vector, force a zero into the lane by setting
44658 bit 7 in the permutation mask. */
44661 {
44668 {
44671 }
44672 }
44696 }
44698 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
44699 with two vpshufb insns, vpermq and vpor. We should have already failed
44700 all two or three instruction sequences. */
44702 static bool
44704 {
44719 /* Generate two permutation masks. If the required element is within
44720 the same lane, it is shuffled in. If the required element from the
44721 other lane, force a zero by setting bit 7 in the permutation mask.
44722 In the other mask the mask has non-negative elements if element
44723 is requested from the other lane, but also moved to the other lane,
44724 so that the result of vpshufb can have the two V2TImode halves
44725 swapped. */
44728 {
44733 {
44736 }
44737 }
44746 /* Swap the 128-byte lanes of h into hp. */
44750 const1_rtx));
44767 }
44769 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
44770 and extract-odd permutations of two V32QImode and V16QImode operand
44771 with two vpshufb insns, vpor and vpermq. We should have already
44772 failed all two or three instruction sequences. */
44774 static bool
44776 {
44795 /* Generate two permutation masks. In the first permutation mask
44796 the first quarter will contain indexes for the first half
44797 of the op0, the second quarter will contain bit 7 set, third quarter
44798 will contain indexes for the second half of the op0 and the
44799 last quarter bit 7 set. In the second permutation mask
44800 the first quarter will contain bit 7 set, the second quarter
44801 indexes for the first half of the op1, the third quarter bit 7 set
44802 and last quarter indexes for the second half of the op1.
44803 I.e. the first mask e.g. for V32QImode extract even will be:
44804 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
44805 (all values masked with 0xf except for -128) and second mask
44806 for extract even will be
44807 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
44810 {
44816 {
44819 }
44820 }
44839 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
44847 }
44849 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
44850 and extract-odd permutations. */
44852 static bool
44854 {
44858 {
44865 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
44869 /* Now an unpck[lh]pd will produce the result required. */
44872 else
44878 {
44887 /* Shuffle within the 128-bit lanes to produce:
44888 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
44892 /* Shuffle the lanes around to produce:
44893 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
44897 /* Shuffle within the 128-bit lanes to produce:
44898 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
44901 /* Shuffle within the 128-bit lanes to produce:
44902 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
44905 /* Shuffle the lanes around to produce:
44906 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
44909 }
44916 /* These are always directly implementable by expand_vec_perm_1. */
44922 else
44923 {
44926 /* We need 2*log2(N)-1 operations to achieve odd/even
44927 with interleave. */
44936 else
44939 }
44945 else
44946 {
44960 else
44963 }
44972 {
44977 else
44982 {
44987 }
44989 }
44997 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
45001 /* Now an vpunpck[lh]qdq will produce the result required. */
45004 else
45011 {
45016 else
45021 {
45026 }
45028 }
45039 /* Shuffle the lanes around into
45040 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
45048 /* Swap the 2nd and 3rd position in each lane into
45049 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
45055 /* Now an vpunpck[lh]qdq will produce
45056 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
45060 else
45069 }
45072 }
45074 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
45075 extract-even and extract-odd permutations. */
45077 static bool
45079 {
45091 }
45093 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
45094 permutations. We assume that expand_vec_perm_1 has already failed. */
45096 static bool
45098 {
45106 {
45109 /* These are special-cased in sse.md so that we can optionally
45110 use the vbroadcast instruction. They expand to two insns
45111 if the input happens to be in a register. */
45118 /* These are always implementable using standard shuffle patterns. */
45123 /* These can be implemented via interleave. We save one insn by
45124 stopping once we have promoted to V4SImode and then use pshufd. */
45127 do
45128 {
45129 rtx dest;
45135 {
45139 }
45146 }
45161 /* For AVX2 broadcasts of the first element vpbroadcast* or
45162 vpermq should be used by expand_vec_perm_1. */
45168 }
45169 }
45171 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
45172 broadcast permutations. */
45174 static bool
45176 {
45188 }
45190 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
45191 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
45192 all the shorter instruction sequences. */
45194 static bool
45196 {
45212 /* Generate 4 permutation masks. If the required element is within
45213 the same lane, it is shuffled in. If the required element from the
45214 other lane, force a zero by setting bit 7 in the permutation mask.
45215 In the other mask the mask has non-negative elements if element
45216 is requested from the other lane, but also moved to the other lane,
45217 so that the result of vpshufb can have the two V2TImode halves
45218 swapped. */
45221 {
45226 }
45232 {
45240 }
45243 {
45245 {
45248 }
45255 }
45257 /* Swap the 128-byte lanes of h[X]. */
45259 {
45265 const1_rtx));
45267 }
45270 {
45272 {
45275 }
45281 }
45284 {
45286 {
45290 }
45293 }
45303 }
45305 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
45306 With all of the interface bits taken care of, perform the expansion
45307 in D and return true on success. */
45309 static bool
45311 {
45312 /* Try a single instruction expansion. */
45316 /* Try sequences of two instructions. */
45336 /* Try sequences of three instructions. */
45350 /* Try sequences of four instructions. */
45358 /* ??? Look for narrow permutations whose element orderings would
45359 allow the promotion to a wider mode. */
45361 /* ??? Look for sequences of interleave or a wider permute that place
45362 the data into the correct lanes for a half-vector shuffle like
45363 pshuf[lh]w or vpermilps. */
45365 /* ??? Look for sequences of interleave that produce the desired results.
45366 The combinatorics of punpck[lh] get pretty ugly... */
45371 /* Even longer sequences. */
45376 }
45378 /* If a permutation only uses one operand, make it clear. Returns true
45379 if the permutation references both operands. */
45381 static bool
45383 {
45391 {
45397 {
45400 }
45401 /* The elements of PERM do not suggest that only the first operand
45402 is used, but both operands are identical. Allow easier matching
45403 of the permutation by folding the permutation into the single
45404 input vector. */
45405 /* FALLTHRU */
45416 }
45419 }
45421 bool
45423 {
45428 rtx sel;
45445 {
45450 }
45457 /* If the selector says both arguments are needed, but the operands are the
45458 same, the above tried to expand with one_operand_p and flattened selector.
45459 If that didn't work, retry without one_operand_p; we succeeded with that
45460 during testing. */
45462 {
45466 }
45469 }
45471 /* Implement targetm.vectorize.vec_perm_const_ok. */
45473 static bool
45476 {
45485 /* Given sufficient ISA support we can just return true here
45486 for selected vector modes. */
45489 /* All implementable with a single vpermi2 insn. */
45492 {
45493 /* All implementable with a single vpperm insn. */
45496 /* All implementable with 2 pshufb + 1 ior. */
45499 /* All implementable with shufpd or unpck[lh]pd. */
45502 }
45504 /* Extract the values from the vector CST into the permutation
45505 array in D. */
45508 {
45512 }
45514 /* For all elements from second vector, fold the elements to first. */
45519 /* Check whether the mask can be applied to the vector type. */
45522 /* Implementable with shufps or pshufd. */
45526 /* Otherwise we have to go through the motions and see if we can
45527 figure out how to generate the requested permutation. */
45538 }
45540 void
45542 {
45557 /* We'll either be able to implement the permutation directly... */
45561 /* ... or we use the special-case patterns. */
45563 }
45565 static void
45567 {
45582 {
45585 }
45587 /* Note that for AVX this isn't one instruction. */
45590 }
45593 /* Expand a vector operation CODE for a V*QImode in terms of the
45594 same operation on V*HImode. */
45596 void
45598 {
45610 {
45623 }
45627 {
45629 /* Unpack data such that we've got a source byte in each low byte of
45630 each word. We don't care what goes into the high byte of each word.
45631 Rather than trying to get zero in there, most convenient is to let
45632 it be a copy of the low byte. */
45637 /* FALLTHRU */
45649 /* FALLTHRU */
45659 }
45661 /* Perform the operation. */
45668 /* Merge the data back into the right place. */
45678 {
45679 /* For SSE2, we used an full interleave, so the desired
45680 results are in the even elements. */
45683 }
45684 else
45685 {
45686 /* For AVX, the interleave used above was not cross-lane. So the
45687 extraction is evens but with the second and third quarter swapped.
45688 Happily, that is even one insn shorter than even extraction. */
45691 }
45698 }
45700 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
45701 if op is CONST_VECTOR with all odd elements equal to their
45702 preceding element. */
45704 static bool
45706 {
45716 }
45718 void
45721 {
45724 rtx x;
45732 /* We only play even/odd games with vectors of SImode. */
45735 /* If we're looking for the odd results, shift those members down to
45736 the even slots. For some cpus this is faster than a PSHUFD. */
45738 {
45739 /* For XOP use vpmacsdqh, but only for smult, as it is only
45740 signed. */
45742 {
45746 }
45757 }
45760 {
45763 else
45765 }
45767 {
45770 else
45772 }
45777 else
45778 {
45781 /* The easiest way to implement this without PMULDQ is to go through
45782 the motions as if we are performing a full 64-bit multiply. With
45783 the exception that we need to do less shuffling of the elements. */
45785 /* Compute the sign-extension, aka highparts, of the two operands. */
45791 /* Multiply LO(A) * HI(B), and vice-versa. */
45797 /* Multiply LO(A) * LO(B). */
45801 /* Combine and shift the highparts into place. */
45806 /* Combine high and low parts. */
45809 }
45811 }
45813 void
45816 {
45822 {
45827 {
45828 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
45829 shuffle the elements once so that all elements are in the right
45830 place for immediate use: { A C B D }. */
45835 }
45836 else
45837 {
45838 /* Put the elements into place for the multiply. */
45842 }
45847 /* Shuffle the elements between the lanes. After this we
45848 have { A B E F | C D G H } for each operand. */
45858 /* Shuffle the elements within the lanes. After this we
45859 have { A A B B | C C D D } or { E E F F | G G H H }. */
45897 }
45898 }
45900 void
45902 {
45912 /* Move the results in element 2 down to element 1; we don't care
45913 what goes in elements 2 and 3. Then we can merge the parts
45914 back together with an interleave.
45916 Note that two other sequences were tried:
45917 (1) Use interleaves at the start instead of psrldq, which allows
45918 us to use a single shufps to merge things back at the end.
45919 (2) Use shufps here to combine the two vectors, then pshufd to
45920 put the elements in the correct order.
45921 In both cases the cost of the reformatting stall was too high
45922 and the overall sequence slower. */
45933 }
45935 void
45937 {
45942 {
45943 /* op1: A,B,C,D, op2: E,F,G,H */
45952 /* t1: B,A,D,C */
45959 /* t2: (B*E),(A*F),(D*G),(C*H) */
45962 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
45965 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
45968 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
45970 }
45971 else
45972 {
45977 {
45980 }
45982 {
45985 }
45987 {
45990 }
45991 else
45995 /* Multiply low parts. */
45999 /* Shift input vectors right 32 bits so we can multiply high parts. */
46004 /* Multiply high parts by low parts. */
46010 /* Combine and shift the highparts back. */
46014 /* Combine high and low parts. */
46016 }
46020 }
46022 /* Return 1 if control tansfer instruction INSN
46023 should be encoded with bnd prefix.
46024 If insn is NULL then return 1 when control
46025 transfer instructions should be prefixed with
46026 bnd by default for current function. */
46028 bool
46030 {
46031 /* For call insns check special flag. */
46033 {
46037 }
46039 /* All other insns are prefixed only if function is instrumented. */
46041 }
46043 /* Calculate integer abs() using only SSE2 instructions. */
46045 void
46047 {
46052 {
46053 /* For 32-bit signed integer X, the best way to calculate the absolute
46054 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
46066 /* For 16-bit signed integer X, the best way to calculate the absolute
46067 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
46075 /* For 8-bit signed integer X, the best way to calculate the absolute
46076 value of X is min ((unsigned char) X, (unsigned char) (-X)),
46077 as SSE2 provides the PMINUB insn. */
46087 }
46091 }
46093 /* Expand an insert into a vector register through pinsr insn.
46094 Return true if successful. */
46096 bool
46098 {
46106 {
46109 }
46115 {
46120 {
46127 {
46159 }
46173 }
46177 }
46178 }
46179 \f
46180 /* This function returns the calling abi specific va_list type node.
46181 It returns the FNDECL specific va_list type. */
46183 static tree
46185 {
46192 else
46194 }
46196 /* This function returns size of bounds for the calling abi
46197 specific va_list node. */
46199 static tree
46201 {
46208 else
46210 }
46212 /* Returns the canonical va_list type specified by TYPE. If there
46213 is no valid TYPE provided, it return NULL_TREE. */
46215 static tree
46217 {
46220 /* Resolve references and pointers to va_list type. */
46229 {
46234 {
46235 /* If va_list is an array type, the argument may have decayed
46236 to a pointer type, e.g. by being passed to another function.
46237 In that case, unwrap both types so that we can compare the
46238 underlying records. */
46241 {
46244 }
46245 }
46252 {
46253 /* If va_list is an array type, the argument may have decayed
46254 to a pointer type, e.g. by being passed to another function.
46255 In that case, unwrap both types so that we can compare the
46256 underlying records. */
46259 {
46262 }
46263 }
46270 {
46271 /* If va_list is an array type, the argument may have decayed
46272 to a pointer type, e.g. by being passed to another function.
46273 In that case, unwrap both types so that we can compare the
46274 underlying records. */
46277 {
46280 }
46281 }
46285 }
46287 }
46289 /* Iterate through the target-specific builtin types for va_list.
46290 IDX denotes the iterator, *PTREE is set to the result type of
46291 the va_list builtin, and *PNAME to its internal type.
46292 Returns zero if there is no element for this index, otherwise
46293 IDX should be increased upon the next call.
46294 Note, do not iterate a base builtin's name like __builtin_va_list.
46295 Used from c_common_nodes_and_builtins. */
46297 static int
46299 {
46301 {
46303 {
46316 }
46317 }
46320 }
46322 #undef TARGET_SCHED_DISPATCH
46323 #define TARGET_SCHED_DISPATCH has_dispatch
46324 #undef TARGET_SCHED_DISPATCH_DO
46325 #define TARGET_SCHED_DISPATCH_DO do_dispatch
46326 #undef TARGET_SCHED_REASSOCIATION_WIDTH
46327 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
46328 #undef TARGET_SCHED_REORDER
46329 #define TARGET_SCHED_REORDER ix86_sched_reorder
46330 #undef TARGET_SCHED_ADJUST_PRIORITY
46331 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
46332 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
46333 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
46334 ix86_dependencies_evaluation_hook
46336 /* The size of the dispatch window is the total number of bytes of
46337 object code allowed in a window. */
46338 #define DISPATCH_WINDOW_SIZE 16
46340 /* Number of dispatch windows considered for scheduling. */
46341 #define MAX_DISPATCH_WINDOWS 3
46343 /* Maximum number of instructions in a window. */
46344 #define MAX_INSN 4
46346 /* Maximum number of immediate operands in a window. */
46347 #define MAX_IMM 4
46349 /* Maximum number of immediate bits allowed in a window. */
46350 #define MAX_IMM_SIZE 128
46352 /* Maximum number of 32 bit immediates allowed in a window. */
46353 #define MAX_IMM_32 4
46355 /* Maximum number of 64 bit immediates allowed in a window. */
46356 #define MAX_IMM_64 2
46358 /* Maximum total of loads or prefetches allowed in a window. */
46359 #define MAX_LOAD 2
46361 /* Maximum total of stores allowed in a window. */
46362 #define MAX_STORE 1
46364 #undef BIG
46365 #define BIG 100
46368 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
46371 disp_load,
46372 disp_store,
46373 disp_load_store,
46374 disp_prefetch,
46375 disp_imm,
46376 disp_imm_32,
46377 disp_imm_64,
46378 disp_branch,
46379 disp_cmp,
46380 disp_jcc,
46381 disp_last
46382 };
46384 /* Number of allowable groups in a dispatch window. It is an array
46385 indexed by dispatch_group enum. 100 is used as a big number,
46386 because the number of these kind of operations does not have any
46387 effect in dispatch window, but we need them for other reasons in
46388 the table. */
46391 };
46397 };
46399 /* Instruction path. */
46405 last_path
46406 };
46408 /* sched_insn_info defines a window to the instructions scheduled in
46409 the basic block. It contains a pointer to the insn_info table and
46410 the instruction scheduled.
46412 Windows are allocated for each basic block and are linked
46413 together. */
46415 rtx insn;
46422 /* Linked list of dispatch windows. This is a two way list of
46423 dispatch windows of a basic block. It contains information about
46424 the number of uops in the window and the total number of
46425 instructions and of bytes in the object code for this dispatch
46426 window. */
46444 /* Immediate valuse used in an insn. */
46446 {
46455 /* Get dispatch group of insn. */
46457 static enum dispatch_group
46459 {
46475 }
46477 /* Return true if insn is a compare instruction. */
46479 static bool
46481 {
46489 }
46491 /* Return true if a dispatch violation encountered. */
46493 static bool
46495 {
46499 }
46501 /* Return true if insn is a branch instruction. */
46503 static bool
46505 {
46507 }
46509 /* Return true if insn is a prefetch instruction. */
46511 static bool
46513 {
46515 }
46517 /* This function initializes a dispatch window and the list container holding a
46518 pointer to the window. */
46520 static void
46522 {
46528 else
46546 {
46552 }
46554 }
46556 /* This function allocates and initializes a dispatch window and the
46557 list container holding a pointer to the window. */
46561 {
46566 }
46568 /* This routine initializes the dispatch scheduling information. It
46569 initiates building dispatch scheduler tables and constructs the
46570 first dispatch window. */
46572 static void
46574 {
46575 /* Allocate a dispatch list and a window. */
46580 }
46582 /* This function returns true if a branch is detected. End of a basic block
46583 does not have to be a branch, but here we assume only branches end a
46584 window. */
46586 static bool
46588 {
46590 }
46592 /* This function is called when the end of a window processing is reached. */
46594 static void
46596 {
46599 {
46604 }
46606 }
46608 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
46609 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
46610 for 48 bytes of instructions. Note that these windows are not dispatch
46611 windows that their sizes are DISPATCH_WINDOW_SIZE. */
46615 {
46617 {
46622 }
46628 }
46630 /* Increment the number of immediate operands of an instruction. */
46632 static int
46634 {
46639 {
46646 else
46657 {
46660 }
46665 }
46668 }
46670 /* Compute number of immediate operands of an instruction. */
46672 static void
46674 {
46677 }
46679 /* Return total size of immediate operands of an instruction along with number
46680 of corresponding immediate-operands. It initializes its parameters to zero
46681 befor calling FIND_CONSTANT.
46682 INSN is the input instruction. IMM is the total of immediates.
46683 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
46684 bit immediates. */
46686 static int
46688 {
46696 }
46698 /* This function indicates if an operand of an instruction is an
46699 immediate. */
46701 static bool
46703 {
46712 }
46714 /* Return single or double path for instructions. */
46716 static enum insn_path
46718 {
46728 }
46730 /* Return insn dispatch group. */
46732 static enum dispatch_group
46734 {
46752 }
46754 /* Count number of GROUP restricted instructions in a dispatch
46755 window WINDOW_LIST. */
46757 static int
46759 {
46770 {
46789 }
46802 }
46804 /* This function returns true if insn satisfies dispatch rules on the
46805 last window scheduled. */
46807 static bool
46809 {
46817 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
46818 instructions should be given the lowest priority in the
46819 scheduling process in Haifa scheduler to make sure they will be
46820 scheduled in the same dispatch window as the reference to them. */
46824 /* Check nonrestricted. */
46828 /* Get last dispatch window. */
46833 {
46838 /* Window 1 is full. Go for next window. */
46840 }
46847 /* See if it fits in the first window. */
46849 {
46850 /* The first widow should have only single and double path
46851 uops. */
46857 }
46859 }
46861 /* Add an instruction INSN with NUM_UOPS micro-operations to the
46862 dispatch window WINDOW_LIST. */
46864 static void
46866 {
46884 /* Initialize window with new instruction. */
46905 {
46908 }
46909 }
46911 /* Adds a scheduled instruction, INSN, to the current dispatch window.
46912 If the total bytes of instructions or the number of instructions in
46913 the window exceed allowable, it allocates a new window. */
46915 static void
46917 {
46940 /* Get the last dispatch window. */
46948 else
46951 /* If current window is full, get a new window.
46952 Window number zero is full, if MAX_INSN uops are scheduled in it.
46953 Window number one is full, if window zero's bytes plus window
46954 one's bytes is 32, or if the bytes of the new instruction added
46955 to the total makes it greater than 48, or it has already MAX_INSN
46956 instructions in it. */
46965 {
46968 }
46971 {
46975 {
46978 }
46979 }
46981 {
46986 {
46989 }
46992 }
46993 else
46997 {
46998 /* End of basic block is reached do end-basic-block process. */
47001 }
47002 }
47004 /* Print the dispatch window, WINDOW_NUM, to FILE. */
47006 DEBUG_FUNCTION static void
47008 {
47014 else
47028 {
47031 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
47037 }
47038 }
47040 /* Print to stdout a dispatch window. */
47042 DEBUG_FUNCTION void
47044 {
47046 }
47048 /* Print INSN dispatch information to FILE. */
47050 DEBUG_FUNCTION static void
47052 {
47075 }
47077 /* Print to STDERR the status of the ready list with respect to
47078 dispatch windows. */
47080 DEBUG_FUNCTION void
47082 {
47090 }
47092 /* This routine is the driver of the dispatch scheduler. */
47094 static void
47096 {
47101 }
47103 /* Return TRUE if Dispatch Scheduling is supported. */
47105 static bool
47107 {
47111 {
47127 }
47130 }
47132 /* Implementation of reassociation_width target hook used by
47133 reassoc phase to identify parallelism level in reassociated
47134 tree. Statements tree_code is passed in OPC. Arguments type
47135 is passed in MODE.
47137 Currently parallel reassociation is enabled for Atom
47138 processors only and we set reassociation width to be 2
47139 because Atom may issue up to 2 instructions per cycle.
47141 Return value should be fixed if parallel reassociation is
47142 enabled for other processors. */
47144 static int
47147 {
47156 }
47158 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
47159 place emms and femms instructions. */
47161 static enum machine_mode
47163 {
47168 {
47185 else
47197 /* FALLTHRU */
47201 }
47202 }
47204 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
47205 vectors. If AVX512F is enabled then try vectorizing with 512bit,
47206 256bit and 128bit vectors. */
47208 static unsigned int
47210 {
47213 }
47215 \f
47217 /* Return class of registers which could be used for pseudo of MODE
47218 and of class RCLASS for spilling instead of memory. Return NO_REGS
47219 if it is not possible or non-profitable. */
47220 static reg_class_t
47222 {
47228 }
47230 /* Implement targetm.vectorize.init_cost. */
47234 {
47238 }
47240 /* Implement targetm.vectorize.add_stmt_cost. */
47242 static unsigned
47246 {
47253 /* Statements in an inner loop relative to the loop being
47254 vectorized are weighted more heavily. The value here is
47255 arbitrary and could potentially be improved with analysis. */
47263 }
47265 /* Implement targetm.vectorize.finish_cost. */
47267 static void
47270 {
47275 }
47277 /* Implement targetm.vectorize.destroy_cost_data. */
47279 static void
47281 {
47283 }
47285 /* Validate target specific memory model bits in VAL. */
47287 static unsigned HOST_WIDE_INT
47289 {
47296 {
47300 }
47303 {
47307 }
47309 {
47313 }
47315 }
47317 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
47318 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
47319 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
47320 or number of vecsize_mangle variants that should be emitted. */
47322 static int
47326 {
47333 {
47337 }
47342 {
47349 /* case SCmode: */
47350 /* case DCmode: */
47356 }
47358 tree t;
47362 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
47364 {
47371 /* case SCmode: */
47372 /* case DCmode: */
47378 }
47381 {
47382 /* Parse here processor clause. If not present, default to 'b'. */
47384 }
47386 {
47387 /* If the function isn't exported, we can pick up just one ISA
47388 for the clones. */
47393 else
47396 }
47397 else
47398 {
47401 }
47403 {
47416 }
47418 {
47421 else
47426 }
47428 }
47430 /* Add target attribute to SIMD clone NODE if needed. */
47432 static void
47434 {
47438 {
47453 }
47463 }
47465 /* If SIMD clone NODE can't be used in a vectorized loop
47466 in current function, return -1, otherwise return a badness of using it
47467 (0 if it is most desirable from vecsize_mangle point of view, 1
47468 slightly less desirable, etc.). */
47470 static int
47472 {
47474 {
47492 }
47493 }
47495 /* This function gives out the number of memory references.
47496 This value determines the unrolling factor for
47497 bdver3 and bdver4 architectures. */
47499 static int
47501 {
47503 {
47512 else
47514 }
47516 }
47518 /* This function adjusts the unroll factor based on
47519 the hardware capabilities. For ex, bdver3 has
47520 a loop buffer which makes unrolling of smaller
47521 loops less important. This function decides the
47522 unroll factor using number of memory references
47523 (value 32 is used) as a heuristic. */
47525 static unsigned
47527 {
47529 rtx insn;
47536 /* Count the number of memory references within the loop body. */
47539 {
47543 }
47550 }
47553 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
47555 static bool
47557 {
47558 /* For x87 floating point with standard excess precision handling,
47559 there is no adddf3 pattern (since x87 floating point only has
47560 XFmode operations) so the default hook implementation gets this
47561 wrong. */
47563 }
47565 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
47567 static void
47569 {
47574 {
47589 hold_fnclex);
47603 }
47605 {
47614 mxcsr_orig_var,
47624 ldmxcsr_hold_call);
47627 else
47632 ldmxcsr_clear_call);
47633 else
47637 stxmcsr_update_call);
47639 {
47645 exceptions_assign);
47646 }
47647 else
47652 ldmxcsr_update_call);
47653 }
47654 tree atomic_feraiseexcept
47659 atomic_feraiseexcept_call);
47660 }
47662 static enum machine_mode
47664 {
47665 /* Do not support pointer checker if MPX
47666 is not enabled. */
47668 {
47673 }
47676 }
47678 static tree
47680 {
47686 /* This function is supposed to be used to create zero and
47687 none bounds only. */
47692 }
47694 static int
47696 {
47715 }
47717 /* Initialize the GCC target structure. */
47718 #undef TARGET_RETURN_IN_MEMORY
47719 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
47721 #undef TARGET_LEGITIMIZE_ADDRESS
47722 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
47724 #undef TARGET_ATTRIBUTE_TABLE
47725 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
47726 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
47727 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
47728 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47729 # undef TARGET_MERGE_DECL_ATTRIBUTES
47730 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
47731 #endif
47733 #undef TARGET_COMP_TYPE_ATTRIBUTES
47734 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
47736 #undef TARGET_INIT_BUILTINS
47737 #define TARGET_INIT_BUILTINS ix86_init_builtins
47738 #undef TARGET_BUILTIN_DECL
47739 #define TARGET_BUILTIN_DECL ix86_builtin_decl
47740 #undef TARGET_EXPAND_BUILTIN
47741 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
47743 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
47744 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
47745 ix86_builtin_vectorized_function
47747 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
47748 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
47750 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
47751 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
47753 #undef TARGET_VECTORIZE_BUILTIN_GATHER
47754 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
47756 #undef TARGET_BUILTIN_RECIPROCAL
47757 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
47759 #undef TARGET_ASM_FUNCTION_EPILOGUE
47760 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
47762 #undef TARGET_ENCODE_SECTION_INFO
47763 #ifndef SUBTARGET_ENCODE_SECTION_INFO
47764 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
47765 #else
47766 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
47767 #endif
47769 #undef TARGET_ASM_OPEN_PAREN
47771 #undef TARGET_ASM_CLOSE_PAREN
47774 #undef TARGET_ASM_BYTE_OP
47775 #define TARGET_ASM_BYTE_OP ASM_BYTE
47777 #undef TARGET_ASM_ALIGNED_HI_OP
47778 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
47779 #undef TARGET_ASM_ALIGNED_SI_OP
47780 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
47781 #ifdef ASM_QUAD
47782 #undef TARGET_ASM_ALIGNED_DI_OP
47783 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
47784 #endif
47786 #undef TARGET_PROFILE_BEFORE_PROLOGUE
47787 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
47789 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
47790 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
47792 #undef TARGET_ASM_UNALIGNED_HI_OP
47793 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
47794 #undef TARGET_ASM_UNALIGNED_SI_OP
47795 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
47796 #undef TARGET_ASM_UNALIGNED_DI_OP
47797 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
47799 #undef TARGET_PRINT_OPERAND
47800 #define TARGET_PRINT_OPERAND ix86_print_operand
47801 #undef TARGET_PRINT_OPERAND_ADDRESS
47802 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
47803 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
47804 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
47805 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
47806 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
47808 #undef TARGET_SCHED_INIT_GLOBAL
47809 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
47810 #undef TARGET_SCHED_ADJUST_COST
47811 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
47812 #undef TARGET_SCHED_ISSUE_RATE
47813 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
47814 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
47815 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
47816 ia32_multipass_dfa_lookahead
47817 #undef TARGET_SCHED_MACRO_FUSION_P
47818 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
47819 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
47820 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
47822 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
47823 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
47825 #undef TARGET_MEMMODEL_CHECK
47826 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
47828 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
47829 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
47831 #ifdef HAVE_AS_TLS
47832 #undef TARGET_HAVE_TLS
47833 #define TARGET_HAVE_TLS true
47834 #endif
47835 #undef TARGET_CANNOT_FORCE_CONST_MEM
47836 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
47837 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
47838 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
47840 #undef TARGET_DELEGITIMIZE_ADDRESS
47841 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
47843 #undef TARGET_MS_BITFIELD_LAYOUT_P
47844 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
47846 #if TARGET_MACHO
47847 #undef TARGET_BINDS_LOCAL_P
47848 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
47849 #endif
47850 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47851 #undef TARGET_BINDS_LOCAL_P
47852 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
47853 #endif
47855 #undef TARGET_ASM_OUTPUT_MI_THUNK
47856 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
47857 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
47858 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
47860 #undef TARGET_ASM_FILE_START
47861 #define TARGET_ASM_FILE_START x86_file_start
47863 #undef TARGET_OPTION_OVERRIDE
47864 #define TARGET_OPTION_OVERRIDE ix86_option_override
47866 #undef TARGET_REGISTER_MOVE_COST
47867 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
47868 #undef TARGET_MEMORY_MOVE_COST
47869 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
47870 #undef TARGET_RTX_COSTS
47871 #define TARGET_RTX_COSTS ix86_rtx_costs
47872 #undef TARGET_ADDRESS_COST
47873 #define TARGET_ADDRESS_COST ix86_address_cost
47875 #undef TARGET_FIXED_CONDITION_CODE_REGS
47876 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
47877 #undef TARGET_CC_MODES_COMPATIBLE
47878 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
47880 #undef TARGET_MACHINE_DEPENDENT_REORG
47881 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
47883 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
47884 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
47886 #undef TARGET_BUILD_BUILTIN_VA_LIST
47887 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
47889 #undef TARGET_FOLD_BUILTIN
47890 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
47892 #undef TARGET_COMPARE_VERSION_PRIORITY
47893 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
47895 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
47896 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
47897 ix86_generate_version_dispatcher_body
47899 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
47900 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
47901 ix86_get_function_versions_dispatcher
47903 #undef TARGET_ENUM_VA_LIST_P
47904 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
47906 #undef TARGET_FN_ABI_VA_LIST
47907 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
47909 #undef TARGET_CANONICAL_VA_LIST_TYPE
47910 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
47912 #undef TARGET_EXPAND_BUILTIN_VA_START
47913 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
47915 #undef TARGET_MD_ASM_CLOBBERS
47916 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
47918 #undef TARGET_PROMOTE_PROTOTYPES
47919 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
47920 #undef TARGET_SETUP_INCOMING_VARARGS
47921 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
47922 #undef TARGET_MUST_PASS_IN_STACK
47923 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
47924 #undef TARGET_FUNCTION_ARG_ADVANCE
47925 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
47926 #undef TARGET_FUNCTION_ARG
47927 #define TARGET_FUNCTION_ARG ix86_function_arg
47928 #undef TARGET_FUNCTION_ARG_BOUNDARY
47929 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
47930 #undef TARGET_PASS_BY_REFERENCE
47931 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
47932 #undef TARGET_INTERNAL_ARG_POINTER
47933 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
47934 #undef TARGET_UPDATE_STACK_BOUNDARY
47935 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
47936 #undef TARGET_GET_DRAP_RTX
47937 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
47938 #undef TARGET_STRICT_ARGUMENT_NAMING
47939 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
47940 #undef TARGET_STATIC_CHAIN
47941 #define TARGET_STATIC_CHAIN ix86_static_chain
47942 #undef TARGET_TRAMPOLINE_INIT
47943 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
47944 #undef TARGET_RETURN_POPS_ARGS
47945 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
47947 #undef TARGET_LEGITIMATE_COMBINED_INSN
47948 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
47950 #undef TARGET_ASAN_SHADOW_OFFSET
47951 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
47953 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
47954 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
47956 #undef TARGET_SCALAR_MODE_SUPPORTED_P
47957 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
47959 #undef TARGET_VECTOR_MODE_SUPPORTED_P
47960 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
47962 #undef TARGET_C_MODE_FOR_SUFFIX
47963 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
47965 #ifdef HAVE_AS_TLS
47966 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
47967 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
47968 #endif
47970 #ifdef SUBTARGET_INSERT_ATTRIBUTES
47971 #undef TARGET_INSERT_ATTRIBUTES
47972 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
47973 #endif
47975 #undef TARGET_MANGLE_TYPE
47976 #define TARGET_MANGLE_TYPE ix86_mangle_type
47978 #if !TARGET_MACHO
47979 #undef TARGET_STACK_PROTECT_FAIL
47980 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
47981 #endif
47983 #undef TARGET_FUNCTION_VALUE
47984 #define TARGET_FUNCTION_VALUE ix86_function_value
47986 #undef TARGET_FUNCTION_VALUE_REGNO_P
47987 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
47989 #undef TARGET_PROMOTE_FUNCTION_MODE
47990 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
47992 #undef TARGET_MEMBER_TYPE_FORCES_BLK
47993 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
47995 #undef TARGET_INSTANTIATE_DECLS
47996 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
47998 #undef TARGET_SECONDARY_RELOAD
47999 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
48001 #undef TARGET_CLASS_MAX_NREGS
48002 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
48004 #undef TARGET_PREFERRED_RELOAD_CLASS
48005 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
48006 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
48007 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
48008 #undef TARGET_CLASS_LIKELY_SPILLED_P
48009 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
48011 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
48012 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
48013 ix86_builtin_vectorization_cost
48014 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
48015 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
48016 ix86_vectorize_vec_perm_const_ok
48017 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
48018 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
48019 ix86_preferred_simd_mode
48020 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
48021 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
48022 ix86_autovectorize_vector_sizes
48023 #undef TARGET_VECTORIZE_INIT_COST
48024 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
48025 #undef TARGET_VECTORIZE_ADD_STMT_COST
48026 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
48027 #undef TARGET_VECTORIZE_FINISH_COST
48028 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
48029 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
48030 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
48032 #undef TARGET_SET_CURRENT_FUNCTION
48033 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
48035 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
48036 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
48038 #undef TARGET_OPTION_SAVE
48039 #define TARGET_OPTION_SAVE ix86_function_specific_save
48041 #undef TARGET_OPTION_RESTORE
48042 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
48044 #undef TARGET_OPTION_PRINT
48045 #define TARGET_OPTION_PRINT ix86_function_specific_print
48047 #undef TARGET_OPTION_FUNCTION_VERSIONS
48048 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
48050 #undef TARGET_CAN_INLINE_P
48051 #define TARGET_CAN_INLINE_P ix86_can_inline_p
48053 #undef TARGET_EXPAND_TO_RTL_HOOK
48054 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
48056 #undef TARGET_LEGITIMATE_ADDRESS_P
48057 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
48059 #undef TARGET_LRA_P
48060 #define TARGET_LRA_P hook_bool_void_true
48062 #undef TARGET_REGISTER_PRIORITY
48063 #define TARGET_REGISTER_PRIORITY ix86_register_priority
48065 #undef TARGET_REGISTER_USAGE_LEVELING_P
48066 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
48068 #undef TARGET_LEGITIMATE_CONSTANT_P
48069 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
48071 #undef TARGET_FRAME_POINTER_REQUIRED
48072 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
48074 #undef TARGET_CAN_ELIMINATE
48075 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
48077 #undef TARGET_EXTRA_LIVE_ON_ENTRY
48078 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
48080 #undef TARGET_ASM_CODE_END
48081 #define TARGET_ASM_CODE_END ix86_code_end
48083 #undef TARGET_CONDITIONAL_REGISTER_USAGE
48084 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
48086 #if TARGET_MACHO
48087 #undef TARGET_INIT_LIBFUNCS
48088 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
48089 #endif
48091 #undef TARGET_LOOP_UNROLL_ADJUST
48092 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
48094 #undef TARGET_SPILL_CLASS
48095 #define TARGET_SPILL_CLASS ix86_spill_class
48097 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
48098 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
48099 ix86_simd_clone_compute_vecsize_and_simdlen
48101 #undef TARGET_SIMD_CLONE_ADJUST
48102 #define TARGET_SIMD_CLONE_ADJUST \
48103 ix86_simd_clone_adjust
48105 #undef TARGET_SIMD_CLONE_USABLE
48106 #define TARGET_SIMD_CLONE_USABLE \
48107 ix86_simd_clone_usable
48109 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
48110 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
48111 ix86_float_exceptions_rounding_supported_p
48113 #undef TARGET_LOAD_BOUNDS_FOR_ARG
48114 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
48116 #undef TARGET_STORE_BOUNDS_FOR_ARG
48117 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
48119 #undef TARGET_LOAD_RETURNED_BOUNDS
48120 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
48122 #undef TARGET_STORE_RETURNED_BOUNDS
48123 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
48125 #undef TARGET_CHKP_BOUND_MODE
48126 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
48128 #undef TARGET_BUILTIN_CHKP_FUNCTION
48129 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
48131 #undef TARGET_FN_ABI_VA_LIST_BOUNDS_SIZE
48132 #define TARGET_FN_ABI_VA_LIST_BOUNDS_SIZE ix86_fn_abi_va_list_bounds_size
48134 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
48135 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
48137 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
48138 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
48140 #undef TARGET_CHKP_INITIALIZE_BOUNDS
48141 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
48143 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
48144 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
48147 \f