| blob | 1a6eda609ed963462a6aa8fab721c93c021df1e3 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 machine_mode,
422 machine_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1216 {
1219 }
1220 }
1221 }
1225 /* Now scan all the insns in forward order. */
1233 {
1239 label_tick++;
1249 {
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1269 into SUBREGs. */
1272 /* Try this insn with each insn it links back to. */
1278 {
1281 }
1283 /* Try each sequence of three linked insns ending with this one. */
1287 {
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1299 {
1302 }
1303 }
1305 /* Try to combine a jump insn that uses CC0
1306 with a preceding insn that sets CC0, and maybe with its
1307 logical predecessor as well.
1308 This is how we make decrement-and-branch insns.
1309 We need this special code because data flow connections
1310 via CC0 do not get entered in LOG_LINKS. */
1317 {
1328 }
1330 /* Do the same for an insn that explicitly references CC0. */
1337 {
1348 }
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1354 {
1366 }
1368 /* Try combining an insn with two different insns whose results it
1369 uses. */
1379 {
1382 }
1384 /* Try four-instruction combinations. */
1387 {
1391 /* If the linked insn has been replaced by a note, then there
1392 is no point in pursuing this chain any further. */
1397 {
1401 /* I0 -> I1 -> I2 -> I3. */
1407 {
1410 }
1411 /* I0, I1 -> I2, I2 -> I3. */
1418 {
1421 }
1422 }
1425 {
1429 /* I0 -> I2; I1, I2 -> I3. */
1435 {
1438 }
1439 /* I0 -> I1; I1, I2 -> I3. */
1445 {
1448 }
1449 }
1450 }
1452 /* Try this insn with each REG_EQUAL note it links back to. */
1454 {
1460 /* Avoid using a register that may already been marked
1461 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1483 last_combined_insn);
1486 {
1489 }
1492 }
1493 }
1498 retry:
1499 ;
1500 }
1501 }
1508 /* Clean up. */
1514 {
1517 {
1520 }
1522 }
1532 /* Make recognizer allow volatile MEMs again. */
1536 }
1538 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1540 static void
1542 {
1548 }
1549 \f
1550 /* Set up any promoted values for incoming argument registers. */
1552 static void
1554 {
1555 tree arg;
1560 {
1565 /* Only continue if the incoming argument is in a register. */
1569 /* Determine, if possible, whether all call sites of the current
1570 function lie within the current compilation unit. (This does
1571 take into account the exporting of a function via taking its
1572 address, and so forth.) */
1575 /* The mode and signedness of the argument before any promotions happen
1576 (equal to the mode of the pseudo holding it at that stage). */
1580 /* The mode and signedness of the argument after any source language and
1581 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1585 /* The mode and signedness of the argument as it is actually passed,
1586 see assign_parm_setup_reg in function.c. */
1590 /* The mode of the register in which the argument is being passed. */
1593 /* Eliminate sign extensions in the callee when:
1594 (a) A mode promotion has occurred; */
1597 /* (b) The mode of the register is the same as the mode of
1598 the argument as it is passed; */
1601 /* (c) There's no language level extension; */
1603 ;
1604 /* (c.1) All callers are from the current compilation unit. If that's
1605 the case we don't have to rely on an ABI, we only have to know
1606 what we're generating right now, and we know that we will do the
1607 mode1 to mode2 promotion with the given sign. */
1610 /* (c.2) The combination of the two promotions is useful. This is
1611 true when the signs match, or if the first promotion is unsigned.
1612 In the later case, (sign_extend (zero_extend x)) is the same as
1613 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1619 /* Record that the value was promoted from mode1 to mode3,
1620 so that any sign extension at the head of the current
1621 function may be eliminated. */
1625 }
1626 }
1628 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1629 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1630 because some machines (maybe most) will actually do the sign-extension and
1631 this is the conservative approach.
1633 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1634 kludge. */
1636 static rtx
1638 {
1646 }
1648 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1649 and SET. */
1651 static void
1653 rtx x)
1654 {
1664 {
1668 }
1670 /* Don't call nonzero_bits if it cannot change anything. */
1672 {
1677 }
1679 /* Don't call num_sign_bit_copies if it cannot change anything. */
1681 {
1684 {
1688 }
1691 }
1692 }
1694 /* Called via note_stores. If X is a pseudo that is narrower than
1695 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1697 If we are setting only a portion of X and we can't figure out what
1698 portion, assume all bits will be used since we don't know what will
1699 be happening.
1701 Similarly, set how many bits of X are known to be copies of the sign bit
1702 at all locations in the function. This is the smallest number implied
1703 by any set of X. */
1705 static void
1707 {
1712 /* If this register is undefined at the start of the file, we can't
1713 say what its contents were. */
1714 && ! REGNO_REG_SET_P
1717 {
1721 {
1725 }
1727 /* If this register is being initialized using itself, and the
1728 register is uninitialized in this basic block, and there are
1729 no LOG_LINKS which set the register, then part of the
1730 register is uninitialized. In that case we can't assume
1731 anything about the number of nonzero bits.
1733 ??? We could do better if we checked this in
1734 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1735 could avoid making assumptions about the insn which initially
1736 sets the register, while still using the information in other
1737 insns. We would have to be careful to check every insn
1738 involved in the combination. */
1744 {
1751 {
1755 }
1756 }
1758 /* If this is a complex assignment, see if we can convert it into a
1759 simple assignment. */
1762 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1763 set what we know about X. */
1769 else
1770 {
1773 }
1774 }
1775 }
1776 \f
1777 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1778 optionally insns that were previously combined into I3 or that will be
1779 combined into the merger of INSN and I3. The order is PRED, PRED2,
1780 INSN, SUCC, SUCC2, I3.
1782 Return 0 if the combination is not allowed for any reason.
1784 If the combination is allowed, *PDEST will be set to the single
1785 destination of INSN and *PSRC to the single source, and this function
1786 will return 1. */
1788 static int
1792 {
1797 rtx link;
1802 {
1804 {
1809 }
1814 }
1818 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1819 or a PARALLEL consisting of such a SET and CLOBBERs.
1821 If INSN has CLOBBER parallel parts, ignore them for our processing.
1822 By definition, these happen during the execution of the insn. When it
1823 is merged with another insn, all bets are off. If they are, in fact,
1824 needed and aren't also supplied in I3, they may be added by
1825 recog_for_combine. Otherwise, it won't match.
1827 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1828 note.
1830 Get the source and destination of INSN. If more than one, can't
1831 combine. */
1837 {
1839 {
1843 {
1844 /* This is important to combine floating point insns
1845 for the SH4 port. */
1847 /* Combining an isolated USE doesn't make sense.
1848 We depend here on combinable_i3pat to reject them. */
1849 /* The code below this loop only verifies that the inputs of
1850 the SET in INSN do not change. We call reg_set_between_p
1851 to verify that the REG in the USE does not change between
1852 I3 and INSN.
1853 If the USE in INSN was for a pseudo register, the matching
1854 insn pattern will likely match any register; combining this
1855 with any other USE would only be safe if we knew that the
1856 used registers have identical values, or if there was
1857 something to tell them apart, e.g. different modes. For
1858 now, we forgo such complicated tests and simply disallow
1859 combining of USES of pseudo registers with any other USE. */
1862 {
1867 do
1868 {
1878 }
1880 }
1883 /* We can ignore CLOBBERs. */
1888 /* Ignore SETs whose result isn't used but not those that
1889 have side-effects. */
1895 /* If we have already found a SET, this is a second one and
1896 so we cannot combine with this insn. */
1904 /* Anything else means we can't combine. */
1906 }
1907 }
1910 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1911 so don't do anything with it. */
1914 }
1915 else
1921 /* The simplification in expand_field_assignment may call back to
1922 get_last_value, so set safe guard here. */
1928 /* Do not eliminate user-specified register if it is in an
1929 asm input because we may break the register asm usage defined
1930 in GCC manual if allow to do so.
1931 Be aware that this may cover more cases than we expect but this
1932 should be harmless. */
1937 /* Don't eliminate a store in the stack pointer. */
1939 /* Don't combine with an insn that sets a register to itself if it has
1940 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1942 /* Can't merge an ASM_OPERANDS. */
1944 /* Can't merge a function call. */
1946 /* Don't eliminate a function call argument. */
1952 /* Don't substitute into an incremented register. */
1956 /* Don't substitute into a non-local goto, this confuses CFG. */
1958 /* Make sure that DEST is not used after INSN but before SUCC, or
1959 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1960 || (!all_adjacent
1961 && ((succ2
1965 || (succ
1966 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1967 that case SUCC is not in the insn stream, so use SUCC2
1968 instead for this test. */
1970 succ2
1973 /* Make sure that the value that is to be substituted for the register
1974 does not use any registers whose values alter in between. However,
1975 If the insns are adjacent, a use can't cross a set even though we
1976 think it might (this can happen for a sequence of insns each setting
1977 the same destination; last_set of that register might point to
1978 a NOTE). If INSN has a REG_EQUIV note, the register is always
1979 equivalent to the memory so the substitution is valid even if there
1980 are intervening stores. Also, don't move a volatile asm or
1981 UNSPEC_VOLATILE across any other insns. */
1982 || (! all_adjacent
1988 /* Don't combine across a CALL_INSN, because that would possibly
1989 change whether the life span of some REGs crosses calls or not,
1990 and it is a pain to update that information.
1991 Exception: if source is a constant, moving it later can't hurt.
1992 Accept that as a special case. */
1996 /* DEST must either be a REG or CC0. */
1998 {
1999 /* If register alignment is being enforced for multi-word items in all
2000 cases except for parameters, it is possible to have a register copy
2001 insn referencing a hard register that is not allowed to contain the
2002 mode being copied and which would not be valid as an operand of most
2003 insns. Eliminate this problem by not combining with such an insn.
2005 Also, on some machines we don't want to extend the life of a hard
2006 register. */
2011 /* Don't extend the life of a hard register unless it is
2012 user variable (if we have few registers) or it can't
2013 fit into the desired register (meaning something special
2014 is going on).
2015 Also avoid substituting a return register into I3, because
2016 reload can't handle a conflict with constraints of other
2017 inputs. */
2021 }
2029 {
2032 /* If the clobber represents an earlyclobber operand, we must not
2033 substitute an expression containing the clobbered register.
2034 As we do not analyze the constraint strings here, we have to
2035 make the conservative assumption. However, if the register is
2036 a fixed hard reg, the clobber cannot represent any operand;
2037 we leave it up to the machine description to either accept or
2038 reject use-and-clobber patterns. */
2044 }
2046 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2047 or not), reject, unless nothing volatile comes between it and I3 */
2050 {
2051 /* Make sure neither succ nor succ2 contains a volatile reference. */
2056 /* We'll check insns between INSN and I3 below. */
2057 }
2059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2060 to be an explicit register variable, and was chosen for a reason. */
2066 /* If INSN contains volatile references (specifically volatile MEMs),
2067 we cannot combine across any other volatile references.
2068 Even if INSN doesn't contain volatile references, any intervening
2069 volatile insn might affect machine state. */
2072 ? volatile_refs_p
2079 /* If INSN contains an autoincrement or autodecrement, make sure that
2080 register is not used between there and I3, and not already used in
2081 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2082 Also insist that I3 not be a jump; if it were one
2083 and the incremented register were spilled, we would lose. */
2101 /* Don't combine an insn that follows a CC0-setting insn.
2102 An insn that uses CC0 must not be separated from the one that sets it.
2103 We do, however, allow I2 to follow a CC0-setting insn if that insn
2104 is passed as I1; in that case it will be deleted also.
2105 We also allow combining in this case if all the insns are adjacent
2106 because that would leave the two CC0 insns adjacent as well.
2107 It would be more logical to test whether CC0 occurs inside I1 or I2,
2108 but that would be much slower, and this ought to be equivalent. */
2111 {
2116 }
2118 /* If we get here, we have passed all the tests and the combination is
2119 to be allowed. */
2125 }
2126 \f
2127 /* LOC is the location within I3 that contains its pattern or the component
2128 of a PARALLEL of the pattern. We validate that it is valid for combining.
2130 One problem is if I3 modifies its output, as opposed to replacing it
2131 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2132 doing so would produce an insn that is not equivalent to the original insns.
2134 Consider:
2136 (set (reg:DI 101) (reg:DI 100))
2137 (set (subreg:SI (reg:DI 101) 0) <foo>)
2139 This is NOT equivalent to:
2141 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2142 (set (reg:DI 101) (reg:DI 100))])
2144 Not only does this modify 100 (in which case it might still be valid
2145 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2147 We can also run into a problem if I2 sets a register that I1
2148 uses and I1 gets directly substituted into I3 (not via I2). In that
2149 case, we would be getting the wrong value of I2DEST into I3, so we
2150 must reject the combination. This case occurs when I2 and I1 both
2151 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2152 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2153 of a SET must prevent combination from occurring. The same situation
2154 can occur for I0, in which case I0_NOT_IN_SRC is set.
2156 Before doing the above check, we first try to expand a field assignment
2157 into a set of logical operations.
2159 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2160 we place a register that is both set and used within I3. If more than one
2161 such register is detected, we fail.
2163 Return 1 if the combination is valid, zero otherwise. */
2165 static int
2168 {
2172 {
2177 rtx subdest;
2184 /* Check for the case where I3 modifies its output, as discussed
2185 above. We don't want to prevent pseudos from being combined
2186 into the address of a MEM, so only prevent the combination if
2187 i1 or i2 set the same MEM. */
2197 /* This is the same test done in can_combine_p except we can't test
2198 all_adjacent; we don't have to, since this instruction will stay
2199 in place, thus we are not considering increasing the lifetime of
2200 INNER_DEST.
2202 Also, if this insn sets a function argument, combining it with
2203 something that might need a spill could clobber a previous
2204 function argument; the all_adjacent test in can_combine_p also
2205 checks this; here, we do a more specific test for this case. */
2215 /* If DEST is used in I3, it is being killed in this insn, so
2216 record that for later. We have to consider paradoxical
2217 subregs here, since they kill the whole register, but we
2218 ignore partial subregs, STRICT_LOW_PART, etc.
2219 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2220 STACK_POINTER_REGNUM, since these are always considered to be
2221 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2231 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2237 {
2242 }
2243 }
2246 {
2253 }
2256 }
2257 \f
2258 /* Return 1 if X is an arithmetic expression that contains a multiplication
2259 and division. We don't count multiplications by powers of two here. */
2261 static int
2263 {
2265 {
2281 }
2282 }
2283 \f
2284 /* Determine whether INSN can be used in a combination. Return nonzero if
2285 not. This is used in try_combine to detect early some cases where we
2286 can't perform combinations. */
2288 static int
2290 {
2291 rtx set;
2294 /* If this isn't really an insn, we can't do anything.
2295 This can occur when flow deletes an insn that it has merged into an
2296 auto-increment address. */
2300 /* Never combine loads and stores involving hard regs that are likely
2301 to be spilled. The register allocator can usually handle such
2302 reg-reg moves by tying. If we allow the combiner to make
2303 substitutions of likely-spilled regs, reload might die.
2304 As an exception, we allow combinations involving fixed regs; these are
2305 not available to the register allocator so there's no risk involved. */
2326 }
2328 struct likely_spilled_retval_info
2329 {
2332 };
2334 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2335 hard registers that are known to be written to / clobbered in full. */
2336 static void
2338 {
2355 else
2358 }
2360 /* Return nonzero iff part of the return value is live during INSN, and
2361 it is likely spilled. This can happen when more than one insn is needed
2362 to copy the return value, e.g. when we consider to combine into the
2363 second copy insn for a complex value. */
2365 static int
2367 {
2369 rtx reg;
2372 /* We assume here that no machine mode needs more than
2373 32 hard registers when the value overlaps with a register
2374 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2389 /* Disregard parts of the return value that are set later. */
2398 /* Check if any of the (probably) live return value registers is
2399 likely spilled. */
2400 nregs --;
2401 do
2402 {
2408 }
2410 /* Adjust INSN after we made a change to its destination.
2412 Changing the destination can invalidate notes that say something about
2413 the results of the insn and a LOG_LINK pointing to the insn. */
2415 static void
2417 {
2418 /* For notes, be conservative and simply remove them. */
2421 /* The new insn will have a destination that was previously the destination
2422 of an insn just above it. Call distribute_links to make a LOG_LINK from
2423 the next use of that destination. */
2439 }
2441 /* Return TRUE if combine can reuse reg X in mode MODE.
2442 ADDED_SETS is nonzero if the original set is still required. */
2443 static bool
2445 {
2452 /* Allow hard registers if the new mode is legal, and occupies no more
2453 registers than the old mode. */
2458 /* Or a pseudo that is only used once. */
2461 && !added_sets
2463 }
2466 /* Check whether X, the destination of a set, refers to part of
2467 the register specified by REG. */
2469 static bool
2471 {
2472 /* Check that reg is an integer mode register. */
2483 }
2485 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2486 Note that the INSN should be deleted *after* removing dead edges, so
2487 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2488 but not for a (set (pc) (label_ref FOO)). */
2490 static void
2492 {
2500 {
2505 /* Remove barriers from the footer if there are any. */
2508 {
2511 else
2515 }
2518 }
2519 }
2521 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2522 by an arbitrary number of CLOBBERs. */
2523 static bool
2525 {
2544 }
2546 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2547 CLOBBERs), can be split into individual SETs in that order, without
2548 changing semantics. */
2549 static bool
2551 {
2559 {
2568 }
2571 }
2573 /* Try to combine the insns I0, I1 and I2 into I3.
2574 Here I0, I1 and I2 appear earlier than I3.
2575 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2576 I3.
2578 If we are combining more than two insns and the resulting insn is not
2579 recognized, try splitting it into two insns. If that happens, I2 and I3
2580 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2581 Otherwise, I0, I1 and I2 are pseudo-deleted.
2583 Return 0 if the combination does not work. Then nothing is changed.
2584 If we did the combination, return the insn at which combine should
2585 resume scanning.
2587 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2588 new direct jump instruction.
2590 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2591 been I3 passed to an earlier try_combine within the same basic
2592 block. */
2597 {
2598 /* New patterns for I3 and I2, respectively. */
2602 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2603 dead. */
2605 /* Total number of SETs to put into I3. */
2607 /* Nonzero if I2's or I1's body now appears in I3. */
2609 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2611 /* Contains I3 if the destination of I3 is used in its source, which means
2612 that the old life of I3 is being killed. If that usage is placed into
2613 I2 and not in I3, a REG_DEAD note must be made. */
2615 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2617 /* Copy of SET_SRC of I1 and I0, if needed. */
2619 /* Set if I2DEST was reused as a scratch register. */
2621 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2623 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2628 /* Notes that must be added to REG_NOTES in I3 and I2. */
2630 /* Notes that we substituted I3 into I2 instead of the normal case. */
2632 /* Notes that I1, I2 or I3 is a MULT operation. */
2639 rtx temp_expr;
2642 rtx new_other_notes;
2645 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2646 never be). */
2650 /* Only try four-insn combinations when there's high likelihood of
2651 success. Look for simple insns, such as loads of constants or
2652 binary operations involving a constant. */
2654 {
2664 {
2667 rtx src;
2672 {
2675 }
2677 ngood++;
2680 nshift++;
2681 }
2683 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2684 are likely manipulating its value. Ideally we'll be able to combine
2685 all four insns into a bitfield insertion of some kind.
2687 Note the source in I0 might be inside a sign/zero extension and the
2688 memory modes in I0 and I3 might be different. So extract the address
2689 from the destination of I3 and search for it in the source of I0.
2691 In the event that there's a match but the source/dest do not actually
2692 refer to the same memory, the worst that happens is we try some
2693 combinations that we wouldn't have otherwise. */
2695 /* Ensure the source of SET0 is a MEM, possibly buried inside
2696 an extension. */
2702 /* Ensure the destination of SET3 is a MEM. */
2704 /* Would it be better to extract the base address for the MEM
2705 in SET3 and look for that? I don't have cases where it matters
2706 but I could envision such cases. */
2712 }
2714 /* Exit early if one of the insns involved can't be used for
2715 combinations. */
2726 combine_attempts++;
2729 /* Reset the hard register usage information. */
2733 {
2740 else
2743 }
2745 /* If multiple insns feed into one of I2 or I3, they can be in any
2746 order. To simplify the code below, reorder them in sequence. */
2756 /* First check for one important special case that the code below will
2757 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2758 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2759 we may be able to replace that destination with the destination of I3.
2760 This occurs in the common code where we compute both a quotient and
2761 remainder into a structure, in which case we want to do the computation
2762 directly into the structure to avoid register-register copies.
2764 Note that this case handles both multiple sets in I2 and also cases
2765 where I2 has a number of CLOBBERs inside the PARALLEL.
2767 We make very conservative checks below and only try to handle the
2768 most common cases of this. For example, we only handle the case
2769 where I2 and I3 are adjacent to avoid making difficult register
2770 usage tests. */
2778 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2779 below would need to check what is inside (and reg_overlap_mentioned_p
2780 doesn't support those codes anyway). Don't allow those destinations;
2781 the resulting insn isn't likely to be recognized anyway. */
2787 {
2790 /* Make sure that the destination of I3,
2791 which we are going to substitute into one output of I2,
2792 is not used within another output of I2. We must avoid making this:
2793 (parallel [(set (mem (reg 69)) ...)
2794 (set (reg 69) ...)])
2795 which is not well-defined as to order of actions.
2796 (Besides, reload can't handle output reloads for this.)
2798 The problem can also happen if the dest of I3 is a memory ref,
2799 if another dest in I2 is an indirect memory ref.
2801 Neither can this PARALLEL be an asm. We do not allow combining
2802 that usually (see can_combine_p), so do not here either. */
2805 {
2814 }
2820 {
2821 combine_merges++;
2831 /* Replace the dest in I2 with our dest and make the resulting
2832 insn the new pattern for I3. Then skip to where we validate
2833 the pattern. Everything was set up above. */
2838 }
2839 }
2841 /* If I2 is setting a pseudo to a constant and I3 is setting some
2842 sub-part of it to another constant, merge them by making a new
2843 constant. */
2850 {
2856 {
2859 {
2865 }
2866 }
2867 else
2868 {
2873 }
2876 {
2877 /* If this is the low part, we're done. */
2879 ;
2880 /* Handle the case where inner is twice the size of outer. */
2884 /* Otherwise give up for now. */
2885 else
2887 }
2890 {
2894 wide_int o
2899 combine_merges++;
2906 /* Replace the source in I2 with the new constant and make the
2907 resulting insn the new pattern for I3. Then skip to where we
2908 validate the pattern. Everything was set up above. */
2914 /* The dest of I3 has been replaced with the dest of I2. */
2917 }
2918 }
2920 /* If we have no I1 and I2 looks like:
2921 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2922 (set Y OP)])
2923 make up a dummy I1 that is
2924 (set Y OP)
2925 and change I2 to be
2926 (set (reg:CC X) (compare:CC Y (const_int 0)))
2928 (We can ignore any trailing CLOBBERs.)
2930 This undoes a previous combination and allows us to match a branch-and-
2931 decrement insn. */
2943 {
2944 /* We make I1 with the same INSN_UID as I2. This gives it
2945 the same DF_INSN_LUID for value tracking. Our fake I1 will
2946 never appear in the insn stream so giving it the same INSN_UID
2947 as I2 will not cause a problem. */
2960 }
2962 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2963 make those two SETs separate I1 and I2 insns, and make an I0 that is
2964 the original I1. */
2970 {
2971 /* If there is no I1, there is no I0 either. */
2974 /* We make I1 with the same INSN_UID as I2. This gives it
2975 the same DF_INSN_LUID for value tracking. Our fake I1 will
2976 never appear in the insn stream so giving it the same INSN_UID
2977 as I2 will not cause a problem. */
2985 }
2987 /* Verify that I2 and I1 are valid for combining. */
2993 {
2996 }
2998 /* Record whether I2DEST is used in I2SRC and similarly for the other
2999 cases. Knowing this will help in register status updating below. */
3010 /* For the earlier insns, determine which of the subsequent ones they
3011 feed. */
3018 /* Ensure that I3's pattern can be the destination of combines. */
3024 {
3027 }
3029 /* See if any of the insns is a MULT operation. Unless one is, we will
3030 reject a combination that is, since it must be slower. Be conservative
3031 here. */
3039 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3040 We used to do this EXCEPT in one case: I3 has a post-inc in an
3041 output operand. However, that exception can give rise to insns like
3042 mov r3,(r3)+
3043 which is a famous insn on the PDP-11 where the value of r3 used as the
3044 source was model-dependent. Avoid this sort of thing. */
3046 #if 0
3052 /* It's not the exception. */
3053 #endif
3055 {
3056 rtx link;
3062 {
3065 }
3066 }
3068 /* See if the SETs in I1 or I2 need to be kept around in the merged
3069 instruction: whenever the value set there is still needed past I3.
3070 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3072 For the SET in I1, we have two cases: if I1 and I2 independently feed
3073 into I3, the set in I1 needs to be kept around unless I1DEST dies
3074 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3075 in I1 needs to be kept around unless I1DEST dies or is set in either
3076 I2 or I3. The same considerations apply to I0. */
3083 else
3091 else
3094 /* We are about to copy insns for the case where they need to be kept
3095 around. Check that they can be copied in the merged instruction. */
3101 {
3104 }
3106 /* If the set in I2 needs to be kept around, we must make a copy of
3107 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3108 PATTERN (I2), we are only substituting for the original I1DEST, not into
3109 an already-substituted copy. This also prevents making self-referential
3110 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3111 I2DEST. */
3114 {
3117 else
3119 }
3122 {
3125 else
3127 }
3130 {
3133 else
3135 }
3137 combine_merges++;
3139 /* Substitute in the latest insn for the regs set by the earlier ones. */
3145 /* Many machines that don't use CC0 have insns that can both perform an
3146 arithmetic operation and set the condition code. These operations will
3147 be represented as a PARALLEL with the first element of the vector
3148 being a COMPARE of an arithmetic operation with the constant zero.
3149 The second element of the vector will set some pseudo to the result
3150 of the same arithmetic operation. If we simplify the COMPARE, we won't
3151 match such a pattern and so will generate an extra insn. Here we test
3152 for this case, where both the comparison and the operation result are
3153 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3154 I2SRC. Later we will make the PARALLEL that contains I2. */
3160 {
3161 rtx newpat_dest;
3175 {
3180 }
3182 /* Do the rest only if op1 is const0_rtx, which may be the
3183 result of simplification. */
3185 {
3186 /* If a single use of the CC is found, prepare to modify it
3187 when SELECT_CC_MODE returns a new CC-class mode, or when
3188 the above simplify_compare_const() returned a new comparison
3189 operator. undobuf.other_insn is assigned the CC use insn
3190 when modifying it. */
3192 {
3193 #ifdef SELECT_CC_MODE
3194 machine_mode new_mode
3199 {
3204 else
3205 {
3208 }
3209 }
3210 #endif
3211 /* Cases for modifying the CC-using comparison. */
3213 /* ??? Do we need to verify the zero rtx? */
3215 {
3216 /* Replace cc_use_loc with entire new RTX. */
3221 }
3223 {
3224 /* Just replace the CC reg with a new mode. */
3227 }
3228 }
3230 /* Now we modify the current newpat:
3231 First, SET_DEST(newpat) is updated if the CC mode has been
3232 altered. For targets without SELECT_CC_MODE, this should be
3233 optimized away. */
3236 /* This is always done to propagate i2src into newpat. */
3239 /* Create new version of i2pat if needed; the below PARALLEL
3240 creation needs this to work correctly. */
3244 }
3245 }
3248 {
3249 /* It is possible that the source of I2 or I1 may be performing
3250 an unneeded operation, such as a ZERO_EXTEND of something
3251 that is known to have the high part zero. Handle that case
3252 by letting subst look at the inner insns.
3254 Another way to do this would be to have a function that tries
3255 to simplify a single insn instead of merging two or more
3256 insns. We don't do this because of the potential of infinite
3257 loops and because of the potential extra memory required.
3258 However, doing it the way we are is a bit of a kludge and
3259 doesn't catch all cases.
3261 But only do this if -fexpensive-optimizations since it slows
3262 things down and doesn't usually win.
3264 This is not done in the COMPARE case above because the
3265 unmodified I2PAT is used in the PARALLEL and so a pattern
3266 with a modified I2SRC would not match. */
3269 {
3270 /* Pass pc_rtx so no substitutions are done, just
3271 simplifications. */
3273 {
3276 }
3280 }
3285 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3286 copy of I2SRC each time we substitute it, in order to avoid creating
3287 self-referential RTL when we will be substituting I1SRC for I1DEST
3288 later. Likewise if I0 feeds into I2, either directly or indirectly
3289 through I1, and I0DEST is in I0SRC. */
3296 /* Record whether I2's body now appears within I3's body. */
3298 }
3300 /* If we already got a failure, don't try to do more. Otherwise, try to
3301 substitute I1 if we have it. */
3304 {
3305 /* Check that an autoincrement side-effect on I1 has not been lost.
3306 This happens if I1DEST is mentioned in I2 and dies there, and
3307 has disappeared from the new pattern. */
3309 && i1_feeds_i2_n
3312 /* Before we can do this substitution, we must redo the test done
3313 above (see detailed comments there) that ensures I1DEST isn't
3314 mentioned in any SETs in NEWPAT that are field assignments. */
3317 {
3320 }
3325 /* If the following substitution will modify I1SRC, make a copy of it
3326 for the case where it is substituted for I1DEST in I2PAT later. */
3330 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3331 copy of I1SRC each time we substitute it, in order to avoid creating
3332 self-referential RTL when we will be substituting I0SRC for I0DEST
3333 later. */
3338 /* Record whether I1's body now appears within I3's body. */
3340 }
3342 /* Likewise for I0 if we have it. */
3345 {
3352 {
3355 }
3357 /* If the following substitution will modify I0SRC, make a copy of it
3358 for the case where it is substituted for I0DEST in I1PAT later. */
3361 /* And a copy for I0DEST in I2PAT substitution. */
3370 }
3372 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3373 to count all the ways that I2SRC and I1SRC can be used. */
3384 /* Fail if we tried to make a new register. */
3386 /* Fail if we couldn't do something and have a CLOBBER. */
3388 /* Fail if this new pattern is a MULT and we didn't have one before
3389 at the outer level. */
3392 {
3395 }
3397 /* If the actions of the earlier insns must be kept
3398 in addition to substituting them into the latest one,
3399 we must make a new PARALLEL for the latest insn
3400 to hold additional the SETs. */
3403 {
3405 combine_extras++;
3408 {
3414 }
3415 else
3416 {
3421 }
3427 {
3433 }
3435 {
3444 }
3445 }
3447 validate_replacement:
3449 /* Note which hard regs this insn has as inputs. */
3452 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3453 consider splitting this pattern, we might need these clobbers. */
3456 {
3462 }
3464 /* We have recognized nothing yet. */
3467 /* See if this is a PARALLEL of two SETs where one SET's destination is
3468 a register that is unused and this isn't marked as an instruction that
3469 might trap in an EH region. In that case, we just need the other SET.
3470 We prefer this over the PARALLEL.
3472 This can occur when simplifying a divmod insn. We *must* test for this
3473 case here because the code below that splits two independent SETs doesn't
3474 handle this case correctly when it updates the register status.
3476 It's pointless doing this if we originally had two sets, one from
3477 i3, and one from i2. Combining then splitting the parallel results
3478 in the original i2 again plus an invalid insn (which we delete).
3479 The net effect is only to move instructions around, which makes
3480 debug info less accurate. */
3485 {
3496 {
3499 }
3508 {
3514 }
3518 }
3520 /* Is the result of combination a valid instruction? */
3524 /* If we were combining three insns and the result is a simple SET
3525 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3526 insns. There are two ways to do this. It can be split using a
3527 machine-specific method (like when you have an addition of a large
3528 constant) or by combine in the function find_split_point. */
3532 {
3536 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3537 use I2DEST as a scratch register will help. In the latter case,
3538 convert I2DEST to the mode of the source of NEWPAT if we can. */
3542 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3543 inputs of NEWPAT. */
3545 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3546 possible to try that as a scratch reg. This would require adding
3547 more code to make it work though. */
3550 {
3553 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3554 (temporarily, until we are committed to this instruction
3555 combination) does not work: for example, any call to nonzero_bits
3556 on the register (from a splitter in the MD file, for example)
3557 will get the old information, which is invalid.
3559 Since nowadays we can create registers during combine just fine,
3560 we should just create a new one here, not reuse i2dest. */
3562 /* First try to split using the original register as a
3563 scratch register. */
3567 i2dest)));
3570 /* If that didn't work, try changing the mode of I2DEST if
3571 we can. */
3576 {
3578 rtx ni2dest;
3582 else
3583 {
3586 }
3588 parallel = (gen_rtx_PARALLEL
3592 ni2dest))));
3597 {
3605 }
3606 }
3609 }
3611 /* If recog_for_combine has discarded clobbers, try to use them
3612 again for the split. */
3614 {
3617 }
3620 {
3625 }
3629 {
3639 /* If I2 or I3 has multiple SETs, we won't know how to track
3640 register status, so don't use these insns. If I2's destination
3641 is used between I2 and I3, we also can't use these insns. */
3651 /* It is possible that both insns now set the destination of I3.
3652 If so, we must show an extra use of it. */
3655 {
3674 }
3675 }
3677 /* If we can split it and use I2DEST, go ahead and see if that
3678 helps things be recognized. Verify that none of the registers
3679 are set between I2 and I3. */
3683 /* We need I2DEST in the proper mode. If it is a hard register
3684 or the only use of a pseudo, we can change its mode.
3685 Make sure we don't change a hard register to have a mode that
3686 isn't valid for it, or change the number of registers. */
3693 /* We can't overwrite I2DEST if its value is still used by
3694 NEWPAT. */
3696 {
3705 /* *SPLIT may be part of I2SRC, so make sure we have the
3706 original expression around for later debug processing.
3707 We should not need I2SRC any more in other cases. */
3710 else
3713 /* Get NEWDEST as a register in the proper mode. We have already
3714 validated that we can do this. */
3716 {
3719 else
3720 {
3723 }
3724 }
3726 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3727 an ASHIFT. This can occur if it was inside a PLUS and hence
3728 appeared to be a memory address. This is a kludge. */
3733 {
3736 /* Update split_code because we may not have a multiply
3737 anymore. */
3739 }
3741 /* Similarly for (plus (mult FOO (const_int pow2))). */
3747 {
3751 /* Update split_code because we may not have a multiply
3752 anymore. */
3754 }
3756 #ifdef INSN_SCHEDULING
3757 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3758 be written as a ZERO_EXTEND. */
3760 {
3761 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3762 what it really is. */
3767 else
3770 }
3771 #endif
3773 /* Attempt to split binary operators using arithmetic identities. */
3777 {
3784 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3786 {
3791 }
3792 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3799 {
3805 /* Split both "((X op Y) op X) op Y" and
3806 "((X op Y) op Y) op X" as "T op T" where T is
3807 "X op Y". */
3810 {
3815 }
3816 /* Split "((X op X) op Y) op Y)" as "T op T" where
3817 T is "X op Y". */
3819 {
3825 }
3826 }
3827 }
3830 {
3833 }
3837 /* recog_for_combine might have added CLOBBERs to newi2pat.
3838 Make sure NEWPAT does not depend on the clobbered regs. */
3842 {
3845 {
3848 }
3849 }
3851 /* If the split point was a MULT and we didn't have one before,
3852 don't use one now. */
3855 }
3856 }
3858 /* Check for a case where we loaded from memory in a narrow mode and
3859 then sign extended it, but we need both registers. In that case,
3860 we have a PARALLEL with both loads from the same memory location.
3861 We can split this into a load from memory followed by a register-register
3862 copy. This saves at least one insn, more if register allocation can
3863 eliminate the copy.
3865 We cannot do this if the destination of the first assignment is a
3866 condition code register or cc0. We eliminate this case by making sure
3867 the SET_DEST and SET_SRC have the same mode.
3869 We cannot do this if the destination of the second assignment is
3870 a register that we have already assumed is zero-extended. Similarly
3871 for a SUBREG of such a register. */
3906 {
3907 rtx ni2dest;
3921 }
3923 /* Similarly, check for a case where we have a PARALLEL of two independent
3924 SETs but we started with three insns. In this case, we can do the sets
3925 as two separate insns. This case occurs when some SET allows two
3926 other insns to combine, but the destination of that SET is still live.
3928 Also do this if we started with two insns and (at least) one of the
3929 resulting sets is a noop; this noop will be deleted later. */
3948 {
3952 /* Normally, it doesn't matter which of the two is done first,
3953 but the one that references cc0 can't be the second, and
3954 one which uses any regs/memory set in between i2 and i3 can't
3955 be first. The PARALLEL might also have been pre-existing in i3,
3956 so we need to make sure that we won't wrongly hoist a SET to i2
3957 that would conflict with a death note present in there. */
3965 /* If I3 is a jump, ensure that set0 is a jump so that
3966 we do not create invalid RTL. */
3968 )
3969 {
3972 }
3980 /* If I3 is a jump, ensure that set1 is a jump so that
3981 we do not create invalid RTL. */
3983 )
3984 {
3987 }
3988 else
3989 {
3992 }
3997 {
3998 /* recog_for_combine might have added CLOBBERs to newi2pat.
3999 Make sure NEWPAT does not depend on the clobbered regs. */
4001 {
4004 {
4007 {
4010 }
4011 }
4012 }
4015 }
4016 }
4018 /* If it still isn't recognized, fail and change things back the way they
4019 were. */
4021 /* Is the result a reasonable ASM_OPERANDS? */
4023 {
4026 }
4028 /* If we had to change another insn, make sure it is valid also. */
4030 {
4038 {
4041 }
4042 }
4044 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4045 they are adjacent to each other or not. */
4047 {
4051 {
4054 }
4055 }
4057 /* Only allow this combination if insn_rtx_costs reports that the
4058 replacement instructions are cheaper than the originals. */
4060 {
4063 }
4066 {
4071 {
4076 /* Temporarily revert mode back. */
4080 {
4081 /* If we used i2dest as a scratch register with a
4082 different mode, substitute it for the original
4083 i2src while its original mode is temporarily
4084 restored, and then clear i2scratch so that we don't
4085 do it again later. */
4087 this_basic_block);
4089 /* Put back the new mode. */
4091 }
4092 else
4093 {
4098 {
4101 }
4102 else
4103 {
4110 }
4112 /* We're dealing with a reg that changed mode but not
4113 meaning, so we want to turn it into a subreg for
4114 the new mode. However, because of REG sharing and
4115 because its mode had already changed, we have to do
4116 it in two steps. First, replace any debug uses of
4117 reg, with its original mode temporarily restored,
4118 with this copy we have created; then, replace the
4119 copy with the SUBREG of the original shared reg,
4120 once again changed to the new mode. */
4122 this_basic_block);
4126 this_basic_block);
4127 }
4128 }
4129 }
4131 /* If we will be able to accept this, we have made a
4132 change to the destination of I3. This requires us to
4133 do a few adjustments. */
4136 {
4139 }
4141 /* We now know that we can do this combination. Merge the insns and
4142 update the status of registers and LOG_LINKS. */
4145 {
4150 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4151 ensure that they are still valid. Then add any non-duplicate
4152 notes added by recog_for_combine. */
4154 {
4163 /* Simply drop equal note since it may be no longer valid
4164 for other_insn. It may be possible to record that CC
4165 register is changed and only discard those notes, but
4166 in practice it's unnecessary complication and doesn't
4167 give any meaningful improvement.
4169 See PR78559. */
4173 }
4177 NULL_RTX);
4178 }
4181 {
4184 rtx ni2dest;
4186 /* I3 now uses what used to be its destination and which is now
4187 I2's destination. This requires us to do a few adjustments. */
4191 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4192 so we still will.
4194 However, some later insn might be using I2's dest and have
4195 a LOG_LINK pointing at I3. We must remove this link.
4196 The simplest way to remove the link is to point it at I1,
4197 which we know will be a NOTE. */
4199 /* newi2pat is usually a SET here; however, recog_for_combine might
4200 have added some clobbers. */
4203 else
4210 {
4213 {
4219 }
4220 }
4221 }
4223 {
4228 /* Compute which registers we expect to eliminate. newi2pat may be setting
4229 either i3dest or i2dest, so we must check it. */
4232 || !i2dest_killed
4234 /* For i1, we need to compute both local elimination and global
4235 elimination information with respect to newi2pat because i1dest
4236 may be the same as i3dest, in which case newi2pat may be setting
4237 i1dest. Global information is used when distributing REG_DEAD
4238 note for i2 and i3, in which case it does matter if newi2pat sets
4239 i1dest or not.
4241 Local information is used when distributing REG_DEAD note for i1,
4242 in which case it doesn't matter if newi2pat sets i1dest or not.
4243 See PR62151, if we have four insns combination:
4244 i0: r0 <- i0src
4245 i1: r1 <- i1src (using r0)
4246 REG_DEAD (r0)
4247 i2: r0 <- i2src (using r1)
4248 i3: r3 <- i3src (using r0)
4249 ix: using r0
4250 From i1's point of view, r0 is eliminated, no matter if it is set
4251 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4252 should be discarded.
4254 Note local information only affects cases in forms like "I1->I2->I3",
4255 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4256 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4257 i0dest anyway. */
4259 || !i1dest_killed
4264 /* Same case as i1. */
4271 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4272 clear them. */
4280 /* Ensure that we do not have something that should not be shared but
4281 occurs multiple times in the new insns. Check this by first
4282 resetting all the `used' flags and then copying anything is shared. */
4306 {
4309 {
4311 {
4312 /* I2SRC must still be meaningful at this point. Some
4313 splitting operations can invalidate I2SRC, but those
4314 operations do not apply to calls. */
4318 }
4325 }
4326 }
4331 /* We had one special case above where I2 had more than one set and
4332 we replaced a destination of one of those sets with the destination
4333 of I3. In that case, we have to update LOG_LINKS of insns later
4334 in this basic block. Note that this (expensive) case is rare.
4336 Also, in this case, we must pretend that all REG_NOTEs for I2
4337 actually came from I3, so that REG_UNUSED notes from I2 will be
4338 properly handled. */
4341 {
4350 temp_insn
4360 {
4365 }
4366 else
4369 }
4377 {
4380 this_basic_block);
4383 }
4384 else
4385 {
4388 this_basic_block);
4390 }
4393 {
4398 this_basic_block);
4400 }
4403 {
4408 this_basic_block);
4410 }
4412 /* Get death notes for everything that is now used in either I3 or
4413 I2 and used to die in a previous insn. If we built two new
4414 patterns, move from I1 to I2 then I2 to I3 so that we get the
4415 proper movement on registers that I2 modifies. */
4421 else
4427 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4444 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4445 know these are REG_UNUSED and want them to go to the desired insn,
4446 so we always pass it as i3. */
4450 NULL_RTX);
4454 NULL_RTX);
4456 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4457 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4458 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4459 in that case, it might delete I2. Similarly for I2 and I1.
4460 Show an additional death due to the REG_DEAD note we make here. If
4461 we discard it in distribute_notes, we will decrement it again. */
4464 {
4469 else
4472 }
4475 {
4480 else
4483 }
4486 {
4491 else
4494 }
4497 {
4502 else
4505 }
4513 {
4518 /* The insn that used to set this register doesn't exist, and
4519 this life of the register may not exist either. See if one of
4520 I3's links points to an insn that sets I2DEST. If it does,
4521 that is now the last known value for I2DEST. If we don't update
4522 this and I2 set the register to a value that depended on its old
4523 contents, we will get confused. If this insn is used, thing
4524 will be set correctly in combine_instructions. */
4532 /* If the reg formerly set in I2 died only once and that was in I3,
4533 zero its use count so it won't make `reload' do any work. */
4536 && ! i2dest_in_i2src
4539 }
4542 {
4555 && ! i1dest_in_i1src
4558 }
4561 {
4574 && ! i0dest_in_i0src
4577 }
4579 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4580 been made to this insn. The order is important, because newi2pat
4581 can affect nonzero_bits of newpat. */
4585 }
4588 {
4590 {
4593 }
4595 }
4598 {
4600 {
4603 }
4605 }
4608 {
4610 {
4613 }
4615 }
4618 {
4620 {
4623 }
4625 }
4628 {
4630 {
4633 }
4635 }
4637 /* Set new_direct_jump_p if a new return or simple jump instruction
4638 has been created. Adjust the CFG accordingly. */
4640 {
4644 }
4649 {
4652 }
4656 {
4662 }
4667 {
4673 }
4675 /* A noop might also need cleaning up of CFG, if it comes from the
4676 simplification of a jump. */
4681 {
4684 }
4691 {
4694 }
4696 combine_successes++;
4703 else
4705 }
4706 \f
4707 /* Get a marker for undoing to the current state. */
4711 {
4713 }
4715 /* Undo the modifications up to the marker. */
4717 static void
4719 {
4723 {
4728 {
4743 }
4747 }
4750 }
4752 /* Undo all the modifications recorded in undobuf. */
4754 static void
4756 {
4758 }
4760 /* We've committed to accepting the changes we made. Move all
4761 of the undos to the free list. */
4763 static void
4765 {
4769 {
4773 }
4775 }
4776 \f
4777 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4778 where we have an arithmetic expression and return that point. LOC will
4779 be inside INSN.
4781 try_combine will call this function to see if an insn can be split into
4782 two insns. */
4786 {
4795 /* First special-case some codes. */
4797 {
4799 #ifdef INSN_SCHEDULING
4800 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4801 point. */
4804 #endif
4808 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4809 using LO_SUM and HIGH. */
4812 {
4820 }
4822 /* If we have a PLUS whose second operand is a constant and the
4823 address is not valid, perhaps will can split it up using
4824 the machine-specific way to split large constants. We use
4825 the first pseudo-reg (one of the virtual regs) as a placeholder;
4826 it will not remain in the result. */
4831 {
4834 subst_insn);
4836 /* This should have produced two insns, each of which sets our
4837 placeholder. If the source of the second is a valid address,
4838 we can make put both sources together and make a split point
4839 in the middle. */
4852 && memory_address_addr_space_p
4855 {
4859 /* Replace the placeholder in SRC2 with SRC1. If we can
4860 find where in SRC2 it was placed, that can become our
4861 split point and we can replace this address with SRC2.
4862 Just try two obvious places. */
4873 {
4876 }
4877 }
4879 /* If that didn't work, perhaps the first operand is complex and
4880 needs to be computed separately, so make a split point there.
4881 This will occur on machines that just support REG + CONST
4882 and have a constant moved through some previous computation. */
4888 }
4890 /* If we have a PLUS whose first operand is complex, try computing it
4891 separately by making a split there. */
4902 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4903 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4904 we need to put the operand into a register. So split at that
4905 point. */
4915 /* See if we can split SET_SRC as it stands. */
4920 /* See if we can split SET_DEST as it stands. */
4925 /* See if this is a bitfield assignment with everything constant. If
4926 so, this is an IOR of an AND, so split it into that. */
4936 {
4942 unsigned HOST_WIDE_INT mask
4944 rtx or_mask;
4953 else
4954 {
4960 or_mask));
4961 }
4968 }
4970 /* Otherwise, see if this is an operation that we can split into two.
4971 If so, try to split that. */
4975 {
4977 /* If we are AND'ing with a large constant that is only a single
4978 bit and the result is only being used in a context where we
4979 need to know if it is zero or nonzero, replace it with a bit
4980 extraction. This will avoid the large constant, which might
4981 have taken more than one insn to make. If the constant were
4982 not a valid argument to the AND but took only one insn to make,
4983 this is no worse, but if it took more than one insn, it will
4984 be better. */
4994 {
4999 {
5002 }
5003 }
5007 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5008 is known to be on, this can be converted into a NEG of a shift. */
5014 {
5026 }
5032 /* We can't optimize if either mode is a partial integer
5033 mode as we don't know how many bits are significant
5034 in those modes. */
5048 {
5056 }
5061 }
5065 {
5068 /* For unsigned, we have a choice of a shift followed by an
5069 AND or two shifts. Use two shifts for field sizes where the
5070 constant might be too large. We assume here that we can
5071 always at least get 8-bit constants in an AND insn, which is
5072 true for every current RISC. */
5075 {
5076 unsigned HOST_WIDE_INT mask
5080 gen_rtx_LSHIFTRT
5088 }
5089 else
5090 {
5092 gen_rtx_fmt_ee
5103 }
5104 }
5106 /* See if this is a simple operation with a constant as the second
5107 operand. It might be that this constant is out of range and hence
5108 could be used as a split point. */
5116 /* Finally, see if this is a simple operation with its first operand
5117 not in a register. The operation might require this operand in a
5118 register, so return it as a split point. We can always do this
5119 because if the first operand were another operation, we would have
5120 already found it as a split point. */
5129 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5130 it is better to write this as (not (ior A B)) so we can split it.
5131 Similarly for IOR. */
5133 {
5141 }
5143 /* Many RISC machines have a large set of logical insns. If the
5144 second operand is a NOT, put it first so we will try to split the
5145 other operand first. */
5147 {
5151 }
5156 /* Canonicalization can produce (minus A (mult B C)), where C is a
5157 constant. It may be better to try splitting (plus (mult B -C) A)
5158 instead if this isn't a multiply by a power of two. */
5162 {
5170 mode)),
5173 }
5175 /* Split at a multiply-accumulate instruction. However if this is
5176 the SET_SRC, we likely do not have such an instruction and it's
5177 worthless to try this split. */
5186 }
5188 /* Otherwise, select our actions depending on our rtx class. */
5190 {
5196 /* fall through */
5204 /* fall through */
5206 /* Some machines have (and (shift ...) ...) insns. If X is not
5207 an AND, but XEXP (X, 0) is, use it as our split point. */
5217 /* Otherwise, we don't have a split point. */
5219 }
5220 }
5221 \f
5222 /* Throughout X, replace FROM with TO, and return the result.
5223 The result is TO if X is FROM;
5224 otherwise the result is X, but its contents may have been modified.
5225 If they were modified, a record was made in undobuf so that
5226 undo_all will (among other things) return X to its original state.
5228 If the number of changes necessary is too much to record to undo,
5229 the excess changes are not made, so the result is invalid.
5230 The changes already made can still be undone.
5231 undobuf.num_undo is incremented for such changes, so by testing that
5232 the caller can tell whether the result is valid.
5234 `n_occurrences' is incremented each time FROM is replaced.
5236 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5238 IN_COND is nonzero if we are at the top level of a condition.
5240 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5241 by copying if `n_occurrences' is nonzero. */
5243 static rtx
5245 {
5250 rtx new_rtx;
5252 /* Two expressions are equal if they are identical copies of a shared
5253 RTX or if they are both registers with the same register number
5254 and mode. */
5256 #define COMBINE_RTX_EQUAL_P(X,Y) \
5257 ((X) == (Y) \
5258 || (REG_P (X) && REG_P (Y) \
5259 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5261 /* Do not substitute into clobbers of regs -- this will never result in
5262 valid RTL. */
5267 {
5268 n_occurrences++;
5270 }
5272 /* If X and FROM are the same register but different modes, they
5273 will not have been seen as equal above. However, the log links code
5274 will make a LOG_LINKS entry for that case. If we do nothing, we
5275 will try to rerecognize our original insn and, when it succeeds,
5276 we will delete the feeding insn, which is incorrect.
5278 So force this insn not to match in this (rare) case. */
5283 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5284 of which may contain things that can be combined. */
5288 /* It is possible to have a subexpression appear twice in the insn.
5289 Suppose that FROM is a register that appears within TO.
5290 Then, after that subexpression has been scanned once by `subst',
5291 the second time it is scanned, TO may be found. If we were
5292 to scan TO here, we would find FROM within it and create a
5293 self-referent rtl structure which is completely wrong. */
5297 /* Parallel asm_operands need special attention because all of the
5298 inputs are shared across the arms. Furthermore, unsharing the
5299 rtl results in recognition failures. Failure to handle this case
5300 specially can result in circular rtl.
5302 Solve this by doing a normal pass across the first entry of the
5303 parallel, and only processing the SET_DESTs of the subsequent
5304 entries. Ug. */
5309 {
5312 /* If this substitution failed, this whole thing fails. */
5320 {
5326 {
5329 /* If this substitution failed, this whole thing fails. */
5335 }
5336 }
5337 }
5338 else
5339 {
5343 /* We don't need to process a SET_DEST that is a register, CC0,
5344 or PC, so set up to skip this common case. All other cases
5345 where we want to suppress replacing something inside a
5346 SET_SRC are handled via the IN_DEST operand. */
5353 /* Trying to simplify the operands of a widening MULT is not likely
5354 to create RTL matching a machine insn. */
5366 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5367 constant. */
5372 {
5374 {
5377 {
5379 {
5382 n_occurrences++;
5383 }
5384 else
5385 {
5387 unique_copy);
5389 /* If this substitution failed, this whole thing
5390 fails. */
5394 }
5397 }
5398 }
5400 {
5401 /* If this is a register being set, ignore it. */
5408 ;
5411 {
5412 /* In general, don't install a subreg involving two
5413 modes not tieable. It can worsen register
5414 allocation, and can even make invalid reload
5415 insns, since the reg inside may need to be copied
5416 from in the outside mode, and that may be invalid
5417 if it is an fp reg copied in integer mode.
5419 We allow two exceptions to this: It is valid if
5420 it is inside another SUBREG and the mode of that
5421 SUBREG and the mode of the inside of TO is
5422 tieable and it is valid if X is a SET that copies
5423 FROM to CC0. */
5431 && (!HAVE_cc0
5446 n_occurrences++;
5447 }
5448 else
5449 /* If we are in a SET_DEST, suppress most cases unless we
5450 have gone inside a MEM, in which case we want to
5451 simplify the address. We assume here that things that
5452 are actually part of the destination have their inner
5453 parts in the first expression. This is true for SUBREG,
5454 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5455 things aside from REG and MEM that should appear in a
5456 SET_DEST. */
5458 (((in_dest
5464 unique_copy);
5466 /* If we found that we will have to reject this combination,
5467 indicate that by returning the CLOBBER ourselves, rather than
5468 an expression containing it. This will speed things up as
5469 well as prevent accidents where two CLOBBERs are considered
5470 to be equal, thus producing an incorrect simplification. */
5476 {
5484 }
5487 {
5491 }
5492 else
5494 }
5495 }
5496 }
5498 /* Check if we are loading something from the constant pool via float
5499 extension; in this case we would undo compress_float_constant
5500 optimization and degenerate constant load to an immediate value. */
5504 {
5508 }
5510 /* Try to simplify X. If the simplification changed the code, it is likely
5511 that further simplification will help, so loop, but limit the number
5512 of repetitions that will be performed. */
5515 {
5516 /* If X is sufficiently simple, don't bother trying to do anything
5517 with it. */
5526 /* We no longer know the original mode of operand 0 since we
5527 have changed the form of X) */
5529 }
5532 }
5533 \f
5534 /* If X is a commutative operation whose operands are not in the canonical
5535 order, use substitutions to swap them. */
5537 static void
5539 {
5542 {
5546 }
5547 }
5549 /* Simplify X, a piece of RTL. We just operate on the expression at the
5550 outer level; call `subst' to simplify recursively. Return the new
5551 expression.
5553 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5554 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5555 of a condition. */
5557 static rtx
5560 {
5563 rtx temp;
5566 /* If this is a commutative operation, put a constant last and a complex
5567 expression first. We don't need to do this for comparisons here. */
5570 /* Try to fold this expression in case we have constants that weren't
5571 present before. */
5574 {
5582 {
5585 {
5589 }
5592 }
5605 }
5608 {
5613 }
5615 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5616 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5617 things. Check for cases where both arms are testing the same
5618 condition.
5620 Don't do anything if all operands are very simple. */
5633 {
5638 /* If everything is a comparison, what we have is highly unlikely
5639 to be simpler, so don't use it. */
5642 {
5649 /* Simplify the alternative arms; this may collapse the true and
5650 false arms to store-flag values. Be careful to use copy_rtx
5651 here since true_rtx or false_rtx might share RTL with x as a
5652 result of the if_then_else_cond call above. */
5656 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5657 is unlikely to be simpler. */
5660 {
5663 /* Restarting if we generate a store-flag expression will cause
5664 us to loop. Just drop through in this case. */
5666 /* If the result values are STORE_FLAG_VALUE and zero, we can
5667 just make the comparison operation. */
5678 /* Likewise, we can make the negate of a comparison operation
5679 if the result values are - STORE_FLAG_VALUE and zero. */
5687 mode);
5698 mode);
5699 else
5702 mode,
5703 VOIDmode,
5704 cond,
5705 cop1),
5710 }
5711 }
5712 }
5714 /* First see if we can apply the inverse distributive law. */
5717 {
5721 }
5723 /* If CODE is an associative operation not otherwise handled, see if we
5724 can associate some operands. This can win if they are constants or
5725 if they are logically related (i.e. (a & b) & a). */
5731 {
5733 {
5737 rtx inner;
5739 /* Make sure we pass the constant operand if any as the second
5740 one if this is a commutative operation. */
5748 /* For commutative operations, try the other pair if that one
5749 didn't simplify. */
5751 {
5756 }
5760 }
5761 }
5763 /* A little bit of algebraic simplification here. */
5765 {
5767 /* Ensure that our address has any ASHIFTs converted to MULT in case
5768 address-recognizing predicates are called later. */
5777 /* See if this can be moved to simplify_subreg. */
5780 /* Don't call gen_lowpart if the inner mode
5781 is VOIDmode and we cannot simplify it, as SUBREG without
5782 inner mode is invalid. */
5789 {
5790 rtx temp;
5796 /* If op is known to have all lower bits zero, the result is zero. */
5806 }
5808 /* Don't change the mode of the MEM if that would change the meaning
5809 of the address. */
5816 /* Note that we cannot do any narrowing for non-constants since
5817 we might have been counting on using the fact that some bits were
5818 zero. We now do this in the SET. */
5825 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5826 replaced by (lshiftrt X C). This will convert
5827 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5835 /* If X has only a single bit that might be nonzero, say, bit I, convert
5836 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5837 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5838 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5839 or a SUBREG of one since we'd be making the expression more
5840 complex if it was just a register. */
5846 {
5847 rtx temp1 = simplify_shift_const
5853 /* If all we did was surround TEMP with the two shifts, we
5854 haven't improved anything, so don't use it. Otherwise,
5855 we are better off with TEMP1. */
5860 }
5864 /* We can't handle truncation to a partial integer mode here
5865 because we don't know the real bitsize of the partial
5866 integer mode. */
5875 /* We can truncate a constant value and return it. */
5879 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5880 whose value is a comparison can be replaced with a subreg if
5881 STORE_FLAG_VALUE permits. */
5890 /* (const (const X)) can become (const X). Do it this way rather than
5891 returning the inner CONST since CONST can be shared with a
5892 REG_EQUAL note. */
5898 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5899 can add in an offset. find_split_point will split this address up
5900 again if it doesn't match. */
5907 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5908 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5909 bit-field and can be replaced by either a sign_extend or a
5910 sign_extract. The `and' may be a zero_extend and the two
5911 <c>, -<c> constants may be reversed. */
5926 return simplify_shift_const
5933 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5934 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5935 the bitsize of the mode - 1. This allows simplification of
5936 "a = (b & 8) == 0;" */
5948 /* If we are adding two things that have no bits in common, convert
5949 the addition into an IOR. This will often be further simplified,
5950 for example in cases like ((a & 1) + (a & 2)), which can
5951 become a & 3. */
5956 {
5957 /* Try to simplify the expression further. */
5961 /* If we could, great. If not, do not go ahead with the IOR
5962 replacement, since PLUS appears in many special purpose
5963 address arithmetic instructions. */
5971 }
5973 /* Canonicalize x + x into x << 1. */
5982 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5983 (and <foo> (const_int pow2-1)) */
5993 /* If we have (mult (plus A B) C), apply the distributive law and then
5994 the inverse distributive law to see if things simplify. This
5995 occurs mostly in addresses, often when unrolling loops. */
5998 {
6002 }
6004 /* Try simplify a*(b/c) as (a*b)/c. */
6007 {
6013 }
6017 /* If this is a divide by a power of two, treat it as a shift if
6018 its first operand is a shift. */
6036 /* If the first operand is a condition code, we can't do anything
6037 with it. */
6041 {
6049 /* Simplify our comparison, if possible. */
6052 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6053 if only the low-order bit is possibly nonzero in X (such as when
6054 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6055 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6056 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6057 (plus X 1).
6059 Remove any ZERO_EXTRACT we made when thinking this was a
6060 comparison. It may now be simpler to use, e.g., an AND. If a
6061 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6062 the call to make_compound_operation in the SET case.
6064 Don't apply these optimizations if the caller would
6065 prefer a comparison rather than a value.
6066 E.g., for the condition in an IF_THEN_ELSE most targets need
6067 an explicit comparison. */
6070 ;
6086 {
6090 mode);
6091 }
6098 {
6102 const1_rtx);
6103 }
6111 {
6114 }
6116 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6117 those above. */
6119 ;
6135 {
6139 mode);
6140 }
6148 {
6152 mode);
6153 }
6155 /* If X is 0/1, (eq X 0) is X-1. */
6161 {
6164 }
6166 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6167 one bit that might be nonzero, we can convert (ne x 0) to
6168 (ashift x c) where C puts the bit in the sign bit. Remove any
6169 AND with STORE_FLAG_VALUE when we are done, since we are only
6170 going to test the sign bit. */
6177 {
6183 else
6185 }
6187 /* If the code changed, return a whole new comparison.
6188 We also need to avoid using SUBST in cases where
6189 simplify_comparison has widened a comparison with a CONST_INT,
6190 since in that case the wider CONST_INT may fail the sanity
6191 checks in do_SUBST. */
6198 /* Otherwise, keep this operation, but maybe change its operands.
6199 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6202 }
6212 /* If we are processing SET_DEST, we are done. */
6230 /* If this is a shift by a constant amount, simplify it. */
6238 (HOST_WIDE_INT_1U
6246 }
6249 }
6250 \f
6251 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6253 static rtx
6255 {
6262 rtx temp;
6265 rtx reversed;
6267 /* Simplify storing of the truth value. */
6272 /* Also when the truth value has to be reversed. */
6278 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6279 in it is being compared against certain values. Get the true and false
6280 comparisons and see if that says anything about the value of each arm. */
6286 {
6287 HOST_WIDE_INT nzb;
6293 /* If FALSE_CODE is EQ, swap the codes and arms. */
6296 {
6299 }
6301 /* If we are comparing against zero and the expression being tested has
6302 only a single bit that might be nonzero, that is its value when it is
6303 not equal to zero. Similarly if it is known to be -1 or 0. */
6307 {
6310 }
6314 {
6317 }
6319 /* Now simplify an arm if we know the value of the register in the
6320 branch and it is used in the arm. Be careful due to the potential
6321 of locally-shared RTL. */
6338 }
6340 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6341 reversed, do so to avoid needing two sets of patterns for
6342 subtract-and-branch insns. Similarly if we have a constant in the true
6343 arm, the false arm is the same as the first operand of the comparison, or
6344 the false arm is more complicated than the true arm. */
6357 {
6366 /* It is possible that the conditional has been simplified out. */
6369 }
6371 /* If the two arms are identical, we don't need the comparison. */
6376 /* Convert a == b ? b : a to "a". */
6388 /* Look for cases where we have (abs x) or (neg (abs X)). */
6391 && comparison_p
6398 {
6404 return
6407 mode);
6410 }
6412 /* Look for MIN or MAX. */
6415 && comparison_p
6420 {
6435 }
6437 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6438 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6439 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6440 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6441 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6442 neither 1 or -1, but it isn't worth checking for. */
6445 && comparison_p
6448 {
6464 /* If an identity-zero op is commutative, check whether there
6465 would be a match if we swapped the operands. */
6485 {
6489 }
6501 {
6505 }
6521 {
6525 }
6537 {
6541 }
6544 {
6550 const_true_rtx));
6558 }
6559 }
6561 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6562 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6563 negation of a single bit, we can convert this operation to a shift. We
6564 can actually do this more generally, but it doesn't seem worth it. */
6573 return
6577 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6578 non-zero bit in A is C1. */
6585 {
6592 }
6595 }
6596 \f
6597 /* Simplify X, a SET expression. Return the new expression. */
6599 static rtx
6601 {
6604 machine_mode mode
6609 /* (set (pc) (return)) gets written as (return). */
6613 /* Now that we know for sure which bits of SRC we are using, see if we can
6614 simplify the expression for the object knowing that we only need the
6615 low-order bits. */
6618 {
6621 }
6623 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6624 the comparison result and try to simplify it unless we already have used
6625 undobuf.other_insn. */
6633 {
6642 {
6645 {
6648 }
6649 }
6650 else
6658 {
6662 }
6663 else
6664 {
6669 /* Attempt to simplify CC user. */
6671 {
6675 }
6677 /* Convert X into a no-op move. */
6681 }
6683 /* Simplify our comparison, if possible. */
6686 #ifdef SELECT_CC_MODE
6687 /* If this machine has CC modes other than CCmode, check to see if we
6688 need to use a different CC mode here. */
6697 else
6700 /* If the mode changed, we have to change SET_DEST, the mode in the
6701 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6702 a hard register, just build new versions with the proper mode. If it
6703 is a pseudo, we lose unless it is only time we set the pseudo, in
6704 which case we can safely change its mode. */
6706 {
6708 {
6710 rtx new_dest;
6714 else
6715 {
6718 }
6725 }
6726 }
6729 /* If the code changed, we have to build a new comparison in
6730 undobuf.other_insn. */
6732 {
6741 /* If the only change we made was to change an EQ into an NE or
6742 vice versa, OP0 has only one bit that might be nonzero, and OP1
6743 is zero, check if changing the user of the condition code will
6744 produce a valid insn. If it won't, we can keep the original code
6745 in that insn by surrounding our operation with an XOR. */
6752 {
6757 {
6764 }
6765 }
6766 }
6771 /* Don't generate a compare of a CC with 0, just use that CC. */
6773 {
6776 }
6777 /* Otherwise, if we didn't previously have the same COMPARE we
6778 want, create it from scratch. */
6781 {
6784 }
6785 }
6786 else
6787 {
6788 /* Get SET_SRC in a form where we have placed back any
6789 compound expressions. Then do the checks below. */
6792 }
6794 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6795 and X being a REG or (subreg (reg)), we may be able to convert this to
6796 (set (subreg:m2 x) (op)).
6798 We can always do this if M1 is narrower than M2 because that means that
6799 we only care about the low bits of the result.
6801 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6802 perform a narrower operation than requested since the high-order bits will
6803 be undefined. On machine where it is defined, this transformation is safe
6804 as long as M1 and M2 have the same number of words. */
6813 #ifdef CANNOT_CHANGE_MODE_CLASS
6818 #endif
6822 {
6825 dest));
6829 }
6831 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6832 in SRC. */
6838 {
6842 /* Here we make sure that we don't have a sign bit on. */
6845 {
6848 }
6849 }
6851 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6852 would require a paradoxical subreg. Replace the subreg with a
6853 zero_extend to avoid the reload that would otherwise be required. */
6859 {
6864 }
6866 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6867 are comparing an item known to be 0 or -1 against 0, use a logical
6868 operation instead. Check for one of the arms being an IOR of the other
6869 arm with some value. We compute three terms to be IOR'ed together. In
6870 practice, at most two will be nonzero. Then we do the IOR's. */
6878 && (!HAVE_conditional_move
6884 {
6910 false_rtx);
6916 term3));
6919 }
6921 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6922 whole thing fail. */
6927 else
6928 /* Convert this into a field assignment operation, if possible. */
6930 }
6931 \f
6932 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6933 result. */
6935 static rtx
6937 {
6943 {
6945 /* We can call simplify_and_const_int only if we don't lose
6946 any (sign) bits when converting INTVAL (op1) to
6947 "unsigned HOST_WIDE_INT". */
6951 {
6958 }
6960 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6961 apply the distributive law and then the inverse distributive
6962 law to see if things simplify. */
6964 {
6968 }
6970 {
6974 }
6978 /* If we have (ior (and A B) C), apply the distributive law and then
6979 the inverse distributive law to see if things simplify. */
6982 {
6986 }
6989 {
6993 }
6998 }
7001 }
7002 \f
7003 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7004 operations" because they can be replaced with two more basic operations.
7005 ZERO_EXTEND is also considered "compound" because it can be replaced with
7006 an AND operation, which is simpler, though only one operation.
7008 The function expand_compound_operation is called with an rtx expression
7009 and will convert it to the appropriate shifts and AND operations,
7010 simplifying at each stage.
7012 The function make_compound_operation is called to convert an expression
7013 consisting of shifts and ANDs into the equivalent compound expression.
7014 It is the inverse of this function, loosely speaking. */
7016 static rtx
7018 {
7022 rtx tem;
7025 {
7028 /* FALLTHRU */
7030 /* We can't necessarily use a const_int for a multiword mode;
7031 it depends on implicitly extending the value.
7032 Since we don't know the right way to extend it,
7033 we can't tell whether the implicit way is right.
7035 Even for a mode that is no wider than a const_int,
7036 we can't win, because we need to sign extend one of its bits through
7037 the rest of it, and we don't know which bit. */
7041 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7042 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7043 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7044 reloaded. If not for that, MEM's would very rarely be safe.
7046 Reject MODEs bigger than a word, because we might not be able
7047 to reference a two-register group starting with an arbitrary register
7048 (and currently gen_lowpart might crash for a SUBREG). */
7053 /* Reject MODEs that aren't scalar integers because turning vector
7054 or complex modes into shifts causes problems. */
7060 /* If the inner object has VOIDmode (the only way this can happen
7061 is if it is an ASM_OPERANDS), we can't do anything since we don't
7062 know how much masking to do. */
7071 /* fall through */
7074 /* If the operand is a CLOBBER, just return it. */
7083 /* Reject MODEs that aren't scalar integers because turning vector
7084 or complex modes into shifts causes problems. */
7092 /* This should stay within the object being extracted, fail otherwise. */
7103 }
7104 /* Convert sign extension to zero extension, if we know that the high
7105 bit is not set, as this is easier to optimize. It will be converted
7106 back to cheaper alternative in make_extraction. */
7114 {
7119 /* Make sure this is a profitable operation. */
7126 else
7128 }
7130 /* We can optimize some special cases of ZERO_EXTEND. */
7132 {
7133 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7134 know that the last value didn't have any inappropriate bits
7135 set. */
7143 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7152 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7153 is a comparison and STORE_FLAG_VALUE permits. This is like
7154 the first case, but it works even when GET_MODE (x) is larger
7155 than HOST_WIDE_INT. */
7164 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7174 }
7176 /* If we reach here, we want to return a pair of shifts. The inner
7177 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7178 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7179 logical depending on the value of UNSIGNEDP.
7181 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7182 converted into an AND of a shift.
7184 We must check for the case where the left shift would have a negative
7185 count. This can happen in a case like (x >> 31) & 255 on machines
7186 that can't shift by a constant. On those machines, we would first
7187 combine the shift with the AND to produce a variable-position
7188 extraction. Then the constant of 31 would be substituted in
7189 to produce such a position. */
7193 {
7202 }
7209 else
7210 /* Any other cases we can't handle. */
7213 /* If we couldn't do this for some reason, return the original
7214 expression. */
7219 }
7220 \f
7221 /* X is a SET which contains an assignment of one object into
7222 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7223 or certain SUBREGS). If possible, convert it into a series of
7224 logical operations.
7226 We half-heartedly support variable positions, but do not at all
7227 support variable lengths. */
7229 static const_rtx
7231 {
7232 rtx inner;
7236 machine_mode compute_mode;
7238 /* Loop until we find something we can't simplify. */
7240 {
7243 {
7247 }
7250 {
7255 /* A constant position should stay within the width of INNER. */
7261 {
7269 /* If position is ADJUST - X, new position is X. */
7271 else
7272 {
7277 pos);
7278 }
7279 }
7280 }
7282 /* A SUBREG between two modes that occupy the same numbers of words
7283 can be done by moving the SUBREG to the source. */
7285 /* We need SUBREGs to compute nonzero_bits properly. */
7286 && nonzero_sign_valid
7291 {
7293 gen_lowpart
7297 }
7298 else
7306 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7308 {
7309 machine_mode imode;
7311 /* Don't do anything for vector or complex integral types. */
7315 /* Try to find an integral mode to pun with. */
7322 }
7324 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7328 /* Don't try to compute in too wide unsupported modes. */
7332 /* Now compute the equivalent expression. Make a copy of INNER
7333 for the SET_DEST in case it is a MEM into which we will substitute;
7334 we don't want shared RTL in that case. */
7336 compute_mode);
7340 compute_mode,
7342 compute_mode),
7343 inner);
7348 mask),
7349 pos);
7354 }
7357 }
7358 \f
7359 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7360 it is an RTX that represents the (variable) starting position; otherwise,
7361 POS is the (constant) starting bit position. Both are counted from the LSB.
7363 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7365 IN_DEST is nonzero if this is a reference in the destination of a SET.
7366 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7367 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7368 be used.
7370 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7371 ZERO_EXTRACT should be built even for bits starting at bit 0.
7373 MODE is the desired mode of the result (if IN_DEST == 0).
7375 The result is an RTX for the extraction or NULL_RTX if the target
7376 can't handle it. */
7378 static rtx
7382 {
7383 /* This mode describes the size of the storage area
7384 to fetch the overall value from. Within that, we
7385 ignore the POS lowest bits, etc. */
7387 machine_mode inner_mode;
7388 machine_mode wanted_inner_mode;
7395 HOST_WIDE_INT orig_pos;
7401 {
7402 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7403 consider just the QI as the memory to extract from.
7404 The subreg adds or removes high bits; its mode is
7405 irrelevant to the meaning of this extraction,
7406 since POS and LEN count from the lsb. */
7410 }
7415 {
7416 /* We're extracting the least significant bits of an rtx
7417 (ashift X (const_int C)), where LEN > C. Extract the
7418 least significant (LEN - C) bits of X, giving an rtx
7419 whose mode is MODE, then shift it left C times. */
7425 }
7431 /* See if this can be done without an extraction. We never can if the
7432 width of the field is not the same as that of some integer mode. For
7433 registers, we can only avoid the extraction if the position is at the
7434 low-order bit and this is either not in the destination or we have the
7435 appropriate STRICT_LOW_PART operation available.
7437 For MEM, we can avoid an extract if the field starts on an appropriate
7438 boundary and we can change the mode of the memory reference. */
7448 && (! in_dest
7452 && (pos
7455 /* We can't do this if we are widening INNER_MODE (it
7456 may not be aligned, for one thing). */
7462 {
7463 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7464 field. If the original and current mode are the same, we need not
7465 adjust the offset. Otherwise, we do if bytes big endian.
7467 If INNER is not a MEM, get a piece consisting of just the field
7468 of interest (in this case POS % BITS_PER_WORD must be 0). */
7471 {
7472 HOST_WIDE_INT offset;
7474 /* POS counts from lsb, but make OFFSET count in memory order. */
7477 else
7481 }
7483 {
7485 {
7486 /* We can't call gen_lowpart in a DEST since we
7487 always want a SUBREG (see below) and it would sometimes
7488 return a new hard register. */
7490 {
7491 unsigned int offset
7494 /* Avoid creating invalid subregs, for example when
7495 simplifying (x>>32)&255. */
7500 }
7501 else
7503 }
7504 else
7506 }
7507 else
7509 len >= HOST_BITS_PER_WIDE_INT
7510 ? HOST_WIDE_INT_M1U
7513 /* If this extraction is going into the destination of a SET,
7514 make a STRICT_LOW_PART unless we made a MEM. */
7529 /* If we know that no extraneous bits are set, and that the high
7530 bit is not set, convert the extraction to the cheaper of
7531 sign and zero extension, that are equivalent in these cases. */
7537 {
7541 /* Prefer ZERO_EXTENSION, since it gives more information to
7542 backends. */
7547 }
7549 /* Otherwise, sign- or zero-extend unless we already are in the
7550 proper mode. */
7554 }
7556 /* Unless this is a COMPARE or we have a funny memory reference,
7557 don't do anything with zero-extending field extracts starting at
7558 the low-order bit since they are simple AND operations. */
7563 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7564 if the position is not a constant and the length is not 1. In all
7565 other cases, we would only be going outside our object in cases when
7566 an original shift would have been undefined. */
7575 /* If INNER is not from memory, we want it to have the mode of a register
7576 extraction pattern's structure operand, or word_mode if there is no
7577 such pattern. The same applies to extraction_mode and pos_mode
7578 and their respective operands.
7580 For memory, assume that the desired extraction_mode and pos_mode
7581 are the same as for a register operation, since at present we don't
7582 have named patterns for aligned memory structures. */
7586 {
7590 }
7592 /* Never narrow an object, since that might not be safe. */
7600 else
7601 {
7602 /* Be careful not to go beyond the extracted object and maintain the
7603 natural alignment of the memory. */
7608 }
7613 {
7614 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7615 BITS_BIG_ENDIAN style. If position is constant, compute new
7616 position. Otherwise, build subtraction.
7617 Note that POS is relative to the mode of the original argument.
7618 If it's a MEM we need to recompute POS relative to that.
7619 However, if we're extracting from (or inserting into) a register,
7620 we want to recompute POS relative to wanted_inner_mode. */
7627 else
7628 pos_rtx
7631 pos_rtx);
7632 /* POS may be less than 0 now, but we check for that below.
7633 Note that it can only be less than 0 if !MEM_P (inner). */
7634 }
7636 /* If INNER has a wider mode, and this is a constant extraction, try to
7637 make it smaller and adjust the byte to point to the byte containing
7638 the value. */
7641 && ! pos_rtx
7646 {
7649 /* The computations below will be correct if the machine is big
7650 endian in both bits and bytes or little endian in bits and bytes.
7651 If it is mixed, we must adjust. */
7653 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7654 adjust OFFSET to compensate. */
7659 /* We can now move to the desired byte. */
7670 }
7672 /* If INNER is not memory, get it into the proper mode. If we are changing
7673 its mode, POS must be a constant and smaller than the size of the new
7674 mode. */
7676 {
7677 /* On the LHS, don't create paradoxical subregs implicitely truncating
7678 the register unless TRULY_NOOP_TRUNCATION. */
7681 wanted_inner_mode))
7693 pos_rtx
7695 ? HOST_WIDE_INT_M1U
7699 }
7701 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7702 have to zero extend. Otherwise, we can just use a SUBREG. */
7705 {
7709 /* If we know that no extraneous bits are set, and that the high
7710 bit is not set, convert extraction to cheaper one - either
7711 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7712 cases. */
7720 {
7724 /* Prefer ZERO_EXTENSION, since it gives more information to
7725 backends. */
7729 }
7731 }
7733 /* Make POS_RTX unless we already have it and it is correct. If we don't
7734 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7735 be a CONST_INT. */
7742 /* Make the required operation. See if we can use existing rtx. */
7749 }
7750 \f
7751 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7752 with any other operations in X. Return X without that shift if so. */
7754 static rtx
7756 {
7759 rtx tem;
7762 {
7764 /* This is the shift itself. If it is wide enough, we will return
7765 either the value being shifted if the shift count is equal to
7766 COUNT or a shift for the difference. */
7780 /* If we can safely shift this constant and we find the inner shift,
7781 make a new operation. */
7786 {
7790 }
7795 }
7798 }
7799 \f
7800 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7801 level of the expression and MODE is its mode. IN_CODE is as for
7802 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7803 that should be used when recursing on operands of *X_PTR.
7805 There are two possible actions:
7807 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7808 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7810 - Return a new rtx, which the caller returns directly. */
7812 static rtx
7816 {
7824 rtx tem;
7828 {
7831 }
7833 /* Process depending on the code of this operation. If NEW is set
7834 nonzero, it will be returned. */
7837 {
7839 /* Convert shifts by constants into multiplications if inside
7840 an address. */
7844 {
7850 {
7853 }
7856 }
7865 {
7869 }
7872 {
7876 mode));
7878 }
7879 else
7880 {
7883 }
7893 {
7897 }
7900 {
7904 mode));
7906 }
7907 else
7908 {
7912 }
7915 /* If the second operand is not a constant, we can't do anything
7916 with it. */
7920 /* If the constant is a power of two minus one and the first operand
7921 is a logical right shift, make an extraction. */
7924 {
7928 }
7930 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7935 {
7943 /* If we narrowed the mode when dropping the subreg, then we lose. */
7947 /* If that didn't give anything, see if the AND simplifies on
7948 its own. */
7950 {
7954 }
7955 }
7956 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7962 {
7963 /* Apply the distributive law, and then try to make extractions. */
7970 }
7972 /* If we are have (and (rotate X C) M) and C is larger than the number
7973 of bits in M, this is an extraction. */
7979 {
7985 }
7987 /* On machines without logical shifts, if the operand of the AND is
7988 a logical shift and our mask turns off all the propagated sign
7989 bits, we can replace the logical shift with an arithmetic shift. */
7997 {
8004 make_compound_operation
8007 }
8009 /* If the constant is one less than a power of two, this might be
8010 representable by an extraction even if no shift is present.
8011 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8012 we are in a COMPARE. */
8016 next_code),
8019 /* If we are in a comparison and this is an AND with a power of two,
8020 convert this into the appropriate bit extract. */
8026 next_code),
8029 /* If the one operand is a paradoxical subreg of a register or memory and
8030 the constant (limited to the smaller mode) has only zero bits where
8031 the sub expression has known zero bits, this can be expressed as
8032 a zero_extend. */
8034 {
8035 rtx sub;
8041 {
8045 /* original AND constant with all the known zero bits set */
8048 {
8053 }
8054 }
8055 }
8060 /* If the sign bit is known to be zero, replace this with an
8061 arithmetic shift. */
8066 {
8069 next_code),
8072 }
8074 /* fall through */
8080 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8081 this is a SIGN_EXTRACT. */
8088 {
8095 }
8097 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8098 If so, try to merge the shifts into a SIGN_EXTEND. We could
8099 also do this for some cases of SIGN_EXTRACT, but it doesn't
8100 seem worth the effort; the case checked for occurs on Alpha. */
8117 /* Call ourselves recursively on the inner expression. If we are
8118 narrowing the object and it has a different RTL code from
8119 what it originally did, do this SUBREG as a force_to_mode. */
8120 {
8124 /* If the SUBREG is masking of a logical right shift,
8125 make an extraction. */
8132 {
8141 }
8143 /* If in_code is COMPARE, it isn't always safe to pass it through
8144 to the recursive make_compound_operation call. */
8148 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8149 is (const_int 0), rather than
8150 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8151 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8152 for non-equality comparisons against 0 is not equivalent
8153 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8163 simplified
8171 {
8172 rtx newer
8175 /* If we have something other than a SUBREG, we might have
8176 done an expansion, so rerun ourselves. */
8180 /* force_to_mode can expand compounds. If it just re-expanded the
8181 compound, use gen_lowpart to convert to the desired mode. */
8183 /* Likewise if it re-expanded the compound only partially.
8184 This happens for SUBREG of ZERO_EXTRACT if they extract
8185 the same number of bits. */
8194 }
8198 }
8203 }
8209 }
8211 /* Look at the expression rooted at X. Look for expressions
8212 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8213 Form these expressions.
8215 Return the new rtx, usually just X.
8217 Also, for machines like the VAX that don't have logical shift insns,
8218 try to convert logical to arithmetic shift operations in cases where
8219 they are equivalent. This undoes the canonicalizations to logical
8220 shifts done elsewhere.
8222 We try, as much as possible, to re-use rtl expressions to save memory.
8224 IN_CODE says what kind of expression we are processing. Normally, it is
8225 SET. In a memory address it is MEM. When processing the arguments of
8226 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8227 precisely it is an equality comparison against zero. */
8229 rtx
8231 {
8238 /* Select the code to be used in recursive calls. Once we are inside an
8239 address, we stay there. If we have a comparison, set to COMPARE,
8240 but once inside, go back to our default of SET. */
8248 {
8254 }
8256 /* Now recursively process each operand of this operation. We need to
8257 handle ZERO_EXTEND specially so that we don't lose track of the
8258 inner mode. */
8260 {
8268 }
8273 {
8276 }
8279 {
8282 }
8286 }
8287 \f
8288 /* Given M see if it is a value that would select a field of bits
8289 within an item, but not the entire word. Return -1 if not.
8290 Otherwise, return the starting position of the field, where 0 is the
8291 low-order bit.
8293 *PLEN is set to the length of the field. */
8295 static int
8297 {
8298 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8303 /* Now shift off the low-order zero bits and see if we have a
8304 power of two minus 1. */
8312 }
8313 \f
8314 /* If X refers to a register that equals REG in value, replace these
8315 references with REG. */
8316 static rtx
8318 {
8326 {
8359 /* FALLTHRU */
8363 {
8367 else
8369 }
8371 /* fall through */
8378 {
8381 {
8383 {
8386 }
8388 }
8389 }
8391 {
8394 {
8397 {
8399 {
8402 }
8404 }
8405 }
8406 }
8409 }
8412 }
8414 /* Return X converted to MODE. If the value is already truncated to
8415 MODE we can just return a subreg even though in the general case we
8416 would need an explicit truncation. */
8418 static rtx
8420 {
8425 {
8426 /* Bit-cast X into an integer mode. */
8431 }
8434 }
8436 /* See if X can be simplified knowing that we will only refer to it in
8437 MODE and will only refer to those bits that are nonzero in MASK.
8438 If other bits are being computed or if masking operations are done
8439 that select a superset of the bits in MASK, they can sometimes be
8440 ignored.
8442 Return a possibly simplified expression, but always convert X to
8443 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8445 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8446 are all off in X. This is used when X will be complemented, by either
8447 NOT, NEG, or XOR. */
8449 static rtx
8452 {
8455 machine_mode op_mode;
8459 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8460 code below will do the wrong thing since the mode of such an
8461 expression is VOIDmode.
8463 Also do nothing if X is a CLOBBER; this can happen if X was
8464 the return value from a call to gen_lowpart. */
8468 /* We want to perform the operation in its present mode unless we know
8469 that the operation is valid in MODE, in which case we do the operation
8470 in MODE. */
8475 /* It is not valid to do a right-shift in a narrower mode
8476 than the one it came in with. */
8481 /* Truncate MASK to fit OP_MODE. */
8485 /* When we have an arithmetic operation, or a shift whose count we
8486 do not know, we need to assume that all bits up to the highest-order
8487 bit in MASK will be needed. This is how we form such a mask. */
8490 else
8494 /* Determine what bits of X are guaranteed to be (non)zero. */
8497 /* If none of the bits in X are needed, return a zero. */
8501 /* If X is a CONST_INT, return a new one. Do this here since the
8502 test below will fail. */
8504 {
8507 else
8508 {
8511 }
8512 }
8514 /* If X is narrower than MODE and we want all the bits in X's mode, just
8515 get X in the proper mode. */
8520 /* We can ignore the effect of a SUBREG if it narrows the mode or
8521 if the constant masks to zero all the bits the mode doesn't have. */
8531 /* The arithmetic simplifications here only work for scalar integer modes. */
8536 {
8538 /* If X is a (clobber (const_int)), return it since we know we are
8539 generating something that won't match. */
8552 /* Similarly for a truncate. */
8556 /* If this is an AND with a constant, convert it into an AND
8557 whose constant is the AND of that constant with MASK. If it
8558 remains an AND of MASK, delete it since it is redundant. */
8561 {
8565 /* If X is still an AND, see if it is an AND with a mask that
8566 is just some low-order bits. If so, and it is MASK, we don't
8567 need it. */
8574 /* If it remains an AND, try making another AND with the bits
8575 in the mode mask that aren't in MASK turned on. If the
8576 constant in the AND is wide enough, this might make a
8577 cheaper constant. */
8582 {
8583 unsigned HOST_WIDE_INT cval
8586 rtx y;
8593 }
8596 }
8601 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8602 low-order bits (as in an alignment operation) and FOO is already
8603 aligned to that boundary, mask C1 to that boundary as well.
8604 This may eliminate that PLUS and, later, the AND. */
8606 {
8610 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8611 number, sign extend it. */
8624 }
8626 /* fall through */
8629 /* Substituting into the operands of a widening MULT is not likely to
8630 create RTL matching a machine insn. */
8640 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8641 most significant bit in MASK since carries from those bits will
8642 affect the bits we are interested in. */
8647 /* If X is (minus C Y) where C's least set bit is larger than any bit
8648 in the mask, then we may replace with (neg Y). */
8651 {
8655 }
8657 /* Similarly, if C contains every bit in the fuller_mask, then we may
8658 replace with (not Y). */
8661 {
8665 }
8672 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8673 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8674 operation which may be a bitfield extraction. Ensure that the
8675 constant we form is not wider than the mode of X. */
8687 {
8696 }
8698 binop:
8699 /* For most binary operations, just propagate into the operation and
8700 change the mode if we have an operation of that mode. */
8705 /* If we ended up truncating both operands, truncate the result of the
8706 operation instead. */
8709 {
8712 }
8722 /* For left shifts, do the same, but just for the first operand.
8723 However, we cannot do anything with shifts where we cannot
8724 guarantee that the counts are smaller than the size of the mode
8725 because such a count will have a different meaning in a
8726 wider mode. */
8736 /* If the shift count is a constant and we can do arithmetic in
8737 the mode of the shift, refine which bits we need. Otherwise, use the
8738 conservative form of the mask. */
8744 else
8756 /* Here we can only do something if the shift count is a constant,
8757 this shift constant is valid for the host, and we can do arithmetic
8758 in OP_MODE. */
8764 {
8768 /* Select the mask of the bits we need for the shift operand. */
8771 /* We can only change the mode of the shift if we can do arithmetic
8772 in the mode of the shift and INNER_MASK is no wider than the
8773 width of X's mode. */
8781 }
8783 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8784 shift and AND produces only copies of the sign bit (C2 is one less
8785 than a power of two), we can do this with just a shift. */
8789 /* The shift puts one of the sign bit copies in the least significant
8790 bit. */
8795 /* Number of bits left after the shift must be more than the mask
8796 needs. */
8799 /* Must be more sign bit copies than the mask needs. */
8809 /* If we are just looking for the sign bit, we don't need this shift at
8810 all, even if it has a variable count. */
8814 /* If this is a shift by a constant, get a mask that contains those bits
8815 that are not copies of the sign bit. We then have two cases: If
8816 MASK only includes those bits, this can be a logical shift, which may
8817 allow simplifications. If MASK is a single-bit field not within
8818 those bits, we are requesting a copy of the sign bit and hence can
8819 shift the sign bit to the appropriate location. */
8823 {
8826 /* If the considered data is wider than HOST_WIDE_INT, we can't
8827 represent a mask for all its bits in a single scalar.
8828 But we only care about the lower bits, so calculate these. */
8831 {
8834 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8835 is the number of bits a full-width mask would have set.
8836 We need only shift if these are fewer than nonzero can
8837 hold. If not, we must keep all bits set in nonzero. */
8842 + HOST_BITS_PER_WIDE_INT
8844 }
8845 else
8846 {
8849 }
8852 {
8857 }
8860 {
8861 x = simplify_shift_const
8867 }
8868 }
8870 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8871 even if the shift count isn't a constant. */
8876 shiftrt:
8878 /* If this is a zero- or sign-extension operation that just affects bits
8879 we don't care about, remove it. Be sure the call above returned
8880 something that is still a shift. */
8890 next_select);
8896 /* If the shift count is constant and we can do computations
8897 in the mode of X, compute where the bits we care about are.
8898 Otherwise, we can't do anything. Don't change the mode of
8899 the shift or propagate MODE into the shift, though. */
8902 {
8912 }
8916 /* If we just want the low-order bit, the NEG isn't needed since it
8917 won't change the low-order bit. */
8921 /* We need any bits less significant than the most significant bit in
8922 MASK since carries from those bits will affect the bits we are
8923 interested in. */
8928 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8929 same as the XOR case above. Ensure that the constant we form is not
8930 wider than the mode of X. */
8938 {
8947 }
8949 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8950 use the full mask inside the NOT. */
8953 unop:
8956 next_select));
8962 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8963 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8964 which is equal to STORE_FLAG_VALUE. */
8976 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8977 written in a narrower mode. We play it safe and do not do so. */
8993 }
8995 /* Ensure we return a value of the proper mode. */
8997 }
8998 \f
8999 /* Return nonzero if X is an expression that has one of two values depending on
9000 whether some other value is zero or nonzero. In that case, we return the
9001 value that is being tested, *PTRUE is set to the value if the rtx being
9002 returned has a nonzero value, and *PFALSE is set to the other alternative.
9004 If we return zero, we set *PTRUE and *PFALSE to X. */
9006 static rtx
9008 {
9014 /* If we are comparing a value against zero, we are done. */
9017 {
9021 }
9023 /* If this is a unary operation whose operand has one of two values, apply
9024 our opcode to compute those values. */
9027 {
9032 }
9034 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9035 make can't possibly match and would suppress other optimizations. */
9037 ;
9039 /* If this is a binary operation, see if either side has only one of two
9040 values. If either one does or if both do and they are conditional on
9041 the same value, compute the new true and false values. */
9043 {
9051 {
9052 /* Try to enable a simplification by undoing work done by
9053 if_then_else_cond if it converted a REG into something more
9054 complex. */
9056 {
9059 }
9060 else
9061 {
9064 }
9065 }
9069 {
9070 /* If if_then_else_cond returned zero, then true/false are the
9071 same rtl. We must copy one of them to prevent invalid rtl
9072 sharing. */
9079 {
9084 }
9085 else
9086 {
9089 }
9092 }
9094 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9095 operands is zero when the other is nonzero, and vice-versa,
9096 and STORE_FLAG_VALUE is 1 or -1. */
9102 {
9119 {
9126 const_true_rtx);
9128 }
9129 }
9131 /* Similarly for MULT, AND and UMIN, except that for these the result
9132 is always zero. */
9136 {
9150 {
9153 }
9154 }
9155 }
9158 {
9159 /* If we have IF_THEN_ELSE already, extract the condition and
9160 canonicalize it if it is NE or EQ. */
9166 {
9169 }
9170 else
9172 }
9174 /* If X is a SUBREG, we can narrow both the true and false values
9175 if the inner expression, if there is a condition. */
9179 {
9185 {
9189 }
9190 }
9192 /* If X is a constant, this isn't special and will cause confusions
9193 if we treat it as such. Likewise if it is equivalent to a constant. */
9196 ;
9198 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9199 will be least confusing to the rest of the compiler. */
9201 {
9204 }
9206 /* If X is known to be either 0 or -1, those are the true and
9207 false values when testing X. */
9211 {
9214 }
9216 /* Likewise for 0 or a single bit. */
9219 {
9222 }
9224 /* Otherwise fail; show no condition with true and false values the same. */
9227 }
9228 \f
9229 /* Return the value of expression X given the fact that condition COND
9230 is known to be true when applied to REG as its first operand and VAL
9231 as its second. X is known to not be shared and so can be modified in
9232 place.
9234 We only handle the simplest cases, and specifically those cases that
9235 arise with IF_THEN_ELSE expressions. */
9237 static rtx
9239 {
9247 /* If either operand of the condition is a floating point value,
9248 then we have to avoid collapsing an EQ comparison. */
9258 /* If X is (abs REG) and we know something about REG's relationship
9259 with zero, we may be able to simplify this. */
9263 {
9272 }
9274 /* The only other cases we handle are MIN, MAX, and comparisons if the
9275 operands are the same as REG and VAL. */
9278 {
9280 {
9283 }
9286 {
9288 {
9296 else
9298 }
9301 {
9304 /* Do not reverse the condition when it is NE or EQ.
9305 This is because we cannot conclude anything about
9306 the value of 'SMAX (x, y)' when x is not equal to y,
9307 but we can when x equals y. */
9313 {
9324 }
9325 }
9326 }
9327 }
9329 {
9334 {
9335 /* We must simplify subreg here, before we lose track of the
9336 original inner_mode. */
9341 else
9343 }
9346 }
9347 /* We don't have to handle SIGN_EXTEND here, because even in the
9348 case of replacing something with a modeless CONST_INT, a
9349 CONST_INT is already (supposed to be) a valid sign extension for
9350 its narrower mode, which implies it's already properly
9351 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9352 story is different. */
9354 {
9359 {
9360 /* We must simplify the zero_extend here, before we lose
9361 track of the original inner_mode. */
9366 else
9368 }
9371 }
9375 {
9382 }
9385 }
9386 \f
9387 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9388 assignment as a field assignment. */
9390 static int
9392 {
9394 {
9399 /* For big endian, adjust the memory offset. */
9404 else
9406 }
9414 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9415 Note that all SUBREGs of MEM are paradoxical; otherwise they
9416 would have been rewritten. */
9429 /* We used to see if get_last_value of X and Y were the same but that's
9430 not correct. In one direction, we'll cause the assignment to have
9431 the wrong destination and in the case, we'll import a register into this
9432 insn that might have already have been dead. So fail if none of the
9433 above cases are true. */
9435 }
9436 \f
9437 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9438 Return that assignment if so.
9440 We only handle the most common cases. */
9442 static rtx
9444 {
9447 rtx assign;
9449 HOST_WIDE_INT c1;
9450 HOST_WIDE_INT pos;
9452 rtx other;
9453 machine_mode mode;
9455 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9456 a clear of a one-bit field. We will have changed it to
9457 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9458 for a SUBREG. */
9464 {
9470 }
9480 {
9487 }
9489 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9490 one-bit field. */
9494 {
9500 }
9502 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9503 SRC is an AND with all bits of that field set, then we can discard
9504 the AND. */
9509 {
9516 else
9519 /* Complete overlap. We can remove the source AND. */
9523 /* Partial overlap. We can reduce the source AND. */
9525 {
9530 }
9531 }
9533 /* The other case we handle is assignments into a constant-position
9534 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9535 a mask that has all one bits except for a group of zero bits and
9536 OTHER is known to have zeros where C1 has ones, this is such an
9537 assignment. Compute the position and length from C1. Shift OTHER
9538 to the appropriate position, force it to the required mode, and
9539 make the extraction. Check for the AND in both operands. */
9541 /* One or more SUBREGs might obscure the constant-position field
9542 assignment. The first one we are likely to encounter is an outer
9543 narrowing SUBREG, which we can just strip for the purposes of
9544 identifying the constant-field assignment. */
9558 /* The second SUBREG that might get in the way is a paradoxical
9559 SUBREG around the first operand of the AND. We want to
9560 pretend the operand is as wide as the destination here. We
9561 do this by adjusting the MEM to wider mode for the sole
9562 purpose of the call to rtx_equal_for_field_assignment_p. Also
9563 note this trick only works for MEMs. */
9575 /* The second SUBREG that might get in the way is a paradoxical
9576 SUBREG around the first operand of the AND. We want to
9577 pretend the operand is as wide as the destination here. We
9578 do this by adjusting the MEM to wider mode for the sole
9579 purpose of the call to rtx_equal_for_field_assignment_p. Also
9580 note this trick only works for MEMs. */
9588 else
9601 /* The mode to use for the source is the mode of the assignment, or of
9602 what is inside a possible STRICT_LOW_PART. */
9606 /* Shift OTHER right POS places and make it the source, restricting it
9607 to the proper length and mode. */
9612 dest);
9614 len >= HOST_BITS_PER_WIDE_INT
9615 ? HOST_WIDE_INT_M1U
9619 /* If SRC is masked by an AND that does not make a difference in
9620 the value being stored, strip it. */
9631 }
9632 \f
9633 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9634 if so. */
9636 static rtx
9638 {
9642 rtx tem;
9644 /* Distributivity is not true for floating point as it can change the
9645 value. So we don't do it unless -funsafe-math-optimizations. */
9650 /* The outer operation can only be one of the following: */
9658 /* If either operand is a primitive we can't do anything, so get out
9659 fast. */
9669 /* See if the inner and outer operations distribute. */
9671 {
9676 /* These all distribute except over PLUS. */
9687 /* This is also a multiply, so it distributes over everything. */
9690 /* This used to handle SUBREG, but this turned out to be counter-
9691 productive, since (subreg (op ...)) usually is not handled by
9692 insn patterns, and this "optimization" therefore transformed
9693 recognizable patterns into unrecognizable ones. Therefore the
9694 SUBREG case was removed from here.
9696 It is possible that distributing SUBREG over arithmetic operations
9697 leads to an intermediate result than can then be optimized further,
9698 e.g. by moving the outer SUBREG to the other side of a SET as done
9699 in simplify_set. This seems to have been the original intent of
9700 handling SUBREGs here.
9702 However, with current GCC this does not appear to actually happen,
9703 at least on major platforms. If some case is found where removing
9704 the SUBREG case here prevents follow-on optimizations, distributing
9705 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9709 }
9711 /* Set LHS and RHS to the inner operands (A and B in the example
9712 above) and set OTHER to the common operand (C in the example).
9713 There is only one way to do this unless the inner operation is
9714 commutative. */
9726 else
9729 /* Form the new inner operation, seeing if it simplifies first. */
9732 /* There is one exception to the general way of distributing:
9733 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9735 {
9738 }
9740 /* We may be able to continuing distributing the result, so call
9741 ourselves recursively on the inner operation before forming the
9742 outer operation, which we return. */
9745 }
9747 /* See if X is of the form (* (+ A B) C), and if so convert to
9748 (+ (* A C) (* B C)) and try to simplify.
9750 Most of the time, this results in no change. However, if some of
9751 the operands are the same or inverses of each other, simplifications
9752 will result.
9754 For example, (and (ior A B) (not B)) can occur as the result of
9755 expanding a bit field assignment. When we apply the distributive
9756 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9757 which then simplifies to (and (A (not B))).
9759 Note that no checks happen on the validity of applying the inverse
9760 distributive law. This is pointless since we can do it in the
9761 few places where this routine is called.
9763 N is the index of the term that is decomposed (the arithmetic operation,
9764 i.e. (+ A B) in the first example above). !N is the index of the term that
9765 is distributed, i.e. of C in the first example above. */
9766 static rtx
9768 {
9769 machine_mode mode;
9773 /* Distributivity is not true for floating point as it can change the
9774 value. So we don't do it unless -funsafe-math-optimizations. */
9791 /* Special case (and (xor B C) (not A)), which is equivalent to
9792 (xor (ior A B) (ior A C)) */
9794 {
9797 }
9800 {
9801 /* Distribute the second term. */
9804 }
9805 else
9806 {
9807 /* Distribute the first term. */
9810 }
9820 }
9821 \f
9822 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9823 in MODE. Return an equivalent form, if different from (and VAROP
9824 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9826 static rtx
9829 {
9832 rtx orig_varop;
9840 /* Simplify VAROP knowing that we will be only looking at some of the
9841 bits in it.
9843 Note by passing in CONSTOP, we guarantee that the bits not set in
9844 CONSTOP are not significant and will never be examined. We must
9845 ensure that is the case by explicitly masking out those bits
9846 before returning. */
9849 /* If VAROP is a CLOBBER, we will fail so return it. */
9853 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9854 to VAROP and return the new constant. */
9858 /* See what bits may be nonzero in VAROP. Unlike the general case of
9859 a call to nonzero_bits, here we don't care about bits outside
9860 MODE. */
9864 /* Turn off all bits in the constant that are known to already be zero.
9865 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9866 which is tested below. */
9870 /* If we don't have any bits left, return zero. */
9874 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9875 a power of two, we can replace this with an ASHIFT. */
9880 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9881 or XOR, then try to apply the distributive law. This may eliminate
9882 operations if either branch can be simplified because of the AND.
9883 It may also make some cases more complex, but those cases probably
9884 won't match a pattern either with or without this. */
9887 return
9888 gen_lowpart
9890 apply_distributive_law
9895 constop),
9899 constop))));
9901 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9902 the AND and see if one of the operands simplifies to zero. If so, we
9903 may eliminate it. */
9907 {
9916 }
9918 /* Make a SUBREG if necessary. If we can't make it, fail. */
9923 /* If we are only masking insignificant bits, return VAROP. */
9930 /* Otherwise, return an AND. */
9932 }
9935 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9936 in MODE.
9938 Return an equivalent form, if different from X. Otherwise, return X. If
9939 X is zero, we are to always construct the equivalent form. */
9941 static rtx
9944 {
9955 }
9956 \f
9957 /* Given a REG, X, compute which bits in X can be nonzero.
9958 We don't care about bits outside of those defined in MODE.
9960 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9961 a shift, AND, or zero_extract, we can do better. */
9963 static rtx
9965 const_rtx known_x ATTRIBUTE_UNUSED,
9966 machine_mode known_mode ATTRIBUTE_UNUSED,
9969 {
9970 rtx tem;
9973 /* If X is a register whose nonzero bits value is current, use it.
9974 Otherwise, if X is a register whose value we can find, use that
9975 value. Otherwise, use the previously-computed global nonzero bits
9976 for this register. */
9990 && !REGNO_REG_SET_P
9993 {
9994 /* Note that, even if the precision of last_set_mode is lower than that
9995 of mode, record_value_for_reg invoked nonzero_bits on the register
9996 with nonzero_bits_mode (because last_set_mode is necessarily integral
9997 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
9998 are all valid, hence in mode too since nonzero_bits_mode is defined
9999 to the largest HWI_COMPUTABLE_MODE_P mode. */
10002 }
10006 {
10012 }
10015 {
10019 /* We don't know anything about the upper bits. */
10023 }
10026 }
10028 /* Return the number of bits at the high-order end of X that are known to
10029 be equal to the sign bit. X will be used in mode MODE; if MODE is
10030 VOIDmode, X will be used in its own mode. The returned value will always
10031 be between 1 and the number of bits in MODE. */
10033 static rtx
10035 const_rtx known_x ATTRIBUTE_UNUSED,
10036 machine_mode known_mode
10037 ATTRIBUTE_UNUSED,
10040 {
10041 rtx tem;
10054 && !REGNO_REG_SET_P
10057 {
10060 }
10071 }
10072 \f
10073 /* Return the number of "extended" bits there are in X, when interpreted
10074 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10075 unsigned quantities, this is the number of high-order zero bits.
10076 For signed quantities, this is the number of copies of the sign bit
10077 minus 1. In both case, this function returns the number of "spare"
10078 bits. For example, if two quantities for which this function returns
10079 at least 1 are added, the addition is known not to overflow.
10081 This function will always return 0 unless called during combine, which
10082 implies that it must be called from a define_split. */
10084 unsigned int
10086 {
10096 }
10098 /* This function is called from `simplify_shift_const' to merge two
10099 outer operations. Specifically, we have already found that we need
10100 to perform operation *POP0 with constant *PCONST0 at the outermost
10101 position. We would now like to also perform OP1 with constant CONST1
10102 (with *POP0 being done last).
10104 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10105 the resulting operation. *PCOMP_P is set to 1 if we would need to
10106 complement the innermost operand, otherwise it is unchanged.
10108 MODE is the mode in which the operation will be done. No bits outside
10109 the width of this mode matter. It is assumed that the width of this mode
10110 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10112 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10113 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10114 result is simply *PCONST0.
10116 If the resulting operation cannot be expressed as one operation, we
10117 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10119 static int
10120 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10121 {
10128 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10132 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10133 if OP0 is SET. */
10142 {
10144 {
10162 }
10163 }
10165 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10169 /* If the two constants aren't the same, we can't do anything. The
10170 remaining six cases can all be done. */
10174 else
10176 {
10179 /* (a & b) | b == b */
10182 /* (a ^ b) | b == a | b */
10183 {;}
10188 /* (a & b) ^ b == (~a) & b */
10191 /* (a | b) ^ b == a & ~b */
10197 /* (a | b) & b == b */
10200 /* (a ^ b) & b) == (~a) & b */
10205 }
10207 /* Check for NO-OP cases. */
10220 /* ??? Slightly redundant with the above mask, but not entirely.
10221 Moving this above means we'd have to sign-extend the mode mask
10222 for the final test. */
10227 }
10228 \f
10229 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10230 the shift in. The original shift operation CODE is performed on OP in
10231 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10232 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10233 result of the shift is subject to operation OUTER_CODE with operand
10234 OUTER_CONST. */
10236 static machine_mode
10240 {
10245 /* In general we can't perform in wider mode for right shift and rotate. */
10247 {
10249 /* We can still widen if the bits brought in from the left are identical
10250 to the sign bit of ORIG_MODE. */
10258 /* Similarly here but with zero bits. */
10263 /* We can also widen if the bits brought in will be masked off. This
10264 operation is performed in ORIG_MODE. */
10266 {
10272 }
10273 /* fall through */
10283 }
10284 }
10286 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10287 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10288 if we cannot simplify it. Otherwise, return a simplified value.
10290 The shift is normally computed in the widest mode we find in VAROP, as
10291 long as it isn't a different number of words than RESULT_MODE. Exceptions
10292 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10294 static rtx
10297 {
10303 unsigned int mode_words
10305 /* We form (outer_op (code varop count) (outer_const)). */
10311 /* Make sure and truncate the "natural" shift on the way in. We don't
10312 want to do this inside the loop as it makes it more difficult to
10313 combine shifts. */
10317 /* If we were given an invalid count, don't do anything except exactly
10318 what was requested. */
10325 /* Unless one of the branches of the `if' in this loop does a `continue',
10326 we will `break' the loop after the `if'. */
10329 {
10330 /* If we have an operand of (clobber (const_int 0)), fail. */
10334 /* Convert ROTATERT to ROTATE. */
10336 {
10340 }
10346 /* Handle cases where the count is greater than the size of the mode
10347 minus 1. For ASHIFT, use the size minus one as the count (this can
10348 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10349 take the count modulo the size. For other shifts, the result is
10350 zero.
10352 Since these shifts are being produced by the compiler by combining
10353 multiple operations, each of which are defined, we know what the
10354 result is supposed to be. */
10357 {
10362 else
10363 {
10364 /* We can't simply return zero because there may be an
10365 outer op. */
10369 }
10370 }
10372 /* If we discovered we had to complement VAROP, leave. Making a NOT
10373 here would cause an infinite loop. */
10378 {
10379 /* An arithmetic right shift of a quantity known to be -1 or 0
10380 is a no-op. */
10384 {
10387 }
10389 /* If we are doing an arithmetic right shift and discarding all but
10390 the sign bit copies, this is equivalent to doing a shift by the
10391 bitsize minus one. Convert it into that shift because it will
10392 often allow other simplifications. */
10399 /* We simplify the tests below and elsewhere by converting
10400 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10401 `make_compound_operation' will convert it to an ASHIFTRT for
10402 those machines (such as VAX) that don't have an LSHIFTRT. */
10407 shift_unit_mode)))
10419 }
10422 {
10429 {
10432 }
10436 /* The following rules apply only to scalars. */
10440 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10441 minus the width of a smaller mode, we can do this with a
10442 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10449 {
10458 }
10462 /* The following rules apply only to scalars. */
10466 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10467 the same number of words as what we've seen so far. Then store
10468 the widest mode in MODE. */
10474 == mode_words
10477 {
10482 }
10486 /* Some machines use MULT instead of ASHIFT because MULT
10487 is cheaper. But it is still better on those machines to
10488 merge two shifts into one. */
10491 {
10492 varop
10498 }
10502 /* Similar, for when divides are cheaper. */
10505 {
10506 varop
10512 }
10516 /* If we are extracting just the sign bit of an arithmetic
10517 right shift, that shift is not needed. However, the sign
10518 bit of a wider mode may be different from what would be
10519 interpreted as the sign bit in a narrower mode, so, if
10520 the result is narrower, don't discard the shift. */
10525 {
10528 }
10530 /* fall through */
10535 /* The following rules apply only to scalars. */
10539 /* Here we have two nested shifts. The result is usually the
10540 AND of a new shift with a mask. We compute the result below. */
10546 {
10550 rtx mask_rtx;
10552 /* We have one common special case. We can't do any merging if
10553 the inner code is an ASHIFTRT of a smaller mode. However, if
10554 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10555 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10556 we can convert it to
10557 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10558 This simplifies certain SIGN_EXTEND operations. */
10562 {
10563 /* C3 has the low-order C1 bits zero. */
10575 }
10577 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10578 than C1 high-order bits equal to the sign bit, we can convert
10579 this to either an ASHIFT or an ASHIFTRT depending on the
10580 two counts.
10582 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10588 {
10592 {
10595 }
10598 }
10600 /* There are some cases we can't do. If CODE is ASHIFTRT,
10601 we can only do this if FIRST_CODE is also ASHIFTRT.
10603 We can't do the case when CODE is ROTATE and FIRST_CODE is
10604 ASHIFTRT.
10606 If the mode of this shift is not the mode of the outer shift,
10607 we can't do this if either shift is a right shift or ROTATE.
10609 Finally, we can't do any of these if the mode is too wide
10610 unless the codes are the same.
10612 Handle the case where the shift codes are the same
10613 first. */
10616 {
10625 }
10636 /* To compute the mask to apply after the shift, shift the
10637 nonzero bits of the inner shift the same way the
10638 outer shift will. */
10641 result_mode);
10643 mask_rtx
10647 /* Give up if we can't compute an outer operation to use. */
10655 /* If the shifts are in the same direction, we add the
10656 counts. Otherwise, we subtract them. */
10660 else
10663 /* If COUNT is positive, the new shift is usually CODE,
10664 except for the two exceptions below, in which case it is
10665 FIRST_CODE. If the count is negative, FIRST_CODE should
10666 always be used */
10676 }
10678 /* If we have (A << B << C) for any shift, we can convert this to
10679 (A << C << B). This wins if A is a constant. Only try this if
10680 B is not a constant. */
10685 {
10686 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10687 sure the result will be masked. See PR70222. */
10695 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10696 up outer sign extension (often left and right shift) is
10697 hardly more efficient than the original. See PR70429. */
10707 }
10711 /* The following rules apply only to scalars. */
10715 /* Make this fit the case below. */
10722 /* The following rules apply only to scalars. */
10726 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10727 with C the size of VAROP - 1 and the shift is logical if
10728 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10729 we have an (le X 0) operation. If we have an arithmetic shift
10730 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10731 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10739 {
10742 const0_rtx);
10748 }
10750 /* If we have (shift (logical)), move the logical to the outside
10751 to allow it to possibly combine with another logical and the
10752 shift to combine with another shift. This also canonicalizes to
10753 what a ZERO_EXTRACT looks like. Also, some machines have
10754 (and (shift)) insns. */
10757 /* We can't do this if we have (ashiftrt (xor)) and the
10758 constant has its sign bit set in shift_mode with shift_mode
10759 wider than result_mode. */
10763 shift_mode))
10771 {
10774 }
10776 /* If we can't do that, try to simplify the shift in each arm of the
10777 logical expression, make a new logical expression, and apply
10778 the inverse distributive law. This also can't be done for
10779 (ashiftrt (xor)) where we've widened the shift and the constant
10780 changes the sign bit. */
10785 shift_mode)))
10786 {
10798 }
10802 /* The following rules apply only to scalars. */
10806 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10807 says that the sign bit can be tested, FOO has mode MODE, C is
10808 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10809 that may be nonzero. */
10819 {
10823 }
10827 /* The following rules apply only to scalars. */
10831 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10832 than the number of bits in the mode is equivalent to A. */
10836 {
10840 }
10842 /* NEG commutes with ASHIFT since it is multiplication. Move the
10843 NEG outside to allow shifts to combine. */
10847 {
10850 }
10854 /* The following rules apply only to scalars. */
10858 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10859 is one less than the number of bits in the mode is
10860 equivalent to (xor A 1). */
10867 {
10871 }
10873 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10874 that might be nonzero in BAR are those being shifted out and those
10875 bits are known zero in FOO, we can replace the PLUS with FOO.
10876 Similarly in the other operand order. This code occurs when
10877 we are computing the size of a variable-size array. */
10884 {
10887 }
10895 result_mode)))
10896 {
10899 }
10901 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10911 {
10914 }
10916 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10917 signbit', and attempt to change the PLUS to an XOR and move it to
10918 the outer operation as is done above in the AND/IOR/XOR case
10919 leg for shift(logical). See details in logical handling above
10920 for reasoning in doing so. */
10931 {
10934 }
10939 /* The following rules apply only to scalars. */
10943 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10944 with C the size of VAROP - 1 and the shift is logical if
10945 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10946 we have a (gt X 0) operation. If the shift is arithmetic with
10947 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10948 we have a (neg (gt X 0)) operation. */
10957 {
10960 const0_rtx);
10966 }
10970 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10971 if the truncate does not affect the value. */
10978 {
10981 varop_inner
10984 GEN_INT
10989 }
10994 }
10997 }
11002 /* We have now finished analyzing the shift. The result should be
11003 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11004 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11005 to the result of the shift. OUTER_CONST is the relevant constant,
11006 but we must turn off all bits turned off in the shift. */
11014 /* Make a SUBREG if necessary. If we can't make it, fail. */
11019 /* If we have an outer operation and we just made a shift, it is
11020 possible that we could have simplified the shift were it not
11021 for the outer operation. So try to do the simplification
11022 recursively. */
11026 else
11032 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11033 turn off all the bits that the shift would have turned off. */
11038 /* Do the remainder of the processing in RESULT_MODE. */
11041 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11042 operation. */
11047 {
11055 {
11056 /* This means that we have determined that the result is
11057 equivalent to a constant. This should be rare. */
11060 }
11063 else
11066 }
11069 }
11071 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11072 The result of the shift is RESULT_MODE. If we cannot simplify it,
11073 return X or, if it is NULL, synthesize the expression with
11074 simplify_gen_binary. Otherwise, return a simplified value.
11076 The shift is normally computed in the widest mode we find in VAROP, as
11077 long as it isn't a different number of words than RESULT_MODE. Exceptions
11078 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11080 static rtx
11083 {
11093 }
11095 \f
11096 /* A subroutine of recog_for_combine. See there for arguments and
11097 return value. */
11099 static int
11101 {
11103 rtx pat_without_clobbers;
11111 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11112 we use to indicate that something didn't match. If we find such a
11113 thing, force rejection. */
11127 {
11130 else
11133 }
11135 /* If it isn't, there is the possibility that we previously had an insn
11136 that clobbered some register as a side effect, but the combined
11137 insn doesn't need to do that. So try once more without the clobbers
11138 unless this represents an ASM insn. */
11142 {
11147 {
11150 pos++;
11151 }
11161 {
11164 else
11167 }
11168 }
11175 /* Recognize all noop sets, these will be killed by followup pass. */
11179 /* If we had any clobbers to add, make a new pattern than contains
11180 them. Then check to make sure that all of them are dead. */
11182 {
11192 else
11199 {
11204 {
11208 }
11209 }
11211 }
11215 {
11223 /* Allow targets to reject combined insn. */
11225 {
11228 dump_file);
11230 /* Callers expect recog_for_combine to strip
11231 clobbers from the pattern on failure. */
11236 }
11241 }
11247 }
11249 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11250 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11251 Return whether anything was so changed. */
11253 static bool
11255 {
11261 {
11272 {
11283 else
11287 }
11294 {
11299 }
11305 {
11308 }
11309 else
11315 {
11318 }
11322 }
11333 {
11348 else
11356 }
11359 }
11361 /* Like recog, but we receive the address of a pointer to a new pattern.
11362 We try to match the rtx that the pointer points to.
11363 If that fails, we may try to modify or replace the pattern,
11364 storing the replacement into the same pointer object.
11366 Modifications include deletion or addition of CLOBBERs. If the
11367 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11368 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11369 (and undo if that fails).
11371 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11372 the CLOBBERs are placed.
11374 The value is the final insn code from the pattern ultimately matched,
11375 or -1. */
11377 static int
11379 {
11391 {
11394 {
11398 }
11399 }
11402 {
11407 }
11410 }
11411 \f
11412 /* Like gen_lowpart_general but for use by combine. In combine it
11413 is not possible to create any new pseudoregs. However, it is
11414 safe to create invalid memory addresses, because combine will
11415 try to recognize them and all they will do is make the combine
11416 attempt fail.
11418 If for some reason this cannot do its job, an rtx
11419 (clobber (const_int 0)) is returned.
11420 An insn containing that will not be recognized. */
11422 static rtx
11424 {
11428 rtx result;
11433 /* We can only support MODE being wider than a word if X is a
11434 constant integer or has a mode the same size. */
11439 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11440 won't know what to do. So we will strip off the SUBREG here and
11441 process normally. */
11443 {
11446 /* For use in case we fall down into the address adjustments
11447 further below, we need to adjust the known mode and size of
11448 x; imode and isize, since we just adjusted x. */
11455 }
11463 {
11466 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11467 address. */
11472 /* If we want to refer to something bigger than the original memref,
11473 generate a paradoxical subreg instead. That will force a reload
11474 of the original memref X. */
11481 /* Adjust the address so that the address-after-the-data is
11482 unchanged. */
11487 }
11489 /* If X is a comparison operator, rewrite it in a new mode. This
11490 probably won't match, but may allow further simplifications. */
11494 /* If we couldn't simplify X any other way, just enclose it in a
11495 SUBREG. Normally, this SUBREG won't match, but some patterns may
11496 include an explicit SUBREG or we may simplify it further in combine. */
11497 else
11498 {
11499 rtx res;
11502 {
11507 }
11511 }
11513 fail:
11515 }
11516 \f
11517 /* Try to simplify a comparison between OP0 and a constant OP1,
11518 where CODE is the comparison code that will be tested, into a
11519 (CODE OP0 const0_rtx) form.
11521 The result is a possibly different comparison code to use.
11522 *POP1 may be updated. */
11524 static enum rtx_code
11527 {
11531 /* Get the constant we are comparing against and turn off all bits
11532 not on in our mode. */
11536 /* If we are comparing against a constant power of two and the value
11537 being compared can only have that single bit nonzero (e.g., it was
11538 `and'ed with that bit), we can replace this with a comparison
11539 with zero. */
11547 {
11550 }
11552 /* Similarly, if we are comparing a value known to be either -1 or
11553 0 with -1, change it to the opposite comparison against zero. */
11558 {
11561 }
11563 /* Do some canonicalizations based on the comparison code. We prefer
11564 comparisons against zero and then prefer equality comparisons.
11565 If we can reduce the size of a constant, we will do that too. */
11567 {
11569 /* < C is equivalent to <= (C - 1) */
11571 {
11574 /* ... fall through to LE case below. */
11576 }
11577 else
11581 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11583 {
11586 }
11588 /* If we are doing a <= 0 comparison on a value known to have
11589 a zero sign bit, we can replace this with == 0. */
11599 /* >= C is equivalent to > (C - 1). */
11601 {
11604 /* ... fall through to GT below. */
11606 }
11607 else
11611 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11613 {
11616 }
11618 /* If we are doing a > 0 comparison on a value known to have
11619 a zero sign bit, we can replace this with != 0. */
11629 /* < C is equivalent to <= (C - 1). */
11631 {
11634 /* ... fall through ... */
11635 }
11636 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11640 {
11644 }
11645 else
11649 /* unsigned <= 0 is equivalent to == 0 */
11652 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11656 {
11659 }
11663 /* >= C is equivalent to > (C - 1). */
11665 {
11668 /* ... fall through ... */
11669 }
11671 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11675 {
11679 }
11680 else
11684 /* unsigned > 0 is equivalent to != 0 */
11687 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11691 {
11694 }
11699 }
11703 }
11704 \f
11705 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11706 comparison code that will be tested.
11708 The result is a possibly different comparison code to use. *POP0 and
11709 *POP1 may be updated.
11711 It is possible that we might detect that a comparison is either always
11712 true or always false. However, we do not perform general constant
11713 folding in combine, so this knowledge isn't useful. Such tautologies
11714 should have been detected earlier. Hence we ignore all such cases. */
11716 static enum rtx_code
11718 {
11725 /* Try a few ways of applying the same transformation to both operands. */
11727 {
11728 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11729 so check specially. */
11745 - (GET_MODE_PRECISION
11747 {
11750 }
11752 /* If both operands are the same constant shift, see if we can ignore the
11753 shift. We can if the shift is a rotate or if the bits shifted out of
11754 this shift are known to be zero for both inputs and if the type of
11755 comparison is compatible with the shift. */
11768 {
11781 else
11783 }
11785 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11786 SUBREGs are of the same mode, and, in both cases, the AND would
11787 be redundant if the comparison was done in the narrower mode,
11788 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11789 and the operand's possibly nonzero bits are 0xffffff01; in that case
11790 if we only care about QImode, we don't need the AND). This case
11791 occurs if the output mode of an scc insn is not SImode and
11792 STORE_FLAG_VALUE == 1 (e.g., the 386).
11794 Similarly, check for a case where the AND's are ZERO_EXTEND
11795 operations from some narrower mode even though a SUBREG is not
11796 present. */
11801 {
11818 {
11822 /* The resulting comparison is always unsigned since we masked
11823 off the original sign bit. */
11827 }
11832 {
11838 }
11842 }
11844 /* If both operands are NOT, we can strip off the outer operation
11845 and adjust the comparison code for swapped operands; similarly for
11846 NEG, except that this must be an equality comparison. */
11852 else
11854 }
11856 /* If the first operand is a constant, swap the operands and adjust the
11857 comparison code appropriately, but don't do this if the second operand
11858 is already a constant integer. */
11860 {
11863 }
11865 /* We now enter a loop during which we will try to simplify the comparison.
11866 For the most part, we only are concerned with comparisons with zero,
11867 but some things may really be comparisons with zero but not start
11868 out looking that way. */
11871 {
11878 HOST_WIDE_INT const_op;
11880 /* We only want to handle integral modes. This catches VOIDmode,
11881 CCmode, and the floating-point modes. An exception is that we
11882 can handle VOIDmode if OP0 is a COMPARE or a comparison
11883 operation. */
11890 /* Try to simplify the compare to constant, possibly changing the
11891 comparison op, and/or changing op1 to zero. */
11895 /* Compute some predicates to simplify code below. */
11902 /* If this is a sign bit comparison and we can do arithmetic in
11903 MODE, say that we will only be needing the sign bit of OP0. */
11906 HOST_WIDE_INT_1U
11910 /* Now try cases based on the opcode of OP0. If none of the cases
11911 does a "continue", we exit this loop immediately after the
11912 switch. */
11915 {
11917 /* If we are extracting a single bit from a variable position in
11918 a constant that has only a single bit set and are comparing it
11919 with zero, we can convert this into an equality comparison
11920 between the position and the location of the single bit. */
11921 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11922 have already reduced the shift count modulo the word size. */
11928 {
11936 /* Result is nonzero iff shift count is equal to I. */
11939 }
11941 /* fall through */
11946 {
11949 }
11953 /* If testing for equality, we can take the NOT of the constant. */
11956 {
11960 }
11962 /* If just looking at the sign bit, reverse the sense of the
11963 comparison. */
11965 {
11969 }
11973 /* If testing for equality, we can take the NEG of the constant. */
11976 {
11980 }
11982 /* The remaining cases only apply to comparisons with zero. */
11986 /* When X is ABS or is known positive,
11987 (neg X) is < 0 if and only if X != 0. */
11995 {
11999 }
12001 /* If we have NEG of something whose two high-order bits are the
12002 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12004 {
12008 }
12012 /* If we are testing equality and our count is a constant, we
12013 can perform the inverse operation on our RHS. */
12017 {
12021 }
12023 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12024 a particular bit. Convert it to an AND of a constant of that
12025 bit. This will be converted into a ZERO_EXTRACT. */
12029 {
12031 (HOST_WIDE_INT_1U
12036 }
12038 /* Fall through. */
12041 /* ABS is ignorable inside an equality comparison with zero. */
12043 {
12046 }
12050 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12051 (compare FOO CONST) if CONST fits in FOO's mode and we
12052 are either testing inequality or have an unsigned
12053 comparison with ZERO_EXTEND or a signed comparison with
12054 SIGN_EXTEND. But don't do it if we don't have a compare
12055 insn of the given mode, since we'd have to revert it
12056 later on, and then we wouldn't know whether to sign- or
12057 zero-extend. */
12060 && ! unsigned_comparison_p
12064 {
12067 }
12071 /* Check for the case where we are comparing A - C1 with C2, that is
12073 (subreg:MODE (plus (A) (-C1))) op (C2)
12075 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12076 comparison in the wider mode. One of the following two conditions
12077 must be true in order for this to be valid:
12079 1. The mode extension results in the same bit pattern being added
12080 on both sides and the comparison is equality or unsigned. As
12081 C2 has been truncated to fit in MODE, the pattern can only be
12082 all 0s or all 1s.
12084 2. The mode extension results in the sign bit being copied on
12085 each side.
12087 The difficulty here is that we have predicates for A but not for
12088 (A - C1) so we need to check that C1 is within proper bounds so
12089 as to perturbate A as little as possible. */
12096 {
12105 /* (A - C1) zero-extends if it is positive and sign-extends
12106 if it is negative, C2 both zero- and sign-extends. */
12110 /* (A - C1) sign-extends if it is positive and 1-extends
12111 if it is negative, C2 both sign- and 1-extends. */
12118 /* (A - C1) always sign-extends, like C2. */
12122 {
12125 }
12126 }
12128 /* If the inner mode is narrower and we are extracting the low part,
12129 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12131 ;
12142 {
12143 /* Remove outer subregs that don't do anything. */
12148 {
12152 }
12154 }
12155 else
12158 /* FALLTHROUGH */
12168 {
12171 }
12175 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12176 this for equality comparisons due to pathological cases involving
12177 overflows. */
12181 {
12185 }
12187 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12190 {
12194 }
12198 /* We used to optimize signed comparisons against zero, but that
12199 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12200 arrive here as equality comparisons, or (GEU, LTU) are
12201 optimized away. No need to special-case them. */
12203 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12204 (eq B (minus A C)), whichever simplifies. We can only do
12205 this for equality comparisons due to pathological cases involving
12206 overflows. */
12210 {
12214 }
12219 {
12223 }
12225 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12226 of bits in X minus 1, is one iff X > 0. */
12231 {
12235 }
12239 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12240 if C is zero or B is a constant. */
12244 {
12248 }
12256 /* We can't do anything if OP0 is a condition code value, rather
12257 than an actual data value. */
12263 /* Get the two operands being compared. */
12266 else
12269 /* Check for the cases where we simply want the result of the
12270 earlier test or the opposite of that result. */
12274 {
12278 else
12282 {
12287 }
12288 }
12292 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12293 iff X <= 0. */
12297 {
12301 }
12305 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12306 will be converted to a ZERO_EXTRACT later. */
12310 {
12315 }
12317 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12318 zero and X is a comparison and C1 and C2 describe only bits set
12319 in STORE_FLAG_VALUE, we can compare with X. */
12327 {
12334 {
12337 }
12338 }
12340 /* If we are doing an equality comparison of an AND of a bit equal
12341 to the sign bit, replace this with a LT or GE comparison of
12342 the underlying value. */
12349 {
12353 }
12355 /* If this AND operation is really a ZERO_EXTEND from a narrower
12356 mode, the constant fits within that mode, and this is either an
12357 equality or unsigned comparison, try to do this comparison in
12358 the narrower mode.
12360 Note that in:
12362 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12363 -> (ne:DI (reg:SI 4) (const_int 0))
12365 unless TRULY_NOOP_TRUNCATION allows it or the register is
12366 known to hold a value of the required mode the
12367 transformation is invalid. */
12375 {
12378 }
12380 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12381 fits in both M1 and M2 and the SUBREG is either paradoxical
12382 or represents the low part, permute the SUBREG and the AND
12383 and try again. */
12386 {
12389 /* Require an integral mode, to avoid creating something like
12390 (AND:SF ...). */
12392 /* It is unsafe to commute the AND into the SUBREG if the
12393 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12394 not defined. As originally written the upper bits
12395 have a defined value due to the AND operation.
12396 However, if we commute the AND inside the SUBREG then
12397 they no longer have defined values and the meaning of
12398 the code has been changed.
12399 Also C1 should not change value in the smaller mode,
12400 see PR67028 (a positive C1 can become negative in the
12401 smaller mode, so that the AND does no longer mask the
12402 upper bits). */
12403 && ((WORD_REGISTER_OPERATIONS
12415 {
12421 }
12422 }
12424 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12428 {
12433 }
12435 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12436 (eq (and (lshiftrt X) 1) 0).
12437 Also handle the case where (not X) is expressed using xor. */
12441 {
12451 == HOST_WIDE_INT_1U
12453 {
12454 op0
12459 }
12460 }
12464 /* If we have (compare (ashift FOO N) (const_int C)) and
12465 the high order N bits of FOO (N+1 if an inequality comparison)
12466 are known to be zero, we can do this by comparing FOO with C
12467 shifted right N bits so long as the low-order N bits of C are
12468 zero. */
12480 {
12481 /* We must perform a logical shift, not an arithmetic one,
12482 as we want the top N bits of C to be zero. */
12489 }
12491 /* If we are doing a sign bit comparison, it means we are testing
12492 a particular bit. Convert it to the appropriate AND. */
12495 {
12497 (HOST_WIDE_INT_1U
12502 }
12504 /* If this an equality comparison with zero and we are shifting
12505 the low bit to the sign bit, we can convert this to an AND of the
12506 low-order bit. */
12510 {
12513 }
12517 /* If this is an equality comparison with zero, we can do this
12518 as a logical shift, which might be much simpler. */
12521 {
12526 }
12528 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12529 do the comparison in a narrower mode. */
12539 {
12542 }
12544 /* Likewise if OP0 is a PLUS of a sign extension with a
12545 constant, which is usually represented with the PLUS
12546 between the shifts. */
12558 {
12566 new_const);
12568 }
12570 /* FALLTHROUGH */
12572 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12573 the low order N bits of FOO are known to be zero, we can do this
12574 by comparing FOO with C shifted left N bits so long as no
12575 overflow occurs. Even if the low order N bits of FOO aren't known
12576 to be zero, if the comparison is >= or < we can use the same
12577 optimization and for > or <= by setting all the low
12578 order N bits in the comparison constant. */
12589 {
12590 unsigned HOST_WIDE_INT low_bits
12592 & ((HOST_WIDE_INT_1U
12595 {
12596 /* If the shift was logical, then we must make the condition
12597 unsigned. */
12606 const_op
12611 }
12612 }
12614 /* If we are using this shift to extract just the sign bit, we
12615 can replace this with an LT or GE comparison. */
12620 {
12624 }
12629 }
12632 }
12634 /* Now make any compound operations involved in this comparison. Then,
12635 check for an outmost SUBREG on OP0 that is not doing anything or is
12636 paradoxical. The latter transformation must only be performed when
12637 it is known that the "extra" bits will be the same in op0 and op1 or
12638 that they don't matter. There are three cases to consider:
12640 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12641 care bits and we can assume they have any convenient value. So
12642 making the transformation is safe.
12644 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12645 In this case the upper bits of op0 are undefined. We should not make
12646 the simplification in that case as we do not know the contents of
12647 those bits.
12649 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12650 In that case we know those bits are zeros or ones. We must also be
12651 sure that they are the same as the upper bits of op1.
12653 We can never remove a SUBREG for a non-equality comparison because
12654 the sign bit is in a different place in the underlying object. */
12667 {
12669 {
12670 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12671 implemented. */
12673 {
12676 }
12677 }
12683 {
12689 }
12690 }
12692 /* We now do the opposite procedure: Some machines don't have compare
12693 insns in all modes. If OP0's mode is an integer mode smaller than a
12694 word and we can't do a compare in that mode, see if there is a larger
12695 mode for which we can do the compare. There are a number of cases in
12696 which we can use the wider mode. */
12703 {
12707 {
12710 /* If this is a test for negative, we can make an explicit
12711 test of the sign bit. Test this first so we can use
12712 a paradoxical subreg to extend OP0. */
12716 {
12717 unsigned HOST_WIDE_INT sign
12724 }
12726 /* If the only nonzero bits in OP0 and OP1 are those in the
12727 narrower mode and this is an equality or unsigned comparison,
12728 we can use the wider mode. Similarly for sign-extended
12729 values, in which case it is true for all comparisons. */
12746 {
12747 /* If OP0 is an AND and we don't have an AND in MODE either,
12748 make a new AND in the proper mode. */
12756 else
12757 {
12759 {
12764 }
12765 else
12766 {
12771 }
12773 }
12774 }
12775 }
12776 }
12778 /* We may have changed the comparison operands. Re-canonicalize. */
12780 {
12783 }
12785 /* If this machine only supports a subset of valid comparisons, see if we
12786 can convert an unsupported one into a supported one. */
12793 }
12794 \f
12795 /* Utility function for record_value_for_reg. Count number of
12796 rtxs in X. */
12797 static int
12799 {
12806 {
12826 }
12837 }
12838 \f
12839 /* Utility function for following routine. Called when X is part of a value
12840 being stored into last_set_value. Sets last_set_table_tick
12841 for each register mentioned. Similar to mention_regs in cse.c */
12843 static void
12845 {
12851 {
12857 {
12860 }
12863 }
12867 {
12868 /* Check for identical subexpressions. If x contains
12869 identical subexpression we only have to traverse one of
12870 them. */
12872 {
12873 /* Note that at this point x1 has already been
12874 processed. */
12878 /* If x0 and x1 are identical then there is no need to
12879 process x0. */
12883 /* If x0 is identical to a subexpression of x1 then while
12884 processing x1, x0 has already been processed. Thus we
12885 are done with x. */
12890 /* If x1 is identical to a subexpression of x0 then we
12891 still have to process the rest of x0. */
12894 {
12897 }
12898 }
12901 }
12905 }
12907 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12908 are saying that the register is clobbered and we no longer know its
12909 value. If INSN is zero, don't update reg_stat[].last_set; this is
12910 only permitted with VALUE also zero and is used to invalidate the
12911 register. */
12913 static void
12915 {
12921 /* If VALUE contains REG and we have a previous value for REG, substitute
12922 the previous value. */
12924 {
12925 rtx tem;
12927 /* Set things up so get_last_value is allowed to see anything set up to
12928 our insn. */
12932 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12933 it isn't going to be useful and will take a lot of time to process,
12934 so just use the CLOBBER. */
12937 {
12943 {
12944 /* If there are two or more occurrences of REG in VALUE,
12945 prevent the value from growing too much. */
12948 }
12951 }
12952 }
12954 /* For each register modified, show we don't know its value, that
12955 we don't know about its bitwise content, that its value has been
12956 updated, and that we don't know the location of the death of the
12957 register. */
12959 {
12971 }
12973 /* Mark registers that are being referenced in this value. */
12977 /* Now update the status of each register being set.
12978 If someone is using this register in this block, set this register
12979 to invalid since we will get confused between the two lives in this
12980 basic block. This makes using this register always invalid. In cse, we
12981 scan the table to invalidate all entries using this register, but this
12982 is too much work for us. */
12985 {
12991 else
12993 }
12995 /* The value being assigned might refer to X (like in "x++;"). In that
12996 case, we must replace it with (clobber (const_int 0)) to prevent
12997 infinite loops. */
13000 {
13004 }
13006 /* For the main register being modified, update the value, the mode, the
13007 nonzero bits, and the number of sign bit copies. */
13012 {
13020 rsp->last_set_sign_bit_copies
13022 }
13023 }
13025 /* Called via note_stores from record_dead_and_set_regs to handle one
13026 SET or CLOBBER in an insn. DATA is the instruction in which the
13027 set is occurring. */
13029 static void
13031 {
13038 {
13042 }
13045 {
13046 /* If we are setting the whole register, we know its value. Otherwise
13047 show that we don't know the value. We can handle SUBREG in
13048 some cases. */
13059 else
13061 }
13063 /* Ignore pushes, they clobber nothing. */
13066 }
13068 /* Update the records of when each REG was most recently set or killed
13069 for the things done by INSN. This is the last thing done in processing
13070 INSN in the combiner loop.
13072 We update reg_stat[], in particular fields last_set, last_set_value,
13073 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13074 last_death, and also the similar information mem_last_set (which insn
13075 most recently modified memory) and last_call_luid (which insn was the
13076 most recent subroutine call). */
13078 static void
13080 {
13081 rtx link;
13085 {
13088 {
13093 {
13098 }
13099 }
13102 }
13105 {
13106 hard_reg_set_iterator hrsi;
13108 {
13120 }
13124 /* We can't combine into a call pattern. Remember, though, that
13125 the return value register is set at this LUID. We could
13126 still replace a register with the return value from the
13127 wrong subroutine call! */
13129 }
13130 else
13132 }
13134 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13135 register present in the SUBREG, so for each such SUBREG go back and
13136 adjust nonzero and sign bit information of the registers that are
13137 known to have some zero/sign bits set.
13139 This is needed because when combine blows the SUBREGs away, the
13140 information on zero/sign bits is lost and further combines can be
13141 missed because of that. */
13143 static void
13145 {
13147 rtx set;
13155 {
13164 {
13167 }
13171 {
13174 }
13177 {
13180 }
13181 else
13183 }
13184 }
13186 /* Check if X, a register, is known to contain a value already
13187 truncated to MODE. In this case we can use a subreg to refer to
13188 the truncated value even though in the generic case we would need
13189 an explicit truncation. */
13191 static bool
13193 {
13205 }
13207 /* If X is a hard reg or a subreg record the mode that the register is
13208 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13209 to turn a truncate into a subreg using this information. Return true
13210 if traversing X is complete. */
13212 static bool
13214 {
13215 machine_mode truncated_mode;
13219 {
13230 }
13231 /* ??? For hard-regs we now record everything. We might be able to
13232 optimize this using last_set_mode. */
13235 else
13243 {
13246 }
13249 }
13251 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13252 the modes they are used in. This can help truning TRUNCATEs into
13253 SUBREGs. */
13255 static void
13257 {
13262 }
13264 /* Scan X for promoted SUBREGs. For each one found,
13265 note what it implies to the registers used in it. */
13267 static void
13269 {
13274 else
13275 {
13281 {
13291 }
13292 }
13293 }
13294 \f
13295 /* Verify that all the registers and memory references mentioned in *LOC are
13296 still valid. *LOC was part of a value set in INSN when label_tick was
13297 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13298 the invalid references with (clobber (const_int 0)) and return 1. This
13299 replacement is useful because we often can get useful information about
13300 the form of a value (e.g., if it was produced by a shift that always
13301 produces -1 or 0) even though we don't know exactly what registers it
13302 was produced from. */
13304 static int
13306 {
13313 {
13319 {
13322 /* If this is a pseudo-register that was only set once and not
13323 live at the beginning of the function, it is always valid. */
13327 && (!REGNO_REG_SET_P
13329 regno)))
13331 {
13335 }
13336 }
13339 }
13340 /* If this is a memory reference, make sure that there were no stores after
13341 it that might have clobbered the value. We don't have alias info, so we
13342 assume any store invalidates it. Moreover, we only have local UIDs, so
13343 we also assume that there were stores in the intervening basic blocks. */
13346 {
13350 }
13353 {
13355 {
13356 /* Check for identical subexpressions. If x contains
13357 identical subexpression we only have to traverse one of
13358 them. */
13360 {
13361 /* Note that at this point x0 has already been checked
13362 and found valid. */
13366 /* If x0 and x1 are identical then x is also valid. */
13370 /* If x1 is identical to a subexpression of x0 then
13371 while checking x0, x1 has already been checked. Thus
13372 it is valid and so as x. */
13377 /* If x0 is identical to a subexpression of x1 then x is
13378 valid iff the rest of x1 is valid. */
13381 return
13385 }
13390 }
13396 }
13398 /* If we haven't found a reason for it to be invalid, it is valid. */
13400 }
13402 /* Get the last value assigned to X, if known. Some registers
13403 in the value may be replaced with (clobber (const_int 0)) if their value
13404 is known longer known reliably. */
13406 static rtx
13408 {
13410 rtx value;
13413 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13414 then convert it to the desired mode. If this is a paradoxical SUBREG,
13415 we cannot predict what values the "extra" bits might have. */
13429 /* If we don't have a value, or if it isn't for this basic block and
13430 it's either a hard register, set more than once, or it's a live
13431 at the beginning of the function, return 0.
13433 Because if it's not live at the beginning of the function then the reg
13434 is always set before being used (is never used without being set).
13435 And, if it's set only once, and it's always set before use, then all
13436 uses must have the same last value, even if it's not from this basic
13437 block. */
13444 || REGNO_REG_SET_P
13448 /* If the value was set in a later insn than the ones we are processing,
13449 we can't use it even if the register was only set once. */
13454 /* If fewer bits were set than what we are asked for now, we cannot use
13455 the value. */
13460 /* If the value has all its registers valid, return it. */
13464 /* Otherwise, make a copy and replace any invalid register with
13465 (clobber (const_int 0)). If that fails for some reason, return 0. */
13472 }
13473 \f
13474 /* Return nonzero if expression X refers to a REG or to memory
13475 that is set in an instruction more recent than FROM_LUID. */
13477 static int
13479 {
13485 {
13489 #ifdef PUSH_ROUNDING
13490 /* Don't allow uses of the stack pointer to be moved,
13491 because we don't know whether the move crosses a push insn. */
13494 #endif
13496 {
13502 }
13504 }
13512 {
13514 {
13519 }
13523 }
13525 }
13526 \f
13527 /* Define three variables used for communication between the following
13528 routines. */
13533 /* Function called via note_stores from reg_dead_at_p.
13535 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13536 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13538 static void
13540 {
13550 }
13552 /* Return nonzero if REG is known to be dead at INSN.
13554 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13555 referencing REG, it is dead. If we hit a SET referencing REG, it is
13556 live. Otherwise, see if it is live or dead at the start of the basic
13557 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13558 must be assumed to be always live. */
13560 static int
13562 {
13563 basic_block block;
13566 /* Set variables for reg_dead_at_p_1. */
13572 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13573 we allow the machine description to decide whether use-and-clobber
13574 patterns are OK. */
13576 {
13580 }
13582 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13583 beginning of basic block. */
13586 {
13588 {
13598 }
13604 }
13606 /* Look at live-in sets for the basic block that we were in. */
13612 }
13613 \f
13614 /* Note hard registers in X that are used. */
13616 static void
13618 {
13624 {
13628 CASE_CONST_ANY:
13633 /* CC0 must die in the insn after it is set, so we don't need to take
13634 special note of it here. */
13639 /* If we are clobbering a MEM, mark any hard registers inside the
13640 address as used. */
13647 /* A hard reg in a wide mode may really be multiple registers.
13648 If so, mark all of them just like the first. */
13650 {
13651 /* None of this applies to the stack, frame or arg pointers. */
13653 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13661 }
13665 {
13666 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13667 the address. */
13679 }
13684 }
13686 /* Recursively scan the operands of this expression. */
13688 {
13692 {
13696 {
13701 }
13702 }
13703 }
13704 }
13705 \f
13706 /* Remove register number REGNO from the dead registers list of INSN.
13708 Return the note used to record the death, if there was one. */
13710 rtx
13712 {
13719 }
13721 /* For each register (hardware or pseudo) used within expression X, if its
13722 death is in an instruction with luid between FROM_LUID (inclusive) and
13723 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13724 list headed by PNOTES.
13726 That said, don't move registers killed by maybe_kill_insn.
13728 This is done when X is being merged by combination into TO_INSN. These
13729 notes will then be distributed as needed. */
13731 static void
13734 {
13740 {
13744 /* Don't move the register if it gets killed in between from and to. */
13753 {
13756 /* It is possible for the call above to return 0. This can occur
13757 when last_death points to I2 or I1 that we combined with.
13758 In that case make a new note.
13760 We must also check for the case where X is a hard register
13761 and NOTE is a death note for a range of hard registers
13762 including X. In that case, we must put REG_DEAD notes for
13763 the remaining registers in place of NOTE. */
13768 {
13777 }
13779 /* If we didn't find any note, or if we found a REG_DEAD note that
13780 covers only part of the given reg, and we have a multi-reg hard
13781 register, then to be safe we must check for REG_DEAD notes
13782 for each register other than the first. They could have
13783 their own REG_DEAD notes lying around. */
13790 {
13797 else
13803 }
13806 {
13809 }
13810 else
13812 }
13815 }
13818 {
13823 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13824 that accesses one word of a multi-word item, some
13825 piece of everything register in the expression is used by
13826 this insn, so remove any old death. */
13827 /* ??? So why do we test for equality of the sizes? */
13836 {
13839 }
13841 /* If this is some other SUBREG, we know it replaces the entire
13842 value, so use that as the destination. */
13846 /* If this is a MEM, adjust deaths of anything used in the address.
13847 For a REG (the only other possibility), the entire value is
13848 being replaced so the old value is not used in this insn. */
13854 }
13863 {
13865 {
13870 }
13873 }
13874 }
13875 \f
13876 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13877 pattern of an insn. X must be a REG. */
13879 static int
13881 {
13885 {
13887 rtx target;
13894 else
13911 }
13919 }
13920 \f
13921 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13922 as appropriate. I3 and I2 are the insns resulting from the combination
13923 insns including FROM (I2 may be zero).
13925 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13926 not need REG_DEAD notes because they are being substituted for. This
13927 saves searching in the most common cases.
13929 Each note in the list is either ignored or placed on some insns, depending
13930 on the type of note. */
13932 static void
13935 {
13937 rtx tem_note;
13941 {
13946 {
13949 /* Doesn't matter much where we put this, as long as it's somewhere.
13950 It is preferable to keep these notes on branches, which is most
13951 likely to be i3. */
13958 else
13959 {
13962 }
13966 /* These notes must remain with the call or trapping instruction. */
13971 else
13972 {
13978 /* ??? Otherwise assume we've combined things such that we
13979 can now prove that the instructions can't trap. Drop the
13980 note in this case. */
13981 }
13985 /* ??? How to distribute between i3-i1. Assume i3 contains the
13986 entire adjustment. Assert i3 contains at least some adjust. */
13988 {
13990 /* fixup_args_size_notes looks at REG_NORETURN note,
13991 so ensure the note is placed there first. */
13993 {
13997 {
14003 }
14004 }
14006 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14007 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14010 && !ACCUMULATE_OUTGOING_ARGS
14012 }
14019 /* These notes must remain with the call. It should not be
14020 possible for both I2 and I3 to be a call. */
14023 else
14024 {
14027 }
14031 /* Any clobbers for i3 may still exist, and so we must process
14032 REG_UNUSED notes from that insn.
14034 Any clobbers from i2 or i1 can only exist if they were added by
14035 recog_for_combine. In that case, recog_for_combine created the
14036 necessary REG_UNUSED notes. Trying to keep any original
14037 REG_UNUSED notes from these insns can cause incorrect output
14038 if it is for the same register as the original i3 dest.
14039 In that case, we will notice that the register is set in i3,
14040 and then add a REG_UNUSED note for the destination of i3, which
14041 is wrong. However, it is possible to have REG_UNUSED notes from
14042 i2 or i1 for register which were both used and clobbered, so
14043 we keep notes from i2 or i1 if they will turn into REG_DEAD
14044 notes. */
14046 /* If this register is set or clobbered in I3, put the note there
14047 unless there is one already. */
14049 {
14057 }
14058 /* Otherwise, if this register is used by I3, then this register
14059 now dies here, so we must put a REG_DEAD note here unless there
14060 is one already. */
14066 {
14069 }
14075 /* These notes say something about results of an insn. We can
14076 only support them if they used to be on I3 in which case they
14077 remain on I3. Otherwise they are ignored.
14079 If the note refers to an expression that is not a constant, we
14080 must also ignore the note since we cannot tell whether the
14081 equivalence is still true. It might be possible to do
14082 slightly better than this (we only have a problem if I2DEST
14083 or I1DEST is present in the expression), but it doesn't
14084 seem worth the trouble. */
14092 /* These notes say something about how a register is used. They must
14093 be present on any use of the register in I2 or I3. */
14098 {
14101 else
14103 }
14108 /* This can show up in several ways -- either directly in the
14109 pattern, or hidden off in the constant pool with (or without?)
14110 a REG_EQUAL note. */
14111 /* ??? Ignore the without-reg_equal-note problem for now. */
14123 {
14126 else
14128 }
14130 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14131 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14132 there. */
14137 {
14144 }
14150 {
14158 }
14162 /* This note says something about the value of a register prior
14163 to the execution of an insn. It is too much trouble to see
14164 if the note is still correct in all situations. It is better
14165 to simply delete it. */
14169 /* If we replaced the right hand side of FROM_INSN with a
14170 REG_EQUAL note, the original use of the dying register
14171 will not have been combined into I3 and I2. In such cases,
14172 FROM_INSN is guaranteed to be the first of the combined
14173 instructions, so we simply need to search back before
14174 FROM_INSN for the previous use or set of this register,
14175 then alter the notes there appropriately.
14177 If the register is used as an input in I3, it dies there.
14178 Similarly for I2, if it is nonzero and adjacent to I3.
14180 If the register is not used as an input in either I3 or I2
14181 and it is not one of the registers we were supposed to eliminate,
14182 there are two possibilities. We might have a non-adjacent I2
14183 or we might have somehow eliminated an additional register
14184 from a computation. For example, we might have had A & B where
14185 we discover that B will always be zero. In this case we will
14186 eliminate the reference to A.
14188 In both cases, we must search to see if we can find a previous
14189 use of A and put the death note there. */
14195 else
14196 {
14207 && !(i2mod
14209 i2mod_old_rhs)))
14214 /* If the new I2 sets the same register that is marked dead
14215 in the note, we do not know where to put the note.
14216 Give up. */
14219 }
14222 {
14226 {
14228 {
14232 }
14234 /* If the register is being set at TEM_INSN, see if that is all
14235 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14236 into a REG_UNUSED note instead. Don't delete sets to
14237 global register vars. */
14241 {
14252 ;
14254 /* Verify that it was the set, and not a clobber that
14255 modified the register.
14257 CC0 targets must be careful to maintain setter/user
14258 pairs. If we cannot delete the setter due to side
14259 effects, mark the user with an UNUSED note instead
14260 of deleting it. */
14264 && (!HAVE_cc0
14268 {
14269 /* Move the notes and links of TEM_INSN elsewhere.
14270 This might delete other dead insns recursively.
14271 First set the pattern to something that won't use
14272 any register. */
14291 /* Delete the setter too. */
14293 {
14306 }
14307 }
14308 else
14309 {
14312 /* If there isn't already a REG_UNUSED note, put one
14313 here. Do not place a REG_DEAD note, even if
14314 the register is also used here; that would not
14315 match the algorithm used in lifetime analysis
14316 and can cause the consistency check in the
14317 scheduler to fail. */
14322 }
14323 }
14327 {
14330 /* If we are doing a 3->2 combination, and we have a
14331 register which formerly died in i3 and was not used
14332 by i2, which now no longer dies in i3 and is used in
14333 i2 but does not die in i2, and place is between i2
14334 and i3, then we may need to move a link from place to
14335 i2. */
14337 && from_insn
14340 {
14344 }
14346 }
14350 }
14352 }
14354 /* If the register is set or already dead at PLACE, we needn't do
14355 anything with this note if it is still a REG_DEAD note.
14356 We check here if it is set at all, not if is it totally replaced,
14357 which is what `dead_or_set_p' checks, so also check for it being
14358 set partially. */
14361 {
14367 {
14368 /* Unless the register previously died in PLACE, clear
14369 last_death. [I no longer understand why this is
14370 being done.] */
14374 }
14375 else
14378 /* If this is a death note for a hard reg that is occupying
14379 multiple registers, ensure that we are still using all
14380 parts of the object. If we find a piece of the object
14381 that is unused, we must arrange for an appropriate REG_DEAD
14382 note to be added for it. However, we can't just emit a USE
14383 and tag the note to it, since the register might actually
14384 be dead; so we recourse, and the recursive call then finds
14385 the previous insn that used this register. */
14388 {
14397 {
14400 }
14403 {
14404 /* Put only REG_DEAD notes for pieces that are
14405 not already dead or set. */
14409 {
14416 {
14418 NULL_RTX);
14422 NULL_RTX);
14423 }
14428 {
14430 {
14434 }
14438 {
14441 }
14442 }
14443 }
14446 }
14447 }
14448 }
14452 /* Any other notes should not be present at this point in the
14453 compilation. */
14455 }
14458 {
14461 }
14465 }
14466 }
14467 \f
14468 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14469 I3, I2, and I1 to new locations. This is also called to add a link
14470 pointing at I3 when I3's destination is changed. */
14472 static void
14474 {
14478 {
14485 /* If the insn that this link points to is a NOTE, ignore it. */
14494 {
14497 {
14513 }
14516 }
14517 else
14527 /* A LOG_LINK is defined as being placed on the first insn that uses
14528 a register and points to the insn that sets the register. Start
14529 searching at the next insn after the target of the link and stop
14530 when we reach a set of the register or the end of the basic block.
14532 Note that this correctly handles the link that used to point from
14533 I3 to I2. Also note that not much searching is typically done here
14534 since most links don't point very far away. */
14543 {
14547 }
14550 {
14553 }
14557 /* If we found a place to put the link, place it there unless there
14558 is already a link to the same insn as LINK at that point. */
14561 {
14569 {
14573 /* Set added_links_insn to the earliest insn we added a
14574 link to. */
14578 }
14579 }
14580 }
14581 }
14582 \f
14583 /* Check for any register or memory mentioned in EQUIV that is not
14584 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14585 of EXPR where some registers may have been replaced by constants. */
14587 static bool
14589 {
14592 {
14597 }
14599 }
14600 \f
14601 DEBUG_FUNCTION void
14603 {
14604 fprintf
14606 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14608 }
14610 void
14612 {
14613 fprintf
14615 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14617 }
14618 \f
14619 /* Try combining insns through substitution. */
14620 static unsigned int
14622 {
14632 rebuild_jump_labels_after_combine
14635 /* Combining insns may have turned an indirect jump into a
14636 direct jump. Rebuild the JUMP_LABEL fields of jumping
14637 instructions. */
14639 {
14646 }
14650 }
14655 {
14665 };
14668 {
14672 {}
14674 /* opt_pass methods: */
14677 {
14679 }
14685 rtl_opt_pass *
14687 {
14689 }