1 @c Copyright (C) 1988-2014 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Overview:: How the machine description is used.
23 * Patterns:: How to write instruction patterns.
24 * Example:: An explained example of a @code{define_insn} pattern.
25 * RTL Template:: The RTL template defines what insns match a pattern.
26 * Output Template:: The output template says how to make assembler code
28 * Output Statement:: For more generality, write C code to output
30 * Predicates:: Controlling what kinds of operands can be used
32 * Constraints:: Fine-tuning operand selection.
33 * Standard Names:: Names mark patterns to use for code generation.
34 * Pattern Ordering:: When the order of patterns makes a difference.
35 * Dependent Patterns:: Having one pattern may make you need another.
36 * Jump Patterns:: Special considerations for patterns for jump insns.
37 * Looping Patterns:: How to define patterns for special looping insns.
38 * Insn Canonicalizations::Canonicalization of Instructions
39 * Expander Definitions::Generating a sequence of several RTL insns
40 for a standard operation.
41 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
42 * Including Patterns:: Including Patterns in Machine Descriptions.
43 * Peephole Definitions::Defining machine-specific peephole optimizations.
44 * Insn Attributes:: Specifying the value of attributes for generated insns.
45 * Conditional Execution::Generating @code{define_insn} patterns for
47 * Define Subst:: Generating @code{define_insn} and @code{define_expand}
48 patterns from other patterns.
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
668 If you just need a little bit of C code in one (or a few) alternatives,
669 you can use @samp{*} inside of a @samp{@@} multi-alternative template:
674 [(set (match_operand:SI 0 "general_operand" "=r,<,m")
679 * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\";
687 @cindex operand predicates
688 @cindex operator predicates
690 A predicate determines whether a @code{match_operand} or
691 @code{match_operator} expression matches, and therefore whether the
692 surrounding instruction pattern will be used for that combination of
693 operands. GCC has a number of machine-independent predicates, and you
694 can define machine-specific predicates as needed. By convention,
695 predicates used with @code{match_operand} have names that end in
696 @samp{_operand}, and those used with @code{match_operator} have names
697 that end in @samp{_operator}.
699 All predicates are Boolean functions (in the mathematical sense) of
700 two arguments: the RTL expression that is being considered at that
701 position in the instruction pattern, and the machine mode that the
702 @code{match_operand} or @code{match_operator} specifies. In this
703 section, the first argument is called @var{op} and the second argument
704 @var{mode}. Predicates can be called from C as ordinary two-argument
705 functions; this can be useful in output templates or other
706 machine-specific code.
708 Operand predicates can allow operands that are not actually acceptable
709 to the hardware, as long as the constraints give reload the ability to
710 fix them up (@pxref{Constraints}). However, GCC will usually generate
711 better code if the predicates specify the requirements of the machine
712 instructions as closely as possible. Reload cannot fix up operands
713 that must be constants (``immediate operands''); you must use a
714 predicate that allows only constants, or else enforce the requirement
715 in the extra condition.
717 @cindex predicates and machine modes
718 @cindex normal predicates
719 @cindex special predicates
720 Most predicates handle their @var{mode} argument in a uniform manner.
721 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
722 any mode. If @var{mode} is anything else, then @var{op} must have the
723 same mode, unless @var{op} is a @code{CONST_INT} or integer
724 @code{CONST_DOUBLE}. These RTL expressions always have
725 @code{VOIDmode}, so it would be counterproductive to check that their
726 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
727 integer @code{CONST_DOUBLE} check that the value stored in the
728 constant will fit in the requested mode.
730 Predicates with this behavior are called @dfn{normal}.
731 @command{genrecog} can optimize the instruction recognizer based on
732 knowledge of how normal predicates treat modes. It can also diagnose
733 certain kinds of common errors in the use of normal predicates; for
734 instance, it is almost always an error to use a normal predicate
735 without specifying a mode.
737 Predicates that do something different with their @var{mode} argument
738 are called @dfn{special}. The generic predicates
739 @code{address_operand} and @code{pmode_register_operand} are special
740 predicates. @command{genrecog} does not do any optimizations or
741 diagnosis when special predicates are used.
744 * Machine-Independent Predicates:: Predicates available to all back ends.
745 * Defining Predicates:: How to write machine-specific predicate
749 @node Machine-Independent Predicates
750 @subsection Machine-Independent Predicates
751 @cindex machine-independent predicates
752 @cindex generic predicates
754 These are the generic predicates available to all back ends. They are
755 defined in @file{recog.c}. The first category of predicates allow
756 only constant, or @dfn{immediate}, operands.
758 @defun immediate_operand
759 This predicate allows any sort of constant that fits in @var{mode}.
760 It is an appropriate choice for instructions that take operands that
764 @defun const_int_operand
765 This predicate allows any @code{CONST_INT} expression that fits in
766 @var{mode}. It is an appropriate choice for an immediate operand that
767 does not allow a symbol or label.
770 @defun const_double_operand
771 This predicate accepts any @code{CONST_DOUBLE} expression that has
772 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
773 accept @code{CONST_INT}. It is intended for immediate floating point
778 The second category of predicates allow only some kind of machine
781 @defun register_operand
782 This predicate allows any @code{REG} or @code{SUBREG} expression that
783 is valid for @var{mode}. It is often suitable for arithmetic
784 instruction operands on a RISC machine.
787 @defun pmode_register_operand
788 This is a slight variant on @code{register_operand} which works around
789 a limitation in the machine-description reader.
792 (match_operand @var{n} "pmode_register_operand" @var{constraint})
799 (match_operand:P @var{n} "register_operand" @var{constraint})
803 would mean, if the machine-description reader accepted @samp{:P}
804 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
805 alias for some other mode, and might vary with machine-specific
806 options. @xref{Misc}.
809 @defun scratch_operand
810 This predicate allows hard registers and @code{SCRATCH} expressions,
811 but not pseudo-registers. It is used internally by @code{match_scratch};
812 it should not be used directly.
816 The third category of predicates allow only some kind of memory reference.
818 @defun memory_operand
819 This predicate allows any valid reference to a quantity of mode
820 @var{mode} in memory, as determined by the weak form of
821 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
824 @defun address_operand
825 This predicate is a little unusual; it allows any operand that is a
826 valid expression for the @emph{address} of a quantity of mode
827 @var{mode}, again determined by the weak form of
828 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
829 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
830 @code{memory_operand}, then @var{exp} is acceptable to
831 @code{address_operand}. Note that @var{exp} does not necessarily have
835 @defun indirect_operand
836 This is a stricter form of @code{memory_operand} which allows only
837 memory references with a @code{general_operand} as the address
838 expression. New uses of this predicate are discouraged, because
839 @code{general_operand} is very permissive, so it's hard to tell what
840 an @code{indirect_operand} does or does not allow. If a target has
841 different requirements for memory operands for different instructions,
842 it is better to define target-specific predicates which enforce the
843 hardware's requirements explicitly.
847 This predicate allows a memory reference suitable for pushing a value
848 onto the stack. This will be a @code{MEM} which refers to
849 @code{stack_pointer_rtx}, with a side-effect in its address expression
850 (@pxref{Incdec}); which one is determined by the
851 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
855 This predicate allows a memory reference suitable for popping a value
856 off the stack. Again, this will be a @code{MEM} referring to
857 @code{stack_pointer_rtx}, with a side-effect in its address
858 expression. However, this time @code{STACK_POP_CODE} is expected.
862 The fourth category of predicates allow some combination of the above
865 @defun nonmemory_operand
866 This predicate allows any immediate or register operand valid for @var{mode}.
869 @defun nonimmediate_operand
870 This predicate allows any register or memory operand valid for @var{mode}.
873 @defun general_operand
874 This predicate allows any immediate, register, or memory operand
875 valid for @var{mode}.
879 Finally, there are two generic operator predicates.
881 @defun comparison_operator
882 This predicate matches any expression which performs an arithmetic
883 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
887 @defun ordered_comparison_operator
888 This predicate matches any expression which performs an arithmetic
889 comparison in @var{mode} and whose expression code is valid for integer
890 modes; that is, the expression code will be one of @code{eq}, @code{ne},
891 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
892 @code{ge}, @code{geu}.
895 @node Defining Predicates
896 @subsection Defining Machine-Specific Predicates
897 @cindex defining predicates
898 @findex define_predicate
899 @findex define_special_predicate
901 Many machines have requirements for their operands that cannot be
902 expressed precisely using the generic predicates. You can define
903 additional predicates using @code{define_predicate} and
904 @code{define_special_predicate} expressions. These expressions have
909 The name of the predicate, as it will be referred to in
910 @code{match_operand} or @code{match_operator} expressions.
913 An RTL expression which evaluates to true if the predicate allows the
914 operand @var{op}, false if it does not. This expression can only use
915 the following RTL codes:
919 When written inside a predicate expression, a @code{MATCH_OPERAND}
920 expression evaluates to true if the predicate it names would allow
921 @var{op}. The operand number and constraint are ignored. Due to
922 limitations in @command{genrecog}, you can only refer to generic
923 predicates and predicates that have already been defined.
926 This expression evaluates to true if @var{op} or a specified
927 subexpression of @var{op} has one of a given list of RTX codes.
929 The first operand of this expression is a string constant containing a
930 comma-separated list of RTX code names (in lower case). These are the
931 codes for which the @code{MATCH_CODE} will be true.
933 The second operand is a string constant which indicates what
934 subexpression of @var{op} to examine. If it is absent or the empty
935 string, @var{op} itself is examined. Otherwise, the string constant
936 must be a sequence of digits and/or lowercase letters. Each character
937 indicates a subexpression to extract from the current expression; for
938 the first character this is @var{op}, for the second and subsequent
939 characters it is the result of the previous character. A digit
940 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
941 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
942 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
943 @code{MATCH_CODE} then examines the RTX code of the subexpression
944 extracted by the complete string. It is not possible to extract
945 components of an @code{rtvec} that is not at position 0 within its RTX
949 This expression has one operand, a string constant containing a C
950 expression. The predicate's arguments, @var{op} and @var{mode}, are
951 available with those names in the C expression. The @code{MATCH_TEST}
952 evaluates to true if the C expression evaluates to a nonzero value.
953 @code{MATCH_TEST} expressions must not have side effects.
959 The basic @samp{MATCH_} expressions can be combined using these
960 logical operators, which have the semantics of the C operators
961 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
962 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
963 arbitrary number of arguments; this has exactly the same effect as
964 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
968 An optional block of C code, which should execute
969 @samp{@w{return true}} if the predicate is found to match and
970 @samp{@w{return false}} if it does not. It must not have any side
971 effects. The predicate arguments, @var{op} and @var{mode}, are
972 available with those names.
974 If a code block is present in a predicate definition, then the RTL
975 expression must evaluate to true @emph{and} the code block must
976 execute @samp{@w{return true}} for the predicate to allow the operand.
977 The RTL expression is evaluated first; do not re-check anything in the
978 code block that was checked in the RTL expression.
981 The program @command{genrecog} scans @code{define_predicate} and
982 @code{define_special_predicate} expressions to determine which RTX
983 codes are possibly allowed. You should always make this explicit in
984 the RTL predicate expression, using @code{MATCH_OPERAND} and
987 Here is an example of a simple predicate definition, from the IA64
992 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
993 (define_predicate "small_addr_symbolic_operand"
994 (and (match_code "symbol_ref")
995 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
1000 And here is another, showing the use of the C block.
1004 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
1005 (define_predicate "gr_register_operand"
1006 (match_operand 0 "register_operand")
1009 if (GET_CODE (op) == SUBREG)
1010 op = SUBREG_REG (op);
1013 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1018 Predicates written with @code{define_predicate} automatically include
1019 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1020 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1021 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1022 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1023 kind of constant fits in the requested mode. This is because
1024 target-specific predicates that take constants usually have to do more
1025 stringent value checks anyway. If you need the exact same treatment
1026 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1027 provide, use a @code{MATCH_OPERAND} subexpression to call
1028 @code{const_int_operand}, @code{const_double_operand}, or
1029 @code{immediate_operand}.
1031 Predicates written with @code{define_special_predicate} do not get any
1032 automatic mode checks, and are treated as having special mode handling
1033 by @command{genrecog}.
1035 The program @command{genpreds} is responsible for generating code to
1036 test predicates. It also writes a header file containing function
1037 declarations for all machine-specific predicates. It is not necessary
1038 to declare these predicates in @file{@var{cpu}-protos.h}.
1041 @c Most of this node appears by itself (in a different place) even
1042 @c when the INTERNALS flag is clear. Passages that require the internals
1043 @c manual's context are conditionalized to appear only in the internals manual.
1046 @section Operand Constraints
1047 @cindex operand constraints
1050 Each @code{match_operand} in an instruction pattern can specify
1051 constraints for the operands allowed. The constraints allow you to
1052 fine-tune matching within the set of operands allowed by the
1058 @section Constraints for @code{asm} Operands
1059 @cindex operand constraints, @code{asm}
1060 @cindex constraints, @code{asm}
1061 @cindex @code{asm} constraints
1063 Here are specific details on what constraint letters you can use with
1064 @code{asm} operands.
1066 Constraints can say whether
1067 an operand may be in a register, and which kinds of register; whether the
1068 operand can be a memory reference, and which kinds of address; whether the
1069 operand may be an immediate constant, and which possible values it may
1070 have. Constraints can also require two operands to match.
1071 Side-effects aren't allowed in operands of inline @code{asm}, unless
1072 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1073 that the side-effects will happen exactly once in an instruction that can update
1074 the addressing register.
1078 * Simple Constraints:: Basic use of constraints.
1079 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1080 * Class Preferences:: Constraints guide which hard register to put things in.
1081 * Modifiers:: More precise control over effects of constraints.
1082 * Machine Constraints:: Existing constraints for some particular machines.
1083 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1084 * Define Constraints:: How to define machine-specific constraints.
1085 * C Constraint Interface:: How to test constraints from C code.
1091 * Simple Constraints:: Basic use of constraints.
1092 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1093 * Modifiers:: More precise control over effects of constraints.
1094 * Machine Constraints:: Special constraints for some particular machines.
1098 @node Simple Constraints
1099 @subsection Simple Constraints
1100 @cindex simple constraints
1102 The simplest kind of constraint is a string full of letters, each of
1103 which describes one kind of operand that is permitted. Here are
1104 the letters that are allowed:
1108 Whitespace characters are ignored and can be inserted at any position
1109 except the first. This enables each alternative for different operands to
1110 be visually aligned in the machine description even if they have different
1111 number of constraints and modifiers.
1113 @cindex @samp{m} in constraint
1114 @cindex memory references in constraints
1116 A memory operand is allowed, with any kind of address that the machine
1117 supports in general.
1118 Note that the letter used for the general memory constraint can be
1119 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1121 @cindex offsettable address
1122 @cindex @samp{o} in constraint
1124 A memory operand is allowed, but only if the address is
1125 @dfn{offsettable}. This means that adding a small integer (actually,
1126 the width in bytes of the operand, as determined by its machine mode)
1127 may be added to the address and the result is also a valid memory
1130 @cindex autoincrement/decrement addressing
1131 For example, an address which is constant is offsettable; so is an
1132 address that is the sum of a register and a constant (as long as a
1133 slightly larger constant is also within the range of address-offsets
1134 supported by the machine); but an autoincrement or autodecrement
1135 address is not offsettable. More complicated indirect/indexed
1136 addresses may or may not be offsettable depending on the other
1137 addressing modes that the machine supports.
1139 Note that in an output operand which can be matched by another
1140 operand, the constraint letter @samp{o} is valid only when accompanied
1141 by both @samp{<} (if the target machine has predecrement addressing)
1142 and @samp{>} (if the target machine has preincrement addressing).
1144 @cindex @samp{V} in constraint
1146 A memory operand that is not offsettable. In other words, anything that
1147 would fit the @samp{m} constraint but not the @samp{o} constraint.
1149 @cindex @samp{<} in constraint
1151 A memory operand with autodecrement addressing (either predecrement or
1152 postdecrement) is allowed. In inline @code{asm} this constraint is only
1153 allowed if the operand is used exactly once in an instruction that can
1154 handle the side-effects. Not using an operand with @samp{<} in constraint
1155 string in the inline @code{asm} pattern at all or using it in multiple
1156 instructions isn't valid, because the side-effects wouldn't be performed
1157 or would be performed more than once. Furthermore, on some targets
1158 the operand with @samp{<} in constraint string must be accompanied by
1159 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1160 or @code{%P0} on IA-64.
1162 @cindex @samp{>} in constraint
1164 A memory operand with autoincrement addressing (either preincrement or
1165 postincrement) is allowed. In inline @code{asm} the same restrictions
1166 as for @samp{<} apply.
1168 @cindex @samp{r} in constraint
1169 @cindex registers in constraints
1171 A register operand is allowed provided that it is in a general
1174 @cindex constants in constraints
1175 @cindex @samp{i} in constraint
1177 An immediate integer operand (one with constant value) is allowed.
1178 This includes symbolic constants whose values will be known only at
1179 assembly time or later.
1181 @cindex @samp{n} in constraint
1183 An immediate integer operand with a known numeric value is allowed.
1184 Many systems cannot support assembly-time constants for operands less
1185 than a word wide. Constraints for these operands should use @samp{n}
1186 rather than @samp{i}.
1188 @cindex @samp{I} in constraint
1189 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1190 Other letters in the range @samp{I} through @samp{P} may be defined in
1191 a machine-dependent fashion to permit immediate integer operands with
1192 explicit integer values in specified ranges. For example, on the
1193 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1194 This is the range permitted as a shift count in the shift
1197 @cindex @samp{E} in constraint
1199 An immediate floating operand (expression code @code{const_double}) is
1200 allowed, but only if the target floating point format is the same as
1201 that of the host machine (on which the compiler is running).
1203 @cindex @samp{F} in constraint
1205 An immediate floating operand (expression code @code{const_double} or
1206 @code{const_vector}) is allowed.
1208 @cindex @samp{G} in constraint
1209 @cindex @samp{H} in constraint
1210 @item @samp{G}, @samp{H}
1211 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1212 permit immediate floating operands in particular ranges of values.
1214 @cindex @samp{s} in constraint
1216 An immediate integer operand whose value is not an explicit integer is
1219 This might appear strange; if an insn allows a constant operand with a
1220 value not known at compile time, it certainly must allow any known
1221 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1222 better code to be generated.
1224 For example, on the 68000 in a fullword instruction it is possible to
1225 use an immediate operand; but if the immediate value is between @minus{}128
1226 and 127, better code results from loading the value into a register and
1227 using the register. This is because the load into the register can be
1228 done with a @samp{moveq} instruction. We arrange for this to happen
1229 by defining the letter @samp{K} to mean ``any integer outside the
1230 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1233 @cindex @samp{g} in constraint
1235 Any register, memory or immediate integer operand is allowed, except for
1236 registers that are not general registers.
1238 @cindex @samp{X} in constraint
1241 Any operand whatsoever is allowed, even if it does not satisfy
1242 @code{general_operand}. This is normally used in the constraint of
1243 a @code{match_scratch} when certain alternatives will not actually
1244 require a scratch register.
1247 Any operand whatsoever is allowed.
1250 @cindex @samp{0} in constraint
1251 @cindex digits in constraint
1252 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1253 An operand that matches the specified operand number is allowed. If a
1254 digit is used together with letters within the same alternative, the
1255 digit should come last.
1257 This number is allowed to be more than a single digit. If multiple
1258 digits are encountered consecutively, they are interpreted as a single
1259 decimal integer. There is scant chance for ambiguity, since to-date
1260 it has never been desirable that @samp{10} be interpreted as matching
1261 either operand 1 @emph{or} operand 0. Should this be desired, one
1262 can use multiple alternatives instead.
1264 @cindex matching constraint
1265 @cindex constraint, matching
1266 This is called a @dfn{matching constraint} and what it really means is
1267 that the assembler has only a single operand that fills two roles
1269 considered separate in the RTL insn. For example, an add insn has two
1270 input operands and one output operand in the RTL, but on most CISC
1273 which @code{asm} distinguishes. For example, an add instruction uses
1274 two input operands and an output operand, but on most CISC
1276 machines an add instruction really has only two operands, one of them an
1277 input-output operand:
1283 Matching constraints are used in these circumstances.
1284 More precisely, the two operands that match must include one input-only
1285 operand and one output-only operand. Moreover, the digit must be a
1286 smaller number than the number of the operand that uses it in the
1290 For operands to match in a particular case usually means that they
1291 are identical-looking RTL expressions. But in a few special cases
1292 specific kinds of dissimilarity are allowed. For example, @code{*x}
1293 as an input operand will match @code{*x++} as an output operand.
1294 For proper results in such cases, the output template should always
1295 use the output-operand's number when printing the operand.
1298 @cindex load address instruction
1299 @cindex push address instruction
1300 @cindex address constraints
1301 @cindex @samp{p} in constraint
1303 An operand that is a valid memory address is allowed. This is
1304 for ``load address'' and ``push address'' instructions.
1306 @findex address_operand
1307 @samp{p} in the constraint must be accompanied by @code{address_operand}
1308 as the predicate in the @code{match_operand}. This predicate interprets
1309 the mode specified in the @code{match_operand} as the mode of the memory
1310 reference for which the address would be valid.
1312 @cindex other register constraints
1313 @cindex extensible constraints
1314 @item @var{other-letters}
1315 Other letters can be defined in machine-dependent fashion to stand for
1316 particular classes of registers or other arbitrary operand types.
1317 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1318 for data, address and floating point registers.
1322 In order to have valid assembler code, each operand must satisfy
1323 its constraint. But a failure to do so does not prevent the pattern
1324 from applying to an insn. Instead, it directs the compiler to modify
1325 the code so that the constraint will be satisfied. Usually this is
1326 done by copying an operand into a register.
1328 Contrast, therefore, the two instruction patterns that follow:
1332 [(set (match_operand:SI 0 "general_operand" "=r")
1333 (plus:SI (match_dup 0)
1334 (match_operand:SI 1 "general_operand" "r")))]
1340 which has two operands, one of which must appear in two places, and
1344 [(set (match_operand:SI 0 "general_operand" "=r")
1345 (plus:SI (match_operand:SI 1 "general_operand" "0")
1346 (match_operand:SI 2 "general_operand" "r")))]
1352 which has three operands, two of which are required by a constraint to be
1353 identical. If we are considering an insn of the form
1356 (insn @var{n} @var{prev} @var{next}
1358 (plus:SI (reg:SI 6) (reg:SI 109)))
1363 the first pattern would not apply at all, because this insn does not
1364 contain two identical subexpressions in the right place. The pattern would
1365 say, ``That does not look like an add instruction; try other patterns''.
1366 The second pattern would say, ``Yes, that's an add instruction, but there
1367 is something wrong with it''. It would direct the reload pass of the
1368 compiler to generate additional insns to make the constraint true. The
1369 results might look like this:
1372 (insn @var{n2} @var{prev} @var{n}
1373 (set (reg:SI 3) (reg:SI 6))
1376 (insn @var{n} @var{n2} @var{next}
1378 (plus:SI (reg:SI 3) (reg:SI 109)))
1382 It is up to you to make sure that each operand, in each pattern, has
1383 constraints that can handle any RTL expression that could be present for
1384 that operand. (When multiple alternatives are in use, each pattern must,
1385 for each possible combination of operand expressions, have at least one
1386 alternative which can handle that combination of operands.) The
1387 constraints don't need to @emph{allow} any possible operand---when this is
1388 the case, they do not constrain---but they must at least point the way to
1389 reloading any possible operand so that it will fit.
1393 If the constraint accepts whatever operands the predicate permits,
1394 there is no problem: reloading is never necessary for this operand.
1396 For example, an operand whose constraints permit everything except
1397 registers is safe provided its predicate rejects registers.
1399 An operand whose predicate accepts only constant values is safe
1400 provided its constraints include the letter @samp{i}. If any possible
1401 constant value is accepted, then nothing less than @samp{i} will do;
1402 if the predicate is more selective, then the constraints may also be
1406 Any operand expression can be reloaded by copying it into a register.
1407 So if an operand's constraints allow some kind of register, it is
1408 certain to be safe. It need not permit all classes of registers; the
1409 compiler knows how to copy a register into another register of the
1410 proper class in order to make an instruction valid.
1412 @cindex nonoffsettable memory reference
1413 @cindex memory reference, nonoffsettable
1415 A nonoffsettable memory reference can be reloaded by copying the
1416 address into a register. So if the constraint uses the letter
1417 @samp{o}, all memory references are taken care of.
1420 A constant operand can be reloaded by allocating space in memory to
1421 hold it as preinitialized data. Then the memory reference can be used
1422 in place of the constant. So if the constraint uses the letters
1423 @samp{o} or @samp{m}, constant operands are not a problem.
1426 If the constraint permits a constant and a pseudo register used in an insn
1427 was not allocated to a hard register and is equivalent to a constant,
1428 the register will be replaced with the constant. If the predicate does
1429 not permit a constant and the insn is re-recognized for some reason, the
1430 compiler will crash. Thus the predicate must always recognize any
1431 objects allowed by the constraint.
1434 If the operand's predicate can recognize registers, but the constraint does
1435 not permit them, it can make the compiler crash. When this operand happens
1436 to be a register, the reload pass will be stymied, because it does not know
1437 how to copy a register temporarily into memory.
1439 If the predicate accepts a unary operator, the constraint applies to the
1440 operand. For example, the MIPS processor at ISA level 3 supports an
1441 instruction which adds two registers in @code{SImode} to produce a
1442 @code{DImode} result, but only if the registers are correctly sign
1443 extended. This predicate for the input operands accepts a
1444 @code{sign_extend} of an @code{SImode} register. Write the constraint
1445 to indicate the type of register that is required for the operand of the
1449 @node Multi-Alternative
1450 @subsection Multiple Alternative Constraints
1451 @cindex multiple alternative constraints
1453 Sometimes a single instruction has multiple alternative sets of possible
1454 operands. For example, on the 68000, a logical-or instruction can combine
1455 register or an immediate value into memory, or it can combine any kind of
1456 operand into a register; but it cannot combine one memory location into
1459 These constraints are represented as multiple alternatives. An alternative
1460 can be described by a series of letters for each operand. The overall
1461 constraint for an operand is made from the letters for this operand
1462 from the first alternative, a comma, the letters for this operand from
1463 the second alternative, a comma, and so on until the last alternative.
1465 Here is how it is done for fullword logical-or on the 68000:
1468 (define_insn "iorsi3"
1469 [(set (match_operand:SI 0 "general_operand" "=m,d")
1470 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1471 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1475 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1476 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1477 2. The second alternative has @samp{d} (data register) for operand 0,
1478 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1479 @samp{%} in the constraints apply to all the alternatives; their
1480 meaning is explained in the next section (@pxref{Class Preferences}).
1483 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1484 If all the operands fit any one alternative, the instruction is valid.
1485 Otherwise, for each alternative, the compiler counts how many instructions
1486 must be added to copy the operands so that that alternative applies.
1487 The alternative requiring the least copying is chosen. If two alternatives
1488 need the same amount of copying, the one that comes first is chosen.
1489 These choices can be altered with the @samp{?} and @samp{!} characters:
1492 @cindex @samp{?} in constraint
1493 @cindex question mark
1495 Disparage slightly the alternative that the @samp{?} appears in,
1496 as a choice when no alternative applies exactly. The compiler regards
1497 this alternative as one unit more costly for each @samp{?} that appears
1500 @cindex @samp{!} in constraint
1501 @cindex exclamation point
1503 Disparage severely the alternative that the @samp{!} appears in.
1504 This alternative can still be used if it fits without reloading,
1505 but if reloading is needed, some other alternative will be used.
1509 When an insn pattern has multiple alternatives in its constraints, often
1510 the appearance of the assembler code is determined mostly by which
1511 alternative was matched. When this is so, the C code for writing the
1512 assembler code can use the variable @code{which_alternative}, which is
1513 the ordinal number of the alternative that was actually satisfied (0 for
1514 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1518 @node Class Preferences
1519 @subsection Register Class Preferences
1520 @cindex class preference constraints
1521 @cindex register class preference constraints
1523 @cindex voting between constraint alternatives
1524 The operand constraints have another function: they enable the compiler
1525 to decide which kind of hardware register a pseudo register is best
1526 allocated to. The compiler examines the constraints that apply to the
1527 insns that use the pseudo register, looking for the machine-dependent
1528 letters such as @samp{d} and @samp{a} that specify classes of registers.
1529 The pseudo register is put in whichever class gets the most ``votes''.
1530 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1531 favor of a general register. The machine description says which registers
1532 are considered general.
1534 Of course, on some machines all registers are equivalent, and no register
1535 classes are defined. Then none of this complexity is relevant.
1539 @subsection Constraint Modifier Characters
1540 @cindex modifiers in constraints
1541 @cindex constraint modifier characters
1543 @c prevent bad page break with this line
1544 Here are constraint modifier characters.
1547 @cindex @samp{=} in constraint
1549 Means that this operand is write-only for this instruction: the previous
1550 value is discarded and replaced by output data.
1552 @cindex @samp{+} in constraint
1554 Means that this operand is both read and written by the instruction.
1556 When the compiler fixes up the operands to satisfy the constraints,
1557 it needs to know which operands are inputs to the instruction and
1558 which are outputs from it. @samp{=} identifies an output; @samp{+}
1559 identifies an operand that is both input and output; all other operands
1560 are assumed to be input only.
1562 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1563 first character of the constraint string.
1565 @cindex @samp{&} in constraint
1566 @cindex earlyclobber operand
1568 Means (in a particular alternative) that this operand is an
1569 @dfn{earlyclobber} operand, which is modified before the instruction is
1570 finished using the input operands. Therefore, this operand may not lie
1571 in a register that is used as an input operand or as part of any memory
1574 @samp{&} applies only to the alternative in which it is written. In
1575 constraints with multiple alternatives, sometimes one alternative
1576 requires @samp{&} while others do not. See, for example, the
1577 @samp{movdf} insn of the 68000.
1579 An input operand can be tied to an earlyclobber operand if its only
1580 use as an input occurs before the early result is written. Adding
1581 alternatives of this form often allows GCC to produce better code
1582 when only some of the inputs can be affected by the earlyclobber.
1583 See, for example, the @samp{mulsi3} insn of the ARM@.
1585 @samp{&} does not obviate the need to write @samp{=}.
1587 @cindex @samp{%} in constraint
1589 Declares the instruction to be commutative for this operand and the
1590 following operand. This means that the compiler may interchange the
1591 two operands if that is the cheapest way to make all operands fit the
1594 This is often used in patterns for addition instructions
1595 that really have only two operands: the result must go in one of the
1596 arguments. Here for example, is how the 68000 halfword-add
1597 instruction is defined:
1600 (define_insn "addhi3"
1601 [(set (match_operand:HI 0 "general_operand" "=m,r")
1602 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1603 (match_operand:HI 2 "general_operand" "di,g")))]
1607 GCC can only handle one commutative pair in an asm; if you use more,
1608 the compiler may fail. Note that you need not use the modifier if
1609 the two alternatives are strictly identical; this would only waste
1610 time in the reload pass. The modifier is not operational after
1611 register allocation, so the result of @code{define_peephole2}
1612 and @code{define_split}s performed after reload cannot rely on
1613 @samp{%} to make the intended insn match.
1615 @cindex @samp{#} in constraint
1617 Says that all following characters, up to the next comma, are to be
1618 ignored as a constraint. They are significant only for choosing
1619 register preferences.
1621 @cindex @samp{*} in constraint
1623 Says that the following character should be ignored when choosing
1624 register preferences. @samp{*} has no effect on the meaning of the
1625 constraint as a constraint, and no effect on reloading. For LRA
1626 @samp{*} additionally disparages slightly the alternative if the
1627 following character matches the operand.
1630 Here is an example: the 68000 has an instruction to sign-extend a
1631 halfword in a data register, and can also sign-extend a value by
1632 copying it into an address register. While either kind of register is
1633 acceptable, the constraints on an address-register destination are
1634 less strict, so it is best if register allocation makes an address
1635 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1636 constraint letter (for data register) is ignored when computing
1637 register preferences.
1640 (define_insn "extendhisi2"
1641 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1643 (match_operand:HI 1 "general_operand" "0,g")))]
1649 @node Machine Constraints
1650 @subsection Constraints for Particular Machines
1651 @cindex machine specific constraints
1652 @cindex constraints, machine specific
1654 Whenever possible, you should use the general-purpose constraint letters
1655 in @code{asm} arguments, since they will convey meaning more readily to
1656 people reading your code. Failing that, use the constraint letters
1657 that usually have very similar meanings across architectures. The most
1658 commonly used constraints are @samp{m} and @samp{r} (for memory and
1659 general-purpose registers respectively; @pxref{Simple Constraints}), and
1660 @samp{I}, usually the letter indicating the most common
1661 immediate-constant format.
1663 Each architecture defines additional constraints. These constraints
1664 are used by the compiler itself for instruction generation, as well as
1665 for @code{asm} statements; therefore, some of the constraints are not
1666 particularly useful for @code{asm}. Here is a summary of some of the
1667 machine-dependent constraints available on some particular machines;
1668 it includes both constraints that are useful for @code{asm} and
1669 constraints that aren't. The compiler source file mentioned in the
1670 table heading for each architecture is the definitive reference for
1671 the meanings of that architecture's constraints.
1674 @item AArch64 family---@file{config/aarch64/constraints.md}
1677 The stack pointer register (@code{SP})
1680 Floating point or SIMD vector register
1683 Integer constant that is valid as an immediate operand in an @code{ADD}
1687 Integer constant that is valid as an immediate operand in a @code{SUB}
1688 instruction (once negated)
1691 Integer constant that can be used with a 32-bit logical instruction
1694 Integer constant that can be used with a 64-bit logical instruction
1697 Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
1698 pseudo instruction. The @code{MOV} may be assembled to one of several different
1699 machine instructions depending on the value
1702 Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
1706 An absolute symbolic address or a label reference
1709 Floating point constant zero
1712 Integer constant zero
1715 The high part (bits 12 and upwards) of the pc-relative address of a symbol
1716 within 4GB of the instruction
1719 A memory address which uses a single base register with no offset
1722 A memory address suitable for a load/store pair instruction in SI, DI, SF and
1728 @item ARC ---@file{config/arc/constraints.md}
1731 Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
1732 @code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
1733 option is in effect.
1736 Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
1737 instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
1738 This constraint can only match when the @option{-mq}
1739 option is in effect.
1741 ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
1744 A signed 12-bit integer constant.
1747 constant for arithmetic/logical operations. This might be any constant
1748 that can be put into a long immediate by the assmbler or linker without
1749 involving a PIC relocation.
1752 A 3-bit unsigned integer constant.
1755 A 6-bit unsigned integer constant.
1758 One's complement of a 6-bit unsigned integer constant.
1761 Two's complement of a 6-bit unsigned integer constant.
1764 A 5-bit unsigned integer constant.
1767 A 7-bit unsigned integer constant.
1770 A 8-bit unsigned integer constant.
1773 Any const_double value.
1776 @item ARM family---@file{config/arm/constraints.md}
1779 VFP floating-point register
1782 The floating-point constant 0.0
1785 Integer that is valid as an immediate operand in a data processing
1786 instruction. That is, an integer in the range 0 to 255 rotated by a
1790 Integer in the range @minus{}4095 to 4095
1793 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1796 Integer that satisfies constraint @samp{I} when negated (twos complement)
1799 Integer in the range 0 to 32
1802 A memory reference where the exact address is in a single register
1803 (`@samp{m}' is preferable for @code{asm} statements)
1806 An item in the constant pool
1809 A symbol in the text segment of the current file
1812 A memory reference suitable for VFP load/store insns (reg+constant offset)
1815 A memory reference suitable for iWMMXt load/store instructions.
1818 A memory reference suitable for the ARMv4 ldrsb instruction.
1821 @item AVR family---@file{config/avr/constraints.md}
1824 Registers from r0 to r15
1827 Registers from r16 to r23
1830 Registers from r16 to r31
1833 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1836 Pointer register (r26--r31)
1839 Base pointer register (r28--r31)
1842 Stack pointer register (SPH:SPL)
1845 Temporary register r0
1848 Register pair X (r27:r26)
1851 Register pair Y (r29:r28)
1854 Register pair Z (r31:r30)
1857 Constant greater than @minus{}1, less than 64
1860 Constant greater than @minus{}64, less than 1
1869 Constant that fits in 8 bits
1872 Constant integer @minus{}1
1875 Constant integer 8, 16, or 24
1881 A floating point constant 0.0
1884 A memory address based on Y or Z pointer with displacement.
1887 @item Epiphany---@file{config/epiphany/constraints.md}
1890 An unsigned 16-bit constant.
1893 An unsigned 5-bit constant.
1896 A signed 11-bit constant.
1899 A signed 11-bit constant added to @minus{}1.
1900 Can only match when the @option{-m1reg-@var{reg}} option is active.
1903 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1904 being a block of trailing zeroes.
1905 Can only match when the @option{-m1reg-@var{reg}} option is active.
1908 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1909 rest being zeroes. Or to put it another way, one less than a power of two.
1910 Can only match when the @option{-m1reg-@var{reg}} option is active.
1913 Constant for arithmetic/logical operations.
1914 This is like @code{i}, except that for position independent code,
1915 no symbols / expressions needing relocations are allowed.
1918 Symbolic constant for call/jump instruction.
1921 The register class usable in short insns. This is a register class
1922 constraint, and can thus drive register allocation.
1923 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1927 The the register class of registers that can be used to hold a
1928 sibcall call address. I.e., a caller-saved register.
1931 Core control register class.
1934 The register group usable in short insns.
1935 This constraint does not use a register class, so that it only
1936 passively matches suitable registers, and doesn't drive register allocation.
1940 Constant suitable for the addsi3_r pattern. This is a valid offset
1941 For byte, halfword, or word addressing.
1945 Matches the return address if it can be replaced with the link register.
1948 Matches the integer condition code register.
1951 Matches the return address if it is in a stack slot.
1954 Matches control register values to switch fp mode, which are encapsulated in
1955 @code{UNSPEC_FP_MODE}.
1958 @item CR16 Architecture---@file{config/cr16/cr16.h}
1962 Registers from r0 to r14 (registers without stack pointer)
1965 Register from r0 to r11 (all 16-bit registers)
1968 Register from r12 to r15 (all 32-bit registers)
1971 Signed constant that fits in 4 bits
1974 Signed constant that fits in 5 bits
1977 Signed constant that fits in 6 bits
1980 Unsigned constant that fits in 4 bits
1983 Signed constant that fits in 32 bits
1986 Check for 64 bits wide constants for add/sub instructions
1989 Floating point constant that is legal for store immediate
1992 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1998 Floating point register
2001 Shift amount register
2004 Floating point register (deprecated)
2007 Upper floating point register (32-bit), floating point register (64-bit)
2013 Signed 11-bit integer constant
2016 Signed 14-bit integer constant
2019 Integer constant that can be deposited with a @code{zdepi} instruction
2022 Signed 5-bit integer constant
2028 Integer constant that can be loaded with a @code{ldil} instruction
2031 Integer constant whose value plus one is a power of 2
2034 Integer constant that can be used for @code{and} operations in @code{depi}
2035 and @code{extru} instructions
2044 Floating-point constant 0.0
2047 A @code{lo_sum} data-linkage-table memory operand
2050 A memory operand that can be used as the destination operand of an
2051 integer store instruction
2054 A scaled or unscaled indexed memory operand
2057 A memory operand for floating-point loads and stores
2060 A register indirect memory operand
2063 @item picoChip family---@file{picochip.h}
2069 Pointer register. A register which can be used to access memory without
2070 supplying an offset. Any other register can be used to access memory,
2071 but will need a constant offset. In the case of the offset being zero,
2072 it is more efficient to use a pointer register, since this reduces code
2076 A twin register. A register which may be paired with an adjacent
2077 register to create a 32-bit register.
2080 Any absolute memory address (e.g., symbolic constant, symbolic
2084 4-bit signed integer.
2087 4-bit unsigned integer.
2090 8-bit signed integer.
2093 Any constant whose absolute value is no greater than 4-bits.
2096 10-bit signed integer
2099 16-bit signed integer.
2103 @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md}
2106 Address base register
2109 Floating point register (containing 64-bit value)
2112 Floating point register (containing 32-bit value)
2115 Altivec vector register
2118 Any VSX register if the -mvsx option was used or NO_REGS.
2121 VSX vector register to hold vector double data or NO_REGS.
2124 VSX vector register to hold vector float data or NO_REGS.
2127 If @option{-mmfpgpr} was used, a floating point register or NO_REGS.
2130 Floating point register if the LFIWAX instruction is enabled or NO_REGS.
2133 VSX register if direct move instructions are enabled, or NO_REGS.
2136 No register (NO_REGS).
2139 General purpose register if 64-bit instructions are enabled or NO_REGS.
2142 VSX vector register to hold scalar double values or NO_REGS.
2145 VSX vector register to hold 128 bit integer or NO_REGS.
2148 Altivec register to use for float/32-bit int loads/stores or NO_REGS.
2151 Altivec register to use for double loads/stores or NO_REGS.
2154 FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
2157 Floating point register if the STFIWX instruction is enabled or NO_REGS.
2160 VSX vector register to hold scalar float values or NO_REGS.
2163 Floating point register if the LFIWZX instruction is enabled or NO_REGS.
2166 Int constant that is the element number of the 64-bit scalar in a vector.
2169 A memory address that will work with the @code{lq} and @code{stq}
2173 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
2182 @samp{LINK} register
2185 @samp{CR} register (condition register) number 0
2188 @samp{CR} register (condition register)
2191 @samp{XER[CA]} carry bit (part of the XER register)
2194 Signed 16-bit constant
2197 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2198 @code{SImode} constants)
2201 Unsigned 16-bit constant
2204 Signed 16-bit constant shifted left 16 bits
2207 Constant larger than 31
2216 Constant whose negation is a signed 16-bit constant
2219 Floating point constant that can be loaded into a register with one
2220 instruction per word
2223 Integer/Floating point constant that can be loaded into a register using
2228 Normally, @code{m} does not allow addresses that update the base register.
2229 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2230 therefore on PowerPC targets in that case it is only safe
2231 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2232 accesses the operand exactly once. The @code{asm} statement must also
2233 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2234 corresponding load or store instruction. For example:
2237 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2243 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2249 A ``stable'' memory operand; that is, one which does not include any
2250 automodification of the base register. This used to be useful when
2251 @samp{m} allowed automodification of the base register, but as those are now only
2252 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2253 as @samp{m} without @samp{<} and @samp{>}.
2256 Memory operand that is an offset from a register (it is usually better
2257 to use @samp{m} or @samp{es} in @code{asm} statements)
2260 Memory operand that is an indexed or indirect from a register (it is
2261 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2267 Address operand that is an indexed or indirect from a register (@samp{p} is
2268 preferable for @code{asm} statements)
2271 Constant suitable as a 64-bit mask operand
2274 Constant suitable as a 32-bit mask operand
2277 System V Release 4 small data area reference
2280 AND masks that can be performed by two rldic@{l, r@} instructions
2283 Vector constant that does not require memory
2286 Vector constant that is all zeros.
2290 @item Intel 386---@file{config/i386/constraints.md}
2293 Legacy register---the eight integer registers available on all
2294 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2295 @code{si}, @code{di}, @code{bp}, @code{sp}).
2298 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2299 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2302 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2303 @code{c}, and @code{d}.
2307 Any register that can be used as the index in a base+index memory
2308 access: that is, any general register except the stack pointer.
2312 The @code{a} register.
2315 The @code{b} register.
2318 The @code{c} register.
2321 The @code{d} register.
2324 The @code{si} register.
2327 The @code{di} register.
2330 The @code{a} and @code{d} registers. This class is used for instructions
2331 that return double word results in the @code{ax:dx} register pair. Single
2332 word values will be allocated either in @code{ax} or @code{dx}.
2333 For example on i386 the following implements @code{rdtsc}:
2336 unsigned long long rdtsc (void)
2338 unsigned long long tick;
2339 __asm__ __volatile__("rdtsc":"=A"(tick));
2344 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2345 or @code{dx}. You have to use the following variant instead:
2348 unsigned long long rdtsc (void)
2350 unsigned int tickl, tickh;
2351 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2352 return ((unsigned long long)tickh << 32)|tickl;
2358 Any 80387 floating-point (stack) register.
2361 Top of 80387 floating-point stack (@code{%st(0)}).
2364 Second from top of 80387 floating-point stack (@code{%st(1)}).
2373 First SSE register (@code{%xmm0}).
2377 Any SSE register, when SSE2 is enabled.
2380 Any SSE register, when SSE2 and inter-unit moves are enabled.
2383 Any MMX register, when inter-unit moves are enabled.
2387 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2390 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2393 Signed 8-bit integer constant.
2396 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2399 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2402 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2407 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2411 Standard 80387 floating point constant.
2414 Standard SSE floating point constant.
2417 32-bit signed integer constant, or a symbolic reference known
2418 to fit that range (for immediate operands in sign-extending x86-64
2422 32-bit unsigned integer constant, or a symbolic reference known
2423 to fit that range (for immediate operands in zero-extending x86-64
2428 @item Intel IA-64---@file{config/ia64/ia64.h}
2431 General register @code{r0} to @code{r3} for @code{addl} instruction
2437 Predicate register (@samp{c} as in ``conditional'')
2440 Application register residing in M-unit
2443 Application register residing in I-unit
2446 Floating-point register
2449 Memory operand. If used together with @samp{<} or @samp{>},
2450 the operand can have postincrement and postdecrement which
2451 require printing with @samp{%Pn} on IA-64.
2454 Floating-point constant 0.0 or 1.0
2457 14-bit signed integer constant
2460 22-bit signed integer constant
2463 8-bit signed integer constant for logical instructions
2466 8-bit adjusted signed integer constant for compare pseudo-ops
2469 6-bit unsigned integer constant for shift counts
2472 9-bit signed integer constant for load and store postincrements
2478 0 or @minus{}1 for @code{dep} instruction
2481 Non-volatile memory for floating-point loads and stores
2484 Integer constant in the range 1 to 4 for @code{shladd} instruction
2487 Memory operand except postincrement and postdecrement. This is
2488 now roughly the same as @samp{m} when not used together with @samp{<}
2492 @item FRV---@file{config/frv/frv.h}
2495 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2498 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2501 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2502 @code{icc0} to @code{icc3}).
2505 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2508 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2509 Odd registers are excluded not in the class but through the use of a machine
2510 mode larger than 4 bytes.
2513 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2516 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2517 Odd registers are excluded not in the class but through the use of a machine
2518 mode larger than 4 bytes.
2521 Register in the class @code{LR_REG} (the @code{lr} register).
2524 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2525 Register numbers not divisible by 4 are excluded not in the class but through
2526 the use of a machine mode larger than 8 bytes.
2529 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2532 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2535 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2538 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2541 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2542 Register numbers not divisible by 4 are excluded not in the class but through
2543 the use of a machine mode larger than 8 bytes.
2546 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2549 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2552 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2555 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2558 Floating point constant zero
2561 6-bit signed integer constant
2564 10-bit signed integer constant
2567 16-bit signed integer constant
2570 16-bit unsigned integer constant
2573 12-bit signed integer constant that is negative---i.e.@: in the
2574 range of @minus{}2048 to @minus{}1
2580 12-bit signed integer constant that is greater than zero---i.e.@: in the
2585 @item Blackfin family---@file{config/bfin/constraints.md}
2594 A call clobbered P register.
2597 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2598 register. If it is @code{A}, then the register P0.
2601 Even-numbered D register
2604 Odd-numbered D register
2607 Accumulator register.
2610 Even-numbered accumulator register.
2613 Odd-numbered accumulator register.
2625 Registers used for circular buffering, i.e. I, B, or L registers.
2640 Any D, P, B, M, I or L register.
2643 Additional registers typically used only in prologues and epilogues: RETS,
2644 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2647 Any register except accumulators or CC.
2650 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2653 Unsigned 16 bit integer (in the range 0 to 65535)
2656 Signed 7 bit integer (in the range @minus{}64 to 63)
2659 Unsigned 7 bit integer (in the range 0 to 127)
2662 Unsigned 5 bit integer (in the range 0 to 31)
2665 Signed 4 bit integer (in the range @minus{}8 to 7)
2668 Signed 3 bit integer (in the range @minus{}3 to 4)
2671 Unsigned 3 bit integer (in the range 0 to 7)
2674 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2677 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2678 use with either accumulator.
2681 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2682 use only with accumulator A1.
2691 An integer constant with exactly a single bit set.
2694 An integer constant with all bits set except exactly one.
2702 @item M32C---@file{config/m32c/m32c.c}
2707 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2710 Any control register, when they're 16 bits wide (nothing if control
2711 registers are 24 bits wide)
2714 Any control register, when they're 24 bits wide.
2723 $r0 or $r2, or $r2r0 for 32 bit values.
2726 $r1 or $r3, or $r3r1 for 32 bit values.
2729 A register that can hold a 64 bit value.
2732 $r0 or $r1 (registers with addressable high/low bytes)
2741 Address registers when they're 16 bits wide.
2744 Address registers when they're 24 bits wide.
2747 Registers that can hold QI values.
2750 Registers that can be used with displacements ($a0, $a1, $sb).
2753 Registers that can hold 32 bit values.
2756 Registers that can hold 16 bit values.
2759 Registers chat can hold 16 bit values, including all control
2763 $r0 through R1, plus $a0 and $a1.
2769 The memory-based pseudo-registers $mem0 through $mem15.
2772 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2773 bit registers for m32cm, m32c).
2776 Matches multiple registers in a PARALLEL to form a larger register.
2777 Used to match function return values.
2783 @minus{}128 @dots{} 127
2786 @minus{}32768 @dots{} 32767
2792 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2795 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2798 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2801 @minus{}65536 @dots{} @minus{}1
2804 An 8 bit value with exactly one bit set.
2807 A 16 bit value with exactly one bit set.
2810 The common src/dest memory addressing modes.
2813 Memory addressed using $a0 or $a1.
2816 Memory addressed with immediate addresses.
2819 Memory addressed using the stack pointer ($sp).
2822 Memory addressed using the frame base register ($fb).
2825 Memory addressed using the small base register ($sb).
2831 @item MeP---@file{config/mep/constraints.md}
2841 Any control register.
2844 Either the $hi or the $lo register.
2847 Coprocessor registers that can be directly loaded ($c0-$c15).
2850 Coprocessor registers that can be moved to each other.
2853 Coprocessor registers that can be moved to core registers.
2865 Registers which can be used in $tp-relative addressing.
2871 The coprocessor registers.
2874 The coprocessor control registers.
2880 User-defined register set A.
2883 User-defined register set B.
2886 User-defined register set C.
2889 User-defined register set D.
2892 Offsets for $gp-rel addressing.
2895 Constants that can be used directly with boolean insns.
2898 Constants that can be moved directly to registers.
2901 Small constants that can be added to registers.
2907 Small constants that can be compared to registers.
2910 Constants that can be loaded into the top half of registers.
2913 Signed 8-bit immediates.
2916 Symbols encoded for $tp-rel or $gp-rel addressing.
2919 Non-constant addresses for loading/saving coprocessor registers.
2922 The top half of a symbol's value.
2925 A register indirect address without offset.
2928 Symbolic references to the control bus.
2932 @item MicroBlaze---@file{config/microblaze/constraints.md}
2935 A general register (@code{r0} to @code{r31}).
2938 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2942 @item MIPS---@file{config/mips/constraints.md}
2945 An address register. This is equivalent to @code{r} unless
2946 generating MIPS16 code.
2949 A floating-point register (if available).
2952 Formerly the @code{hi} register. This constraint is no longer supported.
2955 The @code{lo} register. Use this register to store values that are
2956 no bigger than a word.
2959 The concatenated @code{hi} and @code{lo} registers. Use this register
2960 to store doubleword values.
2963 A register suitable for use in an indirect jump. This will always be
2964 @code{$25} for @option{-mabicalls}.
2967 Register @code{$3}. Do not use this constraint in new code;
2968 it is retained only for compatibility with glibc.
2971 Equivalent to @code{r}; retained for backwards compatibility.
2974 A floating-point condition code register.
2977 A signed 16-bit constant (for arithmetic instructions).
2983 An unsigned 16-bit constant (for logic instructions).
2986 A signed 32-bit constant in which the lower 16 bits are zero.
2987 Such constants can be loaded using @code{lui}.
2990 A constant that cannot be loaded using @code{lui}, @code{addiu}
2994 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2997 A signed 15-bit constant.
3000 A constant in the range 1 to 65535 (inclusive).
3003 Floating-point zero.
3006 An address that can be used in a non-macro load or store.
3009 When compiling microMIPS code, this constraint matches a memory operand
3010 whose address is formed from a base register and a 12-bit offset. These
3011 operands can be used for microMIPS instructions such as @code{ll} and
3012 @code{sc}. When not compiling for microMIPS code, @code{ZC} is
3013 equivalent to @code{R}.
3016 When compiling microMIPS code, this constraint matches an address operand
3017 that is formed from a base register and a 12-bit offset. These operands
3018 can be used for microMIPS instructions such as @code{prefetch}. When
3019 not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}.
3022 @item Motorola 680x0---@file{config/m68k/constraints.md}
3031 68881 floating-point register, if available
3034 Integer in the range 1 to 8
3037 16-bit signed number
3040 Signed number whose magnitude is greater than 0x80
3043 Integer in the range @minus{}8 to @minus{}1
3046 Signed number whose magnitude is greater than 0x100
3049 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
3052 16 (for rotate using swap)
3055 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
3058 Numbers that mov3q can handle
3061 Floating point constant that is not a 68881 constant
3064 Operands that satisfy 'm' when -mpcrel is in effect
3067 Operands that satisfy 's' when -mpcrel is not in effect
3070 Address register indirect addressing mode
3073 Register offset addressing
3088 Range of signed numbers that don't fit in 16 bits
3091 Integers valid for mvq
3094 Integers valid for a moveq followed by a swap
3097 Integers valid for mvz
3100 Integers valid for mvs
3106 Non-register operands allowed in clr
3110 @item Moxie---@file{config/moxie/constraints.md}
3119 A register indirect memory operand
3122 A constant in the range of 0 to 255.
3125 A constant in the range of 0 to @minus{}255.
3129 @item MSP430--@file{config/msp430/constraints.md}
3142 Integer constant -1^20..1^19.
3145 Integer constant 1-4.
3148 Memory references which do not require an extended MOVX instruction.
3151 Memory reference, labels only.
3154 Memory reference, stack only.
3158 @item NDS32---@file{config/nds32/constraints.md}
3161 LOW register class $r0 to $r7 constraint for V3/V3M ISA.
3163 LOW register class $r0 to $r7.
3165 MIDDLE register class $r0 to $r11, $r16 to $r19.
3167 HIGH register class $r12 to $r14, $r20 to $r31.
3169 Temporary assist register $ta (i.e.@: $r15).
3173 Unsigned immediate 3-bit value.
3175 Negative immediate 3-bit value in the range of @minus{}7--0.
3177 Unsigned immediate 4-bit value.
3179 Signed immediate 5-bit value.
3181 Unsigned immediate 5-bit value.
3183 Negative immediate 5-bit value in the range of @minus{}31--0.
3185 Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.
3187 Unsigned immediate 6-bit value constraint for addri36.sp instruction.
3189 Unsigned immediate 8-bit value.
3191 Unsigned immediate 9-bit value.
3193 Signed immediate 10-bit value.
3195 Signed immediate 11-bit value.
3197 Signed immediate 15-bit value.
3199 Unsigned immediate 15-bit value.
3201 A constant which is not in the range of imm15u but ok for bclr instruction.
3203 A constant which is not in the range of imm15u but ok for bset instruction.
3205 A constant which is not in the range of imm15u but ok for btgl instruction.
3207 A constant whose compliment value is in the range of imm15u
3208 and ok for bitci instruction.
3210 Signed immediate 16-bit value.
3212 Signed immediate 17-bit value.
3214 Signed immediate 19-bit value.
3216 Signed immediate 20-bit value.
3218 The immediate value that can be simply set high 20-bit.
3220 The immediate value 0xff.
3222 The immediate value 0xffff.
3224 The immediate value 0x01.
3226 The immediate value 0x7ff.
3228 The immediate value with power of 2.
3230 The immediate value with power of 2 minus 1.
3232 Memory constraint for 333 format.
3234 Memory constraint for 45 format.
3236 Memory constraint for 37 format.
3239 @item Nios II family---@file{config/nios2/constraints.md}
3243 Integer that is valid as an immediate operand in an
3244 instruction taking a signed 16-bit number. Range
3245 @minus{}32768 to 32767.
3248 Integer that is valid as an immediate operand in an
3249 instruction taking an unsigned 16-bit number. Range
3253 Integer that is valid as an immediate operand in an
3254 instruction taking only the upper 16-bits of a
3255 32-bit number. Range 32-bit numbers with the lower
3259 Integer that is valid as an immediate operand for a
3260 shift instruction. Range 0 to 31.
3263 Integer that is valid as an immediate operand for
3264 only the value 0. Can be used in conjunction with
3265 the format modifier @code{z} to use @code{r0}
3266 instead of @code{0} in the assembly output.
3269 Integer that is valid as an immediate operand for
3270 a custom instruction opcode. Range 0 to 255.
3273 Matches immediates which are addresses in the small
3274 data section and therefore can be added to @code{gp}
3275 as a 16-bit immediate to re-create their 32-bit value.
3279 A @code{const} wrapped @code{UNSPEC} expression,
3280 representing a supported PIC or TLS relocation.
3285 @item PDP-11---@file{config/pdp11/constraints.md}
3288 Floating point registers AC0 through AC3. These can be loaded from/to
3289 memory with a single instruction.
3292 Odd numbered general registers (R1, R3, R5). These are used for
3293 16-bit multiply operations.
3296 Any of the floating point registers (AC0 through AC5).
3299 Floating point constant 0.
3302 An integer constant that fits in 16 bits.
3305 An integer constant whose low order 16 bits are zero.
3308 An integer constant that does not meet the constraints for codes
3309 @samp{I} or @samp{J}.
3312 The integer constant 1.
3315 The integer constant @minus{}1.
3318 The integer constant 0.
3321 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
3322 amounts are handled as multiple single-bit shifts rather than a single
3323 variable-length shift.
3326 A memory reference which requires an additional word (address or
3327 offset) after the opcode.
3330 A memory reference that is encoded within the opcode.
3334 @item RL78---@file{config/rl78/constraints.md}
3338 An integer constant in the range 1 @dots{} 7.
3340 An integer constant in the range 0 @dots{} 255.
3342 An integer constant in the range @minus{}255 @dots{} 0
3344 The integer constant 1.
3346 The integer constant -1.
3348 The integer constant 0.
3350 The integer constant 2.
3352 The integer constant -2.
3354 An integer constant in the range 1 @dots{} 15.
3356 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3358 The synthetic compare types--gt, lt, ge, and le.
3360 A memory reference with an absolute address.
3362 A memory reference using @code{BC} as a base register, with an optional offset.
3364 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3366 A memory reference using any 16-bit register pair for the address, for calls.
3368 A memory reference using @code{DE} as a base register, with an optional offset.
3370 A memory reference using @code{DE} as a base register, without any offset.
3372 Any memory reference to an address in the far address space.
3374 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3376 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3378 A memory reference using @code{HL} as a base register, without any offset.
3380 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3382 Any memory reference to an address in the near address space.
3384 The @code{AX} register.
3386 The @code{BC} register.
3388 The @code{DE} register.
3390 @code{A} through @code{L} registers.
3392 The @code{SP} register.
3394 The @code{HL} register.
3396 The 16-bit @code{R8} register.
3398 The 16-bit @code{R10} register.
3400 The registers reserved for interrupts (@code{R24} to @code{R31}).
3402 The @code{A} register.
3404 The @code{B} register.
3406 The @code{C} register.
3408 The @code{D} register.
3410 The @code{E} register.
3412 The @code{H} register.
3414 The @code{L} register.
3416 The virtual registers.
3418 The @code{PSW} register.
3420 The @code{X} register.
3424 @item RX---@file{config/rx/constraints.md}
3427 An address which does not involve register indirect addressing or
3428 pre/post increment/decrement addressing.
3434 A constant in the range @minus{}256 to 255, inclusive.
3437 A constant in the range @minus{}128 to 127, inclusive.
3440 A constant in the range @minus{}32768 to 32767, inclusive.
3443 A constant in the range @minus{}8388608 to 8388607, inclusive.
3446 A constant in the range 0 to 15, inclusive.
3451 @item SPARC---@file{config/sparc/sparc.h}
3454 Floating-point register on the SPARC-V8 architecture and
3455 lower floating-point register on the SPARC-V9 architecture.
3458 Floating-point register. It is equivalent to @samp{f} on the
3459 SPARC-V8 architecture and contains both lower and upper
3460 floating-point registers on the SPARC-V9 architecture.
3463 Floating-point condition code register.
3466 Lower floating-point register. It is only valid on the SPARC-V9
3467 architecture when the Visual Instruction Set is available.
3470 Floating-point register. It is only valid on the SPARC-V9 architecture
3471 when the Visual Instruction Set is available.
3474 64-bit global or out register for the SPARC-V8+ architecture.
3477 The constant all-ones, for floating-point.
3480 Signed 5-bit constant
3486 Signed 13-bit constant
3492 32-bit constant with the low 12 bits clear (a constant that can be
3493 loaded with the @code{sethi} instruction)
3496 A constant in the range supported by @code{movcc} instructions (11-bit
3500 A constant in the range supported by @code{movrcc} instructions (10-bit
3504 Same as @samp{K}, except that it verifies that bits that are not in the
3505 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3506 modes wider than @code{SImode}
3515 Signed 13-bit constant, sign-extended to 32 or 64 bits
3521 Floating-point constant whose integral representation can
3522 be moved into an integer register using a single sethi
3526 Floating-point constant whose integral representation can
3527 be moved into an integer register using a single mov
3531 Floating-point constant whose integral representation can
3532 be moved into an integer register using a high/lo_sum
3533 instruction sequence
3536 Memory address aligned to an 8-byte boundary
3542 Memory address for @samp{e} constraint registers
3545 Memory address with only a base register
3552 @item SPU---@file{config/spu/spu.h}
3555 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3558 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3561 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3564 An immediate which can be loaded with @code{fsmbi}.
3567 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3570 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3573 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3576 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3579 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3582 An unsigned 7-bit constant for conversion/nop/channel instructions.
3585 A signed 10-bit constant for most arithmetic instructions.
3588 A signed 16 bit immediate for @code{stop}.
3591 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3594 An unsigned 7-bit constant whose 3 least significant bits are 0.
3597 An unsigned 3-bit constant for 16-byte rotates and shifts
3600 Call operand, reg, for indirect calls
3603 Call operand, symbol, for relative calls.
3606 Call operand, const_int, for absolute calls.
3609 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3612 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3615 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3618 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3622 @item S/390 and zSeries---@file{config/s390/s390.h}
3625 Address register (general purpose register except r0)
3628 Condition code register
3631 Data register (arbitrary general purpose register)
3634 Floating-point register
3637 Unsigned 8-bit constant (0--255)
3640 Unsigned 12-bit constant (0--4095)
3643 Signed 16-bit constant (@minus{}32768--32767)
3646 Value appropriate as displacement.
3649 for short displacement
3650 @item (@minus{}524288..524287)
3651 for long displacement
3655 Constant integer with a value of 0x7fffffff.
3658 Multiple letter constraint followed by 4 parameter letters.
3661 number of the part counting from most to least significant
3665 mode of the containing operand
3667 value of the other parts (F---all bits set)
3669 The constraint matches if the specified part of a constant
3670 has a value different from its other parts.
3673 Memory reference without index register and with short displacement.
3676 Memory reference with index register and short displacement.
3679 Memory reference without index register but with long displacement.
3682 Memory reference with index register and long displacement.
3685 Pointer with short displacement.
3688 Pointer with long displacement.
3691 Shift count operand.
3695 @item Score family---@file{config/score/score.h}
3698 Registers from r0 to r32.
3701 Registers from r0 to r16.
3704 r8---r11 or r22---r27 registers.
3725 cnt + lcb + scb register.
3728 cr0---cr15 register.
3740 cp1 + cp2 + cp3 registers.
3743 High 16-bit constant (32-bit constant with 16 LSBs zero).
3746 Unsigned 5 bit integer (in the range 0 to 31).
3749 Unsigned 16 bit integer (in the range 0 to 65535).
3752 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3755 Unsigned 14 bit integer (in the range 0 to 16383).
3758 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3764 @item Xstormy16---@file{config/stormy16/stormy16.h}
3779 Registers r0 through r7.
3782 Registers r0 and r1.
3788 Registers r8 and r9.
3791 A constant between 0 and 3 inclusive.
3794 A constant that has exactly one bit set.
3797 A constant that has exactly one bit clear.
3800 A constant between 0 and 255 inclusive.
3803 A constant between @minus{}255 and 0 inclusive.
3806 A constant between @minus{}3 and 0 inclusive.
3809 A constant between 1 and 4 inclusive.
3812 A constant between @minus{}4 and @minus{}1 inclusive.
3815 A memory reference that is a stack push.
3818 A memory reference that is a stack pop.
3821 A memory reference that refers to a constant address of known value.
3824 The register indicated by Rx (not implemented yet).
3827 A constant that is not between 2 and 15 inclusive.
3834 @item TI C6X family---@file{config/c6x/constraints.md}
3837 Register file A (A0--A31).
3840 Register file B (B0--B31).
3843 Predicate registers in register file A (A0--A2 on C64X and
3844 higher, A1 and A2 otherwise).
3847 Predicate registers in register file B (B0--B2).
3850 A call-used register in register file B (B0--B9, B16--B31).
3853 Register file A, excluding predicate registers (A3--A31,
3854 plus A0 if not C64X or higher).
3857 Register file B, excluding predicate registers (B3--B31).
3860 Integer constant in the range 0 @dots{} 15.
3863 Integer constant in the range 0 @dots{} 31.
3866 Integer constant in the range @minus{}31 @dots{} 0.
3869 Integer constant in the range @minus{}16 @dots{} 15.
3872 Integer constant that can be the operand of an ADDA or a SUBA insn.
3875 Integer constant in the range 0 @dots{} 65535.
3878 Integer constant in the range @minus{}32768 @dots{} 32767.
3881 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3884 Integer constant that is a valid mask for the clr instruction.
3887 Integer constant that is a valid mask for the set instruction.
3890 Memory location with A base register.
3893 Memory location with B base register.
3897 On C64x+ targets, a GP-relative small data reference.
3900 Any kind of @code{SYMBOL_REF}, for use in a call address.
3903 Any kind of immediate operand, unless it matches the S0 constraint.
3906 Memory location with B base register, but not using a long offset.
3909 A memory operand with an address that can't be used in an unaligned access.
3913 Register B14 (aka DP).
3917 @item TILE-Gx---@file{config/tilegx/constraints.md}
3930 Each of these represents a register constraint for an individual
3931 register, from r0 to r10.
3934 Signed 8-bit integer constant.
3937 Signed 16-bit integer constant.
3940 Unsigned 16-bit integer constant.
3943 Integer constant that fits in one signed byte when incremented by one
3944 (@minus{}129 @dots{} 126).
3947 Memory operand. If used together with @samp{<} or @samp{>}, the
3948 operand can have postincrement which requires printing with @samp{%In}
3949 and @samp{%in} on TILE-Gx. For example:
3952 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3956 A bit mask suitable for the BFINS instruction.
3959 Integer constant that is a byte tiled out eight times.
3962 The integer zero constant.
3965 Integer constant that is a sign-extended byte tiled out as four shorts.
3968 Integer constant that fits in one signed byte when incremented
3969 (@minus{}129 @dots{} 126), but excluding -1.
3972 Integer constant that has all 1 bits consecutive and starting at bit 0.
3975 A 16-bit fragment of a got, tls, or pc-relative reference.
3978 Memory operand except postincrement. This is roughly the same as
3979 @samp{m} when not used together with @samp{<} or @samp{>}.
3982 An 8-element vector constant with identical elements.
3985 A 4-element vector constant with identical elements.
3988 The integer constant 0xffffffff.
3991 The integer constant 0xffffffff00000000.
3995 @item TILEPro---@file{config/tilepro/constraints.md}
4008 Each of these represents a register constraint for an individual
4009 register, from r0 to r10.
4012 Signed 8-bit integer constant.
4015 Signed 16-bit integer constant.
4018 Nonzero integer constant with low 16 bits zero.
4021 Integer constant that fits in one signed byte when incremented by one
4022 (@minus{}129 @dots{} 126).
4025 Memory operand. If used together with @samp{<} or @samp{>}, the
4026 operand can have postincrement which requires printing with @samp{%In}
4027 and @samp{%in} on TILEPro. For example:
4030 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
4034 A bit mask suitable for the MM instruction.
4037 Integer constant that is a byte tiled out four times.
4040 The integer zero constant.
4043 Integer constant that is a sign-extended byte tiled out as two shorts.
4046 Integer constant that fits in one signed byte when incremented
4047 (@minus{}129 @dots{} 126), but excluding -1.
4050 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
4054 Memory operand except postincrement. This is roughly the same as
4055 @samp{m} when not used together with @samp{<} or @samp{>}.
4058 A 4-element vector constant with identical elements.
4061 A 2-element vector constant with identical elements.
4065 @item Xtensa---@file{config/xtensa/constraints.md}
4068 General-purpose 32-bit register
4071 One-bit boolean register
4074 MAC16 40-bit accumulator register
4077 Signed 12-bit integer constant, for use in MOVI instructions
4080 Signed 8-bit integer constant, for use in ADDI instructions
4083 Integer constant valid for BccI instructions
4086 Unsigned constant valid for BccUI instructions
4093 @node Disable Insn Alternatives
4094 @subsection Disable insn alternatives using the @code{enabled} attribute
4097 The @code{enabled} insn attribute may be used to disable certain insn
4098 alternatives for machine-specific reasons. This is useful when adding
4099 new instructions to an existing pattern which are only available for
4100 certain cpu architecture levels as specified with the @code{-march=}
4103 If an insn alternative is disabled, then it will never be used. The
4104 compiler treats the constraints for the disabled alternative as
4107 In order to make use of the @code{enabled} attribute a back end has to add
4108 in the machine description files:
4112 A definition of the @code{enabled} insn attribute. The attribute is
4113 defined as usual using the @code{define_attr} command. This
4114 definition should be based on other insn attributes and/or target flags.
4115 The @code{enabled} attribute is a numeric attribute and should evaluate to
4116 @code{(const_int 1)} for an enabled alternative and to
4117 @code{(const_int 0)} otherwise.
4119 A definition of another insn attribute used to describe for what
4120 reason an insn alternative might be available or
4121 not. E.g. @code{cpu_facility} as in the example below.
4123 An assignment for the second attribute to each insn definition
4124 combining instructions which are not all available under the same
4125 circumstances. (Note: It obviously only makes sense for definitions
4126 with more than one alternative. Otherwise the insn pattern should be
4127 disabled or enabled using the insn condition.)
4130 E.g. the following two patterns could easily be merged using the @code{enabled}
4135 (define_insn "*movdi_old"
4136 [(set (match_operand:DI 0 "register_operand" "=d")
4137 (match_operand:DI 1 "register_operand" " d"))]
4141 (define_insn "*movdi_new"
4142 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4143 (match_operand:DI 1 "register_operand" " d,d,f"))]
4156 (define_insn "*movdi_combined"
4157 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
4158 (match_operand:DI 1 "register_operand" " d,d,f"))]
4164 [(set_attr "cpu_facility" "*,new,new")])
4168 with the @code{enabled} attribute defined like this:
4172 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
4174 (define_attr "enabled" ""
4175 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
4176 (and (eq_attr "cpu_facility" "new")
4177 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
4186 @node Define Constraints
4187 @subsection Defining Machine-Specific Constraints
4188 @cindex defining constraints
4189 @cindex constraints, defining
4191 Machine-specific constraints fall into two categories: register and
4192 non-register constraints. Within the latter category, constraints
4193 which allow subsets of all possible memory or address operands should
4194 be specially marked, to give @code{reload} more information.
4196 Machine-specific constraints can be given names of arbitrary length,
4197 but they must be entirely composed of letters, digits, underscores
4198 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
4199 must begin with a letter or underscore.
4201 In order to avoid ambiguity in operand constraint strings, no
4202 constraint can have a name that begins with any other constraint's
4203 name. For example, if @code{x} is defined as a constraint name,
4204 @code{xy} may not be, and vice versa. As a consequence of this rule,
4205 no constraint may begin with one of the generic constraint letters:
4206 @samp{E F V X g i m n o p r s}.
4208 Register constraints correspond directly to register classes.
4209 @xref{Register Classes}. There is thus not much flexibility in their
4212 @deffn {MD Expression} define_register_constraint name regclass docstring
4213 All three arguments are string constants.
4214 @var{name} is the name of the constraint, as it will appear in
4215 @code{match_operand} expressions. If @var{name} is a multi-letter
4216 constraint its length shall be the same for all constraints starting
4217 with the same letter. @var{regclass} can be either the
4218 name of the corresponding register class (@pxref{Register Classes}),
4219 or a C expression which evaluates to the appropriate register class.
4220 If it is an expression, it must have no side effects, and it cannot
4221 look at the operand. The usual use of expressions is to map some
4222 register constraints to @code{NO_REGS} when the register class
4223 is not available on a given subarchitecture.
4225 @var{docstring} is a sentence documenting the meaning of the
4226 constraint. Docstrings are explained further below.
4229 Non-register constraints are more like predicates: the constraint
4230 definition gives a Boolean expression which indicates whether the
4233 @deffn {MD Expression} define_constraint name docstring exp
4234 The @var{name} and @var{docstring} arguments are the same as for
4235 @code{define_register_constraint}, but note that the docstring comes
4236 immediately after the name for these expressions. @var{exp} is an RTL
4237 expression, obeying the same rules as the RTL expressions in predicate
4238 definitions. @xref{Defining Predicates}, for details. If it
4239 evaluates true, the constraint matches; if it evaluates false, it
4240 doesn't. Constraint expressions should indicate which RTL codes they
4241 might match, just like predicate expressions.
4243 @code{match_test} C expressions have access to the
4244 following variables:
4248 The RTL object defining the operand.
4250 The machine mode of @var{op}.
4252 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
4254 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
4255 @code{const_double}.
4257 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
4258 @code{const_double}.
4260 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
4261 @code{const_double}.
4264 The @var{*val} variables should only be used once another piece of the
4265 expression has verified that @var{op} is the appropriate kind of RTL
4269 Most non-register constraints should be defined with
4270 @code{define_constraint}. The remaining two definition expressions
4271 are only appropriate for constraints that should be handled specially
4272 by @code{reload} if they fail to match.
4274 @deffn {MD Expression} define_memory_constraint name docstring exp
4275 Use this expression for constraints that match a subset of all memory
4276 operands: that is, @code{reload} can make them match by converting the
4277 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
4278 base register (from the register class specified by
4279 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
4281 For example, on the S/390, some instructions do not accept arbitrary
4282 memory references, but only those that do not make use of an index
4283 register. The constraint letter @samp{Q} is defined to represent a
4284 memory address of this type. If @samp{Q} is defined with
4285 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
4286 memory operand, because @code{reload} knows it can simply copy the
4287 memory address into a base register if required. This is analogous to
4288 the way an @samp{o} constraint can handle any memory operand.
4290 The syntax and semantics are otherwise identical to
4291 @code{define_constraint}.
4294 @deffn {MD Expression} define_address_constraint name docstring exp
4295 Use this expression for constraints that match a subset of all address
4296 operands: that is, @code{reload} can make the constraint match by
4297 converting the operand to the form @samp{@w{(reg @var{X})}}, again
4298 with @var{X} a base register.
4300 Constraints defined with @code{define_address_constraint} can only be
4301 used with the @code{address_operand} predicate, or machine-specific
4302 predicates that work the same way. They are treated analogously to
4303 the generic @samp{p} constraint.
4305 The syntax and semantics are otherwise identical to
4306 @code{define_constraint}.
4309 For historical reasons, names beginning with the letters @samp{G H}
4310 are reserved for constraints that match only @code{const_double}s, and
4311 names beginning with the letters @samp{I J K L M N O P} are reserved
4312 for constraints that match only @code{const_int}s. This may change in
4313 the future. For the time being, constraints with these names must be
4314 written in a stylized form, so that @code{genpreds} can tell you did
4319 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
4321 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
4322 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
4325 @c the semicolons line up in the formatted manual
4327 It is fine to use names beginning with other letters for constraints
4328 that match @code{const_double}s or @code{const_int}s.
4330 Each docstring in a constraint definition should be one or more complete
4331 sentences, marked up in Texinfo format. @emph{They are currently unused.}
4332 In the future they will be copied into the GCC manual, in @ref{Machine
4333 Constraints}, replacing the hand-maintained tables currently found in
4334 that section. Also, in the future the compiler may use this to give
4335 more helpful diagnostics when poor choice of @code{asm} constraints
4336 causes a reload failure.
4338 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4339 beginning of a docstring, then (in the future) it will appear only in
4340 the internals manual's version of the machine-specific constraint tables.
4341 Use this for constraints that should not appear in @code{asm} statements.
4343 @node C Constraint Interface
4344 @subsection Testing constraints from C
4345 @cindex testing constraints
4346 @cindex constraints, testing
4348 It is occasionally useful to test a constraint from C code rather than
4349 implicitly via the constraint string in a @code{match_operand}. The
4350 generated file @file{tm_p.h} declares a few interfaces for working
4351 with machine-specific constraints. None of these interfaces work with
4352 the generic constraints described in @ref{Simple Constraints}. This
4353 may change in the future.
4355 @strong{Warning:} @file{tm_p.h} may declare other functions that
4356 operate on constraints, besides the ones documented here. Do not use
4357 those functions from machine-dependent code. They exist to implement
4358 the old constraint interface that machine-independent components of
4359 the compiler still expect. They will change or disappear in the
4362 Some valid constraint names are not valid C identifiers, so there is a
4363 mangling scheme for referring to them from C@. Constraint names that
4364 do not contain angle brackets or underscores are left unchanged.
4365 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4366 each @samp{>} with @samp{_g}. Here are some examples:
4368 @c the @c's prevent double blank lines in the printed manual.
4370 @multitable {Original} {Mangled}
4371 @item @strong{Original} @tab @strong{Mangled} @c
4372 @item @code{x} @tab @code{x} @c
4373 @item @code{P42x} @tab @code{P42x} @c
4374 @item @code{P4_x} @tab @code{P4__x} @c
4375 @item @code{P4>x} @tab @code{P4_gx} @c
4376 @item @code{P4>>} @tab @code{P4_g_g} @c
4377 @item @code{P4_g>} @tab @code{P4__g_g} @c
4381 Throughout this section, the variable @var{c} is either a constraint
4382 in the abstract sense, or a constant from @code{enum constraint_num};
4383 the variable @var{m} is a mangled constraint name (usually as part of
4384 a larger identifier).
4386 @deftp Enum constraint_num
4387 For each machine-specific constraint, there is a corresponding
4388 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4389 constraint. Functions that take an @code{enum constraint_num} as an
4390 argument expect one of these constants.
4392 Machine-independent constraints do not have associated constants.
4393 This may change in the future.
4396 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4397 For each machine-specific, non-register constraint @var{m}, there is
4398 one of these functions; it returns @code{true} if @var{exp} satisfies the
4399 constraint. These functions are only visible if @file{rtl.h} was included
4400 before @file{tm_p.h}.
4403 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4404 Like the @code{satisfies_constraint_@var{m}} functions, but the
4405 constraint to test is given as an argument, @var{c}. If @var{c}
4406 specifies a register constraint, this function will always return
4410 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
4411 Returns the register class associated with @var{c}. If @var{c} is not
4412 a register constraint, or those registers are not available for the
4413 currently selected subtarget, returns @code{NO_REGS}.
4416 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4417 peephole optimizations (@pxref{Peephole Definitions}), operand
4418 constraint strings are ignored, so if there are relevant constraints,
4419 they must be tested in the C condition. In the example, the
4420 optimization is applied if operand 2 does @emph{not} satisfy the
4421 @samp{K} constraint. (This is a simplified version of a peephole
4422 definition from the i386 machine description.)
4426 [(match_scratch:SI 3 "r")
4427 (set (match_operand:SI 0 "register_operand" "")
4428 (mult:SI (match_operand:SI 1 "memory_operand" "")
4429 (match_operand:SI 2 "immediate_operand" "")))]
4431 "!satisfies_constraint_K (operands[2])"
4433 [(set (match_dup 3) (match_dup 1))
4434 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4439 @node Standard Names
4440 @section Standard Pattern Names For Generation
4441 @cindex standard pattern names
4442 @cindex pattern names
4443 @cindex names, pattern
4445 Here is a table of the instruction names that are meaningful in the RTL
4446 generation pass of the compiler. Giving one of these names to an
4447 instruction pattern tells the RTL generation pass that it can use the
4448 pattern to accomplish a certain task.
4451 @cindex @code{mov@var{m}} instruction pattern
4452 @item @samp{mov@var{m}}
4453 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4454 This instruction pattern moves data with that machine mode from operand
4455 1 to operand 0. For example, @samp{movsi} moves full-word data.
4457 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4458 own mode is wider than @var{m}, the effect of this instruction is
4459 to store the specified value in the part of the register that corresponds
4460 to mode @var{m}. Bits outside of @var{m}, but which are within the
4461 same target word as the @code{subreg} are undefined. Bits which are
4462 outside the target word are left unchanged.
4464 This class of patterns is special in several ways. First of all, each
4465 of these names up to and including full word size @emph{must} be defined,
4466 because there is no other way to copy a datum from one place to another.
4467 If there are patterns accepting operands in larger modes,
4468 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4470 Second, these patterns are not used solely in the RTL generation pass.
4471 Even the reload pass can generate move insns to copy values from stack
4472 slots into temporary registers. When it does so, one of the operands is
4473 a hard register and the other is an operand that can need to be reloaded
4477 Therefore, when given such a pair of operands, the pattern must generate
4478 RTL which needs no reloading and needs no temporary registers---no
4479 registers other than the operands. For example, if you support the
4480 pattern with a @code{define_expand}, then in such a case the
4481 @code{define_expand} mustn't call @code{force_reg} or any other such
4482 function which might generate new pseudo registers.
4484 This requirement exists even for subword modes on a RISC machine where
4485 fetching those modes from memory normally requires several insns and
4486 some temporary registers.
4488 @findex change_address
4489 During reload a memory reference with an invalid address may be passed
4490 as an operand. Such an address will be replaced with a valid address
4491 later in the reload pass. In this case, nothing may be done with the
4492 address except to use it as it stands. If it is copied, it will not be
4493 replaced with a valid address. No attempt should be made to make such
4494 an address into a valid address and no routine (such as
4495 @code{change_address}) that will do so may be called. Note that
4496 @code{general_operand} will fail when applied to such an address.
4498 @findex reload_in_progress
4499 The global variable @code{reload_in_progress} (which must be explicitly
4500 declared if required) can be used to determine whether such special
4501 handling is required.
4503 The variety of operands that have reloads depends on the rest of the
4504 machine description, but typically on a RISC machine these can only be
4505 pseudo registers that did not get hard registers, while on other
4506 machines explicit memory references will get optional reloads.
4508 If a scratch register is required to move an object to or from memory,
4509 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4511 If there are cases which need scratch registers during or after reload,
4512 you must provide an appropriate secondary_reload target hook.
4514 @findex can_create_pseudo_p
4515 The macro @code{can_create_pseudo_p} can be used to determine if it
4516 is unsafe to create new pseudo registers. If this variable is nonzero, then
4517 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4519 The constraints on a @samp{mov@var{m}} must permit moving any hard
4520 register to any other hard register provided that
4521 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4522 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4525 It is obligatory to support floating point @samp{mov@var{m}}
4526 instructions into and out of any registers that can hold fixed point
4527 values, because unions and structures (which have modes @code{SImode} or
4528 @code{DImode}) can be in those registers and they may have floating
4531 There may also be a need to support fixed point @samp{mov@var{m}}
4532 instructions in and out of floating point registers. Unfortunately, I
4533 have forgotten why this was so, and I don't know whether it is still
4534 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4535 floating point registers, then the constraints of the fixed point
4536 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4537 reload into a floating point register.
4539 @cindex @code{reload_in} instruction pattern
4540 @cindex @code{reload_out} instruction pattern
4541 @item @samp{reload_in@var{m}}
4542 @itemx @samp{reload_out@var{m}}
4543 These named patterns have been obsoleted by the target hook
4544 @code{secondary_reload}.
4546 Like @samp{mov@var{m}}, but used when a scratch register is required to
4547 move between operand 0 and operand 1. Operand 2 describes the scratch
4548 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4549 macro in @pxref{Register Classes}.
4551 There are special restrictions on the form of the @code{match_operand}s
4552 used in these patterns. First, only the predicate for the reload
4553 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4554 the predicates for operand 0 or 2. Second, there may be only one
4555 alternative in the constraints. Third, only a single register class
4556 letter may be used for the constraint; subsequent constraint letters
4557 are ignored. As a special exception, an empty constraint string
4558 matches the @code{ALL_REGS} register class. This may relieve ports
4559 of the burden of defining an @code{ALL_REGS} constraint letter just
4562 @cindex @code{movstrict@var{m}} instruction pattern
4563 @item @samp{movstrict@var{m}}
4564 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4565 with mode @var{m} of a register whose natural mode is wider,
4566 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4567 any of the register except the part which belongs to mode @var{m}.
4569 @cindex @code{movmisalign@var{m}} instruction pattern
4570 @item @samp{movmisalign@var{m}}
4571 This variant of a move pattern is designed to load or store a value
4572 from a memory address that is not naturally aligned for its mode.
4573 For a store, the memory will be in operand 0; for a load, the memory
4574 will be in operand 1. The other operand is guaranteed not to be a
4575 memory, so that it's easy to tell whether this is a load or store.
4577 This pattern is used by the autovectorizer, and when expanding a
4578 @code{MISALIGNED_INDIRECT_REF} expression.
4580 @cindex @code{load_multiple} instruction pattern
4581 @item @samp{load_multiple}
4582 Load several consecutive memory locations into consecutive registers.
4583 Operand 0 is the first of the consecutive registers, operand 1
4584 is the first memory location, and operand 2 is a constant: the
4585 number of consecutive registers.
4587 Define this only if the target machine really has such an instruction;
4588 do not define this if the most efficient way of loading consecutive
4589 registers from memory is to do them one at a time.
4591 On some machines, there are restrictions as to which consecutive
4592 registers can be stored into memory, such as particular starting or
4593 ending register numbers or only a range of valid counts. For those
4594 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4595 and make the pattern fail if the restrictions are not met.
4597 Write the generated insn as a @code{parallel} with elements being a
4598 @code{set} of one register from the appropriate memory location (you may
4599 also need @code{use} or @code{clobber} elements). Use a
4600 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4601 @file{rs6000.md} for examples of the use of this insn pattern.
4603 @cindex @samp{store_multiple} instruction pattern
4604 @item @samp{store_multiple}
4605 Similar to @samp{load_multiple}, but store several consecutive registers
4606 into consecutive memory locations. Operand 0 is the first of the
4607 consecutive memory locations, operand 1 is the first register, and
4608 operand 2 is a constant: the number of consecutive registers.
4610 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4611 @item @samp{vec_load_lanes@var{m}@var{n}}
4612 Perform an interleaved load of several vectors from memory operand 1
4613 into register operand 0. Both operands have mode @var{m}. The register
4614 operand is viewed as holding consecutive vectors of mode @var{n},
4615 while the memory operand is a flat array that contains the same number
4616 of elements. The operation is equivalent to:
4619 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4620 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4621 for (i = 0; i < c; i++)
4622 operand0[i][j] = operand1[j * c + i];
4625 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4626 from memory into a register of mode @samp{TI}@. The register
4627 contains two consecutive vectors of mode @samp{V4HI}@.
4629 This pattern can only be used if:
4631 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4633 is true. GCC assumes that, if a target supports this kind of
4634 instruction for some mode @var{n}, it also supports unaligned
4635 loads for vectors of mode @var{n}.
4637 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4638 @item @samp{vec_store_lanes@var{m}@var{n}}
4639 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4640 and register operands reversed. That is, the instruction is
4644 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4645 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4646 for (i = 0; i < c; i++)
4647 operand0[j * c + i] = operand1[i][j];
4650 for a memory operand 0 and register operand 1.
4652 @cindex @code{vec_set@var{m}} instruction pattern
4653 @item @samp{vec_set@var{m}}
4654 Set given field in the vector value. Operand 0 is the vector to modify,
4655 operand 1 is new value of field and operand 2 specify the field index.
4657 @cindex @code{vec_extract@var{m}} instruction pattern
4658 @item @samp{vec_extract@var{m}}
4659 Extract given field from the vector value. Operand 1 is the vector, operand 2
4660 specify field index and operand 0 place to store value into.
4662 @cindex @code{vec_init@var{m}} instruction pattern
4663 @item @samp{vec_init@var{m}}
4664 Initialize the vector to given values. Operand 0 is the vector to initialize
4665 and operand 1 is parallel containing values for individual fields.
4667 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4668 @item @samp{vcond@var{m}@var{n}}
4669 Output a conditional vector move. Operand 0 is the destination to
4670 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4671 dependent on the outcome of the predicate in operand 3 which is a
4672 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4673 modes @var{m} and @var{n} should have the same size. Operand 0
4674 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4675 where @var{msk} is computed by element-wise evaluation of the vector
4676 comparison with a truth value of all-ones and a false value of all-zeros.
4678 @cindex @code{vec_perm@var{m}} instruction pattern
4679 @item @samp{vec_perm@var{m}}
4680 Output a (variable) vector permutation. Operand 0 is the destination
4681 to receive elements from operand 1 and operand 2, which are of mode
4682 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4683 vector of the same width and number of elements as mode @var{m}.
4685 The input elements are numbered from 0 in operand 1 through
4686 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4687 be computed modulo @math{2*@var{N}}. Note that if
4688 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4689 with just operand 1 and selector elements modulo @var{N}.
4691 In order to make things easy for a number of targets, if there is no
4692 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4693 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4694 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4697 @cindex @code{vec_perm_const@var{m}} instruction pattern
4698 @item @samp{vec_perm_const@var{m}}
4699 Like @samp{vec_perm} except that the permutation is a compile-time
4700 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4702 Some targets cannot perform a permutation with a variable selector,
4703 but can efficiently perform a constant permutation. Further, the
4704 target hook @code{vec_perm_ok} is queried to determine if the
4705 specific constant permutation is available efficiently; the named
4706 pattern is never expanded without @code{vec_perm_ok} returning true.
4708 There is no need for a target to supply both @samp{vec_perm@var{m}}
4709 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4710 the operation with, say, the vector constant loaded into a register.
4712 @cindex @code{push@var{m}1} instruction pattern
4713 @item @samp{push@var{m}1}
4714 Output a push instruction. Operand 0 is value to push. Used only when
4715 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4716 missing and in such case an @code{mov} expander is used instead, with a
4717 @code{MEM} expression forming the push operation. The @code{mov} expander
4718 method is deprecated.
4720 @cindex @code{add@var{m}3} instruction pattern
4721 @item @samp{add@var{m}3}
4722 Add operand 2 and operand 1, storing the result in operand 0. All operands
4723 must have mode @var{m}. This can be used even on two-address machines, by
4724 means of constraints requiring operands 1 and 0 to be the same location.
4726 @cindex @code{addptr@var{m}3} instruction pattern
4727 @item @samp{addptr@var{m}3}
4728 Like @code{add@var{m}3} but is guaranteed to only be used for address
4729 calculations. The expanded code is not allowed to clobber the
4730 condition code. It only needs to be defined if @code{add@var{m}3}
4731 sets the condition code. If adds used for address calculations and
4732 normal adds are not compatible it is required to expand a distinct
4733 pattern (e.g. using an unspec). The pattern is used by LRA to emit
4734 address calculations. @code{add@var{m}3} is used if
4735 @code{addptr@var{m}3} is not defined.
4737 @cindex @code{ssadd@var{m}3} instruction pattern
4738 @cindex @code{usadd@var{m}3} instruction pattern
4739 @cindex @code{sub@var{m}3} instruction pattern
4740 @cindex @code{sssub@var{m}3} instruction pattern
4741 @cindex @code{ussub@var{m}3} instruction pattern
4742 @cindex @code{mul@var{m}3} instruction pattern
4743 @cindex @code{ssmul@var{m}3} instruction pattern
4744 @cindex @code{usmul@var{m}3} instruction pattern
4745 @cindex @code{div@var{m}3} instruction pattern
4746 @cindex @code{ssdiv@var{m}3} instruction pattern
4747 @cindex @code{udiv@var{m}3} instruction pattern
4748 @cindex @code{usdiv@var{m}3} instruction pattern
4749 @cindex @code{mod@var{m}3} instruction pattern
4750 @cindex @code{umod@var{m}3} instruction pattern
4751 @cindex @code{umin@var{m}3} instruction pattern
4752 @cindex @code{umax@var{m}3} instruction pattern
4753 @cindex @code{and@var{m}3} instruction pattern
4754 @cindex @code{ior@var{m}3} instruction pattern
4755 @cindex @code{xor@var{m}3} instruction pattern
4756 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4757 @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4758 @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4759 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4760 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4761 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4762 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4763 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4764 Similar, for other arithmetic operations.
4766 @cindex @code{fma@var{m}4} instruction pattern
4767 @item @samp{fma@var{m}4}
4768 Multiply operand 2 and operand 1, then add operand 3, storing the
4769 result in operand 0 without doing an intermediate rounding step. All
4770 operands must have mode @var{m}. This pattern is used to implement
4771 the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from
4772 the ISO C99 standard.
4774 @cindex @code{fms@var{m}4} instruction pattern
4775 @item @samp{fms@var{m}4}
4776 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4777 product instead of added to the product. This is represented
4781 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4784 @cindex @code{fnma@var{m}4} instruction pattern
4785 @item @samp{fnma@var{m}4}
4786 Like @code{fma@var{m}4} except that the intermediate product
4787 is negated before being added to operand 3. This is represented
4791 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4794 @cindex @code{fnms@var{m}4} instruction pattern
4795 @item @samp{fnms@var{m}4}
4796 Like @code{fms@var{m}4} except that the intermediate product
4797 is negated before subtracting operand 3. This is represented
4801 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4804 @cindex @code{min@var{m}3} instruction pattern
4805 @cindex @code{max@var{m}3} instruction pattern
4806 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4807 Signed minimum and maximum operations. When used with floating point,
4808 if both operands are zeros, or if either operand is @code{NaN}, then
4809 it is unspecified which of the two operands is returned as the result.
4811 @cindex @code{reduc_smin_@var{m}} instruction pattern
4812 @cindex @code{reduc_smax_@var{m}} instruction pattern
4813 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4814 Find the signed minimum/maximum of the elements of a vector. The vector is
4815 operand 1, and the scalar result is stored in the least significant bits of
4816 operand 0 (also a vector). The output and input vector should have the same
4819 @cindex @code{reduc_umin_@var{m}} instruction pattern
4820 @cindex @code{reduc_umax_@var{m}} instruction pattern
4821 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4822 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4823 operand 1, and the scalar result is stored in the least significant bits of
4824 operand 0 (also a vector). The output and input vector should have the same
4827 @cindex @code{reduc_splus_@var{m}} instruction pattern
4828 @item @samp{reduc_splus_@var{m}}
4829 Compute the sum of the signed elements of a vector. The vector is operand 1,
4830 and the scalar result is stored in the least significant bits of operand 0
4831 (also a vector). The output and input vector should have the same modes.
4833 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4834 @item @samp{reduc_uplus_@var{m}}
4835 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4836 and the scalar result is stored in the least significant bits of operand 0
4837 (also a vector). The output and input vector should have the same modes.
4839 @cindex @code{sdot_prod@var{m}} instruction pattern
4840 @item @samp{sdot_prod@var{m}}
4841 @cindex @code{udot_prod@var{m}} instruction pattern
4842 @item @samp{udot_prod@var{m}}
4843 Compute the sum of the products of two signed/unsigned elements.
4844 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4845 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4846 wider than the mode of the product. The result is placed in operand 0, which
4847 is of the same mode as operand 3.
4849 @cindex @code{ssum_widen@var{m3}} instruction pattern
4850 @item @samp{ssum_widen@var{m3}}
4851 @cindex @code{usum_widen@var{m3}} instruction pattern
4852 @item @samp{usum_widen@var{m3}}
4853 Operands 0 and 2 are of the same mode, which is wider than the mode of
4854 operand 1. Add operand 1 to operand 2 and place the widened result in
4855 operand 0. (This is used express accumulation of elements into an accumulator
4858 @cindex @code{vec_shl_@var{m}} instruction pattern
4859 @cindex @code{vec_shr_@var{m}} instruction pattern
4860 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4861 Whole vector left/right shift in bits.
4862 Operand 1 is a vector to be shifted.
4863 Operand 2 is an integer shift amount in bits.
4864 Operand 0 is where the resulting shifted vector is stored.
4865 The output and input vectors should have the same modes.
4867 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4868 @item @samp{vec_pack_trunc_@var{m}}
4869 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4870 are vectors of the same mode having N integral or floating point elements
4871 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4872 size N/2 are concatenated after narrowing them down using truncation.
4874 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4875 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4876 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4877 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4878 are vectors of the same mode having N integral elements of size S.
4879 Operand 0 is the resulting vector in which the elements of the two input
4880 vectors are concatenated after narrowing them down using signed/unsigned
4881 saturating arithmetic.
4883 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4884 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4885 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4886 Narrow, convert to signed/unsigned integral type and merge the elements
4887 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4888 floating point elements of size S@. Operand 0 is the resulting vector
4889 in which 2*N elements of size N/2 are concatenated.
4891 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4892 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4893 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4894 Extract and widen (promote) the high/low part of a vector of signed
4895 integral or floating point elements. The input vector (operand 1) has N
4896 elements of size S@. Widen (promote) the high/low elements of the vector
4897 using signed or floating point extension and place the resulting N/2
4898 values of size 2*S in the output vector (operand 0).
4900 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4901 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4902 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4903 Extract and widen (promote) the high/low part of a vector of unsigned
4904 integral elements. The input vector (operand 1) has N elements of size S.
4905 Widen (promote) the high/low elements of the vector using zero extension and
4906 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4908 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4909 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4910 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4911 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4912 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4913 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4914 Extract, convert to floating point type and widen the high/low part of a
4915 vector of signed/unsigned integral elements. The input vector (operand 1)
4916 has N elements of size S@. Convert the high/low elements of the vector using
4917 floating point conversion and place the resulting N/2 values of size 2*S in
4918 the output vector (operand 0).
4920 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4921 @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern
4922 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4923 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4924 @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern
4925 @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern
4926 @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern
4927 @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern
4928 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4929 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4930 @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}}
4931 @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}}
4932 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4933 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4934 or even/odd elements of the two vectors, and put the N/2 products of size 2*S
4935 in the output vector (operand 0). A target shouldn't implement even/odd pattern
4936 pair if it is less efficient than lo/hi one.
4938 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4939 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4940 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4941 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4942 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4943 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4944 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4945 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4946 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4947 output vector (operand 0).
4949 @cindex @code{mulhisi3} instruction pattern
4950 @item @samp{mulhisi3}
4951 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4952 a @code{SImode} product in operand 0.
4954 @cindex @code{mulqihi3} instruction pattern
4955 @cindex @code{mulsidi3} instruction pattern
4956 @item @samp{mulqihi3}, @samp{mulsidi3}
4957 Similar widening-multiplication instructions of other widths.
4959 @cindex @code{umulqihi3} instruction pattern
4960 @cindex @code{umulhisi3} instruction pattern
4961 @cindex @code{umulsidi3} instruction pattern
4962 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4963 Similar widening-multiplication instructions that do unsigned
4966 @cindex @code{usmulqihi3} instruction pattern
4967 @cindex @code{usmulhisi3} instruction pattern
4968 @cindex @code{usmulsidi3} instruction pattern
4969 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4970 Similar widening-multiplication instructions that interpret the first
4971 operand as unsigned and the second operand as signed, then do a signed
4974 @cindex @code{smul@var{m}3_highpart} instruction pattern
4975 @item @samp{smul@var{m}3_highpart}
4976 Perform a signed multiplication of operands 1 and 2, which have mode
4977 @var{m}, and store the most significant half of the product in operand 0.
4978 The least significant half of the product is discarded.
4980 @cindex @code{umul@var{m}3_highpart} instruction pattern
4981 @item @samp{umul@var{m}3_highpart}
4982 Similar, but the multiplication is unsigned.
4984 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4985 @item @samp{madd@var{m}@var{n}4}
4986 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4987 operand 3, and store the result in operand 0. Operands 1 and 2
4988 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4989 Both modes must be integer or fixed-point modes and @var{n} must be twice
4990 the size of @var{m}.
4992 In other words, @code{madd@var{m}@var{n}4} is like
4993 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4995 These instructions are not allowed to @code{FAIL}.
4997 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4998 @item @samp{umadd@var{m}@var{n}4}
4999 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
5000 operands instead of sign-extending them.
5002 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
5003 @item @samp{ssmadd@var{m}@var{n}4}
5004 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
5007 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
5008 @item @samp{usmadd@var{m}@var{n}4}
5009 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
5010 unsigned-saturating.
5012 @cindex @code{msub@var{m}@var{n}4} instruction pattern
5013 @item @samp{msub@var{m}@var{n}4}
5014 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
5015 result from operand 3, and store the result in operand 0. Operands 1 and 2
5016 have mode @var{m} and operands 0 and 3 have mode @var{n}.
5017 Both modes must be integer or fixed-point modes and @var{n} must be twice
5018 the size of @var{m}.
5020 In other words, @code{msub@var{m}@var{n}4} is like
5021 @code{mul@var{m}@var{n}3} except that it also subtracts the result
5024 These instructions are not allowed to @code{FAIL}.
5026 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
5027 @item @samp{umsub@var{m}@var{n}4}
5028 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
5029 operands instead of sign-extending them.
5031 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
5032 @item @samp{ssmsub@var{m}@var{n}4}
5033 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
5036 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
5037 @item @samp{usmsub@var{m}@var{n}4}
5038 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
5039 unsigned-saturating.
5041 @cindex @code{divmod@var{m}4} instruction pattern
5042 @item @samp{divmod@var{m}4}
5043 Signed division that produces both a quotient and a remainder.
5044 Operand 1 is divided by operand 2 to produce a quotient stored
5045 in operand 0 and a remainder stored in operand 3.
5047 For machines with an instruction that produces both a quotient and a
5048 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
5049 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
5050 allows optimization in the relatively common case when both the quotient
5051 and remainder are computed.
5053 If an instruction that just produces a quotient or just a remainder
5054 exists and is more efficient than the instruction that produces both,
5055 write the output routine of @samp{divmod@var{m}4} to call
5056 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
5057 quotient or remainder and generate the appropriate instruction.
5059 @cindex @code{udivmod@var{m}4} instruction pattern
5060 @item @samp{udivmod@var{m}4}
5061 Similar, but does unsigned division.
5063 @anchor{shift patterns}
5064 @cindex @code{ashl@var{m}3} instruction pattern
5065 @cindex @code{ssashl@var{m}3} instruction pattern
5066 @cindex @code{usashl@var{m}3} instruction pattern
5067 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
5068 Arithmetic-shift operand 1 left by a number of bits specified by operand
5069 2, and store the result in operand 0. Here @var{m} is the mode of
5070 operand 0 and operand 1; operand 2's mode is specified by the
5071 instruction pattern, and the compiler will convert the operand to that
5072 mode before generating the instruction. The meaning of out-of-range shift
5073 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
5074 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
5076 @cindex @code{ashr@var{m}3} instruction pattern
5077 @cindex @code{lshr@var{m}3} instruction pattern
5078 @cindex @code{rotl@var{m}3} instruction pattern
5079 @cindex @code{rotr@var{m}3} instruction pattern
5080 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
5081 Other shift and rotate instructions, analogous to the
5082 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
5084 @cindex @code{vashl@var{m}3} instruction pattern
5085 @cindex @code{vashr@var{m}3} instruction pattern
5086 @cindex @code{vlshr@var{m}3} instruction pattern
5087 @cindex @code{vrotl@var{m}3} instruction pattern
5088 @cindex @code{vrotr@var{m}3} instruction pattern
5089 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
5090 Vector shift and rotate instructions that take vectors as operand 2
5091 instead of a scalar type.
5093 @cindex @code{bswap@var{m}2} instruction pattern
5094 @item @samp{bswap@var{m}2}
5095 Reverse the order of bytes of operand 1 and store the result in operand 0.
5097 @cindex @code{neg@var{m}2} instruction pattern
5098 @cindex @code{ssneg@var{m}2} instruction pattern
5099 @cindex @code{usneg@var{m}2} instruction pattern
5100 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
5101 Negate operand 1 and store the result in operand 0.
5103 @cindex @code{abs@var{m}2} instruction pattern
5104 @item @samp{abs@var{m}2}
5105 Store the absolute value of operand 1 into operand 0.
5107 @cindex @code{sqrt@var{m}2} instruction pattern
5108 @item @samp{sqrt@var{m}2}
5109 Store the square root of operand 1 into operand 0.
5111 The @code{sqrt} built-in function of C always uses the mode which
5112 corresponds to the C data type @code{double} and the @code{sqrtf}
5113 built-in function uses the mode which corresponds to the C data
5116 @cindex @code{fmod@var{m}3} instruction pattern
5117 @item @samp{fmod@var{m}3}
5118 Store the remainder of dividing operand 1 by operand 2 into
5119 operand 0, rounded towards zero to an integer.
5121 The @code{fmod} built-in function of C always uses the mode which
5122 corresponds to the C data type @code{double} and the @code{fmodf}
5123 built-in function uses the mode which corresponds to the C data
5126 @cindex @code{remainder@var{m}3} instruction pattern
5127 @item @samp{remainder@var{m}3}
5128 Store the remainder of dividing operand 1 by operand 2 into
5129 operand 0, rounded to the nearest integer.
5131 The @code{remainder} built-in function of C always uses the mode
5132 which corresponds to the C data type @code{double} and the
5133 @code{remainderf} built-in function uses the mode which corresponds
5134 to the C data type @code{float}.
5136 @cindex @code{cos@var{m}2} instruction pattern
5137 @item @samp{cos@var{m}2}
5138 Store the cosine of operand 1 into operand 0.
5140 The @code{cos} built-in function of C always uses the mode which
5141 corresponds to the C data type @code{double} and the @code{cosf}
5142 built-in function uses the mode which corresponds to the C data
5145 @cindex @code{sin@var{m}2} instruction pattern
5146 @item @samp{sin@var{m}2}
5147 Store the sine of operand 1 into operand 0.
5149 The @code{sin} built-in function of C always uses the mode which
5150 corresponds to the C data type @code{double} and the @code{sinf}
5151 built-in function uses the mode which corresponds to the C data
5154 @cindex @code{sincos@var{m}3} instruction pattern
5155 @item @samp{sincos@var{m}3}
5156 Store the cosine of operand 2 into operand 0 and the sine of
5157 operand 2 into operand 1.
5159 The @code{sin} and @code{cos} built-in functions of C always use the
5160 mode which corresponds to the C data type @code{double} and the
5161 @code{sinf} and @code{cosf} built-in function use the mode which
5162 corresponds to the C data type @code{float}.
5163 Targets that can calculate the sine and cosine simultaneously can
5164 implement this pattern as opposed to implementing individual
5165 @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin}
5166 and @code{cos} built-in functions will then be expanded to the
5167 @code{sincos@var{m}3} pattern, with one of the output values
5170 @cindex @code{exp@var{m}2} instruction pattern
5171 @item @samp{exp@var{m}2}
5172 Store the exponential of operand 1 into operand 0.
5174 The @code{exp} built-in function of C always uses the mode which
5175 corresponds to the C data type @code{double} and the @code{expf}
5176 built-in function uses the mode which corresponds to the C data
5179 @cindex @code{log@var{m}2} instruction pattern
5180 @item @samp{log@var{m}2}
5181 Store the natural logarithm of operand 1 into operand 0.
5183 The @code{log} built-in function of C always uses the mode which
5184 corresponds to the C data type @code{double} and the @code{logf}
5185 built-in function uses the mode which corresponds to the C data
5188 @cindex @code{pow@var{m}3} instruction pattern
5189 @item @samp{pow@var{m}3}
5190 Store the value of operand 1 raised to the exponent operand 2
5193 The @code{pow} built-in function of C always uses the mode which
5194 corresponds to the C data type @code{double} and the @code{powf}
5195 built-in function uses the mode which corresponds to the C data
5198 @cindex @code{atan2@var{m}3} instruction pattern
5199 @item @samp{atan2@var{m}3}
5200 Store the arc tangent (inverse tangent) of operand 1 divided by
5201 operand 2 into operand 0, using the signs of both arguments to
5202 determine the quadrant of the result.
5204 The @code{atan2} built-in function of C always uses the mode which
5205 corresponds to the C data type @code{double} and the @code{atan2f}
5206 built-in function uses the mode which corresponds to the C data
5209 @cindex @code{floor@var{m}2} instruction pattern
5210 @item @samp{floor@var{m}2}
5211 Store the largest integral value not greater than argument.
5213 The @code{floor} built-in function of C always uses the mode which
5214 corresponds to the C data type @code{double} and the @code{floorf}
5215 built-in function uses the mode which corresponds to the C data
5218 @cindex @code{btrunc@var{m}2} instruction pattern
5219 @item @samp{btrunc@var{m}2}
5220 Store the argument rounded to integer towards zero.
5222 The @code{trunc} built-in function of C always uses the mode which
5223 corresponds to the C data type @code{double} and the @code{truncf}
5224 built-in function uses the mode which corresponds to the C data
5227 @cindex @code{round@var{m}2} instruction pattern
5228 @item @samp{round@var{m}2}
5229 Store the argument rounded to integer away from zero.
5231 The @code{round} built-in function of C always uses the mode which
5232 corresponds to the C data type @code{double} and the @code{roundf}
5233 built-in function uses the mode which corresponds to the C data
5236 @cindex @code{ceil@var{m}2} instruction pattern
5237 @item @samp{ceil@var{m}2}
5238 Store the argument rounded to integer away from zero.
5240 The @code{ceil} built-in function of C always uses the mode which
5241 corresponds to the C data type @code{double} and the @code{ceilf}
5242 built-in function uses the mode which corresponds to the C data
5245 @cindex @code{nearbyint@var{m}2} instruction pattern
5246 @item @samp{nearbyint@var{m}2}
5247 Store the argument rounded according to the default rounding mode
5249 The @code{nearbyint} built-in function of C always uses the mode which
5250 corresponds to the C data type @code{double} and the @code{nearbyintf}
5251 built-in function uses the mode which corresponds to the C data
5254 @cindex @code{rint@var{m}2} instruction pattern
5255 @item @samp{rint@var{m}2}
5256 Store the argument rounded according to the default rounding mode and
5257 raise the inexact exception when the result differs in value from
5260 The @code{rint} built-in function of C always uses the mode which
5261 corresponds to the C data type @code{double} and the @code{rintf}
5262 built-in function uses the mode which corresponds to the C data
5265 @cindex @code{lrint@var{m}@var{n}2}
5266 @item @samp{lrint@var{m}@var{n}2}
5267 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5268 point mode @var{n} as a signed number according to the current
5269 rounding mode and store in operand 0 (which has mode @var{n}).
5271 @cindex @code{lround@var{m}@var{n}2}
5272 @item @samp{lround@var{m}@var{n}2}
5273 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5274 point mode @var{n} as a signed number rounding to nearest and away
5275 from zero and store in operand 0 (which has mode @var{n}).
5277 @cindex @code{lfloor@var{m}@var{n}2}
5278 @item @samp{lfloor@var{m}@var{n}2}
5279 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5280 point mode @var{n} as a signed number rounding down and store in
5281 operand 0 (which has mode @var{n}).
5283 @cindex @code{lceil@var{m}@var{n}2}
5284 @item @samp{lceil@var{m}@var{n}2}
5285 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5286 point mode @var{n} as a signed number rounding up and store in
5287 operand 0 (which has mode @var{n}).
5289 @cindex @code{copysign@var{m}3} instruction pattern
5290 @item @samp{copysign@var{m}3}
5291 Store a value with the magnitude of operand 1 and the sign of operand
5294 The @code{copysign} built-in function of C always uses the mode which
5295 corresponds to the C data type @code{double} and the @code{copysignf}
5296 built-in function uses the mode which corresponds to the C data
5299 @cindex @code{ffs@var{m}2} instruction pattern
5300 @item @samp{ffs@var{m}2}
5301 Store into operand 0 one plus the index of the least significant 1-bit
5302 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
5303 of operand 0; operand 1's mode is specified by the instruction
5304 pattern, and the compiler will convert the operand to that mode before
5305 generating the instruction.
5307 The @code{ffs} built-in function of C always uses the mode which
5308 corresponds to the C data type @code{int}.
5310 @cindex @code{clz@var{m}2} instruction pattern
5311 @item @samp{clz@var{m}2}
5312 Store into operand 0 the number of leading 0-bits in @var{x}, starting
5313 at the most significant bit position. If @var{x} is 0, the
5314 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5315 the result is undefined or has a useful value.
5316 @var{m} is the mode of operand 0; operand 1's mode is
5317 specified by the instruction pattern, and the compiler will convert the
5318 operand to that mode before generating the instruction.
5320 @cindex @code{ctz@var{m}2} instruction pattern
5321 @item @samp{ctz@var{m}2}
5322 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
5323 at the least significant bit position. If @var{x} is 0, the
5324 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
5325 the result is undefined or has a useful value.
5326 @var{m} is the mode of operand 0; operand 1's mode is
5327 specified by the instruction pattern, and the compiler will convert the
5328 operand to that mode before generating the instruction.
5330 @cindex @code{popcount@var{m}2} instruction pattern
5331 @item @samp{popcount@var{m}2}
5332 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
5333 mode of operand 0; operand 1's mode is specified by the instruction
5334 pattern, and the compiler will convert the operand to that mode before
5335 generating the instruction.
5337 @cindex @code{parity@var{m}2} instruction pattern
5338 @item @samp{parity@var{m}2}
5339 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
5340 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
5341 is specified by the instruction pattern, and the compiler will convert
5342 the operand to that mode before generating the instruction.
5344 @cindex @code{one_cmpl@var{m}2} instruction pattern
5345 @item @samp{one_cmpl@var{m}2}
5346 Store the bitwise-complement of operand 1 into operand 0.
5348 @cindex @code{movmem@var{m}} instruction pattern
5349 @item @samp{movmem@var{m}}
5350 Block move instruction. The destination and source blocks of memory
5351 are the first two operands, and both are @code{mem:BLK}s with an
5352 address in mode @code{Pmode}.
5354 The number of bytes to move is the third operand, in mode @var{m}.
5355 Usually, you specify @code{Pmode} for @var{m}. However, if you can
5356 generate better code knowing the range of valid lengths is smaller than
5357 those representable in a full Pmode pointer, you should provide
5359 mode corresponding to the range of values you can handle efficiently
5360 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
5361 that appear negative) and also a pattern with @code{Pmode}.
5363 The fourth operand is the known shared alignment of the source and
5364 destination, in the form of a @code{const_int} rtx. Thus, if the
5365 compiler knows that both source and destination are word-aligned,
5366 it may provide the value 4 for this operand.
5368 Optional operands 5 and 6 specify expected alignment and size of block
5369 respectively. The expected alignment differs from alignment in operand 4
5370 in a way that the blocks are not required to be aligned according to it in
5371 all cases. This expected alignment is also in bytes, just like operand 4.
5372 Expected size, when unknown, is set to @code{(const_int -1)}.
5374 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5375 beneficial if the patterns for smaller modes have fewer restrictions
5376 on their first, second and fourth operands. Note that the mode @var{m}
5377 in @code{movmem@var{m}} does not impose any restriction on the mode of
5378 individually moved data units in the block.
5380 These patterns need not give special consideration to the possibility
5381 that the source and destination strings might overlap.
5383 @cindex @code{movstr} instruction pattern
5385 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5386 an output operand in mode @code{Pmode}. The addresses of the
5387 destination and source strings are operands 1 and 2, and both are
5388 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5389 the expansion of this pattern should store in operand 0 the address in
5390 which the @code{NUL} terminator was stored in the destination string.
5392 This patern has also several optional operands that are same as in
5395 @cindex @code{setmem@var{m}} instruction pattern
5396 @item @samp{setmem@var{m}}
5397 Block set instruction. The destination string is the first operand,
5398 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5399 number of bytes to set is the second operand, in mode @var{m}. The value to
5400 initialize the memory with is the third operand. Targets that only support the
5401 clearing of memory should reject any value that is not the constant 0. See
5402 @samp{movmem@var{m}} for a discussion of the choice of mode.
5404 The fourth operand is the known alignment of the destination, in the form
5405 of a @code{const_int} rtx. Thus, if the compiler knows that the
5406 destination is word-aligned, it may provide the value 4 for this
5409 Optional operands 5 and 6 specify expected alignment and size of block
5410 respectively. The expected alignment differs from alignment in operand 4
5411 in a way that the blocks are not required to be aligned according to it in
5412 all cases. This expected alignment is also in bytes, just like operand 4.
5413 Expected size, when unknown, is set to @code{(const_int -1)}.
5414 Operand 7 is the minimal size of the block and operand 8 is the
5415 maximal size of the block (NULL if it can not be represented as CONST_INT).
5416 Operand 9 is the probable maximal size (i.e. we can not rely on it for correctness,
5417 but it can be used for choosing proper code sequence for a given size).
5419 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5421 @cindex @code{cmpstrn@var{m}} instruction pattern
5422 @item @samp{cmpstrn@var{m}}
5423 String compare instruction, with five operands. Operand 0 is the output;
5424 it has mode @var{m}. The remaining four operands are like the operands
5425 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5426 byte by byte in lexicographic order starting at the beginning of each
5427 string. The instruction is not allowed to prefetch more than one byte
5428 at a time since either string may end in the first byte and reading past
5429 that may access an invalid page or segment and cause a fault. The
5430 comparison terminates early if the fetched bytes are different or if
5431 they are equal to zero. The effect of the instruction is to store a
5432 value in operand 0 whose sign indicates the result of the comparison.
5434 @cindex @code{cmpstr@var{m}} instruction pattern
5435 @item @samp{cmpstr@var{m}}
5436 String compare instruction, without known maximum length. Operand 0 is the
5437 output; it has mode @var{m}. The second and third operand are the blocks of
5438 memory to be compared; both are @code{mem:BLK} with an address in mode
5441 The fourth operand is the known shared alignment of the source and
5442 destination, in the form of a @code{const_int} rtx. Thus, if the
5443 compiler knows that both source and destination are word-aligned,
5444 it may provide the value 4 for this operand.
5446 The two memory blocks specified are compared byte by byte in lexicographic
5447 order starting at the beginning of each string. The instruction is not allowed
5448 to prefetch more than one byte at a time since either string may end in the
5449 first byte and reading past that may access an invalid page or segment and
5450 cause a fault. The comparison will terminate when the fetched bytes
5451 are different or if they are equal to zero. The effect of the
5452 instruction is to store a value in operand 0 whose sign indicates the
5453 result of the comparison.
5455 @cindex @code{cmpmem@var{m}} instruction pattern
5456 @item @samp{cmpmem@var{m}}
5457 Block compare instruction, with five operands like the operands
5458 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5459 byte by byte in lexicographic order starting at the beginning of each
5460 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5461 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5462 the comparison will not stop if both bytes are zero. The effect of
5463 the instruction is to store a value in operand 0 whose sign indicates
5464 the result of the comparison.
5466 @cindex @code{strlen@var{m}} instruction pattern
5467 @item @samp{strlen@var{m}}
5468 Compute the length of a string, with three operands.
5469 Operand 0 is the result (of mode @var{m}), operand 1 is
5470 a @code{mem} referring to the first character of the string,
5471 operand 2 is the character to search for (normally zero),
5472 and operand 3 is a constant describing the known alignment
5473 of the beginning of the string.
5475 @cindex @code{float@var{m}@var{n}2} instruction pattern
5476 @item @samp{float@var{m}@var{n}2}
5477 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5478 floating point mode @var{n} and store in operand 0 (which has mode
5481 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5482 @item @samp{floatuns@var{m}@var{n}2}
5483 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5484 to floating point mode @var{n} and store in operand 0 (which has mode
5487 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5488 @item @samp{fix@var{m}@var{n}2}
5489 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5490 point mode @var{n} as a signed number and store in operand 0 (which
5491 has mode @var{n}). This instruction's result is defined only when
5492 the value of operand 1 is an integer.
5494 If the machine description defines this pattern, it also needs to
5495 define the @code{ftrunc} pattern.
5497 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5498 @item @samp{fixuns@var{m}@var{n}2}
5499 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5500 point mode @var{n} as an unsigned number and store in operand 0 (which
5501 has mode @var{n}). This instruction's result is defined only when the
5502 value of operand 1 is an integer.
5504 @cindex @code{ftrunc@var{m}2} instruction pattern
5505 @item @samp{ftrunc@var{m}2}
5506 Convert operand 1 (valid for floating point mode @var{m}) to an
5507 integer value, still represented in floating point mode @var{m}, and
5508 store it in operand 0 (valid for floating point mode @var{m}).
5510 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5511 @item @samp{fix_trunc@var{m}@var{n}2}
5512 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5513 of mode @var{m} by converting the value to an integer.
5515 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5516 @item @samp{fixuns_trunc@var{m}@var{n}2}
5517 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5518 value of mode @var{m} by converting the value to an integer.
5520 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5521 @item @samp{trunc@var{m}@var{n}2}
5522 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5523 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5524 point or both floating point.
5526 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5527 @item @samp{extend@var{m}@var{n}2}
5528 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5529 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5530 point or both floating point.
5532 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5533 @item @samp{zero_extend@var{m}@var{n}2}
5534 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5535 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5538 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5539 @item @samp{fract@var{m}@var{n}2}
5540 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5541 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5542 could be fixed-point to fixed-point, signed integer to fixed-point,
5543 fixed-point to signed integer, floating-point to fixed-point,
5544 or fixed-point to floating-point.
5545 When overflows or underflows happen, the results are undefined.
5547 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5548 @item @samp{satfract@var{m}@var{n}2}
5549 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5550 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5551 could be fixed-point to fixed-point, signed integer to fixed-point,
5552 or floating-point to fixed-point.
5553 When overflows or underflows happen, the instruction saturates the
5554 results to the maximum or the minimum.
5556 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5557 @item @samp{fractuns@var{m}@var{n}2}
5558 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5559 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5560 could be unsigned integer to fixed-point, or
5561 fixed-point to unsigned integer.
5562 When overflows or underflows happen, the results are undefined.
5564 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5565 @item @samp{satfractuns@var{m}@var{n}2}
5566 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5567 @var{n} and store in operand 0 (which has mode @var{n}).
5568 When overflows or underflows happen, the instruction saturates the
5569 results to the maximum or the minimum.
5571 @cindex @code{extv@var{m}} instruction pattern
5572 @item @samp{extv@var{m}}
5573 Extract a bit-field from register operand 1, sign-extend it, and store
5574 it in operand 0. Operand 2 specifies the width of the field in bits
5575 and operand 3 the starting bit, which counts from the most significant
5576 bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
5579 Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
5580 target-specific mode.
5582 @cindex @code{extvmisalign@var{m}} instruction pattern
5583 @item @samp{extvmisalign@var{m}}
5584 Extract a bit-field from memory operand 1, sign extend it, and store
5585 it in operand 0. Operand 2 specifies the width in bits and operand 3
5586 the starting bit. The starting bit is always somewhere in the first byte of
5587 operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5588 is true and from the least significant bit otherwise.
5590 Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
5591 Operands 2 and 3 have a target-specific mode.
5593 The instruction must not read beyond the last byte of the bit-field.
5595 @cindex @code{extzv@var{m}} instruction pattern
5596 @item @samp{extzv@var{m}}
5597 Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
5599 @cindex @code{extzvmisalign@var{m}} instruction pattern
5600 @item @samp{extzvmisalign@var{m}}
5601 Like @samp{extvmisalign@var{m}} except that the bit-field value is
5604 @cindex @code{insv@var{m}} instruction pattern
5605 @item @samp{insv@var{m}}
5606 Insert operand 3 into a bit-field of register operand 0. Operand 1
5607 specifies the width of the field in bits and operand 2 the starting bit,
5608 which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5609 is true and from the least significant bit otherwise.
5611 Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
5612 target-specific mode.
5614 @cindex @code{insvmisalign@var{m}} instruction pattern
5615 @item @samp{insvmisalign@var{m}}
5616 Insert operand 3 into a bit-field of memory operand 0. Operand 1
5617 specifies the width of the field in bits and operand 2 the starting bit.
5618 The starting bit is always somewhere in the first byte of operand 0;
5619 it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
5620 is true and from the least significant bit otherwise.
5622 Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
5623 Operands 1 and 2 have a target-specific mode.
5625 The instruction must not read or write beyond the last byte of the bit-field.
5627 @cindex @code{extv} instruction pattern
5629 Extract a bit-field from operand 1 (a register or memory operand), where
5630 operand 2 specifies the width in bits and operand 3 the starting bit,
5631 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5632 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5633 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5634 be valid for @code{word_mode}.
5636 The RTL generation pass generates this instruction only with constants
5637 for operands 2 and 3 and the constant is never zero for operand 2.
5639 The bit-field value is sign-extended to a full word integer
5640 before it is stored in operand 0.
5642 This pattern is deprecated; please use @samp{extv@var{m}} and
5643 @code{extvmisalign@var{m}} instead.
5645 @cindex @code{extzv} instruction pattern
5647 Like @samp{extv} except that the bit-field value is zero-extended.
5649 This pattern is deprecated; please use @samp{extzv@var{m}} and
5650 @code{extzvmisalign@var{m}} instead.
5652 @cindex @code{insv} instruction pattern
5654 Store operand 3 (which must be valid for @code{word_mode}) into a
5655 bit-field in operand 0, where operand 1 specifies the width in bits and
5656 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5657 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5658 Operands 1 and 2 must be valid for @code{word_mode}.
5660 The RTL generation pass generates this instruction only with constants
5661 for operands 1 and 2 and the constant is never zero for operand 1.
5663 This pattern is deprecated; please use @samp{insv@var{m}} and
5664 @code{insvmisalign@var{m}} instead.
5666 @cindex @code{mov@var{mode}cc} instruction pattern
5667 @item @samp{mov@var{mode}cc}
5668 Conditionally move operand 2 or operand 3 into operand 0 according to the
5669 comparison in operand 1. If the comparison is true, operand 2 is moved
5670 into operand 0, otherwise operand 3 is moved.
5672 The mode of the operands being compared need not be the same as the operands
5673 being moved. Some machines, sparc64 for example, have instructions that
5674 conditionally move an integer value based on the floating point condition
5675 codes and vice versa.
5677 If the machine does not have conditional move instructions, do not
5678 define these patterns.
5680 @cindex @code{add@var{mode}cc} instruction pattern
5681 @item @samp{add@var{mode}cc}
5682 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5683 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5684 comparison in operand 1. If the comparison is false, operand 2 is moved into
5685 operand 0, otherwise (operand 2 + operand 3) is moved.
5687 @cindex @code{cstore@var{mode}4} instruction pattern
5688 @item @samp{cstore@var{mode}4}
5689 Store zero or nonzero in operand 0 according to whether a comparison
5690 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5691 are the first and second operand of the comparison, respectively.
5692 You specify the mode that operand 0 must have when you write the
5693 @code{match_operand} expression. The compiler automatically sees which
5694 mode you have used and supplies an operand of that mode.
5696 The value stored for a true condition must have 1 as its low bit, or
5697 else must be negative. Otherwise the instruction is not suitable and
5698 you should omit it from the machine description. You describe to the
5699 compiler exactly which value is stored by defining the macro
5700 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5701 found that can be used for all the possible comparison operators, you
5702 should pick one and use a @code{define_expand} to map all results
5703 onto the one you chose.
5705 These operations may @code{FAIL}, but should do so only in relatively
5706 uncommon cases; if they would @code{FAIL} for common cases involving
5707 integer comparisons, it is best to restrict the predicates to not
5708 allow these operands. Likewise if a given comparison operator will
5709 always fail, independent of the operands (for floating-point modes, the
5710 @code{ordered_comparison_operator} predicate is often useful in this case).
5712 If this pattern is omitted, the compiler will generate a conditional
5713 branch---for example, it may copy a constant one to the target and branching
5714 around an assignment of zero to the target---or a libcall. If the predicate
5715 for operand 1 only rejects some operators, it will also try reordering the
5716 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5717 These possibilities could be cheaper or equivalent to the instructions
5718 used for the @samp{cstore@var{mode}4} pattern followed by those required
5719 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5720 case, you can and should make operand 1's predicate reject some operators
5721 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5722 from the machine description.
5724 @cindex @code{cbranch@var{mode}4} instruction pattern
5725 @item @samp{cbranch@var{mode}4}
5726 Conditional branch instruction combined with a compare instruction.
5727 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5728 first and second operands of the comparison, respectively. Operand 3
5729 is a @code{label_ref} that refers to the label to jump to.
5731 @cindex @code{jump} instruction pattern
5733 A jump inside a function; an unconditional branch. Operand 0 is the
5734 @code{label_ref} of the label to jump to. This pattern name is mandatory
5737 @cindex @code{call} instruction pattern
5739 Subroutine call instruction returning no value. Operand 0 is the
5740 function to call; operand 1 is the number of bytes of arguments pushed
5741 as a @code{const_int}; operand 2 is the number of registers used as
5744 On most machines, operand 2 is not actually stored into the RTL
5745 pattern. It is supplied for the sake of some RISC machines which need
5746 to put this information into the assembler code; they can put it in
5747 the RTL instead of operand 1.
5749 Operand 0 should be a @code{mem} RTX whose address is the address of the
5750 function. Note, however, that this address can be a @code{symbol_ref}
5751 expression even if it would not be a legitimate memory address on the
5752 target machine. If it is also not a valid argument for a call
5753 instruction, the pattern for this operation should be a
5754 @code{define_expand} (@pxref{Expander Definitions}) that places the
5755 address into a register and uses that register in the call instruction.
5757 @cindex @code{call_value} instruction pattern
5758 @item @samp{call_value}
5759 Subroutine call instruction returning a value. Operand 0 is the hard
5760 register in which the value is returned. There are three more
5761 operands, the same as the three operands of the @samp{call}
5762 instruction (but with numbers increased by one).
5764 Subroutines that return @code{BLKmode} objects use the @samp{call}
5767 @cindex @code{call_pop} instruction pattern
5768 @cindex @code{call_value_pop} instruction pattern
5769 @item @samp{call_pop}, @samp{call_value_pop}
5770 Similar to @samp{call} and @samp{call_value}, except used if defined and
5771 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5772 that contains both the function call and a @code{set} to indicate the
5773 adjustment made to the frame pointer.
5775 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5776 patterns increases the number of functions for which the frame pointer
5777 can be eliminated, if desired.
5779 @cindex @code{untyped_call} instruction pattern
5780 @item @samp{untyped_call}
5781 Subroutine call instruction returning a value of any type. Operand 0 is
5782 the function to call; operand 1 is a memory location where the result of
5783 calling the function is to be stored; operand 2 is a @code{parallel}
5784 expression where each element is a @code{set} expression that indicates
5785 the saving of a function return value into the result block.
5787 This instruction pattern should be defined to support
5788 @code{__builtin_apply} on machines where special instructions are needed
5789 to call a subroutine with arbitrary arguments or to save the value
5790 returned. This instruction pattern is required on machines that have
5791 multiple registers that can hold a return value
5792 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5794 @cindex @code{return} instruction pattern
5796 Subroutine return instruction. This instruction pattern name should be
5797 defined only if a single instruction can do all the work of returning
5800 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5801 RTL generation phase. In this case it is to support machines where
5802 multiple instructions are usually needed to return from a function, but
5803 some class of functions only requires one instruction to implement a
5804 return. Normally, the applicable functions are those which do not need
5805 to save any registers or allocate stack space.
5807 It is valid for this pattern to expand to an instruction using
5808 @code{simple_return} if no epilogue is required.
5810 @cindex @code{simple_return} instruction pattern
5811 @item @samp{simple_return}
5812 Subroutine return instruction. This instruction pattern name should be
5813 defined only if a single instruction can do all the work of returning
5814 from a function on a path where no epilogue is required. This pattern
5815 is very similar to the @code{return} instruction pattern, but it is emitted
5816 only by the shrink-wrapping optimization on paths where the function
5817 prologue has not been executed, and a function return should occur without
5818 any of the effects of the epilogue. Additional uses may be introduced on
5819 paths where both the prologue and the epilogue have executed.
5821 @findex reload_completed
5822 @findex leaf_function_p
5823 For such machines, the condition specified in this pattern should only
5824 be true when @code{reload_completed} is nonzero and the function's
5825 epilogue would only be a single instruction. For machines with register
5826 windows, the routine @code{leaf_function_p} may be used to determine if
5827 a register window push is required.
5829 Machines that have conditional return instructions should define patterns
5835 (if_then_else (match_operator
5836 0 "comparison_operator"
5837 [(cc0) (const_int 0)])
5844 where @var{condition} would normally be the same condition specified on the
5845 named @samp{return} pattern.
5847 @cindex @code{untyped_return} instruction pattern
5848 @item @samp{untyped_return}
5849 Untyped subroutine return instruction. This instruction pattern should
5850 be defined to support @code{__builtin_return} on machines where special
5851 instructions are needed to return a value of any type.
5853 Operand 0 is a memory location where the result of calling a function
5854 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5855 expression where each element is a @code{set} expression that indicates
5856 the restoring of a function return value from the result block.
5858 @cindex @code{nop} instruction pattern
5860 No-op instruction. This instruction pattern name should always be defined
5861 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5864 @cindex @code{indirect_jump} instruction pattern
5865 @item @samp{indirect_jump}
5866 An instruction to jump to an address which is operand zero.
5867 This pattern name is mandatory on all machines.
5869 @cindex @code{casesi} instruction pattern
5871 Instruction to jump through a dispatch table, including bounds checking.
5872 This instruction takes five operands:
5876 The index to dispatch on, which has mode @code{SImode}.
5879 The lower bound for indices in the table, an integer constant.
5882 The total range of indices in the table---the largest index
5883 minus the smallest one (both inclusive).
5886 A label that precedes the table itself.
5889 A label to jump to if the index has a value outside the bounds.
5892 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5893 @code{jump_table_data}. The number of elements in the table is one plus the
5894 difference between the upper bound and the lower bound.
5896 @cindex @code{tablejump} instruction pattern
5897 @item @samp{tablejump}
5898 Instruction to jump to a variable address. This is a low-level
5899 capability which can be used to implement a dispatch table when there
5900 is no @samp{casesi} pattern.
5902 This pattern requires two operands: the address or offset, and a label
5903 which should immediately precede the jump table. If the macro
5904 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5905 operand is an offset which counts from the address of the table; otherwise,
5906 it is an absolute address to jump to. In either case, the first operand has
5909 The @samp{tablejump} insn is always the last insn before the jump
5910 table it uses. Its assembler code normally has no need to use the
5911 second operand, but you should incorporate it in the RTL pattern so
5912 that the jump optimizer will not delete the table as unreachable code.
5915 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5916 @item @samp{decrement_and_branch_until_zero}
5917 Conditional branch instruction that decrements a register and
5918 jumps if the register is nonzero. Operand 0 is the register to
5919 decrement and test; operand 1 is the label to jump to if the
5920 register is nonzero. @xref{Looping Patterns}.
5922 This optional instruction pattern is only used by the combiner,
5923 typically for loops reversed by the loop optimizer when strength
5924 reduction is enabled.
5926 @cindex @code{doloop_end} instruction pattern
5927 @item @samp{doloop_end}
5928 Conditional branch instruction that decrements a register and
5929 jumps if the register is nonzero. Operand 0 is the register to
5930 decrement and test; operand 1 is the label to jump to if the
5931 register is nonzero.
5932 @xref{Looping Patterns}.
5934 This optional instruction pattern should be defined for machines with
5935 low-overhead looping instructions as the loop optimizer will try to
5936 modify suitable loops to utilize it. The target hook
5937 @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which
5938 low-overhead loops can be used.
5940 @cindex @code{doloop_begin} instruction pattern
5941 @item @samp{doloop_begin}
5942 Companion instruction to @code{doloop_end} required for machines that
5943 need to perform some initialization, such as loading a special counter
5944 register. Operand 1 is the associated @code{doloop_end} pattern and
5945 operand 0 is the register that it decrements.
5947 If initialization insns do not always need to be emitted, use a
5948 @code{define_expand} (@pxref{Expander Definitions}) and make it fail.
5950 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5951 @item @samp{canonicalize_funcptr_for_compare}
5952 Canonicalize the function pointer in operand 1 and store the result
5955 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5956 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5957 and also has mode @code{Pmode}.
5959 Canonicalization of a function pointer usually involves computing
5960 the address of the function which would be called if the function
5961 pointer were used in an indirect call.
5963 Only define this pattern if function pointers on the target machine
5964 can have different values but still call the same function when
5965 used in an indirect call.
5967 @cindex @code{save_stack_block} instruction pattern
5968 @cindex @code{save_stack_function} instruction pattern
5969 @cindex @code{save_stack_nonlocal} instruction pattern
5970 @cindex @code{restore_stack_block} instruction pattern
5971 @cindex @code{restore_stack_function} instruction pattern
5972 @cindex @code{restore_stack_nonlocal} instruction pattern
5973 @item @samp{save_stack_block}
5974 @itemx @samp{save_stack_function}
5975 @itemx @samp{save_stack_nonlocal}
5976 @itemx @samp{restore_stack_block}
5977 @itemx @samp{restore_stack_function}
5978 @itemx @samp{restore_stack_nonlocal}
5979 Most machines save and restore the stack pointer by copying it to or
5980 from an object of mode @code{Pmode}. Do not define these patterns on
5983 Some machines require special handling for stack pointer saves and
5984 restores. On those machines, define the patterns corresponding to the
5985 non-standard cases by using a @code{define_expand} (@pxref{Expander
5986 Definitions}) that produces the required insns. The three types of
5987 saves and restores are:
5991 @samp{save_stack_block} saves the stack pointer at the start of a block
5992 that allocates a variable-sized object, and @samp{restore_stack_block}
5993 restores the stack pointer when the block is exited.
5996 @samp{save_stack_function} and @samp{restore_stack_function} do a
5997 similar job for the outermost block of a function and are used when the
5998 function allocates variable-sized objects or calls @code{alloca}. Only
5999 the epilogue uses the restored stack pointer, allowing a simpler save or
6000 restore sequence on some machines.
6003 @samp{save_stack_nonlocal} is used in functions that contain labels
6004 branched to by nested functions. It saves the stack pointer in such a
6005 way that the inner function can use @samp{restore_stack_nonlocal} to
6006 restore the stack pointer. The compiler generates code to restore the
6007 frame and argument pointer registers, but some machines require saving
6008 and restoring additional data such as register window information or
6009 stack backchains. Place insns in these patterns to save and restore any
6013 When saving the stack pointer, operand 0 is the save area and operand 1
6014 is the stack pointer. The mode used to allocate the save area defaults
6015 to @code{Pmode} but you can override that choice by defining the
6016 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
6017 specify an integral mode, or @code{VOIDmode} if no save area is needed
6018 for a particular type of save (either because no save is needed or
6019 because a machine-specific save area can be used). Operand 0 is the
6020 stack pointer and operand 1 is the save area for restore operations. If
6021 @samp{save_stack_block} is defined, operand 0 must not be
6022 @code{VOIDmode} since these saves can be arbitrarily nested.
6024 A save area is a @code{mem} that is at a constant offset from
6025 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
6026 nonlocal gotos and a @code{reg} in the other two cases.
6028 @cindex @code{allocate_stack} instruction pattern
6029 @item @samp{allocate_stack}
6030 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
6031 the stack pointer to create space for dynamically allocated data.
6033 Store the resultant pointer to this space into operand 0. If you
6034 are allocating space from the main stack, do this by emitting a
6035 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
6036 If you are allocating the space elsewhere, generate code to copy the
6037 location of the space to operand 0. In the latter case, you must
6038 ensure this space gets freed when the corresponding space on the main
6041 Do not define this pattern if all that must be done is the subtraction.
6042 Some machines require other operations such as stack probes or
6043 maintaining the back chain. Define this pattern to emit those
6044 operations in addition to updating the stack pointer.
6046 @cindex @code{check_stack} instruction pattern
6047 @item @samp{check_stack}
6048 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
6049 probing the stack, define this pattern to perform the needed check and signal
6050 an error if the stack has overflowed. The single operand is the address in
6051 the stack farthest from the current stack pointer that you need to validate.
6052 Normally, on platforms where this pattern is needed, you would obtain the
6053 stack limit from a global or thread-specific variable or register.
6055 @cindex @code{probe_stack_address} instruction pattern
6056 @item @samp{probe_stack_address}
6057 If stack checking (@pxref{Stack Checking}) can be done on your system by
6058 probing the stack but without the need to actually access it, define this
6059 pattern and signal an error if the stack has overflowed. The single operand
6060 is the memory address in the stack that needs to be probed.
6062 @cindex @code{probe_stack} instruction pattern
6063 @item @samp{probe_stack}
6064 If stack checking (@pxref{Stack Checking}) can be done on your system by
6065 probing the stack but doing it with a ``store zero'' instruction is not valid
6066 or optimal, define this pattern to do the probing differently and signal an
6067 error if the stack has overflowed. The single operand is the memory reference
6068 in the stack that needs to be probed.
6070 @cindex @code{nonlocal_goto} instruction pattern
6071 @item @samp{nonlocal_goto}
6072 Emit code to generate a non-local goto, e.g., a jump from one function
6073 to a label in an outer function. This pattern has four arguments,
6074 each representing a value to be used in the jump. The first
6075 argument is to be loaded into the frame pointer, the second is
6076 the address to branch to (code to dispatch to the actual label),
6077 the third is the address of a location where the stack is saved,
6078 and the last is the address of the label, to be placed in the
6079 location for the incoming static chain.
6081 On most machines you need not define this pattern, since GCC will
6082 already generate the correct code, which is to load the frame pointer
6083 and static chain, restore the stack (using the
6084 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
6085 to the dispatcher. You need only define this pattern if this code will
6086 not work on your machine.
6088 @cindex @code{nonlocal_goto_receiver} instruction pattern
6089 @item @samp{nonlocal_goto_receiver}
6090 This pattern, if defined, contains code needed at the target of a
6091 nonlocal goto after the code already generated by GCC@. You will not
6092 normally need to define this pattern. A typical reason why you might
6093 need this pattern is if some value, such as a pointer to a global table,
6094 must be restored when the frame pointer is restored. Note that a nonlocal
6095 goto only occurs within a unit-of-translation, so a global table pointer
6096 that is shared by all functions of a given module need not be restored.
6097 There are no arguments.
6099 @cindex @code{exception_receiver} instruction pattern
6100 @item @samp{exception_receiver}
6101 This pattern, if defined, contains code needed at the site of an
6102 exception handler that isn't needed at the site of a nonlocal goto. You
6103 will not normally need to define this pattern. A typical reason why you
6104 might need this pattern is if some value, such as a pointer to a global
6105 table, must be restored after control flow is branched to the handler of
6106 an exception. There are no arguments.
6108 @cindex @code{builtin_setjmp_setup} instruction pattern
6109 @item @samp{builtin_setjmp_setup}
6110 This pattern, if defined, contains additional code needed to initialize
6111 the @code{jmp_buf}. You will not normally need to define this pattern.
6112 A typical reason why you might need this pattern is if some value, such
6113 as a pointer to a global table, must be restored. Though it is
6114 preferred that the pointer value be recalculated if possible (given the
6115 address of a label for instance). The single argument is a pointer to
6116 the @code{jmp_buf}. Note that the buffer is five words long and that
6117 the first three are normally used by the generic mechanism.
6119 @cindex @code{builtin_setjmp_receiver} instruction pattern
6120 @item @samp{builtin_setjmp_receiver}
6121 This pattern, if defined, contains code needed at the site of a
6122 built-in setjmp that isn't needed at the site of a nonlocal goto. You
6123 will not normally need to define this pattern. A typical reason why you
6124 might need this pattern is if some value, such as a pointer to a global
6125 table, must be restored. It takes one argument, which is the label
6126 to which builtin_longjmp transferred control; this pattern may be emitted
6127 at a small offset from that label.
6129 @cindex @code{builtin_longjmp} instruction pattern
6130 @item @samp{builtin_longjmp}
6131 This pattern, if defined, performs the entire action of the longjmp.
6132 You will not normally need to define this pattern unless you also define
6133 @code{builtin_setjmp_setup}. The single argument is a pointer to the
6136 @cindex @code{eh_return} instruction pattern
6137 @item @samp{eh_return}
6138 This pattern, if defined, affects the way @code{__builtin_eh_return},
6139 and thence the call frame exception handling library routines, are
6140 built. It is intended to handle non-trivial actions needed along
6141 the abnormal return path.
6143 The address of the exception handler to which the function should return
6144 is passed as operand to this pattern. It will normally need to copied by
6145 the pattern to some special register or memory location.
6146 If the pattern needs to determine the location of the target call
6147 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
6148 if defined; it will have already been assigned.
6150 If this pattern is not defined, the default action will be to simply
6151 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
6152 that macro or this pattern needs to be defined if call frame exception
6153 handling is to be used.
6155 @cindex @code{prologue} instruction pattern
6156 @anchor{prologue instruction pattern}
6157 @item @samp{prologue}
6158 This pattern, if defined, emits RTL for entry to a function. The function
6159 entry is responsible for setting up the stack frame, initializing the frame
6160 pointer register, saving callee saved registers, etc.
6162 Using a prologue pattern is generally preferred over defining
6163 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
6165 The @code{prologue} pattern is particularly useful for targets which perform
6166 instruction scheduling.
6168 @cindex @code{window_save} instruction pattern
6169 @anchor{window_save instruction pattern}
6170 @item @samp{window_save}
6171 This pattern, if defined, emits RTL for a register window save. It should
6172 be defined if the target machine has register windows but the window events
6173 are decoupled from calls to subroutines. The canonical example is the SPARC
6176 @cindex @code{epilogue} instruction pattern
6177 @anchor{epilogue instruction pattern}
6178 @item @samp{epilogue}
6179 This pattern emits RTL for exit from a function. The function
6180 exit is responsible for deallocating the stack frame, restoring callee saved
6181 registers and emitting the return instruction.
6183 Using an epilogue pattern is generally preferred over defining
6184 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
6186 The @code{epilogue} pattern is particularly useful for targets which perform
6187 instruction scheduling or which have delay slots for their return instruction.
6189 @cindex @code{sibcall_epilogue} instruction pattern
6190 @item @samp{sibcall_epilogue}
6191 This pattern, if defined, emits RTL for exit from a function without the final
6192 branch back to the calling function. This pattern will be emitted before any
6193 sibling call (aka tail call) sites.
6195 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
6196 parameter passing or any stack slots for arguments passed to the current
6199 @cindex @code{trap} instruction pattern
6201 This pattern, if defined, signals an error, typically by causing some
6202 kind of signal to be raised. Among other places, it is used by the Java
6203 front end to signal `invalid array index' exceptions.
6205 @cindex @code{ctrap@var{MM}4} instruction pattern
6206 @item @samp{ctrap@var{MM}4}
6207 Conditional trap instruction. Operand 0 is a piece of RTL which
6208 performs a comparison, and operands 1 and 2 are the arms of the
6209 comparison. Operand 3 is the trap code, an integer.
6211 A typical @code{ctrap} pattern looks like
6214 (define_insn "ctrapsi4"
6215 [(trap_if (match_operator 0 "trap_operator"
6216 [(match_operand 1 "register_operand")
6217 (match_operand 2 "immediate_operand")])
6218 (match_operand 3 "const_int_operand" "i"))]
6223 @cindex @code{prefetch} instruction pattern
6224 @item @samp{prefetch}
6226 This pattern, if defined, emits code for a non-faulting data prefetch
6227 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
6228 is a constant 1 if the prefetch is preparing for a write to the memory
6229 address, or a constant 0 otherwise. Operand 2 is the expected degree of
6230 temporal locality of the data and is a value between 0 and 3, inclusive; 0
6231 means that the data has no temporal locality, so it need not be left in the
6232 cache after the access; 3 means that the data has a high degree of temporal
6233 locality and should be left in all levels of cache possible; 1 and 2 mean,
6234 respectively, a low or moderate degree of temporal locality.
6236 Targets that do not support write prefetches or locality hints can ignore
6237 the values of operands 1 and 2.
6239 @cindex @code{blockage} instruction pattern
6240 @item @samp{blockage}
6242 This pattern defines a pseudo insn that prevents the instruction
6243 scheduler and other passes from moving instructions and using register
6244 equivalences across the boundary defined by the blockage insn.
6245 This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM.
6247 @cindex @code{memory_barrier} instruction pattern
6248 @item @samp{memory_barrier}
6250 If the target memory model is not fully synchronous, then this pattern
6251 should be defined to an instruction that orders both loads and stores
6252 before the instruction with respect to loads and stores after the instruction.
6253 This pattern has no operands.
6255 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
6256 @item @samp{sync_compare_and_swap@var{mode}}
6258 This pattern, if defined, emits code for an atomic compare-and-swap
6259 operation. Operand 1 is the memory on which the atomic operation is
6260 performed. Operand 2 is the ``old'' value to be compared against the
6261 current contents of the memory location. Operand 3 is the ``new'' value
6262 to store in the memory if the compare succeeds. Operand 0 is the result
6263 of the operation; it should contain the contents of the memory
6264 before the operation. If the compare succeeds, this should obviously be
6265 a copy of operand 2.
6267 This pattern must show that both operand 0 and operand 1 are modified.
6269 This pattern must issue any memory barrier instructions such that all
6270 memory operations before the atomic operation occur before the atomic
6271 operation and all memory operations after the atomic operation occur
6272 after the atomic operation.
6274 For targets where the success or failure of the compare-and-swap
6275 operation is available via the status flags, it is possible to
6276 avoid a separate compare operation and issue the subsequent
6277 branch or store-flag operation immediately after the compare-and-swap.
6278 To this end, GCC will look for a @code{MODE_CC} set in the
6279 output of @code{sync_compare_and_swap@var{mode}}; if the machine
6280 description includes such a set, the target should also define special
6281 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
6282 be able to take the destination of the @code{MODE_CC} set and pass it
6283 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
6284 operand of the comparison (the second will be @code{(const_int 0)}).
6286 For targets where the operating system may provide support for this
6287 operation via library calls, the @code{sync_compare_and_swap_optab}
6288 may be initialized to a function with the same interface as the
6289 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
6290 set of @var{__sync} builtins are supported via library calls, the
6291 target can initialize all of the optabs at once with
6292 @code{init_sync_libfuncs}.
6293 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
6294 assumed that these library calls do @emph{not} use any kind of
6295 interruptable locking.
6297 @cindex @code{sync_add@var{mode}} instruction pattern
6298 @cindex @code{sync_sub@var{mode}} instruction pattern
6299 @cindex @code{sync_ior@var{mode}} instruction pattern
6300 @cindex @code{sync_and@var{mode}} instruction pattern
6301 @cindex @code{sync_xor@var{mode}} instruction pattern
6302 @cindex @code{sync_nand@var{mode}} instruction pattern
6303 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
6304 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
6305 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
6307 These patterns emit code for an atomic operation on memory.
6308 Operand 0 is the memory on which the atomic operation is performed.
6309 Operand 1 is the second operand to the binary operator.
6311 This pattern must issue any memory barrier instructions such that all
6312 memory operations before the atomic operation occur before the atomic
6313 operation and all memory operations after the atomic operation occur
6314 after the atomic operation.
6316 If these patterns are not defined, the operation will be constructed
6317 from a compare-and-swap operation, if defined.
6319 @cindex @code{sync_old_add@var{mode}} instruction pattern
6320 @cindex @code{sync_old_sub@var{mode}} instruction pattern
6321 @cindex @code{sync_old_ior@var{mode}} instruction pattern
6322 @cindex @code{sync_old_and@var{mode}} instruction pattern
6323 @cindex @code{sync_old_xor@var{mode}} instruction pattern
6324 @cindex @code{sync_old_nand@var{mode}} instruction pattern
6325 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
6326 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
6327 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
6329 These patterns emit code for an atomic operation on memory,
6330 and return the value that the memory contained before the operation.
6331 Operand 0 is the result value, operand 1 is the memory on which the
6332 atomic operation is performed, and operand 2 is the second operand
6333 to the binary operator.
6335 This pattern must issue any memory barrier instructions such that all
6336 memory operations before the atomic operation occur before the atomic
6337 operation and all memory operations after the atomic operation occur
6338 after the atomic operation.
6340 If these patterns are not defined, the operation will be constructed
6341 from a compare-and-swap operation, if defined.
6343 @cindex @code{sync_new_add@var{mode}} instruction pattern
6344 @cindex @code{sync_new_sub@var{mode}} instruction pattern
6345 @cindex @code{sync_new_ior@var{mode}} instruction pattern
6346 @cindex @code{sync_new_and@var{mode}} instruction pattern
6347 @cindex @code{sync_new_xor@var{mode}} instruction pattern
6348 @cindex @code{sync_new_nand@var{mode}} instruction pattern
6349 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
6350 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
6351 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
6353 These patterns are like their @code{sync_old_@var{op}} counterparts,
6354 except that they return the value that exists in the memory location
6355 after the operation, rather than before the operation.
6357 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
6358 @item @samp{sync_lock_test_and_set@var{mode}}
6360 This pattern takes two forms, based on the capabilities of the target.
6361 In either case, operand 0 is the result of the operand, operand 1 is
6362 the memory on which the atomic operation is performed, and operand 2
6363 is the value to set in the lock.
6365 In the ideal case, this operation is an atomic exchange operation, in
6366 which the previous value in memory operand is copied into the result
6367 operand, and the value operand is stored in the memory operand.
6369 For less capable targets, any value operand that is not the constant 1
6370 should be rejected with @code{FAIL}. In this case the target may use
6371 an atomic test-and-set bit operation. The result operand should contain
6372 1 if the bit was previously set and 0 if the bit was previously clear.
6373 The true contents of the memory operand are implementation defined.
6375 This pattern must issue any memory barrier instructions such that the
6376 pattern as a whole acts as an acquire barrier, that is all memory
6377 operations after the pattern do not occur until the lock is acquired.
6379 If this pattern is not defined, the operation will be constructed from
6380 a compare-and-swap operation, if defined.
6382 @cindex @code{sync_lock_release@var{mode}} instruction pattern
6383 @item @samp{sync_lock_release@var{mode}}
6385 This pattern, if defined, releases a lock set by
6386 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
6387 that contains the lock; operand 1 is the value to store in the lock.
6389 If the target doesn't implement full semantics for
6390 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
6391 the constant 0 should be rejected with @code{FAIL}, and the true contents
6392 of the memory operand are implementation defined.
6394 This pattern must issue any memory barrier instructions such that the
6395 pattern as a whole acts as a release barrier, that is the lock is
6396 released only after all previous memory operations have completed.
6398 If this pattern is not defined, then a @code{memory_barrier} pattern
6399 will be emitted, followed by a store of the value to the memory operand.
6401 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
6402 @item @samp{atomic_compare_and_swap@var{mode}}
6403 This pattern, if defined, emits code for an atomic compare-and-swap
6404 operation with memory model semantics. Operand 2 is the memory on which
6405 the atomic operation is performed. Operand 0 is an output operand which
6406 is set to true or false based on whether the operation succeeded. Operand
6407 1 is an output operand which is set to the contents of the memory before
6408 the operation was attempted. Operand 3 is the value that is expected to
6409 be in memory. Operand 4 is the value to put in memory if the expected
6410 value is found there. Operand 5 is set to 1 if this compare and swap is to
6411 be treated as a weak operation. Operand 6 is the memory model to be used
6412 if the operation is a success. Operand 7 is the memory model to be used
6413 if the operation fails.
6415 If memory referred to in operand 2 contains the value in operand 3, then
6416 operand 4 is stored in memory pointed to by operand 2 and fencing based on
6417 the memory model in operand 6 is issued.
6419 If memory referred to in operand 2 does not contain the value in operand 3,
6420 then fencing based on the memory model in operand 7 is issued.
6422 If a target does not support weak compare-and-swap operations, or the port
6423 elects not to implement weak operations, the argument in operand 5 can be
6424 ignored. Note a strong implementation must be provided.
6426 If this pattern is not provided, the @code{__atomic_compare_exchange}
6427 built-in functions will utilize the legacy @code{sync_compare_and_swap}
6428 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
6430 @cindex @code{atomic_load@var{mode}} instruction pattern
6431 @item @samp{atomic_load@var{mode}}
6432 This pattern implements an atomic load operation with memory model
6433 semantics. Operand 1 is the memory address being loaded from. Operand 0
6434 is the result of the load. Operand 2 is the memory model to be used for
6437 If not present, the @code{__atomic_load} built-in function will either
6438 resort to a normal load with memory barriers, or a compare-and-swap
6439 operation if a normal load would not be atomic.
6441 @cindex @code{atomic_store@var{mode}} instruction pattern
6442 @item @samp{atomic_store@var{mode}}
6443 This pattern implements an atomic store operation with memory model
6444 semantics. Operand 0 is the memory address being stored to. Operand 1
6445 is the value to be written. Operand 2 is the memory model to be used for
6448 If not present, the @code{__atomic_store} built-in function will attempt to
6449 perform a normal store and surround it with any required memory fences. If
6450 the store would not be atomic, then an @code{__atomic_exchange} is
6451 attempted with the result being ignored.
6453 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6454 @item @samp{atomic_exchange@var{mode}}
6455 This pattern implements an atomic exchange operation with memory model
6456 semantics. Operand 1 is the memory location the operation is performed on.
6457 Operand 0 is an output operand which is set to the original value contained
6458 in the memory pointed to by operand 1. Operand 2 is the value to be
6459 stored. Operand 3 is the memory model to be used.
6461 If this pattern is not present, the built-in function
6462 @code{__atomic_exchange} will attempt to preform the operation with a
6463 compare and swap loop.
6465 @cindex @code{atomic_add@var{mode}} instruction pattern
6466 @cindex @code{atomic_sub@var{mode}} instruction pattern
6467 @cindex @code{atomic_or@var{mode}} instruction pattern
6468 @cindex @code{atomic_and@var{mode}} instruction pattern
6469 @cindex @code{atomic_xor@var{mode}} instruction pattern
6470 @cindex @code{atomic_nand@var{mode}} instruction pattern
6471 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6472 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6473 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6475 These patterns emit code for an atomic operation on memory with memory
6476 model semantics. Operand 0 is the memory on which the atomic operation is
6477 performed. Operand 1 is the second operand to the binary operator.
6478 Operand 2 is the memory model to be used by the operation.
6480 If these patterns are not defined, attempts will be made to use legacy
6481 @code{sync} patterns, or equivalent patterns which return a result. If
6482 none of these are available a compare-and-swap loop will be used.
6484 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6485 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6486 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6487 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6488 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6489 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6490 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6491 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6492 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6494 These patterns emit code for an atomic operation on memory with memory
6495 model semantics, and return the original value. Operand 0 is an output
6496 operand which contains the value of the memory location before the
6497 operation was performed. Operand 1 is the memory on which the atomic
6498 operation is performed. Operand 2 is the second operand to the binary
6499 operator. Operand 3 is the memory model to be used by the operation.
6501 If these patterns are not defined, attempts will be made to use legacy
6502 @code{sync} patterns. If none of these are available a compare-and-swap
6505 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6506 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6507 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6508 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6509 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6510 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6511 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6512 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6513 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6515 These patterns emit code for an atomic operation on memory with memory
6516 model semantics and return the result after the operation is performed.
6517 Operand 0 is an output operand which contains the value after the
6518 operation. Operand 1 is the memory on which the atomic operation is
6519 performed. Operand 2 is the second operand to the binary operator.
6520 Operand 3 is the memory model to be used by the operation.
6522 If these patterns are not defined, attempts will be made to use legacy
6523 @code{sync} patterns, or equivalent patterns which return the result before
6524 the operation followed by the arithmetic operation required to produce the
6525 result. If none of these are available a compare-and-swap loop will be
6528 @cindex @code{atomic_test_and_set} instruction pattern
6529 @item @samp{atomic_test_and_set}
6531 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6532 Operand 0 is an output operand which is set to true if the previous
6533 previous contents of the byte was "set", and false otherwise. Operand 1
6534 is the @code{QImode} memory to be modified. Operand 2 is the memory
6537 The specific value that defines "set" is implementation defined, and
6538 is normally based on what is performed by the native atomic test and set
6541 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6542 @item @samp{mem_thread_fence@var{mode}}
6543 This pattern emits code required to implement a thread fence with
6544 memory model semantics. Operand 0 is the memory model to be used.
6546 If this pattern is not specified, all memory models except
6547 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6550 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6551 @item @samp{mem_signal_fence@var{mode}}
6552 This pattern emits code required to implement a signal fence with
6553 memory model semantics. Operand 0 is the memory model to be used.
6555 This pattern should impact the compiler optimizers the same way that
6556 mem_signal_fence does, but it does not need to issue any barrier
6559 If this pattern is not specified, all memory models except
6560 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6563 @cindex @code{get_thread_pointer@var{mode}} instruction pattern
6564 @cindex @code{set_thread_pointer@var{mode}} instruction pattern
6565 @item @samp{get_thread_pointer@var{mode}}
6566 @itemx @samp{set_thread_pointer@var{mode}}
6567 These patterns emit code that reads/sets the TLS thread pointer. Currently,
6568 these are only needed if the target needs to support the
6569 @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer}
6572 The get/set patterns have a single output/input operand respectively,
6573 with @var{mode} intended to be @code{Pmode}.
6575 @cindex @code{stack_protect_set} instruction pattern
6576 @item @samp{stack_protect_set}
6578 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6579 in operand 1 to the memory in operand 0 without leaving the value in
6580 a register afterward. This is to avoid leaking the value some place
6581 that an attacker might use to rewrite the stack guard slot after
6582 having clobbered it.
6584 If this pattern is not defined, then a plain move pattern is generated.
6586 @cindex @code{stack_protect_test} instruction pattern
6587 @item @samp{stack_protect_test}
6589 This pattern, if defined, compares a @code{ptr_mode} value from the
6590 memory in operand 1 with the memory in operand 0 without leaving the
6591 value in a register afterward and branches to operand 2 if the values
6594 If this pattern is not defined, then a plain compare pattern and
6595 conditional branch pattern is used.
6597 @cindex @code{clear_cache} instruction pattern
6598 @item @samp{clear_cache}
6600 This pattern, if defined, flushes the instruction cache for a region of
6601 memory. The region is bounded to by the Pmode pointers in operand 0
6602 inclusive and operand 1 exclusive.
6604 If this pattern is not defined, a call to the library function
6605 @code{__clear_cache} is used.
6610 @c Each of the following nodes are wrapped in separate
6611 @c "@ifset INTERNALS" to work around memory limits for the default
6612 @c configuration in older tetex distributions. Known to not work:
6613 @c tetex-1.0.7, known to work: tetex-2.0.2.
6615 @node Pattern Ordering
6616 @section When the Order of Patterns Matters
6617 @cindex Pattern Ordering
6618 @cindex Ordering of Patterns
6620 Sometimes an insn can match more than one instruction pattern. Then the
6621 pattern that appears first in the machine description is the one used.
6622 Therefore, more specific patterns (patterns that will match fewer things)
6623 and faster instructions (those that will produce better code when they
6624 do match) should usually go first in the description.
6626 In some cases the effect of ordering the patterns can be used to hide
6627 a pattern when it is not valid. For example, the 68000 has an
6628 instruction for converting a fullword to floating point and another
6629 for converting a byte to floating point. An instruction converting
6630 an integer to floating point could match either one. We put the
6631 pattern to convert the fullword first to make sure that one will
6632 be used rather than the other. (Otherwise a large integer might
6633 be generated as a single-byte immediate quantity, which would not work.)
6634 Instead of using this pattern ordering it would be possible to make the
6635 pattern for convert-a-byte smart enough to deal properly with any
6640 @node Dependent Patterns
6641 @section Interdependence of Patterns
6642 @cindex Dependent Patterns
6643 @cindex Interdependence of Patterns
6645 In some cases machines support instructions identical except for the
6646 machine mode of one or more operands. For example, there may be
6647 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6651 (set (match_operand:SI 0 @dots{})
6652 (extend:SI (match_operand:HI 1 @dots{})))
6654 (set (match_operand:SI 0 @dots{})
6655 (extend:SI (match_operand:QI 1 @dots{})))
6659 Constant integers do not specify a machine mode, so an instruction to
6660 extend a constant value could match either pattern. The pattern it
6661 actually will match is the one that appears first in the file. For correct
6662 results, this must be the one for the widest possible mode (@code{HImode},
6663 here). If the pattern matches the @code{QImode} instruction, the results
6664 will be incorrect if the constant value does not actually fit that mode.
6666 Such instructions to extend constants are rarely generated because they are
6667 optimized away, but they do occasionally happen in nonoptimized
6670 If a constraint in a pattern allows a constant, the reload pass may
6671 replace a register with a constant permitted by the constraint in some
6672 cases. Similarly for memory references. Because of this substitution,
6673 you should not provide separate patterns for increment and decrement
6674 instructions. Instead, they should be generated from the same pattern
6675 that supports register-register add insns by examining the operands and
6676 generating the appropriate machine instruction.
6681 @section Defining Jump Instruction Patterns
6682 @cindex jump instruction patterns
6683 @cindex defining jump instruction patterns
6685 GCC does not assume anything about how the machine realizes jumps.
6686 The machine description should define a single pattern, usually
6687 a @code{define_expand}, which expands to all the required insns.
6689 Usually, this would be a comparison insn to set the condition code
6690 and a separate branch insn testing the condition code and branching
6691 or not according to its value. For many machines, however,
6692 separating compares and branches is limiting, which is why the
6693 more flexible approach with one @code{define_expand} is used in GCC.
6694 The machine description becomes clearer for architectures that
6695 have compare-and-branch instructions but no condition code. It also
6696 works better when different sets of comparison operators are supported
6697 by different kinds of conditional branches (e.g. integer vs. floating-point),
6698 or by conditional branches with respect to conditional stores.
6700 Two separate insns are always used if the machine description represents
6701 a condition code register using the legacy RTL expression @code{(cc0)},
6702 and on most machines that use a separate condition code register
6703 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6704 fact, the set and use of the condition code must be separate and
6705 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6706 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6707 so that the comparison and branch insns could be located from each other
6708 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6710 Even in this case having a single entry point for conditional branches
6711 is advantageous, because it handles equally well the case where a single
6712 comparison instruction records the results of both signed and unsigned
6713 comparison of the given operands (with the branch insns coming in distinct
6714 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6715 there are distinct signed and unsigned compare instructions and only
6716 one set of conditional branch instructions as in the PowerPC.
6720 @node Looping Patterns
6721 @section Defining Looping Instruction Patterns
6722 @cindex looping instruction patterns
6723 @cindex defining looping instruction patterns
6725 Some machines have special jump instructions that can be utilized to
6726 make loops more efficient. A common example is the 68000 @samp{dbra}
6727 instruction which performs a decrement of a register and a branch if the
6728 result was greater than zero. Other machines, in particular digital
6729 signal processors (DSPs), have special block repeat instructions to
6730 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6731 DSPs have a block repeat instruction that loads special registers to
6732 mark the top and end of a loop and to count the number of loop
6733 iterations. This avoids the need for fetching and executing a
6734 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6737 GCC has three special named patterns to support low overhead looping.
6738 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6739 and @samp{doloop_end}. The first pattern,
6740 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6741 generation but may be emitted during the instruction combination phase.
6742 This requires the assistance of the loop optimizer, using information
6743 collected during strength reduction, to reverse a loop to count down to
6744 zero. Some targets also require the loop optimizer to add a
6745 @code{REG_NONNEG} note to indicate that the iteration count is always
6746 positive. This is needed if the target performs a signed loop
6747 termination test. For example, the 68000 uses a pattern similar to the
6748 following for its @code{dbra} instruction:
6752 (define_insn "decrement_and_branch_until_zero"
6755 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6758 (label_ref (match_operand 1 "" ""))
6761 (plus:SI (match_dup 0)
6763 "find_reg_note (insn, REG_NONNEG, 0)"
6768 Note that since the insn is both a jump insn and has an output, it must
6769 deal with its own reloads, hence the `m' constraints. Also note that
6770 since this insn is generated by the instruction combination phase
6771 combining two sequential insns together into an implicit parallel insn,
6772 the iteration counter needs to be biased by the same amount as the
6773 decrement operation, in this case @minus{}1. Note that the following similar
6774 pattern will not be matched by the combiner.
6778 (define_insn "decrement_and_branch_until_zero"
6781 (ge (match_operand:SI 0 "general_operand" "+d*am")
6783 (label_ref (match_operand 1 "" ""))
6786 (plus:SI (match_dup 0)
6788 "find_reg_note (insn, REG_NONNEG, 0)"
6793 The other two special looping patterns, @samp{doloop_begin} and
6794 @samp{doloop_end}, are emitted by the loop optimizer for certain
6795 well-behaved loops with a finite number of loop iterations using
6796 information collected during strength reduction.
6798 The @samp{doloop_end} pattern describes the actual looping instruction
6799 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6800 is an optional companion pattern that can be used for initialization
6801 needed for some low-overhead looping instructions.
6803 Note that some machines require the actual looping instruction to be
6804 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6805 the true RTL for a looping instruction at the top of the loop can cause
6806 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6807 emitted at the end of the loop. The machine dependent reorg pass checks
6808 for the presence of this @code{doloop} insn and then searches back to
6809 the top of the loop, where it inserts the true looping insn (provided
6810 there are no instructions in the loop which would cause problems). Any
6811 additional labels can be emitted at this point. In addition, if the
6812 desired special iteration counter register was not allocated, this
6813 machine dependent reorg pass could emit a traditional compare and jump
6816 The essential difference between the
6817 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6818 patterns is that the loop optimizer allocates an additional pseudo
6819 register for the latter as an iteration counter. This pseudo register
6820 cannot be used within the loop (i.e., general induction variables cannot
6821 be derived from it), however, in many cases the loop induction variable
6822 may become redundant and removed by the flow pass.
6827 @node Insn Canonicalizations
6828 @section Canonicalization of Instructions
6829 @cindex canonicalization of instructions
6830 @cindex insn canonicalization
6832 There are often cases where multiple RTL expressions could represent an
6833 operation performed by a single machine instruction. This situation is
6834 most commonly encountered with logical, branch, and multiply-accumulate
6835 instructions. In such cases, the compiler attempts to convert these
6836 multiple RTL expressions into a single canonical form to reduce the
6837 number of insn patterns required.
6839 In addition to algebraic simplifications, following canonicalizations
6844 For commutative and comparison operators, a constant is always made the
6845 second operand. If a machine only supports a constant as the second
6846 operand, only patterns that match a constant in the second operand need
6850 For associative operators, a sequence of operators will always chain
6851 to the left; for instance, only the left operand of an integer @code{plus}
6852 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6853 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6854 @code{umax} are associative when applied to integers, and sometimes to
6858 @cindex @code{neg}, canonicalization of
6859 @cindex @code{not}, canonicalization of
6860 @cindex @code{mult}, canonicalization of
6861 @cindex @code{plus}, canonicalization of
6862 @cindex @code{minus}, canonicalization of
6863 For these operators, if only one operand is a @code{neg}, @code{not},
6864 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6868 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6869 @code{minus}, the @code{neg} operations (if any) will be moved inside
6870 the operations as far as possible. For instance,
6871 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6872 @code{(plus (mult (neg B) C) A)} is canonicalized as
6873 @code{(minus A (mult B C))}.
6875 @cindex @code{compare}, canonicalization of
6877 For the @code{compare} operator, a constant is always the second operand
6878 if the first argument is a condition code register or @code{(cc0)}.
6881 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6882 @code{minus} is made the first operand under the same conditions as
6886 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6887 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6891 @code{(minus @var{x} (const_int @var{n}))} is converted to
6892 @code{(plus @var{x} (const_int @var{-n}))}.
6895 Within address computations (i.e., inside @code{mem}), a left shift is
6896 converted into the appropriate multiplication by a power of two.
6898 @cindex @code{ior}, canonicalization of
6899 @cindex @code{and}, canonicalization of
6900 @cindex De Morgan's law
6902 De Morgan's Law is used to move bitwise negation inside a bitwise
6903 logical-and or logical-or operation. If this results in only one
6904 operand being a @code{not} expression, it will be the first one.
6906 A machine that has an instruction that performs a bitwise logical-and of one
6907 operand with the bitwise negation of the other should specify the pattern
6908 for that instruction as
6912 [(set (match_operand:@var{m} 0 @dots{})
6913 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6914 (match_operand:@var{m} 2 @dots{})))]
6920 Similarly, a pattern for a ``NAND'' instruction should be written
6924 [(set (match_operand:@var{m} 0 @dots{})
6925 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6926 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6931 In both cases, it is not necessary to include patterns for the many
6932 logically equivalent RTL expressions.
6934 @cindex @code{xor}, canonicalization of
6936 The only possible RTL expressions involving both bitwise exclusive-or
6937 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6938 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6941 The sum of three items, one of which is a constant, will only appear in
6945 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6948 @cindex @code{zero_extract}, canonicalization of
6949 @cindex @code{sign_extract}, canonicalization of
6951 Equality comparisons of a group of bits (usually a single bit) with zero
6952 will be written using @code{zero_extract} rather than the equivalent
6953 @code{and} or @code{sign_extract} operations.
6955 @cindex @code{mult}, canonicalization of
6957 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6958 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6959 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6960 for @code{zero_extend}.
6963 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6964 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6965 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6966 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6967 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6968 operand of @code{mult} is also a shift, then that is extended also.
6969 This transformation is only applied when it can be proven that the
6970 original operation had sufficient precision to prevent overflow.
6974 Further canonicalization rules are defined in the function
6975 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6979 @node Expander Definitions
6980 @section Defining RTL Sequences for Code Generation
6981 @cindex expander definitions
6982 @cindex code generation RTL sequences
6983 @cindex defining RTL sequences for code generation
6985 On some target machines, some standard pattern names for RTL generation
6986 cannot be handled with single insn, but a sequence of RTL insns can
6987 represent them. For these target machines, you can write a
6988 @code{define_expand} to specify how to generate the sequence of RTL@.
6990 @findex define_expand
6991 A @code{define_expand} is an RTL expression that looks almost like a
6992 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6993 only for RTL generation and it can produce more than one RTL insn.
6995 A @code{define_expand} RTX has four operands:
6999 The name. Each @code{define_expand} must have a name, since the only
7000 use for it is to refer to it by name.
7003 The RTL template. This is a vector of RTL expressions representing
7004 a sequence of separate instructions. Unlike @code{define_insn}, there
7005 is no implicit surrounding @code{PARALLEL}.
7008 The condition, a string containing a C expression. This expression is
7009 used to express how the availability of this pattern depends on
7010 subclasses of target machine, selected by command-line options when GCC
7011 is run. This is just like the condition of a @code{define_insn} that
7012 has a standard name. Therefore, the condition (if present) may not
7013 depend on the data in the insn being matched, but only the
7014 target-machine-type flags. The compiler needs to test these conditions
7015 during initialization in order to learn exactly which named instructions
7016 are available in a particular run.
7019 The preparation statements, a string containing zero or more C
7020 statements which are to be executed before RTL code is generated from
7023 Usually these statements prepare temporary registers for use as
7024 internal operands in the RTL template, but they can also generate RTL
7025 insns directly by calling routines such as @code{emit_insn}, etc.
7026 Any such insns precede the ones that come from the RTL template.
7029 Optionally, a vector containing the values of attributes. @xref{Insn
7033 Every RTL insn emitted by a @code{define_expand} must match some
7034 @code{define_insn} in the machine description. Otherwise, the compiler
7035 will crash when trying to generate code for the insn or trying to optimize
7038 The RTL template, in addition to controlling generation of RTL insns,
7039 also describes the operands that need to be specified when this pattern
7040 is used. In particular, it gives a predicate for each operand.
7042 A true operand, which needs to be specified in order to generate RTL from
7043 the pattern, should be described with a @code{match_operand} in its first
7044 occurrence in the RTL template. This enters information on the operand's
7045 predicate into the tables that record such things. GCC uses the
7046 information to preload the operand into a register if that is required for
7047 valid RTL code. If the operand is referred to more than once, subsequent
7048 references should use @code{match_dup}.
7050 The RTL template may also refer to internal ``operands'' which are
7051 temporary registers or labels used only within the sequence made by the
7052 @code{define_expand}. Internal operands are substituted into the RTL
7053 template with @code{match_dup}, never with @code{match_operand}. The
7054 values of the internal operands are not passed in as arguments by the
7055 compiler when it requests use of this pattern. Instead, they are computed
7056 within the pattern, in the preparation statements. These statements
7057 compute the values and store them into the appropriate elements of
7058 @code{operands} so that @code{match_dup} can find them.
7060 There are two special macros defined for use in the preparation statements:
7061 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
7068 Use the @code{DONE} macro to end RTL generation for the pattern. The
7069 only RTL insns resulting from the pattern on this occasion will be
7070 those already emitted by explicit calls to @code{emit_insn} within the
7071 preparation statements; the RTL template will not be generated.
7075 Make the pattern fail on this occasion. When a pattern fails, it means
7076 that the pattern was not truly available. The calling routines in the
7077 compiler will try other strategies for code generation using other patterns.
7079 Failure is currently supported only for binary (addition, multiplication,
7080 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
7084 If the preparation falls through (invokes neither @code{DONE} nor
7085 @code{FAIL}), then the @code{define_expand} acts like a
7086 @code{define_insn} in that the RTL template is used to generate the
7089 The RTL template is not used for matching, only for generating the
7090 initial insn list. If the preparation statement always invokes
7091 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
7092 list of operands, such as this example:
7096 (define_expand "addsi3"
7097 [(match_operand:SI 0 "register_operand" "")
7098 (match_operand:SI 1 "register_operand" "")
7099 (match_operand:SI 2 "register_operand" "")]
7105 handle_add (operands[0], operands[1], operands[2]);
7111 Here is an example, the definition of left-shift for the SPUR chip:
7115 (define_expand "ashlsi3"
7116 [(set (match_operand:SI 0 "register_operand" "")
7120 (match_operand:SI 1 "register_operand" "")
7121 (match_operand:SI 2 "nonmemory_operand" "")))]
7130 if (GET_CODE (operands[2]) != CONST_INT
7131 || (unsigned) INTVAL (operands[2]) > 3)
7138 This example uses @code{define_expand} so that it can generate an RTL insn
7139 for shifting when the shift-count is in the supported range of 0 to 3 but
7140 fail in other cases where machine insns aren't available. When it fails,
7141 the compiler tries another strategy using different patterns (such as, a
7144 If the compiler were able to handle nontrivial condition-strings in
7145 patterns with names, then it would be possible to use a
7146 @code{define_insn} in that case. Here is another case (zero-extension
7147 on the 68000) which makes more use of the power of @code{define_expand}:
7150 (define_expand "zero_extendhisi2"
7151 [(set (match_operand:SI 0 "general_operand" "")
7153 (set (strict_low_part
7157 (match_operand:HI 1 "general_operand" ""))]
7159 "operands[1] = make_safe_from (operands[1], operands[0]);")
7163 @findex make_safe_from
7164 Here two RTL insns are generated, one to clear the entire output operand
7165 and the other to copy the input operand into its low half. This sequence
7166 is incorrect if the input operand refers to [the old value of] the output
7167 operand, so the preparation statement makes sure this isn't so. The
7168 function @code{make_safe_from} copies the @code{operands[1]} into a
7169 temporary register if it refers to @code{operands[0]}. It does this
7170 by emitting another RTL insn.
7172 Finally, a third example shows the use of an internal operand.
7173 Zero-extension on the SPUR chip is done by @code{and}-ing the result
7174 against a halfword mask. But this mask cannot be represented by a
7175 @code{const_int} because the constant value is too large to be legitimate
7176 on this machine. So it must be copied into a register with
7177 @code{force_reg} and then the register used in the @code{and}.
7180 (define_expand "zero_extendhisi2"
7181 [(set (match_operand:SI 0 "register_operand" "")
7183 (match_operand:HI 1 "register_operand" "")
7188 = force_reg (SImode, GEN_INT (65535)); ")
7191 @emph{Note:} If the @code{define_expand} is used to serve a
7192 standard binary or unary arithmetic operation or a bit-field operation,
7193 then the last insn it generates must not be a @code{code_label},
7194 @code{barrier} or @code{note}. It must be an @code{insn},
7195 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
7196 at the end, emit an insn to copy the result of the operation into
7197 itself. Such an insn will generate no code, but it can avoid problems
7202 @node Insn Splitting
7203 @section Defining How to Split Instructions
7204 @cindex insn splitting
7205 @cindex instruction splitting
7206 @cindex splitting instructions
7208 There are two cases where you should specify how to split a pattern
7209 into multiple insns. On machines that have instructions requiring
7210 delay slots (@pxref{Delay Slots}) or that have instructions whose
7211 output is not available for multiple cycles (@pxref{Processor pipeline
7212 description}), the compiler phases that optimize these cases need to
7213 be able to move insns into one-instruction delay slots. However, some
7214 insns may generate more than one machine instruction. These insns
7215 cannot be placed into a delay slot.
7217 Often you can rewrite the single insn as a list of individual insns,
7218 each corresponding to one machine instruction. The disadvantage of
7219 doing so is that it will cause the compilation to be slower and require
7220 more space. If the resulting insns are too complex, it may also
7221 suppress some optimizations. The compiler splits the insn if there is a
7222 reason to believe that it might improve instruction or delay slot
7225 The insn combiner phase also splits putative insns. If three insns are
7226 merged into one insn with a complex expression that cannot be matched by
7227 some @code{define_insn} pattern, the combiner phase attempts to split
7228 the complex pattern into two insns that are recognized. Usually it can
7229 break the complex pattern into two patterns by splitting out some
7230 subexpression. However, in some other cases, such as performing an
7231 addition of a large constant in two insns on a RISC machine, the way to
7232 split the addition into two insns is machine-dependent.
7234 @findex define_split
7235 The @code{define_split} definition tells the compiler how to split a
7236 complex insn into several simpler insns. It looks like this:
7240 [@var{insn-pattern}]
7242 [@var{new-insn-pattern-1}
7243 @var{new-insn-pattern-2}
7245 "@var{preparation-statements}")
7248 @var{insn-pattern} is a pattern that needs to be split and
7249 @var{condition} is the final condition to be tested, as in a
7250 @code{define_insn}. When an insn matching @var{insn-pattern} and
7251 satisfying @var{condition} is found, it is replaced in the insn list
7252 with the insns given by @var{new-insn-pattern-1},
7253 @var{new-insn-pattern-2}, etc.
7255 The @var{preparation-statements} are similar to those statements that
7256 are specified for @code{define_expand} (@pxref{Expander Definitions})
7257 and are executed before the new RTL is generated to prepare for the
7258 generated code or emit some insns whose pattern is not fixed. Unlike
7259 those in @code{define_expand}, however, these statements must not
7260 generate any new pseudo-registers. Once reload has completed, they also
7261 must not allocate any space in the stack frame.
7263 Patterns are matched against @var{insn-pattern} in two different
7264 circumstances. If an insn needs to be split for delay slot scheduling
7265 or insn scheduling, the insn is already known to be valid, which means
7266 that it must have been matched by some @code{define_insn} and, if
7267 @code{reload_completed} is nonzero, is known to satisfy the constraints
7268 of that @code{define_insn}. In that case, the new insn patterns must
7269 also be insns that are matched by some @code{define_insn} and, if
7270 @code{reload_completed} is nonzero, must also satisfy the constraints
7271 of those definitions.
7273 As an example of this usage of @code{define_split}, consider the following
7274 example from @file{a29k.md}, which splits a @code{sign_extend} from
7275 @code{HImode} to @code{SImode} into a pair of shift insns:
7279 [(set (match_operand:SI 0 "gen_reg_operand" "")
7280 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
7283 (ashift:SI (match_dup 1)
7286 (ashiftrt:SI (match_dup 0)
7289 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
7292 When the combiner phase tries to split an insn pattern, it is always the
7293 case that the pattern is @emph{not} matched by any @code{define_insn}.
7294 The combiner pass first tries to split a single @code{set} expression
7295 and then the same @code{set} expression inside a @code{parallel}, but
7296 followed by a @code{clobber} of a pseudo-reg to use as a scratch
7297 register. In these cases, the combiner expects exactly two new insn
7298 patterns to be generated. It will verify that these patterns match some
7299 @code{define_insn} definitions, so you need not do this test in the
7300 @code{define_split} (of course, there is no point in writing a
7301 @code{define_split} that will never produce insns that match).
7303 Here is an example of this use of @code{define_split}, taken from
7308 [(set (match_operand:SI 0 "gen_reg_operand" "")
7309 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
7310 (match_operand:SI 2 "non_add_cint_operand" "")))]
7312 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
7313 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
7316 int low = INTVAL (operands[2]) & 0xffff;
7317 int high = (unsigned) INTVAL (operands[2]) >> 16;
7320 high++, low |= 0xffff0000;
7322 operands[3] = GEN_INT (high << 16);
7323 operands[4] = GEN_INT (low);
7327 Here the predicate @code{non_add_cint_operand} matches any
7328 @code{const_int} that is @emph{not} a valid operand of a single add
7329 insn. The add with the smaller displacement is written so that it
7330 can be substituted into the address of a subsequent operation.
7332 An example that uses a scratch register, from the same file, generates
7333 an equality comparison of a register and a large constant:
7337 [(set (match_operand:CC 0 "cc_reg_operand" "")
7338 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
7339 (match_operand:SI 2 "non_short_cint_operand" "")))
7340 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
7341 "find_single_use (operands[0], insn, 0)
7342 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7343 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7344 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7345 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7348 /* @r{Get the constant we are comparing against, C, and see what it
7349 looks like sign-extended to 16 bits. Then see what constant
7350 could be XOR'ed with C to get the sign-extended value.} */
7352 int c = INTVAL (operands[2]);
7353 int sextc = (c << 16) >> 16;
7354 int xorv = c ^ sextc;
7356 operands[4] = GEN_INT (xorv);
7357 operands[5] = GEN_INT (sextc);
7361 To avoid confusion, don't write a single @code{define_split} that
7362 accepts some insns that match some @code{define_insn} as well as some
7363 insns that don't. Instead, write two separate @code{define_split}
7364 definitions, one for the insns that are valid and one for the insns that
7367 The splitter is allowed to split jump instructions into sequence of
7368 jumps or create new jumps in while splitting non-jump instructions. As
7369 the central flowgraph and branch prediction information needs to be updated,
7370 several restriction apply.
7372 Splitting of jump instruction into sequence that over by another jump
7373 instruction is always valid, as compiler expect identical behavior of new
7374 jump. When new sequence contains multiple jump instructions or new labels,
7375 more assistance is needed. Splitter is required to create only unconditional
7376 jumps, or simple conditional jump instructions. Additionally it must attach a
7377 @code{REG_BR_PROB} note to each conditional jump. A global variable
7378 @code{split_branch_probability} holds the probability of the original branch in case
7379 it was a simple conditional jump, @minus{}1 otherwise. To simplify
7380 recomputing of edge frequencies, the new sequence is required to have only
7381 forward jumps to the newly created labels.
7383 @findex define_insn_and_split
7384 For the common case where the pattern of a define_split exactly matches the
7385 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
7389 (define_insn_and_split
7390 [@var{insn-pattern}]
7392 "@var{output-template}"
7393 "@var{split-condition}"
7394 [@var{new-insn-pattern-1}
7395 @var{new-insn-pattern-2}
7397 "@var{preparation-statements}"
7398 [@var{insn-attributes}])
7402 @var{insn-pattern}, @var{condition}, @var{output-template}, and
7403 @var{insn-attributes} are used as in @code{define_insn}. The
7404 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
7405 in a @code{define_split}. The @var{split-condition} is also used as in
7406 @code{define_split}, with the additional behavior that if the condition starts
7407 with @samp{&&}, the condition used for the split will be the constructed as a
7408 logical ``and'' of the split condition with the insn condition. For example,
7412 (define_insn_and_split "zero_extendhisi2_and"
7413 [(set (match_operand:SI 0 "register_operand" "=r")
7414 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
7415 (clobber (reg:CC 17))]
7416 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
7418 "&& reload_completed"
7419 [(parallel [(set (match_dup 0)
7420 (and:SI (match_dup 0) (const_int 65535)))
7421 (clobber (reg:CC 17))])]
7423 [(set_attr "type" "alu1")])
7427 In this case, the actual split condition will be
7428 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
7430 The @code{define_insn_and_split} construction provides exactly the same
7431 functionality as two separate @code{define_insn} and @code{define_split}
7432 patterns. It exists for compactness, and as a maintenance tool to prevent
7433 having to ensure the two patterns' templates match.
7437 @node Including Patterns
7438 @section Including Patterns in Machine Descriptions.
7439 @cindex insn includes
7442 The @code{include} pattern tells the compiler tools where to
7443 look for patterns that are in files other than in the file
7444 @file{.md}. This is used only at build time and there is no preprocessing allowed.
7458 (include "filestuff")
7462 Where @var{pathname} is a string that specifies the location of the file,
7463 specifies the include file to be in @file{gcc/config/target/filestuff}. The
7464 directory @file{gcc/config/target} is regarded as the default directory.
7467 Machine descriptions may be split up into smaller more manageable subsections
7468 and placed into subdirectories.
7474 (include "BOGUS/filestuff")
7478 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7480 Specifying an absolute path for the include file such as;
7483 (include "/u2/BOGUS/filestuff")
7486 is permitted but is not encouraged.
7488 @subsection RTL Generation Tool Options for Directory Search
7489 @cindex directory options .md
7490 @cindex options, directory search
7491 @cindex search options
7493 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7498 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7503 Add the directory @var{dir} to the head of the list of directories to be
7504 searched for header files. This can be used to override a system machine definition
7505 file, substituting your own version, since these directories are
7506 searched before the default machine description file directories. If you use more than
7507 one @option{-I} option, the directories are scanned in left-to-right
7508 order; the standard default directory come after.
7513 @node Peephole Definitions
7514 @section Machine-Specific Peephole Optimizers
7515 @cindex peephole optimizer definitions
7516 @cindex defining peephole optimizers
7518 In addition to instruction patterns the @file{md} file may contain
7519 definitions of machine-specific peephole optimizations.
7521 The combiner does not notice certain peephole optimizations when the data
7522 flow in the program does not suggest that it should try them. For example,
7523 sometimes two consecutive insns related in purpose can be combined even
7524 though the second one does not appear to use a register computed in the
7525 first one. A machine-specific peephole optimizer can detect such
7528 There are two forms of peephole definitions that may be used. The
7529 original @code{define_peephole} is run at assembly output time to
7530 match insns and substitute assembly text. Use of @code{define_peephole}
7533 A newer @code{define_peephole2} matches insns and substitutes new
7534 insns. The @code{peephole2} pass is run after register allocation
7535 but before scheduling, which may result in much better code for
7536 targets that do scheduling.
7539 * define_peephole:: RTL to Text Peephole Optimizers
7540 * define_peephole2:: RTL to RTL Peephole Optimizers
7545 @node define_peephole
7546 @subsection RTL to Text Peephole Optimizers
7547 @findex define_peephole
7550 A definition looks like this:
7554 [@var{insn-pattern-1}
7555 @var{insn-pattern-2}
7559 "@var{optional-insn-attributes}")
7563 The last string operand may be omitted if you are not using any
7564 machine-specific information in this machine description. If present,
7565 it must obey the same rules as in a @code{define_insn}.
7567 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7568 consecutive insns. The optimization applies to a sequence of insns when
7569 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7570 the next, and so on.
7572 Each of the insns matched by a peephole must also match a
7573 @code{define_insn}. Peepholes are checked only at the last stage just
7574 before code generation, and only optionally. Therefore, any insn which
7575 would match a peephole but no @code{define_insn} will cause a crash in code
7576 generation in an unoptimized compilation, or at various optimization
7579 The operands of the insns are matched with @code{match_operands},
7580 @code{match_operator}, and @code{match_dup}, as usual. What is not
7581 usual is that the operand numbers apply to all the insn patterns in the
7582 definition. So, you can check for identical operands in two insns by
7583 using @code{match_operand} in one insn and @code{match_dup} in the
7586 The operand constraints used in @code{match_operand} patterns do not have
7587 any direct effect on the applicability of the peephole, but they will
7588 be validated afterward, so make sure your constraints are general enough
7589 to apply whenever the peephole matches. If the peephole matches
7590 but the constraints are not satisfied, the compiler will crash.
7592 It is safe to omit constraints in all the operands of the peephole; or
7593 you can write constraints which serve as a double-check on the criteria
7596 Once a sequence of insns matches the patterns, the @var{condition} is
7597 checked. This is a C expression which makes the final decision whether to
7598 perform the optimization (we do so if the expression is nonzero). If
7599 @var{condition} is omitted (in other words, the string is empty) then the
7600 optimization is applied to every sequence of insns that matches the
7603 The defined peephole optimizations are applied after register allocation
7604 is complete. Therefore, the peephole definition can check which
7605 operands have ended up in which kinds of registers, just by looking at
7608 @findex prev_active_insn
7609 The way to refer to the operands in @var{condition} is to write
7610 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7611 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7612 to refer to the last of the insns being matched; use
7613 @code{prev_active_insn} to find the preceding insns.
7615 @findex dead_or_set_p
7616 When optimizing computations with intermediate results, you can use
7617 @var{condition} to match only when the intermediate results are not used
7618 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7619 @var{op})}, where @var{insn} is the insn in which you expect the value
7620 to be used for the last time (from the value of @code{insn}, together
7621 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7622 value (from @code{operands[@var{i}]}).
7624 Applying the optimization means replacing the sequence of insns with one
7625 new insn. The @var{template} controls ultimate output of assembler code
7626 for this combined insn. It works exactly like the template of a
7627 @code{define_insn}. Operand numbers in this template are the same ones
7628 used in matching the original sequence of insns.
7630 The result of a defined peephole optimizer does not need to match any of
7631 the insn patterns in the machine description; it does not even have an
7632 opportunity to match them. The peephole optimizer definition itself serves
7633 as the insn pattern to control how the insn is output.
7635 Defined peephole optimizers are run as assembler code is being output,
7636 so the insns they produce are never combined or rearranged in any way.
7638 Here is an example, taken from the 68000 machine description:
7642 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7643 (set (match_operand:DF 0 "register_operand" "=f")
7644 (match_operand:DF 1 "register_operand" "ad"))]
7645 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7648 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7650 output_asm_insn ("move.l %1,(sp)", xoperands);
7651 output_asm_insn ("move.l %1,-(sp)", operands);
7652 return "fmove.d (sp)+,%0";
7654 output_asm_insn ("movel %1,sp@@", xoperands);
7655 output_asm_insn ("movel %1,sp@@-", operands);
7656 return "fmoved sp@@+,%0";
7662 The effect of this optimization is to change
7688 If a peephole matches a sequence including one or more jump insns, you must
7689 take account of the flags such as @code{CC_REVERSED} which specify that the
7690 condition codes are represented in an unusual manner. The compiler
7691 automatically alters any ordinary conditional jumps which occur in such
7692 situations, but the compiler cannot alter jumps which have been replaced by
7693 peephole optimizations. So it is up to you to alter the assembler code
7694 that the peephole produces. Supply C code to write the assembler output,
7695 and in this C code check the condition code status flags and change the
7696 assembler code as appropriate.
7699 @var{insn-pattern-1} and so on look @emph{almost} like the second
7700 operand of @code{define_insn}. There is one important difference: the
7701 second operand of @code{define_insn} consists of one or more RTX's
7702 enclosed in square brackets. Usually, there is only one: then the same
7703 action can be written as an element of a @code{define_peephole}. But
7704 when there are multiple actions in a @code{define_insn}, they are
7705 implicitly enclosed in a @code{parallel}. Then you must explicitly
7706 write the @code{parallel}, and the square brackets within it, in the
7707 @code{define_peephole}. Thus, if an insn pattern looks like this,
7710 (define_insn "divmodsi4"
7711 [(set (match_operand:SI 0 "general_operand" "=d")
7712 (div:SI (match_operand:SI 1 "general_operand" "0")
7713 (match_operand:SI 2 "general_operand" "dmsK")))
7714 (set (match_operand:SI 3 "general_operand" "=d")
7715 (mod:SI (match_dup 1) (match_dup 2)))]
7717 "divsl%.l %2,%3:%0")
7721 then the way to mention this insn in a peephole is as follows:
7727 [(set (match_operand:SI 0 "general_operand" "=d")
7728 (div:SI (match_operand:SI 1 "general_operand" "0")
7729 (match_operand:SI 2 "general_operand" "dmsK")))
7730 (set (match_operand:SI 3 "general_operand" "=d")
7731 (mod:SI (match_dup 1) (match_dup 2)))])
7738 @node define_peephole2
7739 @subsection RTL to RTL Peephole Optimizers
7740 @findex define_peephole2
7742 The @code{define_peephole2} definition tells the compiler how to
7743 substitute one sequence of instructions for another sequence,
7744 what additional scratch registers may be needed and what their
7749 [@var{insn-pattern-1}
7750 @var{insn-pattern-2}
7753 [@var{new-insn-pattern-1}
7754 @var{new-insn-pattern-2}
7756 "@var{preparation-statements}")
7759 The definition is almost identical to @code{define_split}
7760 (@pxref{Insn Splitting}) except that the pattern to match is not a
7761 single instruction, but a sequence of instructions.
7763 It is possible to request additional scratch registers for use in the
7764 output template. If appropriate registers are not free, the pattern
7765 will simply not match.
7767 @findex match_scratch
7769 Scratch registers are requested with a @code{match_scratch} pattern at
7770 the top level of the input pattern. The allocated register (initially) will
7771 be dead at the point requested within the original sequence. If the scratch
7772 is used at more than a single point, a @code{match_dup} pattern at the
7773 top level of the input pattern marks the last position in the input sequence
7774 at which the register must be available.
7776 Here is an example from the IA-32 machine description:
7780 [(match_scratch:SI 2 "r")
7781 (parallel [(set (match_operand:SI 0 "register_operand" "")
7782 (match_operator:SI 3 "arith_or_logical_operator"
7784 (match_operand:SI 1 "memory_operand" "")]))
7785 (clobber (reg:CC 17))])]
7786 "! optimize_size && ! TARGET_READ_MODIFY"
7787 [(set (match_dup 2) (match_dup 1))
7788 (parallel [(set (match_dup 0)
7789 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7790 (clobber (reg:CC 17))])]
7795 This pattern tries to split a load from its use in the hopes that we'll be
7796 able to schedule around the memory load latency. It allocates a single
7797 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7798 to be live only at the point just before the arithmetic.
7800 A real example requiring extended scratch lifetimes is harder to come by,
7801 so here's a silly made-up example:
7805 [(match_scratch:SI 4 "r")
7806 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7807 (set (match_operand:SI 2 "" "") (match_dup 1))
7809 (set (match_operand:SI 3 "" "") (match_dup 1))]
7810 "/* @r{determine 1 does not overlap 0 and 2} */"
7811 [(set (match_dup 4) (match_dup 1))
7812 (set (match_dup 0) (match_dup 4))
7813 (set (match_dup 2) (match_dup 4))
7814 (set (match_dup 3) (match_dup 4))]
7819 If we had not added the @code{(match_dup 4)} in the middle of the input
7820 sequence, it might have been the case that the register we chose at the
7821 beginning of the sequence is killed by the first or second @code{set}.
7825 @node Insn Attributes
7826 @section Instruction Attributes
7827 @cindex insn attributes
7828 @cindex instruction attributes
7830 In addition to describing the instruction supported by the target machine,
7831 the @file{md} file also defines a group of @dfn{attributes} and a set of
7832 values for each. Every generated insn is assigned a value for each attribute.
7833 One possible attribute would be the effect that the insn has on the machine's
7834 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7835 to track the condition codes.
7838 * Defining Attributes:: Specifying attributes and their values.
7839 * Expressions:: Valid expressions for attribute values.
7840 * Tagging Insns:: Assigning attribute values to insns.
7841 * Attr Example:: An example of assigning attributes.
7842 * Insn Lengths:: Computing the length of insns.
7843 * Constant Attributes:: Defining attributes that are constant.
7844 * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value.
7845 * Delay Slots:: Defining delay slots required for a machine.
7846 * Processor pipeline description:: Specifying information for insn scheduling.
7851 @node Defining Attributes
7852 @subsection Defining Attributes and their Values
7853 @cindex defining attributes and their values
7854 @cindex attributes, defining
7857 The @code{define_attr} expression is used to define each attribute required
7858 by the target machine. It looks like:
7861 (define_attr @var{name} @var{list-of-values} @var{default})
7864 @var{name} is a string specifying the name of the attribute being
7865 defined. Some attributes are used in a special way by the rest of the
7866 compiler. The @code{enabled} attribute can be used to conditionally
7867 enable or disable insn alternatives (@pxref{Disable Insn
7868 Alternatives}). The @code{predicable} attribute, together with a
7869 suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can
7870 be used to automatically generate conditional variants of instruction
7871 patterns. The @code{mnemonic} attribute can be used to check for the
7872 instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler
7873 internally uses the names @code{ce_enabled} and @code{nonce_enabled},
7874 so they should not be used elsewhere as alternative names.
7876 @var{list-of-values} is either a string that specifies a comma-separated
7877 list of values that can be assigned to the attribute, or a null string to
7878 indicate that the attribute takes numeric values.
7880 @var{default} is an attribute expression that gives the value of this
7881 attribute for insns that match patterns whose definition does not include
7882 an explicit value for this attribute. @xref{Attr Example}, for more
7883 information on the handling of defaults. @xref{Constant Attributes},
7884 for information on attributes that do not depend on any particular insn.
7887 For each defined attribute, a number of definitions are written to the
7888 @file{insn-attr.h} file. For cases where an explicit set of values is
7889 specified for an attribute, the following are defined:
7893 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7896 An enumerated class is defined for @samp{attr_@var{name}} with
7897 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7898 the attribute name and value are first converted to uppercase.
7901 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7902 returns the attribute value for that insn.
7905 For example, if the following is present in the @file{md} file:
7908 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7912 the following lines will be written to the file @file{insn-attr.h}.
7915 #define HAVE_ATTR_type 1
7916 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7917 TYPE_STORE, TYPE_ARITH@};
7918 extern enum attr_type get_attr_type ();
7921 If the attribute takes numeric values, no @code{enum} type will be
7922 defined and the function to obtain the attribute's value will return
7925 There are attributes which are tied to a specific meaning. These
7926 attributes are not free to use for other purposes:
7930 The @code{length} attribute is used to calculate the length of emitted
7931 code chunks. This is especially important when verifying branch
7932 distances. @xref{Insn Lengths}.
7935 The @code{enabled} attribute can be defined to prevent certain
7936 alternatives of an insn definition from being used during code
7937 generation. @xref{Disable Insn Alternatives}.
7940 The @code{mnemonic} attribute can be defined to implement instruction
7941 specific checks in e.g. the pipeline description.
7942 @xref{Mnemonic Attribute}.
7945 For each of these special attributes, the corresponding
7946 @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the
7947 attribute is not defined; in that case, it is defined as @samp{0}.
7949 @findex define_enum_attr
7950 @anchor{define_enum_attr}
7951 Another way of defining an attribute is to use:
7954 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7957 This works in just the same way as @code{define_attr}, except that
7958 the list of values is taken from a separate enumeration called
7959 @var{enum} (@pxref{define_enum}). This form allows you to use
7960 the same list of values for several attributes without having to
7961 repeat the list each time. For example:
7964 (define_enum "processor" [
7969 (define_enum_attr "arch" "processor"
7970 (const (symbol_ref "target_arch")))
7971 (define_enum_attr "tune" "processor"
7972 (const (symbol_ref "target_tune")))
7975 defines the same attributes as:
7978 (define_attr "arch" "model_a,model_b,@dots{}"
7979 (const (symbol_ref "target_arch")))
7980 (define_attr "tune" "model_a,model_b,@dots{}"
7981 (const (symbol_ref "target_tune")))
7984 but without duplicating the processor list. The second example defines two
7985 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7986 defines a single C enum (@code{processor}).
7990 @subsection Attribute Expressions
7991 @cindex attribute expressions
7993 RTL expressions used to define attributes use the codes described above
7994 plus a few specific to attribute definitions, to be discussed below.
7995 Attribute value expressions must have one of the following forms:
7998 @cindex @code{const_int} and attributes
7999 @item (const_int @var{i})
8000 The integer @var{i} specifies the value of a numeric attribute. @var{i}
8001 must be non-negative.
8003 The value of a numeric attribute can be specified either with a
8004 @code{const_int}, or as an integer represented as a string in
8005 @code{const_string}, @code{eq_attr} (see below), @code{attr},
8006 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
8007 overrides on specific instructions (@pxref{Tagging Insns}).
8009 @cindex @code{const_string} and attributes
8010 @item (const_string @var{value})
8011 The string @var{value} specifies a constant attribute value.
8012 If @var{value} is specified as @samp{"*"}, it means that the default value of
8013 the attribute is to be used for the insn containing this expression.
8014 @samp{"*"} obviously cannot be used in the @var{default} expression
8015 of a @code{define_attr}.
8017 If the attribute whose value is being specified is numeric, @var{value}
8018 must be a string containing a non-negative integer (normally
8019 @code{const_int} would be used in this case). Otherwise, it must
8020 contain one of the valid values for the attribute.
8022 @cindex @code{if_then_else} and attributes
8023 @item (if_then_else @var{test} @var{true-value} @var{false-value})
8024 @var{test} specifies an attribute test, whose format is defined below.
8025 The value of this expression is @var{true-value} if @var{test} is true,
8026 otherwise it is @var{false-value}.
8028 @cindex @code{cond} and attributes
8029 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
8030 The first operand of this expression is a vector containing an even
8031 number of expressions and consisting of pairs of @var{test} and @var{value}
8032 expressions. The value of the @code{cond} expression is that of the
8033 @var{value} corresponding to the first true @var{test} expression. If
8034 none of the @var{test} expressions are true, the value of the @code{cond}
8035 expression is that of the @var{default} expression.
8038 @var{test} expressions can have one of the following forms:
8041 @cindex @code{const_int} and attribute tests
8042 @item (const_int @var{i})
8043 This test is true if @var{i} is nonzero and false otherwise.
8045 @cindex @code{not} and attributes
8046 @cindex @code{ior} and attributes
8047 @cindex @code{and} and attributes
8048 @item (not @var{test})
8049 @itemx (ior @var{test1} @var{test2})
8050 @itemx (and @var{test1} @var{test2})
8051 These tests are true if the indicated logical function is true.
8053 @cindex @code{match_operand} and attributes
8054 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
8055 This test is true if operand @var{n} of the insn whose attribute value
8056 is being determined has mode @var{m} (this part of the test is ignored
8057 if @var{m} is @code{VOIDmode}) and the function specified by the string
8058 @var{pred} returns a nonzero value when passed operand @var{n} and mode
8059 @var{m} (this part of the test is ignored if @var{pred} is the null
8062 The @var{constraints} operand is ignored and should be the null string.
8064 @cindex @code{match_test} and attributes
8065 @item (match_test @var{c-expr})
8066 The test is true if C expression @var{c-expr} is true. In non-constant
8067 attributes, @var{c-expr} has access to the following variables:
8071 The rtl instruction under test.
8072 @item which_alternative
8073 The @code{define_insn} alternative that @var{insn} matches.
8074 @xref{Output Statement}.
8076 An array of @var{insn}'s rtl operands.
8079 @var{c-expr} behaves like the condition in a C @code{if} statement,
8080 so there is no need to explicitly convert the expression into a boolean
8081 0 or 1 value. For example, the following two tests are equivalent:
8084 (match_test "x & 2")
8085 (match_test "(x & 2) != 0")
8088 @cindex @code{le} and attributes
8089 @cindex @code{leu} and attributes
8090 @cindex @code{lt} and attributes
8091 @cindex @code{gt} and attributes
8092 @cindex @code{gtu} and attributes
8093 @cindex @code{ge} and attributes
8094 @cindex @code{geu} and attributes
8095 @cindex @code{ne} and attributes
8096 @cindex @code{eq} and attributes
8097 @cindex @code{plus} and attributes
8098 @cindex @code{minus} and attributes
8099 @cindex @code{mult} and attributes
8100 @cindex @code{div} and attributes
8101 @cindex @code{mod} and attributes
8102 @cindex @code{abs} and attributes
8103 @cindex @code{neg} and attributes
8104 @cindex @code{ashift} and attributes
8105 @cindex @code{lshiftrt} and attributes
8106 @cindex @code{ashiftrt} and attributes
8107 @item (le @var{arith1} @var{arith2})
8108 @itemx (leu @var{arith1} @var{arith2})
8109 @itemx (lt @var{arith1} @var{arith2})
8110 @itemx (ltu @var{arith1} @var{arith2})
8111 @itemx (gt @var{arith1} @var{arith2})
8112 @itemx (gtu @var{arith1} @var{arith2})
8113 @itemx (ge @var{arith1} @var{arith2})
8114 @itemx (geu @var{arith1} @var{arith2})
8115 @itemx (ne @var{arith1} @var{arith2})
8116 @itemx (eq @var{arith1} @var{arith2})
8117 These tests are true if the indicated comparison of the two arithmetic
8118 expressions is true. Arithmetic expressions are formed with
8119 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
8120 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
8121 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
8124 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
8125 Lengths},for additional forms). @code{symbol_ref} is a string
8126 denoting a C expression that yields an @code{int} when evaluated by the
8127 @samp{get_attr_@dots{}} routine. It should normally be a global
8131 @item (eq_attr @var{name} @var{value})
8132 @var{name} is a string specifying the name of an attribute.
8134 @var{value} is a string that is either a valid value for attribute
8135 @var{name}, a comma-separated list of values, or @samp{!} followed by a
8136 value or list. If @var{value} does not begin with a @samp{!}, this
8137 test is true if the value of the @var{name} attribute of the current
8138 insn is in the list specified by @var{value}. If @var{value} begins
8139 with a @samp{!}, this test is true if the attribute's value is
8140 @emph{not} in the specified list.
8145 (eq_attr "type" "load,store")
8152 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
8155 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
8156 value of the compiler variable @code{which_alternative}
8157 (@pxref{Output Statement}) and the values must be small integers. For
8161 (eq_attr "alternative" "2,3")
8168 (ior (eq (symbol_ref "which_alternative") (const_int 2))
8169 (eq (symbol_ref "which_alternative") (const_int 3)))
8172 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
8173 where the value of the attribute being tested is known for all insns matching
8174 a particular pattern. This is by far the most common case.
8177 @item (attr_flag @var{name})
8178 The value of an @code{attr_flag} expression is true if the flag
8179 specified by @var{name} is true for the @code{insn} currently being
8182 @var{name} is a string specifying one of a fixed set of flags to test.
8183 Test the flags @code{forward} and @code{backward} to determine the
8184 direction of a conditional branch.
8186 This example describes a conditional branch delay slot which
8187 can be nullified for forward branches that are taken (annul-true) or
8188 for backward branches which are not taken (annul-false).
8191 (define_delay (eq_attr "type" "cbranch")
8192 [(eq_attr "in_branch_delay" "true")
8193 (and (eq_attr "in_branch_delay" "true")
8194 (attr_flag "forward"))
8195 (and (eq_attr "in_branch_delay" "true")
8196 (attr_flag "backward"))])
8199 The @code{forward} and @code{backward} flags are false if the current
8200 @code{insn} being scheduled is not a conditional branch.
8202 @code{attr_flag} is only used during delay slot scheduling and has no
8203 meaning to other passes of the compiler.
8206 @item (attr @var{name})
8207 The value of another attribute is returned. This is most useful
8208 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
8209 produce more efficient code for non-numeric attributes.
8215 @subsection Assigning Attribute Values to Insns
8216 @cindex tagging insns
8217 @cindex assigning attribute values to insns
8219 The value assigned to an attribute of an insn is primarily determined by
8220 which pattern is matched by that insn (or which @code{define_peephole}
8221 generated it). Every @code{define_insn} and @code{define_peephole} can
8222 have an optional last argument to specify the values of attributes for
8223 matching insns. The value of any attribute not specified in a particular
8224 insn is set to the default value for that attribute, as specified in its
8225 @code{define_attr}. Extensive use of default values for attributes
8226 permits the specification of the values for only one or two attributes
8227 in the definition of most insn patterns, as seen in the example in the
8230 The optional last argument of @code{define_insn} and
8231 @code{define_peephole} is a vector of expressions, each of which defines
8232 the value for a single attribute. The most general way of assigning an
8233 attribute's value is to use a @code{set} expression whose first operand is an
8234 @code{attr} expression giving the name of the attribute being set. The
8235 second operand of the @code{set} is an attribute expression
8236 (@pxref{Expressions}) giving the value of the attribute.
8238 When the attribute value depends on the @samp{alternative} attribute
8239 (i.e., which is the applicable alternative in the constraint of the
8240 insn), the @code{set_attr_alternative} expression can be used. It
8241 allows the specification of a vector of attribute expressions, one for
8245 When the generality of arbitrary attribute expressions is not required,
8246 the simpler @code{set_attr} expression can be used, which allows
8247 specifying a string giving either a single attribute value or a list
8248 of attribute values, one for each alternative.
8250 The form of each of the above specifications is shown below. In each case,
8251 @var{name} is a string specifying the attribute to be set.
8254 @item (set_attr @var{name} @var{value-string})
8255 @var{value-string} is either a string giving the desired attribute value,
8256 or a string containing a comma-separated list giving the values for
8257 succeeding alternatives. The number of elements must match the number
8258 of alternatives in the constraint of the insn pattern.
8260 Note that it may be useful to specify @samp{*} for some alternative, in
8261 which case the attribute will assume its default value for insns matching
8264 @findex set_attr_alternative
8265 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
8266 Depending on the alternative of the insn, the value will be one of the
8267 specified values. This is a shorthand for using a @code{cond} with
8268 tests on the @samp{alternative} attribute.
8271 @item (set (attr @var{name}) @var{value})
8272 The first operand of this @code{set} must be the special RTL expression
8273 @code{attr}, whose sole operand is a string giving the name of the
8274 attribute being set. @var{value} is the value of the attribute.
8277 The following shows three different ways of representing the same
8278 attribute value specification:
8281 (set_attr "type" "load,store,arith")
8283 (set_attr_alternative "type"
8284 [(const_string "load") (const_string "store")
8285 (const_string "arith")])
8288 (cond [(eq_attr "alternative" "1") (const_string "load")
8289 (eq_attr "alternative" "2") (const_string "store")]
8290 (const_string "arith")))
8294 @findex define_asm_attributes
8295 The @code{define_asm_attributes} expression provides a mechanism to
8296 specify the attributes assigned to insns produced from an @code{asm}
8297 statement. It has the form:
8300 (define_asm_attributes [@var{attr-sets}])
8304 where @var{attr-sets} is specified the same as for both the
8305 @code{define_insn} and the @code{define_peephole} expressions.
8307 These values will typically be the ``worst case'' attribute values. For
8308 example, they might indicate that the condition code will be clobbered.
8310 A specification for a @code{length} attribute is handled specially. The
8311 way to compute the length of an @code{asm} insn is to multiply the
8312 length specified in the expression @code{define_asm_attributes} by the
8313 number of machine instructions specified in the @code{asm} statement,
8314 determined by counting the number of semicolons and newlines in the
8315 string. Therefore, the value of the @code{length} attribute specified
8316 in a @code{define_asm_attributes} should be the maximum possible length
8317 of a single machine instruction.
8322 @subsection Example of Attribute Specifications
8323 @cindex attribute specifications example
8324 @cindex attribute specifications
8326 The judicious use of defaulting is important in the efficient use of
8327 insn attributes. Typically, insns are divided into @dfn{types} and an
8328 attribute, customarily called @code{type}, is used to represent this
8329 value. This attribute is normally used only to define the default value
8330 for other attributes. An example will clarify this usage.
8332 Assume we have a RISC machine with a condition code and in which only
8333 full-word operations are performed in registers. Let us assume that we
8334 can divide all insns into loads, stores, (integer) arithmetic
8335 operations, floating point operations, and branches.
8337 Here we will concern ourselves with determining the effect of an insn on
8338 the condition code and will limit ourselves to the following possible
8339 effects: The condition code can be set unpredictably (clobbered), not
8340 be changed, be set to agree with the results of the operation, or only
8341 changed if the item previously set into the condition code has been
8344 Here is part of a sample @file{md} file for such a machine:
8347 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
8349 (define_attr "cc" "clobber,unchanged,set,change0"
8350 (cond [(eq_attr "type" "load")
8351 (const_string "change0")
8352 (eq_attr "type" "store,branch")
8353 (const_string "unchanged")
8354 (eq_attr "type" "arith")
8355 (if_then_else (match_operand:SI 0 "" "")
8356 (const_string "set")
8357 (const_string "clobber"))]
8358 (const_string "clobber")))
8361 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
8362 (match_operand:SI 1 "general_operand" "r,m,r"))]
8368 [(set_attr "type" "arith,load,store")])
8371 Note that we assume in the above example that arithmetic operations
8372 performed on quantities smaller than a machine word clobber the condition
8373 code since they will set the condition code to a value corresponding to the
8379 @subsection Computing the Length of an Insn
8380 @cindex insn lengths, computing
8381 @cindex computing the length of an insn
8383 For many machines, multiple types of branch instructions are provided, each
8384 for different length branch displacements. In most cases, the assembler
8385 will choose the correct instruction to use. However, when the assembler
8386 cannot do so, GCC can when a special attribute, the @code{length}
8387 attribute, is defined. This attribute must be defined to have numeric
8388 values by specifying a null string in its @code{define_attr}.
8390 In the case of the @code{length} attribute, two additional forms of
8391 arithmetic terms are allowed in test expressions:
8394 @cindex @code{match_dup} and attributes
8395 @item (match_dup @var{n})
8396 This refers to the address of operand @var{n} of the current insn, which
8397 must be a @code{label_ref}.
8399 @cindex @code{pc} and attributes
8401 This refers to the address of the @emph{current} insn. It might have
8402 been more consistent with other usage to make this the address of the
8403 @emph{next} insn but this would be confusing because the length of the
8404 current insn is to be computed.
8407 @cindex @code{addr_vec}, length of
8408 @cindex @code{addr_diff_vec}, length of
8409 For normal insns, the length will be determined by value of the
8410 @code{length} attribute. In the case of @code{addr_vec} and
8411 @code{addr_diff_vec} insn patterns, the length is computed as
8412 the number of vectors multiplied by the size of each vector.
8414 Lengths are measured in addressable storage units (bytes).
8416 The following macros can be used to refine the length computation:
8419 @findex ADJUST_INSN_LENGTH
8420 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
8421 If defined, modifies the length assigned to instruction @var{insn} as a
8422 function of the context in which it is used. @var{length} is an lvalue
8423 that contains the initially computed length of the insn and should be
8424 updated with the correct length of the insn.
8426 This macro will normally not be required. A case in which it is
8427 required is the ROMP@. On this machine, the size of an @code{addr_vec}
8428 insn must be increased by two to compensate for the fact that alignment
8432 @findex get_attr_length
8433 The routine that returns @code{get_attr_length} (the value of the
8434 @code{length} attribute) can be used by the output routine to
8435 determine the form of the branch instruction to be written, as the
8436 example below illustrates.
8438 As an example of the specification of variable-length branches, consider
8439 the IBM 360. If we adopt the convention that a register will be set to
8440 the starting address of a function, we can jump to labels within 4k of
8441 the start using a four-byte instruction. Otherwise, we need a six-byte
8442 sequence to load the address from memory and then branch to it.
8444 On such a machine, a pattern for a branch instruction might be specified
8450 (label_ref (match_operand 0 "" "")))]
8453 return (get_attr_length (insn) == 4
8454 ? "b %l0" : "l r15,=a(%l0); br r15");
8456 [(set (attr "length")
8457 (if_then_else (lt (match_dup 0) (const_int 4096))
8464 @node Constant Attributes
8465 @subsection Constant Attributes
8466 @cindex constant attributes
8468 A special form of @code{define_attr}, where the expression for the
8469 default value is a @code{const} expression, indicates an attribute that
8470 is constant for a given run of the compiler. Constant attributes may be
8471 used to specify which variety of processor is used. For example,
8474 (define_attr "cpu" "m88100,m88110,m88000"
8476 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8477 (symbol_ref "TARGET_88110") (const_string "m88110")]
8478 (const_string "m88000"))))
8480 (define_attr "memory" "fast,slow"
8482 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8483 (const_string "fast")
8484 (const_string "slow"))))
8487 The routine generated for constant attributes has no parameters as it
8488 does not depend on any particular insn. RTL expressions used to define
8489 the value of a constant attribute may use the @code{symbol_ref} form,
8490 but may not use either the @code{match_operand} form or @code{eq_attr}
8491 forms involving insn attributes.
8495 @node Mnemonic Attribute
8496 @subsection Mnemonic Attribute
8497 @cindex mnemonic attribute
8499 The @code{mnemonic} attribute is a string type attribute holding the
8500 instruction mnemonic for an insn alternative. The attribute values
8501 will automatically be generated by the machine description parser if
8502 there is an attribute definition in the md file:
8505 (define_attr "mnemonic" "unknown" (const_string "unknown"))
8508 The default value can be freely chosen as long as it does not collide
8509 with any of the instruction mnemonics. This value will be used
8510 whenever the machine description parser is not able to determine the
8511 mnemonic string. This might be the case for output templates
8512 containing more than a single instruction as in
8513 @code{"mvcle\t%0,%1,0\;jo\t.-4"}.
8515 The @code{mnemonic} attribute set is not generated automatically if the
8516 instruction string is generated via C code.
8518 An existing @code{mnemonic} attribute set in an insn definition will not
8519 be overriden by the md file parser. That way it is possible to
8520 manually set the instruction mnemonics for the cases where the md file
8521 parser fails to determine it automatically.
8523 The @code{mnemonic} attribute is useful for dealing with instruction
8524 specific properties in the pipeline description without defining
8525 additional insn attributes.
8528 (define_attr "ooo_expanded" ""
8529 (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr")
8537 @subsection Delay Slot Scheduling
8538 @cindex delay slots, defining
8540 The insn attribute mechanism can be used to specify the requirements for
8541 delay slots, if any, on a target machine. An instruction is said to
8542 require a @dfn{delay slot} if some instructions that are physically
8543 after the instruction are executed as if they were located before it.
8544 Classic examples are branch and call instructions, which often execute
8545 the following instruction before the branch or call is performed.
8547 On some machines, conditional branch instructions can optionally
8548 @dfn{annul} instructions in the delay slot. This means that the
8549 instruction will not be executed for certain branch outcomes. Both
8550 instructions that annul if the branch is true and instructions that
8551 annul if the branch is false are supported.
8553 Delay slot scheduling differs from instruction scheduling in that
8554 determining whether an instruction needs a delay slot is dependent only
8555 on the type of instruction being generated, not on data flow between the
8556 instructions. See the next section for a discussion of data-dependent
8557 instruction scheduling.
8559 @findex define_delay
8560 The requirement of an insn needing one or more delay slots is indicated
8561 via the @code{define_delay} expression. It has the following form:
8564 (define_delay @var{test}
8565 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8566 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8570 @var{test} is an attribute test that indicates whether this
8571 @code{define_delay} applies to a particular insn. If so, the number of
8572 required delay slots is determined by the length of the vector specified
8573 as the second argument. An insn placed in delay slot @var{n} must
8574 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8575 attribute test that specifies which insns may be annulled if the branch
8576 is true. Similarly, @var{annul-false-n} specifies which insns in the
8577 delay slot may be annulled if the branch is false. If annulling is not
8578 supported for that delay slot, @code{(nil)} should be coded.
8580 For example, in the common case where branch and call insns require
8581 a single delay slot, which may contain any insn other than a branch or
8582 call, the following would be placed in the @file{md} file:
8585 (define_delay (eq_attr "type" "branch,call")
8586 [(eq_attr "type" "!branch,call") (nil) (nil)])
8589 Multiple @code{define_delay} expressions may be specified. In this
8590 case, each such expression specifies different delay slot requirements
8591 and there must be no insn for which tests in two @code{define_delay}
8592 expressions are both true.
8594 For example, if we have a machine that requires one delay slot for branches
8595 but two for calls, no delay slot can contain a branch or call insn,
8596 and any valid insn in the delay slot for the branch can be annulled if the
8597 branch is true, we might represent this as follows:
8600 (define_delay (eq_attr "type" "branch")
8601 [(eq_attr "type" "!branch,call")
8602 (eq_attr "type" "!branch,call")
8605 (define_delay (eq_attr "type" "call")
8606 [(eq_attr "type" "!branch,call") (nil) (nil)
8607 (eq_attr "type" "!branch,call") (nil) (nil)])
8609 @c the above is *still* too long. --mew 4feb93
8613 @node Processor pipeline description
8614 @subsection Specifying processor pipeline description
8615 @cindex processor pipeline description
8616 @cindex processor functional units
8617 @cindex instruction latency time
8618 @cindex interlock delays
8619 @cindex data dependence delays
8620 @cindex reservation delays
8621 @cindex pipeline hazard recognizer
8622 @cindex automaton based pipeline description
8623 @cindex regular expressions
8624 @cindex deterministic finite state automaton
8625 @cindex automaton based scheduler
8629 To achieve better performance, most modern processors
8630 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8631 processors) have many @dfn{functional units} on which several
8632 instructions can be executed simultaneously. An instruction starts
8633 execution if its issue conditions are satisfied. If not, the
8634 instruction is stalled until its conditions are satisfied. Such
8635 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8636 of successor instructions (or demands nop instructions, e.g.@: for some
8639 There are two major kinds of interlock delays in modern processors.
8640 The first one is a data dependence delay determining @dfn{instruction
8641 latency time}. The instruction execution is not started until all
8642 source data have been evaluated by prior instructions (there are more
8643 complex cases when the instruction execution starts even when the data
8644 are not available but will be ready in given time after the
8645 instruction execution start). Taking the data dependence delays into
8646 account is simple. The data dependence (true, output, and
8647 anti-dependence) delay between two instructions is given by a
8648 constant. In most cases this approach is adequate. The second kind
8649 of interlock delays is a reservation delay. The reservation delay
8650 means that two instructions under execution will be in need of shared
8651 processors resources, i.e.@: buses, internal registers, and/or
8652 functional units, which are reserved for some time. Taking this kind
8653 of delay into account is complex especially for modern @acronym{RISC}
8656 The task of exploiting more processor parallelism is solved by an
8657 instruction scheduler. For a better solution to this problem, the
8658 instruction scheduler has to have an adequate description of the
8659 processor parallelism (or @dfn{pipeline description}). GCC
8660 machine descriptions describe processor parallelism and functional
8661 unit reservations for groups of instructions with the aid of
8662 @dfn{regular expressions}.
8664 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8665 figure out the possibility of the instruction issue by the processor
8666 on a given simulated processor cycle. The pipeline hazard recognizer is
8667 automatically generated from the processor pipeline description. The
8668 pipeline hazard recognizer generated from the machine description
8669 is based on a deterministic finite state automaton (@acronym{DFA}):
8670 the instruction issue is possible if there is a transition from one
8671 automaton state to another one. This algorithm is very fast, and
8672 furthermore, its speed is not dependent on processor
8673 complexity@footnote{However, the size of the automaton depends on
8674 processor complexity. To limit this effect, machine descriptions
8675 can split orthogonal parts of the machine description among several
8676 automata: but then, since each of these must be stepped independently,
8677 this does cause a small decrease in the algorithm's performance.}.
8679 @cindex automaton based pipeline description
8680 The rest of this section describes the directives that constitute
8681 an automaton-based processor pipeline description. The order of
8682 these constructions within the machine description file is not
8685 @findex define_automaton
8686 @cindex pipeline hazard recognizer
8687 The following optional construction describes names of automata
8688 generated and used for the pipeline hazards recognition. Sometimes
8689 the generated finite state automaton used by the pipeline hazard
8690 recognizer is large. If we use more than one automaton and bind functional
8691 units to the automata, the total size of the automata is usually
8692 less than the size of the single automaton. If there is no one such
8693 construction, only one finite state automaton is generated.
8696 (define_automaton @var{automata-names})
8699 @var{automata-names} is a string giving names of the automata. The
8700 names are separated by commas. All the automata should have unique names.
8701 The automaton name is used in the constructions @code{define_cpu_unit} and
8702 @code{define_query_cpu_unit}.
8704 @findex define_cpu_unit
8705 @cindex processor functional units
8706 Each processor functional unit used in the description of instruction
8707 reservations should be described by the following construction.
8710 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8713 @var{unit-names} is a string giving the names of the functional units
8714 separated by commas. Don't use name @samp{nothing}, it is reserved
8717 @var{automaton-name} is a string giving the name of the automaton with
8718 which the unit is bound. The automaton should be described in
8719 construction @code{define_automaton}. You should give
8720 @dfn{automaton-name}, if there is a defined automaton.
8722 The assignment of units to automata are constrained by the uses of the
8723 units in insn reservations. The most important constraint is: if a
8724 unit reservation is present on a particular cycle of an alternative
8725 for an insn reservation, then some unit from the same automaton must
8726 be present on the same cycle for the other alternatives of the insn
8727 reservation. The rest of the constraints are mentioned in the
8728 description of the subsequent constructions.
8730 @findex define_query_cpu_unit
8731 @cindex querying function unit reservations
8732 The following construction describes CPU functional units analogously
8733 to @code{define_cpu_unit}. The reservation of such units can be
8734 queried for an automaton state. The instruction scheduler never
8735 queries reservation of functional units for given automaton state. So
8736 as a rule, you don't need this construction. This construction could
8737 be used for future code generation goals (e.g.@: to generate
8738 @acronym{VLIW} insn templates).
8741 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8744 @var{unit-names} is a string giving names of the functional units
8745 separated by commas.
8747 @var{automaton-name} is a string giving the name of the automaton with
8748 which the unit is bound.
8750 @findex define_insn_reservation
8751 @cindex instruction latency time
8752 @cindex regular expressions
8754 The following construction is the major one to describe pipeline
8755 characteristics of an instruction.
8758 (define_insn_reservation @var{insn-name} @var{default_latency}
8759 @var{condition} @var{regexp})
8762 @var{default_latency} is a number giving latency time of the
8763 instruction. There is an important difference between the old
8764 description and the automaton based pipeline description. The latency
8765 time is used for all dependencies when we use the old description. In
8766 the automaton based pipeline description, the given latency time is only
8767 used for true dependencies. The cost of anti-dependencies is always
8768 zero and the cost of output dependencies is the difference between
8769 latency times of the producing and consuming insns (if the difference
8770 is negative, the cost is considered to be zero). You can always
8771 change the default costs for any description by using the target hook
8772 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8774 @var{insn-name} is a string giving the internal name of the insn. The
8775 internal names are used in constructions @code{define_bypass} and in
8776 the automaton description file generated for debugging. The internal
8777 name has nothing in common with the names in @code{define_insn}. It is a
8778 good practice to use insn classes described in the processor manual.
8780 @var{condition} defines what RTL insns are described by this
8781 construction. You should remember that you will be in trouble if
8782 @var{condition} for two or more different
8783 @code{define_insn_reservation} constructions is TRUE for an insn. In
8784 this case what reservation will be used for the insn is not defined.
8785 Such cases are not checked during generation of the pipeline hazards
8786 recognizer because in general recognizing that two conditions may have
8787 the same value is quite difficult (especially if the conditions
8788 contain @code{symbol_ref}). It is also not checked during the
8789 pipeline hazard recognizer work because it would slow down the
8790 recognizer considerably.
8792 @var{regexp} is a string describing the reservation of the cpu's functional
8793 units by the instruction. The reservations are described by a regular
8794 expression according to the following syntax:
8797 regexp = regexp "," oneof
8800 oneof = oneof "|" allof
8803 allof = allof "+" repeat
8806 repeat = element "*" number
8809 element = cpu_function_unit_name
8818 @samp{,} is used for describing the start of the next cycle in
8822 @samp{|} is used for describing a reservation described by the first
8823 regular expression @strong{or} a reservation described by the second
8824 regular expression @strong{or} etc.
8827 @samp{+} is used for describing a reservation described by the first
8828 regular expression @strong{and} a reservation described by the
8829 second regular expression @strong{and} etc.
8832 @samp{*} is used for convenience and simply means a sequence in which
8833 the regular expression are repeated @var{number} times with cycle
8834 advancing (see @samp{,}).
8837 @samp{cpu_function_unit_name} denotes reservation of the named
8841 @samp{reservation_name} --- see description of construction
8842 @samp{define_reservation}.
8845 @samp{nothing} denotes no unit reservations.
8848 @findex define_reservation
8849 Sometimes unit reservations for different insns contain common parts.
8850 In such case, you can simplify the pipeline description by describing
8851 the common part by the following construction
8854 (define_reservation @var{reservation-name} @var{regexp})
8857 @var{reservation-name} is a string giving name of @var{regexp}.
8858 Functional unit names and reservation names are in the same name
8859 space. So the reservation names should be different from the
8860 functional unit names and can not be the reserved name @samp{nothing}.
8862 @findex define_bypass
8863 @cindex instruction latency time
8865 The following construction is used to describe exceptions in the
8866 latency time for given instruction pair. This is so called bypasses.
8869 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8873 @var{number} defines when the result generated by the instructions
8874 given in string @var{out_insn_names} will be ready for the
8875 instructions given in string @var{in_insn_names}. Each of these
8876 strings is a comma-separated list of filename-style globs and
8877 they refer to the names of @code{define_insn_reservation}s.
8880 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8882 defines a bypass between instructions that start with
8883 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8886 @var{guard} is an optional string giving the name of a C function which
8887 defines an additional guard for the bypass. The function will get the
8888 two insns as parameters. If the function returns zero the bypass will
8889 be ignored for this case. The additional guard is necessary to
8890 recognize complicated bypasses, e.g.@: when the consumer is only an address
8891 of insn @samp{store} (not a stored value).
8893 If there are more one bypass with the same output and input insns, the
8894 chosen bypass is the first bypass with a guard in description whose
8895 guard function returns nonzero. If there is no such bypass, then
8896 bypass without the guard function is chosen.
8898 @findex exclusion_set
8899 @findex presence_set
8900 @findex final_presence_set
8902 @findex final_absence_set
8905 The following five constructions are usually used to describe
8906 @acronym{VLIW} processors, or more precisely, to describe a placement
8907 of small instructions into @acronym{VLIW} instruction slots. They
8908 can be used for @acronym{RISC} processors, too.
8911 (exclusion_set @var{unit-names} @var{unit-names})
8912 (presence_set @var{unit-names} @var{patterns})
8913 (final_presence_set @var{unit-names} @var{patterns})
8914 (absence_set @var{unit-names} @var{patterns})
8915 (final_absence_set @var{unit-names} @var{patterns})
8918 @var{unit-names} is a string giving names of functional units
8919 separated by commas.
8921 @var{patterns} is a string giving patterns of functional units
8922 separated by comma. Currently pattern is one unit or units
8923 separated by white-spaces.
8925 The first construction (@samp{exclusion_set}) means that each
8926 functional unit in the first string can not be reserved simultaneously
8927 with a unit whose name is in the second string and vice versa. For
8928 example, the construction is useful for describing processors
8929 (e.g.@: some SPARC processors) with a fully pipelined floating point
8930 functional unit which can execute simultaneously only single floating
8931 point insns or only double floating point insns.
8933 The second construction (@samp{presence_set}) means that each
8934 functional unit in the first string can not be reserved unless at
8935 least one of pattern of units whose names are in the second string is
8936 reserved. This is an asymmetric relation. For example, it is useful
8937 for description that @acronym{VLIW} @samp{slot1} is reserved after
8938 @samp{slot0} reservation. We could describe it by the following
8942 (presence_set "slot1" "slot0")
8945 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8946 reservation. In this case we could write
8949 (presence_set "slot1" "slot0 b0")
8952 The third construction (@samp{final_presence_set}) is analogous to
8953 @samp{presence_set}. The difference between them is when checking is
8954 done. When an instruction is issued in given automaton state
8955 reflecting all current and planned unit reservations, the automaton
8956 state is changed. The first state is a source state, the second one
8957 is a result state. Checking for @samp{presence_set} is done on the
8958 source state reservation, checking for @samp{final_presence_set} is
8959 done on the result reservation. This construction is useful to
8960 describe a reservation which is actually two subsequent reservations.
8961 For example, if we use
8964 (presence_set "slot1" "slot0")
8967 the following insn will be never issued (because @samp{slot1} requires
8968 @samp{slot0} which is absent in the source state).
8971 (define_reservation "insn_and_nop" "slot0 + slot1")
8974 but it can be issued if we use analogous @samp{final_presence_set}.
8976 The forth construction (@samp{absence_set}) means that each functional
8977 unit in the first string can be reserved only if each pattern of units
8978 whose names are in the second string is not reserved. This is an
8979 asymmetric relation (actually @samp{exclusion_set} is analogous to
8980 this one but it is symmetric). For example it might be useful in a
8981 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8982 after either @samp{slot1} or @samp{slot2} have been reserved. This
8983 can be described as:
8986 (absence_set "slot0" "slot1, slot2")
8989 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
8990 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8991 this case we could write
8994 (absence_set "slot2" "slot0 b0, slot1 b1")
8997 All functional units mentioned in a set should belong to the same
9000 The last construction (@samp{final_absence_set}) is analogous to
9001 @samp{absence_set} but checking is done on the result (state)
9002 reservation. See comments for @samp{final_presence_set}.
9004 @findex automata_option
9005 @cindex deterministic finite state automaton
9006 @cindex nondeterministic finite state automaton
9007 @cindex finite state automaton minimization
9008 You can control the generator of the pipeline hazard recognizer with
9009 the following construction.
9012 (automata_option @var{options})
9015 @var{options} is a string giving options which affect the generated
9016 code. Currently there are the following options:
9020 @dfn{no-minimization} makes no minimization of the automaton. This is
9021 only worth to do when we are debugging the description and need to
9022 look more accurately at reservations of states.
9025 @dfn{time} means printing time statistics about the generation of
9029 @dfn{stats} means printing statistics about the generated automata
9030 such as the number of DFA states, NDFA states and arcs.
9033 @dfn{v} means a generation of the file describing the result automata.
9034 The file has suffix @samp{.dfa} and can be used for the description
9035 verification and debugging.
9038 @dfn{w} means a generation of warning instead of error for
9039 non-critical errors.
9042 @dfn{no-comb-vect} prevents the automaton generator from generating
9043 two data structures and comparing them for space efficiency. Using
9044 a comb vector to represent transitions may be better, but it can be
9045 very expensive to construct. This option is useful if the build
9046 process spends an unacceptably long time in genautomata.
9049 @dfn{ndfa} makes nondeterministic finite state automata. This affects
9050 the treatment of operator @samp{|} in the regular expressions. The
9051 usual treatment of the operator is to try the first alternative and,
9052 if the reservation is not possible, the second alternative. The
9053 nondeterministic treatment means trying all alternatives, some of them
9054 may be rejected by reservations in the subsequent insns.
9057 @dfn{collapse-ndfa} modifies the behaviour of the generator when
9058 producing an automaton. An additional state transition to collapse a
9059 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
9060 state is generated. It can be triggered by passing @code{const0_rtx} to
9061 state_transition. In such an automaton, cycle advance transitions are
9062 available only for these collapsed states. This option is useful for
9063 ports that want to use the @code{ndfa} option, but also want to use
9064 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
9067 @dfn{progress} means output of a progress bar showing how many states
9068 were generated so far for automaton being processed. This is useful
9069 during debugging a @acronym{DFA} description. If you see too many
9070 generated states, you could interrupt the generator of the pipeline
9071 hazard recognizer and try to figure out a reason for generation of the
9075 As an example, consider a superscalar @acronym{RISC} machine which can
9076 issue three insns (two integer insns and one floating point insn) on
9077 the cycle but can finish only two insns. To describe this, we define
9078 the following functional units.
9081 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
9082 (define_cpu_unit "port0, port1")
9085 All simple integer insns can be executed in any integer pipeline and
9086 their result is ready in two cycles. The simple integer insns are
9087 issued into the first pipeline unless it is reserved, otherwise they
9088 are issued into the second pipeline. Integer division and
9089 multiplication insns can be executed only in the second integer
9090 pipeline and their results are ready correspondingly in 8 and 4
9091 cycles. The integer division is not pipelined, i.e.@: the subsequent
9092 integer division insn can not be issued until the current division
9093 insn finished. Floating point insns are fully pipelined and their
9094 results are ready in 3 cycles. Where the result of a floating point
9095 insn is used by an integer insn, an additional delay of one cycle is
9096 incurred. To describe all of this we could specify
9099 (define_cpu_unit "div")
9101 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9102 "(i0_pipeline | i1_pipeline), (port0 | port1)")
9104 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
9105 "i1_pipeline, nothing*2, (port0 | port1)")
9107 (define_insn_reservation "div" 8 (eq_attr "type" "div")
9108 "i1_pipeline, div*7, div + (port0 | port1)")
9110 (define_insn_reservation "float" 3 (eq_attr "type" "float")
9111 "f_pipeline, nothing, (port0 | port1))
9113 (define_bypass 4 "float" "simple,mult,div")
9116 To simplify the description we could describe the following reservation
9119 (define_reservation "finish" "port0|port1")
9122 and use it in all @code{define_insn_reservation} as in the following
9126 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
9127 "(i0_pipeline | i1_pipeline), finish")
9133 @node Conditional Execution
9134 @section Conditional Execution
9135 @cindex conditional execution
9138 A number of architectures provide for some form of conditional
9139 execution, or predication. The hallmark of this feature is the
9140 ability to nullify most of the instructions in the instruction set.
9141 When the instruction set is large and not entirely symmetric, it
9142 can be quite tedious to describe these forms directly in the
9143 @file{.md} file. An alternative is the @code{define_cond_exec} template.
9145 @findex define_cond_exec
9148 [@var{predicate-pattern}]
9150 "@var{output-template}"
9151 "@var{optional-insn-attribues}")
9154 @var{predicate-pattern} is the condition that must be true for the
9155 insn to be executed at runtime and should match a relational operator.
9156 One can use @code{match_operator} to match several relational operators
9157 at once. Any @code{match_operand} operands must have no more than one
9160 @var{condition} is a C expression that must be true for the generated
9163 @findex current_insn_predicate
9164 @var{output-template} is a string similar to the @code{define_insn}
9165 output template (@pxref{Output Template}), except that the @samp{*}
9166 and @samp{@@} special cases do not apply. This is only useful if the
9167 assembly text for the predicate is a simple prefix to the main insn.
9168 In order to handle the general case, there is a global variable
9169 @code{current_insn_predicate} that will contain the entire predicate
9170 if the current insn is predicated, and will otherwise be @code{NULL}.
9172 @var{optional-insn-attributes} is an optional vector of attributes that gets
9173 appended to the insn attributes of the produced cond_exec rtx. It can
9174 be used to add some distinguishing attribute to cond_exec rtxs produced
9175 that way. An example usage would be to use this attribute in conjunction
9176 with attributes on the main pattern to disable particular alternatives under
9179 When @code{define_cond_exec} is used, an implicit reference to
9180 the @code{predicable} instruction attribute is made.
9181 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
9182 exactly two elements in its @var{list-of-values}), with the possible
9183 values being @code{no} and @code{yes}. The default and all uses in
9184 the insns must be a simple constant, not a complex expressions. It
9185 may, however, depend on the alternative, by using a comma-separated
9186 list of values. If that is the case, the port should also define an
9187 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
9188 should also allow only @code{no} and @code{yes} as its values.
9190 For each @code{define_insn} for which the @code{predicable}
9191 attribute is true, a new @code{define_insn} pattern will be
9192 generated that matches a predicated version of the instruction.
9196 (define_insn "addsi"
9197 [(set (match_operand:SI 0 "register_operand" "r")
9198 (plus:SI (match_operand:SI 1 "register_operand" "r")
9199 (match_operand:SI 2 "register_operand" "r")))]
9204 [(ne (match_operand:CC 0 "register_operand" "c")
9211 generates a new pattern
9216 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
9217 (set (match_operand:SI 0 "register_operand" "r")
9218 (plus:SI (match_operand:SI 1 "register_operand" "r")
9219 (match_operand:SI 2 "register_operand" "r"))))]
9220 "(@var{test2}) && (@var{test1})"
9221 "(%3) add %2,%1,%0")
9227 @section RTL Templates Transformations
9228 @cindex define_subst
9230 For some hardware architectures there are common cases when the RTL
9231 templates for the instructions can be derived from the other RTL
9232 templates using simple transformations. E.g., @file{i386.md} contains
9233 an RTL template for the ordinary @code{sub} instruction---
9234 @code{*subsi_1}, and for the @code{sub} instruction with subsequent
9235 zero-extension---@code{*subsi_1_zext}. Such cases can be easily
9236 implemented by a single meta-template capable of generating a modified
9237 case based on the initial one:
9239 @findex define_subst
9241 (define_subst "@var{name}"
9242 [@var{input-template}]
9244 [@var{output-template}])
9246 @var{input-template} is a pattern describing the source RTL template,
9247 which will be transformed.
9249 @var{condition} is a C expression that is conjunct with the condition
9250 from the input-template to generate a condition to be used in the
9253 @var{output-template} is a pattern that will be used in the resulting
9256 @code{define_subst} mechanism is tightly coupled with the notion of the
9257 subst attribute (@pxref{Subst Iterators}). The use of
9258 @code{define_subst} is triggered by a reference to a subst attribute in
9259 the transforming RTL template. This reference initiates duplication of
9260 the source RTL template and substitution of the attributes with their
9261 values. The source RTL template is left unchanged, while the copy is
9262 transformed by @code{define_subst}. This transformation can fail in the
9263 case when the source RTL template is not matched against the
9264 input-template of the @code{define_subst}. In such case the copy is
9267 @code{define_subst} can be used only in @code{define_insn} and
9268 @code{define_expand}, it cannot be used in other expressions (e.g. in
9269 @code{define_insn_and_split}).
9272 * Define Subst Example:: Example of @code{define_subst} work.
9273 * Define Subst Pattern Matching:: Process of template comparison.
9274 * Define Subst Output Template:: Generation of output template.
9277 @node Define Subst Example
9278 @subsection @code{define_subst} Example
9279 @cindex define_subst
9281 To illustrate how @code{define_subst} works, let us examine a simple
9282 template transformation.
9284 Suppose there are two kinds of instructions: one that touches flags and
9285 the other that does not. The instructions of the second type could be
9286 generated with the following @code{define_subst}:
9289 (define_subst "add_clobber_subst"
9290 [(set (match_operand:SI 0 "" "")
9291 (match_operand:SI 1 "" ""))]
9295 (clobber (reg:CC FLAGS_REG))]
9298 This @code{define_subst} can be applied to any RTL pattern containing
9299 @code{set} of mode SI and generates a copy with clobber when it is
9302 Assume there is an RTL template for a @code{max} instruction to be used
9303 in @code{define_subst} mentioned above:
9306 (define_insn "maxsi"
9307 [(set (match_operand:SI 0 "register_operand" "=r")
9309 (match_operand:SI 1 "register_operand" "r")
9310 (match_operand:SI 2 "register_operand" "r")))]
9312 "max\t@{%2, %1, %0|%0, %1, %2@}"
9316 To mark the RTL template for @code{define_subst} application,
9317 subst-attributes are used. They should be declared in advance:
9320 (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber")
9323 Here @samp{add_clobber_name} is the attribute name,
9324 @samp{add_clobber_subst} is the name of the corresponding
9325 @code{define_subst}, the third argument (@samp{_noclobber}) is the
9326 attribute value that would be substituted into the unchanged version of
9327 the source RTL template, and the last argument (@samp{_clobber}) is the
9328 value that would be substituted into the second, transformed,
9329 version of the RTL template.
9331 Once the subst-attribute has been defined, it should be used in RTL
9332 templates which need to be processed by the @code{define_subst}. So,
9333 the original RTL template should be changed:
9336 (define_insn "maxsi<add_clobber_name>"
9337 [(set (match_operand:SI 0 "register_operand" "=r")
9339 (match_operand:SI 1 "register_operand" "r")
9340 (match_operand:SI 2 "register_operand" "r")))]
9342 "max\t@{%2, %1, %0|%0, %1, %2@}"
9346 The result of the @code{define_subst} usage would look like the following:
9349 (define_insn "maxsi_noclobber"
9350 [(set (match_operand:SI 0 "register_operand" "=r")
9352 (match_operand:SI 1 "register_operand" "r")
9353 (match_operand:SI 2 "register_operand" "r")))]
9355 "max\t@{%2, %1, %0|%0, %1, %2@}"
9357 (define_insn "maxsi_clobber"
9358 [(set (match_operand:SI 0 "register_operand" "=r")
9360 (match_operand:SI 1 "register_operand" "r")
9361 (match_operand:SI 2 "register_operand" "r")))
9362 (clobber (reg:CC FLAGS_REG))]
9364 "max\t@{%2, %1, %0|%0, %1, %2@}"
9368 @node Define Subst Pattern Matching
9369 @subsection Pattern Matching in @code{define_subst}
9370 @cindex define_subst
9372 All expressions, allowed in @code{define_insn} or @code{define_expand},
9373 are allowed in the input-template of @code{define_subst}, except
9374 @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The
9375 meanings of expressions in the input-template were changed:
9377 @code{match_operand} matches any expression (possibly, a subtree in
9378 RTL-template), if modes of the @code{match_operand} and this expression
9379 are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or
9380 this expression is @code{match_dup}, @code{match_op_dup}. If the
9381 expression is @code{match_operand} too, and predicate of
9382 @code{match_operand} from the input pattern is not empty, then the
9383 predicates are compared. That can be used for more accurate filtering
9384 of accepted RTL-templates.
9386 @code{match_operator} matches common operators (like @code{plus},
9387 @code{minus}), @code{unspec}, @code{unspec_volatile} operators and
9388 @code{match_operator}s from the original pattern if the modes match and
9389 @code{match_operator} from the input pattern has the same number of
9390 operands as the operator from the original pattern.
9392 @node Define Subst Output Template
9393 @subsection Generation of output template in @code{define_subst}
9394 @cindex define_subst
9396 If all necessary checks for @code{define_subst} application pass, a new
9397 RTL-pattern, based on the output-template, is created to replace the old
9398 template. Like in input-patterns, meanings of some RTL expressions are
9399 changed when they are used in output-patterns of a @code{define_subst}.
9400 Thus, @code{match_dup} is used for copying the whole expression from the
9401 original pattern, which matched corresponding @code{match_operand} from
9404 @code{match_dup N} is used in the output template to be replaced with
9405 the expression from the original pattern, which matched
9406 @code{match_operand N} from the input pattern. As a consequence,
9407 @code{match_dup} cannot be used to point to @code{match_operand}s from
9408 the output pattern, it should always refer to a @code{match_operand}
9409 from the input pattern.
9411 In the output template one can refer to the expressions from the
9412 original pattern and create new ones. For instance, some operands could
9413 be added by means of standard @code{match_operand}.
9415 After replacing @code{match_dup} with some RTL-subtree from the original
9416 pattern, it could happen that several @code{match_operand}s in the
9417 output pattern have the same indexes. It is unknown, how many and what
9418 indexes would be used in the expression which would replace
9419 @code{match_dup}, so such conflicts in indexes are inevitable. To
9420 overcome this issue, @code{match_operands} and @code{match_operators},
9421 which were introduced into the output pattern, are renumerated when all
9422 @code{match_dup}s are replaced.
9424 Number of alternatives in @code{match_operand}s introduced into the
9425 output template @code{M} could differ from the number of alternatives in
9426 the original pattern @code{N}, so in the resultant pattern there would
9427 be @code{N*M} alternatives. Thus, constraints from the original pattern
9428 would be duplicated @code{N} times, constraints from the output pattern
9429 would be duplicated @code{M} times, producing all possible combinations.
9433 @node Constant Definitions
9434 @section Constant Definitions
9435 @cindex constant definitions
9436 @findex define_constants
9438 Using literal constants inside instruction patterns reduces legibility and
9439 can be a maintenance problem.
9441 To overcome this problem, you may use the @code{define_constants}
9442 expression. It contains a vector of name-value pairs. From that
9443 point on, wherever any of the names appears in the MD file, it is as
9444 if the corresponding value had been written instead. You may use
9445 @code{define_constants} multiple times; each appearance adds more
9446 constants to the table. It is an error to redefine a constant with
9449 To come back to the a29k load multiple example, instead of
9453 [(match_parallel 0 "load_multiple_operation"
9454 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9455 (match_operand:SI 2 "memory_operand" "m"))
9457 (clobber (reg:SI 179))])]
9473 [(match_parallel 0 "load_multiple_operation"
9474 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9475 (match_operand:SI 2 "memory_operand" "m"))
9477 (clobber (reg:SI R_CR))])]
9482 The constants that are defined with a define_constant are also output
9483 in the insn-codes.h header file as #defines.
9485 @cindex enumerations
9486 @findex define_c_enum
9487 You can also use the machine description file to define enumerations.
9488 Like the constants defined by @code{define_constant}, these enumerations
9489 are visible to both the machine description file and the main C code.
9491 The syntax is as follows:
9494 (define_c_enum "@var{name}" [
9502 This definition causes the equivalent of the following C code to appear
9503 in @file{insn-constants.h}:
9510 @var{valuen} = @var{n}
9512 #define NUM_@var{cname}_VALUES (@var{n} + 1)
9515 where @var{cname} is the capitalized form of @var{name}.
9516 It also makes each @var{valuei} available in the machine description
9517 file, just as if it had been declared with:
9520 (define_constants [(@var{valuei} @var{i})])
9523 Each @var{valuei} is usually an upper-case identifier and usually
9524 begins with @var{cname}.
9526 You can split the enumeration definition into as many statements as
9527 you like. The above example is directly equivalent to:
9530 (define_c_enum "@var{name}" [@var{value0}])
9531 (define_c_enum "@var{name}" [@var{value1}])
9533 (define_c_enum "@var{name}" [@var{valuen}])
9536 Splitting the enumeration helps to improve the modularity of each
9537 individual @code{.md} file. For example, if a port defines its
9538 synchronization instructions in a separate @file{sync.md} file,
9539 it is convenient to define all synchronization-specific enumeration
9540 values in @file{sync.md} rather than in the main @file{.md} file.
9542 Some enumeration names have special significance to GCC:
9546 @findex unspec_volatile
9547 If an enumeration called @code{unspecv} is defined, GCC will use it
9548 when printing out @code{unspec_volatile} expressions. For example:
9551 (define_c_enum "unspecv" [
9556 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
9559 (unspec_volatile ... UNSPECV_BLOCKAGE)
9564 If an enumeration called @code{unspec} is defined, GCC will use
9565 it when printing out @code{unspec} expressions. GCC will also use
9566 it when printing out @code{unspec_volatile} expressions unless an
9567 @code{unspecv} enumeration is also defined. You can therefore
9568 decide whether to keep separate enumerations for volatile and
9569 non-volatile expressions or whether to use the same enumeration
9574 @anchor{define_enum}
9575 Another way of defining an enumeration is to use @code{define_enum}:
9578 (define_enum "@var{name}" [
9586 This directive implies:
9589 (define_c_enum "@var{name}" [
9590 @var{cname}_@var{cvalue0}
9591 @var{cname}_@var{cvalue1}
9593 @var{cname}_@var{cvaluen}
9597 @findex define_enum_attr
9598 where @var{cvaluei} is the capitalized form of @var{valuei}.
9599 However, unlike @code{define_c_enum}, the enumerations defined
9600 by @code{define_enum} can be used in attribute specifications
9601 (@pxref{define_enum_attr}).
9606 @cindex iterators in @file{.md} files
9608 Ports often need to define similar patterns for more than one machine
9609 mode or for more than one rtx code. GCC provides some simple iterator
9610 facilities to make this process easier.
9613 * Mode Iterators:: Generating variations of patterns for different modes.
9614 * Code Iterators:: Doing the same for codes.
9615 * Int Iterators:: Doing the same for integers.
9616 * Subst Iterators:: Generating variations of patterns for define_subst.
9619 @node Mode Iterators
9620 @subsection Mode Iterators
9621 @cindex mode iterators in @file{.md} files
9623 Ports often need to define similar patterns for two or more different modes.
9628 If a processor has hardware support for both single and double
9629 floating-point arithmetic, the @code{SFmode} patterns tend to be
9630 very similar to the @code{DFmode} ones.
9633 If a port uses @code{SImode} pointers in one configuration and
9634 @code{DImode} pointers in another, it will usually have very similar
9635 @code{SImode} and @code{DImode} patterns for manipulating pointers.
9638 Mode iterators allow several patterns to be instantiated from one
9639 @file{.md} file template. They can be used with any type of
9640 rtx-based construct, such as a @code{define_insn},
9641 @code{define_split}, or @code{define_peephole2}.
9644 * Defining Mode Iterators:: Defining a new mode iterator.
9645 * Substitutions:: Combining mode iterators with substitutions
9646 * Examples:: Examples
9649 @node Defining Mode Iterators
9650 @subsubsection Defining Mode Iterators
9651 @findex define_mode_iterator
9653 The syntax for defining a mode iterator is:
9656 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
9659 This allows subsequent @file{.md} file constructs to use the mode suffix
9660 @code{:@var{name}}. Every construct that does so will be expanded
9661 @var{n} times, once with every use of @code{:@var{name}} replaced by
9662 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
9663 and so on. In the expansion for a particular @var{modei}, every
9664 C condition will also require that @var{condi} be true.
9669 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9672 defines a new mode suffix @code{:P}. Every construct that uses
9673 @code{:P} will be expanded twice, once with every @code{:P} replaced
9674 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
9675 The @code{:SI} version will only apply if @code{Pmode == SImode} and
9676 the @code{:DI} version will only apply if @code{Pmode == DImode}.
9678 As with other @file{.md} conditions, an empty string is treated
9679 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
9680 to @code{@var{mode}}. For example:
9683 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9686 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
9687 but that the @code{:SI} expansion has no such constraint.
9689 Iterators are applied in the order they are defined. This can be
9690 significant if two iterators are used in a construct that requires
9691 substitutions. @xref{Substitutions}.
9694 @subsubsection Substitution in Mode Iterators
9695 @findex define_mode_attr
9697 If an @file{.md} file construct uses mode iterators, each version of the
9698 construct will often need slightly different strings or modes. For
9703 When a @code{define_expand} defines several @code{add@var{m}3} patterns
9704 (@pxref{Standard Names}), each expander will need to use the
9705 appropriate mode name for @var{m}.
9708 When a @code{define_insn} defines several instruction patterns,
9709 each instruction will often use a different assembler mnemonic.
9712 When a @code{define_insn} requires operands with different modes,
9713 using an iterator for one of the operand modes usually requires a specific
9714 mode for the other operand(s).
9717 GCC supports such variations through a system of ``mode attributes''.
9718 There are two standard attributes: @code{mode}, which is the name of
9719 the mode in lower case, and @code{MODE}, which is the same thing in
9720 upper case. You can define other attributes using:
9723 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9726 where @var{name} is the name of the attribute and @var{valuei}
9727 is the value associated with @var{modei}.
9729 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9730 each string and mode in the pattern for sequences of the form
9731 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9732 mode attribute. If the attribute is defined for @var{mode}, the whole
9733 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9736 For example, suppose an @file{.md} file has:
9739 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9740 (define_mode_attr load [(SI "lw") (DI "ld")])
9743 If one of the patterns that uses @code{:P} contains the string
9744 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9745 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9748 Here is an example of using an attribute for a mode:
9751 (define_mode_iterator LONG [SI DI])
9752 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9753 (define_insn @dots{}
9754 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9757 The @code{@var{iterator}:} prefix may be omitted, in which case the
9758 substitution will be attempted for every iterator expansion.
9761 @subsubsection Mode Iterator Examples
9763 Here is an example from the MIPS port. It defines the following
9764 modes and attributes (among others):
9767 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9768 (define_mode_attr d [(SI "") (DI "d")])
9771 and uses the following template to define both @code{subsi3}
9775 (define_insn "sub<mode>3"
9776 [(set (match_operand:GPR 0 "register_operand" "=d")
9777 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9778 (match_operand:GPR 2 "register_operand" "d")))]
9781 [(set_attr "type" "arith")
9782 (set_attr "mode" "<MODE>")])
9785 This is exactly equivalent to:
9788 (define_insn "subsi3"
9789 [(set (match_operand:SI 0 "register_operand" "=d")
9790 (minus:SI (match_operand:SI 1 "register_operand" "d")
9791 (match_operand:SI 2 "register_operand" "d")))]
9794 [(set_attr "type" "arith")
9795 (set_attr "mode" "SI")])
9797 (define_insn "subdi3"
9798 [(set (match_operand:DI 0 "register_operand" "=d")
9799 (minus:DI (match_operand:DI 1 "register_operand" "d")
9800 (match_operand:DI 2 "register_operand" "d")))]
9803 [(set_attr "type" "arith")
9804 (set_attr "mode" "DI")])
9807 @node Code Iterators
9808 @subsection Code Iterators
9809 @cindex code iterators in @file{.md} files
9810 @findex define_code_iterator
9811 @findex define_code_attr
9813 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9818 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9821 defines a pseudo rtx code @var{name} that can be instantiated as
9822 @var{codei} if condition @var{condi} is true. Each @var{codei}
9823 must have the same rtx format. @xref{RTL Classes}.
9825 As with mode iterators, each pattern that uses @var{name} will be
9826 expanded @var{n} times, once with all uses of @var{name} replaced by
9827 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9828 @xref{Defining Mode Iterators}.
9830 It is possible to define attributes for codes as well as for modes.
9831 There are two standard code attributes: @code{code}, the name of the
9832 code in lower case, and @code{CODE}, the name of the code in upper case.
9833 Other attributes are defined using:
9836 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9839 Here's an example of code iterators in action, taken from the MIPS port:
9842 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9843 eq ne gt ge lt le gtu geu ltu leu])
9845 (define_expand "b<code>"
9847 (if_then_else (any_cond:CC (cc0)
9849 (label_ref (match_operand 0 ""))
9853 gen_conditional_branch (operands, <CODE>);
9858 This is equivalent to:
9861 (define_expand "bunordered"
9863 (if_then_else (unordered:CC (cc0)
9865 (label_ref (match_operand 0 ""))
9869 gen_conditional_branch (operands, UNORDERED);
9873 (define_expand "bordered"
9875 (if_then_else (ordered:CC (cc0)
9877 (label_ref (match_operand 0 ""))
9881 gen_conditional_branch (operands, ORDERED);
9889 @subsection Int Iterators
9890 @cindex int iterators in @file{.md} files
9891 @findex define_int_iterator
9892 @findex define_int_attr
9894 Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
9899 (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
9902 defines a pseudo integer constant @var{name} that can be instantiated as
9903 @var{inti} if condition @var{condi} is true. Each @var{int}
9904 must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
9905 in only those rtx fields that have 'i' as the specifier. This means that
9906 each @var{int} has to be a constant defined using define_constant or
9909 As with mode and code iterators, each pattern that uses @var{name} will be
9910 expanded @var{n} times, once with all uses of @var{name} replaced by
9911 @var{int1}, once with all uses replaced by @var{int2}, and so on.
9912 @xref{Defining Mode Iterators}.
9914 It is possible to define attributes for ints as well as for codes and modes.
9915 Attributes are defined using:
9918 (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
9921 Here's an example of int iterators in action, taken from the ARM port:
9924 (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
9926 (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
9928 (define_insn "neon_vq<absneg><mode>"
9929 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9930 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9931 (match_operand:SI 2 "immediate_operand" "i")]
9934 "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9935 [(set_attr "type" "neon_vqneg_vqabs")]
9940 This is equivalent to:
9943 (define_insn "neon_vqabs<mode>"
9944 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9945 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9946 (match_operand:SI 2 "immediate_operand" "i")]
9949 "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9950 [(set_attr "type" "neon_vqneg_vqabs")]
9953 (define_insn "neon_vqneg<mode>"
9954 [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
9955 (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
9956 (match_operand:SI 2 "immediate_operand" "i")]
9959 "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
9960 [(set_attr "type" "neon_vqneg_vqabs")]
9965 @node Subst Iterators
9966 @subsection Subst Iterators
9967 @cindex subst iterators in @file{.md} files
9968 @findex define_subst
9969 @findex define_subst_attr
9971 Subst iterators are special type of iterators with the following
9972 restrictions: they could not be declared explicitly, they always have
9973 only two values, and they do not have explicit dedicated name.
9974 Subst-iterators are triggered only when corresponding subst-attribute is
9975 used in RTL-pattern.
9977 Subst iterators transform templates in the following way: the templates
9978 are duplicated, the subst-attributes in these templates are replaced
9979 with the corresponding values, and a new attribute is implicitly added
9980 to the given @code{define_insn}/@code{define_expand}. The name of the
9981 added attribute matches the name of @code{define_subst}. Such
9982 attributes are declared implicitly, and it is not allowed to have a
9983 @code{define_attr} named as a @code{define_subst}.
9985 Each subst iterator is linked to a @code{define_subst}. It is declared
9986 implicitly by the first appearance of the corresponding
9987 @code{define_subst_attr}, and it is not allowed to define it explicitly.
9989 Declarations of subst-attributes have the following syntax:
9991 @findex define_subst_attr
9993 (define_subst_attr "@var{name}"
9995 "@var{no-subst-value}"
9996 "@var{subst-applied-value}")
9999 @var{name} is a string with which the given subst-attribute could be
10002 @var{subst-name} shows which @code{define_subst} should be applied to an
10003 RTL-template if the given subst-attribute is present in the
10006 @var{no-subst-value} is a value with which subst-attribute would be
10007 replaced in the first copy of the original RTL-template.
10009 @var{subst-applied-value} is a value with which subst-attribute would be
10010 replaced in the second copy of the original RTL-template.