gcc/config/aarch64/aarch64-protos.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_PROTOS_H
  23 #define GCC_AARCH64_PROTOS_H
  24
  25 /*
  26   SYMBOL_CONTEXT_ADR
  27   The symbol is used in a load-address operation.
  28   SYMBOL_CONTEXT_MEM
  29   The symbol is used as the address in a MEM.
  30  */
  31 enum aarch64_symbol_context
  32 {
  33   SYMBOL_CONTEXT_MEM,
  34   SYMBOL_CONTEXT_ADR
  35 };
  36
  37 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
  38    high and lo relocs that calculate the base address using a PC
  39    relative reloc.
  40    So to get the address of foo, we generate
  41    adrp x0, foo
  42    add  x0, x0, :lo12:foo
  43
  44    To load or store something to foo, we could use the corresponding
  45    load store variants that generate an
  46    ldr x0, [x0,:lo12:foo]
  47    or
  48    str x1, [x0, :lo12:foo]
  49
  50    This corresponds to the small code model of the compiler.
  51
  52    SYMBOL_SMALL_GOT_4G: Similar to the one above but this
  53    gives us the GOT entry of the symbol being referred to :
  54    Thus calculating the GOT entry for foo is done using the
  55    following sequence of instructions.  The ADRP instruction
  56    gets us to the page containing the GOT entry of the symbol
  57    and the got_lo12 gets us the actual offset in it, together
  58    the base and offset, we can address 4G size GOT table.
  59
  60    adrp  x0, :got:foo
  61    ldr   x0, [x0, :gotoff_lo12:foo]
  62
  63    This corresponds to the small PIC model of the compiler.
  64
  65    SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
  66    restricted within 28K GOT table size.
  67
  68    ldr reg, [gp, #:gotpage_lo15:sym]
  69
  70    This corresponds to -fpic model for small memory model of the compiler.
  71
  72    SYMBOL_SMALL_TLSGD
  73    SYMBOL_SMALL_TLSDESC
  74    SYMBOL_SMALL_GOTTPREL
  75    SYMBOL_TLSLE
  76    Each of these represents a thread-local symbol, and corresponds to the
  77    thread local storage relocation operator for the symbol being referred to.
  78
  79    SYMBOL_TINY_ABSOLUTE
  80
  81    Generate symbol accesses as a PC relative address using a single
  82    instruction.  To compute the address of symbol foo, we generate:
  83
  84    ADR x0, foo
  85
  86    SYMBOL_TINY_GOT
  87
  88    Generate symbol accesses via the GOT using a single PC relative
  89    instruction.  To compute the address of symbol foo, we generate:
  90
  91    ldr t0, :got:foo
  92
  93    The value of foo can subsequently read using:
  94
  95    ldrb    t0, [t0]
  96
  97    SYMBOL_FORCE_TO_MEM : Global variables are addressed using
  98    constant pool.  All variable addresses are spilled into constant
  99    pools.  The constant pools themselves are addressed using PC
 100    relative accesses.  This only works for the large code model.
 101  */
 102 enum aarch64_symbol_type
 103 {
 104   SYMBOL_SMALL_ABSOLUTE,
 105   SYMBOL_SMALL_GOT_28K,
 106   SYMBOL_SMALL_GOT_4G,
 107   SYMBOL_SMALL_TLSGD,
 108   SYMBOL_SMALL_TLSDESC,
 109   SYMBOL_SMALL_GOTTPREL,
 110   SYMBOL_TINY_ABSOLUTE,
 111   SYMBOL_TINY_GOT,
 112   SYMBOL_TLSLE,
 113   SYMBOL_FORCE_TO_MEM
 114 };
 115
 116 /* A set of tuning parameters contains references to size and time
 117    cost models and vectors for address cost calculations, register
 118    move costs and memory move costs.  */
 119
 120 /* Scaled addressing modes can vary cost depending on the mode of the
 121    value to be loaded/stored.  QImode values cannot use scaled
 122    addressing modes.  */
 123
 124 struct scale_addr_mode_cost
 125 {
 126   const int hi;
 127   const int si;
 128   const int di;
 129   const int ti;
 130 };
 131
 132 /* Additional cost for addresses.  */
 133 struct cpu_addrcost_table
 134 {
 135   const struct scale_addr_mode_cost addr_scale_costs;
 136   const int pre_modify;
 137   const int post_modify;
 138   const int register_offset;
 139   const int register_extend;
 140   const int imm_offset;
 141 };
 142
 143 /* Additional costs for register copies.  Cost is for one register.  */
 144 struct cpu_regmove_cost
 145 {
 146   const int GP2GP;
 147   const int GP2FP;
 148   const int FP2GP;
 149   const int FP2FP;
 150 };
 151
 152 /* Cost for vector insn classes.  */
 153 struct cpu_vector_cost
 154 {
 155   const int scalar_stmt_cost;            /* Cost of any scalar operation,
 156                                             excluding load and store.  */
 157   const int scalar_load_cost;            /* Cost of scalar load.  */
 158   const int scalar_store_cost;           /* Cost of scalar store.  */
 159   const int vec_stmt_cost;               /* Cost of any vector operation,
 160                                             excluding load, store,
 161                                             vector-to-scalar and
 162                                             scalar-to-vector operation.  */
 163   const int vec_to_scalar_cost;          /* Cost of vec-to-scalar operation.  */
 164   const int scalar_to_vec_cost;          /* Cost of scalar-to-vector
 165                                             operation.  */
 166   const int vec_align_load_cost;         /* Cost of aligned vector load.  */
 167   const int vec_unalign_load_cost;       /* Cost of unaligned vector load.  */
 168   const int vec_unalign_store_cost;      /* Cost of unaligned vector store.  */
 169   const int vec_store_cost;              /* Cost of vector store.  */
 170   const int cond_taken_branch_cost;      /* Cost of taken branch.  */
 171   const int cond_not_taken_branch_cost;  /* Cost of not taken branch.  */
 172 };
 173
 174 /* Branch costs.  */
 175 struct cpu_branch_cost
 176 {
 177   const int predictable;    /* Predictable branch or optimizing for size.  */
 178   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
 179 };
 180
 181 struct tune_params
 182 {
 183   const struct cpu_cost_table *insn_extra_cost;
 184   const struct cpu_addrcost_table *addr_cost;
 185   const struct cpu_regmove_cost *regmove_cost;
 186   const struct cpu_vector_cost *vec_costs;
 187   const struct cpu_branch_cost *branch_costs;
 188   int memmov_cost;
 189   int issue_rate;
 190   unsigned int fusible_ops;
 191   int function_align;
 192   int jump_align;
 193   int loop_align;
 194   int int_reassoc_width;
 195   int fp_reassoc_width;
 196   int vec_reassoc_width;
 197   int min_div_recip_mul_sf;
 198   int min_div_recip_mul_df;
 199   unsigned int extra_tuning_flags;
 200 };
 201
 202 #define AARCH64_FUSION_PAIR(x, name, index) \
 203   AARCH64_FUSE_##name = (1 << index),
 204 /* Supported fusion operations.  */
 205 enum aarch64_fusion_pairs
 206 {
 207   AARCH64_FUSE_NOTHING = 0,
 208 #include "aarch64-fusion-pairs.def"
 209
 210 /* Hacky macro to build AARCH64_FUSE_ALL.  The sequence below expands
 211    to:
 212    AARCH64_FUSE_ALL = 0 | AARCH64_FUSE_index1 | AARCH64_FUSE_index2 ...  */
 213 #undef AARCH64_FUSION_PAIR
 214 #define AARCH64_FUSION_PAIR(x, name, y) \
 215   | AARCH64_FUSE_##name
 216
 217   AARCH64_FUSE_ALL = 0
 218 #include "aarch64-fusion-pairs.def"
 219 };
 220 #undef AARCH64_FUSION_PAIR
 221
 222 #define AARCH64_EXTRA_TUNING_OPTION(x, name, index) \
 223   AARCH64_EXTRA_TUNE_##name = (1 << index),
 224 /* Supported tuning flags.  */
 225 enum aarch64_extra_tuning_flags
 226 {
 227   AARCH64_EXTRA_TUNE_NONE = 0,
 228 #include "aarch64-tuning-flags.def"
 229
 230 /* Hacky macro to build the "all" flag mask.
 231    Expands to 0 | AARCH64_TUNE_index0 | AARCH64_TUNE_index1 , etc.  */
 232 #undef AARCH64_EXTRA_TUNING_OPTION
 233 #define AARCH64_EXTRA_TUNING_OPTION(x, name, y) \
 234   | AARCH64_EXTRA_TUNE_##name
 235   AARCH64_EXTRA_TUNE_ALL = 0
 236 #include "aarch64-tuning-flags.def"
 237 };
 238 #undef AARCH64_EXTRA_TUNING_OPTION
 239
 240 extern struct tune_params aarch64_tune_params;
 241
 242 HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
 243 int aarch64_get_condition_code (rtx);
 244 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
 245 int aarch64_branch_cost (bool, bool);
 246 enum aarch64_symbol_type
 247 aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context);
 248 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
 249 bool aarch64_constant_address_p (rtx);
 250 bool aarch64_expand_movmem (rtx *);
 251 bool aarch64_float_const_zero_rtx_p (rtx);
 252 bool aarch64_function_arg_regno_p (unsigned);
 253 bool aarch64_gen_movmemqi (rtx *);
 254 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
 255 bool aarch64_is_extend_from_extract (machine_mode, rtx, rtx);
 256 bool aarch64_is_long_call_p (rtx);
 257 bool aarch64_label_mentioned_p (rtx);
 258 void aarch64_declare_function_name (FILE *, const char*, tree);
 259 bool aarch64_legitimate_pic_operand_p (rtx);
 260 bool aarch64_modes_tieable_p (machine_mode mode1,
 261                               machine_mode mode2);
 262 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
 263 bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
 264                             machine_mode);
 265 int aarch64_simd_attr_length_rglist (enum machine_mode);
 266 rtx aarch64_reverse_mask (enum machine_mode);
 267 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
 268 char *aarch64_output_scalar_simd_mov_immediate (rtx, machine_mode);
 269 char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned);
 270 bool aarch64_pad_arg_upward (machine_mode, const_tree);
 271 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
 272 bool aarch64_regno_ok_for_base_p (int, bool);
 273 bool aarch64_regno_ok_for_index_p (int, bool);
 274 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
 275                                             bool high);
 276 bool aarch64_simd_imm_scalar_p (rtx x, machine_mode mode);
 277 bool aarch64_simd_imm_zero_p (rtx, machine_mode);
 278 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, machine_mode);
 279 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
 280 bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
 281                                    struct simd_immediate_info *);
 282 bool aarch64_symbolic_address_p (rtx);
 283 bool aarch64_uimm12_shift (HOST_WIDE_INT);
 284 bool aarch64_use_return_insn_p (void);
 285 const char *aarch64_mangle_builtin_type (const_tree);
 286 const char *aarch64_output_casesi (rtx *);
 287 const char *aarch64_rewrite_selected_cpu (const char *name);
 288
 289 enum aarch64_symbol_type aarch64_classify_symbol (rtx, rtx,
 290                                                   enum aarch64_symbol_context);
 291 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
 292 enum reg_class aarch64_regno_regclass (unsigned);
 293 int aarch64_asm_preferred_eh_data_format (int, int);
 294 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
 295                                                        machine_mode);
 296 int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
 297 int aarch64_hard_regno_nregs (unsigned, machine_mode);
 298 int aarch64_simd_attr_length_move (rtx_insn *);
 299 int aarch64_uxt_size (int, HOST_WIDE_INT);
 300 rtx aarch64_final_eh_return_addr (void);
 301 rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
 302 const char *aarch64_output_move_struct (rtx *operands);
 303 rtx aarch64_return_addr (int, rtx);
 304 rtx aarch64_simd_gen_const_vector_dup (machine_mode, int);
 305 bool aarch64_simd_mem_operand_p (rtx);
 306 rtx aarch64_simd_vect_par_cnst_half (machine_mode, bool);
 307 rtx aarch64_tls_get_addr (void);
 308 tree aarch64_fold_builtin (tree, int, tree *, bool);
 309 unsigned aarch64_dbx_register_number (unsigned);
 310 unsigned aarch64_trampoline_size (void);
 311 void aarch64_asm_output_labelref (FILE *, const char *);
 312 void aarch64_elf_asm_named_section (const char *, unsigned, tree);
 313 void aarch64_err_no_fpadvsimd (machine_mode, const char *);
 314 void aarch64_expand_epilogue (bool);
 315 void aarch64_expand_mov_immediate (rtx, rtx);
 316 void aarch64_expand_prologue (void);
 317 void aarch64_expand_vector_init (rtx, rtx);
 318 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
 319                                    const_tree, unsigned);
 320 void aarch64_init_expanders (void);
 321 void aarch64_print_operand (FILE *, rtx, char);
 322 void aarch64_print_operand_address (FILE *, rtx);
 323 void aarch64_emit_call_insn (rtx);
 324
 325 /* Initialize builtins for SIMD intrinsics.  */
 326 void init_aarch64_simd_builtins (void);
 327
 328 void aarch64_simd_emit_reg_reg_move (rtx *, enum machine_mode, unsigned int);
 329
 330 /* Expand builtins for SIMD intrinsics.  */
 331 rtx aarch64_simd_expand_builtin (int, tree, rtx);
 332
 333 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
 334
 335 void aarch64_split_128bit_move (rtx, rtx);
 336
 337 bool aarch64_split_128bit_move_p (rtx, rtx);
 338
 339 void aarch64_split_simd_combine (rtx, rtx, rtx);
 340
 341 void aarch64_split_simd_move (rtx, rtx);
 342
 343 /* Check for a legitimate floating point constant for FMOV.  */
 344 bool aarch64_float_const_representable_p (rtx);
 345
 346 #if defined (RTX_CODE)
 347
 348 bool aarch64_legitimate_address_p (machine_mode, rtx, RTX_CODE, bool);
 349 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
 350 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
 351 rtx aarch64_load_tp (rtx);
 352
 353 void aarch64_expand_compare_and_swap (rtx op[]);
 354 void aarch64_split_compare_and_swap (rtx op[]);
 355 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 356
 357 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, enum machine_mode, RTX_CODE);
 358 #endif /* RTX_CODE */
 359
 360 void aarch64_init_builtins (void);
 361 rtx aarch64_expand_builtin (tree exp,
 362                             rtx target,
 363                             rtx subtarget ATTRIBUTE_UNUSED,
 364                             machine_mode mode ATTRIBUTE_UNUSED,
 365                             int ignore ATTRIBUTE_UNUSED);
 366 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED);
 367
 368 tree
 369 aarch64_builtin_vectorized_function (tree fndecl,
 370                                      tree type_out,
 371                                      tree type_in);
 372
 373 extern void aarch64_split_combinev16qi (rtx operands[3]);
 374 extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
 375 extern bool aarch64_madd_needs_nop (rtx_insn *);
 376 extern void aarch64_final_prescan_insn (rtx_insn *);
 377 extern bool
 378 aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
 379 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
 380 int aarch64_ccmp_mode_to_code (enum machine_mode mode);
 381
 382 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
 383 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
 384 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
 385 #endif /* GCC_AARCH64_PROTOS_H */