RISC-V: Force scalable vector on all vsetvl tests
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / vsetvl / wredsum_vlmax.c
blobd36560b2bafdc133fe2c092bab263b0c9f2356df
1 /* { dg-do compile } */
2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv64gcv_zvl256b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax -O3" } */
5 #include <stdint-gcc.h>
7 int16_t foo (int8_t *restrict a)
9 int16_t sum = 0;
10 for (int i = 0; i < 8; i += 1)
11 sum += a[i];
12 return sum;
15 /* { dg-final { scan-assembler-not {\tvsetivli\tzero,16} } } */