RISC-V: Force scalable vector on all vsetvl tests
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / vsetvl / vlmax_miss_default-23.c
blobb1faaeebf887009d8eabc914b21584f4c89f5ecd
1 /* { dg-do compile } */
2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
4 #include "riscv_vector.h"
6 /* The for loop body should not have vsetvl instruction. */
7 void f (void * restrict in, void * restrict out, int n, int cond)
9 switch (cond)
11 case 1:{
12 vint16mf2_t v = *(vint16mf2_t*)(in + 100);
13 *(vint16mf2_t*)(out + 100) = v;
14 break;
16 case 2:{
17 vint16mf2_t v = *(vint16mf2_t*)(in + 200);
18 *(vint16mf2_t*)(out + 100) = v;
19 break;
21 case 3:{
22 vint16mf2_t v = *(vint16mf2_t*)(in + 300);
23 *(vint16mf2_t*)(out + 100) = v;
24 break;
26 default:{
27 break;
30 for (int i = 0; i < n; i++)
32 vint16mf2_t v = *(vint16mf2_t*)(in + i);
33 *(vint16mf2_t*)(out + i) = v;
37 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
38 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]\:} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */