gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_switch-7.c

   1 /* { dg-do compile } */
   2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
   3
   4 #include "riscv_vector.h"
   5
   6 void f (void * restrict in, void * restrict out, int n)
   7 {
   8   vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
   9   vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
  10   vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
  11   vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
  12
  13   __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
  14   __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
  15   __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
  16   __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
  17
  18   for (int i = 0; i < n; i++)
  19     {
  20       vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + 5, 5);
  21       __riscv_vse16_v_i16mf4 (out + i + 5, v, 5);
  22       vint16mf2_t v2 = __riscv_vle16_v_i16mf2 (in + i + 6, 8);
  23       __riscv_vse16_v_i16mf2 (out + i + 6, v2, 8);
  24     }
  25 }
  26
  27 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
  28 /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetivli\s+zero,\s*5,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
  29 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*8,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */