RISC-V: Force scalable vector on all vsetvl tests
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / vsetvl / imm_loop_invariant-8.c
blob1b7ce74ecef5af68e887b0b8d4e673052ba85217
1 /* { dg-do compile } */
2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
4 #include "riscv_vector.h"
6 void f (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
8 vbool64_t mask = *(vbool64_t*)mask_in;
9 for (int i = 0; i < l; i++){
10 for (int j = 0; j < m; j++){
11 for (int k = 0; k < n; k++)
13 vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j, 17);
14 __riscv_vse8_v_i8mf8 (out + i + j, v, 17);
15 vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + j + 16, 17);
16 __riscv_vse8_v_i8mf8 (out + i + j + 16, v2, 17);
17 vint8mf8_t v3 = __riscv_vle8_v_i8mf8_mu (mask, v2, in + i + j + 16, 17);
18 __riscv_vse8_v_i8mf8 (out + i + j + 16, v3, 17);
24 void f2 (void * restrict in, void * restrict out, void * restrict mask_in, int l, int n, int m)
26 vbool8_t mask = *(vbool8_t*)mask_in;
27 for (int i = 0; i < l; i++){
28 for (int j = 0; j < m; j++){
29 for (int k = 0; k < n; k++)
31 vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
32 __riscv_vse64_v_f64m8 (out + i + j, v, 17);
33 vfloat64m8_t v2 = __riscv_vle64_v_f64m8_tu (v, in + i + j + 16, 17);
34 __riscv_vse64_v_f64m8 (out + i + j + 16, v2, 17);
35 vfloat64m8_t v3 = __riscv_vle64_v_f64m8_mu (mask, v2, in + i + j + 16, 17);
36 __riscv_vse64_v_f64m8 (out + i + j + 16, v3, 17);
42 /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
43 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
44 /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
45 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */