RISC-V: Force scalable vector on all vsetvl tests
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / vsetvl / avl_single-82.c
blob0cdd6568886d6444167acf8275d77105432c3a8f
1 /* { dg-do compile } */
2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */
4 #include "riscv_vector.h"
6 float f0 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl, float scalar)
8 vbool64_t mask = *(vbool64_t*) (in + 1000000);
10 for (size_t i = 0; i < n; i++)
12 vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), 4);
13 __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, 4);
15 vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), 4);
16 __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, 4);
19 vfloat32m1_t v = *(vfloat32m1_t*)(in + 300000);
20 for (size_t i = 0; i < n; i++)
22 v = __riscv_vfmv_s_f_f32m1_tu (v, (scalar + i), 3);
24 return __riscv_vfmv_f_s_f32m1_f32 (v);
27 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
28 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
29 /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
30 /* { dg-final { scan-assembler-times {vsetivli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */