RISC-V: Force scalable vector on all vsetvl tests
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / rvv / vsetvl / avl_single-60.c
blobd156c39604553fc8a90172c4dc99ebd4cf40f1f1
1 /* { dg-do compile } */
2 /* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
4 #include "riscv_vector.h"
6 void f(void *base, void *out, void *mask_in,
7 size_t m, size_t n, size_t a, size_t b) {
9 size_t vl = 999;
10 for (size_t i = 0; i < m; i++) {
11 if (i % 2 == 0) {
12 for (size_t j = 0; j < n; j++){
13 if (j % 2 == 0) {
14 for (size_t k = 0; k < n; k++) {
15 for (size_t i_a = 0; i_a < a; i_a++){
16 for (size_t i_b = 0; i_b < b; i_b++){
17 vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 500 + k + j + i_a + i_b, vl);
18 vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 600 + k + j + i_a + i_b, vl);
19 __riscv_vse8_v_i8mf8 (out + i + 600 + j + k + i_a + i_b, v1, vl);
29 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
30 /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */