| blob | 74ec1e123fecb3be35930788f79d29757df7299a |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
100 /* Include output.h for dump_file. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
147 rtx last_death;
149 /* Record last point of modification of (hard or pseudo) register n. */
150 rtx last_set;
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
293 that location. */
297 /* Basic block in which we are performing combines. */
301 \f
302 /* Length of the currently allocated uid_insn_cost array. */
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
323 /* Reset to label_tick for each extended basic block in scanning order. */
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
336 in a loop. */
340 \f
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
346 struct undo
347 {
352 };
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
360 struct undobuf
361 {
364 rtx other_insn;
365 };
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
450 \f
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
472 \f
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
477 register. */
479 static rtx
481 {
482 rtx ret;
490 }
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
500 {
509 {
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
543 }
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
550 {
552 {
557 else
563 /* Duplicate usage. */
565 }
567 {
571 {
577 else
584 }
585 }
586 }
589 }
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
594 it is used.
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
608 {
609 basic_block bb;
610 rtx next;
612 rtx link;
614 #ifdef HAVE_cc0
616 {
626 }
627 #endif
637 {
643 {
648 }
649 }
652 }
653 \f
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
658 the undo table. */
660 static void
662 {
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
676 {
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
692 }
696 else
705 }
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
711 not safe. */
713 static void
715 {
724 else
733 }
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
740 well. */
742 static void
744 {
753 else
762 }
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
765 \f
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
773 sequence. */
775 static bool
778 {
783 /* Lookup the original insn_rtx_costs. */
788 {
791 {
795 }
796 else
797 {
801 }
802 }
803 else
804 {
807 }
809 /* Calculate the replacement insn_rtx_costs. */
812 {
816 }
817 else
818 {
821 }
824 {
830 {
833 }
834 else
836 }
838 /* Disallow this recombination if both new_cost and old_cost are
839 greater than zero, and new_cost is greater than old cost. */
842 {
844 {
846 {
853 }
855 {
861 }
862 else
863 {
869 }
872 {
875 }
876 else
878 }
881 }
883 /* Update the uid_insn_cost array with the replacement costs. */
890 }
893 /* Delete any insns that copy a register to itself. */
895 static void
897 {
899 basic_block bb;
902 {
904 {
907 {
912 }
913 }
914 }
915 }
917 \f
918 /* Fill in log links field for all insns. */
920 static void
922 {
923 basic_block bb;
929 /* Pass through each block from the end, recording the uses of each
930 register and establishing log links when def is encountered.
931 Note that we do not clear next_use array in order to save time,
932 so we have to test whether the use is in the same basic block as def.
934 There are a few cases below when we do not consider the definition or
935 usage -- these are taken from original flow.c did. Don't ask me why it is
936 done this way; I don't know and if it works, I don't want to know. */
939 {
941 {
945 /* Log links are created only once. */
949 {
952 rtx use_insn;
957 /* Do not consider if it is pre/post modification in MEM. */
961 /* Do not make the log link for frame pointer. */
964 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
967 #endif
968 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 #endif
971 )
976 {
977 /* flow.c claimed:
979 We don't build a LOG_LINK for hard registers contained
980 in ASM_OPERANDs. If these registers get replaced,
981 we might wind up changing the semantics of the insn,
982 even if reload can make what appear to be valid
983 assignments later. */
986 {
987 /* Don't add duplicate links between instructions. */
988 rtx links;
997 }
998 }
1000 }
1003 {
1007 /* Do not consider the usage of the stack pointer
1008 by function call. */
1013 }
1014 }
1015 }
1018 }
1020 /* Clear LOG_LINKS fields of insns. */
1022 static void
1024 {
1025 rtx insn;
1030 }
1032 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1033 true if we found a LOG_LINK that proves that A feeds B. This only works
1034 if there are no instructions between A and B which could have a link
1035 depending on A, since in that case we would not record a link for B.
1036 We also check the implicit dependency created by a cc0 setter/user
1037 pair. */
1039 static bool
1041 {
1042 rtx links;
1046 #ifdef HAVE_cc0
1049 #endif
1051 }
1052 \f
1053 /* Main entry point for combiner. F is the first insn of the function.
1054 NREGS is the first unused pseudo-reg number.
1056 Return nonzero if the combiner has turned an indirect jump
1057 instruction into a direct jump. */
1058 static int
1060 {
1062 #ifdef HAVE_cc0
1063 rtx prev;
1064 #endif
1066 rtx first;
1067 basic_block last_bb;
1087 /* Allocate array for insn info. */
1094 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1095 problems when, for example, we have j <<= 1 in a loop. */
1100 /* Scan all SETs and see if we can deduce anything about what
1101 bits are known to be zero for some registers and how many copies
1102 of the sign bit are known to exist for those registers.
1104 Also set any known values so that we can use it while searching
1105 for what bits are known to be set. */
1108 /* Allow the entry block and the first block to fall into the same EBB.
1109 Conceptually the incoming promotions are assigned to the entry block. */
1114 {
1119 label_tick++;
1127 {
1132 insn);
1135 #ifdef AUTO_INC_DEC
1139 insn);
1140 #endif
1142 /* Record the current insn_rtx_cost of this instruction. */
1145 optimize_this_for_speed_p);
1149 }
1150 }
1154 /* Now scan all the insns in forward order. */
1161 {
1167 label_tick++;
1177 {
1180 {
1190 /* See if we know about function return values before this
1191 insn based upon SUBREG flags. */
1194 /* See if we can find hardregs and subreg of pseudos in
1195 narrower modes. This could help turning TRUNCATEs
1196 into SUBREGs. */
1199 /* Try this insn with each insn it links back to. */
1207 /* Try each sequence of three linked insns ending with this one. */
1210 {
1213 /* If the linked insn has been replaced by a note, then there
1214 is no point in pursuing this chain any further. */
1219 nextlinks;
1225 }
1227 #ifdef HAVE_cc0
1228 /* Try to combine a jump insn that uses CC0
1229 with a preceding insn that sets CC0, and maybe with its
1230 logical predecessor as well.
1231 This is how we make decrement-and-branch insns.
1232 We need this special code because data flow connections
1233 via CC0 do not get entered in LOG_LINKS. */
1239 {
1251 }
1253 /* Do the same for an insn that explicitly references CC0. */
1260 {
1272 }
1274 /* Finally, see if any of the insns that this insn links to
1275 explicitly references CC0. If so, try this insn, that insn,
1276 and its predecessor if it sets CC0. */
1288 #endif
1290 /* Try combining an insn with two different insns whose results it
1291 uses. */
1301 /* Try four-instruction combinations. */
1303 {
1304 rtx next1;
1307 /* If the linked insn has been replaced by a note, then there
1308 is no point in pursuing this chain any further. */
1313 {
1317 /* I0 -> I1 -> I2 -> I3. */
1325 /* I0, I1 -> I2, I2 -> I3. */
1333 }
1336 {
1340 /* I0 -> I2; I1, I2 -> I3. */
1348 /* I0 -> I1; I1, I2 -> I3. */
1356 }
1357 }
1359 /* Try this insn with each REG_EQUAL note it links back to. */
1361 {
1367 /* Avoid using a register that may already been marked
1368 dead by an earlier instruction. */
1373 {
1374 /* Temporarily replace the set's source with the
1375 contents of the REG_EQUAL note. The insn will
1376 be deleted or recognized by try_combine. */
1384 last_combined_insn);
1389 }
1390 }
1395 retry:
1396 ;
1397 }
1398 }
1399 }
1407 /* Clean up. */
1412 {
1415 {
1418 }
1420 }
1430 /* Make recognizer allow volatile MEMs again. */
1434 }
1436 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1438 static void
1440 {
1446 }
1447 \f
1448 /* Set up any promoted values for incoming argument registers. */
1450 static void
1452 {
1453 tree arg;
1458 {
1463 /* Only continue if the incoming argument is in a register. */
1467 /* Determine, if possible, whether all call sites of the current
1468 function lie within the current compilation unit. (This does
1469 take into account the exporting of a function via taking its
1470 address, and so forth.) */
1473 /* The mode and signedness of the argument before any promotions happen
1474 (equal to the mode of the pseudo holding it at that stage). */
1478 /* The mode and signedness of the argument after any source language and
1479 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1483 /* The mode and signedness of the argument as it is actually passed,
1484 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1488 /* The mode of the register in which the argument is being passed. */
1491 /* Eliminate sign extensions in the callee when:
1492 (a) A mode promotion has occurred; */
1495 /* (b) The mode of the register is the same as the mode of
1496 the argument as it is passed; */
1499 /* (c) There's no language level extension; */
1501 ;
1502 /* (c.1) All callers are from the current compilation unit. If that's
1503 the case we don't have to rely on an ABI, we only have to know
1504 what we're generating right now, and we know that we will do the
1505 mode1 to mode2 promotion with the given sign. */
1508 /* (c.2) The combination of the two promotions is useful. This is
1509 true when the signs match, or if the first promotion is unsigned.
1510 In the later case, (sign_extend (zero_extend x)) is the same as
1511 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1517 /* Record that the value was promoted from mode1 to mode3,
1518 so that any sign extension at the head of the current
1519 function may be eliminated. */
1523 }
1524 }
1526 /* Called via note_stores. If X is a pseudo that is narrower than
1527 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1529 If we are setting only a portion of X and we can't figure out what
1530 portion, assume all bits will be used since we don't know what will
1531 be happening.
1533 Similarly, set how many bits of X are known to be copies of the sign bit
1534 at all locations in the function. This is the smallest number implied
1535 by any set of X. */
1537 static void
1539 {
1545 /* If this register is undefined at the start of the file, we can't
1546 say what its contents were. */
1547 && ! REGNO_REG_SET_P
1550 {
1554 {
1558 }
1560 /* If this register is being initialized using itself, and the
1561 register is uninitialized in this basic block, and there are
1562 no LOG_LINKS which set the register, then part of the
1563 register is uninitialized. In that case we can't assume
1564 anything about the number of nonzero bits.
1566 ??? We could do better if we checked this in
1567 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1568 could avoid making assumptions about the insn which initially
1569 sets the register, while still using the information in other
1570 insns. We would have to be careful to check every insn
1571 involved in the combination. */
1577 {
1578 rtx link;
1581 {
1584 }
1586 {
1590 }
1591 }
1593 /* If this is a complex assignment, see if we can convert it into a
1594 simple assignment. */
1597 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1598 set what we know about X. */
1605 {
1608 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1609 /* If X is narrower than a word and SRC is a non-negative
1610 constant that would appear negative in the mode of X,
1611 sign-extend it for use in reg_stat[].nonzero_bits because some
1612 machines (maybe most) will actually do the sign-extension
1613 and this is the conservative approach.
1615 ??? For 2.5, try to tighten up the MD files in this regard
1616 instead of this kludge. */
1627 #endif
1629 /* Don't call nonzero_bits if it cannot change anything. */
1636 }
1637 else
1638 {
1641 }
1642 }
1643 }
1644 \f
1645 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1646 optionally insns that were previously combined into I3 or that will be
1647 combined into the merger of INSN and I3. The order is PRED, PRED2,
1648 INSN, SUCC, SUCC2, I3.
1650 Return 0 if the combination is not allowed for any reason.
1652 If the combination is allowed, *PDEST will be set to the single
1653 destination of INSN and *PSRC to the single source, and this function
1654 will return 1. */
1656 static int
1660 {
1664 rtx p;
1665 #ifdef AUTO_INC_DEC
1666 rtx link;
1667 #endif
1672 {
1674 {
1679 }
1684 }
1688 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1689 or a PARALLEL consisting of such a SET and CLOBBERs.
1691 If INSN has CLOBBER parallel parts, ignore them for our processing.
1692 By definition, these happen during the execution of the insn. When it
1693 is merged with another insn, all bets are off. If they are, in fact,
1694 needed and aren't also supplied in I3, they may be added by
1695 recog_for_combine. Otherwise, it won't match.
1697 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1698 note.
1700 Get the source and destination of INSN. If more than one, can't
1701 combine. */
1707 {
1709 {
1713 {
1714 /* This is important to combine floating point insns
1715 for the SH4 port. */
1717 /* Combining an isolated USE doesn't make sense.
1718 We depend here on combinable_i3pat to reject them. */
1719 /* The code below this loop only verifies that the inputs of
1720 the SET in INSN do not change. We call reg_set_between_p
1721 to verify that the REG in the USE does not change between
1722 I3 and INSN.
1723 If the USE in INSN was for a pseudo register, the matching
1724 insn pattern will likely match any register; combining this
1725 with any other USE would only be safe if we knew that the
1726 used registers have identical values, or if there was
1727 something to tell them apart, e.g. different modes. For
1728 now, we forgo such complicated tests and simply disallow
1729 combining of USES of pseudo registers with any other USE. */
1732 {
1737 do
1738 {
1748 }
1750 }
1753 /* We can ignore CLOBBERs. */
1758 /* Ignore SETs whose result isn't used but not those that
1759 have side-effects. */
1765 /* If we have already found a SET, this is a second one and
1766 so we cannot combine with this insn. */
1774 /* Anything else means we can't combine. */
1776 }
1777 }
1780 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1781 so don't do anything with it. */
1784 }
1785 else
1794 /* Don't eliminate a store in the stack pointer. */
1796 /* Don't combine with an insn that sets a register to itself if it has
1797 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1799 /* Can't merge an ASM_OPERANDS. */
1801 /* Can't merge a function call. */
1803 /* Don't eliminate a function call argument. */
1809 /* Don't substitute into an incremented register. */
1813 /* Don't substitute into a non-local goto, this confuses CFG. */
1815 /* Make sure that DEST is not used after SUCC but before I3. */
1816 || (!all_adjacent
1817 && ((succ2
1821 /* Make sure that the value that is to be substituted for the register
1822 does not use any registers whose values alter in between. However,
1823 If the insns are adjacent, a use can't cross a set even though we
1824 think it might (this can happen for a sequence of insns each setting
1825 the same destination; last_set of that register might point to
1826 a NOTE). If INSN has a REG_EQUIV note, the register is always
1827 equivalent to the memory so the substitution is valid even if there
1828 are intervening stores. Also, don't move a volatile asm or
1829 UNSPEC_VOLATILE across any other insns. */
1830 || (! all_adjacent
1836 /* Don't combine across a CALL_INSN, because that would possibly
1837 change whether the life span of some REGs crosses calls or not,
1838 and it is a pain to update that information.
1839 Exception: if source is a constant, moving it later can't hurt.
1840 Accept that as a special case. */
1844 /* DEST must either be a REG or CC0. */
1846 {
1847 /* If register alignment is being enforced for multi-word items in all
1848 cases except for parameters, it is possible to have a register copy
1849 insn referencing a hard register that is not allowed to contain the
1850 mode being copied and which would not be valid as an operand of most
1851 insns. Eliminate this problem by not combining with such an insn.
1853 Also, on some machines we don't want to extend the life of a hard
1854 register. */
1859 /* Don't extend the life of a hard register unless it is
1860 user variable (if we have few registers) or it can't
1861 fit into the desired register (meaning something special
1862 is going on).
1863 Also avoid substituting a return register into I3, because
1864 reload can't handle a conflict with constraints of other
1865 inputs. */
1869 }
1877 {
1878 /* Don't substitute for a register intended as a clobberable
1879 operand. */
1884 /* If the clobber represents an earlyclobber operand, we must not
1885 substitute an expression containing the clobbered register.
1886 As we do not analyze the constraint strings here, we have to
1887 make the conservative assumption. However, if the register is
1888 a fixed hard reg, the clobber cannot represent any operand;
1889 we leave it up to the machine description to either accept or
1890 reject use-and-clobber patterns. */
1896 }
1898 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1899 or not), reject, unless nothing volatile comes between it and I3 */
1902 {
1903 /* Make sure neither succ nor succ2 contains a volatile reference. */
1908 /* We'll check insns between INSN and I3 below. */
1909 }
1911 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1912 to be an explicit register variable, and was chosen for a reason. */
1918 /* If INSN contains volatile references (specifically volatile MEMs),
1919 we cannot combine across any other volatile references.
1920 Even if INSN doesn't contain volatile references, any intervening
1921 volatile insn might affect machine state. */
1924 ? volatile_refs_p
1931 /* If INSN contains an autoincrement or autodecrement, make sure that
1932 register is not used between there and I3, and not already used in
1933 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1934 Also insist that I3 not be a jump; if it were one
1935 and the incremented register were spilled, we would lose. */
1937 #ifdef AUTO_INC_DEC
1952 #endif
1954 #ifdef HAVE_cc0
1955 /* Don't combine an insn that follows a CC0-setting insn.
1956 An insn that uses CC0 must not be separated from the one that sets it.
1957 We do, however, allow I2 to follow a CC0-setting insn if that insn
1958 is passed as I1; in that case it will be deleted also.
1959 We also allow combining in this case if all the insns are adjacent
1960 because that would leave the two CC0 insns adjacent as well.
1961 It would be more logical to test whether CC0 occurs inside I1 or I2,
1962 but that would be much slower, and this ought to be equivalent. */
1968 #endif
1970 /* If we get here, we have passed all the tests and the combination is
1971 to be allowed. */
1977 }
1978 \f
1979 /* LOC is the location within I3 that contains its pattern or the component
1980 of a PARALLEL of the pattern. We validate that it is valid for combining.
1982 One problem is if I3 modifies its output, as opposed to replacing it
1983 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1984 doing so would produce an insn that is not equivalent to the original insns.
1986 Consider:
1988 (set (reg:DI 101) (reg:DI 100))
1989 (set (subreg:SI (reg:DI 101) 0) <foo>)
1991 This is NOT equivalent to:
1993 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1994 (set (reg:DI 101) (reg:DI 100))])
1996 Not only does this modify 100 (in which case it might still be valid
1997 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1999 We can also run into a problem if I2 sets a register that I1
2000 uses and I1 gets directly substituted into I3 (not via I2). In that
2001 case, we would be getting the wrong value of I2DEST into I3, so we
2002 must reject the combination. This case occurs when I2 and I1 both
2003 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2004 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2005 of a SET must prevent combination from occurring. The same situation
2006 can occur for I0, in which case I0_NOT_IN_SRC is set.
2008 Before doing the above check, we first try to expand a field assignment
2009 into a set of logical operations.
2011 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2012 we place a register that is both set and used within I3. If more than one
2013 such register is detected, we fail.
2015 Return 1 if the combination is valid, zero otherwise. */
2017 static int
2020 {
2024 {
2029 rtx subdest;
2036 /* Check for the case where I3 modifies its output, as discussed
2037 above. We don't want to prevent pseudos from being combined
2038 into the address of a MEM, so only prevent the combination if
2039 i1 or i2 set the same MEM. */
2049 /* This is the same test done in can_combine_p except we can't test
2050 all_adjacent; we don't have to, since this instruction will stay
2051 in place, thus we are not considering increasing the lifetime of
2052 INNER_DEST.
2054 Also, if this insn sets a function argument, combining it with
2055 something that might need a spill could clobber a previous
2056 function argument; the all_adjacent test in can_combine_p also
2057 checks this; here, we do a more specific test for this case. */
2067 /* If DEST is used in I3, it is being killed in this insn, so
2068 record that for later. We have to consider paradoxical
2069 subregs here, since they kill the whole register, but we
2070 ignore partial subregs, STRICT_LOW_PART, etc.
2071 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2072 STACK_POINTER_REGNUM, since these are always considered to be
2073 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2083 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2085 #endif
2086 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2089 #endif
2091 {
2096 }
2097 }
2100 {
2107 }
2110 }
2111 \f
2112 /* Return 1 if X is an arithmetic expression that contains a multiplication
2113 and division. We don't count multiplications by powers of two here. */
2115 static int
2117 {
2119 {
2135 }
2136 }
2137 \f
2138 /* Determine whether INSN can be used in a combination. Return nonzero if
2139 not. This is used in try_combine to detect early some cases where we
2140 can't perform combinations. */
2142 static int
2144 {
2145 rtx set;
2148 /* If this isn't really an insn, we can't do anything.
2149 This can occur when flow deletes an insn that it has merged into an
2150 auto-increment address. */
2154 /* Never combine loads and stores involving hard regs that are likely
2155 to be spilled. The register allocator can usually handle such
2156 reg-reg moves by tying. If we allow the combiner to make
2157 substitutions of likely-spilled regs, reload might die.
2158 As an exception, we allow combinations involving fixed regs; these are
2159 not available to the register allocator so there's no risk involved. */
2180 }
2182 struct likely_spilled_retval_info
2183 {
2186 };
2188 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2189 hard registers that are known to be written to / clobbered in full. */
2190 static void
2192 {
2209 else
2212 }
2214 /* Return nonzero iff part of the return value is live during INSN, and
2215 it is likely spilled. This can happen when more than one insn is needed
2216 to copy the return value, e.g. when we consider to combine into the
2217 second copy insn for a complex value. */
2219 static int
2221 {
2225 /* We assume here that no machine mode needs more than
2226 32 hard registers when the value overlaps with a register
2227 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2242 /* Disregard parts of the return value that are set later. */
2251 /* Check if any of the (probably) live return value registers is
2252 likely spilled. */
2253 nregs --;
2254 do
2255 {
2261 }
2263 /* Adjust INSN after we made a change to its destination.
2265 Changing the destination can invalidate notes that say something about
2266 the results of the insn and a LOG_LINK pointing to the insn. */
2268 static void
2270 {
2271 /* For notes, be conservative and simply remove them. */
2274 /* The new insn will have a destination that was previously the destination
2275 of an insn just above it. Call distribute_links to make a LOG_LINK from
2276 the next use of that destination. */
2280 }
2282 /* Return TRUE if combine can reuse reg X in mode MODE.
2283 ADDED_SETS is nonzero if the original set is still required. */
2284 static bool
2286 {
2293 /* Allow hard registers if the new mode is legal, and occupies no more
2294 registers than the old mode. */
2300 /* Or a pseudo that is only used once. */
2303 }
2306 /* Check whether X, the destination of a set, refers to part of
2307 the register specified by REG. */
2309 static bool
2311 {
2312 /* Check that reg is an integer mode register. */
2323 }
2325 #ifdef AUTO_INC_DEC
2326 /* Replace auto-increment addressing modes with explicit operations to access
2327 the same addresses without modifying the corresponding registers. */
2329 static rtx
2331 {
2338 {
2349 /* SCRATCH must be shared because they represent distinct values. */
2380 mem_mode);
2384 }
2386 /* Copy the various flags, fields, and other information. We assume
2387 that all fields need copying, and then clear the fields that should
2388 not be copied. That is the sensible default behavior, and forces
2389 us to explicitly document why we are *not* copying a flag. */
2392 /* We do not copy the USED flag, which is used as a mark bit during
2393 walks over the RTL. */
2396 /* We do not copy FRAME_RELATED for INSNs. */
2405 {
2411 }
2414 }
2415 #endif
2417 /* Auxiliary data structure for propagate_for_debug_stmt. */
2419 struct rtx_subst_pair
2420 {
2421 rtx to;
2423 };
2425 /* DATA points to an rtx_subst_pair. Return the value that should be
2426 substituted. */
2428 static rtx
2430 {
2436 {
2438 #ifdef AUTO_INC_DEC
2440 #else
2442 #endif
2445 }
2447 }
2449 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2450 and LAST, not including INSN, but including LAST. Also stop at the end
2451 of THIS_BASIC_BLOCK. */
2453 static void
2455 {
2465 {
2469 {
2476 }
2477 }
2478 }
2480 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2481 Note that the INSN should be deleted *after* removing dead edges, so
2482 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2483 but not for a (set (pc) (label_ref FOO)). */
2485 static void
2487 {
2496 {
2497 rtx insn;
2501 /* Remove barriers from the footer if there are any. */
2504 {
2507 else
2511 }
2514 }
2515 }
2517 /* Try to combine the insns I0, I1 and I2 into I3.
2518 Here I0, I1 and I2 appear earlier than I3.
2519 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2520 I3.
2522 If we are combining more than two insns and the resulting insn is not
2523 recognized, try splitting it into two insns. If that happens, I2 and I3
2524 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2525 Otherwise, I0, I1 and I2 are pseudo-deleted.
2527 Return 0 if the combination does not work. Then nothing is changed.
2528 If we did the combination, return the insn at which combine should
2529 resume scanning.
2531 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2532 new direct jump instruction.
2534 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2535 been I3 passed to an earlier try_combine within the same basic
2536 block. */
2538 static rtx
2540 rtx last_combined_insn)
2541 {
2542 /* New patterns for I3 and I2, respectively. */
2546 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2547 dead. */
2549 /* Total number of SETs to put into I3. */
2551 /* Nonzero if I2's or I1's body now appears in I3. */
2553 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2555 /* Contains I3 if the destination of I3 is used in its source, which means
2556 that the old life of I3 is being killed. If that usage is placed into
2557 I2 and not in I3, a REG_DEAD note must be made. */
2559 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2561 /* Copy of SET_SRC of I1 and I0, if needed. */
2563 /* Set if I2DEST was reused as a scratch register. */
2565 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2567 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2572 /* Notes that must be added to REG_NOTES in I3 and I2. */
2574 /* Notes that we substituted I3 into I2 instead of the normal case. */
2576 /* Notes that I1, I2 or I3 is a MULT operation. */
2582 rtx temp;
2583 rtx link;
2585 rtx new_other_notes;
2588 /* Only try four-insn combinations when there's high likelihood of
2589 success. Look for simple insns, such as loads of constants or
2590 binary operations involving a constant. */
2592 {
2601 {
2604 rtx src;
2609 {
2612 }
2614 ngood++;
2617 nshift++;
2618 }
2621 }
2623 /* Exit early if one of the insns involved can't be used for
2624 combinations. */
2632 combine_attempts++;
2635 /* Reset the hard register usage information. */
2639 {
2646 else
2649 }
2651 /* If multiple insns feed into one of I2 or I3, they can be in any
2652 order. To simplify the code below, reorder them in sequence. */
2662 /* First check for one important special case that the code below will
2663 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2664 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2665 we may be able to replace that destination with the destination of I3.
2666 This occurs in the common code where we compute both a quotient and
2667 remainder into a structure, in which case we want to do the computation
2668 directly into the structure to avoid register-register copies.
2670 Note that this case handles both multiple sets in I2 and also cases
2671 where I2 has a number of CLOBBERs inside the PARALLEL.
2673 We make very conservative checks below and only try to handle the
2674 most common cases of this. For example, we only handle the case
2675 where I2 and I3 are adjacent to avoid making difficult register
2676 usage tests. */
2684 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2685 below would need to check what is inside (and reg_overlap_mentioned_p
2686 doesn't support those codes anyway). Don't allow those destinations;
2687 the resulting insn isn't likely to be recognized anyway. */
2693 {
2696 /* Make sure that the destination of I3,
2697 which we are going to substitute into one output of I2,
2698 is not used within another output of I2. We must avoid making this:
2699 (parallel [(set (mem (reg 69)) ...)
2700 (set (reg 69) ...)])
2701 which is not well-defined as to order of actions.
2702 (Besides, reload can't handle output reloads for this.)
2704 The problem can also happen if the dest of I3 is a memory ref,
2705 if another dest in I2 is an indirect memory ref. */
2717 {
2718 combine_merges++;
2728 /* Replace the dest in I2 with our dest and make the resulting
2729 insn the new pattern for I3. Then skip to where we validate
2730 the pattern. Everything was set up above. */
2735 }
2736 }
2738 /* If I2 is setting a pseudo to a constant and I3 is setting some
2739 sub-part of it to another constant, merge them by making a new
2740 constant. */
2749 {
2755 {
2758 {
2764 }
2765 }
2766 else
2767 {
2772 }
2775 {
2776 /* If this is the low part, we're done. */
2778 ;
2779 /* Handle the case where inner is twice the size of outer. */
2783 /* Otherwise give up for now. */
2784 else
2786 }
2791 {
2805 combine_merges++;
2812 /* Replace the source in I2 with the new constant and make the
2813 resulting insn the new pattern for I3. Then skip to where we
2814 validate the pattern. Everything was set up above. */
2820 /* The dest of I3 has been replaced with the dest of I2. */
2823 }
2824 }
2826 #ifndef HAVE_cc0
2827 /* If we have no I1 and I2 looks like:
2828 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2829 (set Y OP)])
2830 make up a dummy I1 that is
2831 (set Y OP)
2832 and change I2 to be
2833 (set (reg:CC X) (compare:CC Y (const_int 0)))
2835 (We can ignore any trailing CLOBBERs.)
2837 This undoes a previous combination and allows us to match a branch-and-
2838 decrement insn. */
2851 {
2857 {
2858 /* We make I1 with the same INSN_UID as I2. This gives it
2859 the same DF_INSN_LUID for value tracking. Our fake I1 will
2860 never appear in the insn stream so giving it the same INSN_UID
2861 as I2 will not cause a problem. */
2870 }
2871 }
2872 #endif
2874 /* Verify that I2 and I1 are valid for combining. */
2880 {
2883 }
2885 /* Record whether I2DEST is used in I2SRC and similarly for the other
2886 cases. Knowing this will help in register status updating below. */
2897 /* For the earlier insns, determine which of the subsequent ones they
2898 feed. */
2905 /* Ensure that I3's pattern can be the destination of combines. */
2911 {
2914 }
2916 /* See if any of the insns is a MULT operation. Unless one is, we will
2917 reject a combination that is, since it must be slower. Be conservative
2918 here. */
2926 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2927 We used to do this EXCEPT in one case: I3 has a post-inc in an
2928 output operand. However, that exception can give rise to insns like
2929 mov r3,(r3)+
2930 which is a famous insn on the PDP-11 where the value of r3 used as the
2931 source was model-dependent. Avoid this sort of thing. */
2933 #if 0
2939 /* It's not the exception. */
2940 #endif
2941 #ifdef AUTO_INC_DEC
2947 {
2950 }
2951 #endif
2953 /* See if the SETs in I1 or I2 need to be kept around in the merged
2954 instruction: whenever the value set there is still needed past I3.
2955 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2957 For the SET in I1, we have two cases: If I1 and I2 independently
2958 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2959 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2960 in I1 needs to be kept around unless I1DEST dies or is set in either
2961 I2 or I3. The same consideration applies to I0. */
2968 else
2975 else
2978 /* We are about to copy insns for the case where they need to be kept
2979 around. Check that they can be copied in the merged instruction. */
2985 {
2988 }
2990 /* If the set in I2 needs to be kept around, we must make a copy of
2991 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2992 PATTERN (I2), we are only substituting for the original I1DEST, not into
2993 an already-substituted copy. This also prevents making self-referential
2994 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2995 I2DEST. */
2998 {
3001 else
3003 }
3006 {
3009 else
3011 }
3014 {
3017 else
3019 }
3021 combine_merges++;
3023 /* Substitute in the latest insn for the regs set by the earlier ones. */
3029 #ifndef HAVE_cc0
3030 /* Many machines that don't use CC0 have insns that can both perform an
3031 arithmetic operation and set the condition code. These operations will
3032 be represented as a PARALLEL with the first element of the vector
3033 being a COMPARE of an arithmetic operation with the constant zero.
3034 The second element of the vector will set some pseudo to the result
3035 of the same arithmetic operation. If we simplify the COMPARE, we won't
3036 match such a pattern and so will generate an extra insn. Here we test
3037 for this case, where both the comparison and the operation result are
3038 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3039 I2SRC. Later we will make the PARALLEL that contains I2. */
3045 {
3046 #ifdef SELECT_CC_MODE
3049 #endif
3056 #ifdef SELECT_CC_MODE
3057 /* See if a COMPARE with the operand we substituted in should be done
3058 with the mode that is currently being used. If not, do the same
3059 processing we do in `subst' for a SET; namely, if the destination
3060 is used only once, try to replace it with a register of the proper
3061 mode and also replace the COMPARE. */
3068 {
3070 compare_mode))
3071 {
3073 rtx new_dest;
3077 else
3078 {
3081 }
3087 }
3088 else
3090 }
3091 #endif
3092 }
3093 else
3094 #endif
3095 {
3096 /* It is possible that the source of I2 or I1 may be performing
3097 an unneeded operation, such as a ZERO_EXTEND of something
3098 that is known to have the high part zero. Handle that case
3099 by letting subst look at the innermost one of them.
3101 Another way to do this would be to have a function that tries
3102 to simplify a single insn instead of merging two or more
3103 insns. We don't do this because of the potential of infinite
3104 loops and because of the potential extra memory required.
3105 However, doing it the way we are is a bit of a kludge and
3106 doesn't catch all cases.
3108 But only do this if -fexpensive-optimizations since it slows
3109 things down and doesn't usually win.
3111 This is not done in the COMPARE case above because the
3112 unmodified I2PAT is used in the PARALLEL and so a pattern
3113 with a modified I2SRC would not match. */
3116 {
3117 /* Pass pc_rtx so no substitutions are done, just
3118 simplifications. */
3120 {
3123 }
3124 else
3125 {
3128 }
3129 }
3134 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3135 copy of I2SRC each time we substitute it, in order to avoid creating
3136 self-referential RTL when we will be substituting I1SRC for I1DEST
3137 later. Likewise if I0 feeds into I2, either directly or indirectly
3138 through I1, and I0DEST is in I0SRC. */
3145 /* Record whether I2's body now appears within I3's body. */
3147 }
3149 /* If we already got a failure, don't try to do more. Otherwise, try to
3150 substitute I1 if we have it. */
3153 {
3154 /* Check that an autoincrement side-effect on I1 has not been lost.
3155 This happens if I1DEST is mentioned in I2 and dies there, and
3156 has disappeared from the new pattern. */
3158 && i1_feeds_i2_n
3161 /* Before we can do this substitution, we must redo the test done
3162 above (see detailed comments there) that ensures I1DEST isn't
3163 mentioned in any SETs in NEWPAT that are field assignments. */
3166 {
3169 }
3174 /* If the following substitution will modify I1SRC, make a copy of it
3175 for the case where it is substituted for I1DEST in I2PAT later. */
3179 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3180 copy of I1SRC each time we substitute it, in order to avoid creating
3181 self-referential RTL when we will be substituting I0SRC for I0DEST
3182 later. */
3187 /* Record whether I1's body now appears within I3's body. */
3189 }
3191 /* Likewise for I0 if we have it. */
3194 {
3201 {
3204 }
3206 /* If the following substitution will modify I0SRC, make a copy of it
3207 for the case where it is substituted for I0DEST in I1PAT later. */
3210 /* And a copy for I0DEST in I2PAT substitution. */
3219 }
3221 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3222 to count all the ways that I2SRC and I1SRC can be used. */
3233 /* Fail if we tried to make a new register. */
3235 /* Fail if we couldn't do something and have a CLOBBER. */
3237 /* Fail if this new pattern is a MULT and we didn't have one before
3238 at the outer level. */
3241 {
3244 }
3246 /* If the actions of the earlier insns must be kept
3247 in addition to substituting them into the latest one,
3248 we must make a new PARALLEL for the latest insn
3249 to hold additional the SETs. */
3252 {
3254 combine_extras++;
3257 {
3263 }
3264 else
3265 {
3270 }
3276 {
3282 }
3284 {
3293 }
3294 }
3296 validate_replacement:
3298 /* Note which hard regs this insn has as inputs. */
3301 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3302 consider splitting this pattern, we might need these clobbers. */
3305 {
3311 }
3313 /* Is the result of combination a valid instruction? */
3316 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3317 the second SET's destination is a register that is unused and isn't
3318 marked as an instruction that might trap in an EH region. In that case,
3319 we just need the first SET. This can occur when simplifying a divmod
3320 insn. We *must* test for this case here because the code below that
3321 splits two independent SETs doesn't handle this case correctly when it
3322 updates the register status.
3324 It's pointless doing this if we originally had two sets, one from
3325 i3, and one from i2. Combining then splitting the parallel results
3326 in the original i2 again plus an invalid insn (which we delete).
3327 The net effect is only to move instructions around, which makes
3328 debug info less accurate.
3330 Also check the case where the first SET's destination is unused.
3331 That would not cause incorrect code, but does cause an unneeded
3332 insn to remain. */
3341 {
3351 {
3354 }
3363 {
3369 }
3370 }
3372 /* If we were combining three insns and the result is a simple SET
3373 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3374 insns. There are two ways to do this. It can be split using a
3375 machine-specific method (like when you have an addition of a large
3376 constant) or by combine in the function find_split_point. */
3380 {
3383 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3384 use I2DEST as a scratch register will help. In the latter case,
3385 convert I2DEST to the mode of the source of NEWPAT if we can. */
3389 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3390 inputs of NEWPAT. */
3392 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3393 possible to try that as a scratch reg. This would require adding
3394 more code to make it work though. */
3397 {
3400 /* First try to split using the original register as a
3401 scratch register. */
3405 i2dest)));
3408 /* If that didn't work, try changing the mode of I2DEST if
3409 we can. */
3414 {
3416 rtx ni2dest;
3420 else
3421 {
3424 }
3426 parallel = (gen_rtx_PARALLEL
3430 ni2dest))));
3435 {
3443 }
3444 }
3447 }
3449 /* If recog_for_combine has discarded clobbers, try to use them
3450 again for the split. */
3452 {
3455 }
3458 {
3463 }
3467 {
3477 /* If I2 or I3 has multiple SETs, we won't know how to track
3478 register status, so don't use these insns. If I2's destination
3479 is used between I2 and I3, we also can't use these insns. */
3489 /* It is possible that both insns now set the destination of I3.
3490 If so, we must show an extra use of it. */
3493 {
3511 }
3512 }
3514 /* If we can split it and use I2DEST, go ahead and see if that
3515 helps things be recognized. Verify that none of the registers
3516 are set between I2 and I3. */
3519 #ifdef HAVE_cc0
3521 #endif
3522 /* We need I2DEST in the proper mode. If it is a hard register
3523 or the only use of a pseudo, we can change its mode.
3524 Make sure we don't change a hard register to have a mode that
3525 isn't valid for it, or change the number of registers. */
3532 /* We can't overwrite I2DEST if its value is still used by
3533 NEWPAT. */
3535 {
3544 /* *SPLIT may be part of I2SRC, so make sure we have the
3545 original expression around for later debug processing.
3546 We should not need I2SRC any more in other cases. */
3549 else
3552 /* Get NEWDEST as a register in the proper mode. We have already
3553 validated that we can do this. */
3555 {
3558 else
3559 {
3562 }
3563 }
3565 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3566 an ASHIFT. This can occur if it was inside a PLUS and hence
3567 appeared to be a memory address. This is a kludge. */
3572 {
3575 /* Update split_code because we may not have a multiply
3576 anymore. */
3578 }
3580 #ifdef INSN_SCHEDULING
3581 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3582 be written as a ZERO_EXTEND. */
3584 {
3585 #ifdef LOAD_EXTEND_OP
3586 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3587 what it really is. */
3592 else
3593 #endif
3596 }
3597 #endif
3599 /* Attempt to split binary operators using arithmetic identities. */
3603 {
3610 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3612 {
3617 }
3618 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3625 {
3631 /* Split both "((X op Y) op X) op Y" and
3632 "((X op Y) op Y) op X" as "T op T" where T is
3633 "X op Y". */
3636 {
3642 }
3643 /* Split "((X op X) op Y) op Y)" as "T op T" where
3644 T is "X op Y". */
3646 {
3652 }
3653 }
3654 }
3657 {
3660 }
3664 /* recog_for_combine might have added CLOBBERs to newi2pat.
3665 Make sure NEWPAT does not depend on the clobbered regs. */
3669 {
3672 {
3675 }
3676 }
3678 /* If the split point was a MULT and we didn't have one before,
3679 don't use one now. */
3682 }
3683 }
3685 /* Check for a case where we loaded from memory in a narrow mode and
3686 then sign extended it, but we need both registers. In that case,
3687 we have a PARALLEL with both loads from the same memory location.
3688 We can split this into a load from memory followed by a register-register
3689 copy. This saves at least one insn, more if register allocation can
3690 eliminate the copy.
3692 We cannot do this if the destination of the first assignment is a
3693 condition code register or cc0. We eliminate this case by making sure
3694 the SET_DEST and SET_SRC have the same mode.
3696 We cannot do this if the destination of the second assignment is
3697 a register that we have already assumed is zero-extended. Similarly
3698 for a SUBREG of such a register. */
3737 {
3738 rtx ni2dest;
3752 }
3754 /* Similarly, check for a case where we have a PARALLEL of two independent
3755 SETs but we started with three insns. In this case, we can do the sets
3756 as two separate insns. This case occurs when some SET allows two
3757 other insns to combine, but the destination of that SET is still live. */
3774 {
3775 /* Normally, it doesn't matter which of the two is done first,
3776 but the one that references cc0 can't be the second, and
3777 one which uses any regs/memory set in between i2 and i3 can't
3778 be first. */
3781 #ifdef HAVE_cc0
3783 #endif
3784 )
3785 {
3788 }
3791 #ifdef HAVE_cc0
3793 #endif
3794 )
3795 {
3798 }
3799 else
3800 {
3803 }
3808 {
3809 /* recog_for_combine might have added CLOBBERs to newi2pat.
3810 Make sure NEWPAT does not depend on the clobbered regs. */
3812 {
3815 {
3818 {
3821 }
3822 }
3823 }
3826 }
3827 }
3829 /* If it still isn't recognized, fail and change things back the way they
3830 were. */
3832 /* Is the result a reasonable ASM_OPERANDS? */
3834 {
3837 }
3839 /* If we had to change another insn, make sure it is valid also. */
3841 {
3849 {
3852 }
3853 }
3855 #ifdef HAVE_cc0
3856 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3857 they are adjacent to each other or not. */
3858 {
3862 {
3865 }
3866 }
3867 #endif
3869 /* Only allow this combination if insn_rtx_costs reports that the
3870 replacement instructions are cheaper than the originals. */
3872 {
3875 }
3878 {
3883 {
3888 /* Temporarily revert mode back. */
3892 {
3893 /* If we used i2dest as a scratch register with a
3894 different mode, substitute it for the original
3895 i2src while its original mode is temporarily
3896 restored, and then clear i2scratch so that we don't
3897 do it again later. */
3900 /* Put back the new mode. */
3902 }
3903 else
3904 {
3909 {
3912 }
3913 else
3914 {
3921 }
3923 /* We're dealing with a reg that changed mode but not
3924 meaning, so we want to turn it into a subreg for
3925 the new mode. However, because of REG sharing and
3926 because its mode had already changed, we have to do
3927 it in two steps. First, replace any debug uses of
3928 reg, with its original mode temporarily restored,
3929 with this copy we have created; then, replace the
3930 copy with the SUBREG of the original shared reg,
3931 once again changed to the new mode. */
3936 }
3937 }
3938 }
3940 /* If we will be able to accept this, we have made a
3941 change to the destination of I3. This requires us to
3942 do a few adjustments. */
3945 {
3948 }
3950 /* We now know that we can do this combination. Merge the insns and
3951 update the status of registers and LOG_LINKS. */
3954 {
3959 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3960 are still valid. Then add any non-duplicate notes added by
3961 recog_for_combine. */
3963 {
3969 }
3973 NULL_RTX);
3974 }
3977 {
3978 rtx insn;
3979 rtx link;
3980 rtx ni2dest;
3982 /* I3 now uses what used to be its destination and which is now
3983 I2's destination. This requires us to do a few adjustments. */
3987 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3988 so we still will.
3990 However, some later insn might be using I2's dest and have
3991 a LOG_LINK pointing at I3. We must remove this link.
3992 The simplest way to remove the link is to point it at I1,
3993 which we know will be a NOTE. */
3995 /* newi2pat is usually a SET here; however, recog_for_combine might
3996 have added some clobbers. */
3999 else
4006 {
4008 {
4015 }
4016 }
4017 }
4019 {
4025 /* Compute which registers we expect to eliminate. newi2pat may be setting
4026 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4027 same as i3dest, in which case newi2pat may be setting i1dest. */
4030 || !i2dest_killed
4034 || !i1dest_killed
4038 || !i0dest_killed
4041 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4042 clear them. */
4050 /* Ensure that we do not have something that should not be shared but
4051 occurs multiple times in the new insns. Check this by first
4052 resetting all the `used' flags and then copying anything is shared. */
4076 {
4083 {
4084 /* I2SRC must still be meaningful at this point. Some splitting
4085 operations can invalidate I2SRC, but those operations do not
4086 apply to calls. */
4089 }
4097 }
4102 /* We had one special case above where I2 had more than one set and
4103 we replaced a destination of one of those sets with the destination
4104 of I3. In that case, we have to update LOG_LINKS of insns later
4105 in this basic block. Note that this (expensive) case is rare.
4107 Also, in this case, we must pretend that all REG_NOTEs for I2
4108 actually came from I3, so that REG_UNUSED notes from I2 will be
4109 properly handled. */
4112 {
4130 {
4135 }
4136 else
4139 }
4147 {
4152 }
4153 else
4154 {
4158 }
4161 {
4167 }
4170 {
4176 }
4178 /* Get death notes for everything that is now used in either I3 or
4179 I2 and used to die in a previous insn. If we built two new
4180 patterns, move from I1 to I2 then I2 to I3 so that we get the
4181 proper movement on registers that I2 modifies. */
4187 else
4193 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4210 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4211 know these are REG_UNUSED and want them to go to the desired insn,
4212 so we always pass it as i3. */
4216 NULL_RTX);
4220 NULL_RTX);
4222 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4223 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4224 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4225 in that case, it might delete I2. Similarly for I2 and I1.
4226 Show an additional death due to the REG_DEAD note we make here. If
4227 we discard it in distribute_notes, we will decrement it again. */
4230 {
4233 NULL_RTX),
4235 else
4237 NULL_RTX),
4240 }
4243 {
4248 else
4251 }
4254 {
4259 else
4262 }
4265 {
4270 else
4273 }
4281 {
4282 rtx link;
4285 /* The insn that used to set this register doesn't exist, and
4286 this life of the register may not exist either. See if one of
4287 I3's links points to an insn that sets I2DEST. If it does,
4288 that is now the last known value for I2DEST. If we don't update
4289 this and I2 set the register to a value that depended on its old
4290 contents, we will get confused. If this insn is used, thing
4291 will be set correctly in combine_instructions. */
4300 /* If the reg formerly set in I2 died only once and that was in I3,
4301 zero its use count so it won't make `reload' do any work. */
4305 {
4308 }
4309 }
4312 {
4313 rtx link;
4326 }
4329 {
4330 rtx link;
4343 }
4345 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4346 been made to this insn. The order of
4347 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4348 can affect nonzero_bits of newpat */
4352 }
4355 {
4357 {
4360 }
4362 }
4365 {
4367 {
4370 }
4372 }
4375 {
4377 {
4380 }
4382 }
4385 {
4387 {
4390 }
4392 }
4395 {
4397 {
4400 }
4402 }
4404 /* Set new_direct_jump_p if a new return or simple jump instruction
4405 has been created. Adjust the CFG accordingly. */
4408 {
4412 }
4417 {
4420 }
4422 /* A noop might also need cleaning up of CFG, if it comes from the
4423 simplification of a jump. */
4427 {
4430 }
4436 {
4439 }
4441 combine_successes++;
4448 else
4450 }
4451 \f
4452 /* Undo all the modifications recorded in undobuf. */
4454 static void
4456 {
4460 {
4463 {
4475 }
4479 }
4482 }
4484 /* We've committed to accepting the changes we made. Move all
4485 of the undos to the free list. */
4487 static void
4489 {
4493 {
4497 }
4499 }
4500 \f
4501 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4502 where we have an arithmetic expression and return that point. LOC will
4503 be inside INSN.
4505 try_combine will call this function to see if an insn can be split into
4506 two insns. */
4510 {
4519 /* First special-case some codes. */
4521 {
4523 #ifdef INSN_SCHEDULING
4524 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4525 point. */
4528 #endif
4532 #ifdef HAVE_lo_sum
4533 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4534 using LO_SUM and HIGH. */
4537 {
4538 enum machine_mode address_mode
4546 }
4547 #endif
4549 /* If we have a PLUS whose second operand is a constant and the
4550 address is not valid, perhaps will can split it up using
4551 the machine-specific way to split large constants. We use
4552 the first pseudo-reg (one of the virtual regs) as a placeholder;
4553 it will not remain in the result. */
4558 {
4562 subst_insn);
4564 /* This should have produced two insns, each of which sets our
4565 placeholder. If the source of the second is a valid address,
4566 we can make put both sources together and make a split point
4567 in the middle. */
4580 && memory_address_addr_space_p
4583 {
4587 /* Replace the placeholder in SRC2 with SRC1. If we can
4588 find where in SRC2 it was placed, that can become our
4589 split point and we can replace this address with SRC2.
4590 Just try two obvious places. */
4601 {
4604 }
4605 }
4607 /* If that didn't work, perhaps the first operand is complex and
4608 needs to be computed separately, so make a split point there.
4609 This will occur on machines that just support REG + CONST
4610 and have a constant moved through some previous computation. */
4616 }
4618 /* If we have a PLUS whose first operand is complex, try computing it
4619 separately by making a split there. */
4630 #ifdef HAVE_cc0
4631 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4632 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4633 we need to put the operand into a register. So split at that
4634 point. */
4643 #endif
4645 /* See if we can split SET_SRC as it stands. */
4650 /* See if we can split SET_DEST as it stands. */
4655 /* See if this is a bitfield assignment with everything constant. If
4656 so, this is an IOR of an AND, so split it into that. */
4667 {
4673 unsigned HOST_WIDE_INT mask
4675 rtx or_mask;
4684 else
4685 {
4691 or_mask));
4692 }
4699 }
4701 /* Otherwise, see if this is an operation that we can split into two.
4702 If so, try to split that. */
4706 {
4708 /* If we are AND'ing with a large constant that is only a single
4709 bit and the result is only being used in a context where we
4710 need to know if it is zero or nonzero, replace it with a bit
4711 extraction. This will avoid the large constant, which might
4712 have taken more than one insn to make. If the constant were
4713 not a valid argument to the AND but took only one insn to make,
4714 this is no worse, but if it took more than one insn, it will
4715 be better. */
4725 {
4730 {
4733 }
4734 }
4738 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4739 is known to be on, this can be converted into a NEG of a shift. */
4745 {
4757 }
4763 /* We can't optimize if either mode is a partial integer
4764 mode as we don't know how many bits are significant
4765 in those modes. */
4779 {
4787 }
4792 }
4795 {
4798 /* For unsigned, we have a choice of a shift followed by an
4799 AND or two shifts. Use two shifts for field sizes where the
4800 constant might be too large. We assume here that we can
4801 always at least get 8-bit constants in an AND insn, which is
4802 true for every current RISC. */
4805 {
4808 gen_rtx_LSHIFTRT
4817 }
4818 else
4819 {
4821 gen_rtx_fmt_ee
4832 }
4833 }
4835 /* See if this is a simple operation with a constant as the second
4836 operand. It might be that this constant is out of range and hence
4837 could be used as a split point. */
4845 /* Finally, see if this is a simple operation with its first operand
4846 not in a register. The operation might require this operand in a
4847 register, so return it as a split point. We can always do this
4848 because if the first operand were another operation, we would have
4849 already found it as a split point. */
4858 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4859 it is better to write this as (not (ior A B)) so we can split it.
4860 Similarly for IOR. */
4862 {
4870 }
4872 /* Many RISC machines have a large set of logical insns. If the
4873 second operand is a NOT, put it first so we will try to split the
4874 other operand first. */
4876 {
4880 }
4885 /* Canonicalization can produce (minus A (mult B C)), where C is a
4886 constant. It may be better to try splitting (plus (mult B -C) A)
4887 instead if this isn't a multiply by a power of two. */
4891 {
4900 }
4902 /* Split at a multiply-accumulate instruction. However if this is
4903 the SET_SRC, we likely do not have such an instruction and it's
4904 worthless to try this split. */
4910 }
4912 /* Otherwise, select our actions depending on our rtx class. */
4914 {
4920 /* ... fall through ... */
4928 /* ... fall through ... */
4930 /* Some machines have (and (shift ...) ...) insns. If X is not
4931 an AND, but XEXP (X, 0) is, use it as our split point. */
4941 /* Otherwise, we don't have a split point. */
4943 }
4944 }
4945 \f
4946 /* Throughout X, replace FROM with TO, and return the result.
4947 The result is TO if X is FROM;
4948 otherwise the result is X, but its contents may have been modified.
4949 If they were modified, a record was made in undobuf so that
4950 undo_all will (among other things) return X to its original state.
4952 If the number of changes necessary is too much to record to undo,
4953 the excess changes are not made, so the result is invalid.
4954 The changes already made can still be undone.
4955 undobuf.num_undo is incremented for such changes, so by testing that
4956 the caller can tell whether the result is valid.
4958 `n_occurrences' is incremented each time FROM is replaced.
4960 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4962 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4963 by copying if `n_occurrences' is nonzero. */
4965 static rtx
4967 {
4972 rtx new_rtx;
4974 /* Two expressions are equal if they are identical copies of a shared
4975 RTX or if they are both registers with the same register number
4976 and mode. */
4978 #define COMBINE_RTX_EQUAL_P(X,Y) \
4979 ((X) == (Y) \
4980 || (REG_P (X) && REG_P (Y) \
4981 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4984 {
4985 n_occurrences++;
4987 }
4989 /* If X and FROM are the same register but different modes, they
4990 will not have been seen as equal above. However, the log links code
4991 will make a LOG_LINKS entry for that case. If we do nothing, we
4992 will try to rerecognize our original insn and, when it succeeds,
4993 we will delete the feeding insn, which is incorrect.
4995 So force this insn not to match in this (rare) case. */
5000 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5001 of which may contain things that can be combined. */
5005 /* It is possible to have a subexpression appear twice in the insn.
5006 Suppose that FROM is a register that appears within TO.
5007 Then, after that subexpression has been scanned once by `subst',
5008 the second time it is scanned, TO may be found. If we were
5009 to scan TO here, we would find FROM within it and create a
5010 self-referent rtl structure which is completely wrong. */
5014 /* Parallel asm_operands need special attention because all of the
5015 inputs are shared across the arms. Furthermore, unsharing the
5016 rtl results in recognition failures. Failure to handle this case
5017 specially can result in circular rtl.
5019 Solve this by doing a normal pass across the first entry of the
5020 parallel, and only processing the SET_DESTs of the subsequent
5021 entries. Ug. */
5026 {
5029 /* If this substitution failed, this whole thing fails. */
5037 {
5043 {
5046 /* If this substitution failed, this whole thing fails. */
5052 }
5053 }
5054 }
5055 else
5056 {
5060 /* We don't need to process a SET_DEST that is a register, CC0,
5061 or PC, so set up to skip this common case. All other cases
5062 where we want to suppress replacing something inside a
5063 SET_SRC are handled via the IN_DEST operand. */
5070 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5071 constant. */
5076 {
5078 {
5081 {
5083 {
5086 n_occurrences++;
5087 }
5088 else
5089 {
5091 unique_copy);
5093 /* If this substitution failed, this whole thing
5094 fails. */
5098 }
5101 }
5102 }
5104 {
5105 /* If this is a register being set, ignore it. */
5112 ;
5115 {
5116 /* In general, don't install a subreg involving two
5117 modes not tieable. It can worsen register
5118 allocation, and can even make invalid reload
5119 insns, since the reg inside may need to be copied
5120 from in the outside mode, and that may be invalid
5121 if it is an fp reg copied in integer mode.
5123 We allow two exceptions to this: It is valid if
5124 it is inside another SUBREG and the mode of that
5125 SUBREG and the mode of the inside of TO is
5126 tieable and it is valid if X is a SET that copies
5127 FROM to CC0. */
5135 #ifdef HAVE_cc0
5137 #endif
5138 )
5141 #ifdef CANNOT_CHANGE_MODE_CLASS
5149 #endif
5152 n_occurrences++;
5153 }
5154 else
5155 /* If we are in a SET_DEST, suppress most cases unless we
5156 have gone inside a MEM, in which case we want to
5157 simplify the address. We assume here that things that
5158 are actually part of the destination have their inner
5159 parts in the first expression. This is true for SUBREG,
5160 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5161 things aside from REG and MEM that should appear in a
5162 SET_DEST. */
5164 (((in_dest
5170 /* If we found that we will have to reject this combination,
5171 indicate that by returning the CLOBBER ourselves, rather than
5172 an expression containing it. This will speed things up as
5173 well as prevent accidents where two CLOBBERs are considered
5174 to be equal, thus producing an incorrect simplification. */
5182 {
5190 }
5193 {
5197 }
5198 else
5200 }
5201 }
5202 }
5204 /* Check if we are loading something from the constant pool via float
5205 extension; in this case we would undo compress_float_constant
5206 optimization and degenerate constant load to an immediate value. */
5210 {
5214 }
5216 /* Try to simplify X. If the simplification changed the code, it is likely
5217 that further simplification will help, so loop, but limit the number
5218 of repetitions that will be performed. */
5221 {
5222 /* If X is sufficiently simple, don't bother trying to do anything
5223 with it. */
5232 /* We no longer know the original mode of operand 0 since we
5233 have changed the form of X) */
5235 }
5238 }
5239 \f
5240 /* Simplify X, a piece of RTL. We just operate on the expression at the
5241 outer level; call `subst' to simplify recursively. Return the new
5242 expression.
5244 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5245 if we are inside a SET_DEST. */
5247 static rtx
5249 {
5252 rtx temp;
5255 /* If this is a commutative operation, put a constant last and a complex
5256 expression first. We don't need to do this for comparisons here. */
5259 {
5263 }
5265 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5266 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5267 things. Check for cases where both arms are testing the same
5268 condition.
5270 Don't do anything if all operands are very simple. */
5283 {
5288 /* If everything is a comparison, what we have is highly unlikely
5289 to be simpler, so don't use it. */
5292 {
5299 /* Simplify the alternative arms; this may collapse the true and
5300 false arms to store-flag values. Be careful to use copy_rtx
5301 here since true_rtx or false_rtx might share RTL with x as a
5302 result of the if_then_else_cond call above. */
5306 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5307 is unlikely to be simpler. */
5310 {
5313 /* Restarting if we generate a store-flag expression will cause
5314 us to loop. Just drop through in this case. */
5316 /* If the result values are STORE_FLAG_VALUE and zero, we can
5317 just make the comparison operation. */
5328 /* Likewise, we can make the negate of a comparison operation
5329 if the result values are - STORE_FLAG_VALUE and zero. */
5337 mode);
5348 mode);
5349 else
5352 mode,
5353 VOIDmode,
5354 cond,
5355 cop1),
5360 }
5361 }
5362 }
5364 /* Try to fold this expression in case we have constants that weren't
5365 present before. */
5368 {
5376 {
5379 {
5383 }
5386 }
5399 }
5402 {
5407 }
5409 /* First see if we can apply the inverse distributive law. */
5412 {
5416 }
5418 /* If CODE is an associative operation not otherwise handled, see if we
5419 can associate some operands. This can win if they are constants or
5420 if they are logically related (i.e. (a & b) & a). */
5426 {
5428 {
5432 rtx inner;
5434 /* Make sure we pass the constant operand if any as the second
5435 one if this is a commutative operation. */
5437 {
5441 }
5447 /* For commutative operations, try the other pair if that one
5448 didn't simplify. */
5450 {
5455 }
5459 }
5460 }
5462 /* A little bit of algebraic simplification here. */
5464 {
5466 /* Ensure that our address has any ASHIFTs converted to MULT in case
5467 address-recognizing predicates are called later. */
5476 /* See if this can be moved to simplify_subreg. */
5479 /* Don't call gen_lowpart if the inner mode
5480 is VOIDmode and we cannot simplify it, as SUBREG without
5481 inner mode is invalid. */
5488 {
5489 rtx temp;
5494 }
5496 /* Don't change the mode of the MEM if that would change the meaning
5497 of the address. */
5503 /* Note that we cannot do any narrowing for non-constants since
5504 we might have been counting on using the fact that some bits were
5505 zero. We now do this in the SET. */
5512 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5513 replaced by (lshiftrt X C). This will convert
5514 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5522 /* If X has only a single bit that might be nonzero, say, bit I, convert
5523 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5524 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5525 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5526 or a SUBREG of one since we'd be making the expression more
5527 complex if it was just a register. */
5533 {
5534 rtx temp1 = simplify_shift_const
5540 /* If all we did was surround TEMP with the two shifts, we
5541 haven't improved anything, so don't use it. Otherwise,
5542 we are better off with TEMP1. */
5547 }
5551 /* We can't handle truncation to a partial integer mode here
5552 because we don't know the real bitsize of the partial
5553 integer mode. */
5562 /* We can truncate a constant value and return it. */
5566 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5567 whose value is a comparison can be replaced with a subreg if
5568 STORE_FLAG_VALUE permits. */
5577 /* (const (const X)) can become (const X). Do it this way rather than
5578 returning the inner CONST since CONST can be shared with a
5579 REG_EQUAL note. */
5584 #ifdef HAVE_lo_sum
5586 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5587 can add in an offset. find_split_point will split this address up
5588 again if it doesn't match. */
5593 #endif
5596 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5597 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5598 bit-field and can be replaced by either a sign_extend or a
5599 sign_extract. The `and' may be a zero_extend and the two
5600 <c>, -<c> constants may be reversed. */
5615 return simplify_shift_const
5622 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5623 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5624 the bitsize of the mode - 1. This allows simplification of
5625 "a = (b & 8) == 0;" */
5637 /* If we are adding two things that have no bits in common, convert
5638 the addition into an IOR. This will often be further simplified,
5639 for example in cases like ((a & 1) + (a & 2)), which can
5640 become a & 3. */
5645 {
5646 /* Try to simplify the expression further. */
5650 /* If we could, great. If not, do not go ahead with the IOR
5651 replacement, since PLUS appears in many special purpose
5652 address arithmetic instructions. */
5655 }
5659 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5660 (and <foo> (const_int pow2-1)) */
5670 /* If we have (mult (plus A B) C), apply the distributive law and then
5671 the inverse distributive law to see if things simplify. This
5672 occurs mostly in addresses, often when unrolling loops. */
5675 {
5679 }
5681 /* Try simplify a*(b/c) as (a*b)/c. */
5684 {
5690 }
5694 /* If this is a divide by a power of two, treat it as a shift if
5695 its first operand is a shift. */
5713 /* If the first operand is a condition code, we can't do anything
5714 with it. */
5718 {
5726 /* Simplify our comparison, if possible. */
5729 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5730 if only the low-order bit is possibly nonzero in X (such as when
5731 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5732 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5733 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5734 (plus X 1).
5736 Remove any ZERO_EXTRACT we made when thinking this was a
5737 comparison. It may now be simpler to use, e.g., an AND. If a
5738 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5739 the call to make_compound_operation in the SET case. */
5755 {
5759 mode);
5760 }
5767 {
5771 const1_rtx);
5772 }
5780 {
5783 }
5785 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5786 those above. */
5800 {
5804 mode);
5805 }
5813 {
5817 mode);
5818 }
5820 /* If X is 0/1, (eq X 0) is X-1. */
5826 {
5829 }
5831 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5832 one bit that might be nonzero, we can convert (ne x 0) to
5833 (ashift x c) where C puts the bit in the sign bit. Remove any
5834 AND with STORE_FLAG_VALUE when we are done, since we are only
5835 going to test the sign bit. */
5843 {
5849 else
5851 }
5853 /* If the code changed, return a whole new comparison. */
5857 /* Otherwise, keep this operation, but maybe change its operands.
5858 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5861 }
5871 /* If we are processing SET_DEST, we are done. */
5889 /* If this is a shift by a constant amount, simplify it. */
5905 }
5908 }
5909 \f
5910 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5912 static rtx
5914 {
5921 rtx temp;
5924 rtx reversed;
5926 /* Simplify storing of the truth value. */
5931 /* Also when the truth value has to be reversed. */
5937 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5938 in it is being compared against certain values. Get the true and false
5939 comparisons and see if that says anything about the value of each arm. */
5945 {
5946 HOST_WIDE_INT nzb;
5952 /* If FALSE_CODE is EQ, swap the codes and arms. */
5955 {
5958 }
5960 /* If we are comparing against zero and the expression being tested has
5961 only a single bit that might be nonzero, that is its value when it is
5962 not equal to zero. Similarly if it is known to be -1 or 0. */
5966 {
5969 }
5973 {
5976 }
5978 /* Now simplify an arm if we know the value of the register in the
5979 branch and it is used in the arm. Be careful due to the potential
5980 of locally-shared RTL. */
5997 }
5999 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6000 reversed, do so to avoid needing two sets of patterns for
6001 subtract-and-branch insns. Similarly if we have a constant in the true
6002 arm, the false arm is the same as the first operand of the comparison, or
6003 the false arm is more complicated than the true arm. */
6016 {
6025 /* It is possible that the conditional has been simplified out. */
6028 }
6030 /* If the two arms are identical, we don't need the comparison. */
6035 /* Convert a == b ? b : a to "a". */
6047 /* Look for cases where we have (abs x) or (neg (abs X)). */
6050 && comparison_p
6057 {
6063 return
6066 mode);
6069 }
6071 /* Look for MIN or MAX. */
6074 && comparison_p
6079 {
6094 }
6096 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6097 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6098 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6099 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6100 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6101 neither 1 or -1, but it isn't worth checking for. */
6104 && comparison_p
6107 {
6123 /* If an identity-zero op is commutative, check whether there
6124 would be a match if we swapped the operands. */
6144 {
6148 }
6160 {
6164 }
6180 {
6184 }
6196 {
6200 }
6203 {
6209 const_true_rtx));
6217 }
6218 }
6220 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6221 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6222 negation of a single bit, we can convert this operation to a shift. We
6223 can actually do this more generally, but it doesn't seem worth it. */
6232 return
6236 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6246 }
6247 \f
6248 /* Simplify X, a SET expression. Return the new expression. */
6250 static rtx
6252 {
6255 enum machine_mode mode
6257 rtx other_insn;
6260 /* (set (pc) (return)) gets written as (return). */
6264 /* Now that we know for sure which bits of SRC we are using, see if we can
6265 simplify the expression for the object knowing that we only need the
6266 low-order bits. */
6270 {
6273 }
6275 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6276 the comparison result and try to simplify it unless we already have used
6277 undobuf.other_insn. */
6285 {
6294 else
6302 {
6306 }
6307 else
6308 {
6313 /* Attempt to simplify CC user. */
6315 {
6319 }
6321 /* Convert X into a no-op move. */
6325 }
6327 /* Simplify our comparison, if possible. */
6330 #ifdef SELECT_CC_MODE
6331 /* If this machine has CC modes other than CCmode, check to see if we
6332 need to use a different CC mode here. */
6335 else
6338 #ifndef HAVE_cc0
6339 /* If the mode changed, we have to change SET_DEST, the mode in the
6340 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6341 a hard register, just build new versions with the proper mode. If it
6342 is a pseudo, we lose unless it is only time we set the pseudo, in
6343 which case we can safely change its mode. */
6345 {
6347 {
6349 rtx new_dest;
6353 else
6354 {
6357 }
6364 }
6365 }
6369 /* If the code changed, we have to build a new comparison in
6370 undobuf.other_insn. */
6372 {
6381 /* If the only change we made was to change an EQ into an NE or
6382 vice versa, OP0 has only one bit that might be nonzero, and OP1
6383 is zero, check if changing the user of the condition code will
6384 produce a valid insn. If it won't, we can keep the original code
6385 in that insn by surrounding our operation with an XOR. */
6392 {
6397 {
6403 }
6404 }
6405 }
6410 /* Otherwise, if we didn't previously have a COMPARE in the
6411 correct mode, we need one. */
6413 {
6416 }
6418 {
6421 }
6422 /* Otherwise, update the COMPARE if needed. */
6424 {
6427 }
6428 }
6429 else
6430 {
6431 /* Get SET_SRC in a form where we have placed back any
6432 compound expressions. Then do the checks below. */
6435 }
6437 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6438 and X being a REG or (subreg (reg)), we may be able to convert this to
6439 (set (subreg:m2 x) (op)).
6441 We can always do this if M1 is narrower than M2 because that means that
6442 we only care about the low bits of the result.
6444 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6445 perform a narrower operation than requested since the high-order bits will
6446 be undefined. On machine where it is defined, this transformation is safe
6447 as long as M1 and M2 have the same number of words. */
6455 #ifndef WORD_REGISTER_OPERATIONS
6458 #endif
6459 #ifdef CANNOT_CHANGE_MODE_CLASS
6464 #endif
6468 {
6471 dest));
6475 }
6477 #ifdef HAVE_cc0
6478 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6479 in SRC. */
6485 {
6489 /* Here we make sure that we don't have a sign bit on. */
6494 {
6497 }
6498 }
6499 #endif
6501 #ifdef LOAD_EXTEND_OP
6502 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6503 would require a paradoxical subreg. Replace the subreg with a
6504 zero_extend to avoid the reload that would otherwise be required. */
6513 {
6519 }
6520 #endif
6522 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6523 are comparing an item known to be 0 or -1 against 0, use a logical
6524 operation instead. Check for one of the arms being an IOR of the other
6525 arm with some value. We compute three terms to be IOR'ed together. In
6526 practice, at most two will be nonzero. Then we do the IOR's. */
6534 #ifdef HAVE_conditional_move
6536 #endif
6541 {
6567 false_rtx);
6573 term3));
6576 }
6578 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6579 whole thing fail. */
6584 else
6585 /* Convert this into a field assignment operation, if possible. */
6587 }
6588 \f
6589 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6590 result. */
6592 static rtx
6594 {
6600 {
6602 /* We can call simplify_and_const_int only if we don't lose
6603 any (sign) bits when converting INTVAL (op1) to
6604 "unsigned HOST_WIDE_INT". */
6608 {
6615 }
6617 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6618 apply the distributive law and then the inverse distributive
6619 law to see if things simplify. */
6621 {
6625 }
6627 {
6631 }
6635 /* If we have (ior (and A B) C), apply the distributive law and then
6636 the inverse distributive law to see if things simplify. */
6639 {
6643 }
6646 {
6650 }
6655 }
6658 }
6659 \f
6660 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6661 operations" because they can be replaced with two more basic operations.
6662 ZERO_EXTEND is also considered "compound" because it can be replaced with
6663 an AND operation, which is simpler, though only one operation.
6665 The function expand_compound_operation is called with an rtx expression
6666 and will convert it to the appropriate shifts and AND operations,
6667 simplifying at each stage.
6669 The function make_compound_operation is called to convert an expression
6670 consisting of shifts and ANDs into the equivalent compound expression.
6671 It is the inverse of this function, loosely speaking. */
6673 static rtx
6675 {
6679 rtx tem;
6682 {
6686 /* We can't necessarily use a const_int for a multiword mode;
6687 it depends on implicitly extending the value.
6688 Since we don't know the right way to extend it,
6689 we can't tell whether the implicit way is right.
6691 Even for a mode that is no wider than a const_int,
6692 we can't win, because we need to sign extend one of its bits through
6693 the rest of it, and we don't know which bit. */
6697 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6698 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6699 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6700 reloaded. If not for that, MEM's would very rarely be safe.
6702 Reject MODEs bigger than a word, because we might not be able
6703 to reference a two-register group starting with an arbitrary register
6704 (and currently gen_lowpart might crash for a SUBREG). */
6709 /* Reject MODEs that aren't scalar integers because turning vector
6710 or complex modes into shifts causes problems. */
6716 /* If the inner object has VOIDmode (the only way this can happen
6717 is if it is an ASM_OPERANDS), we can't do anything since we don't
6718 know how much masking to do. */
6727 /* ... fall through ... */
6730 /* If the operand is a CLOBBER, just return it. */
6739 /* Reject MODEs that aren't scalar integers because turning vector
6740 or complex modes into shifts causes problems. */
6748 /* This should stay within the object being extracted, fail otherwise. */
6759 }
6760 /* Convert sign extension to zero extension, if we know that the high
6761 bit is not set, as this is easier to optimize. It will be converted
6762 back to cheaper alternative in make_extraction. */
6770 {
6774 /* Make sure this is a profitable operation. */
6781 else
6783 }
6785 /* We can optimize some special cases of ZERO_EXTEND. */
6787 {
6788 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6789 know that the last value didn't have any inappropriate bits
6790 set. */
6798 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6807 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6808 is a comparison and STORE_FLAG_VALUE permits. This is like
6809 the first case, but it works even when GET_MODE (x) is larger
6810 than HOST_WIDE_INT. */
6819 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6829 }
6831 /* If we reach here, we want to return a pair of shifts. The inner
6832 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6833 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6834 logical depending on the value of UNSIGNEDP.
6836 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6837 converted into an AND of a shift.
6839 We must check for the case where the left shift would have a negative
6840 count. This can happen in a case like (x >> 31) & 255 on machines
6841 that can't shift by a constant. On those machines, we would first
6842 combine the shift with the AND to produce a variable-position
6843 extraction. Then the constant of 31 would be substituted in
6844 to produce such a position. */
6848 {
6857 }
6864 else
6865 /* Any other cases we can't handle. */
6868 /* If we couldn't do this for some reason, return the original
6869 expression. */
6874 }
6875 \f
6876 /* X is a SET which contains an assignment of one object into
6877 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6878 or certain SUBREGS). If possible, convert it into a series of
6879 logical operations.
6881 We half-heartedly support variable positions, but do not at all
6882 support variable lengths. */
6884 static const_rtx
6886 {
6887 rtx inner;
6893 /* Loop until we find something we can't simplify. */
6895 {
6898 {
6902 }
6905 {
6910 /* A constant position should stay within the width of INNER. */
6916 {
6924 /* If position is ADJUST - X, new position is X. */
6926 else
6931 pos);
6932 }
6933 }
6935 /* A SUBREG between two modes that occupy the same numbers of words
6936 can be done by moving the SUBREG to the source. */
6938 /* We need SUBREGs to compute nonzero_bits properly. */
6939 && nonzero_sign_valid
6944 {
6946 gen_lowpart
6950 }
6951 else
6959 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6961 {
6964 /* Don't do anything for vector or complex integral types. */
6968 /* Try to find an integral mode to pun with. */
6975 }
6977 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6981 /* Now compute the equivalent expression. Make a copy of INNER
6982 for the SET_DEST in case it is a MEM into which we will substitute;
6983 we don't want shared RTL in that case. */
6988 compute_mode,
6990 compute_mode),
6991 inner);
6996 mask),
6997 pos);
7002 }
7005 }
7006 \f
7007 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7008 it is an RTX that represents a variable starting position; otherwise,
7009 POS is the (constant) starting bit position (counted from the LSB).
7011 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7012 signed reference.
7014 IN_DEST is nonzero if this is a reference in the destination of a
7015 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7016 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7017 be used.
7019 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7020 ZERO_EXTRACT should be built even for bits starting at bit 0.
7022 MODE is the desired mode of the result (if IN_DEST == 0).
7024 The result is an RTX for the extraction or NULL_RTX if the target
7025 can't handle it. */
7027 static rtx
7031 {
7032 /* This mode describes the size of the storage area
7033 to fetch the overall value from. Within that, we
7034 ignore the POS lowest bits, etc. */
7044 HOST_WIDE_INT orig_pos;
7047 {
7048 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7049 consider just the QI as the memory to extract from.
7050 The subreg adds or removes high bits; its mode is
7051 irrelevant to the meaning of this extraction,
7052 since POS and LEN count from the lsb. */
7056 }
7061 {
7062 /* We're extracting the least significant bits of an rtx
7063 (ashift X (const_int C)), where LEN > C. Extract the
7064 least significant (LEN - C) bits of X, giving an rtx
7065 whose mode is MODE, then shift it left C times. */
7071 }
7078 /* See if this can be done without an extraction. We never can if the
7079 width of the field is not the same as that of some integer mode. For
7080 registers, we can only avoid the extraction if the position is at the
7081 low-order bit and this is either not in the destination or we have the
7082 appropriate STRICT_LOW_PART operation available.
7084 For MEM, we can avoid an extract if the field starts on an appropriate
7085 boundary and we can change the mode of the memory reference. */
7095 && (! in_dest
7099 && (pos
7102 /* We can't do this if we are widening INNER_MODE (it
7103 may not be aligned, for one thing). */
7108 {
7109 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7110 field. If the original and current mode are the same, we need not
7111 adjust the offset. Otherwise, we do if bytes big endian.
7113 If INNER is not a MEM, get a piece consisting of just the field
7114 of interest (in this case POS % BITS_PER_WORD must be 0). */
7117 {
7118 HOST_WIDE_INT offset;
7120 /* POS counts from lsb, but make OFFSET count in memory order. */
7123 else
7127 }
7129 {
7131 {
7132 /* We can't call gen_lowpart in a DEST since we
7133 always want a SUBREG (see below) and it would sometimes
7134 return a new hard register. */
7136 {
7151 /* Avoid creating invalid subregs, for example when
7152 simplifying (x>>32)&255. */
7157 }
7158 else
7160 }
7161 else
7163 }
7164 else
7166 len >= HOST_BITS_PER_WIDE_INT
7171 /* If this extraction is going into the destination of a SET,
7172 make a STRICT_LOW_PART unless we made a MEM. */
7188 /* If we know that no extraneous bits are set, and that the high
7189 bit is not set, convert the extraction to the cheaper of
7190 sign and zero extension, that are equivalent in these cases. */
7198 {
7202 /* Prefer ZERO_EXTENSION, since it gives more information to
7203 backends. */
7208 }
7210 /* Otherwise, sign- or zero-extend unless we already are in the
7211 proper mode. */
7215 }
7217 /* Unless this is a COMPARE or we have a funny memory reference,
7218 don't do anything with zero-extending field extracts starting at
7219 the low-order bit since they are simple AND operations. */
7224 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7225 if the position is not a constant and the length is not 1. In all
7226 other cases, we would only be going outside our object in cases when
7227 an original shift would have been undefined. */
7233 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7234 and the mode for the result. */
7236 {
7240 }
7244 {
7248 }
7252 {
7256 }
7258 /* Never narrow an object, since that might not be safe. */
7268 /* If this is not from memory, the desired mode is the preferred mode
7269 for an extraction pattern's first input operand, or word_mode if there
7270 is none. */
7273 else
7274 {
7275 /* Be careful not to go beyond the extracted object and maintain the
7276 natural alignment of the memory. */
7280 {
7283 }
7285 /* If we have to change the mode of memory and cannot, the desired mode
7286 is EXTRACTION_MODE. */
7292 }
7297 {
7298 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7299 BITS_BIG_ENDIAN style. If position is constant, compute new
7300 position. Otherwise, build subtraction.
7301 Note that POS is relative to the mode of the original argument.
7302 If it's a MEM we need to recompute POS relative to that.
7303 However, if we're extracting from (or inserting into) a register,
7304 we want to recompute POS relative to wanted_inner_mode. */
7311 else
7312 pos_rtx
7314 /* POS may be less than 0 now, but we check for that below.
7315 Note that it can only be less than 0 if !MEM_P (inner). */
7316 }
7318 /* If INNER has a wider mode, and this is a constant extraction, try to
7319 make it smaller and adjust the byte to point to the byte containing
7320 the value. */
7323 && ! pos_rtx
7328 {
7331 /* The computations below will be correct if the machine is big
7332 endian in both bits and bytes or little endian in bits and bytes.
7333 If it is mixed, we must adjust. */
7335 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7336 adjust OFFSET to compensate. */
7341 /* We can now move to the desired byte. */
7352 }
7354 /* If INNER is not memory, get it into the proper mode. If we are changing
7355 its mode, POS must be a constant and smaller than the size of the new
7356 mode. */
7358 {
7359 /* On the LHS, don't create paradoxical subregs implicitely truncating
7360 the register unless TRULY_NOOP_TRUNCATION. */
7375 pos_rtx
7381 }
7383 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7384 have to zero extend. Otherwise, we can just use a SUBREG. */
7387 {
7390 /* If we know that no extraneous bits are set, and that the high
7391 bit is not set, convert extraction to cheaper one - either
7392 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7393 cases. */
7401 {
7404 /* Prefer ZERO_EXTENSION, since it gives more information to
7405 backends. */
7409 }
7411 }
7416 /* Make POS_RTX unless we already have it and it is correct. If we don't
7417 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7418 be a CONST_INT. */
7425 /* Make the required operation. See if we can use existing rtx. */
7432 }
7433 \f
7434 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7435 with any other operations in X. Return X without that shift if so. */
7437 static rtx
7439 {
7442 rtx tem;
7445 {
7447 /* This is the shift itself. If it is wide enough, we will return
7448 either the value being shifted if the shift count is equal to
7449 COUNT or a shift for the difference. */
7463 /* If we can safely shift this constant and we find the inner shift,
7464 make a new operation. */
7476 }
7479 }
7480 \f
7481 /* Look at the expression rooted at X. Look for expressions
7482 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7483 Form these expressions.
7485 Return the new rtx, usually just X.
7487 Also, for machines like the VAX that don't have logical shift insns,
7488 try to convert logical to arithmetic shift operations in cases where
7489 they are equivalent. This undoes the canonicalizations to logical
7490 shifts done elsewhere.
7492 We try, as much as possible, to re-use rtl expressions to save memory.
7494 IN_CODE says what kind of expression we are processing. Normally, it is
7495 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7496 being kludges), it is MEM. When processing the arguments of a comparison
7497 or a COMPARE against zero, it is COMPARE. */
7499 static rtx
7501 {
7509 rtx tem;
7512 /* Select the code to be used in recursive calls. Once we are inside an
7513 address, we stay there. If we have a comparison, set to COMPARE,
7514 but once inside, go back to our default of SET. */
7523 /* Process depending on the code of this operation. If NEW is set
7524 nonzero, it will be returned. */
7527 {
7529 /* Convert shifts by constants into multiplications if inside
7530 an address. */
7535 {
7541 {
7544 }
7547 }
7557 {
7561 }
7564 {
7568 mode));
7570 }
7571 else
7572 {
7576 }
7587 {
7591 }
7594 {
7598 mode));
7600 }
7601 else
7602 {
7606 }
7610 /* If the second operand is not a constant, we can't do anything
7611 with it. */
7615 /* If the constant is a power of two minus one and the first operand
7616 is a logical right shift, make an extraction. */
7619 {
7623 }
7625 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7630 {
7632 next_code);
7636 }
7637 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7643 {
7644 /* Apply the distributive law, and then try to make extractions. */
7651 }
7653 /* If we are have (and (rotate X C) M) and C is larger than the number
7654 of bits in M, this is an extraction. */
7660 {
7666 }
7668 /* On machines without logical shifts, if the operand of the AND is
7669 a logical shift and our mask turns off all the propagated sign
7670 bits, we can replace the logical shift with an arithmetic shift. */
7678 {
7685 make_compound_operation
7688 }
7690 /* If the constant is one less than a power of two, this might be
7691 representable by an extraction even if no shift is present.
7692 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7693 we are in a COMPARE. */
7697 next_code),
7700 /* If we are in a comparison and this is an AND with a power of two,
7701 convert this into the appropriate bit extract. */
7706 next_code),
7712 /* If the sign bit is known to be zero, replace this with an
7713 arithmetic shift. */
7718 {
7721 next_code),
7724 }
7726 /* ... fall through ... */
7732 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7733 this is a SIGN_EXTRACT. */
7740 {
7747 }
7749 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7750 If so, try to merge the shifts into a SIGN_EXTEND. We could
7751 also do this for some cases of SIGN_EXTRACT, but it doesn't
7752 seem worth the effort; the case checked for occurs on Alpha. */
7768 /* Call ourselves recursively on the inner expression. If we are
7769 narrowing the object and it has a different RTL code from
7770 what it originally did, do this SUBREG as a force_to_mode. */
7771 {
7776 simplified
7784 {
7785 rtx newer
7788 /* If we have something other than a SUBREG, we might have
7789 done an expansion, so rerun ourselves. */
7793 /* force_to_mode can expand compounds. If it just re-expanded the
7794 compound, use gen_lowpart to convert to the desired mode. */
7796 /* Likewise if it re-expanded the compound only partially.
7797 This happens for SUBREG of ZERO_EXTRACT if they extract
7798 the same number of bits. */
7807 }
7811 }
7816 }
7819 {
7822 }
7824 /* Now recursively process each operand of this operation. */
7828 {
7831 }
7834 {
7837 }
7839 maybe_swap:
7840 /* If this is a commutative operation, the changes to the operands
7841 may have made it noncanonical. */
7844 {
7848 }
7851 }
7852 \f
7853 /* Given M see if it is a value that would select a field of bits
7854 within an item, but not the entire word. Return -1 if not.
7855 Otherwise, return the starting position of the field, where 0 is the
7856 low-order bit.
7858 *PLEN is set to the length of the field. */
7860 static int
7862 {
7863 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7868 /* Now shift off the low-order zero bits and see if we have a
7869 power of two minus 1. */
7877 }
7878 \f
7879 /* If X refers to a register that equals REG in value, replace these
7880 references with REG. */
7881 static rtx
7883 {
7891 {
7927 {
7931 else
7933 }
7935 /* fall through */
7942 {
7945 {
7947 {
7950 }
7952 }
7953 }
7955 {
7958 {
7961 {
7963 {
7966 }
7968 }
7969 }
7970 }
7973 }
7976 }
7978 /* Return X converted to MODE. If the value is already truncated to
7979 MODE we can just return a subreg even though in the general case we
7980 would need an explicit truncation. */
7982 static rtx
7984 {
7990 {
7991 /* Bit-cast X into an integer mode. */
7996 }
7999 }
8001 /* See if X can be simplified knowing that we will only refer to it in
8002 MODE and will only refer to those bits that are nonzero in MASK.
8003 If other bits are being computed or if masking operations are done
8004 that select a superset of the bits in MASK, they can sometimes be
8005 ignored.
8007 Return a possibly simplified expression, but always convert X to
8008 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8010 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8011 are all off in X. This is used when X will be complemented, by either
8012 NOT, NEG, or XOR. */
8014 static rtx
8017 {
8024 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8025 code below will do the wrong thing since the mode of such an
8026 expression is VOIDmode.
8028 Also do nothing if X is a CLOBBER; this can happen if X was
8029 the return value from a call to gen_lowpart. */
8033 /* We want to perform the operation is its present mode unless we know
8034 that the operation is valid in MODE, in which case we do the operation
8035 in MODE. */
8040 /* It is not valid to do a right-shift in a narrower mode
8041 than the one it came in with. */
8046 /* Truncate MASK to fit OP_MODE. */
8050 /* When we have an arithmetic operation, or a shift whose count we
8051 do not know, we need to assume that all bits up to the highest-order
8052 bit in MASK will be needed. This is how we form such a mask. */
8055 else
8059 /* Determine what bits of X are guaranteed to be (non)zero. */
8062 /* If none of the bits in X are needed, return a zero. */
8066 /* If X is a CONST_INT, return a new one. Do this here since the
8067 test below will fail. */
8069 {
8072 else
8073 {
8076 }
8077 }
8079 /* If X is narrower than MODE and we want all the bits in X's mode, just
8080 get X in the proper mode. */
8085 /* We can ignore the effect of a SUBREG if it narrows the mode or
8086 if the constant masks to zero all the bits the mode doesn't have. */
8096 /* The arithmetic simplifications here only work for scalar integer modes. */
8101 {
8103 /* If X is a (clobber (const_int)), return it since we know we are
8104 generating something that won't match. */
8117 /* Similarly for a truncate. */
8121 /* If this is an AND with a constant, convert it into an AND
8122 whose constant is the AND of that constant with MASK. If it
8123 remains an AND of MASK, delete it since it is redundant. */
8126 {
8130 /* If X is still an AND, see if it is an AND with a mask that
8131 is just some low-order bits. If so, and it is MASK, we don't
8132 need it. */
8139 /* If it remains an AND, try making another AND with the bits
8140 in the mode mask that aren't in MASK turned on. If the
8141 constant in the AND is wide enough, this might make a
8142 cheaper constant. */
8147 {
8148 unsigned HOST_WIDE_INT cval
8152 rtx y;
8154 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8155 number, sign extend it. */
8165 }
8168 }
8173 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8174 low-order bits (as in an alignment operation) and FOO is already
8175 aligned to that boundary, mask C1 to that boundary as well.
8176 This may eliminate that PLUS and, later, the AND. */
8178 {
8182 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8183 number, sign extend it. */
8196 }
8198 /* ... fall through ... */
8201 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8202 most significant bit in MASK since carries from those bits will
8203 affect the bits we are interested in. */
8208 /* If X is (minus C Y) where C's least set bit is larger than any bit
8209 in the mask, then we may replace with (neg Y). */
8214 {
8218 }
8220 /* Similarly, if C contains every bit in the fuller_mask, then we may
8221 replace with (not Y). */
8224 {
8228 }
8235 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8236 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8237 operation which may be a bitfield extraction. Ensure that the
8238 constant we form is not wider than the mode of X. */
8250 {
8258 }
8260 binop:
8261 /* For most binary operations, just propagate into the operation and
8262 change the mode if we have an operation of that mode. */
8267 /* If we ended up truncating both operands, truncate the result of the
8268 operation instead. */
8271 {
8274 }
8284 /* For left shifts, do the same, but just for the first operand.
8285 However, we cannot do anything with shifts where we cannot
8286 guarantee that the counts are smaller than the size of the mode
8287 because such a count will have a different meaning in a
8288 wider mode. */
8298 /* If the shift count is a constant and we can do arithmetic in
8299 the mode of the shift, refine which bits we need. Otherwise, use the
8300 conservative form of the mask. */
8306 else
8318 /* Here we can only do something if the shift count is a constant,
8319 this shift constant is valid for the host, and we can do arithmetic
8320 in OP_MODE. */
8325 {
8329 /* Select the mask of the bits we need for the shift operand. */
8332 /* We can only change the mode of the shift if we can do arithmetic
8333 in the mode of the shift and INNER_MASK is no wider than the
8334 width of X's mode. */
8342 }
8344 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8345 shift and AND produces only copies of the sign bit (C2 is one less
8346 than a power of two), we can do this with just a shift. */
8350 /* The shift puts one of the sign bit copies in the least significant
8351 bit. */
8356 /* Number of bits left after the shift must be more than the mask
8357 needs. */
8360 /* Must be more sign bit copies than the mask needs. */
8370 /* If we are just looking for the sign bit, we don't need this shift at
8371 all, even if it has a variable count. */
8377 /* If this is a shift by a constant, get a mask that contains those bits
8378 that are not copies of the sign bit. We then have two cases: If
8379 MASK only includes those bits, this can be a logical shift, which may
8380 allow simplifications. If MASK is a single-bit field not within
8381 those bits, we are requesting a copy of the sign bit and hence can
8382 shift the sign bit to the appropriate location. */
8386 {
8389 /* If the considered data is wider than HOST_WIDE_INT, we can't
8390 represent a mask for all its bits in a single scalar.
8391 But we only care about the lower bits, so calculate these. */
8394 {
8397 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8398 is the number of bits a full-width mask would have set.
8399 We need only shift if these are fewer than nonzero can
8400 hold. If not, we must keep all bits set in nonzero. */
8405 + HOST_BITS_PER_WIDE_INT
8407 }
8408 else
8409 {
8412 }
8415 {
8420 }
8423 {
8424 x = simplify_shift_const
8430 }
8431 }
8433 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8434 even if the shift count isn't a constant. */
8439 shiftrt:
8441 /* If this is a zero- or sign-extension operation that just affects bits
8442 we don't care about, remove it. Be sure the call above returned
8443 something that is still a shift. */
8453 next_select);
8459 /* If the shift count is constant and we can do computations
8460 in the mode of X, compute where the bits we care about are.
8461 Otherwise, we can't do anything. Don't change the mode of
8462 the shift or propagate MODE into the shift, though. */
8465 {
8473 }
8477 /* If we just want the low-order bit, the NEG isn't needed since it
8478 won't change the low-order bit. */
8482 /* We need any bits less significant than the most significant bit in
8483 MASK since carries from those bits will affect the bits we are
8484 interested in. */
8489 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8490 same as the XOR case above. Ensure that the constant we form is not
8491 wider than the mode of X. */
8499 {
8508 }
8510 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8511 use the full mask inside the NOT. */
8514 unop:
8517 next_select));
8523 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8524 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8525 which is equal to STORE_FLAG_VALUE. */
8537 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8538 written in a narrower mode. We play it safe and do not do so. */
8552 }
8554 /* Ensure we return a value of the proper mode. */
8556 }
8557 \f
8558 /* Return nonzero if X is an expression that has one of two values depending on
8559 whether some other value is zero or nonzero. In that case, we return the
8560 value that is being tested, *PTRUE is set to the value if the rtx being
8561 returned has a nonzero value, and *PFALSE is set to the other alternative.
8563 If we return zero, we set *PTRUE and *PFALSE to X. */
8565 static rtx
8567 {
8573 /* If we are comparing a value against zero, we are done. */
8576 {
8580 }
8582 /* If this is a unary operation whose operand has one of two values, apply
8583 our opcode to compute those values. */
8586 {
8591 }
8593 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8594 make can't possibly match and would suppress other optimizations. */
8596 ;
8598 /* If this is a binary operation, see if either side has only one of two
8599 values. If either one does or if both do and they are conditional on
8600 the same value, compute the new true and false values. */
8602 {
8608 {
8609 /* If if_then_else_cond returned zero, then true/false are the
8610 same rtl. We must copy one of them to prevent invalid rtl
8611 sharing. */
8618 {
8623 }
8624 else
8625 {
8628 }
8631 }
8633 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8634 operands is zero when the other is nonzero, and vice-versa,
8635 and STORE_FLAG_VALUE is 1 or -1. */
8641 {
8658 {
8665 const_true_rtx);
8667 }
8668 }
8670 /* Similarly for MULT, AND and UMIN, except that for these the result
8671 is always zero. */
8675 {
8689 {
8692 }
8693 }
8694 }
8697 {
8698 /* If we have IF_THEN_ELSE already, extract the condition and
8699 canonicalize it if it is NE or EQ. */
8705 {
8708 }
8709 else
8711 }
8713 /* If X is a SUBREG, we can narrow both the true and false values
8714 if the inner expression, if there is a condition. */
8718 {
8724 {
8728 }
8729 }
8731 /* If X is a constant, this isn't special and will cause confusions
8732 if we treat it as such. Likewise if it is equivalent to a constant. */
8735 ;
8737 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8738 will be least confusing to the rest of the compiler. */
8740 {
8743 }
8745 /* If X is known to be either 0 or -1, those are the true and
8746 false values when testing X. */
8750 {
8753 }
8755 /* Likewise for 0 or a single bit. */
8759 {
8762 }
8764 /* Otherwise fail; show no condition with true and false values the same. */
8767 }
8768 \f
8769 /* Return the value of expression X given the fact that condition COND
8770 is known to be true when applied to REG as its first operand and VAL
8771 as its second. X is known to not be shared and so can be modified in
8772 place.
8774 We only handle the simplest cases, and specifically those cases that
8775 arise with IF_THEN_ELSE expressions. */
8777 static rtx
8779 {
8781 rtx temp;
8788 /* If either operand of the condition is a floating point value,
8789 then we have to avoid collapsing an EQ comparison. */
8799 /* If X is (abs REG) and we know something about REG's relationship
8800 with zero, we may be able to simplify this. */
8804 {
8813 }
8815 /* The only other cases we handle are MIN, MAX, and comparisons if the
8816 operands are the same as REG and VAL. */
8819 {
8824 {
8826 {
8834 else
8836 }
8839 {
8842 /* Do not reverse the condition when it is NE or EQ.
8843 This is because we cannot conclude anything about
8844 the value of 'SMAX (x, y)' when x is not equal to y,
8845 but we can when x equals y. */
8851 {
8862 }
8863 }
8864 }
8865 }
8867 {
8872 {
8873 /* We must simplify subreg here, before we lose track of the
8874 original inner_mode. */
8879 else
8881 }
8884 }
8885 /* We don't have to handle SIGN_EXTEND here, because even in the
8886 case of replacing something with a modeless CONST_INT, a
8887 CONST_INT is already (supposed to be) a valid sign extension for
8888 its narrower mode, which implies it's already properly
8889 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8890 story is different. */
8892 {
8897 {
8898 /* We must simplify the zero_extend here, before we lose
8899 track of the original inner_mode. */
8904 else
8906 }
8909 }
8913 {
8920 }
8923 }
8924 \f
8925 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8926 assignment as a field assignment. */
8928 static int
8930 {
8937 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8938 Note that all SUBREGs of MEM are paradoxical; otherwise they
8939 would have been rewritten. */
8952 /* We used to see if get_last_value of X and Y were the same but that's
8953 not correct. In one direction, we'll cause the assignment to have
8954 the wrong destination and in the case, we'll import a register into this
8955 insn that might have already have been dead. So fail if none of the
8956 above cases are true. */
8958 }
8959 \f
8960 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8961 Return that assignment if so.
8963 We only handle the most common cases. */
8965 static rtx
8967 {
8970 rtx assign;
8972 HOST_WIDE_INT c1;
8973 HOST_WIDE_INT pos;
8975 rtx other;
8978 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8979 a clear of a one-bit field. We will have changed it to
8980 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8981 for a SUBREG. */
8987 {
8993 }
9003 {
9010 }
9012 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9013 one-bit field. */
9017 {
9023 }
9025 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9026 SRC is an AND with all bits of that field set, then we can discard
9027 the AND. */
9032 {
9039 else
9042 /* Complete overlap. We can remove the source AND. */
9046 /* Partial overlap. We can reduce the source AND. */
9048 {
9053 }
9054 }
9056 /* The other case we handle is assignments into a constant-position
9057 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9058 a mask that has all one bits except for a group of zero bits and
9059 OTHER is known to have zeros where C1 has ones, this is such an
9060 assignment. Compute the position and length from C1. Shift OTHER
9061 to the appropriate position, force it to the required mode, and
9062 make the extraction. Check for the AND in both operands. */
9078 else
9091 /* The mode to use for the source is the mode of the assignment, or of
9092 what is inside a possible STRICT_LOW_PART. */
9096 /* Shift OTHER right POS places and make it the source, restricting it
9097 to the proper length and mode. */
9102 dest);
9109 /* If SRC is masked by an AND that does not make a difference in
9110 the value being stored, strip it. */
9121 }
9122 \f
9123 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9124 if so. */
9126 static rtx
9128 {
9132 rtx tem;
9134 /* Distributivity is not true for floating point as it can change the
9135 value. So we don't do it unless -funsafe-math-optimizations. */
9140 /* The outer operation can only be one of the following: */
9148 /* If either operand is a primitive we can't do anything, so get out
9149 fast. */
9159 /* See if the inner and outer operations distribute. */
9161 {
9166 /* These all distribute except over PLUS. */
9177 /* This is also a multiply, so it distributes over everything. */
9181 /* Non-paradoxical SUBREGs distributes over all operations,
9182 provided the inner modes and byte offsets are the same, this
9183 is an extraction of a low-order part, we don't convert an fp
9184 operation to int or vice versa, this is not a vector mode,
9185 and we would not be converting a single-word operation into a
9186 multi-word operation. The latter test is not required, but
9187 it prevents generating unneeded multi-word operations. Some
9188 of the previous tests are redundant given the latter test,
9189 but are retained because they are required for correctness.
9191 We produce the result slightly differently in this case. */
9202 /* Result might need to be truncated. Don't change mode if
9203 explicit truncation is needed. */
9204 || !TRULY_NOOP_TRUNCATION
9215 }
9217 /* Set LHS and RHS to the inner operands (A and B in the example
9218 above) and set OTHER to the common operand (C in the example).
9219 There is only one way to do this unless the inner operation is
9220 commutative. */
9232 else
9235 /* Form the new inner operation, seeing if it simplifies first. */
9238 /* There is one exception to the general way of distributing:
9239 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9241 {
9244 }
9246 /* We may be able to continuing distributing the result, so call
9247 ourselves recursively on the inner operation before forming the
9248 outer operation, which we return. */
9251 }
9253 /* See if X is of the form (* (+ A B) C), and if so convert to
9254 (+ (* A C) (* B C)) and try to simplify.
9256 Most of the time, this results in no change. However, if some of
9257 the operands are the same or inverses of each other, simplifications
9258 will result.
9260 For example, (and (ior A B) (not B)) can occur as the result of
9261 expanding a bit field assignment. When we apply the distributive
9262 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9263 which then simplifies to (and (A (not B))).
9265 Note that no checks happen on the validity of applying the inverse
9266 distributive law. This is pointless since we can do it in the
9267 few places where this routine is called.
9269 N is the index of the term that is decomposed (the arithmetic operation,
9270 i.e. (+ A B) in the first example above). !N is the index of the term that
9271 is distributed, i.e. of C in the first example above. */
9272 static rtx
9274 {
9279 /* Distributivity is not true for floating point as it can change the
9280 value. So we don't do it unless -funsafe-math-optimizations. */
9297 /* Special case (and (xor B C) (not A)), which is equivalent to
9298 (xor (ior A B) (ior A C)) */
9300 {
9303 }
9306 {
9307 /* Distribute the second term. */
9310 }
9311 else
9312 {
9313 /* Distribute the first term. */
9316 }
9326 }
9327 \f
9328 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9329 in MODE. Return an equivalent form, if different from (and VAROP
9330 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9332 static rtx
9335 {
9338 rtx orig_varop;
9346 /* Simplify VAROP knowing that we will be only looking at some of the
9347 bits in it.
9349 Note by passing in CONSTOP, we guarantee that the bits not set in
9350 CONSTOP are not significant and will never be examined. We must
9351 ensure that is the case by explicitly masking out those bits
9352 before returning. */
9355 /* If VAROP is a CLOBBER, we will fail so return it. */
9359 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9360 to VAROP and return the new constant. */
9364 /* See what bits may be nonzero in VAROP. Unlike the general case of
9365 a call to nonzero_bits, here we don't care about bits outside
9366 MODE. */
9370 /* Turn off all bits in the constant that are known to already be zero.
9371 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9372 which is tested below. */
9376 /* If we don't have any bits left, return zero. */
9380 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9381 a power of two, we can replace this with an ASHIFT. */
9386 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9387 or XOR, then try to apply the distributive law. This may eliminate
9388 operations if either branch can be simplified because of the AND.
9389 It may also make some cases more complex, but those cases probably
9390 won't match a pattern either with or without this. */
9393 return
9394 gen_lowpart
9396 apply_distributive_law
9401 constop),
9405 constop))));
9407 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9408 the AND and see if one of the operands simplifies to zero. If so, we
9409 may eliminate it. */
9413 {
9422 }
9424 /* Make a SUBREG if necessary. If we can't make it, fail. */
9429 /* If we are only masking insignificant bits, return VAROP. */
9436 /* Otherwise, return an AND. */
9438 }
9441 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9442 in MODE.
9444 Return an equivalent form, if different from X. Otherwise, return X. If
9445 X is zero, we are to always construct the equivalent form. */
9447 static rtx
9450 {
9461 }
9462 \f
9463 /* Given a REG, X, compute which bits in X can be nonzero.
9464 We don't care about bits outside of those defined in MODE.
9466 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9467 a shift, AND, or zero_extract, we can do better. */
9469 static rtx
9471 const_rtx known_x ATTRIBUTE_UNUSED,
9475 {
9476 rtx tem;
9479 /* If X is a register whose nonzero bits value is current, use it.
9480 Otherwise, if X is a register whose value we can find, use that
9481 value. Otherwise, use the previously-computed global nonzero bits
9482 for this register. */
9495 && !REGNO_REG_SET_P
9497 {
9500 }
9505 {
9506 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9507 /* If X is narrower than MODE and TEM is a non-negative
9508 constant that would appear negative in the mode of X,
9509 sign-extend it for use in reg_nonzero_bits because some
9510 machines (maybe most) will actually do the sign-extension
9511 and this is the conservative approach.
9513 ??? For 2.5, try to tighten up the MD files in this regard
9514 instead of this kludge. */
9525 #endif
9527 }
9529 {
9533 /* We don't know anything about the upper bits. */
9536 }
9539 }
9541 /* Return the number of bits at the high-order end of X that are known to
9542 be equal to the sign bit. X will be used in mode MODE; if MODE is
9543 VOIDmode, X will be used in its own mode. The returned value will always
9544 be between 1 and the number of bits in MODE. */
9546 static rtx
9548 const_rtx known_x ATTRIBUTE_UNUSED,
9549 enum machine_mode known_mode
9550 ATTRIBUTE_UNUSED,
9553 {
9554 rtx tem;
9566 && !REGNO_REG_SET_P
9568 {
9571 }
9582 }
9583 \f
9584 /* Return the number of "extended" bits there are in X, when interpreted
9585 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9586 unsigned quantities, this is the number of high-order zero bits.
9587 For signed quantities, this is the number of copies of the sign bit
9588 minus 1. In both case, this function returns the number of "spare"
9589 bits. For example, if two quantities for which this function returns
9590 at least 1 are added, the addition is known not to overflow.
9592 This function will always return 0 unless called during combine, which
9593 implies that it must be called from a define_split. */
9595 unsigned int
9597 {
9607 }
9608 \f
9609 /* This function is called from `simplify_shift_const' to merge two
9610 outer operations. Specifically, we have already found that we need
9611 to perform operation *POP0 with constant *PCONST0 at the outermost
9612 position. We would now like to also perform OP1 with constant CONST1
9613 (with *POP0 being done last).
9615 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9616 the resulting operation. *PCOMP_P is set to 1 if we would need to
9617 complement the innermost operand, otherwise it is unchanged.
9619 MODE is the mode in which the operation will be done. No bits outside
9620 the width of this mode matter. It is assumed that the width of this mode
9621 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9623 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9624 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9625 result is simply *PCONST0.
9627 If the resulting operation cannot be expressed as one operation, we
9628 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9630 static int
9631 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9632 {
9639 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9643 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9644 if OP0 is SET. */
9653 {
9655 {
9673 }
9674 }
9676 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9680 /* If the two constants aren't the same, we can't do anything. The
9681 remaining six cases can all be done. */
9685 else
9687 {
9690 /* (a & b) | b == b */
9693 /* (a ^ b) | b == a | b */
9694 {;}
9699 /* (a & b) ^ b == (~a) & b */
9702 /* (a | b) ^ b == a & ~b */
9708 /* (a | b) & b == b */
9711 /* (a ^ b) & b) == (~a) & b */
9716 }
9718 /* Check for NO-OP cases. */
9731 /* ??? Slightly redundant with the above mask, but not entirely.
9732 Moving this above means we'd have to sign-extend the mode mask
9733 for the final test. */
9738 }
9739 \f
9740 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9741 the shift in. The original shift operation CODE is performed on OP in
9742 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9743 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9744 result of the shift is subject to operation OUTER_CODE with operand
9745 OUTER_CONST. */
9747 static enum machine_mode
9751 {
9756 /* In general we can't perform in wider mode for right shift and rotate. */
9758 {
9760 /* We can still widen if the bits brought in from the left are identical
9761 to the sign bit of ORIG_MODE. */
9769 /* Similarly here but with zero bits. */
9774 /* We can also widen if the bits brought in will be masked off. This
9775 operation is performed in ORIG_MODE. */
9777 {
9783 }
9784 /* fall through */
9794 }
9795 }
9797 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9798 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9799 simplify it. Otherwise, return a simplified value.
9801 The shift is normally computed in the widest mode we find in VAROP, as
9802 long as it isn't a different number of words than RESULT_MODE. Exceptions
9803 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9805 static rtx
9808 {
9814 unsigned int mode_words
9816 /* We form (outer_op (code varop count) (outer_const)). */
9822 /* Make sure and truncate the "natural" shift on the way in. We don't
9823 want to do this inside the loop as it makes it more difficult to
9824 combine shifts. */
9828 /* If we were given an invalid count, don't do anything except exactly
9829 what was requested. */
9836 /* Unless one of the branches of the `if' in this loop does a `continue',
9837 we will `break' the loop after the `if'. */
9840 {
9841 /* If we have an operand of (clobber (const_int 0)), fail. */
9845 /* Convert ROTATERT to ROTATE. */
9847 {
9852 else
9854 }
9859 /* Handle cases where the count is greater than the size of the mode
9860 minus 1. For ASHIFT, use the size minus one as the count (this can
9861 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9862 take the count modulo the size. For other shifts, the result is
9863 zero.
9865 Since these shifts are being produced by the compiler by combining
9866 multiple operations, each of which are defined, we know what the
9867 result is supposed to be. */
9870 {
9875 else
9876 {
9877 /* We can't simply return zero because there may be an
9878 outer op. */
9882 }
9883 }
9885 /* If we discovered we had to complement VAROP, leave. Making a NOT
9886 here would cause an infinite loop. */
9890 /* An arithmetic right shift of a quantity known to be -1 or 0
9891 is a no-op. */
9895 {
9898 }
9900 /* If we are doing an arithmetic right shift and discarding all but
9901 the sign bit copies, this is equivalent to doing a shift by the
9902 bitsize minus one. Convert it into that shift because it will often
9903 allow other simplifications. */
9910 /* We simplify the tests below and elsewhere by converting
9911 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9912 `make_compound_operation' will convert it to an ASHIFTRT for
9913 those machines (such as VAX) that don't have an LSHIFTRT. */
9932 {
9939 {
9942 }
9946 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9947 minus the width of a smaller mode, we can do this with a
9948 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9954 {
9963 }
9967 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9968 the same number of words as what we've seen so far. Then store
9969 the widest mode in MODE. */
9975 == mode_words
9978 {
9983 }
9987 /* Some machines use MULT instead of ASHIFT because MULT
9988 is cheaper. But it is still better on those machines to
9989 merge two shifts into one. */
9992 {
9993 varop
9999 }
10003 /* Similar, for when divides are cheaper. */
10006 {
10007 varop
10013 }
10017 /* If we are extracting just the sign bit of an arithmetic
10018 right shift, that shift is not needed. However, the sign
10019 bit of a wider mode may be different from what would be
10020 interpreted as the sign bit in a narrower mode, so, if
10021 the result is narrower, don't discard the shift. */
10026 {
10029 }
10031 /* ... fall through ... */
10036 /* Here we have two nested shifts. The result is usually the
10037 AND of a new shift with a mask. We compute the result below. */
10044 {
10048 rtx mask_rtx;
10050 /* We have one common special case. We can't do any merging if
10051 the inner code is an ASHIFTRT of a smaller mode. However, if
10052 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10053 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10054 we can convert it to
10055 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10056 This simplifies certain SIGN_EXTEND operations. */
10060 {
10061 /* C3 has the low-order C1 bits zero. */
10073 }
10075 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10076 than C1 high-order bits equal to the sign bit, we can convert
10077 this to either an ASHIFT or an ASHIFTRT depending on the
10078 two counts.
10080 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10086 {
10090 {
10093 }
10096 }
10098 /* There are some cases we can't do. If CODE is ASHIFTRT,
10099 we can only do this if FIRST_CODE is also ASHIFTRT.
10101 We can't do the case when CODE is ROTATE and FIRST_CODE is
10102 ASHIFTRT.
10104 If the mode of this shift is not the mode of the outer shift,
10105 we can't do this if either shift is a right shift or ROTATE.
10107 Finally, we can't do any of these if the mode is too wide
10108 unless the codes are the same.
10110 Handle the case where the shift codes are the same
10111 first. */
10114 {
10123 }
10134 /* To compute the mask to apply after the shift, shift the
10135 nonzero bits of the inner shift the same way the
10136 outer shift will. */
10140 mask_rtx
10144 /* Give up if we can't compute an outer operation to use. */
10152 /* If the shifts are in the same direction, we add the
10153 counts. Otherwise, we subtract them. */
10157 else
10160 /* If COUNT is positive, the new shift is usually CODE,
10161 except for the two exceptions below, in which case it is
10162 FIRST_CODE. If the count is negative, FIRST_CODE should
10163 always be used */
10173 }
10175 /* If we have (A << B << C) for any shift, we can convert this to
10176 (A << C << B). This wins if A is a constant. Only try this if
10177 B is not a constant. */
10182 {
10189 }
10196 /* Make this fit the case below. */
10204 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10205 with C the size of VAROP - 1 and the shift is logical if
10206 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10207 we have an (le X 0) operation. If we have an arithmetic shift
10208 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10209 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10217 {
10220 const0_rtx);
10226 }
10228 /* If we have (shift (logical)), move the logical to the outside
10229 to allow it to possibly combine with another logical and the
10230 shift to combine with another shift. This also canonicalizes to
10231 what a ZERO_EXTRACT looks like. Also, some machines have
10232 (and (shift)) insns. */
10235 /* We can't do this if we have (ashiftrt (xor)) and the
10236 constant has its sign bit set in shift_mode. */
10239 shift_mode))
10246 {
10249 }
10251 /* If we can't do that, try to simplify the shift in each arm of the
10252 logical expression, make a new logical expression, and apply
10253 the inverse distributive law. This also can't be done
10254 for some (ashiftrt (xor)). */
10258 shift_mode)))
10259 {
10271 }
10275 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10276 says that the sign bit can be tested, FOO has mode MODE, C is
10277 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10278 that may be nonzero. */
10288 {
10292 }
10296 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10297 than the number of bits in the mode is equivalent to A. */
10301 {
10305 }
10307 /* NEG commutes with ASHIFT since it is multiplication. Move the
10308 NEG outside to allow shifts to combine. */
10312 {
10315 }
10319 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10320 is one less than the number of bits in the mode is
10321 equivalent to (xor A 1). */
10328 {
10332 }
10334 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10335 that might be nonzero in BAR are those being shifted out and those
10336 bits are known zero in FOO, we can replace the PLUS with FOO.
10337 Similarly in the other operand order. This code occurs when
10338 we are computing the size of a variable-size array. */
10345 {
10348 }
10356 result_mode)))
10357 {
10360 }
10362 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10371 {
10374 }
10376 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10377 signbit', and attempt to change the PLUS to an XOR and move it to
10378 the outer operation as is done above in the AND/IOR/XOR case
10379 leg for shift(logical). See details in logical handling above
10380 for reasoning in doing so. */
10390 {
10393 }
10398 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10399 with C the size of VAROP - 1 and the shift is logical if
10400 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10401 we have a (gt X 0) operation. If the shift is arithmetic with
10402 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10403 we have a (neg (gt X 0)) operation. */
10412 {
10415 const0_rtx);
10421 }
10425 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10426 if the truncate does not affect the value. */
10433 {
10436 varop_inner
10439 GEN_INT
10444 }
10449 }
10452 }
10457 /* We have now finished analyzing the shift. The result should be
10458 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10459 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10460 to the result of the shift. OUTER_CONST is the relevant constant,
10461 but we must turn off all bits turned off in the shift. */
10469 /* Make a SUBREG if necessary. If we can't make it, fail. */
10474 /* If we have an outer operation and we just made a shift, it is
10475 possible that we could have simplified the shift were it not
10476 for the outer operation. So try to do the simplification
10477 recursively. */
10481 else
10487 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10488 turn off all the bits that the shift would have turned off. */
10493 /* Do the remainder of the processing in RESULT_MODE. */
10496 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10497 operation. */
10502 {
10510 {
10511 /* This means that we have determined that the result is
10512 equivalent to a constant. This should be rare. */
10515 }
10518 else
10521 }
10524 }
10526 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10527 The result of the shift is RESULT_MODE. If we cannot simplify it,
10528 return X or, if it is NULL, synthesize the expression with
10529 simplify_gen_binary. Otherwise, return a simplified value.
10531 The shift is normally computed in the widest mode we find in VAROP, as
10532 long as it isn't a different number of words than RESULT_MODE. Exceptions
10533 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10535 static rtx
10538 {
10548 }
10550 \f
10551 /* Like recog, but we receive the address of a pointer to a new pattern.
10552 We try to match the rtx that the pointer points to.
10553 If that fails, we may try to modify or replace the pattern,
10554 storing the replacement into the same pointer object.
10556 Modifications include deletion or addition of CLOBBERs.
10558 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10559 the CLOBBERs are placed.
10561 The value is the final insn code from the pattern ultimately matched,
10562 or -1. */
10564 static int
10566 {
10574 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10575 we use to indicate that something didn't match. If we find such a
10576 thing, force rejection. */
10590 {
10593 else
10596 }
10598 /* If it isn't, there is the possibility that we previously had an insn
10599 that clobbered some register as a side effect, but the combined
10600 insn doesn't need to do that. So try once more without the clobbers
10601 unless this represents an ASM insn. */
10605 {
10610 {
10613 pos++;
10614 }
10624 {
10627 else
10630 }
10631 }
10635 /* Recognize all noop sets, these will be killed by followup pass. */
10639 /* If we had any clobbers to add, make a new pattern than contains
10640 them. Then check to make sure that all of them are dead. */
10642 {
10652 else
10659 {
10664 {
10668 }
10669 }
10671 }
10677 }
10678 \f
10679 /* Like gen_lowpart_general but for use by combine. In combine it
10680 is not possible to create any new pseudoregs. However, it is
10681 safe to create invalid memory addresses, because combine will
10682 try to recognize them and all they will do is make the combine
10683 attempt fail.
10685 If for some reason this cannot do its job, an rtx
10686 (clobber (const_int 0)) is returned.
10687 An insn containing that will not be recognized. */
10689 static rtx
10691 {
10695 rtx result;
10700 /* Return identity if this is a CONST or symbolic reference. */
10707 /* We can only support MODE being wider than a word if X is a
10708 constant integer or has a mode the same size. */
10716 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10717 won't know what to do. So we will strip off the SUBREG here and
10718 process normally. */
10720 {
10723 /* For use in case we fall down into the address adjustments
10724 further below, we need to adjust the known mode and size of
10725 x; imode and isize, since we just adjusted x. */
10732 }
10740 {
10743 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10744 address. */
10748 /* If we want to refer to something bigger than the original memref,
10749 generate a paradoxical subreg instead. That will force a reload
10750 of the original memref X. */
10757 /* Adjust the address so that the address-after-the-data is
10758 unchanged. */
10763 }
10765 /* If X is a comparison operator, rewrite it in a new mode. This
10766 probably won't match, but may allow further simplifications. */
10770 /* If we couldn't simplify X any other way, just enclose it in a
10771 SUBREG. Normally, this SUBREG won't match, but some patterns may
10772 include an explicit SUBREG or we may simplify it further in combine. */
10773 else
10774 {
10776 rtx res;
10780 {
10785 }
10789 }
10791 fail:
10793 }
10794 \f
10795 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10796 comparison code that will be tested.
10798 The result is a possibly different comparison code to use. *POP0 and
10799 *POP1 may be updated.
10801 It is possible that we might detect that a comparison is either always
10802 true or always false. However, we do not perform general constant
10803 folding in combine, so this knowledge isn't useful. Such tautologies
10804 should have been detected earlier. Hence we ignore all such cases. */
10806 static enum rtx_code
10808 {
10815 /* Try a few ways of applying the same transformation to both operands. */
10817 {
10818 #ifndef WORD_REGISTER_OPERATIONS
10819 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10820 so check specially. */
10835 - (GET_MODE_BITSIZE
10837 {
10840 }
10841 #endif
10843 /* If both operands are the same constant shift, see if we can ignore the
10844 shift. We can if the shift is a rotate or if the bits shifted out of
10845 this shift are known to be zero for both inputs and if the type of
10846 comparison is compatible with the shift. */
10859 {
10872 else
10874 }
10876 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10877 SUBREGs are of the same mode, and, in both cases, the AND would
10878 be redundant if the comparison was done in the narrower mode,
10879 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10880 and the operand's possibly nonzero bits are 0xffffff01; in that case
10881 if we only care about QImode, we don't need the AND). This case
10882 occurs if the output mode of an scc insn is not SImode and
10883 STORE_FLAG_VALUE == 1 (e.g., the 386).
10885 Similarly, check for a case where the AND's are ZERO_EXTEND
10886 operations from some narrower mode even though a SUBREG is not
10887 present. */
10892 {
10910 {
10914 /* The resulting comparison is always unsigned since we masked
10915 off the original sign bit. */
10919 }
10926 {
10932 }
10936 }
10938 /* If both operands are NOT, we can strip off the outer operation
10939 and adjust the comparison code for swapped operands; similarly for
10940 NEG, except that this must be an equality comparison. */
10946 else
10948 }
10950 /* If the first operand is a constant, swap the operands and adjust the
10951 comparison code appropriately, but don't do this if the second operand
10952 is already a constant integer. */
10954 {
10957 }
10959 /* We now enter a loop during which we will try to simplify the comparison.
10960 For the most part, we only are concerned with comparisons with zero,
10961 but some things may really be comparisons with zero but not start
10962 out looking that way. */
10965 {
10972 HOST_WIDE_INT const_op;
10974 /* We only want to handle integral modes. This catches VOIDmode,
10975 CCmode, and the floating-point modes. An exception is that we
10976 can handle VOIDmode if OP0 is a COMPARE or a comparison
10977 operation. */
10984 /* Get the constant we are comparing against and turn off all bits
10985 not on in our mode. */
10991 /* If we are comparing against a constant power of two and the value
10992 being compared can only have that single bit nonzero (e.g., it was
10993 `and'ed with that bit), we can replace this with a comparison
10994 with zero. */
11001 {
11004 }
11006 /* Similarly, if we are comparing a value known to be either -1 or
11007 0 with -1, change it to the opposite comparison against zero. */
11013 {
11016 }
11018 /* Do some canonicalizations based on the comparison code. We prefer
11019 comparisons against zero and then prefer equality comparisons.
11020 If we can reduce the size of a constant, we will do that too. */
11023 {
11025 /* < C is equivalent to <= (C - 1) */
11027 {
11031 /* ... fall through to LE case below. */
11032 }
11033 else
11037 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11039 {
11043 }
11045 /* If we are doing a <= 0 comparison on a value known to have
11046 a zero sign bit, we can replace this with == 0. */
11056 /* >= C is equivalent to > (C - 1). */
11058 {
11062 /* ... fall through to GT below. */
11063 }
11064 else
11068 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11070 {
11074 }
11076 /* If we are doing a > 0 comparison on a value known to have
11077 a zero sign bit, we can replace this with != 0. */
11087 /* < C is equivalent to <= (C - 1). */
11089 {
11093 /* ... fall through ... */
11094 }
11096 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11100 {
11104 }
11105 else
11109 /* unsigned <= 0 is equivalent to == 0 */
11113 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11117 {
11120 }
11124 /* >= C is equivalent to > (C - 1). */
11126 {
11130 /* ... fall through ... */
11131 }
11133 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11137 {
11141 }
11142 else
11146 /* unsigned > 0 is equivalent to != 0 */
11150 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11154 {
11157 }
11162 }
11164 /* Compute some predicates to simplify code below. */
11171 /* If this is a sign bit comparison and we can do arithmetic in
11172 MODE, say that we will only be needing the sign bit of OP0. */
11180 /* Now try cases based on the opcode of OP0. If none of the cases
11181 does a "continue", we exit this loop immediately after the
11182 switch. */
11185 {
11187 /* If we are extracting a single bit from a variable position in
11188 a constant that has only a single bit set and are comparing it
11189 with zero, we can convert this into an equality comparison
11190 between the position and the location of the single bit. */
11191 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11192 have already reduced the shift count modulo the word size. */
11198 {
11200 {
11201 enum machine_mode new_mode
11205 else
11206 {
11209 }
11210 }
11216 /* Result is nonzero iff shift count is equal to I. */
11219 }
11221 /* ... fall through ... */
11226 {
11229 }
11233 /* If testing for equality, we can take the NOT of the constant. */
11236 {
11240 }
11242 /* If just looking at the sign bit, reverse the sense of the
11243 comparison. */
11245 {
11249 }
11253 /* If testing for equality, we can take the NEG of the constant. */
11256 {
11260 }
11262 /* The remaining cases only apply to comparisons with zero. */
11266 /* When X is ABS or is known positive,
11267 (neg X) is < 0 if and only if X != 0. */
11275 {
11279 }
11281 /* If we have NEG of something whose two high-order bits are the
11282 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11284 {
11288 }
11292 /* If we are testing equality and our count is a constant, we
11293 can perform the inverse operation on our RHS. */
11297 {
11301 }
11303 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11304 a particular bit. Convert it to an AND of a constant of that
11305 bit. This will be converted into a ZERO_EXTRACT. */
11309 {
11316 }
11318 /* Fall through. */
11321 /* ABS is ignorable inside an equality comparison with zero. */
11323 {
11326 }
11330 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11331 (compare FOO CONST) if CONST fits in FOO's mode and we
11332 are either testing inequality or have an unsigned
11333 comparison with ZERO_EXTEND or a signed comparison with
11334 SIGN_EXTEND. But don't do it if we don't have a compare
11335 insn of the given mode, since we'd have to revert it
11336 later on, and then we wouldn't know whether to sign- or
11337 zero-extend. */
11340 && ! unsigned_comparison_p
11346 {
11349 }
11353 /* Check for the case where we are comparing A - C1 with C2, that is
11355 (subreg:MODE (plus (A) (-C1))) op (C2)
11357 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11358 comparison in the wider mode. One of the following two conditions
11359 must be true in order for this to be valid:
11361 1. The mode extension results in the same bit pattern being added
11362 on both sides and the comparison is equality or unsigned. As
11363 C2 has been truncated to fit in MODE, the pattern can only be
11364 all 0s or all 1s.
11366 2. The mode extension results in the sign bit being copied on
11367 each side.
11369 The difficulty here is that we have predicates for A but not for
11370 (A - C1) so we need to check that C1 is within proper bounds so
11371 as to perturbate A as little as possible. */
11378 {
11387 /* (A - C1) zero-extends if it is positive and sign-extends
11388 if it is negative, C2 both zero- and sign-extends. */
11392 /* (A - C1) sign-extends if it is positive and 1-extends
11393 if it is negative, C2 both sign- and 1-extends. */
11400 /* (A - C1) always sign-extends, like C2. */
11404 {
11407 }
11408 }
11410 /* If the inner mode is narrower and we are extracting the low part,
11411 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11415 else
11418 /* ... fall through ... */
11427 {
11430 }
11434 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11435 this for equality comparisons due to pathological cases involving
11436 overflows. */
11440 {
11444 }
11446 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11449 {
11453 }
11457 /* We used to optimize signed comparisons against zero, but that
11458 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11459 arrive here as equality comparisons, or (GEU, LTU) are
11460 optimized away. No need to special-case them. */
11462 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11463 (eq B (minus A C)), whichever simplifies. We can only do
11464 this for equality comparisons due to pathological cases involving
11465 overflows. */
11469 {
11473 }
11478 {
11482 }
11484 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11485 of bits in X minus 1, is one iff X > 0. */
11490 {
11494 }
11498 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11499 if C is zero or B is a constant. */
11503 {
11507 }
11515 /* We can't do anything if OP0 is a condition code value, rather
11516 than an actual data value. */
11522 /* Get the two operands being compared. */
11525 else
11528 /* Check for the cases where we simply want the result of the
11529 earlier test or the opposite of that result. */
11533 && (STORE_FLAG_VALUE
11537 {
11541 else
11545 {
11550 }
11551 }
11555 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11556 iff X <= 0. */
11560 {
11564 }
11568 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11569 will be converted to a ZERO_EXTRACT later. */
11573 {
11578 }
11580 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11581 zero and X is a comparison and C1 and C2 describe only bits set
11582 in STORE_FLAG_VALUE, we can compare with X. */
11590 {
11597 {
11600 }
11601 }
11603 /* If we are doing an equality comparison of an AND of a bit equal
11604 to the sign bit, replace this with a LT or GE comparison of
11605 the underlying value. */
11612 {
11616 }
11618 /* If this AND operation is really a ZERO_EXTEND from a narrower
11619 mode, the constant fits within that mode, and this is either an
11620 equality or unsigned comparison, try to do this comparison in
11621 the narrower mode.
11623 Note that in:
11625 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11626 -> (ne:DI (reg:SI 4) (const_int 0))
11628 unless TRULY_NOOP_TRUNCATION allows it or the register is
11629 known to hold a value of the required mode the
11630 transformation is invalid. */
11642 {
11645 }
11647 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11648 fits in both M1 and M2 and the SUBREG is either paradoxical
11649 or represents the low part, permute the SUBREG and the AND
11650 and try again. */
11652 {
11655 /* Require an integral mode, to avoid creating something like
11656 (AND:SF ...). */
11658 /* It is unsafe to commute the AND into the SUBREG if the
11659 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11660 not defined. As originally written the upper bits
11661 have a defined value due to the AND operation.
11662 However, if we commute the AND inside the SUBREG then
11663 they no longer have defined values and the meaning of
11664 the code has been changed. */
11666 #ifdef WORD_REGISTER_OPERATIONS
11669 #endif
11679 {
11685 }
11686 }
11688 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11692 {
11697 }
11699 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11700 (eq (and (lshiftrt X) 1) 0).
11701 Also handle the case where (not X) is expressed using xor. */
11705 {
11717 {
11718 op0
11723 }
11724 }
11728 /* If we have (compare (ashift FOO N) (const_int C)) and
11729 the high order N bits of FOO (N+1 if an inequality comparison)
11730 are known to be zero, we can do this by comparing FOO with C
11731 shifted right N bits so long as the low-order N bits of C are
11732 zero. */
11744 {
11745 /* We must perform a logical shift, not an arithmetic one,
11746 as we want the top N bits of C to be zero. */
11753 }
11755 /* If we are doing a sign bit comparison, it means we are testing
11756 a particular bit. Convert it to the appropriate AND. */
11759 {
11766 }
11768 /* If this an equality comparison with zero and we are shifting
11769 the low bit to the sign bit, we can convert this to an AND of the
11770 low-order bit. */
11774 {
11777 }
11781 /* If this is an equality comparison with zero, we can do this
11782 as a logical shift, which might be much simpler. */
11785 {
11790 }
11792 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11793 do the comparison in a narrower mode. */
11803 {
11806 }
11808 /* Likewise if OP0 is a PLUS of a sign extension with a
11809 constant, which is usually represented with the PLUS
11810 between the shifts. */
11822 {
11830 new_const);
11832 }
11834 /* ... fall through ... */
11836 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11837 the low order N bits of FOO are known to be zero, we can do this
11838 by comparing FOO with C shifted left N bits so long as no
11839 overflow occurs. Even if the low order N bits of FOO aren't known
11840 to be zero, if the comparison is >= or < we can use the same
11841 optimization and for > or <= by setting all the low
11842 order N bits in the comparison constant. */
11853 {
11854 unsigned HOST_WIDE_INT low_bits
11859 {
11860 /* If the shift was logical, then we must make the condition
11861 unsigned. */
11869 const_op
11874 }
11875 }
11877 /* If we are using this shift to extract just the sign bit, we
11878 can replace this with an LT or GE comparison. */
11883 {
11887 }
11892 }
11895 }
11897 /* Now make any compound operations involved in this comparison. Then,
11898 check for an outmost SUBREG on OP0 that is not doing anything or is
11899 paradoxical. The latter transformation must only be performed when
11900 it is known that the "extra" bits will be the same in op0 and op1 or
11901 that they don't matter. There are three cases to consider:
11903 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11904 care bits and we can assume they have any convenient value. So
11905 making the transformation is safe.
11907 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11908 In this case the upper bits of op0 are undefined. We should not make
11909 the simplification in that case as we do not know the contents of
11910 those bits.
11912 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11913 UNKNOWN. In that case we know those bits are zeros or ones. We must
11914 also be sure that they are the same as the upper bits of op1.
11916 We can never remove a SUBREG for a non-equality comparison because
11917 the sign bit is in a different place in the underlying object. */
11926 {
11929 {
11930 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11931 implemented. */
11933 {
11936 }
11937 }
11943 {
11949 }
11950 }
11952 /* We now do the opposite procedure: Some machines don't have compare
11953 insns in all modes. If OP0's mode is an integer mode smaller than a
11954 word and we can't do a compare in that mode, see if there is a larger
11955 mode for which we can do the compare. There are a number of cases in
11956 which we can use the wider mode. */
11967 {
11970 /* If this is a test for negative, we can make an explicit
11971 test of the sign bit. Test this first so we can use
11972 a paradoxical subreg to extend OP0. */
11976 {
11984 }
11986 /* If the only nonzero bits in OP0 and OP1 are those in the
11987 narrower mode and this is an equality or unsigned comparison,
11988 we can use the wider mode. Similarly for sign-extended
11989 values, in which case it is true for all comparisons. */
12006 {
12007 /* If OP0 is an AND and we don't have an AND in MODE either,
12008 make a new AND in the proper mode. */
12016 else
12017 {
12019 {
12022 }
12023 else
12024 {
12027 }
12029 }
12030 }
12031 }
12033 #ifdef CANONICALIZE_COMPARISON
12034 /* If this machine only supports a subset of valid comparisons, see if we
12035 can convert an unsupported one into a supported one. */
12037 #endif
12043 }
12044 \f
12045 /* Utility function for record_value_for_reg. Count number of
12046 rtxs in X. */
12047 static int
12049 {
12056 {
12076 }
12087 }
12088 \f
12089 /* Utility function for following routine. Called when X is part of a value
12090 being stored into last_set_value. Sets last_set_table_tick
12091 for each register mentioned. Similar to mention_regs in cse.c */
12093 static void
12095 {
12101 {
12107 {
12110 }
12113 }
12117 {
12118 /* Check for identical subexpressions. If x contains
12119 identical subexpression we only have to traverse one of
12120 them. */
12122 {
12123 /* Note that at this point x1 has already been
12124 processed. */
12128 /* If x0 and x1 are identical then there is no need to
12129 process x0. */
12133 /* If x0 is identical to a subexpression of x1 then while
12134 processing x1, x0 has already been processed. Thus we
12135 are done with x. */
12140 /* If x1 is identical to a subexpression of x0 then we
12141 still have to process the rest of x0. */
12144 {
12147 }
12148 }
12151 }
12155 }
12157 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12158 are saying that the register is clobbered and we no longer know its
12159 value. If INSN is zero, don't update reg_stat[].last_set; this is
12160 only permitted with VALUE also zero and is used to invalidate the
12161 register. */
12163 static void
12165 {
12171 /* If VALUE contains REG and we have a previous value for REG, substitute
12172 the previous value. */
12174 {
12175 rtx tem;
12177 /* Set things up so get_last_value is allowed to see anything set up to
12178 our insn. */
12182 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12183 it isn't going to be useful and will take a lot of time to process,
12184 so just use the CLOBBER. */
12187 {
12193 {
12194 /* If there are two or more occurrences of REG in VALUE,
12195 prevent the value from growing too much. */
12198 }
12201 }
12202 }
12204 /* For each register modified, show we don't know its value, that
12205 we don't know about its bitwise content, that its value has been
12206 updated, and that we don't know the location of the death of the
12207 register. */
12209 {
12221 }
12223 /* Mark registers that are being referenced in this value. */
12227 /* Now update the status of each register being set.
12228 If someone is using this register in this block, set this register
12229 to invalid since we will get confused between the two lives in this
12230 basic block. This makes using this register always invalid. In cse, we
12231 scan the table to invalidate all entries using this register, but this
12232 is too much work for us. */
12235 {
12241 else
12243 }
12245 /* The value being assigned might refer to X (like in "x++;"). In that
12246 case, we must replace it with (clobber (const_int 0)) to prevent
12247 infinite loops. */
12250 {
12254 }
12256 /* For the main register being modified, update the value, the mode, the
12257 nonzero bits, and the number of sign bit copies. */
12262 {
12270 rsp->last_set_sign_bit_copies
12272 }
12273 }
12275 /* Called via note_stores from record_dead_and_set_regs to handle one
12276 SET or CLOBBER in an insn. DATA is the instruction in which the
12277 set is occurring. */
12279 static void
12281 {
12288 {
12292 }
12295 {
12296 /* If we are setting the whole register, we know its value. Otherwise
12297 show that we don't know the value. We can handle SUBREG in
12298 some cases. */
12309 else
12311 }
12313 /* Ignore pushes, they clobber nothing. */
12316 }
12318 /* Update the records of when each REG was most recently set or killed
12319 for the things done by INSN. This is the last thing done in processing
12320 INSN in the combiner loop.
12322 We update reg_stat[], in particular fields last_set, last_set_value,
12323 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12324 last_death, and also the similar information mem_last_set (which insn
12325 most recently modified memory) and last_call_luid (which insn was the
12326 most recent subroutine call). */
12328 static void
12330 {
12331 rtx link;
12335 {
12338 {
12343 {
12348 }
12349 }
12352 }
12355 {
12358 {
12370 }
12374 /* We can't combine into a call pattern. Remember, though, that
12375 the return value register is set at this LUID. We could
12376 still replace a register with the return value from the
12377 wrong subroutine call! */
12379 }
12380 else
12382 }
12384 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12385 register present in the SUBREG, so for each such SUBREG go back and
12386 adjust nonzero and sign bit information of the registers that are
12387 known to have some zero/sign bits set.
12389 This is needed because when combine blows the SUBREGs away, the
12390 information on zero/sign bits is lost and further combines can be
12391 missed because of that. */
12393 static void
12395 {
12404 {
12413 {
12416 }
12420 {
12423 }
12426 {
12429 }
12430 else
12432 }
12433 }
12435 /* Check if X, a register, is known to contain a value already
12436 truncated to MODE. In this case we can use a subreg to refer to
12437 the truncated value even though in the generic case we would need
12438 an explicit truncation. */
12440 static bool
12442 {
12455 }
12457 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12458 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12459 might be able to turn a truncate into a subreg using this information.
12460 Return -1 if traversing *P is complete or 0 otherwise. */
12462 static int
12464 {
12470 {
12482 }
12483 /* ??? For hard-regs we now record everything. We might be able to
12484 optimize this using last_set_mode. */
12487 else
12495 {
12498 }
12501 }
12503 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12504 the modes they are used in. This can help truning TRUNCATEs into
12505 SUBREGs. */
12507 static void
12509 {
12511 }
12513 /* Scan X for promoted SUBREGs. For each one found,
12514 note what it implies to the registers used in it. */
12516 static void
12518 {
12523 else
12524 {
12530 {
12540 }
12541 }
12542 }
12543 \f
12544 /* Verify that all the registers and memory references mentioned in *LOC are
12545 still valid. *LOC was part of a value set in INSN when label_tick was
12546 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12547 the invalid references with (clobber (const_int 0)) and return 1. This
12548 replacement is useful because we often can get useful information about
12549 the form of a value (e.g., if it was produced by a shift that always
12550 produces -1 or 0) even though we don't know exactly what registers it
12551 was produced from. */
12553 static int
12555 {
12562 {
12568 {
12571 /* If this is a pseudo-register that was only set once and not
12572 live at the beginning of the function, it is always valid. */
12575 && (!REGNO_REG_SET_P
12578 {
12582 }
12583 }
12586 }
12587 /* If this is a memory reference, make sure that there were no stores after
12588 it that might have clobbered the value. We don't have alias info, so we
12589 assume any store invalidates it. Moreover, we only have local UIDs, so
12590 we also assume that there were stores in the intervening basic blocks. */
12593 {
12597 }
12600 {
12602 {
12603 /* Check for identical subexpressions. If x contains
12604 identical subexpression we only have to traverse one of
12605 them. */
12607 {
12608 /* Note that at this point x0 has already been checked
12609 and found valid. */
12613 /* If x0 and x1 are identical then x is also valid. */
12617 /* If x1 is identical to a subexpression of x0 then
12618 while checking x0, x1 has already been checked. Thus
12619 it is valid and so as x. */
12624 /* If x0 is identical to a subexpression of x1 then x is
12625 valid iff the rest of x1 is valid. */
12628 return
12632 }
12637 }
12643 }
12645 /* If we haven't found a reason for it to be invalid, it is valid. */
12647 }
12649 /* Get the last value assigned to X, if known. Some registers
12650 in the value may be replaced with (clobber (const_int 0)) if their value
12651 is known longer known reliably. */
12653 static rtx
12655 {
12657 rtx value;
12660 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12661 then convert it to the desired mode. If this is a paradoxical SUBREG,
12662 we cannot predict what values the "extra" bits might have. */
12677 /* If we don't have a value, or if it isn't for this basic block and
12678 it's either a hard register, set more than once, or it's a live
12679 at the beginning of the function, return 0.
12681 Because if it's not live at the beginning of the function then the reg
12682 is always set before being used (is never used without being set).
12683 And, if it's set only once, and it's always set before use, then all
12684 uses must have the same last value, even if it's not from this basic
12685 block. */
12691 || REGNO_REG_SET_P
12695 /* If the value was set in a later insn than the ones we are processing,
12696 we can't use it even if the register was only set once. */
12701 /* If the value has all its registers valid, return it. */
12705 /* Otherwise, make a copy and replace any invalid register with
12706 (clobber (const_int 0)). If that fails for some reason, return 0. */
12713 }
12714 \f
12715 /* Return nonzero if expression X refers to a REG or to memory
12716 that is set in an instruction more recent than FROM_LUID. */
12718 static int
12720 {
12726 {
12730 #ifdef PUSH_ROUNDING
12731 /* Don't allow uses of the stack pointer to be moved,
12732 because we don't know whether the move crosses a push insn. */
12735 #endif
12737 {
12743 }
12745 }
12753 {
12755 {
12760 }
12764 }
12766 }
12767 \f
12768 /* Define three variables used for communication between the following
12769 routines. */
12774 /* Function called via note_stores from reg_dead_at_p.
12776 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12777 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12779 static void
12781 {
12791 }
12793 /* Return nonzero if REG is known to be dead at INSN.
12795 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12796 referencing REG, it is dead. If we hit a SET referencing REG, it is
12797 live. Otherwise, see if it is live or dead at the start of the basic
12798 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12799 must be assumed to be always live. */
12801 static int
12803 {
12804 basic_block block;
12807 /* Set variables for reg_dead_at_p_1. */
12813 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12814 we allow the machine description to decide whether use-and-clobber
12815 patterns are OK. */
12817 {
12821 }
12823 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12824 beginning of basic block. */
12827 {
12829 {
12836 }
12842 }
12844 /* Look at live-in sets for the basic block that we were in. */
12850 }
12851 \f
12852 /* Note hard registers in X that are used. */
12854 static void
12856 {
12862 {
12873 #ifdef HAVE_cc0
12874 /* CC0 must die in the insn after it is set, so we don't need to take
12875 special note of it here. */
12877 #endif
12881 /* If we are clobbering a MEM, mark any hard registers inside the
12882 address as used. */
12889 /* A hard reg in a wide mode may really be multiple registers.
12890 If so, mark all of them just like the first. */
12892 {
12893 /* None of this applies to the stack, frame or arg pointers. */
12895 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12897 #endif
12898 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12900 #endif
12905 }
12909 {
12910 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12911 the address. */
12923 }
12928 }
12930 /* Recursively scan the operands of this expression. */
12932 {
12936 {
12940 {
12945 }
12946 }
12947 }
12948 }
12949 \f
12950 /* Remove register number REGNO from the dead registers list of INSN.
12952 Return the note used to record the death, if there was one. */
12954 rtx
12956 {
12963 }
12965 /* For each register (hardware or pseudo) used within expression X, if its
12966 death is in an instruction with luid between FROM_LUID (inclusive) and
12967 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12968 list headed by PNOTES.
12970 That said, don't move registers killed by maybe_kill_insn.
12972 This is done when X is being merged by combination into TO_INSN. These
12973 notes will then be distributed as needed. */
12975 static void
12978 {
12984 {
12988 /* Don't move the register if it gets killed in between from and to. */
12997 {
13000 /* It is possible for the call above to return 0. This can occur
13001 when last_death points to I2 or I1 that we combined with.
13002 In that case make a new note.
13004 We must also check for the case where X is a hard register
13005 and NOTE is a death note for a range of hard registers
13006 including X. In that case, we must put REG_DEAD notes for
13007 the remaining registers in place of NOTE. */
13012 {
13021 }
13023 /* If we didn't find any note, or if we found a REG_DEAD note that
13024 covers only part of the given reg, and we have a multi-reg hard
13025 register, then to be safe we must check for REG_DEAD notes
13026 for each register other than the first. They could have
13027 their own REG_DEAD notes lying around. */
13034 {
13041 else
13047 }
13050 {
13053 }
13054 else
13056 }
13059 }
13062 {
13067 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13068 that accesses one word of a multi-word item, some
13069 piece of everything register in the expression is used by
13070 this insn, so remove any old death. */
13071 /* ??? So why do we test for equality of the sizes? */
13080 {
13083 }
13085 /* If this is some other SUBREG, we know it replaces the entire
13086 value, so use that as the destination. */
13090 /* If this is a MEM, adjust deaths of anything used in the address.
13091 For a REG (the only other possibility), the entire value is
13092 being replaced so the old value is not used in this insn. */
13098 }
13107 {
13109 {
13114 }
13117 }
13118 }
13119 \f
13120 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13121 pattern of an insn. X must be a REG. */
13123 static int
13125 {
13129 {
13131 rtx target;
13138 else
13155 }
13163 }
13164 \f
13165 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13166 as appropriate. I3 and I2 are the insns resulting from the combination
13167 insns including FROM (I2 may be zero).
13169 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13170 not need REG_DEAD notes because they are being substituted for. This
13171 saves searching in the most common cases.
13173 Each note in the list is either ignored or placed on some insns, depending
13174 on the type of note. */
13176 static void
13179 {
13181 rtx tem;
13184 {
13189 {
13192 /* Doesn't matter much where we put this, as long as it's somewhere.
13193 It is preferable to keep these notes on branches, which is most
13194 likely to be i3. */
13201 else
13202 {
13205 }
13209 /* These notes must remain with the call or trapping instruction. */
13214 else
13215 {
13221 /* ??? Otherwise assume we've combined things such that we
13222 can now prove that the instructions can't trap. Drop the
13223 note in this case. */
13224 }
13229 /* These notes must remain with the call. It should not be
13230 possible for both I2 and I3 to be a call. */
13233 else
13234 {
13237 }
13241 /* Any clobbers for i3 may still exist, and so we must process
13242 REG_UNUSED notes from that insn.
13244 Any clobbers from i2 or i1 can only exist if they were added by
13245 recog_for_combine. In that case, recog_for_combine created the
13246 necessary REG_UNUSED notes. Trying to keep any original
13247 REG_UNUSED notes from these insns can cause incorrect output
13248 if it is for the same register as the original i3 dest.
13249 In that case, we will notice that the register is set in i3,
13250 and then add a REG_UNUSED note for the destination of i3, which
13251 is wrong. However, it is possible to have REG_UNUSED notes from
13252 i2 or i1 for register which were both used and clobbered, so
13253 we keep notes from i2 or i1 if they will turn into REG_DEAD
13254 notes. */
13256 /* If this register is set or clobbered in I3, put the note there
13257 unless there is one already. */
13259 {
13267 }
13268 /* Otherwise, if this register is used by I3, then this register
13269 now dies here, so we must put a REG_DEAD note here unless there
13270 is one already. */
13276 {
13279 }
13285 /* These notes say something about results of an insn. We can
13286 only support them if they used to be on I3 in which case they
13287 remain on I3. Otherwise they are ignored.
13289 If the note refers to an expression that is not a constant, we
13290 must also ignore the note since we cannot tell whether the
13291 equivalence is still true. It might be possible to do
13292 slightly better than this (we only have a problem if I2DEST
13293 or I1DEST is present in the expression), but it doesn't
13294 seem worth the trouble. */
13302 /* These notes say something about how a register is used. They must
13303 be present on any use of the register in I2 or I3. */
13308 {
13311 else
13313 }
13318 /* This can show up in several ways -- either directly in the
13319 pattern, or hidden off in the constant pool with (or without?)
13320 a REG_EQUAL note. */
13321 /* ??? Ignore the without-reg_equal-note problem for now. */
13333 {
13336 else
13338 }
13340 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13341 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13342 there. */
13347 {
13354 }
13360 {
13368 }
13372 /* This note says something about the value of a register prior
13373 to the execution of an insn. It is too much trouble to see
13374 if the note is still correct in all situations. It is better
13375 to simply delete it. */
13379 /* If we replaced the right hand side of FROM_INSN with a
13380 REG_EQUAL note, the original use of the dying register
13381 will not have been combined into I3 and I2. In such cases,
13382 FROM_INSN is guaranteed to be the first of the combined
13383 instructions, so we simply need to search back before
13384 FROM_INSN for the previous use or set of this register,
13385 then alter the notes there appropriately.
13387 If the register is used as an input in I3, it dies there.
13388 Similarly for I2, if it is nonzero and adjacent to I3.
13390 If the register is not used as an input in either I3 or I2
13391 and it is not one of the registers we were supposed to eliminate,
13392 there are two possibilities. We might have a non-adjacent I2
13393 or we might have somehow eliminated an additional register
13394 from a computation. For example, we might have had A & B where
13395 we discover that B will always be zero. In this case we will
13396 eliminate the reference to A.
13398 In both cases, we must search to see if we can find a previous
13399 use of A and put the death note there. */
13405 else
13406 {
13417 && !(i2mod
13419 i2mod_old_rhs)))
13424 }
13427 {
13431 {
13433 {
13437 }
13439 /* If the register is being set at TEM, see if that is all
13440 TEM is doing. If so, delete TEM. Otherwise, make this
13441 into a REG_UNUSED note instead. Don't delete sets to
13442 global register vars. */
13446 {
13449 #ifdef HAVE_cc0
13451 #endif
13459 ;
13461 /* Verify that it was the set, and not a clobber that
13462 modified the register.
13464 CC0 targets must be careful to maintain setter/user
13465 pairs. If we cannot delete the setter due to side
13466 effects, mark the user with an UNUSED note instead
13467 of deleting it. */
13471 #ifdef HAVE_cc0
13475 #endif
13476 )
13477 {
13478 /* Move the notes and links of TEM elsewhere.
13479 This might delete other dead insns recursively.
13480 First set the pattern to something that won't use
13481 any register. */
13495 #ifdef HAVE_cc0
13496 /* Delete the setter too. */
13498 {
13511 }
13512 #endif
13513 }
13514 else
13515 {
13518 /* If there isn't already a REG_UNUSED note, put one
13519 here. Do not place a REG_DEAD note, even if
13520 the register is also used here; that would not
13521 match the algorithm used in lifetime analysis
13522 and can cause the consistency check in the
13523 scheduler to fail. */
13528 }
13529 }
13533 {
13536 /* If we are doing a 3->2 combination, and we have a
13537 register which formerly died in i3 and was not used
13538 by i2, which now no longer dies in i3 and is used in
13539 i2 but does not die in i2, and place is between i2
13540 and i3, then we may need to move a link from place to
13541 i2. */
13543 && from_insn
13546 {
13550 }
13552 }
13556 }
13558 }
13560 /* If the register is set or already dead at PLACE, we needn't do
13561 anything with this note if it is still a REG_DEAD note.
13562 We check here if it is set at all, not if is it totally replaced,
13563 which is what `dead_or_set_p' checks, so also check for it being
13564 set partially. */
13567 {
13573 {
13574 /* Unless the register previously died in PLACE, clear
13575 last_death. [I no longer understand why this is
13576 being done.] */
13580 }
13581 else
13584 /* If this is a death note for a hard reg that is occupying
13585 multiple registers, ensure that we are still using all
13586 parts of the object. If we find a piece of the object
13587 that is unused, we must arrange for an appropriate REG_DEAD
13588 note to be added for it. However, we can't just emit a USE
13589 and tag the note to it, since the register might actually
13590 be dead; so we recourse, and the recursive call then finds
13591 the previous insn that used this register. */
13595 {
13607 {
13608 /* Put only REG_DEAD notes for pieces that are
13609 not already dead or set. */
13613 {
13620 {
13622 NULL_RTX);
13626 NULL_RTX);
13627 }
13633 {
13635 {
13639 }
13643 {
13646 }
13647 }
13649 }
13652 }
13653 }
13654 }
13658 /* Any other notes should not be present at this point in the
13659 compilation. */
13661 }
13664 {
13667 }
13671 }
13672 }
13673 \f
13674 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13675 I3, I2, and I1 to new locations. This is also called to add a link
13676 pointing at I3 when I3's destination is changed. */
13678 static void
13680 {
13684 {
13686 rtx insn;
13691 /* If the insn that this link points to is a NOTE or isn't a single
13692 set, ignore it. In the latter case, it isn't clear what we
13693 can do other than ignore the link, since we can't tell which
13694 register it was for. Such links wouldn't be used by combine
13695 anyway.
13697 It is not possible for the destination of the target of the link to
13698 have been changed by combine. The only potential of this is if we
13699 replace I3, I2, and I1 by I3 and I2. But in that case the
13700 destination of I2 also remains unchanged. */
13711 /* A LOG_LINK is defined as being placed on the first insn that uses
13712 a register and points to the insn that sets the register. Start
13713 searching at the next insn after the target of the link and stop
13714 when we reach a set of the register or the end of the basic block.
13716 Note that this correctly handles the link that used to point from
13717 I3 to I2. Also note that not much searching is typically done here
13718 since most links don't point very far away. */
13727 {
13731 }
13734 {
13737 }
13741 /* If we found a place to put the link, place it there unless there
13742 is already a link to the same insn as LINK at that point. */
13745 {
13746 rtx link2;
13753 {
13757 /* Set added_links_insn to the earliest insn we added a
13758 link to. */
13762 }
13763 }
13764 }
13765 }
13766 \f
13767 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13768 Check whether the expression pointer to by LOC is a register or
13769 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13770 Otherwise return zero. */
13772 static int
13774 {
13782 }
13784 /* Check for any register or memory mentioned in EQUIV that is not
13785 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13786 of EXPR where some registers may have been replaced by constants. */
13788 static bool
13790 {
13792 }
13793 \f
13794 void
13796 {
13797 fprintf
13799 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13801 }
13803 void
13805 {
13806 fprintf
13808 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13810 }
13811 \f
13812 static bool
13814 {
13816 }
13818 /* Try combining insns through substitution. */
13819 static unsigned int
13821 {
13830 rebuild_jump_labels_after_combine
13833 /* Combining insns may have turned an indirect jump into a
13834 direct jump. Rebuild the JUMP_LABEL fields of jumping
13835 instructions. */
13837 {
13842 }
13846 }
13849 {
13850 {
13851 RTL_PASS,
13863 TODO_dump_func |
13866 }
13867 };