1 ; Options for the SH port of the compiler.
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
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13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
21 ;; Used for various architecture options.
24 ;; Set if the default precision of th FPU is single.
27 ;; Set if we should generate code using type 2A insns.
30 ;; Set if we should generate code using type 2A DF insns.
31 Mask(HARD_SH2A_DOUBLE)
33 ;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
36 ;; Set if we should generate code for a SH5 CPU (either ISA).
39 ;; Set if we should save all target registers.
40 Mask(SAVE_ALL_TARGET_REGS)
43 Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
47 Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
51 Target RejectNegative Condition(SUPPORT_SH2A)
52 Generate default double-precision SH2a-FPU code
55 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
56 Generate SH2a FPU-less code
59 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
60 Generate default single-precision SH2a-FPU code
63 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
64 Generate only single-precision SH2a-FPU code
67 Target RejectNegative Condition(SUPPORT_SH2E)
71 Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
75 Target RejectNegative Condition(SUPPORT_SH3E)
79 Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
83 Target RejectNegative Condition(SUPPORT_SH4)
87 Target RejectNegative Condition(SUPPORT_SH4)
90 ;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
91 ;; pipeline - irrespective of ABI.
93 Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
97 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
98 Generate SH4 FPU-less code
101 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
102 Generate SH4-100 FPU-less code
105 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
106 Generate SH4-200 FPU-less code
109 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
110 Generate SH4-300 FPU-less code
113 Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists
114 Generate code for SH4 340 series (MMU/FPU-less)
115 ;; passes -isa=sh4-nommu-nofpu to the assembler.
118 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
119 Generate code for SH4 400 series (MMU/FPU-less)
120 ;; passes -isa=sh4-nommu-nofpu to the assembler.
123 Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
124 Generate code for SH4 500 series (FPU-less).
125 ;; passes -isa=sh4-nofpu to the assembler.
128 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
129 Generate default single-precision SH4 code
132 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
133 Generate default single-precision SH4-100 code
136 Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
137 Generate default single-precision SH4-200 code
140 Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists
141 Generate default single-precision SH4-300 code
144 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
145 Generate only single-precision SH4 code
148 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
149 Generate only single-precision SH4-100 code
152 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
153 Generate only single-precision SH4-200 code
156 Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists
157 Generate only single-precision SH4-300 code
160 Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
164 Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
165 Generate SH4a FPU-less code
168 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
169 Generate default single-precision SH4a code
172 Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
173 Generate only single-precision SH4a code
176 Target RejectNegative Condition(SUPPORT_SH4AL)
177 Generate SH4al-dsp code
180 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
181 Generate 32-bit SHmedia code
184 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
185 Generate 32-bit FPU-less SHmedia code
188 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
189 Generate 64-bit SHmedia code
192 Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
193 Generate 64-bit FPU-less SHmedia code
196 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
197 Generate SHcompact code
200 Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
201 Generate FPU-less SHcompact code
203 maccumulate-outgoing-args
204 Target Report Mask(ACCUMULATE_OUTGOING_ARGS)
205 Reserve space for outgoing arguments in the function prologue
208 Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5)
209 Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this
212 Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
213 Generate code in big endian mode
216 Target Report RejectNegative Mask(BIGTABLE)
217 Generate 32-bit offsets in switch tables
220 Target Report RejectNegative Mask(BITOPS)
221 Generate bit instructions
224 Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
225 Cost to assume for a branch insn
228 Target Var(TARGET_CBRANCHDI4)
229 Enable cbranchdi4 pattern
232 Target Var(TARGET_CMPEQDI_T)
233 Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
236 Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
237 Enable SH5 cut2 workaround
240 Target Report RejectNegative Mask(ALIGN_DOUBLE)
241 Align doubles at 64-bit boundaries
244 Target RejectNegative Joined Var(sh_div_str) Init("")
245 Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table
248 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
249 Specify name for 32 bit signed division function
252 Target RejectNegative Mask(FMOVD)
253 Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
256 Target RejectNegative Joined Var(sh_fixed_range_str)
257 Specify range of registers to make fixed
260 Target Var(TARGET_FMAC)
261 Enable the use of the fused floating point multiply-accumulate operation
264 Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
265 Cost to assume for gettr insn
268 Target Report RejectNegative Mask(HITACHI)
269 Follow Renesas (formerly Hitachi) / SuperH calling conventions
272 Target Report Mask(IEEE)
273 Increase the IEEE compliance for floating-point code
276 Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
277 Enable the use of the indexed addressing mode for SHmedia32/SHcompact
279 minline-ic_invalidate
280 Target Report Var(TARGET_INLINE_IC_INVALIDATE)
281 inline code to invalidate instruction cache entries after setting up nested function trampolines
284 Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
285 Assume symbols might be invalid
288 Target Report RejectNegative Mask(DUMPISIZE)
289 Annotate assembler instructions with estimated addresses
292 Target Report RejectNegative Mask(LITTLE_ENDIAN)
293 Generate code in little endian mode
296 Target Report RejectNegative Mask(NOMACSAVE)
297 Mark MAC register as call-clobbered
299 ;; ??? This option is not useful, but is retained in case there are people
300 ;; who are still relying on it. It may be deleted in the future.
302 Target Report RejectNegative Mask(PADSTRUCT)
303 Make structs a multiple of 4 bytes (warning: ABI altered)
306 Target Report RejectNegative Mask(PREFERGOT)
307 Emit function-calls using global offset table when generating PIC
310 Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
311 Assume pt* instructions won't trap
314 Target Report RejectNegative Mask(RELAX)
315 Shorten address references during linking
318 Target Mask(HITACHI) MaskExists
319 Follow Renesas (formerly Hitachi) / SuperH calling conventions
322 Target Report RejectNegative Mask(SMALLCODE)
323 Deprecated. Use -Os instead
326 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
327 Cost to assume for a multiply insn
330 Target Report RejectNegative Mask(USERMODE)
331 Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
333 ;; We might want to enable this by default for TARGET_HARD_SH4, because
334 ;; zero-offset branches have zero latency. Needs some benchmarking.
336 Target Var(TARGET_PRETEND_CMOVE)
337 Pretend a branch-around-a-move is a conditional move.