| blob | 7d3c5b2eebe622a0b89d1cf592f9a9ee51c6227d |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
59 /* Not really meaningful values, but at least something. */
60 #ifndef SIMULTANEOUS_PREFETCHES
61 #define SIMULTANEOUS_PREFETCHES 3
62 #endif
63 #ifndef PREFETCH_BLOCK
64 #define PREFETCH_BLOCK 32
65 #endif
66 #ifndef HAVE_prefetch
67 #define HAVE_prefetch 0
68 #define CODE_FOR_prefetch 0
69 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
70 #endif
72 /* Give up the prefetch optimizations once we exceed a given threshhold.
73 It is unlikely that we would be able to optimize something in a loop
74 with so many detected prefetches. */
75 #define MAX_PREFETCHES 100
76 /* The number of prefetch blocks that are beneficial to fetch at once before
77 a loop with a known (and low) iteration count. */
78 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
79 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
80 since it is likely that the data are already in the cache. */
81 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
82 /* The minimal number of prefetch blocks that a loop must consume to make
83 the emitting of prefetch instruction in the body of loop worthwhile. */
84 #define PREFETCH_BLOCKS_IN_LOOP_MIN 6
86 /* Parameterize some prefetch heuristics so they can be turned on and off
87 easily for performance testing on new architecures. These can be
88 defined in target-dependent files. */
90 /* Prefetch is worthwhile only when loads/stores are dense. */
91 #ifndef PREFETCH_ONLY_DENSE_MEM
92 #define PREFETCH_ONLY_DENSE_MEM 1
93 #endif
95 /* Define what we mean by "dense" loads and stores; This value divided by 256
96 is the minimum percentage of memory references that worth prefetching. */
97 #ifndef PREFETCH_DENSE_MEM
98 #define PREFETCH_DENSE_MEM 220
99 #endif
101 /* Do not prefetch for a loop whose iteration count is known to be low. */
102 #ifndef PREFETCH_NO_LOW_LOOPCNT
103 #define PREFETCH_NO_LOW_LOOPCNT 1
104 #endif
106 /* Define what we mean by a "low" iteration count. */
107 #ifndef PREFETCH_LOW_LOOPCNT
108 #define PREFETCH_LOW_LOOPCNT 32
109 #endif
111 /* Do not prefetch for a loop that contains a function call; such a loop is
112 probably not an internal loop. */
113 #ifndef PREFETCH_NO_CALL
114 #define PREFETCH_NO_CALL 1
115 #endif
117 /* Do not prefetch accesses with an extreme stride. */
118 #ifndef PREFETCH_NO_EXTREME_STRIDE
119 #define PREFETCH_NO_EXTREME_STRIDE 1
120 #endif
122 /* Define what we mean by an "extreme" stride. */
123 #ifndef PREFETCH_EXTREME_STRIDE
124 #define PREFETCH_EXTREME_STRIDE 4096
125 #endif
127 /* Define a limit to how far apart indices can be and still be merged
128 into a single prefetch. */
129 #ifndef PREFETCH_EXTREME_DIFFERENCE
130 #define PREFETCH_EXTREME_DIFFERENCE 4096
131 #endif
133 /* Issue prefetch instructions before the loop to fetch data to be used
134 in the first few loop iterations. */
135 #ifndef PREFETCH_BEFORE_LOOP
136 #define PREFETCH_BEFORE_LOOP 1
137 #endif
139 /* Do not handle reversed order prefetches (negative stride). */
140 #ifndef PREFETCH_NO_REVERSE_ORDER
141 #define PREFETCH_NO_REVERSE_ORDER 1
142 #endif
144 /* Prefetch even if the GIV is in conditional code. */
145 #ifndef PREFETCH_CONDITIONAL
146 #define PREFETCH_CONDITIONAL 1
147 #endif
149 /* If the loop requires more prefetches than the target can process in
150 parallel then don't prefetch anything in that loop. */
151 #ifndef PREFETCH_LIMIT_TO_SIMULTANEOUS
152 #define PREFETCH_LIMIT_TO_SIMULTANEOUS 1
153 #endif
155 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
156 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
158 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
159 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
160 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
162 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
163 ((REGNO) < FIRST_PSEUDO_REGISTER \
164 ? HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
167 /* Vector mapping INSN_UIDs to luids.
168 The luids are like uids but increase monotonically always.
169 We use them to see whether a jump comes from outside a given loop. */
173 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
174 number the insn is contained in. */
178 /* 1 + largest uid of any insn. */
182 /* 1 + luid of last insn. */
186 /* Number of loops detected in current function. Used as index to the
187 next few tables. */
191 /* Bound on pseudo register number before loop optimization.
192 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
195 /* The value to pass to the next call of reg_scan_update. */
198 #define obstack_chunk_alloc xmalloc
199 #define obstack_chunk_free free
200 \f
201 /* During the analysis of a loop, a chain of `struct movable's
202 is made to record all the movable insns found.
203 Then the entire chain can be scanned to decide which to move. */
205 struct movable
206 {
211 of any registers used within the LIBCALL. */
213 that must be moved with this one. */
216 may be adjusted when matching movables
217 that load the same value are found. */
219 including other movables that force this
220 or match this one. */
224 /* If PARTIAL is 1, GLOBAL means something different:
225 that the reg is live outside the range from where it is set
226 to the following label. */
230 In particular, moving it does not make it
231 invariant. */
233 load SRC, rather than copying INSN. */
235 first insn of a consecutive sets group. */
238 that we should avoid changing when clearing
239 the rest of the reg. */
243 };
248 /* Forward declarations. */
263 #if 0
265 #endif
295 rtx *));
378 {
379 rtx r1;
380 rtx r2;
384 {
385 rtx match;
386 rtx replacement;
387 rtx insn;
390 /* Nonzero iff INSN is between START and END, inclusive. */
391 #define INSN_IN_RANGE_P(INSN, START, END) \
392 (INSN_UID (INSN) < max_uid_for_loop \
393 && INSN_LUID (INSN) >= INSN_LUID (START) \
394 && INSN_LUID (INSN) <= INSN_LUID (END))
396 /* Indirect_jump_in_function is computed once per function. */
404 rtx));
405 \f
406 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
407 copy the value of the strength reduced giv to its original register. */
410 /* Cost of using a register, to normalize the benefits of a giv. */
413 void
415 {
421 }
422 \f
423 /* Compute the mapping from uids to luids.
424 LUIDs are numbers assigned to insns, like uids,
425 except that luids increase monotonically through the code.
426 Start at insn START and stop just before END. Assign LUIDs
427 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
428 static int
432 {
434 rtx insn;
437 {
440 /* Don't assign luids to line-number NOTEs, so that the distance in
441 luids between two insns is not affected by -g. */
445 else
446 /* Give a line number note the same luid as preceding insn. */
448 }
450 }
451 \f
452 /* Entry point of this file. Perform loop optimization
453 on the current function. F is the first insn of the function
454 and DUMPFILE is a stream for output of a trace of actions taken
455 (or 0 if none should be output). */
457 void
459 /* f is the first instruction of a chain of insns for one function */
460 rtx f;
463 {
464 rtx insn;
479 /* Count the number of loops. */
483 {
486 max_loop_num++;
487 }
489 /* Don't waste time if no loops. */
495 /* Get size to use for tables indexed by uids.
496 Leave some space for labels allocated by find_and_verify_loops. */
503 /* Allocate storage for array of loops. */
507 /* Find and process each loop.
508 First, find them, and record them in order of their beginnings. */
511 /* Allocate and initialize auxiliary loop information. */
516 /* Now find all register lifetimes. This must be done after
517 find_and_verify_loops, because it might reorder the insns in the
518 function. */
521 /* This must occur after reg_scan so that registers created by gcse
522 will have entries in the register tables.
524 We could have added a call to reg_scan after gcse_main in toplev.c,
525 but moving this call to init_alias_analysis is more efficient. */
528 /* See if we went too far. Note that get_max_uid already returns
529 one more that the maximum uid of all insn. */
532 /* Now reset it to the actual size we need. See above. */
535 /* find_and_verify_loops has already called compute_luids, but it
536 might have rearranged code afterwards, so we need to recompute
537 the luids now. */
540 /* Don't leave gaps in uid_luid for insns that have been
541 deleted. It is possible that the first or last insn
542 using some register has been deleted by cross-jumping.
543 Make sure that uid_luid for that former insn's uid
544 points to the general area where that insn used to be. */
546 {
550 }
555 /* Determine if the function has indirect jump. On some systems
556 this prevents low overhead loop instructions from being used. */
559 /* Now scan the loops, last ones first, since this means inner ones are done
560 before outer ones. */
562 {
567 }
569 /* If there were lexical blocks inside the loop, they have been
570 replicated. We will now have more than one NOTE_INSN_BLOCK_BEG
571 and NOTE_INSN_BLOCK_END for each such block. We must duplicate
572 the BLOCKs as well. */
578 /* Clean up. */
583 }
584 \f
585 /* Returns the next insn, in execution order, after INSN. START and
586 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
587 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
588 insn-stream; it is used with loops that are entered near the
589 bottom. */
591 static rtx
594 rtx insn;
595 {
599 {
601 /* Go to the top of the loop, and continue there. */
603 else
604 /* We're done. */
606 }
609 /* We're done. */
613 }
615 /* Optimize one loop described by LOOP. */
617 /* ??? Could also move memory writes out of loops if the destination address
618 is invariant, the source is invariant, the memory write is not volatile,
619 and if we can prove that no read inside the loop can read this address
620 before the write occurs. If there is a read of this address after the
621 write, then we can also mark the memory read as invariant. */
623 static void
627 {
633 rtx p;
634 /* 1 if we are scanning insns that could be executed zero times. */
636 /* 1 if we are scanning insns that might never be executed
637 due to a subroutine call which might exit before they are reached. */
639 /* Jump insn that enters the loop, or 0 if control drops in. */
641 /* Number of insns in the loop. */
645 /* The SET from an insn, if it is the only SET in the insn. */
647 /* Chain describing insns movable in current loop. */
649 /* Ratio of extra register life span we can justify
650 for saving an instruction. More if loop doesn't call subroutines
651 since in that case saving an insn makes more difference
652 and more registers are available. */
654 /* Nonzero if we are scanning instructions in a sub-loop. */
662 /* Determine whether this loop starts with a jump down to a test at
663 the end. This will occur for a small number of loops with a test
664 that is too complex to duplicate in front of the loop.
666 We search for the first insn or label in the loop, skipping NOTEs.
667 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
668 (because we might have a loop executed only once that contains a
669 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
670 (in case we have a degenerate loop).
672 Note that if we mistakenly think that a loop is entered at the top
673 when, in fact, it is entered at the exit test, the only effect will be
674 slightly poorer optimization. Making the opposite error can generate
675 incorrect code. Since very few loops now start with a jump to the
676 exit test, the code here to detect that case is very conservative. */
679 p != loop_end
685 ;
689 /* If loop end is the end of the current function, then emit a
690 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
691 note insn. This is the position we use when sinking insns out of
692 the loop. */
695 else
698 /* Set up variables describing this loop. */
702 /* If loop has a jump before the first label,
703 the true entry is the target of that jump.
704 Start scan from there.
705 But record in LOOP->TOP the place where the end-test jumps
706 back to so we can scan that after the end of the loop. */
708 {
711 /* Loop entry must be unconditional jump (and not a RETURN) */
714 /* Check to see whether the jump actually
715 jumps out of the loop (meaning it's no loop).
716 This case can happen for things like
717 do {..} while (0). If this label was generated previously
718 by loop, we can't tell anything about it and have to reject
719 the loop. */
721 {
724 }
725 }
727 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
728 as required by loop_reg_used_before_p. So skip such loops. (This
729 test may never be true, but it's best to play it safe.)
731 Also, skip loops where we do not start scanning at a label. This
732 test also rejects loops starting with a JUMP_INSN that failed the
733 test above. */
737 {
742 }
744 /* Allocate extra space for REGs that might be created by load_mems.
745 We allocate a little extra slop as well, in the hopes that we
746 won't have to reallocate the regs array. */
751 {
757 }
759 /* Scan through the loop finding insns that are safe to move.
760 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
761 this reg will be considered invariant for subsequent insns.
762 We consider whether subsequent insns use the reg
763 in deciding whether it is worth actually moving.
765 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
766 and therefore it is possible that the insns we are scanning
767 would never be executed. At such times, we must make sure
768 that it is safe to execute the insn once instead of zero times.
769 When MAYBE_NEVER is 0, all insns will be executed at least once
770 so that is not a problem. */
775 {
779 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
781 #endif
783 {
790 /* Figure out what to use as a source of this insn. If a REG_EQUIV
791 note is given or if a REG_EQUAL note with a constant operand is
792 specified, use it as the source and mark that we should move
793 this insn by calling emit_move_insn rather that duplicating the
794 insn.
796 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL note
797 is present. */
801 else
802 {
807 {
809 /* A libcall block can use regs that don't appear in
810 the equivalent expression. To move the libcall,
811 we must move those regs too. */
813 }
814 }
816 /* For parallels, add any possible uses to the depencies, as we can't move
817 the insn without resolving them first. */
819 {
821 {
825 }
826 }
828 /* Don't try to optimize a register that was made
829 by loop-optimization for an inner loop.
830 We don't know its life-span, so we can't compute the benefit. */
832 ;
834 than the one where it is set (meaning that
835 something after this point in the loop might
836 depend on its value before the set). */
838 /* And the set is not guaranteed to be executed once
839 the loop starts, or the value before the set is
840 needed before the set occurs...
842 ??? Note we have quadratic behaviour here, mitigated
843 by the fact that the previous test will often fail for
844 large loops. Rather than re-scanning the entire loop
845 each time for register usage, we should build tables
846 of the register usage and use them here instead. */
847 && (maybe_never
849 /* It is unsafe to move the set.
851 This code used to consider it OK to move a set of a variable
852 which was not created by the user and not used in an exit test.
853 That behavior is incorrect and was removed. */
854 ;
859 || (tem1
860 = consec_sets_invariant_p
863 p)))
864 /* If the insn can cause a trap (such as divide by zero),
865 can't move it unless it's guaranteed to be executed
866 once loop is entered. Even a function call might
867 prevent the trap insn from being reached
868 (since it might exit!) */
871 {
875 /* A potential lossage is where we have a case where two insns
876 can be combined as long as they are both in the loop, but
877 we move one of them outside the loop. For large loops,
878 this can lose. The most common case of this is the address
879 of a function being called.
881 Therefore, if this register is marked as being used exactly
882 once if we are in a loop with calls (a "large loop"), see if
883 we can replace the usage of this register with the source
884 of this SET. If we can, delete this insn.
886 Don't do this if P has a REG_RETVAL note or if we have
887 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
899 && (! SMALL_REGISTER_CLASSES
902 /* This test is not redundant; SET_SRC (set) might be
903 a call-clobbered register and the life of REGNO
904 might span a call. */
910 {
911 /* Replace any usage in a REG_EQUAL note. Must copy the
912 new source, so that we don't get rtx sharing between the
913 SET_SOURCE and REG_NOTES of insn p. */
922 }
940 /* Set M->cond if either loop_invariant_p
941 or consec_sets_invariant_p returned 2
942 (only conditionally invariant). */
952 /* Add M to the end of the chain MOVABLES. */
956 {
957 /* It is possible for the first instruction to have a
958 REG_EQUAL note but a non-invariant SET_SRC, so we must
959 remember the status of the first instruction in case
960 the last instruction doesn't have a REG_EQUAL note. */
963 /* Skip this insn, not checking REG_LIBCALL notes. */
965 /* Skip the consecutive insns, if there are any. */
967 /* Back up to the last insn of the consecutive group. */
970 /* We must now reset m->move_insn, m->is_equiv, and possibly
971 m->set_src to correspond to the effects of all the
972 insns. */
976 else
977 {
981 else
984 }
986 }
987 }
988 /* If this register is always set within a STRICT_LOW_PART
989 or set to zero, then its high bytes are constant.
990 So clear them outside the loop and within the loop
991 just load the low bytes.
992 We must check that the machine has an instruction to do so.
993 Also, if the value loaded into the register
994 depends on the same register, this cannot be done. */
1004 {
1007 {
1021 /* If the insn may not be executed on some cycles,
1022 we can't clear the whole reg; clear just high part.
1023 Not even if the reg is used only within this loop.
1024 Consider this:
1025 while (1)
1026 while (s != t) {
1027 if (foo ()) x = *s;
1028 use (x);
1029 }
1030 Clearing x before the inner loop could clobber a value
1031 being saved from the last time around the outer loop.
1032 However, if the reg is not used outside this loop
1033 and all uses of the register are in the same
1034 basic block as the store, there is no problem.
1036 If this insn was made by loop, we don't know its
1037 INSN_LUID and hence must make a conservative
1038 assumption. */
1041 || (labels_in_range_p
1045 else
1054 /* Add M to the end of the chain MOVABLES. */
1056 }
1057 }
1058 }
1059 /* Past a call insn, we get to insns which might not be executed
1060 because the call might exit. This matters for insns that trap.
1061 Constant and pure call insns always return, so they don't count. */
1064 /* Past a label or a jump, we get to insns for which we
1065 can't count on whether or how many times they will be
1066 executed during each iteration. Therefore, we can
1067 only move out sets of trivial variables
1068 (those not used after the loop). */
1069 /* Similar code appears twice in strength_reduce. */
1071 /* If we enter the loop in the middle, and scan around to the
1072 beginning, don't set maybe_never for that. This must be an
1073 unconditional jump, otherwise the code at the top of the
1074 loop might never be executed. Unconditional jumps are
1075 followed by a barrier then the loop_end. */
1081 {
1082 /* At the virtual top of a converted loop, insns are again known to
1083 be executed: logically, the loop begins here even though the exit
1084 code has been duplicated. */
1088 loop_depth++;
1090 loop_depth--;
1091 }
1092 }
1094 /* If one movable subsumes another, ignore that other. */
1098 /* For each movable insn, see if the reg that it loads
1099 leads when it dies right into another conditionally movable insn.
1100 If so, record that the second insn "forces" the first one,
1101 since the second can be moved only if the first is. */
1105 /* See if there are multiple movable insns that load the same value.
1106 If there are, make all but the first point at the first one
1107 through the `match' field, and add the priorities of them
1108 all together as the priority of the first. */
1112 /* Now consider each movable insn to decide whether it is worth moving.
1113 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1115 Generally this increases code size, so do not move moveables when
1116 optimizing for code size. */
1119 {
1122 /* Recalculate regs->array if move_movables has created new
1123 registers. */
1125 {
1131 ;
1136 }
1137 }
1139 /* Now candidates that still are negative are those not moved.
1140 Change regs->array[I].set_in_loop to indicate that those are not actually
1141 invariant. */
1146 /* Now that we've moved some things out of the loop, we might be able to
1147 hoist even more memory references. */
1150 /* Recalculate regs->array if load_mems has created new registers. */
1158 ;
1165 {
1167 /* Ensure our label doesn't go away. */
1178 }
1181 /* The movable information is required for strength reduction. */
1187 }
1188 \f
1189 /* Add elements to *OUTPUT to record all the pseudo-regs
1190 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1192 void
1196 {
1204 {
1222 }
1226 {
1230 {
1239 }
1240 }
1241 }
1242 \f
1243 /* Check what regs are referred to in the libcall block ending with INSN,
1244 aside from those mentioned in the equivalent value.
1245 If there are none, return 0.
1246 If there are one or more, return an EXPR_LIST containing all of them. */
1248 rtx
1251 {
1256 /* First, find all the regs used in the libcall block
1257 that are not mentioned as inputs to the result. */
1260 {
1265 }
1268 }
1269 \f
1270 /* Return 1 if all uses of REG
1271 are between INSN and the end of the basic block. */
1273 static int
1276 {
1278 rtx p;
1283 /* Search this basic block for the already recorded last use of the reg. */
1285 {
1287 {
1293 /* Ordinary insn: if this is the last use, we win. */
1299 /* Jump insn: if this is the last use, we win. */
1302 /* Otherwise, it's the end of the basic block, so we lose. */
1307 /* It's the end of the basic block, so we lose. */
1312 }
1313 }
1315 /* The "last use" that was recorded can't be found after the first
1316 use. This can happen when the last use was deleted while
1317 processing an inner loop, this inner loop was then completely
1318 unrolled, and the outer loop is always exited after the inner loop,
1319 so that everything after the first use becomes a single basic block. */
1321 }
1322 \f
1323 /* Compute the benefit of eliminating the insns in the block whose
1324 last insn is LAST. This may be a group of insns used to compute a
1325 value directly or can contain a library call. */
1327 static int
1329 rtx last;
1330 {
1331 rtx insn;
1336 {
1339 routine. */
1343 benefit++;
1344 }
1347 }
1348 \f
1349 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1351 static rtx
1353 rtx insn;
1355 {
1357 {
1358 rtx temp;
1360 /* If first insn of libcall sequence, skip to end. */
1361 /* Do this at start of loop, since INSN is guaranteed to
1362 be an insn here. */
1367 do
1370 }
1373 }
1375 /* Ignore any movable whose insn falls within a libcall
1376 which is part of another movable.
1377 We make use of the fact that the movable for the libcall value
1378 was made later and so appears later on the chain. */
1380 static void
1383 {
1387 {
1388 /* Is this a movable for the value of a libcall? */
1391 {
1392 rtx insn;
1393 /* Check for earlier movables inside that range,
1394 and mark them invalid. We cannot use LUIDs here because
1395 insns created by loop.c for prior loops don't have LUIDs.
1396 Rather than reject all such insns from movables, we just
1397 explicitly check each insn in the libcall (since invariant
1398 libcalls aren't that common). */
1403 }
1404 }
1405 }
1407 /* For each movable insn, see if the reg that it loads
1408 leads when it dies right into another conditionally movable insn.
1409 If so, record that the second insn "forces" the first one,
1410 since the second can be moved only if the first is. */
1412 static void
1415 {
1419 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1421 {
1424 /* ??? Could this be a bug? What if CSE caused the
1425 register of M1 to be used after this insn?
1426 Since CSE does not update regno_last_uid,
1427 this insn M->insn might not be where it dies.
1428 But very likely this doesn't matter; what matters is
1429 that M's reg is computed from M1's reg. */
1434 /* If m->consec, m->set_src isn't valid. */
1438 /* Increase the priority of the moving the first insn
1439 since it permits the second to be moved as well. */
1441 {
1445 }
1446 }
1447 }
1448 \f
1449 /* Find invariant expressions that are equal and can be combined into
1450 one register. */
1452 static void
1456 {
1461 /* Regs that are set more than once are not allowed to match
1462 or be matched. I'm no longer sure why not. */
1463 /* Only pseudo registers are allowed to match or be matched,
1464 since move_movables does not validate the change. */
1465 /* Perhaps testing m->consec_sets would be more appropriate here? */
1471 {
1478 /* We want later insns to match the first one. Don't make the first
1479 one match any later ones. So start this loop at m->next. */
1484 /* A reg used outside the loop mustn't be eliminated. */
1486 /* A reg used for zero-extending mustn't be eliminated. */
1489 ||
1490 (
1491 /* Can combine regs with different modes loaded from the
1492 same constant only if the modes are the same or
1493 if both are integer modes with M wider or the same
1494 width as M1. The check for integer is redundant, but
1495 safe, since the only case of differing destination
1496 modes with equal sources is when both sources are
1497 VOIDmode, i.e., CONST_INT. */
1503 /* See if the source of M1 says it matches M. */
1510 {
1516 }
1517 }
1519 /* Now combine the regs used for zero-extension.
1520 This can be done for those not marked `global'
1521 provided their lives don't overlap. */
1525 {
1528 /* Combine all the registers for extension from mode MODE.
1529 Don't combine any that are used outside this loop. */
1533 {
1540 {
1541 /* First one: don't check for overlap, just record it. */
1544 }
1546 /* Make sure they extend to the same mode.
1547 (Almost always true.) */
1551 /* We already have one: check for overlap with those
1552 already combined together. */
1559 /* No overlap: we can combine this with the others. */
1565 overlap:
1566 ;
1567 }
1568 }
1570 /* Clean up. */
1572 }
1574 /* Returns the number of movable instructions in LOOP that were not
1575 moved outside the loop. */
1577 static int
1580 {
1589 }
1591 \f
1592 /* Return 1 if regs X and Y will become the same if moved. */
1594 static int
1598 {
1615 }
1617 /* Return 1 if X and Y are identical-looking rtx's.
1618 This is the Lisp function EQUAL for rtx arguments.
1620 If two registers are matching movables or a movable register and an
1621 equivalent constant, consider them equal. */
1623 static int
1628 {
1642 /* If we have a register and a constant, they may sometimes be
1643 equal. */
1646 {
1651 }
1654 {
1659 }
1661 /* Otherwise, rtx's of different codes cannot be equal. */
1665 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1666 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1671 /* These three types of rtx's can be compared nonrecursively. */
1680 /* Compare the elements. If any pair of corresponding elements
1681 fail to match, return 0 for the whole things. */
1685 {
1687 {
1699 /* Two vectors must have the same length. */
1703 /* And the corresponding elements must match. */
1722 /* These are just backpointers, so they don't matter. */
1728 /* It is believed that rtx's at this level will never
1729 contain anything but integers and other rtx's,
1730 except for within LABEL_REFs and SYMBOL_REFs. */
1733 }
1734 }
1736 }
1737 \f
1738 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1739 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1740 references is incremented once for each added note. */
1742 static void
1744 rtx x;
1745 rtx insns;
1746 {
1750 rtx insn;
1753 {
1754 /* This code used to ignore labels that referred to dispatch tables to
1755 avoid flow generating (slighly) worse code.
1757 We no longer ignore such label references (see LABEL_REF handling in
1758 mark_jump_label for additional information). */
1761 {
1766 }
1767 }
1771 {
1777 }
1778 }
1779 \f
1780 /* Scan MOVABLES, and move the insns that deserve to be moved.
1781 If two matching movables are combined, replace one reg with the
1782 other throughout. */
1784 static void
1790 {
1795 rtx p;
1798 /* Map of pseudo-register replacements to handle combining
1799 when we move several insns that load the same value
1800 into different pseudo-registers. */
1805 {
1806 /* Describe this movable insn. */
1809 {
1830 }
1832 /* Ignore the insn if it's already done (it matched something else).
1833 Otherwise, see if it is now safe to move. */
1845 {
1847 rtx p;
1850 /* We have an insn that is safe to move.
1851 Compute its desirability. */
1862 /* An insn MUST be moved if we already moved something else
1863 which is safe only if this one is moved too: that is,
1864 if already_moved[REGNO] is nonzero. */
1866 /* An insn is desirable to move if the new lifetime of the
1867 register is no more than THRESHOLD times the old lifetime.
1868 If it's not desirable, it means the loop is so big
1869 that moving won't speed things up much,
1870 and it is liable to make register usage worse. */
1872 /* It is also desirable to move if it can be moved at no
1873 extra cost because something else was already moved. */
1876 || flag_move_all_movables
1881 {
1886 /* Now move the insns that set the reg. */
1889 {
1892 /* Find the end of this chain of matching regs.
1893 Thus, we load each reg in the chain from that one reg.
1894 And that reg is loaded with 0 directly,
1895 since it has ->match == 0. */
1901 /* Mark the moved, invariant reg as being allowed to
1902 share a hard reg with the other matching invariant. */
1906 regs_may_share
1909 regs_may_share));
1917 }
1918 /* If we are to re-generate the item being moved with a
1919 new move insn, first delete what we have and then emit
1920 the move insn before the loop. */
1922 {
1926 {
1927 /* If this is the first insn of a library call sequence,
1928 skip to the end. */
1933 /* If this is the last insn of a libcall sequence, then
1934 delete every insn in the sequence except the last.
1935 The last insn is handled in the normal manner. */
1938 {
1942 }
1947 /* simplify_giv_expr expects that it can walk the insns
1948 at m->insn forwards and see this old sequence we are
1949 tossing here. delete_insn does preserve the next
1950 pointers, but when we skip over a NOTE we must fix
1951 it up. Otherwise that code walks into the non-deleted
1952 insn stream. */
1955 }
1974 /* The more regs we move, the less we like moving them. */
1976 }
1977 else
1978 {
1980 {
1983 /* If first insn of libcall sequence, skip to end. */
1984 /* Do this at start of loop, since p is guaranteed to
1985 be an insn here. */
1990 /* If last insn of libcall sequence, move all
1991 insns except the last before the loop. The last
1992 insn is handled in the normal manner. */
1995 {
2003 {
2004 rtx body;
2005 rtx n;
2006 rtx next;
2013 /* Find the next insn after TEMP,
2014 not counting USE or NOTE insns. */
2022 /* If that is the call, this may be the insn
2023 that loads the function address.
2025 Extract the function address from the insn
2026 that loads it into a register.
2027 If this insn was cse'd, we get incorrect code.
2029 So emit a new move insn that copies the
2030 function address into the register that the
2031 call insn will use. flow.c will delete any
2032 redundant stores that we have created. */
2037 NULL_RTX)))
2038 {
2044 }
2045 /* We have the call insn.
2046 If it uses the register we suspect it might,
2047 load it with the correct address directly. */
2052 gen_move_insn
2056 {
2058 /* Because the USAGE information potentially
2059 contains objects other than hard registers
2060 we need to copy it. */
2064 }
2065 else
2074 }
2077 }
2079 {
2080 /* P sets REG to zero; but we should clear only
2081 the bits that are not covered by the mode
2082 m->savemode. */
2084 rtx sequence;
2085 rtx tem;
2088 tem = expand_simple_binop
2101 }
2103 {
2105 /* Because the USAGE information potentially
2106 contains objects other than hard registers
2107 we need to copy it. */
2111 }
2113 {
2114 rtx seq;
2115 /* The SET_SRC might not be invariant, so we must
2116 use the REG_EQUAL note. */
2129 }
2130 else
2134 {
2138 /* If there is a REG_EQUAL note present whose value
2139 is not loop invariant, then delete it, since it
2140 may cause problems with later optimization passes.
2141 It is possible for cse to create such notes
2142 like this as a result of record_jump_cond. */
2147 }
2156 /* If library call, now fix the REG_NOTES that contain
2157 insn pointers, namely REG_LIBCALL on FIRST
2158 and REG_RETVAL on I1. */
2160 {
2164 }
2170 /* simplify_giv_expr expects that it can walk the insns
2171 at m->insn forwards and see this old sequence we are
2172 tossing here. delete_insn does preserve the next
2173 pointers, but when we skip over a NOTE we must fix
2174 it up. Otherwise that code walks into the non-deleted
2175 insn stream. */
2178 }
2180 /* The more regs we move, the less we like moving them. */
2182 }
2184 /* Any other movable that loads the same register
2185 MUST be moved. */
2188 /* This reg has been moved out of one loop. */
2191 /* The reg set here is now invariant. */
2193 {
2197 }
2201 /* Change the length-of-life info for the register
2202 to say it lives at least the full length of this loop.
2203 This will help guide optimizations in outer loops. */
2206 /* This is the old insn before all the moved insns.
2207 We can't use the moved insn because it is out of range
2208 in uid_luid. Only the old insns have luids. */
2213 /* Combine with this moved insn any other matching movables. */
2218 {
2219 rtx temp;
2221 /* Schedule the reg loaded by M1
2222 for replacement so that shares the reg of M.
2223 If the modes differ (only possible in restricted
2224 circumstances, make a SUBREG.
2226 Note this assumes that the target dependent files
2227 treat REG and SUBREG equally, including within
2228 GO_IF_LEGITIMATE_ADDRESS and in all the
2229 predicates since we never verify that replacing the
2230 original register with a SUBREG results in a
2231 recognizable insn. */
2234 else
2239 /* Get rid of the matching insn
2240 and prevent further processing of it. */
2243 /* if library call, delete all insns. */
2245 NULL_RTX)))
2247 else
2250 /* Any other movable that loads the same register
2251 MUST be moved. */
2254 /* The reg merged here is now invariant,
2255 if the reg it matches is invariant. */
2257 {
2261 i++)
2263 }
2264 }
2265 }
2268 }
2274 }
2279 /* Go through all the instructions in the loop, making
2280 all the register substitutions scheduled in REG_MAP. */
2284 {
2288 }
2290 /* Clean up. */
2293 }
2296 static void
2300 {
2303 else
2306 }
2309 static void
2312 {
2317 {
2320 }
2321 }
2322 \f
2323 #if 0
2324 /* Scan X and replace the address of any MEM in it with ADDR.
2325 REG is the address that MEM should have before the replacement. */
2327 static void
2330 {
2339 {
2351 /* Short cut for very common case. */
2356 /* Short cut for very common case. */
2361 /* If this MEM uses a reg other than the one we expected,
2362 something is wrong. */
2370 }
2374 {
2378 {
2382 }
2383 }
2384 }
2385 #endif
2386 \f
2387 /* Return the number of memory refs to addresses that vary
2388 in the rtx X. */
2390 static int
2393 rtx x;
2394 {
2405 {
2422 }
2427 {
2431 {
2435 }
2436 }
2438 }
2439 \f
2440 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2441 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2442 `unknown_address_altered', `unknown_constant_address_altered', and
2443 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2444 list `store_mems' in LOOP. */
2446 static void
2449 {
2451 rtx insn;
2455 /* The label after END. Jumping here is just like falling off the
2456 end of the loop. We use next_nonnote_insn instead of next_label
2457 as a hedge against the (pathological) case where some actual insn
2458 might end up between the two. */
2481 {
2483 {
2486 }
2487 }
2491 {
2493 {
2496 {
2498 /* Count number of loops contained in this one. */
2500 }
2507 {
2510 }
2520 {
2524 {
2529 {
2532 }
2533 else
2534 {
2537 }
2539 do
2540 {
2542 {
2544 {
2545 /* Something tricky. */
2548 }
2551 {
2552 /* A jump outside the current loop. */
2555 }
2556 }
2560 }
2562 }
2563 else
2564 {
2565 /* A return, or something tricky. */
2567 }
2568 }
2569 /* FALLTHRU */
2590 }
2591 }
2593 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2595 anywhere. */
2597 /* We don't want loads for MEMs moved to a location before the
2598 one at which their stack memory becomes allocated. (Note
2599 that this is not a problem for malloc, etc., since those
2600 require actual function calls. */
2601 && ! current_function_calls_alloca
2602 /* There are ways to leave the loop other than falling off the
2603 end. */
2609 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2610 that loop_invariant_p and load_mems can use true_dependence
2611 to determine what is really clobbered. */
2613 {
2616 loop_info->store_mems
2618 }
2620 {
2624 loop_info->store_mems
2626 }
2627 }
2628 \f
2629 /* Invalidate all loops containing LABEL. */
2631 static void
2633 rtx label;
2634 {
2638 }
2640 /* Scan the function looking for loops. Record the start and end of each loop.
2641 Also mark as invalid loops any loops that contain a setjmp or are branched
2642 to from outside the loop. */
2644 static void
2646 rtx f;
2648 {
2649 rtx insn;
2650 rtx label;
2660 /* If there are jumps to undefined labels,
2661 treat them as jumps out of any/all loops.
2662 This also avoids writing past end of tables when there are no loops. */
2665 /* Find boundaries of loops, mark which loops are contained within
2666 loops, and invalidate loops that have setjmp. */
2671 {
2674 {
2678 num_loops++;
2702 }
2706 {
2707 /* In this case, we must invalidate our current loop and any
2708 enclosing loop. */
2710 {
2716 }
2717 }
2719 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2720 enclosing loop, but this doesn't matter. */
2722 }
2724 /* Any loop containing a label used in an initializer must be invalidated,
2725 because it can be jumped into from anywhere. */
2729 /* Any loop containing a label used for an exception handler must be
2730 invalidated, because it can be jumped into from anywhere. */
2733 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2734 loop that it is not contained within, that loop is marked invalid.
2735 If any INSN or CALL_INSN uses a label's address, then the loop containing
2736 that label is marked invalid, because it could be jumped into from
2737 anywhere.
2739 Also look for blocks of code ending in an unconditional branch that
2740 exits the loop. If such a block is surrounded by a conditional
2741 branch around the block, move the block elsewhere (see below) and
2742 invert the jump to point to the code block. This may eliminate a
2743 label in our loop and will simplify processing by both us and a
2744 possible second cse pass. */
2748 {
2752 {
2756 }
2763 /* See if this is an unconditional branch outside the loop. */
2771 {
2772 rtx p;
2778 /* Go backwards until we reach the start of the loop, a label,
2779 or a JUMP_INSN. */
2786 ;
2788 /* Check for the case where we have a jump to an inner nested
2789 loop, and do not perform the optimization in that case. */
2792 {
2795 {
2800 }
2801 }
2803 /* Make sure that the target of P is within the current loop. */
2809 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2810 we have a block of code to try to move.
2812 We look backward and then forward from the target of INSN
2813 to find a BARRIER at the same loop depth as the target.
2814 If we find such a BARRIER, we make a new label for the start
2815 of the block, invert the jump in P and point it to that label,
2816 and move the block of code to the spot we found. */
2821 /* Just ignore jumps to labels that were never emitted.
2822 These always indicate compilation errors. */
2826 /* If it's not safe to move the sequence, then we
2827 mustn't try. */
2830 {
2831 rtx target
2835 rtx tmp;
2837 /* Search for possible garbage past the conditional jumps
2838 and look for the last barrier. */
2846 /* Don't move things inside a tablejump. */
2859 /* Don't move things inside a tablejump. */
2870 {
2874 /* Ensure our label doesn't go away. */
2877 /* Verify that uid_loop is large enough and that
2878 we can invert P. */
2880 {
2883 /* If no suitable BARRIER was found, create a suitable
2884 one before TARGET. Since TARGET is a fall through
2885 path, we'll need to insert an jump around our block
2886 and add a BARRIER before TARGET.
2888 This creates an extra unconditional jump outside
2889 the loop. However, the benefits of removing rarely
2890 executed instructions from inside the loop usually
2891 outweighs the cost of the extra unconditional jump
2892 outside the loop. */
2894 {
2895 rtx temp;
2902 }
2904 /* Include the BARRIER after INSN and copy the
2905 block after LOC. */
2910 /* All those insns are now in TARGET_LOOP. */
2916 /* The label jumped to by INSN is no longer a loop
2917 exit. Unless INSN does not have a label (e.g.,
2918 it is a RETURN insn), search loop->exit_labels
2919 to find its label_ref, and remove it. Also turn
2920 off LABEL_OUTSIDE_LOOP_P bit. */
2922 {
2924 r;
2927 {
2931 else
2934 }
2940 /* If we didn't find it, then something is
2941 wrong. */
2944 }
2946 /* P is now a jump outside the loop, so it must be put
2947 in loop->exit_labels, and marked as such.
2948 The easiest way to do this is to just call
2949 mark_loop_jump again for P. */
2952 /* If INSN now jumps to the insn after it,
2953 delete INSN. */
2958 }
2960 /* Continue the loop after where the conditional
2961 branch used to jump, since the only branch insn
2962 in the block (if it still remains) is an inter-loop
2963 branch and hence needs no processing. */
2969 /* This loop will be continued with NEXT_INSN (insn). */
2971 }
2972 }
2973 }
2974 }
2975 }
2977 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
2978 loops it is contained in, mark the target loop invalid.
2980 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
2982 static void
2984 rtx x;
2986 {
2992 {
3004 /* There could be a label reference in here. */
3016 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3028 /* Link together all labels that branch outside the loop. This
3029 is used by final_[bg]iv_value and the loop unrolling code. Also
3030 mark this LABEL_REF so we know that this branch should predict
3031 false. */
3033 /* A check to make sure the label is not in an inner nested loop,
3034 since this does not count as a loop exit. */
3036 {
3041 }
3042 else
3046 {
3055 }
3057 /* If this is inside a loop, but not in the current loop or one enclosed
3058 by it, it invalidates at least one loop. */
3063 /* We must invalidate every nested loop containing the target of this
3064 label, except those that also contain the jump insn. */
3067 {
3068 /* Stop when we reach a loop that also contains the jump insn. */
3073 /* If we get here, we know we need to invalidate a loop. */
3080 }
3084 /* If this is not setting pc, ignore. */
3106 /* Strictly speaking this is not a jump into the loop, only a possible
3107 jump out of the loop. However, we have no way to link the destination
3108 of this jump onto the list of exit labels. To be safe we mark this
3109 loop and any containing loops as invalid. */
3111 {
3113 {
3119 }
3120 }
3122 }
3123 }
3124 \f
3125 /* Return nonzero if there is a label in the range from
3126 insn INSN to and including the insn whose luid is END
3127 INSN must have an assigned luid (i.e., it must not have
3128 been previously created by loop.c). */
3130 static int
3132 rtx insn;
3134 {
3136 {
3140 }
3143 }
3145 /* Record that a memory reference X is being set. */
3147 static void
3149 rtx x;
3150 rtx y ATTRIBUTE_UNUSED;
3152 {
3158 /* Count number of memory writes.
3159 This affects heuristics in strength_reduce. */
3162 /* BLKmode MEM means all memory is clobbered. */
3164 {
3167 else
3171 }
3175 }
3177 /* X is a value modified by an INSN that references a biv inside a loop
3178 exit test (ie, X is somehow related to the value of the biv). If X
3179 is a pseudo that is used more than once, then the biv is (effectively)
3180 used more than once. DATA is a pointer to a loop_regs structure. */
3182 static void
3184 rtx x;
3185 rtx y ATTRIBUTE_UNUSED;
3187 {
3202 /* If we do not have usage information, or if we know the register
3203 is used more than once, note that fact for check_dbra_loop. */
3208 }
3209 \f
3210 /* Return nonzero if the rtx X is invariant over the current loop.
3212 The value is 2 if we refer to something only conditionally invariant.
3214 A memory ref is invariant if it is not volatile and does not conflict
3215 with anything stored in `loop_info->store_mems'. */
3217 int
3220 rtx x;
3221 {
3228 rtx mem_list_entry;
3234 {
3242 /* A LABEL_REF is normally invariant, however, if we are unrolling
3243 loops, and this label is inside the loop, then it isn't invariant.
3244 This is because each unrolled copy of the loop body will have
3245 a copy of this label. If this was invariant, then an insn loading
3246 the address of this label into a register might get moved outside
3247 the loop, and then each loop body would end up using the same label.
3249 We don't know the loop bounds here though, so just fail for all
3250 labels. */
3253 else
3262 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3263 since the reg might be set by initialization within the loop. */
3280 /* Volatile memory references must be rejected. Do this before
3281 checking for read-only items, so that volatile read-only items
3282 will be rejected also. */
3286 /* See if there is any dependence between a store and this load. */
3289 {
3295 }
3297 /* It's not invalidated by a store in memory
3298 but we must still verify the address is invariant. */
3302 /* Don't mess with insns declared volatile. */
3309 }
3313 {
3315 {
3321 }
3323 {
3326 {
3332 }
3334 }
3335 }
3338 }
3339 \f
3340 /* Return nonzero if all the insns in the loop that set REG
3341 are INSN and the immediately following insns,
3342 and if each of those insns sets REG in an invariant way
3343 (not counting uses of REG in them).
3345 The value is 2 if some of these insns are only conditionally invariant.
3347 We assume that INSN itself is the first set of REG
3348 and that its source is invariant. */
3350 static int
3355 {
3359 rtx temp;
3360 /* Number of sets we have to insist on finding after INSN. */
3366 /* If N_SETS hit the limit, we can't rely on its value. */
3373 {
3375 rtx set;
3380 /* If library call, skip to end of it. */
3389 {
3394 {
3395 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3396 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3397 notes are OK. */
3403 }
3404 }
3406 count--;
3408 {
3411 }
3412 }
3415 /* If loop_invariant_p ever returned 2, we return 2. */
3417 }
3419 #if 0
3420 /* I don't think this condition is sufficient to allow INSN
3421 to be moved, so we no longer test it. */
3423 /* Return 1 if all insns in the basic block of INSN and following INSN
3424 that set REG are invariant according to TABLE. */
3426 static int
3430 {
3435 {
3444 {
3447 }
3448 }
3449 }
3451 \f
3452 /* Look at all uses (not sets) of registers in X. For each, if it is
3453 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3454 a different insn, set USAGE[REGNO] to const0_rtx. */
3456 static void
3459 rtx insn;
3460 rtx x;
3461 {
3473 {
3474 /* Don't count SET_DEST if it is a REG; otherwise count things
3475 in SET_DEST because if a register is partially modified, it won't
3476 show up as a potential movable so we don't care how USAGE is set
3477 for it. */
3481 }
3482 else
3484 {
3490 }
3491 }
3492 \f
3493 /* Count and record any set in X which is contained in INSN. Update
3494 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3495 in X. */
3497 static void
3502 {
3504 /* Don't move a reg that has an explicit clobber.
3505 It's not worth the pain to try to do it correctly. */
3509 {
3517 {
3521 {
3522 /* If this is the first setting of this reg
3523 in current basic block, and it was set before,
3524 it must be set in two basic blocks, so it cannot
3525 be moved out of the loop. */
3529 /* If this is not first setting in current basic block,
3530 see if reg was used in between previous one and this.
3531 If so, neither one can be moved. */
3538 }
3539 }
3540 }
3541 }
3542 \f
3543 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3544 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3545 contained in insn INSN is used by any insn that precedes INSN in
3546 cyclic order starting from the loop entry point.
3548 We don't want to use INSN_LUID here because if we restrict INSN to those
3549 that have a valid INSN_LUID, it means we cannot move an invariant out
3550 from an inner loop past two loops. */
3552 static int
3556 {
3558 rtx p;
3560 /* Scan forward checking for register usage. If we hit INSN, we
3561 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3563 {
3569 }
3572 }
3573 \f
3575 /* Information we collect about arrays that we might want to prefetch. */
3576 struct prefetch_info
3577 {
3581 index. */
3582 HOST_WIDE_INT index;
3584 iteration. */
3586 prefetch area in one iteration. */
3588 This is set only for loops with known
3589 iteration counts and is 0xffffffff
3590 otherwise. */
3594 };
3596 /* Data used by check_store function. */
3597 struct check_store_data
3598 {
3599 rtx mem_address;
3601 };
3607 /* Set mem_write when mem_address is found. Used as callback to
3608 note_stores. */
3609 static void
3613 {
3618 }
3619 \f
3620 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3621 important to get some addresses combined. Later more sophisticated
3622 transformations can be added when necesary.
3624 ??? Same trick with swapping operand is done at several other places.
3625 It can be nice to develop some common way to handle this. */
3627 static int
3630 {
3644 {
3649 }
3650 /* Compare the elements. If any pair of corresponding elements fails to
3651 match, return 0 for the whole thing. */
3655 {
3657 {
3669 /* Two vectors must have the same length. */
3673 /* And the corresponding elements must match. */
3691 /* These are just backpointers, so they don't matter. */
3697 /* It is believed that rtx's at this level will never
3698 contain anything but integers and other rtx's,
3699 except for within LABEL_REFs and SYMBOL_REFs. */
3702 }
3703 }
3705 }
3706 \f
3707 /* Remove constant addition value from the expression X (when present)
3708 and return it. */
3710 static HOST_WIDE_INT
3713 {
3717 /* Avoid clobbering a shared CONST expression. */
3719 {
3723 {
3726 }
3728 }
3731 {
3734 }
3736 /* For plus expression recurse on ourself. */
3738 {
3742 /* In case our parameter was constant, remove extra zero from the
3743 expression. */
3748 }
3751 }
3753 /* Attempt to identify accesses to arrays that are most likely to cause cache
3754 misses, and emit prefetch instructions a few prefetch blocks forward.
3756 To detect the arrays we use the GIV information that was collected by the
3757 strength reduction pass.
3759 The prefetch instructions are generated after the GIV information is done
3760 and before the strength reduction process. The new GIVs are injected into
3761 the strength reduction tables, so the prefetch addresses are optimized as
3762 well.
3764 GIVs are split into base address, stride, and constant addition values.
3765 GIVs with the same address, stride and close addition values are combined
3766 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3767 for write instructions can be used for the block we write to, on machines
3768 that support write prefetches.
3770 Several heuristics are used to determine when to prefetch. They are
3771 controlled by defined symbols that can be overridden for each target. */
3773 static void
3776 {
3792 /* Consider only loops w/o calls. When a call is done, the loop is probably
3793 slow enough to read the memory. */
3795 {
3800 }
3802 /* Don't prefetch in loops known to have few iterations. */
3806 {
3811 }
3813 /* Search all induction variables and pick those interesting for the prefetch
3814 machinery. */
3816 {
3822 /* Expect all BIVs to be executed in each iteration. This makes our
3823 analysis more conservative. */
3825 {
3826 /* Discard non-constant additions that we can't handle well yet, and
3827 BIVs that are executed multiple times; such BIVs ought to be
3828 handled in the nested loop. We accept not_every_iteration BIVs,
3829 since these only result in larger strides and make our
3830 heuristics more conservative. */
3832 {
3834 {
3840 }
3842 }
3845 {
3847 {
3853 }
3855 }
3859 }
3865 {
3866 rtx address;
3867 rtx temp;
3876 /* See whether an induction variable is interesting to us and if
3877 not, report the reason. */
3881 /* We are interested only in constant stride memory references
3882 in order to be able to compute density easily. */
3886 else
3887 {
3890 {
3893 }
3895 /* On some targets, reversed order prefetches are not
3896 worthwhile. */
3900 /* Prefetch of accesses with an extreme stride might not be
3901 worthwhile, either. */
3906 /* Ignore GIVs with varying add values; we can't predict the
3907 value for the next iteration. */
3911 /* Ignore GIVs in the nested loops; they ought to have been
3912 handled already. */
3915 }
3918 {
3924 }
3926 /* Determine the pointer to the basic array we are examining. It is
3927 the sum of the BIV's initial value and the GIV's add_val. */
3937 /* When the GIV is not always executed, we might be better off by
3938 not dirtying the cache pages. */
3941 else
3942 {
3947 }
3949 /* Attempt to find another prefetch to the same array and see if we
3950 can merge this one. */
3954 {
3955 /* In case both access same array (same location
3956 just with small difference in constant indexes), merge
3957 the prefetches. Just do the later and the earlier will
3958 get prefetched from previous iteration.
3959 The artificial threshold should not be too small,
3960 but also not bigger than small portion of memory usually
3961 traversed by single loop. */
3964 {
3973 }
3977 {
3982 }
3983 }
3985 /* Merging failed. */
3987 {
3995 num_prefetches++;
3997 {
4002 }
4003 }
4004 }
4005 }
4008 {
4011 /* Attempt to calculate the total number of bytes fetched by all
4012 iterations of the loop. Avoid overflow. */
4017 else
4022 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4027 {
4032 }
4033 else
4034 {
4040 }
4041 else
4044 /* Find how many prefetch instructions we'll use within the loop. */
4046 {
4052 }
4053 }
4055 /* Determine how many iterations ahead to prefetch within the loop, based
4056 on how many prefetches we currently expect to do within the loop. */
4058 {
4060 {
4066 }
4067 }
4068 /* We'll also use AHEAD to determine how many prefetch instructions to
4069 emit before a loop, so don't leave it zero. */
4074 {
4075 /* Update if we've decided not to prefetch anything within the loop. */
4079 /* Find how many prefetch instructions we'll use before the loop. */
4081 {
4089 }
4092 {
4114 }
4115 }
4118 {
4119 /* Record that this loop uses prefetch instructions. */
4123 {
4128 }
4129 }
4132 {
4136 {
4138 rtx insn;
4143 /* We can save some effort by offsetting the address on
4144 architectures with offsettable memory references. */
4147 else
4148 {
4154 }
4156 /* Make sure the address operand is valid for prefetch. */
4162 before_insn);
4164 /* Check all insns emitted and record the new GIV
4165 information. */
4168 {
4173 }
4174 }
4177 {
4178 /* Emit insns before the loop to fetch the first cache lines or,
4179 if we're not prefetching within the loop, everything we expect
4180 to need. */
4182 {
4190 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4191 non-constant INIT_VAL to have the same mode as REG, which
4192 in this case we know to be Pmode. */
4200 loop_start);
4201 }
4202 }
4203 }
4206 }
4207 \f
4208 /* A "basic induction variable" or biv is a pseudo reg that is set
4209 (within this loop) only by incrementing or decrementing it. */
4210 /* A "general induction variable" or giv is a pseudo reg whose
4211 value is a linear function of a biv. */
4213 /* Bivs are recognized by `basic_induction_var';
4214 Givs by `general_induction_var'. */
4216 /* Communication with routines called via `note_stores'. */
4220 /* Dummy register to have non-zero DEST_REG for DEST_ADDR type givs. */
4224 /* ??? Unfinished optimizations, and possible future optimizations,
4225 for the strength reduction code. */
4227 /* ??? The interaction of biv elimination, and recognition of 'constant'
4228 bivs, may cause problems. */
4230 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4231 performance problems.
4233 Perhaps don't eliminate things that can be combined with an addressing
4234 mode. Find all givs that have the same biv, mult_val, and add_val;
4235 then for each giv, check to see if its only use dies in a following
4236 memory address. If so, generate a new memory address and check to see
4237 if it is valid. If it is valid, then store the modified memory address,
4238 otherwise, mark the giv as not done so that it will get its own iv. */
4240 /* ??? Could try to optimize branches when it is known that a biv is always
4241 positive. */
4243 /* ??? When replace a biv in a compare insn, we should replace with closest
4244 giv so that an optimized branch can still be recognized by the combiner,
4245 e.g. the VAX acb insn. */
4247 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4248 was rerun in loop_optimize whenever a register was added or moved.
4249 Also, some of the optimizations could be a little less conservative. */
4250 \f
4251 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4252 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4253 callback.
4255 NOT_EVERY_ITERATION if current insn is not executed at least once for every
4256 loop iteration except for the last one.
4258 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4259 loop iteration.
4260 */
4261 void
4264 loop_insn_callback fncall;
4265 {
4266 /* This is 1 if current insn is not executed at least once for every loop
4267 iteration. */
4272 rtx p;
4274 /* If loop_scan_start points to the loop exit test, we have to be wary of
4275 subversive use of gotos inside expression statements. */
4279 /* Scan through loop to find all possible bivs. */
4284 {
4287 /* Past CODE_LABEL, we get to insns that may be executed multiple
4288 times. The only way we can be sure that they can't is if every
4289 jump insn between here and the end of the loop either
4290 returns, exits the loop, is a jump to a location that is still
4291 behind the label, or is a jump to the loop start. */
4294 {
4300 {
4305 {
4308 else
4312 }
4320 {
4323 }
4324 }
4325 }
4327 /* Past a jump, we get to insns for which we can't count
4328 on whether they will be executed during each iteration. */
4329 /* This code appears twice in strength_reduce. There is also similar
4330 code in scan_loop. */
4332 /* If we enter the loop in the middle, and scan around to the
4333 beginning, don't set not_every_iteration for that.
4334 This can be any kind of jump, since we want to know if insns
4335 will be executed if the loop is executed. */
4340 {
4343 /* If this is a jump outside the loop, then it also doesn't
4344 matter. Check to see if the target of this branch is on the
4345 loop->exits_labels list. */
4353 }
4356 {
4357 /* At the virtual top of a converted loop, insns are again known to
4358 be executed each iteration: logically, the loop begins here
4359 even though the exit code has been duplicated.
4361 Insns are also again known to be executed each iteration at
4362 the LOOP_CONT note. */
4368 loop_depth++;
4370 loop_depth--;
4371 }
4373 /* Note if we pass a loop latch. If we do, then we can not clear
4374 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4375 a loop since a jump before the last CODE_LABEL may have started
4376 a new loop iteration.
4378 Note that LOOP_TOP is only set for rotated loops and we need
4379 this check for all loops, so compare against the CODE_LABEL
4380 which immediately follows LOOP_START. */
4385 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4386 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4387 or not an insn is known to be executed each iteration of the
4388 loop, whether or not any iterations are known to occur.
4390 Therefore, if we have just passed a label and have no more labels
4391 between here and the test insn of the loop, and we have not passed
4392 a jump to the top of the loop, then we know these insns will be
4393 executed each iteration. */
4396 && !past_loop_latch
4401 }
4402 }
4403 \f
4404 static void
4407 {
4410 /* Temporary list pointers for traversing ivs->list. */
4417 /* Scan ivs->list to remove all regs that proved not to be bivs.
4418 Make a sanity check against regs->n_times_set. */
4420 {
4422 /* Above happens if register modified by subreg, etc. */
4423 /* Make sure it is not recognized as a basic induction var: */
4425 /* If never incremented, it is invariant that we decided not to
4426 move. So leave it alone. */
4428 {
4439 }
4440 else
4441 {
4446 }
4447 }
4448 }
4451 /* Determine how BIVS are initialised by looking through pre-header
4452 extended basic block. */
4453 static void
4456 {
4458 /* Temporary list pointers for traversing ivs->list. */
4461 rtx p;
4463 /* Find initial value for each biv by searching backwards from loop_start,
4464 halting at first label. Also record any test condition. */
4468 {
4469 rtx test;
4479 /* Record any test of a biv that branches around the loop if no store
4480 between it and the start of loop. We only care about tests with
4481 constants and registers and only certain of those. */
4491 {
4492 /* If an NE test, we have an initial value! */
4494 {
4498 }
4499 else
4501 }
4502 }
4503 }
4506 /* Look at the each biv and see if we can say anything better about its
4507 initial value from any initializing insns set up above. (This is done
4508 in two passes to avoid missing SETs in a PARALLEL.) */
4509 static void
4512 {
4514 /* Temporary list pointers for traversing ivs->list. */
4519 {
4520 rtx src;
4521 rtx note;
4526 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4527 is a constant, use the value of that. */
4533 else
4546 {
4550 {
4553 }
4554 }
4555 /* If we can't make it a giv,
4556 let biv keep initial value of "itself". */
4559 }
4560 }
4563 /* Search the loop for general induction variables. */
4565 static void
4568 {
4570 }
4573 /* For each giv for which we still don't know whether or not it is
4574 replaceable, check to see if it is replaceable because its final value
4575 can be calculated. */
4577 static void
4580 {
4585 {
4591 }
4592 }
4595 /* Return non-zero if it is possible to eliminate the biv BL provided
4596 all givs are reduced. This is possible if either the reg is not
4597 used outside the loop, or we can compute what its final value will
4598 be. */
4600 static int
4606 {
4607 /* For architectures with a decrement_and_branch_until_zero insn,
4608 don't do this if we put a REG_NONNEG note on the endtest for this
4609 biv. */
4611 #ifdef HAVE_decrement_and_branch_until_zero
4613 {
4618 }
4619 #endif
4621 /* Check that biv is used outside loop or if it has a final value.
4622 Compare against bl->init_insn rather than loop->start. We aren't
4623 concerned with any uses of the biv between init_insn and
4624 loop->start since these won't be affected by the value of the biv
4625 elsewhere in the function, so long as init_insn doesn't use the
4626 biv itself. */
4637 {
4645 }
4647 }
4650 /* Reduce each giv of BL that we have decided to reduce. */
4652 static void
4656 {
4660 {
4663 {
4666 /* If the code for derived givs immediately below has already
4667 allocated a new_reg, we must keep it. */
4671 #ifdef AUTO_INC_DEC
4672 /* If the target has auto-increment addressing modes, and
4673 this is an address giv, then try to put the increment
4674 immediately after its use, so that flow can create an
4675 auto-increment addressing mode. */
4678 /* We don't handle reversed biv's because bl->biv->insn
4679 does not have a valid INSN_LUID. */
4683 {
4684 /* If other giv's have been combined with this one, then
4685 this will work only if all uses of the other giv's occur
4686 before this giv's insn. This is difficult to check.
4688 We simplify this by looking for the common case where
4689 there is one DEST_REG giv, and this giv's insn is the
4690 last use of the dest_reg of that DEST_REG giv. If the
4691 increment occurs after the address giv, then we can
4692 perform the optimization. (Otherwise, the increment
4693 would have to go before other_giv, and we would not be
4694 able to combine it with the address giv to get an
4695 auto-inc address.) */
4697 {
4702 {
4705 else
4707 }
4714 }
4715 /* Check for case where increment is before the address
4716 giv. Do this test in "loop order". */
4725 else
4728 #ifdef HAVE_cc0
4729 {
4730 rtx prev;
4732 /* We can't put an insn immediately after one setting
4733 cc0, or immediately before one using cc0. */
4740 }
4741 #endif
4745 }
4746 #endif
4748 /* For each place where the biv is incremented, add an insn
4749 to increment the new, reduced reg for the giv. */
4751 {
4752 rtx insert_before;
4758 else
4766 /* A multiply is acceptable here
4767 since this is presumed to be seldom executed. */
4771 }
4773 /* Add code at loop start to initialize giv's reduced reg. */
4778 }
4779 }
4780 }
4783 /* Check for givs whose first use is their definition and whose
4784 last use is the definition of another giv. If so, it is likely
4785 dead and should not be used to derive another giv nor to
4786 eliminate a biv. */
4788 static void
4792 {
4796 {
4803 {
4809 }
4810 }
4811 }
4814 static void
4819 {
4823 {
4830 /* Update expression if this was combined, in case other giv was
4831 replaced. */
4836 /* See if this register is known to be a pointer to something. If
4837 so, see if we can find the alignment. First see if there is a
4838 destination register that is a pointer. If so, this shares the
4839 alignment too. Next see if we can deduce anything from the
4840 computational information. If not, and this is a DEST_ADDR
4841 giv, at least we know that it's a pointer, though we don't know
4842 the alignment. */
4850 {
4859 }
4863 {
4871 }
4876 /* Store reduced reg as the address in the memref where we found
4877 this giv. */
4880 {
4882 }
4883 else
4884 {
4885 /* Not replaceable; emit an insn to set the original giv reg from
4886 the reduced giv, same as above. */
4889 }
4891 /* When a loop is reversed, givs which depend on the reversed
4892 biv, and which are live outside the loop, must be set to their
4893 correct final value. This insn is only needed if the giv is
4894 not replaceable. The correct final value is the same as the
4895 value that the giv starts the reversed loop with. */
4906 {
4911 }
4912 }
4913 }
4916 static int
4921 rtx test_reg;
4922 {
4931 /* Reduce benefit if not replaceable, since we will insert a
4932 move-insn to replace the insn that calculates this giv. Don't do
4933 this unless the giv is a user variable, since it will often be
4934 marked non-replaceable because of the duplication of the exit
4935 code outside the loop. In such a case, the copies we insert are
4936 dead and will be deleted. So they don't have a cost. Similar
4937 situations exist. */
4938 /* ??? The new final_[bg]iv_value code does a much better job of
4939 finding replaceable giv's, and hence this code may no longer be
4940 necessary. */
4945 /* Decrease the benefit to count the add-insns that we will insert
4946 to increment the reduced reg for the giv. ??? This can
4947 overestimate the run-time cost of the additional insns, e.g. if
4948 there are multiple basic blocks that increment the biv, but only
4949 one of these blocks is executed during each iteration. There is
4950 no good way to detect cases like this with the current structure
4951 of the loop optimizer. This code is more accurate for
4952 determining code size than run-time benefits. */
4955 /* Decide whether to strength-reduce this giv or to leave the code
4956 unchanged (recompute it from the biv each time it is used). This
4957 decision can be made independently for each giv. */
4959 #ifdef AUTO_INC_DEC
4960 /* Attempt to guess whether autoincrement will handle some of the
4961 new add insns; if so, increase BENEFIT (undo the subtraction of
4962 add_cost that was done above). */
4964 /* Increasing the benefit is risky, since this is only a guess.
4965 Avoid increasing register pressure in cases where there would
4966 be no other benefit from reducing this giv. */
4969 {
4984 }
4985 #endif
4988 }
4991 /* Free IV structures for LOOP. */
4993 static void
4996 {
5003 {
5009 {
5012 }
5014 {
5017 }
5021 }
5022 }
5025 /* Perform strength reduction and induction variable elimination.
5027 Pseudo registers created during this function will be beyond the
5028 last valid index in several tables including
5029 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5030 problem here, because the added registers cannot be givs outside of
5031 their loop, and hence will never be reconsidered. But scan_loop
5032 must check regnos to make sure they are in bounds. */
5034 static void
5038 {
5042 rtx p;
5043 /* Temporary list pointer for traversing ivs->list. */
5045 /* Ratio of extra register life span we can justify
5046 for saving an instruction. More if loop doesn't call subroutines
5047 since in that case saving an insn makes more difference
5048 and more registers are available. */
5049 /* ??? could set this to last value of threshold in move_movables */
5051 /* Map of pseudo-register replacements. */
5063 /* Find all BIVs in loop. */
5066 /* Exit if there are no bivs. */
5068 {
5069 /* Can still unroll the loop anyways, but indicate that there is no
5070 strength reduction info available. */
5076 }
5078 /* Determine how BIVS are initialised by looking through pre-header
5079 extended basic block. */
5082 /* Look at the each biv and see if we can say anything better about its
5083 initial value from any initializing insns set up above. */
5086 /* Search the loop for general induction variables. */
5089 /* Try to calculate and save the number of loop iterations. This is
5090 set to zero if the actual number can not be calculated. This must
5091 be called after all giv's have been identified, since otherwise it may
5092 fail if the iteration variable is a giv. */
5095 #ifdef HAVE_prefetch
5098 #endif
5100 /* Now for each giv for which we still don't know whether or not it is
5101 replaceable, check to see if it is replaceable because its final value
5102 can be calculated. This must be done after loop_iterations is called,
5103 so that final_giv_value will work correctly. */
5106 /* Try to prove that the loop counter variable (if any) is always
5107 nonnegative; if so, record that fact with a REG_NONNEG note
5108 so that "decrement and branch until zero" insn can be used. */
5111 /* Create reg_map to hold substitutions for replaceable giv regs.
5112 Some givs might have been made from biv increments, so look at
5113 ivs->reg_iv_type for a suitable size. */
5117 /* Examine each iv class for feasibility of strength reduction/induction
5118 variable elimination. */
5121 {
5125 /* Test whether it will be possible to eliminate this biv
5126 provided all givs are reduced. */
5129 /* This will be true at the end, if all givs which depend on this
5130 biv have been strength reduced.
5131 We can't (currently) eliminate the biv unless this is so. */
5134 /* Check each extension dependent giv in this class to see if its
5135 root biv is safe from wrapping in the interior mode. */
5138 /* Combine all giv's for this iv_class. */
5142 {
5150 /* If an insn is not to be strength reduced, then set its ignore
5151 flag, and clear bl->all_reduced. */
5153 /* A giv that depends on a reversed biv must be reduced if it is
5154 used after the loop exit, otherwise, it would have the wrong
5155 value after the loop exit. To make it simple, just reduce all
5156 of such giv's whether or not we know they are used after the loop
5157 exit. */
5162 {
5170 }
5171 else
5172 {
5173 /* Check that we can increment the reduced giv without a
5174 multiply insn. If not, reject it. */
5179 {
5187 }
5188 }
5189 }
5191 /* Check for givs whose first use is their definition and whose
5192 last use is the definition of another giv. If so, it is likely
5193 dead and should not be used to derive another giv nor to
5194 eliminate a biv. */
5197 /* Reduce each giv that we decided to reduce. */
5200 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5201 as not reduced.
5203 For each giv register that can be reduced now: if replaceable,
5204 substitute reduced reg wherever the old giv occurs;
5205 else add new move insn "giv_reg = reduced_reg". */
5208 /* All the givs based on the biv bl have been reduced if they
5209 merit it. */
5211 /* For each giv not marked as maybe dead that has been combined with a
5212 second giv, clear any "maybe dead" mark on that second giv.
5213 v->new_reg will either be or refer to the register of the giv it
5214 combined with.
5216 Doing this clearing avoids problems in biv elimination where
5217 a giv's new_reg is a complex value that can't be put in the
5218 insn but the giv combined with (with a reg as new_reg) is
5219 marked maybe_dead. Since the register will be used in either
5220 case, we'd prefer it be used from the simpler giv. */
5226 /* Try to eliminate the biv, if it is a candidate.
5227 This won't work if ! bl->all_reduced,
5228 since the givs we planned to use might not have been reduced.
5230 We have to be careful that we didn't initially think we could
5231 eliminate this biv because of a giv that we now think may be
5232 dead and shouldn't be used as a biv replacement.
5234 Also, there is the possibility that we may have a giv that looks
5235 like it can be used to eliminate a biv, but the resulting insn
5236 isn't valid. This can happen, for example, on the 88k, where a
5237 JUMP_INSN can compare a register only with zero. Attempts to
5238 replace it with a compare with a constant will fail.
5240 Note that in cases where this call fails, we may have replaced some
5241 of the occurrences of the biv with a giv, but no harm was done in
5242 doing so in the rare cases where it can occur. */
5246 {
5247 /* ?? If we created a new test to bypass the loop entirely,
5248 or otherwise drop straight in, based on this test, then
5249 we might want to rewrite it also. This way some later
5250 pass has more hope of removing the initialization of this
5251 biv entirely. */
5253 /* If final_value != 0, then the biv may be used after loop end
5254 and we must emit an insn to set it just in case.
5256 Reversed bivs already have an insn after the loop setting their
5257 value, so we don't need another one. We can't calculate the
5258 proper final value for such a biv here anyways. */
5267 }
5268 /* See above note wrt final_value. But since we couldn't eliminate
5269 the biv, we must set the value after the loop instead of before. */
5273 }
5275 /* Go through all the instructions in the loop, making all the
5276 register substitutions scheduled in REG_MAP. */
5281 {
5285 }
5288 {
5289 /* When we completely unroll a loop we will likely not need the increment
5290 of the loop BIV and we will not need the conditional branch at the
5291 end of the loop. */
5294 #ifdef HAVE_cc0
5295 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5296 need the comparison before the conditional branch at the end of the
5297 loop. */
5299 #endif
5301 /* We'll need one copy for each loop iteration. */
5304 /* A little slop to account for the ability to remove initialization
5305 code, better CSE, and other secondary benefits of completely
5306 unrolling some loops. */
5309 /* Clamp the value. */
5312 }
5314 /* Unroll loops from within strength reduction so that we can use the
5315 induction variable information that strength_reduce has already
5316 collected. Always unroll loops that would be as small or smaller
5317 unrolled than when rolled. */
5324 #ifdef HAVE_doloop_end
5329 /* In case number of iterations is known, drop branch prediction note
5330 in the branch. Do that only in second loop pass, as loop unrolling
5331 may change the number of iterations performed. */
5333 {
5334 unsigned HOST_WIDE_INT n
5339 }
5347 }
5348 \f
5349 /*Record all basic induction variables calculated in the insn. */
5350 static rtx
5353 rtx p;
5356 {
5358 rtx set;
5359 rtx dest_reg;
5360 rtx inc_val;
5361 rtx mult_val;
5367 {
5372 {
5377 {
5378 /* It is a possible basic induction variable.
5379 Create and initialize an induction structure for it. */
5387 }
5390 }
5391 }
5393 }
5394 \f
5395 /* Record all givs calculated in the insn.
5396 A register is a giv if: it is only set once, it is a function of a
5397 biv and a constant (or invariant), and it is not a biv. */
5398 static rtx
5401 rtx p;
5404 {
5407 rtx set;
5408 /* Look for a general induction variable in a register. */
5413 {
5414 rtx src_reg;
5415 rtx dest_reg;
5416 rtx add_val;
5417 rtx mult_val;
5418 rtx ext_val;
5421 rtx last_consec_insn;
5430 /* Equivalent expression is a giv. */
5435 /* Don't try to handle any regs made by loop optimization.
5436 We have nothing on them in regno_first_uid, etc. */
5438 /* Don't recognize a BASIC_INDUCT_VAR here. */
5440 /* This must be the only place where the register is set. */
5442 /* or all sets must be consecutive and make a giv. */
5447 {
5451 /* If this is a library call, increase benefit. */
5455 /* Skip the consecutive insns, if there are any. */
5463 }
5464 }
5466 #ifndef DONT_REDUCE_ADDR
5467 /* Look for givs which are memory addresses. */
5468 /* This resulted in worse code on a VAX 8600. I wonder if it
5469 still does. */
5472 maybe_multiple);
5473 #endif
5475 /* Update the status of whether giv can derive other givs. This can
5476 change when we pass a label or an insn that updates a biv. */
5481 }
5482 \f
5483 /* Return 1 if X is a valid source for an initial value (or as value being
5484 compared against in an initial test).
5486 X must be either a register or constant and must not be clobbered between
5487 the current insn and the start of the loop.
5489 INSN is the insn containing X. */
5491 static int
5493 rtx x;
5494 rtx insn;
5496 rtx loop_start;
5497 {
5501 /* Only consider pseudos we know about initialized in insns whose luids
5502 we know. */
5507 /* Don't use call-clobbered registers across a call which clobbers it. On
5508 some machines, don't use any hard registers at all. */
5510 && (SMALL_REGISTER_CLASSES
5514 /* Don't use registers that have been clobbered before the start of the
5515 loop. */
5520 }
5521 \f
5522 /* Scan X for memory refs and check each memory address
5523 as a possible giv. INSN is the insn whose pattern X comes from.
5524 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5525 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5526 more thanonce in each loop iteration. */
5528 static void
5531 rtx x;
5532 rtx insn;
5534 {
5544 {
5560 {
5561 rtx src_reg;
5562 rtx add_val;
5563 rtx mult_val;
5564 rtx ext_val;
5567 /* This code used to disable creating GIVs with mult_val == 1 and
5568 add_val == 0. However, this leads to lost optimizations when
5569 it comes time to combine a set of related DEST_ADDR GIVs, since
5570 this one would not be seen. */
5575 {
5576 /* Found one; record it. */
5585 }
5586 }
5591 }
5593 /* Recursively scan the subexpressions for other mem refs. */
5599 maybe_multiple);
5603 maybe_multiple);
5604 }
5605 \f
5606 /* Fill in the data about one biv update.
5607 V is the `struct induction' in which we record the biv. (It is
5608 allocated by the caller, with alloca.)
5609 INSN is the insn that sets it.
5610 DEST_REG is the biv's reg.
5612 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5613 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5614 being set to INC_VAL.
5616 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5617 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5618 can be executed more than once per iteration. If MAYBE_MULTIPLE
5619 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5620 executed exactly once per iteration. */
5622 static void
5627 rtx insn;
5628 rtx dest_reg;
5629 rtx inc_val;
5630 rtx mult_val;
5634 {
5650 /* Add this to the reg's iv_class, creating a class
5651 if this is the first incrementation of the reg. */
5655 {
5656 /* Create and initialize new iv_class. */
5666 /* Set initial value to the reg itself. */
5669 /* We haven't seen the initializing insn yet */
5679 /* Add this class to ivs->list. */
5683 /* Put it in the array of biv register classes. */
5685 }
5687 /* Update IV_CLASS entry for this biv. */
5696 }
5697 \f
5698 /* Fill in the data about one giv.
5699 V is the `struct induction' in which we record the giv. (It is
5700 allocated by the caller, with alloca.)
5701 INSN is the insn that sets it.
5702 BENEFIT estimates the savings from deleting this insn.
5703 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5704 into a register or is used as a memory address.
5706 SRC_REG is the biv reg which the giv is computed from.
5707 DEST_REG is the giv's reg (if the giv is stored in a reg).
5708 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5709 LOCATION points to the place where this giv's value appears in INSN. */
5711 static void
5716 rtx insn;
5717 rtx src_reg;
5718 rtx dest_reg;
5724 {
5729 rtx temp;
5731 /* Attempt to prove constantness of the values. Don't let simplity_rtx
5732 undo the MULT canonicalization that we performed earlier. */
5762 /* The v->always_computable field is used in update_giv_derive, to
5763 determine whether a giv can be used to derive another giv. For a
5764 DEST_REG giv, INSN computes a new value for the giv, so its value
5765 isn't computable if INSN insn't executed every iteration.
5766 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5767 it does not compute a new value. Hence the value is always computable
5768 regardless of whether INSN is executed each iteration. */
5772 else
5778 {
5781 }
5783 {
5788 /* If the lifetime is zero, it means that this register is
5789 really a dead store. So mark this as a giv that can be
5790 ignored. This will not prevent the biv from being eliminated. */
5796 }
5798 /* Add the giv to the class of givs computed from one biv. */
5802 {
5805 /* Don't count DEST_ADDR. This is supposed to count the number of
5806 insns that calculate givs. */
5810 }
5811 else
5812 /* Fatal error, biv missing for this giv? */
5817 else
5818 {
5819 /* The giv can be replaced outright by the reduced register only if all
5820 of the following conditions are true:
5821 - the insn that sets the giv is always executed on any iteration
5822 on which the giv is used at all
5823 (there are two ways to deduce this:
5824 either the insn is executed on every iteration,
5825 or all uses follow that insn in the same basic block),
5826 - the giv is not used outside the loop
5827 - no assignments to the biv occur during the giv's lifetime. */
5830 /* Previous line always fails if INSN was moved by loop opt. */
5833 && (! not_every_iteration
5835 {
5836 /* Now check that there are no assignments to the biv within the
5837 giv's lifetime. This requires two separate checks. */
5839 /* Check each biv update, and fail if any are between the first
5840 and last use of the giv.
5842 If this loop contains an inner loop that was unrolled, then
5843 the insn modifying the biv may have been emitted by the loop
5844 unrolling code, and hence does not have a valid luid. Just
5845 mark the biv as not replaceable in this case. It is not very
5846 useful as a biv, because it is used in two different loops.
5847 It is very unlikely that we would be able to optimize the giv
5848 using this biv anyways. */
5852 {
5858 {
5862 }
5863 }
5865 /* If there are any backwards branches that go from after the
5866 biv update to before it, then this giv is not replaceable. */
5870 {
5874 }
5875 }
5876 else
5877 {
5878 /* May still be replaceable, we don't have enough info here to
5879 decide. */
5882 }
5883 }
5885 /* Record whether the add_val contains a const_int, for later use by
5886 combine_givs. */
5887 {
5892 ;
5896 {
5898 {
5903 else
5905 }
5908 }
5909 }
5913 }
5915 /* All this does is determine whether a giv can be made replaceable because
5916 its final value can be calculated. This code can not be part of record_giv
5917 above, because final_giv_value requires that the number of loop iterations
5918 be known, and that can not be accurately calculated until after all givs
5919 have been identified. */
5921 static void
5925 {
5932 /* DEST_ADDR givs will never reach here, because they are always marked
5933 replaceable above in record_giv. */
5935 /* The giv can be replaced outright by the reduced register only if all
5936 of the following conditions are true:
5937 - the insn that sets the giv is always executed on any iteration
5938 on which the giv is used at all
5939 (there are two ways to deduce this:
5940 either the insn is executed on every iteration,
5941 or all uses follow that insn in the same basic block),
5942 - its final value can be calculated (this condition is different
5943 than the one above in record_giv)
5944 - it's not used before the it's set
5945 - no assignments to the biv occur during the giv's lifetime. */
5947 #if 0
5948 /* This is only called now when replaceable is known to be false. */
5949 /* Clear replaceable, so that it won't confuse final_giv_value. */
5951 #endif
5955 {
5958 rtx last_giv_use;
5962 /* When trying to determine whether or not a biv increment occurs
5963 during the lifetime of the giv, we can ignore uses of the variable
5964 outside the loop because final_value is true. Hence we can not
5965 use regno_last_uid and regno_first_uid as above in record_giv. */
5967 /* Search the loop to determine whether any assignments to the
5968 biv occur during the giv's lifetime. Start with the insn
5969 that sets the giv, and search around the loop until we come
5970 back to that insn again.
5972 Also fail if there is a jump within the giv's lifetime that jumps
5973 to somewhere outside the lifetime but still within the loop. This
5974 catches spaghetti code where the execution order is not linear, and
5975 hence the above test fails. Here we assume that the giv lifetime
5976 does not extend from one iteration of the loop to the next, so as
5977 to make the test easier. Since the lifetime isn't known yet,
5978 this requires two loops. See also record_giv above. */
5983 {
5986 {
5989 }
5995 {
5996 /* It is possible for the BIV increment to use the GIV if we
5997 have a cycle. Thus we must be sure to check each insn for
5998 both BIV and GIV uses, and we must check for BIV uses
5999 first. */
6006 {
6008 {
6012 }
6014 }
6015 }
6016 }
6018 /* Now that the lifetime of the giv is known, check for branches
6019 from within the lifetime to outside the lifetime if it is still
6020 replaceable. */
6023 {
6026 {
6039 {
6048 }
6049 }
6050 }
6052 /* If it is replaceable, then save the final value. */
6055 }
6060 }
6061 \f
6062 /* Update the status of whether a giv can derive other givs.
6064 We need to do something special if there is or may be an update to the biv
6065 between the time the giv is defined and the time it is used to derive
6066 another giv.
6068 In addition, a giv that is only conditionally set is not allowed to
6069 derive another giv once a label has been passed.
6071 The cases we look at are when a label or an update to a biv is passed. */
6073 static void
6076 rtx p;
6077 {
6081 rtx tem;
6084 /* Search all IV classes, then all bivs, and finally all givs.
6086 There are three cases we are concerned with. First we have the situation
6087 of a giv that is only updated conditionally. In that case, it may not
6088 derive any givs after a label is passed.
6090 The second case is when a biv update occurs, or may occur, after the
6091 definition of a giv. For certain biv updates (see below) that are
6092 known to occur between the giv definition and use, we can adjust the
6093 giv definition. For others, or when the biv update is conditional,
6094 we must prevent the giv from deriving any other givs. There are two
6095 sub-cases within this case.
6097 If this is a label, we are concerned with any biv update that is done
6098 conditionally, since it may be done after the giv is defined followed by
6099 a branch here (actually, we need to pass both a jump and a label, but
6100 this extra tracking doesn't seem worth it).
6102 If this is a jump, we are concerned about any biv update that may be
6103 executed multiple times. We are actually only concerned about
6104 backward jumps, but it is probably not worth performing the test
6105 on the jump again here.
6107 If this is a biv update, we must adjust the giv status to show that a
6108 subsequent biv update was performed. If this adjustment cannot be done,
6109 the giv cannot derive further givs. */
6115 {
6117 {
6118 /* If cant_derive is already true, there is no point in
6119 checking all of these conditions again. */
6123 /* If this giv is conditionally set and we have passed a label,
6124 it cannot derive anything. */
6128 /* Skip givs that have mult_val == 0, since
6129 they are really invariants. Also skip those that are
6130 replaceable, since we know their lifetime doesn't contain
6131 any biv update. */
6135 /* The only way we can allow this giv to derive another
6136 is if this is a biv increment and we can form the product
6137 of biv->add_val and giv->mult_val. In this case, we will
6138 be able to compute a compensation. */
6140 {
6141 rtx ext_val_dummy;
6152 tem = simplify_giv_expr
6159 else
6161 }
6165 }
6166 }
6167 }
6168 \f
6169 /* Check whether an insn is an increment legitimate for a basic induction var.
6170 X is the source of insn P, or a part of it.
6171 MODE is the mode in which X should be interpreted.
6173 DEST_REG is the putative biv, also the destination of the insn.
6174 We accept patterns of these forms:
6175 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6176 REG = INVARIANT + REG
6178 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6179 store the additive term into *INC_VAL, and store the place where
6180 we found the additive term into *LOCATION.
6182 If X is an assignment of an invariant into DEST_REG, we set
6183 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6185 We also want to detect a BIV when it corresponds to a variable
6186 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6187 of the variable may be a PLUS that adds a SUBREG of that variable to
6188 an invariant and then sign- or zero-extends the result of the PLUS
6189 into the variable.
6191 Most GIVs in such cases will be in the promoted mode, since that is the
6192 probably the natural computation mode (and almost certainly the mode
6193 used for addresses) on the machine. So we view the pseudo-reg containing
6194 the variable as the BIV, as if it were simply incremented.
6196 Note that treating the entire pseudo as a BIV will result in making
6197 simple increments to any GIVs based on it. However, if the variable
6198 overflows in its declared mode but not its promoted mode, the result will
6199 be incorrect. This is acceptable if the variable is signed, since
6200 overflows in such cases are undefined, but not if it is unsigned, since
6201 those overflows are defined. So we only check for SIGN_EXTEND and
6202 not ZERO_EXTEND.
6204 If we cannot find a biv, we return 0. */
6206 static int
6209 rtx x;
6211 rtx dest_reg;
6212 rtx p;
6216 {
6224 {
6230 {
6232 }
6237 {
6239 }
6240 else
6253 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6254 handle addition of promoted variables.
6255 ??? The comment at the start of this function is wrong: promoted
6256 variable increments don't look like it says they do. */
6262 /* If this register is assigned in a previous insn, look at its
6263 source, but don't go outside the loop or past a label. */
6265 /* If this sets a register to itself, we would repeat any previous
6266 biv increment if we applied this strategy blindly. */
6272 {
6273 rtx dest;
6274 do
6275 {
6277 }
6306 }
6307 /* Fall through. */
6309 /* Can accept constant setting of biv only when inside inner most loop.
6310 Otherwise, a biv of an inner loop may be incorrectly recognized
6311 as a biv of the outer loop,
6312 causing code to be moved INTO the inner loop. */
6319 /* convert_modes aborts if we try to convert to or from CCmode, so just
6320 exclude that case. It is very unlikely that a condition code value
6321 would be a useful iterator anyways. convert_modes aborts if we try to
6322 convert a float mode to non-float or vice versa too. */
6326 {
6327 /* Possible bug here? Perhaps we don't know the mode of X. */
6331 }
6332 else
6340 /* Similar, since this can be a sign extension. */
6345 ;
6359 location);
6364 }
6365 }
6366 \f
6367 /* A general induction variable (giv) is any quantity that is a linear
6368 function of a basic induction variable,
6369 i.e. giv = biv * mult_val + add_val.
6370 The coefficients can be any loop invariant quantity.
6371 A giv need not be computed directly from the biv;
6372 it can be computed by way of other givs. */
6374 /* Determine whether X computes a giv.
6375 If it does, return a nonzero value
6376 which is the benefit from eliminating the computation of X;
6377 set *SRC_REG to the register of the biv that it is computed from;
6378 set *ADD_VAL and *MULT_VAL to the coefficients,
6379 such that the value of X is biv * mult + add; */
6381 static int
6385 rtx x;
6393 {
6397 /* If this is an invariant, forget it, it isn't a giv. */
6408 {
6411 /* Since this is now an invariant and wasn't before, it must be a giv
6412 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6413 with. */
6420 /* This is equivalent to a BIV. */
6427 /* Either (plus (biv) (invar)) or
6428 (plus (mult (biv) (invar_1)) (invar_2)). */
6430 {
6433 }
6434 else
6435 {
6438 }
6443 /* ADD_VAL is zero. */
6451 }
6453 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6454 unless they are CONST_INT). */
6462 else
6465 /* Always return true if this is a giv so it will be detected as such,
6466 even if the benefit is zero or negative. This allows elimination
6467 of bivs that might otherwise not be eliminated. */
6469 }
6470 \f
6471 /* Given an expression, X, try to form it as a linear function of a biv.
6472 We will canonicalize it to be of the form
6473 (plus (mult (BIV) (invar_1))
6474 (invar_2))
6475 with possible degeneracies.
6477 The invariant expressions must each be of a form that can be used as a
6478 machine operand. We surround then with a USE rtx (a hack, but localized
6479 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6480 routine; it is the caller's responsibility to strip them.
6482 If no such canonicalization is possible (i.e., two biv's are used or an
6483 expression that is neither invariant nor a biv or giv), this routine
6484 returns 0.
6486 For a non-zero return, the result will have a code of CONST_INT, USE,
6487 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6489 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6494 static rtx
6497 rtx x;
6500 {
6505 rtx tem;
6507 /* If this is not an integer mode, or if we cannot do arithmetic in this
6508 mode, this can't be a giv. */
6515 {
6522 /* Put constant last, CONST_INT last if both constant. */
6530 /* Handle addition of zero, then addition of an invariant. */
6535 {
6538 /* Adding two invariants must result in an invariant, so enclose
6539 addition operation inside a USE and return it. */
6549 else
6558 /* biv + invar or mult + invar. Return sum. */
6562 /* (a + invar_1) + invar_2. Associate. */
6563 return
6569 arg1)),
6574 }
6576 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6577 MULT to reduce cases. */
6583 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6584 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6585 Recurse to associate the second PLUS. */
6590 return
6598 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6614 /* Handle "a - b" as "a + b * (-1)". */
6620 constm1_rtx)),
6629 /* Put constant last, CONST_INT last if both constant. */
6634 /* If second argument is not now constant, not giv. */
6638 /* Handle multiply by 0 or 1. */
6646 {
6648 /* biv * invar. Done. */
6652 /* Product of two constants. */
6656 /* invar * invar is a giv, but attempt to simplify it somehow. */
6662 {
6663 /* (invar_0 * invar_1) * invar_2. Associate. */
6670 arg1)),
6672 }
6673 /* Porpagate the MULT expressions to the intermost nodes. */
6675 {
6676 /* (invar_0 + invar_1) * invar_2. Distribute. */
6682 arg1),
6686 arg1)),
6688 }
6692 /* (a * invar_1) * invar_2. Associate. */
6698 arg1)),
6702 /* (a + invar_1) * invar_2. Distribute. */
6707 arg1),
6710 arg1)),
6715 }
6718 /* Shift by constant is multiply by power of two. */
6722 return
6731 /* "-a" is "a * (-1)" */
6737 /* "~a" is "-a - 1". Silly, but easy. */
6741 const1_rtx),
6745 /* Already in proper form for invariant. */
6751 /* Conditionally recognize extensions of simple IVs. After we've
6752 computed loop traversal counts and verified the range of the
6753 source IV, we'll reevaluate this as a GIV. */
6755 {
6758 {
6761 }
6762 }
6766 /* If this is a new register, we can't deal with it. */
6770 /* Check for biv or giv. */
6772 {
6776 {
6779 /* Form expression from giv and add benefit. Ensure this giv
6780 can derive another and subtract any needed adjustment if so. */
6782 /* Increasing the benefit here is risky. The only case in which it
6783 is arguably correct is if this is the only use of V. In other
6784 cases, this will artificially inflate the benefit of the current
6785 giv, and lead to suboptimal code. Thus, it is disabled, since
6786 potentially not reducing an only marginally beneficial giv is
6787 less harmful than reducing many givs that are not really
6788 beneficial. */
6789 {
6793 }
6806 {
6809 }
6810 else
6811 {
6814 }
6816 }
6819 do_default:
6820 /* If it isn't an induction variable, and it is invariant, we
6821 may be able to simplify things further by looking through
6822 the bits we just moved outside the loop. */
6824 {
6830 {
6831 /* Ok, we found a match. Substitute and simplify. */
6833 /* If we match another movable, we must use that, as
6834 this one is going away. */
6839 /* If consec is non-zero, this is a member of a group of
6840 instructions that were moved together. We handle this
6841 case only to the point of seeking to the last insn and
6842 looking for a REG_EQUAL. Fail if we don't find one. */
6844 {
6847 do
6848 {
6850 }
6856 }
6857 else
6858 {
6862 }
6865 {
6866 /* What we are most interested in is pointer
6867 arithmetic on invariants -- only take
6868 patterns we may be able to do something with. */
6874 {
6876 benefit);
6879 }
6884 {
6889 }
6890 }
6892 }
6893 }
6895 }
6897 /* Fall through to general case. */
6899 /* If invariant, return as USE (unless CONST_INT).
6900 Otherwise, not giv. */
6905 {
6914 }
6915 else
6917 }
6918 }
6920 /* This routine folds invariants such that there is only ever one
6921 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6923 static rtx
6926 {
6932 {
6935 }
6938 {
6941 }
6942 else
6943 {
6946 }
6947 }
6949 static rtx
6953 {
6955 {
6959 else
6962 }
6965 else
6968 }
6969 \f
6970 /* Help detect a giv that is calculated by several consecutive insns;
6971 for example,
6972 giv = biv * M
6973 giv = giv + A
6974 The caller has already identified the first insn P as having a giv as dest;
6975 we check that all other insns that set the same register follow
6976 immediately after P, that they alter nothing else,
6977 and that the result of the last is still a giv.
6979 The value is 0 if the reg set in P is not really a giv.
6980 Otherwise, the value is the amount gained by eliminating
6981 all the consecutive insns that compute the value.
6983 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6984 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6986 The coefficients of the ultimate giv value are stored in
6987 *MULT_VAL and *ADD_VAL. */
6989 static int
6994 rtx p;
6995 rtx src_reg;
6996 rtx dest_reg;
7001 {
7007 rtx temp;
7008 rtx set;
7010 /* Indicate that this is a giv so that we can update the value produced in
7011 each insn of the multi-insn sequence.
7013 This induction structure will be used only by the call to
7014 general_induction_var below, so we can allocate it on our stack.
7015 If this is a giv, our caller will replace the induct var entry with
7016 a new induction structure. */
7037 {
7041 /* If libcall, skip to end of call sequence. */
7052 /* Giv created by equivalent expression. */
7058 {
7062 count--;
7066 }
7068 {
7069 /* Allow insns that set something other than this giv to a
7070 constant. Such insns are needed on machines which cannot
7071 include long constants and should not disqualify a giv. */
7080 }
7081 }
7086 }
7087 \f
7088 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7089 represented by G1. If no such expression can be found, or it is clear that
7090 it cannot possibly be a valid address, 0 is returned.
7092 To perform the computation, we note that
7093 G1 = x * v + a and
7094 G2 = y * v + b
7095 where `v' is the biv.
7097 So G2 = (y/b) * G1 + (b - a*y/x).
7099 Note that MULT = y/x.
7101 Update: A and B are now allowed to be additive expressions such that
7102 B contains all variables in A. That is, computing B-A will not require
7103 subtracting variables. */
7105 static rtx
7108 {
7109 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7114 /* If MULT is not 1, we cannot handle A with non-constants, since we
7115 would then be required to subtract multiples of the registers in A.
7116 This is theoretically possible, and may even apply to some Fortran
7117 constructs, but it is a lot of work and we do not attempt it here. */
7122 /* In general these structures are sorted top to bottom (down the PLUS
7123 chain), but not left to right across the PLUS. If B is a higher
7124 order giv than A, we can strip one level and recurse. If A is higher
7125 order, we'll eventually bail out, but won't know that until the end.
7126 If they are the same, we'll strip one level around this loop. */
7129 {
7141 /* We matched: remove one reg completely. */
7144 /* An alternate match. */
7147 /* An alternate match. */
7149 else
7150 {
7151 /* Indicates an extra register in B. Strip one level from B and
7152 recurse, hoping B was the higher order expression. */
7157 }
7158 }
7160 /* Here we are at the last level of A, go through the cases hoping to
7161 get rid of everything but a constant. */
7164 {
7177 }
7179 {
7181 }
7183 {
7188 }
7190 {
7195 else
7197 }
7202 }
7204 rtx
7207 {
7210 /* The value that G1 will be multiplied by must be a constant integer. Also,
7211 the only chance we have of getting a valid address is if b*c/a (see above
7212 for notation) is also an integer. */
7215 {
7220 }
7223 else
7224 {
7225 /* ??? Find out if the one is a multiple of the other? */
7227 }
7231 {
7232 /* Failed. If we've got a multiplication factor between G1 and G2,
7233 scale G1's addend and try again. */
7235 {
7239 {
7240 HOST_WIDE_INT m;
7244 }
7245 else
7246 {
7248 mult);
7249 }
7252 }
7253 }
7257 /* Form simplified final result. */
7262 else
7267 else
7268 {
7271 {
7275 }
7278 }
7279 }
7280 \f
7281 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7282 represented by G1. This indicates that G2 should be combined with G1 and
7283 that G2 can use (either directly or via an address expression) a register
7284 used to represent G1. */
7286 static rtx
7289 {
7292 /* With the introduction of ext dependent givs, we must care for modes.
7293 G2 must not use a wider mode than G1. */
7303 /* If these givs are identical, they can be combined. We use the results
7304 of express_from because the addends are not in a canonical form, so
7305 rtx_equal_p is a weaker test. */
7306 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7307 combination to be the other way round. */
7310 {
7312 }
7314 /* If G2 can be expressed as a function of G1 and that function is valid
7315 as an address and no more expensive than using a register for G2,
7316 the expression of G2 in terms of G1 can be used. */
7320 /* ??? Looses, especially with -fforce-addr, where *g2->location
7321 will always be a register, and so anything more complicated
7322 gets discarded. */
7323 #if 0
7324 #ifdef ADDRESS_COST
7326 #else
7328 #endif
7329 #endif
7330 )
7331 {
7333 }
7336 }
7337 \f
7338 /* Check each extension dependent giv in this class to see if its
7339 root biv is safe from wrapping in the interior mode, which would
7340 make the giv illegal. */
7342 static void
7346 {
7349 HOST_WIDE_INT start_val;
7355 /* Make sure the iteration data is available. We must have
7356 constants in order to be certain of no overflow. */
7357 /* ??? An unknown iteration count with an increment of +-1
7358 combined with friendly exit tests of against an invariant
7359 value is also ameanable to optimization. Not implemented. */
7365 /* Make sure the host can represent the arithmetic. */
7367 {
7369 HOST_WIDE_INT s_end_val;
7381 /* Check for host arithmatic overflow. */
7383 {
7385 HOST_WIDE_INT s_max;
7392 /* Check zero extension of biv ok. */
7394 /* Check for host arithmatic overflow. */
7395 && (neg_incr
7398 /* Check for target arithmetic overflow. */
7399 && (neg_incr
7402 {
7404 }
7406 /* Check sign extension of biv ok. */
7407 /* ??? While it is true that overflow with signed and pointer
7408 arithmetic is undefined, I fear too many programmers don't
7409 keep this fact in mind -- myself included on occasion.
7410 So leave alone with the signed overflow optimizations. */
7412 /* Check for host arithmatic overflow. */
7413 && (neg_incr
7416 /* Check for target arithmetic overflow. */
7417 && (neg_incr
7420 {
7422 }
7423 }
7424 }
7426 /* Invalidate givs that fail the tests. */
7429 {
7434 {
7443 /* We don't know whether this value is being used as either
7444 signed or unsigned, so to safely truncate we must satisfy
7445 both. The initial check here verifies the BIV itself;
7446 once that is successful we may check its range wrt the
7447 derived GIV. */
7449 {
7453 /* We know from the above that both endpoints are nonnegative,
7454 and that there is no wrapping. Verify that both endpoints
7455 are within the (signed) range of the outer mode. */
7458 }
7463 }
7466 {
7468 {
7472 }
7473 }
7474 else
7475 {
7477 {
7482 else
7483 {
7488 else
7490 }
7495 }
7498 }
7499 }
7500 }
7502 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7504 rtx
7507 rtx value;
7508 {
7514 /* Recall that check_ext_dependent_givs verified that the known bounds
7515 of a biv did not overflow or wrap with respect to the extension for
7516 the giv. Therefore, constants need no additional adjustment. */
7520 /* Otherwise, we must adjust the value to compensate for the
7521 differing modes of the biv and the giv. */
7523 }
7524 \f
7525 struct combine_givs_stats
7526 {
7529 };
7531 static int
7535 {
7542 /* Stabilize the sort. */
7546 }
7548 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7549 any other. If so, point SAME to the giv combined with and set NEW_REG to
7550 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7551 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7553 static void
7557 {
7558 /* Additional benefit to add for being combined multiple times. */
7566 /* Count givs, because bl->giv_count is incorrect here. */
7570 giv_count++;
7572 giv_array
7583 {
7585 rtx single_use;
7590 /* If a DEST_REG GIV is used only once, do not allow it to combine
7591 with anything, for in doing so we will gain nothing that cannot
7592 be had by simply letting the GIV with which we would have combined
7593 to be reduced on its own. The losage shows up in particular with
7594 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7595 be seen elsewhere as well. */
7602 /* Add an additional weight for zero addends. */
7607 {
7608 rtx this_combine;
7613 {
7616 }
7617 }
7619 }
7621 /* Iterate, combining until we can't. */
7622 restart:
7626 {
7629 {
7635 }
7637 }
7640 {
7646 /* If it has already been combined, skip. */
7651 {
7654 /* If it has already been combined, skip. */
7656 {
7661 /* For destination, we now may replace by mem expression instead
7662 of register. This changes the costs considerably, so add the
7663 compensation. */
7673 /* ??? The new final_[bg]iv_value code does a much better job
7674 of finding replaceable giv's, and hence this code may no
7675 longer be necessary. */
7679 /* To help optimize the next set of combinations, remove
7680 this giv from the benefits of other potential mates. */
7682 {
7686 }
7693 }
7694 }
7696 /* To help optimize the next set of combinations, remove
7697 this giv from the benefits of other potential mates. */
7699 {
7701 {
7705 }
7709 /* We've finished with this giv, and everything it touched.
7710 Restart the combination so that proper weights for the
7711 rest of the givs are properly taken into account. */
7712 /* ??? Ideally we would compact the arrays at this point, so
7713 as to not cover old ground. But sanely compacting
7714 can_combine is tricky. */
7716 }
7717 }
7719 /* Clean up. */
7722 }
7723 \f
7724 /* Generate sequence for REG = B * M + A. */
7726 static rtx
7732 {
7733 rtx seq;
7734 rtx result;
7737 /* Use unsigned arithmetic. */
7745 }
7748 /* Update registers created in insn sequence SEQ. */
7750 static void
7753 rtx seq;
7754 {
7755 /* Update register info for alias analysis. */
7758 {
7761 {
7765 }
7766 }
7767 else
7768 {
7772 }
7773 }
7776 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. */
7778 void
7785 basic_block before_bb;
7786 rtx before_insn;
7787 {
7788 rtx seq;
7791 {
7794 }
7796 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7799 /* Increase the lifetime of any invariants moved further in code. */
7806 /* It is possible that the expansion created lots of new registers.
7807 Iterate over the sequence we just created and record them all. */
7809 }
7812 /* Emit insns in loop pre-header to set REG = B * M + A. */
7814 void
7821 {
7822 rtx seq;
7824 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7827 /* Increase the lifetime of any invariants moved further in code.
7828 ???? Is this really necessary? */
7835 /* It is possible that the expansion created lots of new registers.
7836 Iterate over the sequence we just created and record them all. */
7838 }
7841 /* Emit insns after loop to set REG = B * M + A. */
7843 void
7850 {
7851 rtx seq;
7853 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7858 /* It is possible that the expansion created lots of new registers.
7859 Iterate over the sequence we just created and record them all. */
7861 }
7865 /* Similar to gen_add_mult, but compute cost rather than generating
7866 sequence. */
7868 static int
7874 {
7884 {
7889 }
7892 }
7893 \f
7894 /* Test whether A * B can be computed without
7895 an actual multiply insn. Value is 1 if so. */
7897 static int
7899 rtx a;
7900 rtx b;
7901 {
7903 rtx tmp;
7906 /* If only one is constant, make it B. */
7910 /* If first constant, both constant, so don't need multiply. */
7914 /* If second not constant, neither is constant, so would need multiply. */
7918 /* One operand is constant, so might not need multiply insn. Generate the
7919 code for the multiply and see if a call or multiply, or long sequence
7920 of insns is generated. */
7928 {
7933 else
7935 {
7944 {
7947 }
7948 }
7949 }
7959 }
7960 \f
7961 /* Check to see if loop can be terminated by a "decrement and branch until
7962 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7963 Also try reversing an increment loop to a decrement loop
7964 to see if the optimization can be performed.
7965 Value is nonzero if optimization was performed. */
7967 /* This is useful even if the architecture doesn't have such an insn,
7968 because it might change a loops which increments from 0 to n to a loop
7969 which decrements from n to 0. A loop that decrements to zero is usually
7970 faster than one that increments from zero. */
7972 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7973 such as approx_final_value, biv_total_increment, loop_iterations, and
7974 final_[bg]iv_value. */
7976 static int
7980 {
7985 rtx reg;
7986 rtx jump_label;
7987 rtx final_value;
7988 rtx start_value;
7989 rtx new_add_val;
7990 rtx comparison;
7991 rtx before_comparison;
7992 rtx p;
7993 rtx jump;
7994 rtx first_compare;
7999 /* If last insn is a conditional branch, and the insn before tests a
8000 register value, try to optimize it. Otherwise, we can't do anything. */
8009 /* Try to compute whether the compare/branch at the loop end is one or
8010 two instructions. */
8016 else
8019 {
8020 /* If more than one condition is present to control the loop, then
8021 do not proceed, as this function does not know how to rewrite
8022 loop tests with more than one condition.
8024 Look backwards from the first insn in the last comparison
8025 sequence and see if we've got another comparison sequence. */
8027 rtx jump1;
8031 }
8033 /* Check all of the bivs to see if the compare uses one of them.
8034 Skip biv's set more than once because we can't guarantee that
8035 it will be zero on the last iteration. Also skip if the biv is
8036 used between its update and the test insn. */
8039 {
8044 first_compare))
8046 }
8051 /* Look for the case where the basic induction variable is always
8052 nonnegative, and equals zero on the last iteration.
8053 In this case, add a reg_note REG_NONNEG, which allows the
8054 m68k DBRA instruction to be used. */
8062 {
8063 /* Initial value must be greater than 0,
8064 init_val % -dec_value == 0 to ensure that it equals zero on
8065 the last iteration */
8071 {
8072 /* register always nonnegative, add REG_NOTE to branch */
8080 }
8082 /* If the decrement is 1 and the value was tested as >= 0 before
8083 the loop, then we can safely optimize. */
8085 {
8098 {
8106 }
8107 }
8108 }
8111 {
8112 /* Try to change inc to dec, so can apply above optimization. */
8113 /* Can do this if:
8114 all registers modified are induction variables or invariant,
8115 all memory references have non-overlapping addresses
8116 (obviously true if only one write)
8117 allow 2 insns for the compare/jump at the end of the loop. */
8118 /* Also, we must avoid any instructions which use both the reversed
8119 biv and another biv. Such instructions will fail if the loop is
8120 reversed. We meet this condition by requiring that either
8121 no_use_except_counting is true, or else that there is only
8122 one biv. */
8124 /* 1 if the iteration var is used only to count iterations. */
8126 /* 1 if the loop has no memory store, or it has a single memory store
8127 which is reversible. */
8133 {
8137 /* If there are no givs for this biv, and the only exit is the
8138 fall through at the end of the loop, then
8139 see if perhaps there are no uses except to count. */
8143 {
8148 /* An insn that sets the biv is okay. */
8149 ;
8153 {
8154 /* If either of these insns uses the biv and sets a pseudo
8155 that has more than one usage, then the biv has uses
8156 other than counting since it's used to derive a value
8157 that is used more than one time. */
8159 regs);
8161 {
8164 }
8165 }
8167 {
8170 }
8171 }
8173 /* A biv has uses besides counting if it is used to set
8174 another biv. */
8178 {
8181 }
8182 }
8185 /* No need to worry about MEMs. */
8186 ;
8188 {
8193 /* If the loop has a single store, and the destination address is
8194 invariant, then we can't reverse the loop, because this address
8195 might then have the wrong value at loop exit.
8196 This would work if the source was invariant also, however, in that
8197 case, the insn should have been moved out of the loop. */
8200 {
8203 /* If we could prove that each of the memory locations
8204 written to was different, then we could reverse the
8205 store -- but we don't presently have any way of
8206 knowing that. */
8209 /* If the store depends on a register that is set after the
8210 store, it depends on the initial value, and is thus not
8211 reversible. */
8213 {
8220 }
8221 }
8222 }
8223 else
8226 /* This code only acts for innermost loops. Also it simplifies
8227 the memory address check by only reversing loops with
8228 zero or one memory access.
8229 Two memory accesses could involve parts of the same array,
8230 and that can't be reversed.
8231 If the biv is used only for counting, than we don't need to worry
8232 about all these things. */
8238 && reversible_mem_store
8243 {
8244 rtx tem;
8246 /* Loop can be reversed. */
8250 /* Now check other conditions:
8252 The increment must be a constant, as must the initial value,
8253 and the comparison code must be LT.
8255 This test can probably be improved since +/- 1 in the constant
8256 can be obtained by changing LT to LE and vice versa; this is
8257 confusing. */
8260 /* for constants, LE gets turned into LT */
8264 {
8275 comparison_const_width
8277 else
8278 comparison_const_width
8282 comparison_sign_mask
8285 /* If the comparison value is not a loop invariant, then we
8286 can not reverse this loop.
8288 ??? If the insns which initialize the comparison value as
8289 a whole compute an invariant result, then we could move
8290 them out of the loop and proceed with loop reversal. */
8298 /* Normalize the initial value if it is an integer and
8299 has no other use except as a counter. This will allow
8300 a few more loops to be reversed. */
8304 {
8306 /* The code below requires comparison_val to be a multiple
8307 of add_val in order to do the loop reversal, so
8308 round up comparison_val to a multiple of add_val.
8309 Since comparison_value is constant, we know that the
8310 current comparison code is LT. */
8312 comparison_val
8314 /* We postpone overflow checks for COMPARISON_VAL here;
8315 even if there is an overflow, we might still be able to
8316 reverse the loop, if converting the loop exit test to
8317 NE is possible. */
8319 }
8321 /* First check if we can do a vanilla loop reversal. */
8323 /* If we have a decrement_and_branch_on_count,
8324 prefer the NE test, since this will allow that
8325 instruction to be generated. Note that we must
8326 use a vanilla loop reversal if the biv is used to
8327 calculate a giv or has a non-counting use. */
8328 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8329 && defined (HAVE_decrement_and_branch_on_count)
8333 #endif
8335 /* Now do postponed overflow checks on COMPARISON_VAL. */
8338 {
8339 /* Register will always be nonnegative, with value
8340 0 on last iteration */
8344 }
8348 {
8351 }
8352 else
8358 /* If the initial value is not zero, or if the comparison
8359 value is not an exact multiple of the increment, then we
8360 can not reverse this loop. */
8363 {
8366 }
8367 else
8368 {
8371 }
8375 /* Reset these in case we normalized the initial value
8376 and comparison value above. */
8379 {
8381 final_value
8383 }
8386 /* Save some info needed to produce the new insns. */
8391 /* Set start_value; if this is not a CONST_INT, we need
8392 to generate a SUB.
8393 Initialize biv to start_value before loop start.
8394 The old initializing insn will be deleted as a
8395 dead store by flow.c. */
8398 {
8401 }
8403 {
8411 start_value
8417 }
8419 {
8422 initial_value);
8426 start_value
8429 }
8430 else
8431 /* We could handle the other cases too, but it'll be
8432 better to have a testcase first. */
8435 /* We may not have a single insn which can increment a reg, so
8436 create a sequence to hold all the insns from expand_inc. */
8445 /* Update biv info to reflect its new status. */
8450 /* Update loop info. */
8459 /* Inc LABEL_NUSES so that delete_insn will
8460 not delete the label. */
8463 /* Emit an insn after the end of the loop to set the biv's
8464 proper exit value if it is used anywhere outside the loop. */
8470 /* Delete compare/branch at end of loop. */
8475 /* Add new compare/branch insn at end of loop. */
8487 ;
8493 {
8495 {
8496 /* Increment of LABEL_NUSES done above. */
8497 /* Register is now always nonnegative,
8498 so add REG_NONNEG note to the branch. */
8501 }
8503 }
8505 /* No insn may reference both the reversed and another biv or it
8506 will fail (see comment near the top of the loop reversal
8507 code).
8508 Earlier on, we have verified that the biv has no use except
8509 counting, or it is the only biv in this function.
8510 However, the code that computes no_use_except_counting does
8511 not verify reg notes. It's possible to have an insn that
8512 references another biv, and has a REG_EQUAL note with an
8513 expression based on the reversed biv. To avoid this case,
8514 remove all REG_EQUAL notes based on the reversed biv
8515 here. */
8518 {
8521 /* If this is a set of a GIV based on the reversed biv, any
8522 REG_EQUAL notes should still be correct. */
8529 {
8534 else
8536 }
8537 }
8539 /* Mark that this biv has been reversed. Each giv which depends
8540 on this biv, and which is also live past the end of the loop
8541 will have to be fixed up. */
8546 {
8550 else
8552 }
8555 }
8556 }
8557 }
8560 }
8561 \f
8562 /* Verify whether the biv BL appears to be eliminable,
8563 based on the insns in the loop that refer to it.
8565 If ELIMINATE_P is non-zero, actually do the elimination.
8567 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8568 determine whether invariant insns should be placed inside or at the
8569 start of the loop. */
8571 static int
8577 {
8580 rtx p;
8582 /* Scan all insns in the loop, stopping if we find one that uses the
8583 biv in a way that we cannot eliminate. */
8586 {
8591 /* If this is a libcall that sets a giv, skip ahead to its end. */
8593 {
8597 {
8602 {
8609 }
8610 }
8611 }
8616 {
8622 }
8623 }
8626 {
8631 }
8634 }
8635 \f
8636 /* INSN and REFERENCE are instructions in the same insn chain.
8637 Return non-zero if INSN is first. */
8639 int
8642 {
8646 {
8647 /* Start with test for not first so that INSN == REFERENCE yields not
8648 first. */
8654 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8655 previous insn, hence the <= comparison below does not work if
8656 P is a note. */
8667 }
8668 }
8670 /* We are trying to eliminate BIV in INSN using GIV. Return non-zero if
8671 the offset that we have to take into account due to auto-increment /
8672 div derivation is zero. */
8673 static int
8676 rtx insn;
8677 {
8678 /* If the giv V had the auto-inc address optimization applied
8679 to it, and INSN occurs between the giv insn and the biv
8680 insn, then we'd have to adjust the value used here.
8681 This is rare, so we don't bother to make this possible. */
8690 }
8692 /* If BL appears in X (part of the pattern of INSN), see if we can
8693 eliminate its use. If so, return 1. If not, return 0.
8695 If BIV does not appear in X, return 1.
8697 If ELIMINATE_P is non-zero, actually do the elimination.
8698 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8699 Depending on how many items have been moved out of the loop, it
8700 will either be before INSN (when WHERE_INSN is non-zero) or at the
8701 start of the loop (when WHERE_INSN is zero). */
8703 static int
8709 basic_block where_bb;
8710 rtx where_insn;
8711 {
8717 #ifdef HAVE_cc0
8719 #endif
8725 {
8727 /* If we haven't already been able to do something with this BIV,
8728 we can't eliminate it. */
8734 /* If this sets the BIV, it is not a problem. */
8738 /* If this is an insn that defines a giv, it is also ok because
8739 it will go away when the giv is reduced. */
8744 #ifdef HAVE_cc0
8746 {
8747 /* Can replace with any giv that was reduced and
8748 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8749 Require a constant for MULT_VAL, so we know it's nonzero.
8750 ??? We disable this optimization to avoid potential
8751 overflows. */
8759 {
8766 /* If the giv has the opposite direction of change,
8767 then reverse the comparison. */
8771 else
8774 /* We can probably test that giv's reduced reg. */
8777 }
8779 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8780 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8781 Require a constant for MULT_VAL, so we know it's nonzero.
8782 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8783 overflow problem. */
8795 {
8802 /* If the giv has the opposite direction of change,
8803 then reverse the comparison. */
8807 else
8811 /* Replace biv with the giv's reduced register. */
8816 /* Insn doesn't support that constant or invariant. Copy it
8817 into a register (it will be a loop invariant.) */
8824 /* Substitute the new register for its invariant value in
8825 the compare expression. */
8829 }
8830 }
8831 #endif
8838 /* See if either argument is the biv. */
8843 else
8847 {
8848 /* First try to replace with any giv that has constant positive
8849 mult_val and constant add_val. We might be able to support
8850 negative mult_val, but it seems complex to do it in general. */
8862 {
8869 /* Replace biv with the giv's reduced reg. */
8872 /* If all constants are actually constant integers and
8873 the derived constant can be directly placed in the COMPARE,
8874 do so. */
8878 {
8883 }
8884 else
8885 {
8886 /* Otherwise, load it into a register. */
8892 }
8895 }
8897 /* Look for giv with positive constant mult_val and nonconst add_val.
8898 Insert insns to calculate new compare value.
8899 ??? Turn this off due to possible overflow. */
8907 {
8908 rtx tem;
8918 /* Replace biv with giv's reduced register. */
8922 /* Compute value to compare against. */
8926 /* Use it in this insn. */
8930 }
8931 }
8933 {
8935 {
8936 /* Look for giv with constant positive mult_val and nonconst
8937 add_val. Insert insns to compute new compare value.
8938 ??? Turn this off due to possible overflow. */
8945 {
8946 rtx tem;
8956 /* Replace biv with giv's reduced register. */
8960 /* Compute value to compare against. */
8967 }
8968 }
8970 /* This code has problems. Basically, you can't know when
8971 seeing if we will eliminate BL, whether a particular giv
8972 of ARG will be reduced. If it isn't going to be reduced,
8973 we can't eliminate BL. We can try forcing it to be reduced,
8974 but that can generate poor code.
8976 The problem is that the benefit of reducing TV, below should
8977 be increased if BL can actually be eliminated, but this means
8978 we might have to do a topological sort of the order in which
8979 we try to process biv. It doesn't seem worthwhile to do
8980 this sort of thing now. */
8982 #if 0
8983 /* Otherwise the reg compared with had better be a biv. */
8988 /* Look for a pair of givs, one for each biv,
8989 with identical coefficients. */
8991 {
9003 {
9010 /* Replace biv with its giv's reduced reg. */
9012 /* Replace other operand with the other giv's
9013 reduced reg. */
9016 }
9017 }
9018 #endif
9019 }
9021 /* If we get here, the biv can't be eliminated. */
9025 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9026 biv is used in it, since it will be replaced. */
9034 }
9036 /* See if any subexpression fails elimination. */
9039 {
9041 {
9054 }
9055 }
9058 }
9059 \f
9060 /* Return nonzero if the last use of REG
9061 is in an insn following INSN in the same basic block. */
9063 static int
9065 rtx reg;
9066 rtx insn;
9067 {
9068 rtx n;
9072 {
9075 }
9077 }
9078 \f
9079 /* Called via `note_stores' to record the initial value of a biv. Here we
9080 just record the location of the set and process it later. */
9082 static void
9084 rtx dest;
9085 rtx set;
9087 {
9098 /* If this is the first set found, record it. */
9100 {
9103 }
9104 }
9105 \f
9106 /* If any of the registers in X are "old" and currently have a last use earlier
9107 than INSN, update them to have a last use of INSN. Their actual last use
9108 will be the previous insn but it will not have a valid uid_luid so we can't
9109 use it. X must be a source expression only. */
9111 static void
9113 rtx x;
9114 rtx insn;
9115 {
9116 /* Check for the case where INSN does not have a valid luid. In this case,
9117 there is no need to modify the regno_last_uid, as this can only happen
9118 when code is inserted after the loop_end to set a pseudo's final value,
9119 and hence this insn will never be the last use of x.
9120 ???? This comment is not correct. See for example loop_givs_reduce.
9121 This may insert an insn before another new insn. */
9125 {
9127 }
9128 else
9129 {
9133 {
9139 }
9140 }
9141 }
9142 \f
9143 /* Given an insn INSN and condition COND, return the condition in a
9144 canonical form to simplify testing by callers. Specifically:
9146 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9147 (2) Both operands will be machine operands; (cc0) will have been replaced.
9148 (3) If an operand is a constant, it will be the second operand.
9149 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9150 for GE, GEU, and LEU.
9152 If the condition cannot be understood, or is an inequality floating-point
9153 comparison which needs to be reversed, 0 will be returned.
9155 If REVERSE is non-zero, then reverse the condition prior to canonizing it.
9157 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9158 insn used in locating the condition was found. If a replacement test
9159 of the condition is desired, it should be placed in front of that
9160 insn and we will be sure that the inputs are still valid.
9162 If WANT_REG is non-zero, we wish the condition to be relative to that
9163 register, if possible. Therefore, do not canonicalize the condition
9164 further. */
9166 rtx
9168 rtx insn;
9169 rtx cond;
9172 rtx want_reg;
9173 {
9176 rtx set;
9177 rtx tem;
9195 /* If we are comparing a register with zero, see if the register is set
9196 in the previous insn to a COMPARE or a comparison operation. Perform
9197 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9198 in cse.c */
9203 {
9204 /* Set non-zero when we find something of interest. */
9207 #ifdef HAVE_cc0
9208 /* If comparison with cc0, import actual comparison from compare
9209 insn. */
9211 {
9222 }
9223 #endif
9225 /* If this is a COMPARE, pick up the two things being compared. */
9227 {
9231 }
9235 /* Go back to the previous insn. Stop if it is not an INSN. We also
9236 stop if it isn't a single set or if it has a REG_INC note because
9237 we don't want to bother dealing with it. */
9251 /* If this is setting OP0, get what it sets it to if it looks
9252 relevant. */
9254 {
9257 /* ??? We may not combine comparisons done in a CCmode with
9258 comparisons not done in a CCmode. This is to aid targets
9259 like Alpha that have an IEEE compliant EQ instruction, and
9260 a non-IEEE compliant BEQ instruction. The use of CCmode is
9261 actually artificial, simply to prevent the combination, but
9262 should not affect other platforms.
9264 However, we must allow VOIDmode comparisons to match either
9265 CCmode or non-CCmode comparison, because some ports have
9266 modeless comparisons inside branch patterns.
9268 ??? This mode check should perhaps look more like the mode check
9269 in simplify_comparison in combine. */
9277 && (STORE_FLAG_VALUE
9280 #ifdef FLOAT_STORE_FLAG_VALUE
9283 && (REAL_VALUE_NEGATIVE
9285 #endif
9286 ))
9297 && (STORE_FLAG_VALUE
9300 #ifdef FLOAT_STORE_FLAG_VALUE
9303 && (REAL_VALUE_NEGATIVE
9305 #endif
9306 ))
9312 {
9315 }
9316 else
9318 }
9321 /* If this sets OP0, but not directly, we have to give up. */
9325 {
9329 {
9334 }
9339 }
9340 }
9342 /* If constant is first, put it last. */
9346 /* If OP0 is the result of a comparison, we weren't able to find what
9347 was really being compared, so fail. */
9351 /* Canonicalize any ordered comparison with integers involving equality
9352 if we can do computations in the relevant mode and we do not
9353 overflow. */
9358 {
9361 unsigned HOST_WIDE_INT max_val
9365 {
9371 /* When cross-compiling, const_val might be sign-extended from
9372 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9392 }
9393 }
9395 #ifdef HAVE_cc0
9396 /* Never return CC0; return zero instead. */
9399 #endif
9402 }
9404 /* Given a jump insn JUMP, return the condition that will cause it to branch
9405 to its JUMP_LABEL. If the condition cannot be understood, or is an
9406 inequality floating-point comparison which needs to be reversed, 0 will
9407 be returned.
9409 If EARLIEST is non-zero, it is a pointer to a place where the earliest
9410 insn used in locating the condition was found. If a replacement test
9411 of the condition is desired, it should be placed in front of that
9412 insn and we will be sure that the inputs are still valid. */
9414 rtx
9416 rtx jump;
9418 {
9419 rtx cond;
9421 rtx set;
9423 /* If this is not a standard conditional jump, we can't parse it. */
9431 /* If this branches to JUMP_LABEL when the condition is false, reverse
9432 the condition. */
9433 reverse
9438 }
9440 /* Similar to above routine, except that we also put an invariant last
9441 unless both operands are invariants. */
9443 rtx
9446 rtx x;
9447 {
9457 }
9459 /* Scan the function and determine whether it has indirect (computed) jumps.
9461 This is taken mostly from flow.c; similar code exists elsewhere
9462 in the compiler. It may be useful to put this into rtlanal.c. */
9463 static int
9465 rtx start;
9466 {
9467 rtx insn;
9474 }
9476 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9477 documentation for LOOP_MEMS for the definition of `appropriate'.
9478 This function is called from prescan_loop via for_each_rtx. */
9480 static int
9484 {
9493 {
9498 /* We're not interested in MEMs that are only clobbered. */
9502 /* We're not interested in the MEM associated with a
9503 CONST_DOUBLE, so there's no need to traverse into this. */
9507 /* We're not interested in any MEMs that only appear in notes. */
9511 /* This is not a MEM. */
9513 }
9515 /* See if we've already seen this MEM. */
9518 {
9520 /* The modes of the two memory accesses are different. If
9521 this happens, something tricky is going on, and we just
9522 don't optimize accesses to this MEM. */
9526 }
9528 /* Resize the array, if necessary. */
9530 {
9533 else
9539 }
9541 /* Actually insert the MEM. */
9543 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9544 because we can't put it in a register. We still store it in the
9545 table, though, so that if we see the same address later, but in a
9546 non-BLK mode, we'll not think we can optimize it at that point. */
9552 }
9555 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9557 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9558 register that is modified by an insn between FROM and TO. If the
9559 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9560 more, stop incrementing it, to avoid overflow.
9562 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9563 register I is used, if it is only used once. Otherwise, it is set
9564 to 0 (for no uses) or const0_rtx for more than one use. This
9565 parameter may be zero, in which case this processing is not done.
9567 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9568 optimize register I. */
9570 static void
9574 {
9577 /* last_set[n] is nonzero iff reg n has been set in the current
9578 basic block. In that case, it is the insn that last set reg n. */
9580 rtx insn;
9586 /* Grow the regs array if not allocated or too small. */
9588 {
9594 /* Zero the new elements. */
9597 }
9599 /* Clear previously scanned fields but do not clear n_times_set. */
9601 {
9605 }
9609 /* Scan the loop, recording register usage. */
9612 {
9614 {
9615 /* Record registers that have exactly one use. */
9618 /* Include uses in REG_EQUAL notes. */
9626 {
9630 last_set);
9631 }
9632 }
9636 }
9638 /* Invalidate all hard registers clobbered by calls. With one exception:
9639 a call-clobbered PIC register is still function-invariant for our
9640 purposes, since we can hoist any PIC calculations out of the loop.
9641 Thus the call to rtx_varies_p. */
9646 {
9649 }
9651 #ifdef AVOID_CCMODE_COPIES
9652 /* Don't try to move insns which set CC registers if we should not
9653 create CCmode register copies. */
9657 #endif
9659 /* Set regs->array[I].n_times_set for the new registers. */
9664 }
9666 /* Returns the number of real INSNs in the LOOP. */
9668 static int
9671 {
9673 rtx insn;
9681 }
9683 /* Move MEMs into registers for the duration of the loop. */
9685 static void
9688 {
9695 rtx end_label;
9696 /* Nonzero if the next instruction may never be executed. */
9703 /* We cannot use next_label here because it skips over normal insns. */
9708 /* Check to see if it's possible that some instructions in the loop are
9709 never executed. Also check if there is a goto out of the loop other
9710 than right after the end of the loop. */
9714 {
9718 /* If we enter the loop in the middle, and scan
9719 around to the beginning, don't set maybe_never
9720 for that. This must be an unconditional jump,
9721 otherwise the code at the top of the loop might
9722 never be executed. Unconditional jumps are
9723 followed a by barrier then loop end. */
9728 {
9729 /* If this is a jump outside of the loop but not right
9730 after the end of the loop, we would have to emit new fixup
9731 sequences for each such label. */
9733 JUMP_INSN is executed, we must be conservative. */
9742 /* Something complicated. */
9744 else
9745 /* If there are any more instructions in the loop, they
9746 might not be reached. */
9748 }
9751 }
9753 /* Find start of the extended basic block that enters the loop. */
9757 ;
9762 /* Build table of mems that get set to constant values before the
9763 loop. */
9767 /* Actually move the MEMs. */
9769 {
9770 regset_head load_copies;
9771 regset_head store_copies;
9773 rtx reg;
9775 rtx mem_list_entry;
9779 /* There's no telling whether or not MEM is modified. */
9782 /* Go through the MEMs written to in the loop to see if this
9783 one is aliased by one of them. */
9786 {
9791 {
9792 /* MEM is indeed aliased by this store. */
9795 }
9797 }
9803 /* If this MEM is written to, we must be sure that there
9804 are no reads from another MEM that aliases this one. */
9806 {
9810 {
9814 VOIDmode,
9816 rtx_varies_p))
9817 {
9818 /* It's not safe to hoist loop_info->mems[i] out of
9819 the loop because writes to it might not be
9820 seen by reads from loop_info->mems[j]. */
9823 }
9824 }
9825 }
9828 /* We can't access the MEM outside the loop; it might
9829 cause a trap that wouldn't have happened otherwise. */
9833 /* We thought we were going to lift this MEM out of the
9834 loop, but later discovered that we could not. */
9840 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9841 order to keep scan_loop from moving stores to this MEM
9842 out of the loop just because this REG is neither a
9843 user-variable nor used in the loop test. */
9848 /* Now, replace all references to the MEM with the
9849 corresponding pseudos. */
9854 {
9856 {
9857 rtx set;
9861 /* See if this copies the mem into a register that isn't
9862 modified afterwards. We'll try to do copy propagation
9863 a little further on. */
9865 /* @@@ This test is _way_ too conservative. */
9866 && ! maybe_never
9874 /* See if this copies the mem from a register that isn't
9875 modified afterwards. We'll try to remove the
9876 redundant copy later on by doing a little register
9877 renaming and copy propagation. This will help
9878 to untangle things for the BIV detection code. */
9880 && ! maybe_never
9888 /* If this is a call which uses / clobbers this memory
9889 location, we must not change the interface here. */
9893 {
9897 }
9898 else
9899 /* Replace the memory reference with the shadow register. */
9902 }
9907 }
9912 /* We couldn't replace all occurrences of the MEM. */
9914 else
9915 {
9916 /* Load the memory immediately before LOOP->START, which is
9917 the NOTE_LOOP_BEG. */
9919 rtx set;
9925 {
9929 {
9933 /* Extending hard register lifetimes causes crash
9934 on SRC targets. Doing so on non-SRC is
9935 probably also not good idea, since we most
9936 probably have pseudoregister equivalence as
9937 well. */
9940 }
9941 /* Use the constant equivalence if that is cheap enough. */
9947 {
9950 }
9952 /* If best_equiv is nonzero, we know that MEM is set to a
9953 constant or register before the loop. We will use this
9954 knowledge to initialize the shadow register with that
9955 constant or reg rather than by loading from MEM. */
9958 }
9963 {
9966 {
9969 }
9970 }
9976 {
9978 {
9981 }
9983 /* Store the memory immediately after END, which is
9984 the NOTE_LOOP_END. */
9987 }
9990 {
9995 }
9997 /* Attempt a bit of copy propagation. This helps untangle the
9998 data flow, and enables {basic,general}_induction_var to find
9999 more bivs/givs. */
10000 EXECUTE_IF_SET_IN_REG_SET
10002 {
10004 });
10007 EXECUTE_IF_SET_IN_REG_SET
10009 {
10011 });
10013 }
10014 }
10017 {
10018 /* Now, we need to replace all references to the previous exit
10019 label with the new one. */
10020 rtx_pair rr;
10025 {
10028 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
10029 field. This is not handled by for_each_rtx because it doesn't
10030 handle unprinted ('0') fields. We need to update JUMP_LABEL
10031 because the immediately following unroll pass will use it.
10032 replace_label would not work anyways, because that only handles
10033 LABEL_REFs. */
10036 }
10037 }
10040 }
10042 /* For communication between note_reg_stored and its caller. */
10043 struct note_reg_stored_arg
10044 {
10046 rtx reg;
10047 };
10049 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10050 is equal to ARG. */
10051 static void
10055 {
10059 }
10061 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10062 There must be exactly one insn that sets this pseudo; it will be
10063 deleted if all replacements succeed and we can prove that the register
10064 is not used after the loop. */
10066 static void
10069 rtx replacement;
10071 {
10072 /* This is the reg that we are copying from. */
10075 rtx insn;
10076 /* These help keep track of whether we replaced all uses of the reg. */
10083 {
10084 rtx set;
10086 /* Only substitute within one extended basic block from the initializing
10087 insn. */
10094 /* Is this the initializing insn? */
10099 {
10106 }
10108 /* Only substitute after seeing the initializing insn. */
10110 {
10117 /* Stop replacing when REPLACEMENT is modified. */
10122 {
10125 /* It is possible that we've turned previously valid REG_EQUAL to
10126 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10127 REPLACEMENT is modified, we get different meaning. */
10131 }
10132 }
10133 }
10137 {
10141 {
10142 rtx first;
10143 rtx retval_note;
10145 /* Assume we're just deleting INIT_INSN. */
10147 /* Look for REG_RETVAL note. If we're deleting the end of
10148 the libcall sequence, the whole sequence can go. */
10150 /* If we found a REG_RETVAL note, find the first instruction
10151 in the sequence. */
10155 /* Delete the instructions. */
10157 }
10160 }
10161 }
10163 /* Replace all the instructions from FIRST up to and including LAST
10164 with NOTE_INSN_DELETED notes. */
10166 static void
10168 rtx first;
10169 rtx last;
10170 {
10172 {
10178 /* If this was the LAST instructions we're supposed to delete,
10179 we're done. */
10184 }
10185 }
10187 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10188 loop LOOP if the order of the sets of these registers can be
10189 swapped. There must be exactly one insn within the loop that sets
10190 this pseudo followed immediately by a move insn that sets
10191 REPLACEMENT with REGNO. */
10192 static void
10195 rtx replacement;
10197 {
10198 rtx insn;
10207 {
10208 /* Search for the insn that copies REGNO to NEW_REGNO? */
10216 }
10219 {
10220 rtx prev_insn;
10221 rtx prev_set;
10223 /* Some DEF-USE info would come in handy here to make this
10224 function more general. For now, just check the previous insn
10225 which is the most likely candidate for setting REGNO. */
10233 {
10234 /* We have:
10235 (set (reg regno) (expr))
10236 (set (reg new_regno) (reg regno))
10238 so try converting this to:
10239 (set (reg new_regno) (expr))
10240 (set (reg regno) (reg new_regno))
10242 The former construct is often generated when a global
10243 variable used for an induction variable is shadowed by a
10244 register (NEW_REGNO). The latter construct improves the
10245 chances of GIV replacement and BIV elimination. */
10255 {
10262 /* Update first use of REGNO. */
10266 /* Now perform copy propagation to hopefully
10267 remove all uses of REGNO within the loop. */
10269 }
10270 }
10271 }
10272 }
10274 /* Replace MEM with its associated pseudo register. This function is
10275 called from load_mems via for_each_rtx. DATA is actually a pointer
10276 to a structure describing the instruction currently being scanned
10277 and the MEM we are currently replacing. */
10279 static int
10283 {
10291 {
10296 /* We're not interested in the MEM associated with a
10297 CONST_DOUBLE, so there's no need to traverse into one. */
10301 /* This is not a MEM. */
10303 }
10306 /* This is not the MEM we are currently replacing. */
10309 /* Actually replace the MEM. */
10313 }
10315 static void
10317 rtx insn;
10318 rtx mem;
10319 rtx reg;
10320 {
10321 loop_replace_args args;
10328 }
10330 /* Replace one register with another. Called through for_each_rtx; PX points
10331 to the rtx being scanned. DATA is actually a pointer to
10332 a structure of arguments. */
10334 static int
10338 {
10349 }
10351 static void
10353 rtx insn;
10354 rtx reg;
10355 rtx replacement;
10356 {
10357 loop_replace_args args;
10364 }
10366 /* Replace occurrences of the old exit label for the loop with the new
10367 one. DATA is an rtx_pair containing the old and new labels,
10368 respectively. */
10370 static int
10374 {
10393 }
10394 \f
10395 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10396 (ignored in the interim). */
10398 static rtx
10401 basic_block where_bb ATTRIBUTE_UNUSED;
10402 rtx where_insn;
10403 rtx pattern;
10404 {
10406 }
10409 /* If WHERE_INSN is non-zero emit insn for PATTERN before WHERE_INSN
10410 in basic block WHERE_BB (ignored in the interim) within the loop
10411 otherwise hoist PATTERN into the loop pre-header. */
10413 rtx
10416 basic_block where_bb ATTRIBUTE_UNUSED;
10417 rtx where_insn;
10418 rtx pattern;
10419 {
10423 }
10426 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10427 WHERE_BB (ignored in the interim) within the loop. */
10429 static rtx
10432 basic_block where_bb ATTRIBUTE_UNUSED;
10433 rtx where_insn;
10434 rtx pattern;
10435 {
10437 }
10440 /* Hoist insn for PATTERN into the loop pre-header. */
10442 rtx
10445 rtx pattern;
10446 {
10448 }
10451 /* Hoist call insn for PATTERN into the loop pre-header. */
10453 static rtx
10456 rtx pattern;
10457 {
10459 }
10462 /* Sink insn for PATTERN after the loop end. */
10464 rtx
10467 rtx pattern;
10468 {
10470 }
10472 /* bl->final_value can be eighter general_operand or PLUS of general_operand
10473 and constant. Emit sequence of intructions to load it into REG */
10474 static rtx
10477 {
10478 rtx seq;
10486 }
10488 /* If the loop has multiple exits, emit insn for PATTERN before the
10489 loop to ensure that it will always be executed no matter how the
10490 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10491 since this is slightly more efficient. */
10493 static rtx
10496 rtx pattern;
10497 {
10500 else
10502 }
10503 \f
10504 static void
10509 {
10517 iv_num++;
10522 {
10525 }
10526 }
10529 static void
10534 {
10536 rtx incr;
10547 {
10550 }
10552 {
10555 }
10559 {
10563 }
10566 {
10570 }
10572 /* List the increments. */
10574 {
10578 }
10580 /* List the givs. */
10582 {
10587 else
10590 }
10591 }
10594 static void
10599 {
10610 {
10614 }
10617 }
10620 static void
10625 {
10632 else
10648 {
10650 {
10662 }
10663 }
10674 {
10678 }
10681 }
10684 void
10687 {
10689 }
10692 void
10695 {
10697 }
10700 void
10703 {
10705 }
10708 void
10711 {
10713 }
10716 #define LOOP_BLOCK_NUM_1(INSN) \
10717 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10719 /* The notes do not have an assigned block, so look at the next insn. */
10720 #define LOOP_BLOCK_NUM(INSN) \
10721 ((INSN) ? (GET_CODE (INSN) == NOTE \
10722 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10723 : LOOP_BLOCK_NUM_1 (INSN)) \
10724 : -1)
10726 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10728 static void
10733 {
10734 rtx label;
10739 /* Print diagnostics to compare our concept of a loop with
10740 what the loop notes say. */
10755 {
10775 {
10778 {
10781 }
10782 }
10785 /* This can happen when a marked loop appears as two nested loops,
10786 say from while (a || b) {}. The inner loop won't match
10787 the loop markers but the outer one will. */
10790 }
10791 }
10793 /* Call this function from the debugger to dump LOOP. */
10795 void
10798 {
10800 }
10802 /* Call this function from the debugger to dump LOOPS. */
10804 void
10807 {
10809 }