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* config/xtensa/lib1funcs.asm: Avoid use of .Lfe* in .size directives.
[official-gcc.git] / gcc / config / xtensa / xtensa.h
blob89ae1fda79f06047f507d3c4e03d12e970c70999
1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001,2002,2003 Free Software Foundation, Inc.
3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 /* Get Xtensa configuration settings */
23 #include "xtensa/xtensa-config.h"
24
25 /* Standard GCC variables that we reference. */
26 extern int current_function_calls_alloca;
27 extern int target_flags;
28 extern int optimize;
29
30 /* External variables defined in xtensa.c. */
31
32 /* comparison type */
33 enum cmp_type {
34 CMP_SI, /* four byte integers */
35 CMP_DI, /* eight byte integers */
36 CMP_SF, /* single precision floats */
37 CMP_DF, /* double precision floats */
38 CMP_MAX /* max comparison type */
39 };
40
41 extern struct rtx_def * branch_cmp[2]; /* operands for compare */
42 extern enum cmp_type branch_type; /* what type of branch to use */
43 extern unsigned xtensa_current_frame_size;
44
45 /* Run-time compilation parameters selecting different hardware subsets. */
46
47 #define MASK_BIG_ENDIAN 0x00000001 /* big or little endian */
48 #define MASK_DENSITY 0x00000002 /* code density option */
49 #define MASK_MAC16 0x00000004 /* MAC16 option */
50 #define MASK_MUL16 0x00000008 /* 16-bit integer multiply */
51 #define MASK_MUL32 0x00000010 /* integer multiply/divide */
52 #define MASK_DIV32 0x00000020 /* integer multiply/divide */
53 #define MASK_NSA 0x00000040 /* nsa instruction option */
54 #define MASK_MINMAX 0x00000080 /* min/max instructions */
55 #define MASK_SEXT 0x00000100 /* sign extend insn option */
56 #define MASK_BOOLEANS 0x00000200 /* boolean register option */
57 #define MASK_HARD_FLOAT 0x00000400 /* floating-point option */
58 #define MASK_HARD_FLOAT_DIV 0x00000800 /* floating-point divide */
59 #define MASK_HARD_FLOAT_RECIP 0x00001000 /* floating-point reciprocal */
60 #define MASK_HARD_FLOAT_SQRT 0x00002000 /* floating-point sqrt */
61 #define MASK_HARD_FLOAT_RSQRT 0x00004000 /* floating-point recip sqrt */
62 #define MASK_NO_FUSED_MADD 0x00008000 /* avoid f-p mul/add */
63 #define MASK_SERIALIZE_VOLATILE 0x00010000 /* serialize volatile refs */
64 #define MASK_CONST16 0x00020000 /* use CONST16 instruction */
65 #define MASK_ABS 0x00040000 /* use ABS instruction */
66 #define MASK_ADDX 0x00080000 /* use ADDX* and SUBX* */
67
68 /* Macros used in the machine description to test the flags. */
69
70 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
71 #define TARGET_DENSITY (target_flags & MASK_DENSITY)
72 #define TARGET_MAC16 (target_flags & MASK_MAC16)
73 #define TARGET_MUL16 (target_flags & MASK_MUL16)
74 #define TARGET_MUL32 (target_flags & MASK_MUL32)
75 #define TARGET_DIV32 (target_flags & MASK_DIV32)
76 #define TARGET_NSA (target_flags & MASK_NSA)
77 #define TARGET_MINMAX (target_flags & MASK_MINMAX)
78 #define TARGET_SEXT (target_flags & MASK_SEXT)
79 #define TARGET_BOOLEANS (target_flags & MASK_BOOLEANS)
80 #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT)
81 #define TARGET_HARD_FLOAT_DIV (target_flags & MASK_HARD_FLOAT_DIV)
82 #define TARGET_HARD_FLOAT_RECIP (target_flags & MASK_HARD_FLOAT_RECIP)
83 #define TARGET_HARD_FLOAT_SQRT (target_flags & MASK_HARD_FLOAT_SQRT)
84 #define TARGET_HARD_FLOAT_RSQRT (target_flags & MASK_HARD_FLOAT_RSQRT)
85 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
86 #define TARGET_SERIALIZE_VOLATILE (target_flags & MASK_SERIALIZE_VOLATILE)
87 #define TARGET_CONST16 (target_flags & MASK_CONST16)
88 #define TARGET_ABS (target_flags & MASK_ABS)
89 #define TARGET_ADDX (target_flags & MASK_ADDX)
90
91 /* Default target_flags if no switches are specified */
92
93 #define TARGET_DEFAULT ( \
94 (XCHAL_HAVE_BE ? MASK_BIG_ENDIAN : 0) | \
95 (XCHAL_HAVE_DENSITY ? MASK_DENSITY : 0) | \
96 (XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \
97 (XCHAL_HAVE_ABS ? MASK_ABS : 0) | \
98 (XCHAL_HAVE_ADDX ? MASK_ADDX : 0) | \
99 (XCHAL_HAVE_MAC16 ? MASK_MAC16 : 0) | \
100 (XCHAL_HAVE_MUL16 ? MASK_MUL16 : 0) | \
101 (XCHAL_HAVE_MUL32 ? MASK_MUL32 : 0) | \
102 (XCHAL_HAVE_DIV32 ? MASK_DIV32 : 0) | \
103 (XCHAL_HAVE_NSA ? MASK_NSA : 0) | \
104 (XCHAL_HAVE_MINMAX ? MASK_MINMAX : 0) | \
105 (XCHAL_HAVE_SEXT ? MASK_SEXT : 0) | \
106 (XCHAL_HAVE_BOOLEANS ? MASK_BOOLEANS : 0) | \
107 (XCHAL_HAVE_FP ? MASK_HARD_FLOAT : 0) | \
108 (XCHAL_HAVE_FP_DIV ? MASK_HARD_FLOAT_DIV : 0) | \
109 (XCHAL_HAVE_FP_RECIP ? MASK_HARD_FLOAT_RECIP : 0) | \
110 (XCHAL_HAVE_FP_SQRT ? MASK_HARD_FLOAT_SQRT : 0) | \
111 (XCHAL_HAVE_FP_RSQRT ? MASK_HARD_FLOAT_RSQRT : 0) | \
112 MASK_SERIALIZE_VOLATILE)
113
114 /* Macro to define tables used to set the flags. */
115
116 #define TARGET_SWITCHES \
117 { \
118 {"big-endian", MASK_BIG_ENDIAN, \
119 N_("Use big-endian byte order")}, \
120 {"little-endian", -MASK_BIG_ENDIAN, \
121 N_("Use little-endian byte order")}, \
122 {"density", MASK_DENSITY, \
123 N_("Use the Xtensa code density option")}, \
124 {"no-density", -MASK_DENSITY, \
125 N_("Do not use the Xtensa code density option")}, \
126 {"const16", MASK_CONST16, \
127 N_("Use CONST16 instruction to load constants")}, \
128 {"no-const16", -MASK_CONST16, \
129 N_("Use PC-relative L32R instruction to load constants")}, \
130 {"abs", MASK_ABS, \
131 N_("Use the Xtensa ABS instruction")}, \
132 {"no-abs", -MASK_ABS, \
133 N_("Do not use the Xtensa ABS instruction")}, \
134 {"addx", MASK_ADDX, \
135 N_("Use the Xtensa ADDX and SUBX instructions")}, \
136 {"no-addx", -MASK_ADDX, \
137 N_("Do not use the Xtensa ADDX and SUBX instructions")}, \
138 {"mac16", MASK_MAC16, \
139 N_("Use the Xtensa MAC16 option")}, \
140 {"no-mac16", -MASK_MAC16, \
141 N_("Do not use the Xtensa MAC16 option")}, \
142 {"mul16", MASK_MUL16, \
143 N_("Use the Xtensa MUL16 option")}, \
144 {"no-mul16", -MASK_MUL16, \
145 N_("Do not use the Xtensa MUL16 option")}, \
146 {"mul32", MASK_MUL32, \
147 N_("Use the Xtensa MUL32 option")}, \
148 {"no-mul32", -MASK_MUL32, \
149 N_("Do not use the Xtensa MUL32 option")}, \
150 {"div32", MASK_DIV32, \
151 0 /* undocumented */}, \
152 {"no-div32", -MASK_DIV32, \
153 0 /* undocumented */}, \
154 {"nsa", MASK_NSA, \
155 N_("Use the Xtensa NSA option")}, \
156 {"no-nsa", -MASK_NSA, \
157 N_("Do not use the Xtensa NSA option")}, \
158 {"minmax", MASK_MINMAX, \
159 N_("Use the Xtensa MIN/MAX option")}, \
160 {"no-minmax", -MASK_MINMAX, \
161 N_("Do not use the Xtensa MIN/MAX option")}, \
162 {"sext", MASK_SEXT, \
163 N_("Use the Xtensa SEXT option")}, \
164 {"no-sext", -MASK_SEXT, \
165 N_("Do not use the Xtensa SEXT option")}, \
166 {"booleans", MASK_BOOLEANS, \
167 N_("Use the Xtensa boolean register option")}, \
168 {"no-booleans", -MASK_BOOLEANS, \
169 N_("Do not use the Xtensa boolean register option")}, \
170 {"hard-float", MASK_HARD_FLOAT, \
171 N_("Use the Xtensa floating-point unit")}, \
172 {"soft-float", -MASK_HARD_FLOAT, \
173 N_("Do not use the Xtensa floating-point unit")}, \
174 {"hard-float-div", MASK_HARD_FLOAT_DIV, \
175 0 /* undocumented */}, \
176 {"no-hard-float-div", -MASK_HARD_FLOAT_DIV, \
177 0 /* undocumented */}, \
178 {"hard-float-recip", MASK_HARD_FLOAT_RECIP, \
179 0 /* undocumented */}, \
180 {"no-hard-float-recip", -MASK_HARD_FLOAT_RECIP, \
181 0 /* undocumented */}, \
182 {"hard-float-sqrt", MASK_HARD_FLOAT_SQRT, \
183 0 /* undocumented */}, \
184 {"no-hard-float-sqrt", -MASK_HARD_FLOAT_SQRT, \
185 0 /* undocumented */}, \
186 {"hard-float-rsqrt", MASK_HARD_FLOAT_RSQRT, \
187 0 /* undocumented */}, \
188 {"no-hard-float-rsqrt", -MASK_HARD_FLOAT_RSQRT, \
189 0 /* undocumented */}, \
190 {"no-fused-madd", MASK_NO_FUSED_MADD, \
191 N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
192 {"fused-madd", -MASK_NO_FUSED_MADD, \
193 N_("Enable fused multiply/add and multiply/subtract FP instructions")}, \
194 {"serialize-volatile", MASK_SERIALIZE_VOLATILE, \
195 N_("Serialize volatile memory references with MEMW instructions")}, \
196 {"no-serialize-volatile", -MASK_SERIALIZE_VOLATILE, \
197 N_("Do not serialize volatile memory references with MEMW instructions")},\
198 {"text-section-literals", 0, \
199 N_("Intersperse literal pools with code in the text section")}, \
200 {"no-text-section-literals", 0, \
201 N_("Put literal pools in a separate literal section")}, \
202 {"target-align", 0, \
203 N_("Automatically align branch targets to reduce branch penalties")}, \
204 {"no-target-align", 0, \
205 N_("Do not automatically align branch targets")}, \
206 {"longcalls", 0, \
207 N_("Use indirect CALLXn instructions for large programs")}, \
208 {"no-longcalls", 0, \
209 N_("Use direct CALLn instructions for fast calls")}, \
210 {"", TARGET_DEFAULT, 0} \
211 }
212
213
214 #define OVERRIDE_OPTIONS override_options ()
215 \f
216 /* Target CPU builtins. */
217 #define TARGET_CPU_CPP_BUILTINS() \
218 do { \
219 builtin_assert ("cpu=xtensa"); \
220 builtin_assert ("machine=xtensa"); \
221 builtin_define ("__XTENSA__"); \
222 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
223 if (!TARGET_HARD_FLOAT) \
224 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
225 if (flag_pic) \
226 { \
227 builtin_define ("__PIC__"); \
228 builtin_define ("__pic__"); \
229 } \
230 } while (0)
231
232 #define CPP_SPEC " %(subtarget_cpp_spec) "
233
234 #ifndef SUBTARGET_CPP_SPEC
235 #define SUBTARGET_CPP_SPEC ""
236 #endif
237
238 #define EXTRA_SPECS \
239 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
240
241 #ifdef __XTENSA_EB__
242 #define LIBGCC2_WORDS_BIG_ENDIAN 1
243 #else
244 #define LIBGCC2_WORDS_BIG_ENDIAN 0
245 #endif
246
247 /* Show we can debug even without a frame pointer. */
248 #define CAN_DEBUG_WITHOUT_FP
249
250
251 /* Target machine storage layout */
252
253 /* Define this if most significant bit is lowest numbered
254 in instructions that operate on numbered bit-fields. */
255 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
256
257 /* Define this if most significant byte of a word is the lowest numbered. */
258 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
259
260 /* Define this if most significant word of a multiword number is the lowest. */
261 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
262
263 #define MAX_BITS_PER_WORD 32
264
265 /* Width of a word, in units (bytes). */
266 #define UNITS_PER_WORD 4
267 #define MIN_UNITS_PER_WORD 4
268
269 /* Width of a floating point register. */
270 #define UNITS_PER_FPREG 4
271
272 /* Size in bits of various types on the target machine. */
273 #define INT_TYPE_SIZE 32
274 #define SHORT_TYPE_SIZE 16
275 #define LONG_TYPE_SIZE 32
276 #define MAX_LONG_TYPE_SIZE 32
277 #define LONG_LONG_TYPE_SIZE 64
278 #define FLOAT_TYPE_SIZE 32
279 #define DOUBLE_TYPE_SIZE 64
280 #define LONG_DOUBLE_TYPE_SIZE 64
281
282 /* Allocation boundary (in *bits*) for storing pointers in memory. */
283 #define POINTER_BOUNDARY 32
284
285 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
286 #define PARM_BOUNDARY 32
287
288 /* Allocation boundary (in *bits*) for the code of a function. */
289 #define FUNCTION_BOUNDARY 32
290
291 /* Alignment of field after 'int : 0' in a structure. */
292 #define EMPTY_FIELD_BOUNDARY 32
293
294 /* Every structure's size must be a multiple of this. */
295 #define STRUCTURE_SIZE_BOUNDARY 8
296
297 /* There is no point aligning anything to a rounder boundary than this. */
298 #define BIGGEST_ALIGNMENT 128
299
300 /* Set this nonzero if move instructions will actually fail to work
301 when given unaligned data. */
302 #define STRICT_ALIGNMENT 1
303
304 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
305 for QImode, because there is no 8-bit load from memory with sign
306 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
307 loads both with and without sign extension. */
308 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
309 do { \
310 if (GET_MODE_CLASS (MODE) == MODE_INT \
311 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
312 { \
313 if ((MODE) == QImode) \
314 (UNSIGNEDP) = 1; \
315 (MODE) = SImode; \
316 } \
317 } while (0)
318
319 /* The promotion described by `PROMOTE_MODE' should also be done for
320 outgoing function arguments. */
321 #define PROMOTE_FUNCTION_ARGS
322
323 /* The promotion described by `PROMOTE_MODE' should also be done for
324 the return value of functions. Note: `FUNCTION_VALUE' must perform
325 the same promotions done by `PROMOTE_MODE'. */
326 #define PROMOTE_FUNCTION_RETURN
327
328 /* Imitate the way many other C compilers handle alignment of
329 bitfields and the structures that contain them. */
330 #define PCC_BITFIELD_TYPE_MATTERS 1
331
332 /* Align string constants and constructors to at least a word boundary.
333 The typical use of this macro is to increase alignment for string
334 constants to be word aligned so that 'strcpy' calls that copy
335 constants can be done inline. */
336 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
337 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
338 && (ALIGN) < BITS_PER_WORD \
339 ? BITS_PER_WORD \
340 : (ALIGN))
341
342 /* Align arrays, unions and records to at least a word boundary.
343 One use of this macro is to increase alignment of medium-size
344 data to make it all fit in fewer cache lines. Another is to
345 cause character arrays to be word-aligned so that 'strcpy' calls
346 that copy constants to character arrays can be done inline. */
347 #undef DATA_ALIGNMENT
348 #define DATA_ALIGNMENT(TYPE, ALIGN) \
349 ((((ALIGN) < BITS_PER_WORD) \
350 && (TREE_CODE (TYPE) == ARRAY_TYPE \
351 || TREE_CODE (TYPE) == UNION_TYPE \
352 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
353
354 /* An argument declared as 'char' or 'short' in a prototype should
355 actually be passed as an 'int'. */
356 #define PROMOTE_PROTOTYPES 1
357
358 /* Operations between registers always perform the operation
359 on the full register even if a narrower mode is specified. */
360 #define WORD_REGISTER_OPERATIONS
361
362 /* Xtensa loads are zero-extended by default. */
363 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
364
365 /* Standard register usage. */
366
367 /* Number of actual hardware registers.
368 The hardware registers are assigned numbers for the compiler
369 from 0 to just below FIRST_PSEUDO_REGISTER.
370 All registers that the compiler knows about must be given numbers,
371 even those that are not normally considered general registers.
372
373 The fake frame pointer and argument pointer will never appear in
374 the generated code, since they will always be eliminated and replaced
375 by either the stack pointer or the hard frame pointer.
376
377 0 - 15 AR[0] - AR[15]
378 16 FRAME_POINTER (fake = initial sp)
379 17 ARG_POINTER (fake = initial sp + framesize)
380 18 BR[0] for floating-point CC
381 19 - 34 FR[0] - FR[15]
382 35 MAC16 accumulator */
383
384 #define FIRST_PSEUDO_REGISTER 36
385
386 /* Return the stabs register number to use for REGNO. */
387 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
388
389 /* 1 for registers that have pervasive standard uses
390 and are not available for the register allocator. */
391 #define FIXED_REGISTERS \
392 { \
393 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
394 1, 1, 0, \
395 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
396 0, \
397 }
398
399 /* 1 for registers not available across function calls.
400 These must include the FIXED_REGISTERS and also any
401 registers that can be used without being saved.
402 The latter must include the registers where values are returned
403 and the register where structure-value addresses are passed.
404 Aside from that, you can include as many other registers as you like. */
405 #define CALL_USED_REGISTERS \
406 { \
407 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
408 1, 1, 1, \
409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
410 1, \
411 }
412
413 /* For non-leaf procedures on Xtensa processors, the allocation order
414 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
415 want to use the lowest numbered registers first to minimize
416 register window overflows. However, local-alloc is not smart
417 enough to consider conflicts with incoming arguments. If an
418 incoming argument in a2 is live throughout the function and
419 local-alloc decides to use a2, then the incoming argument must
420 either be spilled or copied to another register. To get around
421 this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine
422 reg_alloc_order for leaf functions such that lowest numbered
423 registers are used first with the exception that the incoming
424 argument registers are not used until after other register choices
425 have been exhausted. */
426
427 #define REG_ALLOC_ORDER \
428 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
429 18, \
430 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
431 0, 1, 16, 17, \
432 35, \
433 }
434
435 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
436
437 /* For Xtensa, the only point of this is to prevent GCC from otherwise
438 giving preference to call-used registers. To minimize window
439 overflows for the AR registers, we want to give preference to the
440 lower-numbered AR registers. For other register files, which are
441 not windowed, we still prefer call-used registers, if there are any. */
442 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
443 #define LEAF_REGISTERS xtensa_leaf_regs
444
445 /* For Xtensa, no remapping is necessary, but this macro must be
446 defined if LEAF_REGISTERS is defined. */
447 #define LEAF_REG_REMAP(REGNO) (REGNO)
448
449 /* this must be declared if LEAF_REGISTERS is set */
450 extern int leaf_function;
451
452 /* Internal macros to classify a register number. */
453
454 /* 16 address registers + fake registers */
455 #define GP_REG_FIRST 0
456 #define GP_REG_LAST 17
457 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
458
459 /* Coprocessor registers */
460 #define BR_REG_FIRST 18
461 #define BR_REG_LAST 18
462 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
463
464 /* 16 floating-point registers */
465 #define FP_REG_FIRST 19
466 #define FP_REG_LAST 34
467 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
468
469 /* MAC16 accumulator */
470 #define ACC_REG_FIRST 35
471 #define ACC_REG_LAST 35
472 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
473
474 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
475 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
476 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
477 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
478
479 /* Return number of consecutive hard regs needed starting at reg REGNO
480 to hold something of mode MODE. */
481 #define HARD_REGNO_NREGS(REGNO, MODE) \
482 (FP_REG_P (REGNO) ? \
483 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
484 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
485
486 /* Value is 1 if hard register REGNO can hold a value of machine-mode
487 MODE. */
488 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
489
490 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
491 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
492
493 /* Value is 1 if it is a good idea to tie two pseudo registers
494 when one has mode MODE1 and one has mode MODE2.
495 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
496 for any hard reg, then this must be 0 for correct output. */
497 #define MODES_TIEABLE_P(MODE1, MODE2) \
498 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
499 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
500 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
501 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
502
503 /* Register to use for pushing function arguments. */
504 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
505
506 /* Base register for access to local variables of the function. */
507 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
508
509 /* The register number of the frame pointer register, which is used to
510 access automatic variables in the stack frame. For Xtensa, this
511 register never appears in the output. It is always eliminated to
512 either the stack pointer or the hard frame pointer. */
513 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
514
515 /* Value should be nonzero if functions must have frame pointers.
516 Zero means the frame pointer need not be set up (and parms
517 may be accessed via the stack pointer) in functions that seem suitable.
518 This is computed in 'reload', in reload1.c. */
519 #define FRAME_POINTER_REQUIRED xtensa_frame_pointer_required ()
520
521 /* Base register for access to arguments of the function. */
522 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
523
524 /* If the static chain is passed in memory, these macros provide rtx
525 giving 'mem' expressions that denote where they are stored.
526 'STATIC_CHAIN' and 'STATIC_CHAIN_INCOMING' give the locations as
527 seen by the calling and called functions, respectively. */
528
529 #define STATIC_CHAIN \
530 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, -5 * UNITS_PER_WORD))
531
532 #define STATIC_CHAIN_INCOMING \
533 gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -5 * UNITS_PER_WORD))
534
535 /* For now we don't try to use the full set of boolean registers. Without
536 software pipelining of FP operations, there's not much to gain and it's
537 a real pain to get them reloaded. */
538 #define FPCC_REGNUM (BR_REG_FIRST + 0)
539
540 /* Pass structure value address as an "invisible" first argument. */
541 #define STRUCT_VALUE 0
542
543 /* It is as good or better to call a constant function address than to
544 call an address kept in a register. */
545 #define NO_FUNCTION_CSE 1
546
547 /* It is as good or better for a function to call itself with an
548 explicit address than to call an address kept in a register. */
549 #define NO_RECURSIVE_FUNCTION_CSE 1
550
551 /* Xtensa processors have "register windows". GCC does not currently
552 take advantage of the possibility for variable-sized windows; instead,
553 we use a fixed window size of 8. */
554
555 #define INCOMING_REGNO(OUT) \
556 ((GP_REG_P (OUT) && \
557 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
558 (OUT) - WINDOW_SIZE : (OUT))
559
560 #define OUTGOING_REGNO(IN) \
561 ((GP_REG_P (IN) && \
562 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
563 (IN) + WINDOW_SIZE : (IN))
564
565
566 /* Define the classes of registers for register constraints in the
567 machine description. */
568 enum reg_class
569 {
570 NO_REGS, /* no registers in set */
571 BR_REGS, /* coprocessor boolean registers */
572 FP_REGS, /* floating point registers */
573 ACC_REG, /* MAC16 accumulator */
574 SP_REG, /* sp register (aka a1) */
575 RL_REGS, /* preferred reload regs (not sp or fp) */
576 GR_REGS, /* integer registers except sp */
577 AR_REGS, /* all integer registers */
578 ALL_REGS, /* all registers */
579 LIM_REG_CLASSES /* max value + 1 */
580 };
581
582 #define N_REG_CLASSES (int) LIM_REG_CLASSES
583
584 #define GENERAL_REGS AR_REGS
585
586 /* An initializer containing the names of the register classes as C
587 string constants. These names are used in writing some of the
588 debugging dumps. */
589 #define REG_CLASS_NAMES \
590 { \
591 "NO_REGS", \
592 "BR_REGS", \
593 "FP_REGS", \
594 "ACC_REG", \
595 "SP_REG", \
596 "RL_REGS", \
597 "GR_REGS", \
598 "AR_REGS", \
599 "ALL_REGS" \
600 }
601
602 /* Contents of the register classes. The Nth integer specifies the
603 contents of class N. The way the integer MASK is interpreted is
604 that register R is in the class if 'MASK & (1 << R)' is 1. */
605 #define REG_CLASS_CONTENTS \
606 { \
607 { 0x00000000, 0x00000000 }, /* no registers */ \
608 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
609 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
610 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
611 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
612 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
613 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
614 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
615 { 0xffffffff, 0x0000000f } /* all registers */ \
616 }
617
618 /* A C expression whose value is a register class containing hard
619 register REGNO. In general there is more that one such class;
620 choose a class which is "minimal", meaning that no smaller class
621 also contains the register. */
622 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
623
624 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
625
626 /* Use the Xtensa AR register file for base registers.
627 No index registers. */
628 #define BASE_REG_CLASS AR_REGS
629 #define INDEX_REG_CLASS NO_REGS
630
631 /* SMALL_REGISTER_CLASSES is required for Xtensa, because all of the
632 16 AR registers may be explicitly used in the RTL, as either
633 incoming or outgoing arguments. */
634 #define SMALL_REGISTER_CLASSES 1
635
636
637 /* REGISTER AND CONSTANT CLASSES */
638
639 /* Get reg_class from a letter such as appears in the machine
640 description.
641
642 Available letters: a-f,h,j-l,q,t-z,A-D,W,Y-Z
643
644 DEFINED REGISTER CLASSES:
645
646 'a' general-purpose registers except sp
647 'q' sp (aka a1)
648 'D' general-purpose registers (only if density option enabled)
649 'd' general-purpose registers, including sp (only if density enabled)
650 'A' MAC16 accumulator (only if MAC16 option enabled)
651 'B' general-purpose registers (only if sext instruction enabled)
652 'C' general-purpose registers (only if mul16 option enabled)
653 'W' general-purpose registers (only if const16 option enabled)
654 'b' coprocessor boolean registers
655 'f' floating-point registers
656 */
657
658 extern enum reg_class xtensa_char_to_class[256];
659
660 #define REG_CLASS_FROM_LETTER(C) xtensa_char_to_class[ (int) (C) ]
661
662 /* The letters I, J, K, L, M, N, O, and P in a register constraint
663 string can be used to stand for particular ranges of immediate
664 operands. This macro defines what the ranges are. C is the
665 letter, and VALUE is a constant value. Return 1 if VALUE is
666 in the range specified by C.
667
668 For Xtensa:
669
670 I = 12-bit signed immediate for movi
671 J = 8-bit signed immediate for addi
672 K = 4-bit value in (b4const U {0})
673 L = 4-bit value in b4constu
674 M = 7-bit value in simm7
675 N = 8-bit unsigned immediate shifted left by 8 bits for addmi
676 O = 4-bit value in ai4const
677 P = valid immediate mask value for extui */
678
679 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
680 ((C) == 'I' ? (xtensa_simm12b (VALUE)) \
681 : (C) == 'J' ? (xtensa_simm8 (VALUE)) \
682 : (C) == 'K' ? (((VALUE) == 0) || xtensa_b4const (VALUE)) \
683 : (C) == 'L' ? (xtensa_b4constu (VALUE)) \
684 : (C) == 'M' ? (xtensa_simm7 (VALUE)) \
685 : (C) == 'N' ? (xtensa_simm8x256 (VALUE)) \
686 : (C) == 'O' ? (xtensa_ai4const (VALUE)) \
687 : (C) == 'P' ? (xtensa_mask_immediate (VALUE)) \
688 : FALSE)
689
690
691 /* Similar, but for floating constants, and defining letters G and H.
692 Here VALUE is the CONST_DOUBLE rtx itself. */
693 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) (0)
694
695
696 /* Other letters can be defined in a machine-dependent fashion to
697 stand for particular classes of registers or other arbitrary
698 operand types.
699
700 R = memory that can be accessed with a 4-bit unsigned offset
701 S = memory where the second word can be addressed with a 4-bit offset
702 T = memory in a constant pool (addressable with a pc-relative load)
703 U = memory *NOT* in a constant pool
704
705 The offset range should not be checked here (except to distinguish
706 denser versions of the instructions for which more general versions
707 are available). Doing so leads to problems in reloading: an
708 argptr-relative address may become invalid when the phony argptr is
709 eliminated in favor of the stack pointer (the offset becomes too
710 large to fit in the instruction's immediate field); a reload is
711 generated to fix this but the RTL is not immediately updated; in
712 the meantime, the constraints are checked and none match. The
713 solution seems to be to simply skip the offset check here. The
714 address will be checked anyway because of the code in
715 GO_IF_LEGITIMATE_ADDRESS. */
716
717 #define EXTRA_CONSTRAINT(OP, CODE) \
718 ((GET_CODE (OP) != MEM) ? \
719 ((CODE) >= 'R' && (CODE) <= 'U' \
720 && reload_in_progress && GET_CODE (OP) == REG \
721 && REGNO (OP) >= FIRST_PSEUDO_REGISTER) \
722 : ((CODE) == 'R') ? smalloffset_mem_p (OP) \
723 : ((CODE) == 'S') ? smalloffset_double_mem_p (OP) \
724 : ((CODE) == 'T') ? !TARGET_CONST16 && constantpool_mem_p (OP) \
725 : ((CODE) == 'U') ? !constantpool_mem_p (OP) \
726 : FALSE)
727
728 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
729 xtensa_preferred_reload_class (X, CLASS, 0)
730
731 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
732 xtensa_preferred_reload_class (X, CLASS, 1)
733
734 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
735 xtensa_secondary_reload_class (CLASS, MODE, X, 0)
736
737 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
738 xtensa_secondary_reload_class (CLASS, MODE, X, 1)
739
740 /* Return the maximum number of consecutive registers
741 needed to represent mode MODE in a register of class CLASS. */
742 #define CLASS_UNITS(mode, size) \
743 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
744
745 #define CLASS_MAX_NREGS(CLASS, MODE) \
746 (CLASS_UNITS (MODE, UNITS_PER_WORD))
747
748
749 /* Stack layout; function entry, exit and calling. */
750
751 #define STACK_GROWS_DOWNWARD
752
753 /* Offset within stack frame to start allocating local variables at. */
754 #define STARTING_FRAME_OFFSET \
755 current_function_outgoing_args_size
756
757 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
758 they are eliminated to either the stack pointer or hard frame pointer. */
759 #define ELIMINABLE_REGS \
760 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
761 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
762 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
763 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
764
765 #define CAN_ELIMINATE(FROM, TO) 1
766
767 /* Specify the initial difference between the specified pair of registers. */
768 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
769 do { \
770 compute_frame_size (get_frame_size ()); \
771 if ((FROM) == FRAME_POINTER_REGNUM) \
772 (OFFSET) = 0; \
773 else if ((FROM) == ARG_POINTER_REGNUM) \
774 (OFFSET) = xtensa_current_frame_size; \
775 else \
776 abort (); \
777 } while (0)
778
779 /* If defined, the maximum amount of space required for outgoing
780 arguments will be computed and placed into the variable
781 'current_function_outgoing_args_size'. No space will be pushed
782 onto the stack for each call; instead, the function prologue
783 should increase the stack frame size by this amount. */
784 #define ACCUMULATE_OUTGOING_ARGS 1
785
786 /* Offset from the argument pointer register to the first argument's
787 address. On some machines it may depend on the data type of the
788 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
789 location above the first argument's address. */
790 #define FIRST_PARM_OFFSET(FNDECL) 0
791
792 /* Align stack frames on 128 bits for Xtensa. This is necessary for
793 128-bit datatypes defined in TIE (e.g., for Vectra). */
794 #define STACK_BOUNDARY 128
795
796 /* Functions do not pop arguments off the stack. */
797 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
798
799 /* Use a fixed register window size of 8. */
800 #define WINDOW_SIZE 8
801
802 /* Symbolic macros for the registers used to return integer, floating
803 point, and values of coprocessor and user-defined modes. */
804 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
805 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
806
807 /* Symbolic macros for the first/last argument registers. */
808 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
809 #define GP_ARG_LAST (GP_REG_FIRST + 7)
810 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
811 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
812
813 #define MAX_ARGS_IN_REGISTERS 6
814
815 /* Don't worry about compatibility with PCC. */
816 #define DEFAULT_PCC_STRUCT_RETURN 0
817
818 /* For Xtensa, up to 4 words can be returned in registers. (It would
819 have been nice to allow up to 6 words in registers but GCC cannot
820 support that. The return value must be given one of the standard
821 MODE_INT modes, and there is no 6 word mode. Instead, if we try to
822 return a 6 word structure, GCC selects the next biggest mode
823 (OImode, 8 words) and then the register allocator fails because
824 there is no 8-register group beginning with a10.) */
825 #define RETURN_IN_MEMORY(TYPE) \
826 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 4 * UNITS_PER_WORD)
827
828 /* Define how to find the value returned by a library function
829 assuming the value has mode MODE. Because we have defined
830 PROMOTE_FUNCTION_RETURN, we have to perform the same promotions as
831 PROMOTE_MODE. */
832 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
833 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
834 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
835 ? SImode : (MODE), \
836 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
837
838 #define LIBCALL_VALUE(MODE) \
839 XTENSA_LIBCALL_VALUE ((MODE), 0)
840
841 #define LIBCALL_OUTGOING_VALUE(MODE) \
842 XTENSA_LIBCALL_VALUE ((MODE), 1)
843
844 /* Define how to find the value returned by a function.
845 VALTYPE is the data type of the value (as a tree).
846 If the precise function being called is known, FUNC is its FUNCTION_DECL;
847 otherwise, FUNC is 0. */
848 #define XTENSA_FUNCTION_VALUE(VALTYPE, FUNC, OUTGOINGP) \
849 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
850 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
851 ? SImode: TYPE_MODE (VALTYPE), \
852 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
853
854 #define FUNCTION_VALUE(VALTYPE, FUNC) \
855 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 0)
856
857 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
858 XTENSA_FUNCTION_VALUE (VALTYPE, FUNC, 1)
859
860 /* A C expression that is nonzero if REGNO is the number of a hard
861 register in which the values of called function may come back. A
862 register whose use for returning values is limited to serving as
863 the second of a pair (for a value of type 'double', say) need not
864 be recognized by this macro. If the machine has register windows,
865 so that the caller and the called function use different registers
866 for the return value, this macro should recognize only the caller's
867 register numbers. */
868 #define FUNCTION_VALUE_REGNO_P(N) \
869 ((N) == GP_RETURN)
870
871 /* A C expression that is nonzero if REGNO is the number of a hard
872 register in which function arguments are sometimes passed. This
873 does *not* include implicit arguments such as the static chain and
874 the structure-value address. On many machines, no registers can be
875 used for this purpose since all function arguments are pushed on
876 the stack. */
877 #define FUNCTION_ARG_REGNO_P(N) \
878 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
879
880 /* Define a data type for recording info about an argument list
881 during the scan of that argument list. This data type should
882 hold all necessary information about the function itself
883 and about the args processed so far, enough to enable macros
884 such as FUNCTION_ARG to determine where the next arg should go. */
885 typedef struct xtensa_args {
886 int arg_words; /* # total words the arguments take */
887 } CUMULATIVE_ARGS;
888
889 /* Initialize a variable CUM of type CUMULATIVE_ARGS
890 for a call to a function whose data type is FNTYPE.
891 For a library call, FNTYPE is 0. */
892 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
893 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
894
895 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
896 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
897
898 /* Update the data in CUM to advance over an argument
899 of mode MODE and data type TYPE.
900 (TYPE is null for libcalls where that information may not be available.) */
901 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
902 function_arg_advance (&CUM, MODE, TYPE)
903
904 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
905 function_arg (&CUM, MODE, TYPE, FALSE)
906
907 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
908 function_arg (&CUM, MODE, TYPE, TRUE)
909
910 /* Arguments are never passed partly in memory and partly in registers. */
911 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) (0)
912
913 /* Specify function argument alignment. */
914 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
915 ((TYPE) != 0 \
916 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
917 ? PARM_BOUNDARY \
918 : TYPE_ALIGN (TYPE)) \
919 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
920 ? PARM_BOUNDARY \
921 : GET_MODE_ALIGNMENT (MODE)))
922
923
924 /* Nonzero if we do not know how to pass TYPE solely in registers.
925 We cannot do so in the following cases:
926
927 - if the type has variable size
928 - if the type is marked as addressable (it is required to be constructed
929 into the stack)
930
931 This differs from the default in that it does not check if the padding
932 and mode of the type are such that a copy into a register would put it
933 into the wrong part of the register. */
934
935 #define MUST_PASS_IN_STACK(MODE, TYPE) \
936 ((TYPE) != 0 \
937 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
938 || TREE_ADDRESSABLE (TYPE)))
939
940 /* Profiling Xtensa code is typically done with the built-in profiling
941 feature of Tensilica's instruction set simulator, which does not
942 require any compiler support. Profiling code on a real (i.e.,
943 non-simulated) Xtensa processor is currently only supported by
944 GNU/Linux with glibc. The glibc version of _mcount doesn't require
945 counter variables. The _mcount function needs the current PC and
946 the current return address to identify an arc in the call graph.
947 Pass the current return address as the first argument; the current
948 PC is available as a0 in _mcount's register window. Both of these
949 values contain window size information in the two most significant
950 bits; we assume that _mcount will mask off those bits. The call to
951 _mcount uses a window size of 8 to make sure that it doesn't clobber
952 any incoming argument values. */
953
954 #define NO_PROFILE_COUNTERS
955
956 #define FUNCTION_PROFILER(FILE, LABELNO) \
957 do { \
958 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
959 if (flag_pic) \
960 { \
961 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
962 fprintf (FILE, "\tcallx8\ta8\n"); \
963 } \
964 else \
965 fprintf (FILE, "\tcall8\t_mcount\n"); \
966 } while (0)
967
968 /* Stack pointer value doesn't matter at exit. */
969 #define EXIT_IGNORE_STACK 1
970
971 /* A C statement to output, on the stream FILE, assembler code for a
972 block of data that contains the constant parts of a trampoline.
973 This code should not include a label--the label is taken care of
974 automatically.
975
976 For Xtensa, the trampoline must perform an entry instruction with a
977 minimal stack frame in order to get some free registers. Once the
978 actual call target is known, the proper stack frame size is extracted
979 from the entry instruction at the target and the current frame is
980 adjusted to match. The trampoline then transfers control to the
981 instruction following the entry at the target. Note: this assumes
982 that the target begins with an entry instruction. */
983
984 /* minimum frame = reg save area (4 words) plus static chain (1 word)
985 and the total number of words must be a multiple of 128 bits */
986 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
987
988 #define TRAMPOLINE_TEMPLATE(STREAM) \
989 do { \
990 fprintf (STREAM, "\t.begin no-generics\n"); \
991 fprintf (STREAM, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); \
992 \
993 /* save the return address */ \
994 fprintf (STREAM, "\tmov\ta10, a0\n"); \
995 \
996 /* Use a CALL0 instruction to skip past the constants and in the \
997 process get the PC into A0. This allows PC-relative access to \
998 the constants without relying on L32R, which may not always be \
999 available. */ \
1000 \
1001 fprintf (STREAM, "\tcall0\t.Lskipconsts\n"); \
1002 fprintf (STREAM, "\t.align\t4\n"); \
1003 fprintf (STREAM, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); \
1004 fprintf (STREAM, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); \
1005 fprintf (STREAM, ".Lskipconsts:\n"); \
1006 \
1007 /* store the static chain */ \
1008 fprintf (STREAM, "\taddi\ta0, a0, 3\n"); \
1009 fprintf (STREAM, "\tl32i\ta8, a0, 0\n"); \
1010 fprintf (STREAM, "\ts32i\ta8, sp, %d\n", MIN_FRAME_SIZE - 20); \
1011 \
1012 /* set the proper stack pointer value */ \
1013 fprintf (STREAM, "\tl32i\ta8, a0, 4\n"); \
1014 fprintf (STREAM, "\tl32i\ta9, a8, 0\n"); \
1015 fprintf (STREAM, "\textui\ta9, a9, %d, 12\n", \
1016 TARGET_BIG_ENDIAN ? 8 : 12); \
1017 fprintf (STREAM, "\tslli\ta9, a9, 3\n"); \
1018 fprintf (STREAM, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); \
1019 fprintf (STREAM, "\tsub\ta9, sp, a9\n"); \
1020 fprintf (STREAM, "\tmovsp\tsp, a9\n"); \
1021 \
1022 /* restore the return address */ \
1023 fprintf (STREAM, "\tmov\ta0, a10\n"); \
1024 \
1025 /* jump to the instruction following the entry */ \
1026 fprintf (STREAM, "\taddi\ta8, a8, 3\n"); \
1027 fprintf (STREAM, "\tjx\ta8\n"); \
1028 fprintf (STREAM, "\t.end no-generics\n"); \
1029 } while (0)
1030
1031 /* Size in bytes of the trampoline, as an integer. */
1032 #define TRAMPOLINE_SIZE 59
1033
1034 /* Alignment required for trampolines, in bits. */
1035 #define TRAMPOLINE_ALIGNMENT (32)
1036
1037 /* A C statement to initialize the variable parts of a trampoline. */
1038 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1039 do { \
1040 rtx addr = ADDR; \
1041 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 12)), CHAIN); \
1042 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 16)), FUNC); \
1043 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__xtensa_sync_caches"), \
1044 0, VOIDmode, 1, addr, Pmode); \
1045 } while (0)
1046
1047 /* Define the `__builtin_va_list' type for the ABI. */
1048 #define BUILD_VA_LIST_TYPE(VALIST) \
1049 (VALIST) = xtensa_build_va_list ()
1050
1051 /* If defined, is a C expression that produces the machine-specific
1052 code for a call to '__builtin_saveregs'. This code will be moved
1053 to the very beginning of the function, before any parameter access
1054 are made. The return value of this function should be an RTX that
1055 contains the value to use as the return of '__builtin_saveregs'. */
1056 #define EXPAND_BUILTIN_SAVEREGS \
1057 xtensa_builtin_saveregs
1058
1059 /* Implement `va_start' for varargs and stdarg. */
1060 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1061 xtensa_va_start (valist, nextarg)
1062
1063 /* Implement `va_arg'. */
1064 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1065 xtensa_va_arg (valist, type)
1066
1067 /* If defined, a C expression that produces the machine-specific code
1068 to setup the stack so that arbitrary frames can be accessed.
1069
1070 On Xtensa, a stack back-trace must always begin from the stack pointer,
1071 so that the register overflow save area can be located. However, the
1072 stack-walking code in GCC always begins from the hard_frame_pointer
1073 register, not the stack pointer. The frame pointer is usually equal
1074 to the stack pointer, but the __builtin_return_address and
1075 __builtin_frame_address functions will not work if count > 0 and
1076 they are called from a routine that uses alloca. These functions
1077 are not guaranteed to work at all if count > 0 so maybe that is OK.
1078
1079 A nicer solution would be to allow the architecture-specific files to
1080 specify whether to start from the stack pointer or frame pointer. That
1081 would also allow us to skip the machine->accesses_prev_frame stuff that
1082 we currently need to ensure that there is a frame pointer when these
1083 builtin functions are used. */
1084
1085 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
1086
1087 /* A C expression whose value is RTL representing the address in a
1088 stack frame where the pointer to the caller's frame is stored.
1089 Assume that FRAMEADDR is an RTL expression for the address of the
1090 stack frame itself.
1091
1092 For Xtensa, there is no easy way to get the frame pointer if it is
1093 not equivalent to the stack pointer. Moreover, the result of this
1094 macro is used for continuing to walk back up the stack, so it must
1095 return the stack pointer address. Thus, there is some inconsistency
1096 here in that __builtin_frame_address will return the frame pointer
1097 when count == 0 and the stack pointer when count > 0. */
1098
1099 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1100 gen_rtx (PLUS, Pmode, frame, \
1101 gen_rtx_CONST_INT (VOIDmode, -3 * UNITS_PER_WORD))
1102
1103 /* Define this if the return address of a particular stack frame is
1104 accessed from the frame pointer of the previous stack frame. */
1105 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1106
1107 /* A C expression whose value is RTL representing the value of the
1108 return address for the frame COUNT steps up from the current
1109 frame, after the prologue. */
1110 #define RETURN_ADDR_RTX xtensa_return_addr
1111
1112 /* Addressing modes, and classification of registers for them. */
1113
1114 /* C expressions which are nonzero if register number NUM is suitable
1115 for use as a base or index register in operand addresses. It may
1116 be either a suitable hard register or a pseudo register that has
1117 been allocated such a hard register. The difference between an
1118 index register and a base register is that the index register may
1119 be scaled. */
1120
1121 #define REGNO_OK_FOR_BASE_P(NUM) \
1122 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
1123
1124 #define REGNO_OK_FOR_INDEX_P(NUM) 0
1125
1126 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
1127 valid for use as a base or index register. For hard registers, it
1128 should always accept those which the hardware permits and reject
1129 the others. Whether the macro accepts or rejects pseudo registers
1130 must be controlled by `REG_OK_STRICT'. This usually requires two
1131 variant definitions, of which `REG_OK_STRICT' controls the one
1132 actually used. The difference between an index register and a base
1133 register is that the index register may be scaled. */
1134
1135 #ifdef REG_OK_STRICT
1136
1137 #define REG_OK_FOR_INDEX_P(X) 0
1138 #define REG_OK_FOR_BASE_P(X) \
1139 REGNO_OK_FOR_BASE_P (REGNO (X))
1140
1141 #else /* !REG_OK_STRICT */
1142
1143 #define REG_OK_FOR_INDEX_P(X) 0
1144 #define REG_OK_FOR_BASE_P(X) \
1145 ((REGNO (X) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (REGNO (X))))
1146
1147 #endif /* !REG_OK_STRICT */
1148
1149 /* Maximum number of registers that can appear in a valid memory address. */
1150 #define MAX_REGS_PER_ADDRESS 1
1151
1152 /* Identify valid Xtensa addresses. */
1153 #define GO_IF_LEGITIMATE_ADDRESS(MODE, ADDR, LABEL) \
1154 do { \
1155 rtx xinsn = (ADDR); \
1156 \
1157 /* allow constant pool addresses */ \
1158 if ((MODE) != BLKmode && GET_MODE_SIZE (MODE) >= UNITS_PER_WORD \
1159 && !TARGET_CONST16 && constantpool_address_p (xinsn)) \
1160 goto LABEL; \
1161 \
1162 while (GET_CODE (xinsn) == SUBREG) \
1163 xinsn = SUBREG_REG (xinsn); \
1164 \
1165 /* allow base registers */ \
1166 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1167 goto LABEL; \
1168 \
1169 /* check for "register + offset" addressing */ \
1170 if (GET_CODE (xinsn) == PLUS) \
1171 { \
1172 rtx xplus0 = XEXP (xinsn, 0); \
1173 rtx xplus1 = XEXP (xinsn, 1); \
1174 enum rtx_code code0; \
1175 enum rtx_code code1; \
1176 \
1177 while (GET_CODE (xplus0) == SUBREG) \
1178 xplus0 = SUBREG_REG (xplus0); \
1179 code0 = GET_CODE (xplus0); \
1180 \
1181 while (GET_CODE (xplus1) == SUBREG) \
1182 xplus1 = SUBREG_REG (xplus1); \
1183 code1 = GET_CODE (xplus1); \
1184 \
1185 /* swap operands if necessary so the register is first */ \
1186 if (code0 != REG && code1 == REG) \
1187 { \
1188 xplus0 = XEXP (xinsn, 1); \
1189 xplus1 = XEXP (xinsn, 0); \
1190 code0 = GET_CODE (xplus0); \
1191 code1 = GET_CODE (xplus1); \
1192 } \
1193 \
1194 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
1195 && code1 == CONST_INT \
1196 && xtensa_mem_offset (INTVAL (xplus1), (MODE))) \
1197 { \
1198 goto LABEL; \
1199 } \
1200 } \
1201 } while (0)
1202
1203 /* A C expression that is 1 if the RTX X is a constant which is a
1204 valid address. This is defined to be the same as 'CONSTANT_P (X)',
1205 but rejecting CONST_DOUBLE. */
1206 #define CONSTANT_ADDRESS_P(X) \
1207 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1208 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1209 || (GET_CODE (X) == CONST)))
1210
1211 /* Nonzero if the constant value X is a legitimate general operand.
1212 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1213 #define LEGITIMATE_CONSTANT_P(X) 1
1214
1215 /* A C expression that is nonzero if X is a legitimate immediate
1216 operand on the target machine when generating position independent
1217 code. */
1218 #define LEGITIMATE_PIC_OPERAND_P(X) \
1219 ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X)) \
1220 && GET_CODE (X) != LABEL_REF \
1221 && GET_CODE (X) != CONST)
1222
1223 /* Tell GCC how to use ADDMI to generate addresses. */
1224 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1225 do { \
1226 rtx xinsn = (X); \
1227 if (GET_CODE (xinsn) == PLUS) \
1228 { \
1229 rtx plus0 = XEXP (xinsn, 0); \
1230 rtx plus1 = XEXP (xinsn, 1); \
1231 \
1232 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) \
1233 { \
1234 plus0 = XEXP (xinsn, 1); \
1235 plus1 = XEXP (xinsn, 0); \
1236 } \
1237 \
1238 if (GET_CODE (plus0) == REG \
1239 && GET_CODE (plus1) == CONST_INT \
1240 && !xtensa_mem_offset (INTVAL (plus1), MODE) \
1241 && !xtensa_simm8 (INTVAL (plus1)) \
1242 && xtensa_mem_offset (INTVAL (plus1) & 0xff, MODE) \
1243 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) \
1244 { \
1245 rtx temp = gen_reg_rtx (Pmode); \
1246 emit_insn (gen_rtx (SET, Pmode, temp, \
1247 gen_rtx (PLUS, Pmode, plus0, \
1248 GEN_INT (INTVAL (plus1) & ~0xff)))); \
1249 (X) = gen_rtx (PLUS, Pmode, temp, \
1250 GEN_INT (INTVAL (plus1) & 0xff)); \
1251 goto WIN; \
1252 } \
1253 } \
1254 } while (0)
1255
1256
1257 /* Treat constant-pool references as "mode dependent" since they can
1258 only be accessed with SImode loads. This works around a bug in the
1259 combiner where a constant pool reference is temporarily converted
1260 to an HImode load, which is then assumed to zero-extend based on
1261 our definition of LOAD_EXTEND_OP. This is wrong because the high
1262 bits of a 16-bit value in the constant pool are now sign-extended
1263 by default. */
1264
1265 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1266 do { \
1267 if (constantpool_address_p (ADDR)) \
1268 goto LABEL; \
1269 } while (0)
1270
1271 /* Specify the machine mode that this machine uses
1272 for the index in the tablejump instruction. */
1273 #define CASE_VECTOR_MODE (SImode)
1274
1275 /* Define this if the tablejump instruction expects the table
1276 to contain offsets from the address of the table.
1277 Do not define this if the table should contain absolute addresses. */
1278 /* #define CASE_VECTOR_PC_RELATIVE */
1279
1280 /* Define this as 1 if 'char' should by default be signed; else as 0. */
1281 #define DEFAULT_SIGNED_CHAR 0
1282
1283 /* Max number of bytes we can move from memory to memory
1284 in one reasonably fast instruction. */
1285 #define MOVE_MAX 4
1286 #define MAX_MOVE_MAX 4
1287
1288 /* Prefer word-sized loads. */
1289 #define SLOW_BYTE_ACCESS 1
1290
1291 /* Xtensa doesn't have any instructions that set integer values based on the
1292 results of comparisons, but the simplification code in the combiner also
1293 uses this macro. The value should be either 1 or -1 to enable some
1294 optimizations in the combiner; I'm not sure which is better for us.
1295 Since we've been using 1 for a while, it should probably stay that way for
1296 compatibility. */
1297 #define STORE_FLAG_VALUE 1
1298
1299 /* Shift instructions ignore all but the low-order few bits. */
1300 #define SHIFT_COUNT_TRUNCATED 1
1301
1302 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1303 is done just by pretending it is already truncated. */
1304 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1305
1306 /* Specify the machine mode that pointers have.
1307 After generation of rtl, the compiler makes no further distinction
1308 between pointers and any other objects of this machine mode. */
1309 #define Pmode SImode
1310
1311 /* A function address in a call instruction is a word address (for
1312 indexing purposes) so give the MEM rtx a words's mode. */
1313 #define FUNCTION_MODE SImode
1314
1315 /* A C expression for the cost of moving data from a register in
1316 class FROM to one in class TO. The classes are expressed using
1317 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
1318 the default; other values are interpreted relative to that. */
1319 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1320 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
1321 ? 2 \
1322 : (reg_class_subset_p ((FROM), AR_REGS) \
1323 && reg_class_subset_p ((TO), AR_REGS) \
1324 ? 2 \
1325 : (reg_class_subset_p ((FROM), AR_REGS) \
1326 && (TO) == ACC_REG \
1327 ? 3 \
1328 : ((FROM) == ACC_REG \
1329 && reg_class_subset_p ((TO), AR_REGS) \
1330 ? 3 \
1331 : 10))))
1332
1333 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
1334
1335 #define BRANCH_COST 3
1336
1337 /* Optionally define this if you have added predicates to
1338 'MACHINE.c'. This macro is called within an initializer of an
1339 array of structures. The first field in the structure is the
1340 name of a predicate and the second field is an array of rtl
1341 codes. For each predicate, list all rtl codes that can be in
1342 expressions matched by the predicate. The list should have a
1343 trailing comma. */
1344
1345 #define PREDICATE_CODES \
1346 {"add_operand", { REG, CONST_INT, SUBREG }}, \
1347 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
1348 {"nonimmed_operand", { REG, SUBREG, MEM }}, \
1349 {"mem_operand", { MEM }}, \
1350 {"mask_operand", { REG, CONST_INT, SUBREG }}, \
1351 {"extui_fldsz_operand", { CONST_INT }}, \
1352 {"sext_fldsz_operand", { CONST_INT }}, \
1353 {"lsbitnum_operand", { CONST_INT }}, \
1354 {"fpmem_offset_operand", { CONST_INT }}, \
1355 {"sext_operand", { REG, SUBREG, MEM }}, \
1356 {"branch_operand", { REG, CONST_INT, SUBREG }}, \
1357 {"ubranch_operand", { REG, CONST_INT, SUBREG }}, \
1358 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG }}, \
1359 {"move_operand", { REG, SUBREG, MEM, CONST_INT, CONST_DOUBLE, \
1360 CONST, SYMBOL_REF, LABEL_REF }}, \
1361 {"const_float_1_operand", { CONST_DOUBLE }}, \
1362 {"branch_operator", { EQ, NE, LT, GE }}, \
1363 {"ubranch_operator", { LTU, GEU }}, \
1364 {"boolean_operator", { EQ, NE }},
1365
1366 /* Control the assembler format that we output. */
1367
1368 /* How to refer to registers in assembler output.
1369 This sequence is indexed by compiler's hard-register-number (see above). */
1370 #define REGISTER_NAMES \
1371 { \
1372 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
1373 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
1374 "fp", "argp", "b0", \
1375 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1376 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
1377 "acc" \
1378 }
1379
1380 /* If defined, a C initializer for an array of structures containing a
1381 name and a register number. This macro defines additional names
1382 for hard registers, thus allowing the 'asm' option in declarations
1383 to refer to registers using alternate names. */
1384 #define ADDITIONAL_REGISTER_NAMES \
1385 { \
1386 { "a1", 1 + GP_REG_FIRST } \
1387 }
1388
1389 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1390 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1391
1392 /* Recognize machine-specific patterns that may appear within
1393 constants. Used for PIC-specific UNSPECs. */
1394 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
1395 do { \
1396 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
1397 { \
1398 switch (XINT ((X), 1)) \
1399 { \
1400 case UNSPEC_PLT: \
1401 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
1402 fputs ("@PLT", (STREAM)); \
1403 break; \
1404 default: \
1405 goto FAIL; \
1406 } \
1407 break; \
1408 } \
1409 else \
1410 goto FAIL; \
1411 } while (0)
1412
1413 /* Globalizing directive for a label. */
1414 #define GLOBAL_ASM_OP "\t.global\t"
1415
1416 /* Declare an uninitialized external linkage data object. */
1417 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1418 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1419
1420 /* This is how to output an element of a case-vector that is absolute. */
1421 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
1422 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
1423 LOCAL_LABEL_PREFIX, VALUE)
1424
1425 /* This is how to output an element of a case-vector that is relative.
1426 This is used for pc-relative code. */
1427 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
1428 do { \
1429 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
1430 LOCAL_LABEL_PREFIX, (VALUE), \
1431 LOCAL_LABEL_PREFIX, (REL)); \
1432 } while (0)
1433
1434 /* This is how to output an assembler line that says to advance the
1435 location counter to a multiple of 2**LOG bytes. */
1436 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
1437 do { \
1438 if ((LOG) != 0) \
1439 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
1440 } while (0)
1441
1442 /* Indicate that jump tables go in the text section. This is
1443 necessary when compiling PIC code. */
1444 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
1445
1446
1447 /* Define the strings to put out for each section in the object file. */
1448 #define TEXT_SECTION_ASM_OP "\t.text"
1449 #define DATA_SECTION_ASM_OP "\t.data"
1450 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1451
1452
1453 /* Define output to appear before the constant pool. If the function
1454 has been assigned to a specific ELF section, or if it goes into a
1455 unique section, set the name of that section to be the literal
1456 prefix. */
1457 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
1458 do { \
1459 tree fnsection; \
1460 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
1461 fnsection = DECL_SECTION_NAME (FUNDECL); \
1462 if (fnsection != NULL_TREE) \
1463 { \
1464 const char *fnsectname = TREE_STRING_POINTER (fnsection); \
1465 fprintf (FILE, "\t.begin\tliteral_prefix %s\n", \
1466 strcmp (fnsectname, ".text") ? fnsectname : ""); \
1467 } \
1468 if ((SIZE) > 0) \
1469 { \
1470 function_section (FUNDECL); \
1471 fprintf (FILE, "\t.literal_position\n"); \
1472 } \
1473 } while (0)
1474
1475
1476 /* Define code to write out the ".end literal_prefix" directive for a
1477 function in a special section. This is appended to the standard ELF
1478 code for ASM_DECLARE_FUNCTION_SIZE. */
1479 #define XTENSA_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
1480 if (DECL_SECTION_NAME (DECL) != NULL_TREE) \
1481 fprintf (FILE, "\t.end\tliteral_prefix\n")
1482
1483 /* A C statement (with or without semicolon) to output a constant in
1484 the constant pool, if it needs special treatment. */
1485 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
1486 do { \
1487 xtensa_output_literal (FILE, X, MODE, LABELNO); \
1488 goto JUMPTO; \
1489 } while (0)
1490
1491 /* How to start an assembler comment. */
1492 #define ASM_COMMENT_START "#"
1493
1494 /* Exception handling TODO!! */
1495 #define DWARF_UNWIND_INFO 0
1496
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