1 /* Testcase to check generation of a SH2A specific instruction for
2 "BXOR.B #imm3, @(disp12, Rn)". */
3 /* { dg-do compile { target { sh2a } } } */
4 /* { dg-options "-O1 -mbitops" } */
5 /* { dg-final { scan-assembler "bxor.b"} } */
34 unsigned char IOR15
:1;
35 unsigned char IOR14
:1;
36 unsigned char IOR13
:1;
37 unsigned char IOR12
:1;
38 unsigned char IOR11
:1;
39 unsigned char IOR10
:1;
58 volatile unsigned char a
;
60 /* Instruction generated is BXOR.B #imm3, @(disp12, Rn) */
61 USRSTR
.ICR0
.BIT
.BIT3
= USRSTR
.ICR0
.BIT
.BIT4
^ USRSTR
.ICR0
.BIT
.BIT1
;
62 USRSTR
.ICR0
.BIT
.BIT2
= USRSTR
.ICR0
.BIT
.BIT6
^ USRSTR
.ICR0
.BIT
.BIT6
;
63 USRSTR
.ICR0
.BIT
.BIT4
= USRSTR
.ICR0
.BIT
.BIT2
^ USRSTR
.ICR0
.BIT
.BIT4
;
64 USRSTR
.ICR0
.BIT
.BIT6
= USRSTR
.ICR0
.BIT
.BIT1
^ USRSTR
.ICR0
.BIT
.BIT3
;
66 a
= USRSTR
.ICR0
.BIT
.BIT0
^ USRSTR
.ICR0
.BIT
.BIT1
;
67 a
= USRSTR
.ICR0
.BIT
.BIT5
^ USRSTR
.ICR0
.BIT
.BIT7
;
68 a
= USRSTR
.ICR0
.BIT
.BIT2
^ USRSTR
.ICR0
.BIT
.BIT6
;
70 PORT
.BIT
.IOR13
= PORT
.BIT
.IOR0
^ USRSTR
.ICR0
.BIT
.BIT7
;
71 PORT
.BIT
.IOR15
= PORT
.BIT
.IOR6
^ USRSTR
.ICR0
.BIT
.BIT2
;
72 PORT
.BIT
.IOR3
= PORT
.BIT
.IOR2
^ USRSTR
.ICR0
.BIT
.BIT5
;
73 PORT
.BIT
.IOR1
= PORT
.BIT
.IOR13
^ USRSTR
.ICR0
.BIT
.BIT1
;
75 PORT
.BIT
.IOR1
= PORT
.BIT
.IOR2
^ USRSTR
.ICR0
.BIT
.BIT1
;
76 PORT
.BIT
.IOR11
= PORT
.BIT
.IOR9
^ USRSTR
.ICR0
.BIT
.BIT2
;
77 PORT
.BIT
.IOR8
= PORT
.BIT
.IOR14
^ USRSTR
.ICR0
.BIT
.BIT5
;
79 PORT
.BIT
.IOR10
^= USRSTR
.ICR0
.BIT
.BIT1
;
80 PORT
.BIT
.IOR1
^= USRSTR
.ICR0
.BIT
.BIT2
;
81 PORT
.BIT
.IOR5
^= USRSTR
.ICR0
.BIT
.BIT5
;
82 PORT
.BIT
.IOR14
^= USRSTR
.ICR0
.BIT
.BIT4
;
84 /* Instruction generated on using size optimization option "-Os". */
85 a
= a
^ USRSTR
.ICR0
.BIT
.BIT1
;
86 a
= a
^ USRSTR
.ICR0
.BIT
.BIT4
;
87 a
= a
^ USRSTR
.ICR0
.BIT
.BIT0
;