1 /* { dg-do compile } */
2 /* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32" } */
4 #include "riscv_vector.h"
6 /* Check vsetvl instruction is hoisted outside the loop, so it should
9 void foo2 (void * restrict in
, void * restrict out
, int n
)
11 for (int i
= 0; i
< n
; i
++)
13 vuint16mf4_t v
= *(vuint16mf4_t
*)(in
+ i
);
14 *(vuint16mf4_t
*)(out
+ i
) = v
;
18 void foo3 (void * restrict in
, void * restrict out
, int n
)
20 for (int i
= 0; i
< n
; i
++)
22 vuint16mf2_t v
= *(vuint16mf2_t
*)(in
+ i
);
23 *(vuint16mf2_t
*)(out
+ i
) = v
;
27 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
28 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
30 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
31 /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */