gcc/testsuite/gcc.target/powerpc/vec-strir-6.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-mdejagnu-cpu=power10" } */
   3
   4 #include <altivec.h>
   5
   6 extern void abort (void);
   7
   8 /* Vector string isolate right-justified on array of signed short.  */
   9 vector signed short
  10 sirj (vector signed short arg)
  11 {
  12   return vec_strir (arg);
  13 }
  14
  15 /* Enforce that a single dot-form instruction which is properly biased
  16    for the target's endianness implements this built-in.  */
  17
  18 /* { dg-final { scan-assembler-times {\mvstrihr\M} 1 { target { be } } } } */
  19 /* { dg-final { scan-assembler-times {\mvstrihl} 0 { target { be } } } } */
  20 /* { dg-final { scan-assembler-times {\mvstrihl\M} 1 { target { le } } } } */
  21 /* { dg-final { scan-assembler-times {\mvstrihr} 0 { target { le } } } } */