gcc/testsuite/gcc.target/powerpc/pr83862.c

   1 /* PR target/83862.c */
   2 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
   3 /* { dg-options "-mvsx -O2 -mabi=ieeelongdouble -Wno-psabi" } */
   4 /* { dg-additional-options "-mdejagnu-cpu=power8" { target { ! has_arch_pwr8 } } } */
   5 /* { dg-require-effective-target ppc_float128_sw } */
   6 /* { dg-require-effective-target powerpc_vsx } */
   7
   8 /* On little endian systems, optimizing signbit of IEEE 128-bit values from
   9    memory could abort if the memory address was indexed (reg+reg).  The
  10    optimization is only on 64-bit machines with direct move.
  11
  12    Compile with -g -O2 -mabi=ieeelongdouble -Wno-psabi.  */
  13
  14 #ifndef TYPE
  15 #define TYPE long double
  16 #endif
  17
  18 int sbr (TYPE a) { return __builtin_signbit (a); }
  19 int sbm (TYPE *a) { return __builtin_signbit (*a); }
  20 int sbo (TYPE *a) { return __builtin_signbit (a[4]); }
  21 int sbi (TYPE *a, unsigned long n) { return __builtin_signbit (a[n]); }
  22 void sbs (int *p, TYPE a) { *p = __builtin_signbit (a); }
  23
  24 /* On big endian systems, this will generate 2 LDs and 1 LDX, while on
  25    little endian systems, this will generate 3 LDs and an ADD.  */
  26
  27 /* { dg-final { scan-assembler-times {\mldx?\M}    3 } } */
  28 /* { dg-final { scan-assembler-times {\mmfvsrd\M}  2 } } */
  29 /* { dg-final { scan-assembler-times {\msrdi\M}    5 } } */
  30 /* { dg-final { scan-assembler-not   {\mmfvsrld\M}   } } */
  31 /* { dg-final { scan-assembler-not   {\mstxvx?\M}    } } */
  32 /* { dg-final { scan-assembler-not   {\mstxvw4x\M}   } } */
  33 /* { dg-final { scan-assembler-not   {\mstxvd2x\M}   } } */
  34 /* { dg-final { scan-assembler-not   {\mstvx\M}      } } */
  35