gcc/testsuite/gcc.target/powerpc/mul-vectorize-1.c

   1 /* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
   2 /* { dg-require-effective-target powerpc_vsx } */
   3
   4 /* Test vectorizer can exploit ISA 2.07 instruction vmuluwm (Vector Multiply
   5    Unsigned Word Modulo) for both signed and unsigned word multiplication.  */
   6
   7 #define N 128
   8
   9 extern signed int si_a[N], si_b[N], si_c[N];
  10 extern unsigned int ui_a[N], ui_b[N], ui_c[N];
  11
  12 __attribute__ ((noipa)) void
  13 test_si ()
  14 {
  15   for (int i = 0; i < N; i++)
  16     si_c[i] = si_a[i] * si_b[i];
  17 }
  18
  19 __attribute__ ((noipa)) void
  20 test_ui ()
  21 {
  22   for (int i = 0; i < N; i++)
  23     ui_c[i] = ui_a[i] * ui_b[i];
  24 }
  25
  26 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
  27 /* { dg-final { scan-assembler-times {\mvmuluwm\M} 2 } } */