gcc/testsuite/gcc.target/powerpc/fold-vec-insert-short-p9.c

   1 /* Verify that overloaded built-ins for vec_insert() with short
   2    inputs produce the right codegen.  Power9 variant.  */
   3
   4 /* { dg-do compile } */
   5 /* { dg-options "-O2 -mdejagnu-cpu=power9 -mvsx" } */
   6 /* { dg-require-effective-target powerpc_vsx } */
   7
   8 #include <altivec.h>
   9
  10 vector bool short
  11 testbs_var(unsigned short x, vector bool short v, signed int i)
  12 {
  13    return vec_insert(x, v, i);
  14 }
  15 vector signed short
  16 testss_var(signed short x, vector signed short v, signed int i)
  17 {
  18    return vec_insert(x, v, i);
  19 }
  20 vector unsigned short
  21 testus1_var(signed short x, vector unsigned short v, signed int i)
  22 {
  23    return vec_insert(x, v, i);
  24 }
  25 vector unsigned short
  26 testus2_var(unsigned short x, vector unsigned short v, signed int i)
  27 {
  28    return vec_insert(x, v, i);
  29 }
  30 vector bool short
  31 testbs_cst(signed short x, vector bool short v)
  32 {
  33    return vec_insert(x, v, 12);
  34 }
  35 vector signed short
  36 testss_cst(signed short x, vector signed short v)
  37 {
  38    return vec_insert(x, v, 12);
  39 }
  40 vector unsigned short
  41 testus1_cst(signed short x, vector unsigned short v)
  42 {
  43    return vec_insert(x, v, 12);
  44 }
  45 vector unsigned short
  46 testus2_cst(unsigned short x, vector unsigned short v)
  47 {
  48    return vec_insert(x, v, 12);
  49 }
  50
  51 /* { dg-final { scan-assembler-times {\mmtvsrwz\M} 8 { target lp64 } } } */
  52 /* { dg-final { scan-assembler-times {\mvinserth\M} 8 { target lp64 } } } */
  53
  54 /* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target lp64 } } } */
  55 /* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 0 { target lp64 }} } */
  56
  57 /* -m32 uses sth/lvehx as part of the sequence. */
  58 /* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 0 { target ilp32 } } } */
  59 /* { dg-final { scan-assembler-times {\msth\M} 4 { target ilp32 } } } */
  60 /* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 } } } */
  61 /* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
  62 /* { dg-final { scan-assembler-times {\mxxperm\M} 8 { target ilp32 } } } */
  63 /* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 } } } */
  64