gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c

   1 /* Verify that overloaded built-ins for vec_extract() with short
   2    inputs produce the right results with a P8 (LE or BE) target.  */
   3
   4 /* { dg-do compile } */
   5 /* { dg-options "-mdejagnu-cpu=power8 -mvsx -O2" } */
   6 /* { dg-require-effective-target powerpc_vsx } */
   7
   8 // six tests total. Targeting P8, both LE and BE.
   9 // p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh/2:rlwinm)
  10 // p8 (le) const offset:                          mtvsrd,                                (1:extsh/2:rlwinm)
  11 // p8 (be) var offset:                      sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh:2:rlwinm)
  12 // p8 (be) const offset:    vsplth,               mfvsrd,                                (1:extsh/2:rlwinm)
  13
  14 // * - each of the above will have an extsh if the argument is signed.
  15 // * - bool and unsigned tests also have an rlwinm.
  16
  17 /* { dg-final { scan-assembler-times "rldicl" 3 {target { lp64 && le } } } } */
  18 /* { dg-final { scan-assembler-times "subfic" 3 {target { lp64 && le } } } } */
  19 /* { dg-final { scan-assembler-times "vsplth" 3 { target { lp64 && be } } } } */
  20 /* { dg-final { scan-assembler-times "sldi" 3 { target lp64 } } } */
  21 /* { dg-final { scan-assembler-times "mtvsrd" 3 { target lp64 } } } */
  22 /* { dg-final { scan-assembler-times "xxpermdi" 3 { target lp64 } } } */
  23 /* { dg-final { scan-assembler-times "vslo" 3 { target lp64 } } } */
  24 /* { dg-final { scan-assembler-times "mfvsrd" 6 { target lp64 } } } */
  25 /* { dg-final { scan-assembler-times "srdi" 3 { target lp64 } } } */
  26 /* { dg-final { scan-assembler-times "extsh" 2 { target lp64 } } } */
  27 /* { dg-final { scan-assembler-times "rlwinm" 4 { target lp64 } } } */
  28
  29 /* -m32 codegen tests. */
  30 /* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
  31 /* { dg-final { scan-assembler-times "stxvw4x" 6 { target ilp32 } } } */
  32 /* add and rlwinm instructions only on the variable tests. */
  33 /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
  34 /* { dg-final { scan-assembler-times {\maddi?\M} 9 { target ilp32 } } } */
  35 /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
  36
  37
  38 #include <altivec.h>
  39
  40 unsigned short
  41 testbi_cst (vector bool short vbs2)
  42 {
  43   return vec_extract (vbs2, 12);
  44 }
  45
  46 signed short
  47 testsi_cst (vector signed short vss2)
  48 {
  49   return vec_extract (vss2, 12);
  50 }
  51
  52 unsigned short
  53 testui_cst12 (vector unsigned short vus2)
  54 {
  55   return vec_extract (vus2, 12);
  56 }
  57
  58 unsigned short
  59 testbi_var (vector bool short vbs2, signed int si)
  60 {
  61   return vec_extract (vbs2, si);
  62 }
  63
  64 signed short
  65 testsi_var (vector signed short vss2, signed int si)
  66 {
  67 return vec_extract (vss2, si);
  68 }
  69
  70 unsigned short
  71 testui_var (vector unsigned short vus2, signed int si)
  72 {
  73 return vec_extract (vus2, si);
  74 }
  75