[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64
[official-gcc.git] / gcc / testsuite / gcc.target / powerpc / bool3-p7.c
blob11ae87cadb8122edc99011bf3e918e1f021cd0ce
1 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
2 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
3 /* { dg-options "-O2 -mdejagnu-cpu=power7" } */
4 /* { dg-require-effective-target powerpc_vsx } */
5 /* { dg-final { scan-assembler "\[ \t\]and " } } */
6 /* { dg-final { scan-assembler "\[ \t\]or " } } */
7 /* { dg-final { scan-assembler "\[ \t\]xor " } } */
8 /* { dg-final { scan-assembler "\[ \t\]nor " } } */
9 /* { dg-final { scan-assembler "\[ \t\]andc " } } */
10 /* { dg-final { scan-assembler-not "\[ \t\]vand " } } */
11 /* { dg-final { scan-assembler-not "\[ \t\]vandc " } } */
12 /* { dg-final { scan-assembler-not "\[ \t\]vor " } } */
13 /* { dg-final { scan-assembler-not "\[ \t\]vxor " } } */
14 /* { dg-final { scan-assembler-not "\[ \t\]vnor " } } */
15 /* { dg-final { scan-assembler-not "\[ \t\]xxland " } } */
16 /* { dg-final { scan-assembler-not "\[ \t\]xxlor " } } */
17 /* { dg-final { scan-assembler-not "\[ \t\]xxlxor " } } */
18 /* { dg-final { scan-assembler-not "\[ \t\]xxlnor " } } */
19 /* { dg-final { scan-assembler-not "\[ \t\]xxlandc " } } */
20 /* { dg-final { scan-assembler-not "\[ \t\]xxleqv " } } */
21 /* { dg-final { scan-assembler-not "\[ \t\]xxlorc " } } */
22 /* { dg-final { scan-assembler-not "\[ \t\]xxlnand " } } */
24 /* On power7, for 128-bit types, ORC/ANDC/EQV might not show up, since the
25 vector unit doesn't support these, so the appropriate combine patterns may
26 not be generated. */
28 #ifndef TYPE
29 #ifdef _ARCH_PPC64
30 #define TYPE __int128_t
31 #else
32 typedef int v4si __attribute__ ((vector_size (16)));
33 #define TYPE v4si
34 #endif
35 #endif
37 #include "bool3.h"