RISC-V: testsuite: Fix SELECT_VL SLP fallout.
[official-gcc.git] / gcc / testsuite / gcc.target / arm / neon-compare-4.c
blob3f8cc906c6699b00d94fb0f574fc85f221576b26
1 /* { dg-do compile } */
2 /* { dg-require-effective-target arm_neon_ok } */
3 /* { dg-options "-O1 -ftree-vectorize -funsafe-math-optimizations" } */
4 /* { dg-add-options arm_neon } */
6 #define ordered(a, b) (!__builtin_isunordered (a, b))
7 #define unordered(a, b) (__builtin_isunordered (a, b))
9 int x[16];
10 float a[16];
11 float b[16];
13 #define COMPARE(NAME) \
14 void \
15 cmp_##NAME##_reg (void) \
16 { \
17 for (int i = 0; i < 16; ++i) \
18 x[i] = NAME (a[i], b[i]) ? 2 : 0; \
19 } \
21 void \
22 cmp_##NAME##_zero (void) \
23 { \
24 for (int i = 0; i < 16; ++i) \
25 x[i] = NAME (a[i], 0) ? 2 : 0; \
28 typedef int int_vec __attribute__((vector_size(16)));
29 typedef float vec __attribute__((vector_size(16)));
31 COMPARE (ordered)
32 COMPARE (unordered)
34 /* { dg-final { scan-assembler-times {\tvcgt.f32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
35 /* { dg-final { scan-assembler-times {\tvcgt.f32\tq[0-9]+, q[0-9]+, #0\n} 2 } } */
37 /* { dg-final { scan-assembler-times {\tvcge.f32\tq[0-9]+, q[0-9]+, q[0-9]+\n} 2 } } */
38 /* { dg-final { scan-assembler-times {\tvcle.f32\tq[0-9]+, q[0-9]+, #0\n} 2 } } */