2 /* { dg-require-effective-target arm_mve_hw } */
3 /* { dg-options "-O2" } */
4 /* { dg-add-options arm_v8_1m_mve } */
9 volatile uint32x4_t c2
;
15 int32x4_t a1
= vcreateq_s32 (0, 0);
16 int32x4_t b1
= vcreateq_s32 (0, 0);
17 int32x4_t inactive1
= vcreateq_s32 (0, 0);
19 uint32x4_t a2
= vcreateq_u32 (0, 0);
20 uint32x4_t b2
= vcreateq_u32 (0, 0);
21 uint32x4_t inactive2
= vcreateq_u32 (0, 0);
23 mve_pred16_t p
= 0xFFFF;
26 __builtin_arm_set_fpscr_nzcvqc (0);
27 c1
= vadcq (a1
, b1
, &carry
);
28 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
31 __builtin_arm_set_fpscr_nzcvqc (0);
32 c2
= vadcq (a2
, b2
, &carry
);
33 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
36 __builtin_arm_set_fpscr_nzcvqc (0);
37 c1
= vsbcq (a1
, b1
, &carry
);
38 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
41 __builtin_arm_set_fpscr_nzcvqc (0);
42 c2
= vsbcq (a2
, b2
, &carry
);
43 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
46 __builtin_arm_set_fpscr_nzcvqc (0);
47 c1
= vadcq_m (inactive1
, a1
, b1
, &carry
, p
);
48 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
51 __builtin_arm_set_fpscr_nzcvqc (0);
52 c2
= vadcq_m (inactive2
, a2
, b2
, &carry
, p
);
53 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
56 __builtin_arm_set_fpscr_nzcvqc (0);
57 c1
= vsbcq_m (inactive1
, a1
, b1
, &carry
, p
);
58 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)
61 __builtin_arm_set_fpscr_nzcvqc (0);
62 c2
= vsbcq_m (inactive2
, a2
, b2
, &carry
, p
);
63 if (__builtin_arm_get_fpscr_nzcvqc () & !0x20000000)