RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]
[official-gcc.git] / gcc / testsuite / gcc.target / arc / firq-2.c
blobdc7dafca11a3c72d64710aed2abe50922c8588d9
1 /* { dg-do compile } */
2 /* { dg-require-effective-target archs }*/
3 /* { dg-options "-O0 -mll64 -mirq-ctrl-saved=r0-r9 -mrgf-banked-regs=4" } */
5 /* Check that on archs the 'firq' interrupt function type is
6 available, these are the fast interrupts. For fast interrupts,
7 despite the use of 'irq-ctrl-saved', no registers are automatically
8 saved on stack on entry to the function. However, the cpu save via
9 bank switch R0-R3.
11 We also take the opportunity to check the use of the 'rtie' instruction
12 at the end of the interrupt function. */
14 void __attribute__ ((interrupt("firq")))
15 handler1 (void)
17 asm (""
20 : "r0", "r1", "r2", "r3", "r4",
21 "r5", "r6", "r7", "r8", "r9");
23 /* { dg-final { scan-assembler-not "r0,\\\[sp" } } */
24 /* { dg-final { scan-assembler-not "push.*r0" } } */
25 /* { dg-final { scan-assembler-not "r1,\\\[sp" } } */
26 /* { dg-final { scan-assembler-not "r2,\\\[sp" } } */
27 /* { dg-final { scan-assembler-not "r3,\\\[sp" } } */
28 /* { dg-final { scan-assembler "st.*r4,\\\[sp" } } */
29 /* { dg-final { scan-assembler "st.*r6,\\\[sp,\[0-9\]+\\\]" } } */
30 /* { dg-final { scan-assembler "st.*r8,\\\[sp,\[0-9\]+\\\]" } } */
31 /* { dg-final { scan-assembler "rtie" } } */