RISC-V: Add testcases for unsigned .SAT_SUB vector form 10
[official-gcc.git] / gcc / testsuite / gcc.target / aarch64 / simd / extq_p16_1.c
blobfbe27dd2b26da9b663fb7e6271db94ebdcf12e3a
1 /* Test the `vextQp16' AArch64 SIMD intrinsic. */
3 /* { dg-do run } */
4 /* { dg-options "-save-temps -O3 -fno-inline" } */
6 #include "arm_neon.h"
7 #include "extq_p16.x"
9 /* { dg-final { scan-assembler-times "ext\[ \t\]+\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?\[vV\]\[0-9\]+\.16\[bB\], ?#\[0-9\]+\(?:.2\)?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 7 } } */