gcc/testsuite/gcc.target/aarch64/fmul_intrinsic_1.c

   1 /* { dg-do run } */
   2 /* { dg-options "-O3 --save-temps" } */
   3
   4 #include <arm_neon.h>
   5
   6 #define DELTA 0.0001
   7 extern void abort (void);
   8 extern double fabs (double);
   9
  10 #define TEST_VMUL(q1, q2, size, in1_lanes, in2_lanes)                   \
  11 static void                                                             \
  12 __attribute__((noipa,noinline))                                         \
  13 test_vmul##q1##_lane##q2##_f##size (float##size##_t * res,              \
  14                                    const float##size##_t *in1,          \
  15                                    const float##size##_t *in2)          \
  16 {                                                                       \
  17   float##size##x##in1_lanes##_t a = vld1##q1##_f##size (res);           \
  18   float##size##x##in1_lanes##_t b = vld1##q1##_f##size (in1);           \
  19   float##size##x##in2_lanes##_t c;                                      \
  20   if (in2_lanes > 1)                                                    \
  21     {                                                                   \
  22       c = vld1##q2##_f##size (in2);                                     \
  23       a = vmul##q1##_lane##q2##_f##size (b, c, 1);                      \
  24     }                                                                   \
  25   else                                                                  \
  26     {                                                                   \
  27       c = vld1##q2##_f##size (in2 + 1);                                 \
  28       a = vmul##q1##_lane##q2##_f##size (b, c, 0);                      \
  29     }                                                                   \
  30   vst1##q1##_f##size (res, a);                                          \
  31 }
  32
  33 #define BUILD_VARS(width, n_lanes, n_half_lanes)                \
  34 TEST_VMUL ( ,  , width, n_half_lanes, n_half_lanes)             \
  35 TEST_VMUL (q,  , width, n_lanes, n_half_lanes)                  \
  36 TEST_VMUL ( , q, width, n_half_lanes, n_lanes)                  \
  37 TEST_VMUL (q, q, width, n_lanes, n_lanes)
  38
  39 BUILD_VARS (32, 4, 2)
  40 BUILD_VARS (64, 2, 1)
  41
  42 #define POOL2 {0.0, 1.0}
  43 #define POOL4 {0.0, 1.0, 2.0, 3.0}
  44 #define EMPTY2 {0.0, 0.0}
  45 #define EMPTY4 {0.0, 0.0, 0.0, 0.0}
  46
  47 #define BUILD_TEST(size, lanes)                                 \
  48 static void                                                     \
  49 test_f##size (void)                                             \
  50 {                                                               \
  51   int i;                                                        \
  52   float##size##_t pool[lanes] = POOL##lanes;                    \
  53   float##size##_t res[lanes] = EMPTY##lanes;                    \
  54   float##size##_t res2[lanes] = EMPTY##lanes;                   \
  55   float##size##_t res3[lanes] = EMPTY##lanes;                   \
  56   float##size##_t res4[lanes] = EMPTY##lanes;                   \
  57                                                                 \
  58   /* Avoid constant folding the multiplication.  */             \
  59   asm volatile ("" : : : "memory");                             \
  60   test_vmul_lane_f##size (res, pool, pool);                     \
  61   /* Avoid fusing multiplication and subtraction.  */           \
  62   asm volatile ("" : :"Q" (res) : "memory");                    \
  63   for (i = 0; i < lanes / 2; i++)                               \
  64     if (fabs (res[i] - pool[i]) > DELTA)                        \
  65       abort ();                                                 \
  66                                                                 \
  67   test_vmulq_lane_f##size (res2, pool, pool);                   \
  68   /* Avoid fusing multiplication and subtraction.  */           \
  69   asm volatile ("" : :"Q" (res2) : "memory");                   \
  70   for (i = 0; i < lanes; i++)                                   \
  71     if (fabs (res2[i] - pool[i]) > DELTA)                       \
  72       abort ();                                                 \
  73                                                                 \
  74   test_vmul_laneq_f##size (res3, pool, pool);                   \
  75   /* Avoid fusing multiplication and subtraction.  */           \
  76   asm volatile ("" : :"Q" (res3) : "memory");                   \
  77   for (i = 0; i < lanes / 2; i++)                               \
  78     if (fabs (res3[i] - pool[i]) > DELTA)                       \
  79       abort ();                                                 \
  80                                                                 \
  81   test_vmulq_laneq_f##size (res4, pool, pool);                  \
  82   /* Avoid fusing multiplication and subtraction.  */           \
  83   asm volatile ("" : :"Q" (res4) : "memory");                   \
  84   for (i = 0; i < lanes; i++)                                   \
  85     if (fabs (res4[i] - pool[i]) > DELTA)                       \
  86       abort ();                                                 \
  87 }
  88
  89 BUILD_TEST (32, 4)
  90 BUILD_TEST (64, 2)
  91
  92 int
  93 main (int argc, char **argv)
  94 {
  95   test_f32 ();
  96   test_f64 ();
  97   return 0;
  98 }
  99
 100 /* vmul_laneq_f32.
 101    vmul_lane_f32.  */
 102 /* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 103
 104 /* vmulq_lane_f32.
 105    vmulq_laneq_f32.  */
 106 /* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
 107
 108 /* vmul_lane_f64.
 109    Vmul_laneq_f64. */
 110 /* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 { target aarch64_big_endian } } } */
 111 /* { dg-final { scan-assembler-times "fmul\\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 2 { target aarch64_little_endian } } } */
 112
 113 /* vmulq_lane_f64.
 114    vmulq_laneq_f64.  */
 115 /* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 { target aarch64_big_endian } } } */
 116 /* { dg-final { scan-assembler-times "fmul\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 2 { target aarch64_little_endian } } } */
 117
 118